PCA9632
2
4-bit Fm+ I C-bus low power LED driver
Rev. 6 — 21 September 2021
1
Product data sheet
General description
2
The PCA9632 is an I C-bus controlled 4-bit LED driver optimized for Red/Green/Blue/
Amber (RGBA) color mixing applications. The PCA9632 is a drop-in upgrade for the
PCA9633 with 40× power reduction. In Individual brightness control mode, each LED
output has its own 8-bit resolution (256 steps) fixed frequency Individual PWM controller
that operates at 1.5625 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to
allow the LED to be set to a specific brightness value. In group dimming mode, each LED
output has its own 6-bit resolution (64 steps) fixed frequency Individual PWM controller
that operates at 6.25 kHz with a duty cycle that is adjustable from 0 % to 98.4 % to allow
the LED to be set to a specific brightness value. A fifth 4-bit resolution (16 steps) Group
PWM controller has a fixed frequency of 190 Hz that is used to dim all the LEDs with the
same value.
While operating in the Blink mode, each LED output has its own 8-bit resolution (256
steps) fixed frequency Individual PWM controller that operates at 1.5625 kHz with a
duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set to a specific
brightness value. Blink rate is controlled by the Group frequency setting that has 8-bit
resolution (256 steps). The blink rate is adjustable between 24 Hz and once every 10.73
seconds. For Group frequency settings between 6 Hz and 24 Hz, the Group PWM has
a 6-bit resolution (64 steps) with a duty cycle that is adjustable from 0 % to 98.4 %. For
Group frequency settings between 6 Hz and 0.09 Hz (once in 10.73 seconds), the Group
PWM has an 8-bit resolution (256 steps) with a duty cycle that is adjustable from 0 % to
99.6 %.
Each LED output can be off, on (no PWM control), set at its Individual PWM controller
value or at both Individual and Group PWM controller values. The LED output driver is
programmed to be either open-drain with a 25 mA current sink capability at 5 V or totem
pole with a 25 mA sink, 10 mA source capability at 5 V. The PCA9632 operates with a
supply voltage range of 2.3 V to 5.5 V and the outputs are 5.5 V tolerant. LEDs can be
directly connected to the LED output (up to 25 mA, 5.5 V) or controlled with external
drivers and a minimum amount of discrete components for larger current or higher
voltage LEDs.
The PCA9632 is in the new Fast-mode Plus (Fm+) family. Fm+ devices offer higher
frequency (up to 1 MHz) and more densely populated bus operation (up to 4000 pF).
2
Software programmable LED Group and three Sub Call I C-bus addresses allow all or
2
defined groups of PCA9632 devices to respond to a common I C-bus address, allowing,
for example, all red LEDs to be turned on or off at the same time or marquee chasing
2
effect, thus minimizing I C-bus commands.
The Software Reset (SWRST) Call allows the controller to perform a reset of the
2
PCA9632 through the I C-bus, identical to the Power-On Reset (POR) that initializes the
registers to their default state causing the outputs to be set high-impedance. This allows
an easy and quick way to reconfigure all device registers to the same condition.
NXP Semiconductors
2
PCA9632
4-bit Fm+ I C-bus low power LED driver
2
Features and benefits
• 40× power reduction compared to PCA9633
• 4 LED drivers. Each output programmable at:
– Off
– On
– Programmable LED brightness
– Programmable group dimming/blinking mixed with individual LED brightness
2
• 1 MHz Fast-mode Plus I C-bus interface with 30 mA high drive capability on SDA
output for driving high capacitive buses
• 256-step (8-bit) linear programmable brightness per LED output varying from fully
off (default) to maximum brightness using a 1.5625 kHz PWM signal in Individual
brightness mode
• 64-step (6-bit) linear programmable brightness for each LED output varying from fully
off (default) to maximum brightness using a 6.25 kHz PWM signal in group dimming
mode
• In group dimming mode, 16-step group brightness control allows global dimming (using
a 190 Hz PWM signal) from fully off to maximum brightness (default)
• 256-step (8-bit) linear programmable brightness per LED output varying from fully off
(default) to maximum brightness using a 1.5625 kHz PWM signal in group blinking
mode
• 64-step group blinking with frequency programmable from 24 Hz to 6 Hz and duty cycle
from 0 % to 98.4 %
• 256-step group blinking with frequency programmable from 6 Hz to 0.09 Hz (10.73 s)
and duty cycle from 0 % to 99.6 %
• Four totem pole outputs (sink 25 mA and source 10 mA at 5 V) with software
programmable open-drain LED outputs selection (default at high-impedance). No input
function.
• 10-pin package option provides two hardware address pins allowing four devices to
operate on the same bus
• Output state change programmable on the Acknowledge or the STOP Command to
update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).
2
• Software Reset feature (SWRST Call) allows the device to be reset through the I C-bus
• 400 kHz internal oscillator requires no external components
• Internal power-on reset
• Noise filter on SDA/SCL inputs
• Edge rate control on outputs
• No glitch on power-up
• Supports hot insertion
• Low standby current of < 1 μA
• Operating power supply voltage range of 2.3 V to 5.5 V
• 5.5 V tolerant inputs
• -40 °C to +85 °C operation
• ESD protection exceeds 5000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Packages offered: TSSOP8, TSSOP10, HVSON8
PCA9632
Product data sheet
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Rev. 6 — 21 September 2021
© NXP B.V. 2021. All rights reserved.
2 / 37
PCA9632
NXP Semiconductors
2
4-bit Fm+ I C-bus low power LED driver
3
Applications
•
•
•
•
•
4
RGB or RGBA LED drivers for color mixing
LED status information
LED displays
LCD backlights
Keypad backlights for cellular phones or handheld devices
Ordering information
Table 1. Ordering information
Type number
Topside
mark
Package
Name
Description
Version
PCA9632DP1
9632
TSSOP8
plastic thin shrink small outline package; 8 leads; body width 3
mm with 0.65 mm pitch.
SOT505-1
PCA9632DP2
9632
TSSOP10
plastic thin shrink small outline package; 10 leads; body width
3 mm with 0.5 mm pitch.
SOT552-1
PCA9632TK
9632
HVSON8
plastic thermal enhanced very thin small outline package; no
leads; 8 terminals; body 3 × 3 × 0.85 mm with 0.5 mm pitch.
SOT908-1
4.1 Ordering options
Table 2. Ordering options
[1]
Type number
Orderable part
number
Package
Packing method
PCA9632DP1
PCA9632DP1,
118
SOT505-1
Reel 13" Q1 NDP
PCA9632DP2
PCA9632DP2Z
SOT552-1
PCA9632DP2
PCA9632DP2,
[3]
118
PCA9632TK
PCA9632TK, 118
[1]
[2]
[3]
Minimum order
quantity
Temperature range
2500
–40 °C to +85 °C
Reel 13" Q1 NDP SSB
2500
–40 °C to +85 °C
SOT552-1
Reel 13" Q1 NDP
2500
–40 °C to +85 °C
SOT908-1
Reel 13" Q1 NDP
6000
–40 °C to +85 °C
[2]
Standard packing quantities and other packaging data are available at www.nxp.com/packages/
This packing method uses a Static Shielding Bag (SSB) solution. Material should be kept in the sealed bag between uses.
Discontinued Notice 202104010DN - PCA9632DP2Z is drop in replacement in accordance with PCN 202104008A
PCA9632
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 21 September 2021
© NXP B.V. 2021. All rights reserved.
3 / 37
NXP Semiconductors
2
PCA9632
4-bit Fm+ I C-bus low power LED driver
5
Block diagram
10-pin version
A0
A1
PCA9632
SCL
INPUT FILTER
SDA
I2C-BUS
CONTROL
POWER-ON
RESET
VDD
VDD
VSS
LED
STATE
SELECT
REGISTER
PWM
REGISTER X
BRIGHTNESS
CONTROL
6.25 kHz/
1.56 kHz
400 kHz
OSCILLATOR
LEDn
GRPFREQ
REGISTER
190 Hz
24 Hz
to
0.09 Hz
GRPPWM
REGISTER
MUX/
CONTROL
'0' - permanently OFF
'1' - permanently ON
002aad039
Figure 1. Block diagram of PCA9632
PCA9632
Product data sheet
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4 / 37
PCA9632
NXP Semiconductors
2
4-bit Fm+ I C-bus low power LED driver
6
Pinning information
6.1 Pinning
LED0
1
LED1
2
LED2
3
LED3
4
PCA9632DP1
8
VDD
7
SDA
6
SCL
5
VSS
LED0
1
LED1
2
LED2
3
LED3
A0
10 VDD
9
SDA
8
SCL
4
7
A1
5
6
VSS
PCA9632DP2
002aad637
002aad040
Figure 2. Pin configuration for TSSOP8
Figure 3. Pin configuration for TSSOP10
terminal 1
index area
LED0
1
LED1
2
LED2
3
LED3
4
PCA9632TK
8
VDD
7
SDA
6
SCL
5
VSS
002aad041
Transparent top view
Figure 4. Pin configuration for HVSON8
6.2 Pin description
Table 3. Pin description for TSSOP8 and HVSON8
Symbol
Pin
Type
Description
LED0
1
O
LED driver 0
LED1
2
O
LED driver 1
LED2
3
O
LED driver 2
LED3
4
O
LED driver 3
power supply
supply ground
VSS
5
SCL
6
I
serial clock line
SDA
7
I/O
serial data line
VDD
8
power supply
supply voltage
[1]
PCA9632
Product data sheet
[1]
HVSON8 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be
connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance,
the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat
conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region.
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 21 September 2021
© NXP B.V. 2021. All rights reserved.
5 / 37
NXP Semiconductors
2
PCA9632
4-bit Fm+ I C-bus low power LED driver
Table 4. Pin description for TSSOP10
7
Symbol
Pin
Type
Description
LED0
1
O
LED driver 0
LED1
2
O
LED driver 1
LED2
3
O
LED driver 2
LED3
4
O
LED driver 3
A0
5
I
address input 0
VSS
6
power supply
supply ground
A1
7
I
address input 1
SCL
8
I
serial clock line
SDA
9
I/O
serial data line
VDD
10
power supply
supply voltage
Functional description
Refer to Figure 1.
7.1 Device addresses
Following a START condition, the bus controller must output the address of the target it is
accessing.
There are a maximum of 4 possible programmable addresses using the 2 hardware
address pins for the 10-pin version and just one fixed address for the 8-pin version.
2
7.1.1 Regular I C-bus target address
2
The I C-bus target address of the PCA9632 is shown in Figure 5. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW (10-pin versions only).
2
Remark: Using reserved I C-bus addresses will interfere with other devices, but only if
2
the devices are on the bus and/or the bus will be open to other I C-bus systems at some
later date. In a closed system where the designer controls the address assignment these
addresses can be used since the PCA9632 treats them like any other address. The LED
All Call, Software Reset and PCA9564 or PCA9665 target address (if on the bus) can
never be used for individual device addresses.
• PCA9632 LED All Call address (1110 000) or Software Reset (0000 0110) which are
active on start-up
• PCA9564 (0000 000) or PCA9665 (1110 000) target address which is active on start-up
2
• ‘reserved for future use’ I C-bus addresses (0000 011, 1111 1XX)
• target devices that use the 10-bit addressing scheme (1111 0XX)
• target devices that are designed to respond to the General Call address (0000 000)
• High-speed mode (Hs-mode) controller code (0000 1XX)
PCA9632
Product data sheet
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Rev. 6 — 21 September 2021
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6 / 37
PCA9632
NXP Semiconductors
2
4-bit Fm+ I C-bus low power LED driver
target address
target address
1
1
0
0
0
fixed
1
1
0
R/W
1
0
fixed
0
0
A1
hardware
selectable
002aab295
002aab318
a. 8-pin version
A0 R/W
b. 10-pin version
Figure 5. Target address
The last bit of the address byte defines the operation to be performed. When set to logic
1 a read is selected, while a logic 0 selects a write operation.
2
7.1.2 LED All Call I C-bus address
• Default power-up value (ALLCALLADR register): E0h or 1110 000
2
• Programmable through I C-bus (volatile programming)
2
• At power-up, LED All Call I C-bus address is enabled. PCA9632 sends an ACK when
E0h (R/W = 0) or E1h (R/W = 1) is sent by the controller.
See Section 7.3.8 "LED All Call I2C-bus address, ALLCALLADR" for more detail.
2
Remark: The default LED All Call I C-bus address (E0h or 1110 000) must not be used
2
as a regular I C-bus target address since this address is enabled at power-up. All the
2
2
PCA9632s on the I C-bus will acknowledge the address if sent by the I C-bus controller.
2
7.1.3 LED Sub Call I C-bus addresses
2
• 3 different I C-bus addresses can be used
• Default power-up values:
– SUBADR1 register: E2h or 1110 001
– SUBADR2 register: E4h or 1110 010
– SUBADR3 register: E8h or 1110 100
2
• Programmable through I C-bus (volatile programming)
2
• At power-up, Sub Call I C-bus addresses are disabled. PCA9632 does not send an
ACK when E2h (R/W = 0) or E3h (R/W = 1), E4h (R/W = 0) or E5h (R/W = 1), or E8h
(R/W = 0) or E9h (R/W = 1) is sent by the controller.
See Section 7.3.7 "I2C-bus subaddress 1 to 3, SUBADRx" for more detail.
2
2
Remark: The default LED Sub Call I C-bus addresses may be used as regular I C-bus
target addresses as long as they are disabled.
2
7.1.4 Software reset I C-bus address
The address shown in Figure 6 is used when a reset of the PCA9632 needs to be
performed by the controller. The Software Reset address (SWRST Call) must be
used with R/W = 0. If R/W = 1, the PCA9632 does not acknowledge the SWRST. See
Section 7.5 "Software reset" for more detail.
PCA9632
Product data sheet
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Rev. 6 — 21 September 2021
© NXP B.V. 2021. All rights reserved.
7 / 37
PCA9632
NXP Semiconductors
2
4-bit Fm+ I C-bus low power LED driver
R/W
0
0
0
0
0
1
1
0
002aab416
Figure 6. Software reset address
2
Remark: The Software Reset I C-bus address is a reserved address and cannot be used
2
as a regular I C-bus target address or as an LED All Call or LED Sub Call address.
7.2 Control register
Following the successful acknowledgment of the target address, LED All Call address or
LED Sub Call address, the bus controller will send a byte to the PCA9632, which will be
stored in the Control register.
The lowest 4 bits are used as a pointer to determine which register will be accessed
(D[3:0]). The highest 3 bits are used as Auto-Increment flag and Auto-Increment options
(AI[2:0]). Bit 4 is unused and must be programmed with zero (0) for proper device
operation.
register address
AI2 AI1 AI0
0
D3
D2
Auto-Increment options
Auto-Increment flag
D1
D0
002aab296
reset state = 80h
2
Remark: The Control register does not apply to the Software Reset I C-bus address.
Figure 7. Control register
When the Auto-Increment flag is set (AI2 = 1), the four low order bits of the Control
register are automatically incremented after a read or write. This allows the user to
program the registers sequentially. Four different types of Auto-Increment are possible,
depending on AI1 and AI0 values.
Table 5. Auto-Increment options
AI2
AI1
AI0
Function
0
0
0
no Auto-Increment
1
0
0
Auto-Increment for all registers. D3, D2, D1, D0 roll over to ‘0000’ after
the last register (1100) is accessed.
1
0
1
Auto-Increment for Individual brightness registers only. D3, D2, D1, D0
roll over to ‘0010’ after the last register (0101) is accessed.
1
1
0
Auto-Increment for global control registers only. D3, D2, D1, D0 roll over
to ‘0110’ after the last register (0111) is accessed.
1
1
1
Auto-Increment for individual and global control registers only. D3, D2,
D1, D0 roll over to ‘0010’ after the last register (0111) is accessed.
Remark: Other combinations not shown in Table 5 (AI[2:0] = 001, 010, and 011) are
reserved and must not be used for proper device operation.
AI[2:0] = 000 is used when the same register must be accessed several times during
2
a single I C-bus communication, for example, changes the brightness of a single LED.
Data is overwritten each time the register is accessed during a write operation.
PCA9632
Product data sheet
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PCA9632
NXP Semiconductors
2
4-bit Fm+ I C-bus low power LED driver
AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example,
power-up programming.
AI[2:0] = 101 is used when the four LED drivers must be individually programmed with
2
different values during the same I C-bus communication, for example, changing color
setting to another color setting.
AI[2:0] = 110 is used when the LED drivers must be globally programmed with different
2
settings during the same I C-bus communication, for example, global brightness or
blinking change.
AI[2:0] = 111 is used when individual and global changes must be performed during the
2
same I C-bus communication, for example, changing a color and global brightness at the
same time.
Only the 4 least significant bits D[3:0] are affected by the AI[2:0] bits.
When the Control register is written, the register entry point determined by D[3:0] is
the first register that will be addressed (read or write operation), and can be anywhere
between 0000 and 1100 (as defined in Table 6). When AI[2] = 1, the Auto-Increment
flag is set and the rollover value at which the point where the register increment stops
and goes to the next one is determined by AI[2:0]. See Table 5 for rollover values.
For example, if the Control register = 1110 1000 (E8h), then the register addressing
sequence will be (in hex):
08 → … → 0C → 00 → … → 07 → 02 → … → 07 → 02 → … → 07 → 02 → …
as long as the controller keeps sending or reading data.
7.3 Register definitions
Table 6. Register summary
Only D[3:0] = 0000 to 1100 are allowed and will be acknowledged. D[3:0] = 1101, 1110, or 1111 are reserved and will not be
acknowledged.
When writing to the Control register, bit 4 must be programmed with logic 0 for proper device operation.
Register number (hex)
D3
D2
D1
D0
Name
Type
Function
00h
0
0
0
0
MODE1
read/write
Mode register 1
01h
0
0
0
1
MODE2
read/write
Mode register 2
02h
0
0
1
0
PWM0
read/write
brightness control LED0
03h
0
0
1
1
PWM1
read/write
brightness control LED1
04h
0
1
0
0
PWM2
read/write
brightness control LED2
05h
0
1
0
1
PWM3
read/write
brightness control LED3
06h
0
1
1
0
GRPPWM
read/write
group duty cycle control
07h
0
1
1
1
GRPFREQ
read/write
group frequency
08h
1
0
0
0
LEDOUT
read/write
LED output state
09h
1
0
0
1
SUBADR1
read/write
I C-bus subaddress 1
0Ah
1
0
1
0
SUBADR2
read/write
I C-bus subaddress 2
0Bh
1
0
1
1
SUBADR3
read/write
I C-bus subaddress 3
0Ch
1
1
0
0
ALLCALLADR
read/write
LED All Call I C-bus address
PCA9632
Product data sheet
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Rev. 6 — 21 September 2021
2
2
2
2
© NXP B.V. 2021. All rights reserved.
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PCA9632
NXP Semiconductors
2
4-bit Fm+ I C-bus low power LED driver
7.3.1 Mode register 1, MODE1
Table 7. MODE1 - Mode register 1 (address 00h) bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
AI2
read only
0
Register Auto-Increment disabled
1*
Register Auto-Increment enabled
0*
Auto-Increment bit 1 = 0
1
Auto-Increment bit 1 = 1
0*
Auto-Increment bit 0 = 0
1
Auto-Increment bit 0 = 1
0
Normal mode .
1*
Low power mode. Oscillator off .
0*
PCA9632 does not respond to I C-bus subaddress 1.
1
PCA9632 responds to I C-bus subaddress 1.
0*
PCA9632 does not respond to I C-bus subaddress 2.
1
PCA9632 responds to I C-bus subaddress 2.
0*
PCA9632 does not respond to I C-bus subaddress 3.
1
PCA9632 responds to I C-bus subaddress 3.
0
PCA9632 does not respond to LED All Call I C-bus address.
1*
PCA9632 responds to LED All Call I C-bus address.
6
AI1
5
AI0
4
R/W
SUB1
2
R/W
SUB2
1
R/W
SUB3
0
[2]
read only
SLEEP
3
[1]
read only
R/W
ALLCALL
R/W
[1]
[2]
2
2
2
2
2
2
2
2
It takes 500 μs max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not guaranteed if PWMx,
GRPPWM or GRPFREQ registers are accessed within the 500 μs window.
When the oscillator is off (Sleep mode), the LED outputs cannot be turned on, off or dimmed/blinked.
7.3.2 Mode register 2, MODE2
Table 8. MODE2 - Mode register 2 (address 01h) bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
-
read only
0*
reserved
6
-
read only
0*
reserved
5
DMBLNK
R/W
0*
Group control = dimming
1
Group control = blinking
0*
Output logic state not inverted. Value to use when no external driver used.
1
Output logic state inverted. Value to use when external driver used.
0*
Outputs change on STOP command.
1
Outputs change on ACK.
0*
The 4 LED outputs are configured with an open-drain structure.
1
The 4 LED outputs are configured with a totem pole structure.
01*
unused
4
3
2
1 to 0
INVRT
[1]
R/W
OCH
R/W
[1]
OUTDRV
OUTNE[1:0]
PCA9632
Product data sheet
R/W
R/W
[2]
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PCA9632
NXP Semiconductors
2
4-bit Fm+ I C-bus low power LED driver
[1]
[2]
See Section 7.6 "Using the PCA9632 with and without external drivers" for more details. Normal LEDs can be driven directly in either mode. Some newer
LEDs include integrated Zener diodes to limit voltage transients, reduce EMI, protect the LEDs, and these must be driven only in the open-drain mode to
prevent overheating the IC.
Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9632. Applicable to registers from 02h (PWM0) to 08h
(LEDOUT) only.
7.3.3 PWM registers 0 to 3, PWMx — Individual brightness control registers
Table 9. PWM0 to PWM3 - PWM registers 0 to 3 (address 02h to 05h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access Value
Description
02h
PWM0
7:0
IDC0[7:0]
R/W
0000 0000* PWM0 Individual Duty Cycle
03h
PWM1
7:0
IDC1[7:0]
R/W
0000 0000* PWM1 Individual Duty Cycle
04h
PWM2
7:0
IDC2[7:0]
R/W
0000 0000* PWM2 Individual Duty Cycle
05h
PWM3
7:0
IDC3[7:0]
R/W
0000 0000* PWM3 Individual Duty Cycle
While operating in Individual brightness mode (LDRx = 10), a 1.5625 kHz fixed frequency
signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = LED output at maximum
brightness). In this mode, all the 8 bits are used.
(1)
E.g., if IDCx[7:0] = 1111 1111, then duty cycle = 255 / 256 = 99.6 %.
While operating in group dimming mode, a 6.25 kHz fixed frequency signal is used for
each output. Duty cycle is controlled through 64 linear steps from 00h (0 % duty cycle
= LED output off) to 3Fh (98.4 % duty cycle = LED output at maximum brightness). In
this mode only the 6 MSBs are used (IDCx[7:2]). The 2 LSBs IDCx[1:0] are ignored.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
(2)
E.g., if IDCx[7:2] = 111111, then duty cycle = 1111 1100 / 256 = 252 / 256 = 98.4 %.
While operating in blink mode, a 1.5625 kHz fixed frequency signal is used for each
output. Duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = LED
output off) to FFh (99.6 % duty cycle = LED output at maximum brightness). In this mode,
all the 8 bits are used.
(3)
E.g., if IDCx[7:0] = 1111 1111, then duty cycle = 255 / 256 = 99.6 %.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
7.3.4 Group duty cycle control, GRPPWM
Table 10. GRPPWM - Group duty cycle control register (address 06h) bit
description
Legend: * default value.
PCA9632
Product data sheet
Address
Register
Bit
Symbol
Access
Value
Description
06h
GRPPWM
7:0
GDC[7:0]
R/W
1111 1111
GRPPWM register
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PCA9632
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2
4-bit Fm+ I C-bus low power LED driver
When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz fixed frequency
signal is superimposed with the 6.25 kHz Individual brightness control signal. GRPPWM
is then used as a global brightness control allowing the LED outputs to be dimmed with
the same value. The value in GRPFREQ is then a ‘don’t care’.
In the group dimming mode (DMBLNK = 0) global brightness for the 4 outputs is
controlled through 16 linear steps from 00h (0 % duty cycle = LED output off) to F0h
(93.75 % duty cycle = maximum brightness). In this mode only the 4 MSBs of the
GRPPWM[7:4] are used. Bits GRPPWM[3:0] are unused.
(4)
E.g., if GDC[7:4] = 1111, then duty cycle = 1111 0000 / 256 = 240 / 256 = 93.75 %.
When DMBLNK bit is programmed with 1, GRPPWM and GRPFREQ registers define
a global blinking pattern, where GRPFREQ contains the blinking period (from 24 Hz to
10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
In this mode, when GRPFREQ is programmed to provide a blinking with frequency
programmable from 24 Hz to 6 Hz, GRPPWM[7:2] is used to provide 64-step duty cycle
resolution from 0 % to 98.4 %. GRPPWM[1:0] bits are unused.
(5)
E.g., if GDC[7:2] = 111111, then duty cycle = 1111 1100 / 256 = 252 / 256 = 98.4 %.
When GRPFREQ is programmed to provide a blinking with frequency programmable
from 6 Hz to 0.09 Hz (10.73 s), GRPPWM[7:0] is used to provide a 256-step duty cycle
resolution from 0 % to 99.6 %. In this case, all the 8 bits of the GRPPWM register are
used.
(6)
E.g., If GDC[7:0] = 1111 1111, then duty cycle = 255 / 256 = 99.6 %.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
7.3.5 Group frequency, GRPFREQ
Table 11. GRPFREQ - Group frequency register (address 07h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
07h
GRPFREQ
7:0
GFRQ[7:0]
R/W
0000 0000*
GRPFREQ register
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to logic 1. Value in this register is a ‘don’t care’ when DMBLNK = 0.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)
to FFh (10.73 seconds).
(7)
PCA9632
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PCA9632
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2
4-bit Fm+ I C-bus low power LED driver
7.3.6 LED driver output state, LEDOUT
Table 12. LEDOUT - LED driver output state register (address 08h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
08h
LEDOUT
7:6
LDR3
R/W
00*
LED3 output state control
5:4
LDR2
R/W
00*
LED2 output state control
3:2
LDR1
R/W
00*
LED1 output state control
1:0
LDR0
R/W
00*
LED0 output state control
LDRx = 00 — LED driver x is off (default power-up state).
LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking
not controlled).
LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx
register.
LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be
controlled through its PWMx register and the GRPPWM registers.
2
7.3.7 I C-bus subaddress 1 to 3, SUBADRx
2
Table 13. SUBADR1 to SUBADR3 - I C-bus subaddress registers 0 to 3 (address 09h to 0Bh)
bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access Value
Description
09h
SUBADR1
7:1
A1[7:1]
R/W
1110 001*
I C-bus subaddress 1
0
A1[0]
R only
0*
reserved
7:1
A2[7:1]
R/W
1110 010*
I C-bus subaddress 2
0
A2[0]
R only
0*
reserved
7:1
A3[7:1]
R/W
1110 100*
I C-bus subaddress 3
0
A3[0]
R only
0*
reserved
0Ah
0Bh
SUBADR2
SUBADR3
2
2
2
2
Subaddresses are programmable through the I C-bus. Default power-up values are E2h,
E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up
(the corresponding SUBx bit in MODE1 register is equal to logic 0).
Once subaddresses have been programmed to their right values, SUBx bits need to be
set to 1 in order to have the device acknowledging these addresses (MODE1 register).
2
Only the 7 MSBs representing the I C-bus subaddress are valid. The LSB in SUBADRx
register is a read-only bit (0).
2
When SUBx is set to 1, the corresponding I C-bus subaddress can be used during either
2
an I C-bus read or write sequence.
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PCA9632
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2
4-bit Fm+ I C-bus low power LED driver
2
7.3.8 LED All Call I C-bus address, ALLCALLADR
2
Table 14. ALLCALLADR - LED All Call I C-bus address register (address 0Ch) bit
description
Legend: * default value.
Address
Register
Bit
Symbol
Access Value
Description
0Ch
ALLCALLADR
7:1
AC[7:1]
R/W
1110 000*
ALLCALL I C-bus
address register
0
AC[0]
R only
0*
reserved
2
2
The LED All Call I C-bus address allows all the PCA9632s in the bus to be programmed
at the same time (ALLCALL bit in register MODE1 must be equal to 1, power-up default
2
state). This address is programmable through the I C-bus and can be used during either
2
an I C-bus read or write sequence. The register address can be programmed as a sub
call.
2
Only the 7 MSBs representing the All Call I C-bus address are valid. The LSB in
ALLCALLADR register is a read-only bit (0).
If ALLCALL bit = 0, the device does not acknowledge the address programmed in
register ALLCALLADR.
7.4 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCA9632 in a reset
condition until VDD has reached VPOR. At this point, the reset condition is released and
2
the PCA9632 registers and I C-bus state machine are initialized to their default states
(all zeroes) causing all the channels to be deselected. Thereafter, VDD must be lowered
below 0.2 V to reset the device.
7.5 Software reset
2
The Software Reset Call (SWRST Call) allows all the devices in the I C-bus to be reset
2
to the power-up state value through a specific formatted I C-bus command. To be
2
performed correctly, it implies that the I C-bus is functional and that there is no device
hanging the bus.
The SWRST Call function is defined as the following:
2
1. A START command is sent by the I C-bus controller.
2
2. The reserved SWRST I C-bus address ‘0000 011’ with the R/W bit set to 0 (write) is
2
sent by the I C-bus controller.
3. The PCA9632 device(s) acknowledge(s) after seeing the SWRST Call address ‘0000
0110’ (06h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to the
2
I C-bus controller.
4. Once the SWRST Call address has been sent and acknowledged, the controller
sends 2 bytes with 2 specific values (SWRST data byte 1 and byte 2):
a. Byte 1 = A5h: the PCA9632 acknowledges this value only. If byte 1 is not equal to
A5h, the PCA9632 does not acknowledge it.
b. Byte 2 = 5Ah: the PCA9632 acknowledges this value only. If byte 2 is not equal to
5Ah, then the PCA9632 does not acknowledge it.
If more than 2 bytes of data are sent, the PCA9632 does not acknowledge any more.
PCA9632
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2
PCA9632
4-bit Fm+ I C-bus low power LED driver
5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and
correctly acknowledged, the controller sends a STOP command to end the SWRST
Call: the PCA9632 then resets to the default value (power-up value) and is ready to
be addressed again within the specified bus free time (tBUF).
2
The I C-bus controller must interpret a non-acknowledge from the PCA9632 (at any time)
as a ‘SWRST Call Abort’. The PCA9632 does not initiate a reset of its registers. This
happens only when the format of the SWRST Call sequence is not correct.
7.6 Using the PCA9632 with and without external drivers
The PCA9632 LED output drivers are 5.5 V only tolerant and can sink up to 25 mA at 5 V.
If the device needs to drive LEDs to a higher voltage and/or higher current, use of an
external driver is required.
• INVRT bit (MODE2 register) can be used to keep the LED PWM control firmware the
same (PWMx and GRPPWM values directly calculated from their respective formulas
and the LED output state determined by LEDOUT register value) independently of the
type of external driver.
• OUTDRV bit (MODE2 register) allows minimizing the amount of external components
required to control the external driver (N-type or P-type device).
Table 15. Use of INVRT and OUTDRV based on connection to the LEDn outputs
INVRT OUTDRV Direct connection to LEDn
Firmware
External
pull-up
resistor
External N-type driver
External P-type driver
Firmware
External
pull-up
resistor
Firmware
formulas and LED required
output state values
apply
External
pull-up
resistor
0
0
formulas and LED
output state values
[1]
apply
LED current formulas and
[1]
limiting R
LED output state
values inverted
required
0
1
formulas and LED
output state values
[1]
apply
LED current formulas and
[1]
limiting R
LED output state
values inverted
not required formulas and LED not
[2]
output state values required
[2]
apply
1
0
formulas and LED
output state values
inverted
LED current formulas and
limiting R
LED output state
values apply
required
formulas and LED required
output state values
inverted
1
1
formulas and LED
output state values
inverted
LED current formulas and
limiting R
LED output state
[3]
values apply
not
[3]
required
formulas and LED not required
output state values
inverted
[1]
[2]
[3]
Correct configuration when LEDs directly connected to the LEDn outputs (connection to VDD through current limiting resistor).
Optimum configuration when external P-type (PNP, PMOS) driver used.
Optimum configuration when external N-type (NPN, NMOS) driver used.
PCA9632
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PCA9632
NXP Semiconductors
2
4-bit Fm+ I C-bus low power LED driver
Table 16. Output transistors based on LEDOUT registers, INVRT and OUTDRV bits
LEDOUT
INVRT
OUTDRV Upper transistor Lower transistor (LEDn to
(VDD to LEDn)
VSS)
LEDn state
00
LED driver off
0
0
off
off
high-Z
0
1
on
off
VDD
1
0
off
on
VSS
1
1
off
on
VSS
0
0
off
on
VSS
0
1
off
on
VSS
1
0
off
off
high-Z
1
1
on
off
VDD
0
0
off
Individual PWM (non-inverted) VSS or high-Z
0
1
Individual PWM
(non-inverted)
Individual PWM (non-inverted) VSS or VDD = PWMx value
1
0
off
Individual PWM (inverted)
high-Z
1
1
Individual PWM
(inverted)
Individual PWM (inverted)
VDD or VSS = 1 - PWMx value
0
0
off
Individual + Group PWM (non- VSS or high-Z = PWMx/
inverted)
GRPPWM values
0
1
Individual PWM
(non-inverted)
Individual PWM (non-inverted) VSS or VDD = PWMx/GRPPWM
values
1
0
off
Individual + Group PWM
(inverted)
high-Z or VSS = (1 - PWMx) or (1
- GRPPWM) values
1
1
Individual PWM
(inverted)
Individual PWM (inverted)
VDD or VSS = (1 - PWMx) or (1 GRPPWM) values
01
LED driver on
10
Individual
brightness
control
11
Individual
+ group
dimming/
blinking
[1]
[1]
[1]
[1]
[1]
= PWMx value
or VSS = 1 - PWMx value
[1]
[1]
External pull-up or LED current limiting resistor connects LEDn to VDD.
7.7 Individual brightness control with group dimming/blinking
A 1.5625 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is
used to control individually the brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can
be applied to the 4 LED outputs):
• A lower 190 Hz fixed frequency signal with programmable duty cycle (4 bits, 16 steps)
is used to provide a global brightness control.
1
• A programmable frequency signal from 24 Hz to ⁄10.73 Hz (8 bits, 256 steps) with
programmable duty cycle (6 bits, 64 steps) is used to provide a global blinking control
1
for (24 Hz to 6 Hz) and (8 bits, 256 steps) for (6 Hz to ⁄10.73 Hz).
PCA9632
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PCA9632
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2
4-bit Fm+ I C-bus low power LED driver
1
2
3
4
5
6
7
8
9 10 11 12
507
508
509
510
511
512
1
2
3
4
5
6
7
8
9 10 11
brightness control signal (LEDn)
N × 2.5 µs
with N = (0 to 256)
(PWMx Register)
256 × 2.5 µs = 640 µs
(1.5625 kHz)
002aad101
Minimum pulse width for LEDn brightness control is 2.5 μs.
Figure 8. Individual LED brightness control signals
1
2
3
4
5
6
7
8
9 10 11 12
27 28 29 30 31 32 1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9 10 11
brightness control signal (LEDn)
N × 2.5 µs
with N = (0 to 64)
(PWMx Register)
M × 64 × 2 × 2.5 µs
with M = (1 to 16)
(GRPPWM Register)
64 × 2.5 µs = 160 µs
(6.25 kHz)
group dimming signal
16 × 64 × 2 × 2.5 µs = 5.24 ms (190.7 Hz)
1
2
3
4
5
6
7
8
1
resulting brightness + group dimming signal (M = 4)
002aad042
Minimum pulse width for LEDn brightness control is 2.5 μs.
Minimum pulse width for group dimming is 320 μs (M = 1).
When M = 1 (GRPPWM register value), the resulting LEDn brightness control + group dimming signal will have 2 pulses of
the LED brightness control signal (pulse width = N × 2.5 μs, with ‘N’ defined in PWMx register).
Figure 9. Brightness + group dimming signals
Table 17. Dimming and blinking resolution
Type of control
DMBLNK
GRPPWM
GRPFREQ
Frequency
PWMx
Individual LED brightness 10
without dimming
X
X
X
1.5625 kHz
256 steps
Individual LED brightness 11
with global dimming
0
16 steps
X
190 Hz with 6.25 kHz modulation
64 steps
Blinking (fast)
11
1
64 steps
256 steps
blink frequency = 6 Hz to 24 Hz
PWMx frequency = 1.5625 kHz
256 steps
Blinking (slow)
11
1
256 steps
256 steps
blink frequency = 0.09 Hz to 6 Hz
PWMx frequency = 1.5625 kHz
256 steps
PCA9632
Product data sheet
LDRx
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2
PCA9632
4-bit Fm+ I C-bus low power LED driver
8
2
Characteristics of the I C-bus
2
The I C-bus is for 2-way, 2-line communication between different ICs or modules. The
two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at
this time will be interpreted as control signals (see Figure 10).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Figure 10. Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 11).
SDA
SCL
S
P
START condition
STOP condition
mba608
Figure 11. Definition of START and STOP conditions
8.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘controller’ and the devices which are controlled
by the controller are the ‘targets’ (see Figure 12).
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PCA9632
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2
4-bit Fm+ I C-bus low power LED driver
SDA
SCL
CONTROLLER
TRANSMITTER/
RECEIVER
TARGET
RECEIVER
TARGET
TRANSMITTER/
RECEIVER
CONTROLLER
TRANSMITTER
CONTROLLER
TRANSMITTER/
RECEIVER
I2C-BUS
MULTIPLEXER
TARGET
002aaa966
Figure 12. System configuration
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions
from transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the controller generates an extra acknowledge related clock pulse.
A target receiver which is addressed must generate an acknowledge after the reception
of each byte. Also a controller must generate an acknowledge after the reception of each
byte that has been clocked out of the target transmitter. The device that acknowledges
has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during the HIGH period of the acknowledge related clock pulse; set-up time
and hold time must be taken into account.
A controller receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the target. In this event, the
transmitter must leave the data line HIGH to enable the controller to generate a STOP
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from controller
1
2
S
8
clock pulse for
acknowledgement
START
condition
9
002aaa987
2
Figure 13. Acknowledgment on the I C-bus
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PCA9632
4-bit Fm+ I C-bus low power LED driver
9
Bus transactions
target address(1)
S
1
1
0
0
data for register D3, D2, D1, D0(2)
control register
0 A1 A0 0
START condition
A
X
X
X
0 D3 D2 D1 D0 A
Auto-Increment options
Auto-Increment flag
R/W
A
acknowledge
from target
P
acknowledge
from target
acknowledge
from target
STOP
condition
002aad043
1. 10-pin version only.
2. See Table 6 for register definition.
Figure 14. Write to a specific register
target address(1)
S
1
1
0
0
control register
0 A1 A0 0
START condition
A
1
0
0
0
0
0
0
MODE1
register
selection
Auto-Increment
on all registers
R/W
acknowledge
from target
0
MODE1 register
MODE2 register
A
acknowledge
from target
A
A
acknowledge
from target
acknowledge
from target
(cont.)
Auto-Increment on
SUBADR3 register
ALLCALLADR register
(cont.)
A
A
acknowledge
from target
acknowledge
from target
P
STOP
condition
002aad044
1. 10-pin version only.
Figure 15. Write to all registers using the Auto-Increment feature
target address(1)
S
1
1
0
0
control register
0 A1 A0 0
START condition
A
R/W
acknowledge
from target
1
0
1
0
0
0
PWM0 register
1
0
PWM0
register
selection
increment
on Individual
brightness
registers only
PWM1 register
A
acknowledge
from target
A
A
acknowledge
from target
acknowledge
from target
(cont.)
Auto-Increment on
PWM2 register
(cont.)
PWM3 register
PWM0 register
PWMx register
A
A
A
A
acknowledge
from target
acknowledge
from target
acknowledge
from target
acknowledge
from target
P
STOP
condition
002aad045
1. 10-pin version only.
Figure 16. Multiple writes to Individual brightness registers only using the Auto-Increment feature
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PCA9632
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2
4-bit Fm+ I C-bus low power LED driver
target address(1)
S
1
1
0
0
ReSTART
condition
control register
0 A1 A0 0
START condition
A
1
data from MODE2 register
(cont.)
0
0
0
0
0
0
MODE1
register
selection
Auto-Increment
on all registers
R/W
acknowledge
from target
0
target address
data from MODE1 register
A Sr A6 A5 A4 A3 A2 A1 A0 1
acknowledge
from target
R/W
acknowledge
from controller
acknowledge
from target
Auto-Increment on
data from
ALLCALLADR register
data from PWM0
A (cont.)
A
data from
MODE1 register
A
A
A
acknowledge
from controller
acknowledge
from controller
acknowledge
from controller
A (cont.)
acknowledge
from controller
data from last read byte
(cont.)
A
not acknowledge
from controller
P
STOP
condition
002aad046
1. 10-pin version only.
Figure 17. Read all registers using the Auto-Increment feature
target address(1)
sequence (A) S
1
1
0
0
new LED All Call I 2C-bus address(2)
control register
0 A1 A0 0
START condition
A
R/W
acknowledge
from target
X
X
X
0
1
1
0
0
A
1
0
1
0
1
ALLCALLADR
register selection acknowledge
from target
Auto-Increment on
0
1
X
A
P
acknowledge
from target
STOP
condition
the 16 LEDs are on at the acknowledge(3)
LED All Call I 2C-bus address
sequence (B) S
1
0
1
0
START condition
1
0
1
control register
0
A
R/W
acknowledge
from the
4 devices
X
X
X
0
1
0
LEDOUT register (LED fully ON)
0
0
A
0
1
0
1
0
LEDOUT
register selection acknowledge
from the
4 devices
1
0
1
A
P
acknowledge
from the
4 devices
STOP
condition
002aad047
1. 10-pin version is used for this figure. Four PCA9632DP2 or PCA9632TK2 and same sequence (A) (above) is sent to
each of them. A[1:0] = 00 to 11.
2. ALLCALL bit in MODE1 register is equal to logic 1 for this example.
3. OCH bit in MODE2 register is equal to logic 1 for this example.
2
Figure 18. LED All Call I C-bus address programming and LED All Call sequence example
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PCA9632
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2
4-bit Fm+ I C-bus low power LED driver
SWRST data
Byte 1 = A5h
SWRST Call I2C address
S
0
0
0
0
START condition
0
1
1
0
A
1
0
1
0
0
1
SWRST data
Byte 2 = 5Ah
0
R/W
1
A
0
1
0
1
1
acknowledge
from target(s)
acknowledge
from target(s)
0
1
0
A
P
acknowledge
from target(s)
PCA9632 is(are) reset.
Registers are set to default power-up values.
002aad048
Figure 19. Software Reset (SWRST) Call sequence
10 Application design-in information
5V
12 V
VDD = 2.5 V, 3.3 V or 5.0 V
I2C-BUS/SMBus
CONTROLLER
SDA
10 kΩ
10 kΩ
VDD
SDA
SCL
LED0
SCL
LED1
LED2
A0
PCA9632
A1
VSS
LED3
002aad049
2
I C-bus address = 1100 001X.
All of the 4 LED outputs configurable as either open-drain or totem pole. Mixing of configurations
is not possible.
Figure 20. Typical application
Question 1: What kind of edge rate control is there on the outputs?
• The typical edge rates depend on the output configuration, supply voltage, and the
applied load. The outputs can be configured as either open-drain NMOS or totem pole
outputs. If the customer is using the part to directly drive LEDs, they should be using
it in an open-drain NMOS, if they are concerned about the maximum ISS and ground
bounce. The edge rate control was designed primarily to slow down the turn-on of the
output device; it turns off rather quickly (~ 1.5 ns). In simulation, the typical turn-on time
for the open-drain NMOS was ~ 14 ns (VDD = 3.6 V; CL = 50 pF; RPU = 500 Ω).
Question 2: Is ground bounce possible?
• Ground bounce is a possibility, especially if all 16 outputs transition at full current (25
mA each). There is a fair amount of decoupling capacitance on-chip (~ 50 pF), which is
intended to suppress some of the ground bounce. The customer will need to determine
if additional decoupling capacitance externally placed as close as physically possible to
the device is required.
Question 3: Can I really sink 400 mA through the single ground pin on the package and
will this cause any ground bounce problem due to the PWM of the LEDs?
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PCA9632
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2
4-bit Fm+ I C-bus low power LED driver
• Yes, you can sink 400 mA through a single ground pin on the package. Although
the package only has one ground pin, there are two ground pads on the die itself
connected to this one pin. Although some ground bounce is likely, it will not disrupt the
operation of the part and would be reduced by the external decoupling capacitance.
Question 4: I can’t turn the LEDs on or off, but their registers are set properly. Why?
• Check the Mode register 1 bit 4 (MODE1[4]) SLEEP setting. The value needs to be
a logic 0 so that the OSC is turned on. If the OSC is turned off, the LEDs cannot be
turned on or off and also can’t be dimmed or blinked.
Question 5: I’m using LEDs with integrated Zener diodes and the IC is getting very hot.
Why?
• The IC outputs can be set to either open-drain or push-pull and default to push-pull
outputs. In this application with the Zener diodes, they need to be set to open-drain
since in the push-pull architecture there is a low resistance path to ground through the
Zener and this is causing the IC to overheat. The PCA9632/33/34/35 ICs all power-up
in the push-pull output mode and with the logic state HIGH, so one of the first things
that need to be done is to set the outputs to open-drain.
11 Limiting values
Table 18. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
Min
Max
Unit
supply voltage
-0.5
+6.0
V
VI/O
voltage on an input/output pin
VSS - 0.5
5.5
V
IO(LEDn)
output current on pin LEDn
-
25
mA
ISS
ground supply current
-
100
mA
Ptot
total power dissipation
-
400
mW
Tstg
storage temperature
-65
+150
°C
Tamb
ambient temperature
-40
+85
°C
PCA9632
Product data sheet
Conditions
operating
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PCA9632
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4-bit Fm+ I C-bus low power LED driver
12 Static characteristics
Table 19. Static characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.3
-
5.5
V
VDD = 2.3 V
-
38
150
μA
VDD = 3.3 V
-
53
150
μA
VDD = 5.5 V
-
108
150
μA
-
0.005
1
μA
-
1.70
2.0
V
Supply
VDD
supply voltage
IDD
supply current
Istb
standby current
operating mode; no load; fSCL = 1 MHz
no load; fSCL = 0 Hz; I/O = inputs; VI = VDD
VDD = 5.5 V, MODE1[4] = 1 (Sleep
mode)
VPOR
power-on reset voltage
no load; VI = VDD or VSS
[1]
Input SCL; input/output SDA
VIL
LOW-level input voltage
-0.5
-
+0.3VDD V
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
IOL
LOW-level output
current
VOL = 0.4 V; VDD = 2.3 V
20
-
-
mA
VOL = 0.4 V; VDD = 5.0 V
30
-
-
mA
IL
leakage current
VI = VDD or VSS
-1
-
+1
μA
Ci
input capacitance
VI = VSS
-
6
10
pF
LED driver outputs
IOL
LOW-level output
current
VOL = 0.5 V; VDD = 2.3 V
[2]
12
-
-
mA
VOL = 0.5 V; VDD = 3.0 V
[2]
17
-
-
mA
VOL = 0.5 V; VDD = 4.5 V
[2]
25
-
-
mA
[2]
-
-
100
mA
IOL(tot)
total LOW-level output
current
VOL = 0.5 V; VDD = 4.5 V
VOH
HIGH-level output
voltage
IOH = -10 mA; VDD = 2.3 V
1.6
-
-
V
IOH = -10 mA; VDD = 3.0 V
2.3
-
-
V
IOH = -10 mA; VDD = 4.5 V
4.0
-
-
V
-
2.5
5
pF
Co
[1]
[2]
output capacitance
VDD must be lowered to 0.2 V in order to reset part.
Each bit must be limited to a maximum of 25 mA and the total package limited to 100 mA due to internal busing limits.
PCA9632
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PCA9632
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4-bit Fm+ I C-bus low power LED driver
13 Dynamic characteristics
Table 20. Dynamic characteristics
Symbol Parameter
Conditions
[1]
Standard2
mode I C-bus
Fast-mode
2
I C-bus
Fast-mode
2
Plus I C-bus
Min
Max
Min
Max
Min
Max
0
100
0
400
0
1000
Unit
fSCL
SCL clock frequency
kHz
tBUF
bus free time between a
STOP and START condition
4.7
-
1.3
-
0.5
-
μs
tHD;STA
hold time (repeated) START
condition
4.0
-
0.6
-
0.26
-
μs
tSU;STA
set-up time for a repeated
START condition
4.7
-
0.6
-
0.26
-
μs
tSU;STO
set-up time for STOP
condition
4.0
-
0.6
-
0.26
-
μs
tHD;DAT
data hold time
0
-
0
-
0
-
ns
data valid acknowledge time
[2]
0.3
3.45
0.1
0.9
0.05
0.45
μs
tVD;DAT
data valid time
[3]
0.3
3.45
0.1
0.9
0.05
0.45
μs
tSU;DAT
data set-up time
250
-
100
-
50
-
ns
tLOW
LOW period of the SCL
clock
4.7
-
1.3
-
0.5
-
μs
tHIGH
HIGH period of the SCL
clock
4.0
-
0.6
-
0.26
-
μs
tf
fall time of both SDA and
SCL signals
-
300
20 + 0.1Cb
[6]
300
-
120
ns
tr
risetime of both SDA and
SCL signals
-
1000
20 + 0.1Cb
[6]
300
-
120
ns
tSP
pulse width of spikes that
must be suppressed by the
input filter
-
50
50
-
50
ns
tVD;ACK
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[4] [5]
[7]
-
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held LOW for a minimum
of 25 ms. Disable bus time-out feature for DC operation.
tVD;ACK = time for Acknowledgment signal from SCL LOW to SDA (out) LOW.
tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
A controller device must internally provide a hold time of at least 300 ns for the SDA signal (refer to Table 19, VIL of the SCL signal) in order to bridge the
undefined region of SCL’s falling edge.
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified at 250 ns. This
allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum
specified tf.
Cb = total capacitance of one bus line in pF.
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
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PCA9632
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2
4-bit Fm+ I C-bus low power LED driver
0.7 × VDD
SDA
0.3 × VDD
tr
tBUF
tf
tHD;STA
tSP
tLOW
0.7 × VDD
SCL
0.3 × VDD
P
S
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
Sr
tSU;STO
P
002aaa986
Figure 21. Definition of timing
protocol
START
condition
(S)
tSU;STA
bit 7
MSB
(A7)
tLOW
bit 6
(A6)
tHIGH
bit 1
(D1)
bit 0
(D0)
STOP
condition
(P)
acknowledge
(A)
1 / fSCL
0.7 × VDD
SCL
tBUF
tr
0.3 × VDD
tf
0.7 × VDD
SDA
0.3 × VDD
tHD;STA
tSU;DAT
tVD;DAT
tHD;DAT
tVD;ACK
tSU;STO
002aab285
Rise and fall times refer to VIL and VIH.
2
Figure 22. I C-bus timing diagram
14 Test information
VDD
PULSE
GENERATOR
VI
DUT
VO
RT
RL
500 Ω
VDD
open
VSS
CL
50 pF
002aab880
RL = Load resistor for LEDn. RL for SDA and SCL > 1 kΩ (3 mA or less current).
CL = Load capacitance includes jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generators.
Figure 23. Test circuitry for switching times
PCA9632
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PCA9632
NXP Semiconductors
2
4-bit Fm+ I C-bus low power LED driver
15 Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
D
E
SOT505-1
A
X
c
y
HE
v M A
Z
5
8
A2
pin 1 index
(A3)
A1
A
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.45
0.25
0.28
0.15
3.1
2.9
3.1
2.9
0.65
5.1
4.7
0.94
0.7
0.4
0.1
0.1
0.1
0.70
0.35
6°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-04-09
03-02-18
SOT505-1
Figure 24. Package outline SOT505-1 (TSSOP8)
PCA9632
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PCA9632
NXP Semiconductors
2
4-bit Fm+ I C-bus low power LED driver
HVSON8: plastic thermal enhanced very thin small outline package; no leads;
8 terminals; body 3 x 3 x 0.85 mm
SOT908-1
0
1
2 mm
scale
X
D
B
A
E
A
A1
c
detail X
terminal 1
index area
e1
terminal 1
index area
e
v
w
b
1
4
M
M
C
C A B
C
y1 C
y
L
exposed tie bar (4×)
Eh
exposed tie bar (4×)
8
5
Dh
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
b
1
0.05
0.00
0.3
0.2
c
D(1)
Dh
E(1)
Eh
0.2
3.1
2.9
2.25
1.95
3.1
2.9
1.65
1.35
e
0.5
e1
L
v
w
y
y1
1.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
SOT908-1
JEDEC
JEITA
MO-229
EUROPEAN
PROJECTION
ISSUE DATE
05-09-26
05-10-05
Figure 25. Package outline SOT908-1 (HVSON8)
PCA9632
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PCA9632
NXP Semiconductors
2
4-bit Fm+ I C-bus low power LED driver
TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm
D
E
SOT552-1
A
X
c
y
HE
v M A
Z
6
10
A2
pin 1 index
(A3)
A1
A
θ
Lp
L
1
5
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.15
0.23
0.15
3.1
2.9
3.1
2.9
0.5
5.0
4.8
0.95
0.7
0.4
0.1
0.1
0.1
0.67
0.34
6°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-07-29
03-02-18
SOT552-1
Figure 26. Package outline SOT552-1 (TSSOP10)
PCA9632
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NXP Semiconductors
2
PCA9632
4-bit Fm+ I C-bus low power LED driver
16 Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
17 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 "Surface mount reflow
soldering description".
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
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2
PCA9632
4-bit Fm+ I C-bus low power LED driver
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 27) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 21 and Table 22
Table 21. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
3
Volume (mm )
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 22. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
3
Volume (mm )
< 350
350 to 2 000
> 2 000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 27.
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PCA9632
NXP Semiconductors
2
4-bit Fm+ I C-bus low power LED driver
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 27. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
"Surface mount reflow soldering description".
18 Abbreviations
Table 23. Abbreviations
Acronym
Description
CDM
Charged-Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
2
PCA9632
Product data sheet
I C-bus
Inter-Integrated Circuit bus
LCD
Liquid Crystal Display
LED
Light Emitting Diode
LSB
Least Significant Bit
MSB
Most Significant Bit
NMOS
Negative-channel Metal-Oxide Semiconductor
PCB
Printed-Circuit Board
PMOS
Positive-channel Metal-Oxide Semiconductor
PWM
Pulse Width Modulation
RGB
Red/Green/Blue
RGBA
Red/Green/Blue/Amber
SMBus
System Management Bus
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PCA9632
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4-bit Fm+ I C-bus low power LED driver
19 Revision history
Table 24. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9632 v.6
20210921
Product data sheet
202104010DN
PCA9632 v.5
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP
Semiconductors, N.V. Legal texts have been adapted to the new company name where appropriate.
• Global changes, revised as follows:
– "Master" or "master": revised to "Controller" or "controller" to conform with NXP inclusive language
guidelines.
– "Slave" or "slave": revised to "Target" or "target" to conform with NXP inclusive language guidelines.
• Section 2: removed "HVSON10" from "Packages offered".
• Section 4: added pitch dimensions to the descriptions and removed the ordering information for
"PCA9632TK2".
• Section 4.1, added new section.
• Section 6.1, removed pin configuration for HVSON10.
• Section 6.2, Table 4: removed references to HVSON10.
• Section 15, removed figure for package outline SOT650-1 (HVSON10).
PCA9632 v.5
20110727
Product data sheet
—
PCA9632 v.4
PCA9632 v.4
20110701
Product data sheet
—
PCA9632 v.3
PCA9632 v.3
20080715
Product data sheet
—
PCA9632 v.2
PCA9632 v.2
20080401
Product data sheet
—
PCA9632 v.1
PCA9632 v.1
20070928
Objective data sheet
—
—
PCA9632
Product data sheet
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33 / 37
NXP Semiconductors
2
PCA9632
4-bit Fm+ I C-bus low power LED driver
20 Legal information
20.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
20.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed
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give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
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savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
PCA9632
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 21 September 2021
© NXP B.V. 2021. All rights reserved.
34 / 37
NXP Semiconductors
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PCA9632
4-bit Fm+ I C-bus low power LED driver
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
PCA9632
Product data sheet
Security — Customer understands that all NXP products may be subject
to unidentified or documented vulnerabilities. Customer is responsible
for the design and operation of its applications and products throughout
their lifecycles to reduce the effect of these vulnerabilities on customer’s
applications and products. Customer’s responsibility also extends to other
open and/or proprietary technologies supported by NXP products for use
in customer’s applications. NXP accepts no liability for any vulnerability.
Customer should regularly check security updates from NXP and follow up
appropriately. Customer shall select products with security features that best
meet rules, regulations, and standards of the intended application and make
the ultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may
be provided by NXP. NXP has a Product Security Incident Response Team
(PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation,
reporting, and solution release to security vulnerabilities of NXP products.
20.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
2
I C-bus — logo is a trademark of NXP B.V.
NXP — wordmark and logo are trademarks of NXP B.V.
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 21 September 2021
© NXP B.V. 2021. All rights reserved.
35 / 37
NXP Semiconductors
2
PCA9632
4-bit Fm+ I C-bus low power LED driver
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.
Tab. 11.
Tab. 12.
Ordering information ..........................................3
Ordering options ................................................3
Pin description for TSSOP8 and HVSON8 ........ 5
Pin description for TSSOP10 ............................ 6
Auto-Increment options ..................................... 8
Register summary ............................................. 9
MODE1 - Mode register 1 (address 00h) bit
description ....................................................... 10
MODE2 - Mode register 2 (address 01h) bit
description ....................................................... 10
PWM0 to PWM3 - PWM registers 0 to 3
(address 02h to 05h) bit description ................ 11
GRPPWM - Group duty cycle control
register (address 06h) bit description .............. 11
GRPFREQ - Group frequency register
(address 07h) bit description ...........................12
LEDOUT - LED driver output state register
(address 08h) bit description ...........................13
Tab. 13.
Tab. 14.
Tab. 15.
Tab. 16.
Tab. 17.
Tab. 18.
Tab. 19.
Tab. 20.
Tab. 21.
Tab. 22.
Tab. 23.
Tab. 24.
SUBADR1 to SUBADR3 - I2C-bus
subaddress registers 0 to 3 (address 09h to
0Bh) bit description ......................................... 13
ALLCALLADR - LED All Call I2Cbus address register (address 0Ch) bit
description ....................................................... 14
Use of INVRT and OUTDRV based on
connection to the LEDn outputs ...................... 15
Output transistors based on LEDOUT
registers, INVRT and OUTDRV bits ................ 16
Dimming and blinking resolution ..................... 17
Limiting values ................................................ 23
Static characteristics ....................................... 24
Dynamic characteristics .................................. 25
SnPb eutectic process (from J-STD-020D) ..... 31
Lead-free process (from J-STD-020D) ............ 31
Abbreviations ...................................................32
Revision history ...............................................33
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Fig. 14.
Fig. 15.
Block diagram of PCA9632 ...............................4
Pin configuration for TSSOP8 ........................... 5
Pin configuration for TSSOP10 ......................... 5
Pin configuration for HVSON8 .......................... 5
Target address .................................................. 7
Software reset address ..................................... 8
Control register ..................................................8
Individual LED brightness control signals ........ 17
Brightness + group dimming signals ............... 17
Bit transfer .......................................................18
Definition of START and STOP conditions ...... 18
System configuration .......................................19
Acknowledgment on the I2C-bus .................... 19
Write to a specific register ...............................20
Write to all registers using the AutoIncrement feature ............................................ 20
PCA9632
Product data sheet
Fig. 16.
Fig. 17.
Fig. 18.
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.
Fig. 24.
Fig. 25.
Fig. 26.
Fig. 27.
Multiple writes to Individual brightness
registers only using the Auto-Increment
feature ............................................................. 20
Read all registers using the Auto-Increment
feature ............................................................. 21
LED All Call I2C-bus address programming
and LED All Call sequence example ............... 21
Software Reset (SWRST) Call sequence ........ 22
Typical application ........................................... 22
Definition of timing .......................................... 26
I2C-bus timing diagram ................................... 26
Test circuitry for switching times ......................26
Package outline SOT505-1 (TSSOP8) ............27
Package outline SOT908-1 (HVSON8) ........... 28
Package outline SOT552-1 (TSSOP10) ..........29
Temperature profiles for large and small
components ..................................................... 32
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 21 September 2021
© NXP B.V. 2021. All rights reserved.
36 / 37
NXP Semiconductors
2
PCA9632
4-bit Fm+ I C-bus low power LED driver
Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.4
7.5
7.6
7.7
8
8.1
8.1.1
8.2
8.3
9
10
11
12
13
14
15
16
17
17.1
17.2
17.3
17.4
18
19
General description ............................................ 1
Features and benefits .........................................2
Applications .........................................................3
Ordering information .......................................... 3
Ordering options ................................................ 3
Block diagram ..................................................... 4
Pinning information ............................................ 5
Pinning ............................................................... 5
Pin description ................................................... 5
Functional description ........................................6
Device addresses .............................................. 6
Regular I2C-bus target address ........................ 6
LED All Call I2C-bus address ............................7
LED Sub Call I2C-bus addresses ......................7
Software reset I2C-bus address ........................ 7
Control register .................................................. 8
Register definitions ............................................ 9
Mode register 1, MODE1 .................................10
Mode register 2, MODE2 .................................10
PWM registers 0 to 3, PWMx — Individual
brightness control registers ............................. 11
Group duty cycle control, GRPPWM ............... 11
Group frequency, GRPFREQ .......................... 12
LED driver output state, LEDOUT ................... 13
I2C-bus subaddress 1 to 3, SUBADRx ............ 13
LED All Call I2C-bus address,
ALLCALLADR .................................................. 14
Power-on reset ................................................ 14
Software reset ................................................. 14
Using the PCA9632 with and without
external drivers ................................................ 15
Individual brightness control with group
dimming/blinking .............................................. 16
Characteristics of the I2C-bus ......................... 18
Bit transfer ....................................................... 18
START and STOP conditions .......................... 18
System configuration ....................................... 18
Acknowledge ....................................................19
Bus transactions ............................................... 20
Application design-in information ................... 22
Limiting values .................................................. 23
Static characteristics ........................................ 24
Dynamic characteristics ...................................25
Test information ................................................ 26
Package outline .................................................27
Handling information ........................................ 30
Soldering of SMD packages .............................30
Introduction to soldering .................................. 30
Wave and reflow soldering .............................. 30
Wave soldering ................................................ 30
Reflow soldering .............................................. 31
Abbreviations .................................................... 32
Revision history ................................................ 33
20
Legal information .............................................. 34
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 21 September 2021
Document identifier: PCA9632
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