PCA9634
8-bit Fm+ I2C-bus LED driver
Rev. 7.1 — 18 December 2017
Product data sheet
1. General description
The PCA9634 is an I2C-bus controlled 8-bit LED driver optimized for
Red/Green/Blue/Amber (RGBA) color mixing applications. Each LED output has its own
8-bit resolution (256 steps) fixed frequency Individual PWM controller that operates at
97 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set
to a specific brightness value. An additional 8-bit resolution (256 steps) Group PWM
controller has both a fixed frequency of 190 Hz and an adjustable frequency between
24 Hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 % to 99.6 %
that is used to either dim or blink all LEDs with the same value.
Each LED output can be off, on (no PWM control), set at its Individual PWM controller
value or at both Individual and Group PWM controller values. The LED output driver is
programmed to be either open-drain with a 25 mA current sink capability at 5 V or
totem-pole with a 25 mA sink, 10 mA source capability at 5 V. The PCA9634 operates with
a supply voltage range of 2.3 V to 5.5 V and the outputs are 5.5 V tolerant. LEDs can be
directly connected to the LED output (up to 25 mA, 5.5 V) or controlled with external
drivers and a minimum amount of discrete components for larger current or higher voltage
LEDs.
The PCA9634 is one of the first LED controller devices in a new Fast-mode Plus (Fm+)
family. Fm+ devices offer higher frequency (up to 1 MHz) and more densely populated
bus operation (up to 4000 pF).
The active LOW Output Enable input pin (OE) allows asynchronous control of the LED
outputs and can be used to set all the outputs to a defined I2C-bus programmable logic
state. The OE can also be used to externally PWM the outputs, which is useful when
multiple devices need to be dimmed or blinked together using software control.
Software programmable LED Group and three Sub Call I2C-bus addresses allow all or
defined groups of PCA9634 devices to respond to a common I2C-bus address, allowing
for example, all red LEDs to be turned on or off at the same time or marquee chasing
effect, thus minimizing I2C-bus commands. Seven hardware address pins allow up to
126 devices on the same bus.
The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9634
through the I2C-bus, identical to the Power-On Reset (POR) that initializes the registers to
their default state causing the outputs to be set HIGH (LED off). This allows an easy and
quick way to reconfigure all device registers to the same condition.
PCA9634
NXP Semiconductors
8-bit Fm+ I2C-bus LED driver
2. Features and benefits
8 LED drivers. Each output programmable at:
Off
On
Programmable LED brightness
Programmable group dimming/blinking mixed with individual LED brightness
1 MHz Fast-mode Plus compatible I2C-bus interface with 30 mA high drive capability
on SDA output for driving high capacitive buses
256-step (8-bit) linear programmable brightness per LED output varying from fully off
(default) to maximum brightness using a 97 kHz PWM signal
256-step group brightness control allows general dimming (using a 190 Hz PWM
signal) from fully off to maximum brightness (default)
256-step group blinking with frequency programmable from 24 Hz to 10.73 s and duty
cycle from 0 % to 99.6 %
Eight totem-pole outputs (sink 25 mA and source 10 mA at 5 V) with software
programmable open-drain LED outputs selection (default at totem-pole). No input
function.
Output state change programmable on the Acknowledge or the STOP Command to
update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).
Active LOW Output Enable (OE) input pin. LED outputs programmable to 1 (default at
power-up), 0 or ‘high-impedance’ when OE is HIGH, thus allowing hardware blinking
and dimming of the LEDs.
7 hardware address pins allow 126 devices to be connected to the same I2C-bus
4 software programmable I2C-bus addresses (one LED Group Call address and three
LED Sub Call addresses) allow groups of devices to be addressed at the same time in
any combination (for example, one register used for ‘All Call’ so that all the PCA9634s
on the I2C-bus can be addressed at the same time and the second register used for
three different addresses so that 13 of all devices on the bus can be addressed at the
same time in a group). Software enable and disable for I2C-bus address.
Software Reset feature (SWRST Call) allows the device to be reset through the
I2C-bus
25 MHz internal oscillator requires no external components
Internal power-on reset
Noise filter on SDA/SCL inputs
Edge rate control on outputs
No glitch on power-up
Supports hot insertion
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
5.5 V tolerant inputs
40 C to +85 C operation
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO20, TSSOP20, HVQFN20
PCA9634
Product data sheet
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Rev. 7.1 — 18 December 2017
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PCA9634
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8-bit Fm+ I2C-bus LED driver
3. Applications
RGB or RGBA LED drivers
LED status information
LED displays
LCD backlights
Keypad backlights for cellular phones or handheld devices
4. Ordering information
Table 1.
Ordering information
Type number
Topside
mark
Package
Description
Version
PCA9634D
PCA9634D SO20
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
PCA9634PW
PCA9634
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
PCA9634BS
9634
HVQFN20
plastic thermal enhanced very thin quad flat package; no leads; SOT662-1
20 terminals; body 5 5 0.85 mm
Name
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order
quantity
Temperature range
PCA9634D
PCA9634D,118
SO20
Reel 13” Q1/T1
*Standard mark SMD
2000
Tamb = 40 C to +85 C
PCA9634PW
PCA9634PW,118
TSSOP20
Reel 13” Q1/T1
*Standard mark SMD
2500
Tamb = 40 C to +85 C
PCA9634BS
PCA9634BS,118
HVQFN20
Reel 13” Q1/T1
*Standard mark SMD
6000
Tamb = 40 C to +85 C
PCA9634
Product data sheet
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PCA9634
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8-bit Fm+ I2C-bus LED driver
5. Block diagram
A0
A1
A2
A3
A4
A5
A6
PCA9634
SCL
INPUT FILTER
SDA
I2C-BUS
CONTROL
POWER-ON
RESET
VDD
VDD
VSS
LED
STATE
SELECT
REGISTER
PWM
REGISTER X
BRIGHTNESS
CONTROL
97 kHz
24.3 kHz
25 MHz
OSCILLATOR
LEDn
GRPFREQ
REGISTER
MUX/
CONTROL
GRPPWM
REGISTER
190 Hz
'0' – permanently OFF
'1' – permanently ON
OE
002aac135
Remark: Only one LED output shown for clarity.
Fig 1.
Block diagram of PCA9634
PCA9634
Product data sheet
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PCA9634
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8-bit Fm+ I2C-bus LED driver
6. Pinning information
6.1 Pinning
A0
1
20 VDD
A0
1
20 VDD
A1
2
19 SDA
A1
2
19 SDA
A2
3
18 SCL
A2
3
18 SCL
A3
4
17 A6
A3
4
17 A6
A4
5
16 A5
A4
5
LED0
6
15 OE
LED0
6
LED1
7
14 LED7
LED1
7
14 LED7
LED2
8
13 LED6
LED2
8
13 LED6
LED3
9
12 LED5
LED3
9
12 LED5
VSS 10
11 LED4
VSS 10
11 LED4
PCA9634D
PCA9634PW
002aac131
15 OE
002aac132
Pin configuration for TSSOP20
16 SCL
17 SDA
18 VDD
20 A1
terminal 1
index area
Fig 3.
19 A0
Pin configuration for SO20
A2
1
A3
2
15 A6
A4
3
LED0
4
12 LED7
LED1
5
11 LED6
14 A5
7
8
9
LED3
VSS
LED4
13 OE
LED5 10
6
PCA9634BS
LED2
Fig 2.
16 A5
002aac133
Transparent top view
Fig 4.
PCA9634
Product data sheet
Pin configuration for HVQFN20
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PCA9634
NXP Semiconductors
8-bit Fm+ I2C-bus LED driver
6.2 Pin description
Table 3.
Symbol
Product data sheet
Pin
Type
Description
SO20, TSSOP20
HVQFN20
A0
1
19
I
address input 0
A1
2
20
I
address input 1
A2
3
1
I
address input 2
A3
4
2
I
address input 3
A4
5
3
I
address input 4
LED0
6
4
O
LED driver 0
LED1
7
5
O
LED driver 1
LED2
8
6
O
LED driver 2
LED3
9
7
O
LED driver 3
VSS
10
8[1]
power supply
supply ground
LED4
11
9
O
LED driver 4
LED5
12
10
O
LED driver 5
LED6
13
11
O
LED driver 6
LED7
14
12
O
LED driver 7
OE
15
13
I
active LOW output enable
A5
16
14
I
address input 5
A6
17
15
I
address input 6
SCL
18
16
I
serial clock line
SDA
19
17
I/O
serial data line
VDD
20
18
power supply
supply voltage
[1]
PCA9634
Pin description
HVQFN20 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
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PCA9634
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8-bit Fm+ I2C-bus LED driver
7. Functional description
Refer to Figure 1 “Block diagram of PCA9634”.
7.1 Device addresses
Following a START condition, the bus master must output the address of the slave it is
accessing.
There are a maximum of 128 possible programmable addresses using the 7 hardware
address pins. Two of these addresses, Software Reset and LED All Call, cannot be used
because their default power-up state is ON, leaving a maximum of 126 addresses. Using
other reserved addresses, as well as any other Sub Call address, will reduce the total
number of possible addresses even further.
7.1.1 Regular I2C-bus slave address
The I2C-bus slave address of the PCA9634 is shown in Figure 5. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
Remark: Using reserved I2C-bus addresses will interfere with other devices, but only if
the devices are on the bus and/or the bus will be open to other I2C-bus systems at some
later date. In a closed system where the designer controls the address assignment these
addresses can be used since the PCA9634 treats them like any other address. The
LED All Call, Software Rest and PCA9564 or PCA9665 slave address (if on the bus) can
never be used for individual device addresses.
• PCA9634 LED All Call address (1110 000) and Software Reset (0000 0110) which are
active on start-up
• PCA9564 (0000 000) or PCA9665 (1110 000) slave address which is active on
start-up
•
•
•
•
‘reserved for future use’ I2C-bus addresses (0000 011, 1111 1XX)
slave devices that use the 10-bit addressing scheme (1111 0XX)
slave devices that are designed to respond to the General Call address (0000 000)
High-speed mode (Hs-mode) master code (0000 1XX).
slave address
A6
A5
A4
A3
A2
A1
hardware selectable
Fig 5.
A0 R/W
002aab319
Slave address
The last bit of the address byte defines the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
PCA9634
Product data sheet
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PCA9634
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8-bit Fm+ I2C-bus LED driver
7.1.2 LED All Call I2C-bus address
• Default power-up value (ALLCALLADR register): E0h or 1110 000X
• Programmable through I2C-bus (volatile programming)
• At power-up, LED All Call I2C-bus address is enabled. PCA9634 sends an ACK when
E0h (R/W = 0) or E1h (R/W = 1) is sent by the master.
See Section 7.3.8 “ALLCALLADR: LED All Call I2C-bus address” for more detail.
Remark: The default LED All Call I2C-bus address (E0h or 1110 000X) must not be used
as a regular I2C-bus slave address since this address is enabled at power-up. All the
PCA9634s on the I2C-bus will acknowledge the address if sent by the I2C-bus master.
7.1.3 LED Sub Call I2C-bus addresses
• 3 different I2C-bus addresses can be used
• Default power-up values:
– SUBADR1 register: E2h or 1110 001X
– SUBADR2 register: E4h or 1110 010X
– SUBADR3 register: E8h or 1110 100X
• Programmable through I2C-bus (volatile programming)
• At power-up, Sub Call I2C-bus addresses are disabled. PCA9634 does not send an
ACK when E2h (R/W = 0) or E3h (R/W = 1), E4h (R/W = 0) or E5h (R/W = 1), or
E8h (R/W = 0) or E9h (R/W = 1) is sent by the master.
See Section 7.3.7 “SUBADR1 to SUBADR3: I2C-bus subaddress 1 to 3” for more detail.
Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus
slave addresses as long as they are disabled.
7.1.4 Software Reset I2C-bus address
The address shown in Figure 6 is used when a reset of the PCA9634 needs to be
performed by the master. The Software Reset address (SWRST Call) must be used with
R/W = 0. If R/W = 1, the PCA9634 does not acknowledge the SWRST. See Section 7.6
“Software Reset” for more detail.
R/W
0
0
0
0
0
1
1
0
002aab416
Fig 6.
Software Reset address
Remark: The Software Reset I2C-bus address is a reserved address and cannot be used
as a regular I2C-bus slave address or as an LED All Call or LED Sub Call address.
PCA9634
Product data sheet
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PCA9634
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8-bit Fm+ I2C-bus LED driver
7.2 Control register
Following the successful acknowledgement of the slave address, LED All Call address or
LED Sub Call address, the bus master will send a byte to the PCA9634, which will be
stored in the Control register.
The lowest 5 bits are used as a pointer to determine which register will be accessed
(D[4:0]). The highest 3 bits are used as Auto-Increment flag and Auto-Increment options
(AI[2:0]).
register address
AI2 AI1 AI0
D4
D3
D2
D1
D0
002aac140
Auto-Increment options
Auto-Increment flag
reset state = 80h
Remark: The Control register does not apply to the Software Reset I2C-bus address.
Fig 7.
Control register
When the Auto-Increment flag is set (AI2 = 1), the five low order bits of the Control register
are automatically incremented after a read or write. This allows the user to program the
registers sequentially. Four different types of Auto-Increment are possible, depending on
AI1 and AI0 values.
Table 4.
Auto-Increment options
AI2
AI1
AI0
Function
0
0
0
no Auto-Increment
1
0
0
Auto-Increment for all registers. D[4:0] roll over to ‘0 0000’ after the last
register (1 0001) is accessed.
1
0
1
Auto-Increment for individual brightness registers only. D[4:0] roll over to
‘0 0010’ after the last register (0 1001) is accessed.
1
1
0
Auto-Increment for global control registers only. D[4:0] roll over to
‘0 1010’ after the last register (0 1011) is accessed.
1
1
1
Auto-Increment for individual and global control registers only. D[4:0] roll
over to ‘0 0010’ after the last register (0 1011) is accessed.
Remark: Other combinations not shown in Table 4 (AI[2:0] = 001, 010, and 011) are
reserved and must not be used for proper device operation.
AI[2:0] = 000 is used when the same register must be accessed several times during a
single I2C-bus communication, for example, changes the brightness of a single LED. Data
is overwritten each time the register is accessed during a write operation.
AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example,
power-up programming.
AI[2:0] = 101 is used when the four LED drivers must be individually programmed with
different values during the same I2C-bus communication, for example, changing color
setting to another color setting.
PCA9634
Product data sheet
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PCA9634
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8-bit Fm+ I2C-bus LED driver
AI[2:0] = 110 is used when the LED drivers must be globally programmed with different
settings during the same I2C-bus communication, for example, global brightness or
blinking change.
AI[2:0] = 111 is used when individual and global changes must be performed during the
same I2C-bus communication, for example, changing a color and global brightness at the
same time.
Only the 5 least significant bits D[4:0] are affected by the AI[2:0] bits.
When the Control register is written, the register entry point determined by D[4:0] is the
first register that will be addressed (read or write operation), and can be anywhere
between 0 0000 and 1 0001 (as defined in Table 5). When AI[2] = 1, the Auto-Increment
flag is set and the rollover value at which the register increment stops and goes to the next
one is determined by AI[2:0]. See Table 4 for rollover values. For example, if the Control
register = 1110 1100 (ECh), then the register addressing sequence will be (in hex):
0C … 11 00 … 0B 02 … 0B 02 … 0B 02 … as long
as the master keeps sending or reading data.
7.3 Register definitions
Table 5.
Register summary
Only D[4:0] = 0 0000 to 1 0001 are allowed and will be acknowledged.
D[4:0] = 1 0010 to 1 1111 are reserved and will not be acknowledged.
Register number (hex)
D4
D3
D2
D1
D0
Name
Type
Function
00
0
0
0
0
0
MODE1
read/write
Mode register 1
01
0
0
0
0
1
MODE2
read/write
Mode register 2
02
0
0
0
1
0
PWM0
read/write
brightness control LED0
03
0
0
0
1
1
PWM1
read/write
brightness control LED1
04
0
0
1
0
0
PWM2
read/write
brightness control LED2
05
0
0
1
0
1
PWM3
read/write
brightness control LED3
06
0
0
1
1
0
PWM4
read/write
brightness control LED4
07
0
0
1
1
1
PWM5
read/write
brightness control LED5
08
0
1
0
0
0
PWM6
read/write
brightness control LED6
09
0
1
0
0
1
PWM7
read/write
brightness control LED7
0A
0
1
0
1
0
GRPPWM
read/write
group duty cycle control
0B
0
1
0
1
1
GRPFREQ
read/write
group frequency
0C
0
1
1
0
0
LEDOUT0
read/write
LED output state 0
0D
0
1
1
0
1
LEDOUT1
read/write
LED output state 1
0E
0
1
1
1
0
SUBADR1
read/write
I2C-bus subaddress 1
0F
0
1
1
1
1
SUBADR2
read/write
I2C-bus subaddress 2
10
1
0
0
0
0
SUBADR3
read/write
I2C-bus subaddress 3
11
1
0
0
0
1
ALLCALLADR
read/write
LED All Call I2C-bus address
PCA9634
Product data sheet
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PCA9634
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8-bit Fm+ I2C-bus LED driver
7.3.1 Mode register 1, MODE1
Table 6.
MODE1 - Mode register 1 (address 00h) bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
AI2
read only
0
register Auto-Increment disabled
1*
register Auto-Increment enabled
Auto-Increment bit 1 = 0
6
AI1
read only
0*
1
Auto-Increment bit 1 = 1
5
AI0
read only
0*
Auto-Increment bit 0 = 0
1
Auto-Increment bit 0 = 1
0
Normal mode[1]
1*
Low power mode; oscillator off[2]
0*
PCA9634 does not respond to I2C-bus subaddress 1
1
PCA9634 responds to I2C-bus subaddress 1
0*
PCA9634 does not respond to I2C-bus subaddress 2
1
PCA9634 responds to I2C-bus subaddress 2
0*
PCA9634 does not respond to I2C-bus subaddress 3
1
PCA9634 responds to I2C-bus subaddress 3
0
PCA9634 does not respond to LED All Call I2C-bus address
1*
PCA9634 responds to LED All Call I2C-bus address
4
SLEEP
3
SUB1
2
R/W
SUB2
1
R/W
SUB3
0
R/W
R/W
ALLCALL
R/W
[1]
It takes 500 s max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not
guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 s window.
[2]
When the oscillator is off (Sleep mode) the LED outputs cannot be turned on, off or dimmed/blinked.
7.3.2 Mode register 2, MODE2
Table 7.
MODE2 - Mode register 2 (address 01h) bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
-
read only
0*
reserved
6
-
read only
0*
reserved
5
DMBLNK
R/W
0*
Group control = dimming
1
Group control = blinking
4
INVRT[1]
0*
output logic state not inverted; value to use when no external driver used;
applicable when OE = 0
1
output logic state inverted; value to use when external driver used;
applicable when OE = 0
outputs change on STOP command[2]
R/W
3
OCH
R/W
0*
1
outputs change on ACK
2
OUTDRV[1]
R/W
0
the 8 LED outputs are configured with an open-drain structure
1*
the 8 LED outputs are configured with a totem-pole structure
PCA9634
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8-bit Fm+ I2C-bus LED driver
Table 7.
MODE2 - Mode register 2 (address 01h) bit description …continued
Legend: * default value.
Bit
Symbol
Access
Value
Description
1 to 0
OUTNE[1:0][3]
R/W
00
when OE = 1 (output drivers not enabled), LEDn = 0
01*
when OE = 1 (output drivers not enabled):
LEDn = 1 when OUTDRV = 1
LEDn = high-impedance when OUTDRV = 0 (same as OUTNE[1:0] = 10)
10
when OE = 1 (output drivers not enabled), LEDn = high-impedance
11
reserved
[1]
See Section 7.7 “Using the PCA9634 with and without external drivers” for more details. Normal LEDs can be driven directly in either
mode. Some newer LEDs include integrated Zener diodes to limit voltage transients, reduce EMI and protect the LEDs, and these must
be driven only in the open-drain mode to prevent overheating the IC.
[2]
Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9634. Applicable to registers from
02h (PWM0) to 0Dh (LEDOUT) only.
[3]
See Section 7.4 “Active LOW output enable input” for more details.
7.3.3 PWM0 to PWM7: Individual brightness control
Table 8.
PWM0 to PWM7 - PWM registers 0 to 7 (address 02h to 09h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access Value
Description
02h
PWM0
7:0
IDC0[7:0]
R/W
0000 0000* PWM0 Individual Duty Cycle
03h
PWM1
7:0
IDC1[7:0]
R/W
0000 0000* PWM1 Individual Duty Cycle
04h
PWM2
7:0
IDC2[7:0]
R/W
0000 0000* PWM2 Individual Duty Cycle
05h
PWM3
7:0
IDC3[7:0]
R/W
0000 0000* PWM3 Individual Duty Cycle
06h
PWM4
7:0
IDC4[7:0]
R/W
0000 0000* PWM4 Individual Duty Cycle
07h
PWM5
7:0
IDC5[7:0]
R/W
0000 0000* PWM5 Individual Duty Cycle
08h
PWM6
7:0
IDC6[7:0]
R/W
0000 0000* PWM6 Individual Duty Cycle
09h
PWM7
7:0
IDC7[7:0]
R/W
0000 0000* PWM7 Individual Duty Cycle
A 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through
256 linear steps from 00h (0 % duty cycle = LED output off) to FFh
(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs
programmed with LDRx = 10 or 11 (LEDOUT0 and LEDOUT1 registers).
IDC 7:0
duty cycle = -----------------------256
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8-bit Fm+ I2C-bus LED driver
7.3.4 GRPPWM: Group duty cycle control
Table 9.
GRPPWM - Group duty cycle control register (address 0Ah) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
0Ah
GRPPWM
7:0
GDC[7:0]
R/W
1111 1111
GRPPWM register
When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz fixed frequency
signal is superimposed with the 97 kHz individual brightness control signal. GRPPWM is
then used as a global brightness control allowing the LED outputs to be dimmed with the
same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the 8 outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 and LEDOUT1
registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers
define a global blinking pattern, where GRPFREQ contains the blinking period (from
24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
7:0
duty cycle = GDC
-------------------------256
(2)
7.3.5 GRPFREQ: Group frequency
Table 10. GRPFREQ - Group Frequency register (address 0Bh) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
0Bh
GRPFREQ
7:0
GFRQ[7:0]
R/W
0000 0000*
GRPFREQ register
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 and LEDOUT1
registers).
Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)
to FFh (10.73 s).
GFRQ 7:0 + 1
global blinking period = ---------------------------------------- in sec onds
24
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7.3.6 LEDOUT0 and LEDOUT1: LED driver output state
Table 11.
LEDOUT0 and LEDOUT1- LED driver output state registers (address 0Ch and
0Dh) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
0Ch
LEDOUT0
7:6
LDR3
R/W
00*
LED3 output state control
5:4
LDR2
R/W
00*
LED2 output state control
3:2
LDR1
R/W
00*
LED1 output state control
1:0
LDR0
R/W
00*
LED0 output state control
7:6
LDR7
R/W
00*
LED7 output state control
5:4
LDR6
R/W
00*
LED6 output state control
3:2
LDR5
R/W
00*
LED5 output state control
1:0
LDR4
R/W
00*
LED4 output state control
0Dh
LEDOUT1
LDRx = 00 — LED driver x is off (default power-up state).
LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking
not controlled).
LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx
register.
LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be
controlled through its PWMx register and the GRPPWM registers.
7.3.7 SUBADR1 to SUBADR3: I2C-bus subaddress 1 to 3
SUBADR1 to SUBADR3 - I2C-bus subaddress registers 1 to 3 (address 0Eh to
10h) bit description
Legend: * default value.
Table 12.
Address
Register
Bit
Symbol
Access Value
Description
0Eh
SUBADR1
7:1
A1[7:1]
R/W
1110 001*
I2C-bus subaddress 1
0
A1[0]
R only
0*
reserved
A2[7:1]
R/W
1110 010*
I2C-bus subaddress 2
0Fh
SUBADR2
7:1
0
A2[0]
R only
0*
reserved
10h
SUBADR3
7:1
A3[7:1]
R/W
1110 100*
I2C-bus subaddress 3
0
A3[0]
R only
0*
reserved
Subaddresses are programmable through the I2C-bus. Default power-up values are E2h,
E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up
(the corresponding SUBx bit in MODE1 register is equal to 0).
Once subaddresses have been programmed to their right values, SUBx bits need to be
set to 1 in order to have the device acknowledging these addresses (MODE1 register).
Only the 7 MSBs representing the I2C-bus subaddress are valid. The LSB in SUBADRx
register is a read-only bit (0).
When SUBx is set to 1, the corresponding I2C-bus subaddress can be used during either
an I2C-bus read or write sequence.
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7.3.8 ALLCALLADR: LED All Call I2C-bus address
ALLCALLADR - LED All Call I2C-bus address register (address 11h) bit
description
Legend: * default value.
Table 13.
Address
Register
Bit
Symbol
Access Value
Description
11h
ALLCALLADR
7:1
AC[7:1]
R/W
1110 000*
ALLCALL I2C-bus
address register
0
AC[0]
R only
0*
reserved
The LED All Call I2C-bus address allows all the PCA9634s on the bus to be programmed
at the same time (ALLCALL bit in register MODE1 must be equal to 1 (power-up default
state)). This address is programmable through the I2C-bus and can be used during either
an I2C-bus read or write sequence. The register address can also be programmed as a
Sub Call.
Only the 7 MSBs representing the All Call I2C-bus address are valid. The LSB in
ALLCALLADR register is a read-only bit (0).
If ALLCALL bit = 0, the device does not acknowledge the address programmed in register
ALLCALLADR.
7.4 Active LOW output enable input
The active LOW output enable (OE) pin, allows to enable or disable all the LED outputs at
the same time.
• When a LOW level is applied to OE pin, all the LED outputs are enabled and follow
the output state defined in the LEDOUT register with the polarity defined by INVRT bit
(MODE2 register).
• When a HIGH level is applied to OE pin, all the LED outputs are programmed to the
value that is defined by OUTNE[1:0] in the MODE2 register.
Table 14.
LED outputs when OE = 1
OUTNE1
OUTNE0
LED outputs
0
0
0
0
1
1 if OUTDRV = 1, high-impedance if OUTDRV = 0
1
0
high-impedance
1
1
reserved
The OE pin can be used as a synchronization signal to switch on/off several PCA9634
devices at the same time. This requires an external clock reference that provides blinking
period and the duty cycle.
The OE pin can also be used as an external dimming control signal. The frequency of the
external clock must be high enough not to be seen by the human eye, and the duty cycle
value determines the brightness of the LEDs.
Remark: Do not use OE as an external blinking control signal when internal global
blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an undefined
blinking pattern. Do not use OE as an external dimming control signal when internal global
dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an undefined
dimming pattern.
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7.5 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCA9634 in a reset
condition until VDD has reached VPOR. At this point, the reset condition is released and the
PCA9634 registers and I2C-bus state machine are initialized to their default states (all
zeroes) causing all the channels to be deselected. Thereafter, VDD must be lowered below
0.2 V to reset the device.
7.6 Software Reset
The Software Reset Call (SWRST Call) allows all the devices in the I2C-bus to be reset to
the power-up state value through a specific formatted I2C-bus command. To be performed
correctly, it implies that the I2C-bus is functional and that there is no device hanging the
bus.
The SWRST Call function is defined as the following:
1. A START command is sent by the I2C-bus master.
2. The reserved SWRST I2C-bus address ‘0000 011’ with the R/W bit set to ‘0’ (write) is
sent by the I2C-bus master.
3. The PCA9634 device(s) acknowledge(s) after seeing the SWRST Call address
‘0000 0110’ (06h) only. If the R/W bit is set to ‘1’ (read), no acknowledge is returned to
the I2C-bus master.
4. Once the SWRST Call address has been sent and acknowledged, the master sends
2 bytes with 2 specific values (SWRST data byte 1 and byte 2):
a. Byte 1 = A5h: the PCA9634 acknowledges this value only. If byte 1 is not equal to
A5h, the PCA9634 does not acknowledge it.
b. Byte 2 = 5Ah: the PCA9634 acknowledges this value only. If byte 2 is not equal to
5Ah, then the PCA9634 does not acknowledge it.
If more than 2 bytes of data are sent, the PCA9634 does not acknowledge any more.
5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and
correctly acknowledged, the master sends a STOP command to end the
SWRST Call: the PCA9634 then resets to the default value (power-up value) and is
ready to be addressed again within the specified bus free time (tBUF).
The I2C-bus master must interpret a non-acknowledge from the PCA9634 (at any time) as
a ‘SWRST Call Abort’. The PCA9634 does not initiate a reset of its registers. This
happens only when the format of the SWRST Call sequence is not correct.
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7.7 Using the PCA9634 with and without external drivers
The PCA9634 LED output drivers are 5.5 V only tolerant and can sink up to 25 mA at 5 V.
If the device needs to drive LEDs to a higher voltage and/or higher current, use of an
external driver is required.
• INVRT bit (MODE2 register) can be used to keep the LED PWM control firmware the
same (PWMx and GRPPWM values directly calculated from their respective formulas
and the LED output state determined by LEDOUT register value) independently of the
type of external driver. This bit allows LED output polarity inversion/non-inversion only
when OE = 0.
• OUTDRV bit (MODE2 register) allows minimizing the amount of external components
required to control the external driver (N-type or P-type device).
Table 15. Use of INVRT and OUTDRV based on connection to the LEDn outputs when OE = 0
When OE = 1, LED output state is controlled only by OUTNE[1:0] bits (MODE2 register).
INVRT OUTDRV Direct connection to LEDn
Firmware
External
pull-up
resistor
External N-type driver
External P-type driver
Firmware
Firmware
External
pull-up
resistor
External
pull-up
resistor
0
0
formulas and LED
output state values
apply[1]
LED current formulas and LED required
limiting R[1] output state
values inverted
formulas and LED required
output state values
apply
0
1
formulas and LED
output state values
apply[1]
LED current formulas and LED not required formulas and LED not
limiting R[1] output state
output state values required[2]
values inverted
apply[2]
1
0
formulas and LED
output state values
inverted
LED current formulas and LED required
limiting R
output state
values apply
formulas and LED required
output state values
inverted
1
1
formulas and LED
output state values
inverted
LED current formulas and LED not
limiting R
output state
required[3]
values apply[3]
formulas and LED not required
output state values
inverted
[1]
Correct configuration when LEDs directly connected to the LEDn outputs (connection to VDD through current limiting resistor).
[2]
Optimum configuration when external P-type (PNP, PMOS) driver used.
[3]
Optimum configuration when external N-type (NPN, NMOS) driver used.
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Table 16. Output transistors based on LEDOUT registers, INVRT and OUTDRV bits when OE = 0
When OE = 1, LED output state is controlled only by OUTNE[1:0] bits (MODE2 register).
LEDOUT
INVRT
OUTDRV
Upper transistor Lower transistor
(VDD to LEDn)
(LEDn to VSS)
LEDn state
00
0
0
off
off
high-Z[1]
LED driver off
0
1
on
off
VDD
1
0
off
on
VSS
1
1
off
on
VSS
01
0
0
off
on
VSS
LED driver on
0
1
off
on
VSS
1
0
off
off
high-Z[1]
1
1
on
off
VDD
10
0
0
off
VSS or high-Z[1] = PWMx value
Individual
brightness
control
Individual PWM
(non-inverted)
0
1
Individual PWM
(non-inverted)
Individual PWM
(non-inverted)
VSS or VDD = PWMx value
1
0
off
Individual PWM
(inverted)
high-Z[1] or VSS = 1 PWMx value
1
1
Individual PWM
(inverted)
Individual PWM
(inverted)
VDD or VSS = 1 PWMx value
0
0
off
Individual +
Group
dimming/blinking 0
Individual + Group VSS or high-Z[1] = PWMx or GRPPWM
values
PWM
(non-inverted)
1
Individual PWM
(non-inverted)
Individual PWM
(non-inverted)
1
0
off
Individual + Group high-Z[1] or VSS = (1 PWMx) or
(1 GRPPWM) values
PWM (inverted)
1
1
Individual PWM
(inverted)
Individual PWM
(inverted)
11
[1]
VSS or VDD = PWMx or GRPPWM values
VDD or VSS = (1 PWMx) or
(1 GRPPWM) values
External pull-up or LED current limiting resistor connects LEDn to VDD.
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7.8 Individual brightness control with group dimming/blinking
A 97 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used
to control individually the brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be
applied to the 4 LED outputs):
• A lower 190 Hz fixed frequency signal with programmable duty cycle (8 bits,
256 steps) is used to provide a global brightness control.
• A programmable frequency signal from 24 Hz to 110.73 Hz (8 bits, 256 steps) with
programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking
control.
1
2
3
4
5
6
7
8
9 10 11 12
507
508
509
510
511
512
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9 10 11
Brightness Control signal (LEDn)
N × 40 ns
with N = (0 to 255)
(PWMx Register)
M × 256 × 2 × 40 ns
with M = (0 to 255)
(GRPPWM Register)
256 × 40 ns = 10.24 μs
(97.6 kHz)
Group Dimming signal
256 × 2 × 256 × 40 ns = 5.24 ms (190.7 Hz)
1
2
3
4
5
6
7
8
resulting Brightness + Group Dimming signal
002aab417
Minimum pulse width for LEDn Brightness Control is 40 ns.
Minimum pulse width for Group Dimming is 20.48 s.
When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal will have 2 pulses of
the LED Brightness Control signal (pulse width = N 40 ns, with ‘N’ defined in PWMx register).
This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 4 (8 pulses).
Fig 8.
Brightness + Group Dimming signals
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8. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 9).
SDA
SCL
data line
stable;
data valid
Fig 9.
change
of data
allowed
mba607
Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 10).
SDA
SCL
S
P
START condition
STOP condition
mba608
Fig 10. Definition of START and STOP conditions
8.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 11).
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SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I2C-BUS
MULTIPLEXER
SLAVE
002aaa966
Fig 11. System configuration
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master
1
2
S
START
condition
8
9
clock pulse for
acknowledgement
002aaa987
Fig 12. Acknowledgement on the I2C-bus
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8-bit Fm+ I2C-bus LED driver
9. Bus transactions
slave address
data for register D[4:0](1)
control register
S A6 A5 A4 A3 A2 A1 A0 0
START condition
A
X
X
X D4 D3 D2 D1 D0 A
Auto-Increment options
Auto-Increment flag
R/W
A
acknowledge
from slave
P
acknowledge
from slave
acknowledge
from slave
STOP
condition
002aac141
(1) See Table 5 for register definition.
Fig 13. Write to a specific register
slave address
control register
S A6 A5 A4 A3 A2 A1 A0 0
START condition
A
1
0
0
0
0
0
acknowledge
from slave
0
0
MODE1
register
selection
Auto-Increment
on all registers
R/W
MODE1 register
MODE2 register
A
acknowledge
from slave
A
A
acknowledge
from slave
acknowledge
from slave
(cont.)
Auto-Increment on
SUBADR3 register
ALLCALLADR register
(cont.)
A
A
acknowledge
from slave
acknowledge
from slave
P
STOP
condition
002aac142
Fig 14. Write to all registers using the Auto-Increment feature
slave address
control register
S A6 A5 A4 A3 A2 A1 A0 0
START condition
A
R/W
acknowledge
from slave
1
0
1
0
0
0
PWM0 register
1
0
PWM0
register
selection
increment
on Individual
brightness
registers only
PWM1 register
A
acknowledge
from slave
A
A
acknowledge
from slave
acknowledge
from slave
(cont.)
Auto-Increment on
PWM6 register
(cont.)
PWM7 register
PWM0 register
PWMx register
A
A
A
A
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
P
STOP
condition
002aac143
Fig 15. Multiple writes to Individual Brightness registers only using the Auto-Increment feature
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slave address
ReSTART
condition
control register
S A6 A5 A4 A3 A2 A1 A0 0
START condition
A
1
0
0
0
Auto-Increment
on all registers
R/W
acknowledge
from slave
data from MODE2 register
(cont.)
0
0
0
0
MODE1
register
selection
slave address
data from MODE1 register
A Sr A6 A5 A4 A3 A2 A1 A0 1
R/W
acknowledge
from slave
acknowledge
from master
acknowledge
from slave
Auto-Increment on
data from
ALLCALLADR register
data from PWM0
A (cont.)
A
data from
MODE1 register
A
A
A
acknowledge
from master
acknowledge
from master
acknowledge
from master
A (cont.)
acknowledge
from master
data from last read byte
(cont.)
A
not acknowledge
from master
P
STOP
condition
002aac144
Fig 16. Read all registers using the Auto-Increment feature
slave address(1)
new LED All Call I2C address(2)
control register
sequence (A) S A6 A5 A4 A3 A2 A1 A0 0
START condition
A
R/W
acknowledge
from slave
X
X
X
1
0
0
0
1
A
1
0
1
0
1
ALLCALLADR
register selection acknowledge
from slave
Auto-Increment on
0
1
X
A
P
acknowledge
from slave
STOP
condition
the 16 LEDs are on at the acknowledge(3)
LED All Call I2C address
sequence (B) S
1
0
1
0
START condition
1
0
1
control register
0
A
X
X
X
R/W
acknowledge
from the
4 devices
0
1
0
LEDOUT register (LED fully ON)
0
0
A
0
1
0
1
0
LEDOUT
register selection acknowledge
from the
4 devices
1
0
1
A
P
acknowledge
from the
4 devices
STOP
condition
002aac145
(1) In this example, several PCA9634s are used and the same sequence (A) (above) is sent to each of them.
(2) ALLCALL bit in MODE1 register is equal to 1 for this example.
(3) OCH bit in MODE2 register is equal to 1 for this example.
Fig 17. LED All Call I2C-bus address programming and LED All Call sequence example
PCA9634
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8-bit Fm+ I2C-bus LED driver
10. Application design-in information
5V
12 V
5V
12 V
VDD = 2.5 V, 3.3 V or 5.0 V
10 kΩ
I2C-BUS/SMBus
MASTER
SDA
10 kΩ
10 kΩ(1)
VDD
SDA
SCL
SCL
OE
OE
LED0
LED1
LED2
LED3
PCA9634
A0
A1
A2
A3
LED4
A4
A5
LED5
A6
LED6
VSS
LED7
002aac137
I2C-bus address = 0010 101X.
All of the 8 LEDn outputs configurable as either open-drain or totem pole. Mixing of configurations is not possible.
(1) OE requires pull-up resistor if control signal from the master is open-drain.
Fig 18. Typical application
Question 1: What kind of edge rate control is there on the outputs?
• The typical edge rates depend on the output configuration, supply voltage, and the
applied load. The outputs can be configured as either open-drain NMOS or
totem-pole outputs. If the customer is using the part to directly drive LEDs, they
should be using it in an open-drain NMOS, if they are concerned about the maximum
ISS and ground bounce. The edge rate control was designed primarily to slow down
the turn-on of the output device; it turns off rather quickly (~1.5 ns). In simulation, the
typical turn-on time for the open-drain NMOS was ~14 ns (VDD = 3.6 V; CL = 50 pF;
RPU = 500 ).
Question 2: Is ground bounce possible?
• Ground bounce is a possibility, especially if all 16 outputs are changed at full current
(25 mA each). There is a fair amount of decoupling capacitance on chip (~50 pF),
which is intended to suppress some of the ground bounce. The customer will need to
determine if additional decoupling capacitance externally placed as close as
physically possible to the device is required.
PCA9634
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8-bit Fm+ I2C-bus LED driver
Question 3: Can I really sink 400 mA through the single ground pin on the package and
will this cause any ground bounce problem due to the PWM of the LEDs?
• Yes, you can sink 400 mA through a single ground pin on the package. Although the
package only has one ground pin, there are two ground pads on the die itself
connected to this one pin. Although some ground bounce is likely, it will not disrupt the
operation of the part and would be reduced by the external decoupling capacitance.
Question 4: I can’t turn the LEDs on or off, but their registers are set properly. Why?
• Check the Mode Register 1 bit 4 SLEEP setting. The value needs to be 0 so that the
OSC is turn on. If the OSC is turned off, the LEDs cannot be turned on or off and also
can’t be dimmed or blinked.
Question 5: I’m using LEDs with integrated Zener diodes and the IC is getting very hot.
Why?
• The IC outputs can be set to either open-drain or push-pull and default to push-pull
outputs. In this application with the Zener diodes, they need to be set to open-drain
since in the push-pull architecture there is a low resistance path to ground through the
Zener and this is causing the IC to overheat. The PCA9632/33/34/35 ICs all power-up
in the push-pull output mode and with the logic state HIGH, so one of the first things
that need to be done is to set the outputs to open-drain.
11. Limiting values
Table 17. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
PCA9634
Product data sheet
Symbol
Parameter
Conditions
VDD
supply voltage
Min
Max
Unit
0.5
+6.0
V
VI/O
voltage on an input/output pin
VSS 0.5
5.5
V
IO(LEDn)
output current on pin LEDn
-
25
mA
ISS
ground supply current
-
200
mA
Ptot
total power dissipation
-
400
mW
Tstg
storage temperature
65
+150
C
Tamb
ambient temperature
40
+85
C
Tj
junction temperature
40
+125
C
operating
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12. Static characteristics
Table 18. Static characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.3
-
5.5
V
Operating mode; VDD = 2.3 V;
no load; fSCL = 1 MHz
-
2.5
10
mA
Operating mode; VDD = 3.3 V;
no load; fSCL = 1 MHz
-
2.5
10
mA
Operating mode; VDD = 5.5 V;
no load; fSCL = 1 MHz
-
2.5
10
mA
VDD = 2.3 V; no load; fSCL = 0 Hz;
I/O = inputs; VI = VDD
-
2.3
11
A
VDD = 3.3 V; no load; fSCL = 0 Hz;
I/O = inputs; VI = VDD
-
2.9
12
A
VDD = 5.5 V; no load; fSCL = 0 Hz;
I/O = inputs; VI = VDD
-
3.8
15.5
A
-
1.5
2.0
V
Supply
VDD
supply voltage
IDD
supply current
Istb
VPOR
standby current
power-on reset voltage
no load; VI = VDD or VSS
[1]
Input SCL; input/output SDA
VIL
LOW-level input voltage
0.5
-
+0.3VDD V
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
IOL
LOW-level output current
VOL = 0.4 V; VDD = 2.3 V
20
-
-
mA
VOL = 0.4 V; VDD = 5.0 V
30
-
-
mA
IL
leakage current
VI = VDD or VSS
1
-
+1
A
Ci
input capacitance
VI = VSS
-
6
10
pF
LED driver outputs
IOL
LOW-level output current
VOL = 0.5 V; VDD = 2.3 V
[2]
12
-
-
mA
VOL = 0.5 V; VDD = 3.0 V
[2]
17
-
-
mA
VOL = 0.5 V; VDD = 4.5 V
[2]
25
-
-
mA
[2]
-
-
200
mA
IOL(tot)
total LOW-level output current
VOL = 0.5 V; VDD = 4.5 V
IOH
HIGH-level output current
open-drain; VOH = VDD
50
-
+50
A
VOH
HIGH-level output voltage
IOH = 10 mA; VDD = 2.3 V
1.6
-
-
V
IOH = 10 mA; VDD = 3.0 V
2.3
-
-
V
IOH = 10 mA; VDD = 4.5 V
4.0
-
-
V
output capacitance
-
2.5
5
pF
VIL
LOW-level input voltage
0.5
-
+0.8
V
VIH
HIGH-level input voltage
2
-
5.5
V
ILI
input leakage current
1
-
+1
A
Ci
input capacitance
-
3.7
5
pF
Co
OE input
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Table 18. Static characteristics …continued
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Address inputs
VIL
LOW-level input voltage
0.5
-
+0.3VDD V
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
ILI
input leakage current
1
-
+1
A
Ci
input capacitance
-
3.7
5
pF
[1]
VDD must be lowered to 0.2 V in order to reset part.
[2]
Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal busing limits.
13. Dynamic characteristics
Table 19.
Dynamic characteristics
Symbol Parameter
Conditions
Standard-mode
I2C-bus
[1]
Min
Max
Fast-mode
I2C-bus
Fast-mode Plus Unit
I2C-bus
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
0
1000
tBUF
bus free time between a
STOP and START condition
4.7
-
1.3
-
0.5
-
kHz
s
tHD;STA
hold time (repeated) START
condition
4.0
-
0.6
-
0.26
-
s
tSU;STA
set-up time for a repeated
START condition
4.7
-
0.6
-
0.26
-
s
tSU;STO
set-up time for STOP
condition
4.0
-
0.6
-
0.26
-
s
tHD;DAT
data hold time
0
-
0
-
0
-
ns
data valid acknowledge time
[2]
0.3
3.45
0.1
0.9
0.05
0.45
s
tVD;DAT
data valid time
[3]
0.3
3.45
0.1
0.9
0.05
0.45
s
tSU;DAT
data set-up time
250
-
100
-
50
-
ns
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
0.5
-
s
tHIGH
HIGH period of the SCL
clock
4.0
-
0.6
-
0.26
-
s
tf
fall time of both SDA and
SCL signals
-
300
20 + 0.1Cb[6]
300
-
120
ns
tr
rise time of both SDA and
SCL signals
-
1000
20 + 0.1Cb[6]
300
-
120
ns
tSP
pulse width of spikes that
must be suppressed by the
input filter
-
50
-
50
-
50
ns
tVD;ACK
[4][5]
[7]
[1]
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held
LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.
[2]
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[3]
tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[4]
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
PCA9634
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[5]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified tf.
[6]
Cb = total capacitance of one bus line in pF.
[7]
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
0.7 × VDD
SDA
0.3 × VDD
tr
tBUF
tf
tHD;STA
tSP
tLOW
0.7 × VDD
SCL
0.3 × VDD
tHD;STA
P
tSU;STA
tHD;DAT
S
tHIGH
tSU;DAT
tSU;STO
Sr
P
002aaa986
Fig 19. Definition of timing
protocol
START
condition
(S)
tSU;STA
bit 7
MSB
(A7)
tLOW
bit 6
(A6)
tHIGH
bit 1
(D1)
bit 0
(D0)
acknowledge
(A)
STOP
condition
(P)
1 / fSCL
0.7 × VDD
SCL
0.3 × VDD
tBUF
tf
tr
0.7 × VDD
SDA
0.3 × VDD
tSU;DAT
tHD;STA
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
002aab285
Rise and fall times refer to VIL and VIH.
Fig 20. I2C-bus timing diagram
PCA9634
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14. Test information
VDD
PULSE
GENERATOR
VI
VO
RL
500 Ω
VDD
open
GND
DUT
RT
CL
50 pF
002aab284
RL = Load resistor for LEDn. RL for SDA and SCL > 1 k (3 mA or less current).
CL = Load capacitance includes jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generators.
Fig 21. Test circuitry for switching times
PCA9634
Product data sheet
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PCA9634
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8-bit Fm+ I2C-bus LED driver
15. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
HE
y
v M A
Z
20
11
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
10
1
e
bp
detail X
w M
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.51
0.49
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT163-1
075E04
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 22. Package outline SOT163-1 (SO20)
PCA9634
Product data sheet
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PCA9634
NXP Semiconductors
8-bit Fm+ I2C-bus LED driver
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
E
D
A
X
c
HE
y
v M A
Z
11
20
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
10
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT360-1
REFERENCES
IEC
JEDEC
JEITA
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 23. Package outline SOT360-1 (TSSOP20)
PCA9634
Product data sheet
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PCA9634
NXP Semiconductors
8-bit Fm+ I2C-bus LED driver
HVQFN20: plastic thermal enhanced very thin quad flat package; no leads;
20 terminals; body 5 x 5 x 0.85 mm
A
B
D
SOT662-1
terminal 1
index area
A
A1
E
c
detail X
C
e1
e
b
6
y
y1 C
v M C A B
w M C
10
L
11
5
e
e2
Eh
1
15
terminal 1
index area
20
16
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D(1)
Dh
E(1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.38
0.23
0.2
5.1
4.9
3.25
2.95
5.1
4.9
3.25
2.95
0.65
2.6
2.6
0.75
0.50
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT662-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-22
Fig 24. Package outline SOT662-1 (HVQFN20)
PCA9634
Product data sheet
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8-bit Fm+ I2C-bus LED driver
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
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• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 25) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 20 and 21
Table 20.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
350
< 350
< 2.5
235
220
2.5
220
220
Table 21.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 25.
PCA9634
Product data sheet
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8-bit Fm+ I2C-bus LED driver
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 25. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
18. Abbreviations
Table 22.
PCA9634
Product data sheet
Abbreviations
Acronym
Description
CDM
Charged-Device Model
DUT
Device Under Test
EMI
ElectroMagnetic Interference
ESD
ElectroStatic Discharge
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
IC
Integrated Circuit
LCD
Liquid Crystal Display
LED
Light Emitting Diode
LSB
Least Significant Bit
MM
Machine Model
MSB
Most Significant Bit
PCB
Printed-Circuit Board
PWM
Pulse Width Modulation
RGB
Red/Green/Blue
RGBA
Red/Green/Blue/Amber
SMBus
System Management Bus
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19. Revision history
Table 23.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9634 v.7.1
20171218
Product data sheet
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PCA9634_7
Modifications:
PCA9634_7
Modifications:
•
Corrected typo in Section 2 “Features and benefits” from “LED outputs programmable to 1, 0 or
‘high-impedance’ (default at power-up)...” to “LED outputs programmable to 1 (default at
power-up), 0 or ‘high-impedance’....”
20141010
•
Product data sheet
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PCA9634_6
Table 17 “Limiting values”: added Tj junction temperature
PCA9634_6
20080912
Product data sheet
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PCA9634_5
PCA9634_5
20080228
Product data sheet
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PCA9634_4
PCA9634_4
20070105
Product data sheet
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PCA9634_3
PCA9634_3
20061113
Product data sheet
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PCA9634_2
PCA9634_2
20060713
Objective data sheet
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PCA9634_1
PCA9634_1
20060411
Objective data sheet
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PCA9634
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7.1 — 18 December 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
36 of 39
PCA9634
NXP Semiconductors
8-bit Fm+ I2C-bus LED driver
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9634
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 7.1 — 18 December 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
37 of 39
PCA9634
NXP Semiconductors
8-bit Fm+ I2C-bus LED driver
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9634
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7.1 — 18 December 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
38 of 39
PCA9634
NXP Semiconductors
8-bit Fm+ I2C-bus LED driver
22. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.4
7.5
7.6
7.7
7.8
8
8.1
8.1.1
8.2
8.3
9
10
11
12
13
14
15
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 7
Device addresses . . . . . . . . . . . . . . . . . . . . . . . 7
Regular I2C-bus slave address. . . . . . . . . . . . . 7
LED All Call I2C-bus address . . . . . . . . . . . . . . 8
LED Sub Call I2C-bus addresses . . . . . . . . . . . 8
Software Reset I2C-bus address . . . . . . . . . . . 8
Control register . . . . . . . . . . . . . . . . . . . . . . . . . 9
Register definitions . . . . . . . . . . . . . . . . . . . . . 10
Mode register 1, MODE1 . . . . . . . . . . . . . . . . 11
Mode register 2, MODE2 . . . . . . . . . . . . . . . . 11
PWM0 to PWM7: Individual brightness control 12
GRPPWM: Group duty cycle control . . . . . . . 13
GRPFREQ: Group frequency . . . . . . . . . . . . . 13
LEDOUT0 and LEDOUT1: LED driver output
state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SUBADR1 to SUBADR3: I2C-bus subaddress
1 to 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ALLCALLADR: LED All Call I2C-bus address. 15
Active LOW output enable input . . . . . . . . . . . 15
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 16
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . 16
Using the PCA9634 with and without external
drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Individual brightness control with group
dimming/blinking . . . . . . . . . . . . . . . . . . . . . . . 19
Characteristics of the I2C-bus . . . . . . . . . . . . 20
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
START and STOP conditions . . . . . . . . . . . . . 20
System configuration . . . . . . . . . . . . . . . . . . . 20
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 21
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 22
Application design-in information . . . . . . . . . 24
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 25
Static characteristics. . . . . . . . . . . . . . . . . . . . 26
Dynamic characteristics . . . . . . . . . . . . . . . . . 27
Test information . . . . . . . . . . . . . . . . . . . . . . . . 29
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 30
16
17
17.1
17.2
17.3
17.4
18
19
20
20.1
20.2
20.3
20.4
21
22
Handling information . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
33
33
33
34
35
36
37
37
37
37
38
38
39
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2017.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 December 2017
Document identifier: PCA9634
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湘ICP备2023018690号
