PCA9670

PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset Rev. 02 — 17 July 2007 Product data sheet 1. General description The PCA9670 provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I2C-bus) and is a part of the Fast-mode Plus family. The PCA9670 is a drop-in upgrade for the PCF8574 providing higher Fast-mode Plus (Fm+) I2C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWM dimming of LEDs, higher I2C-bus drive (30 mA versus 3 mA) so that many more devices can be on the bus without the need for bus buffers, higher total package sink capacity (200 mA versus 100 mA) that supports having all 25 mA LEDs on at the same time and more device addresses (64 versus 8) are available to allow many more devices on the bus without address conflicts. The difference between the PCA9670 and the PCF8574 is that the interrupt output on the PCF8574 is replaced by a RESET input on the PCA9670. The devices consist of an 8-bit quasi-bidirectional port and an I2C-bus interface. The PCA9670 have low current consumption and include latched outputs with 25 mA high current drive capability for directly driving LEDs. The internal Power-On Reset (POR), hardware reset pin (RESET), or software reset sequence initializes the I/Os as inputs. 2. Features I I I I I I I I I I I I I 1 MHz I2C-bus interface Compliant with the I2C-bus Fast and Standard modes SDA with 30 mA sink capability for 4000 pF buses 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os 8-bit remote I/O pins that default to inputs at power-up Latched outputs with 25 mA sink capability for directly driving LEDs Total package sink capability of 200 mA Active LOW reset input 64 programmable slave addresses using 3 address pins Readable device ID (manufacturer, device type, and revision) Low standby current −40 °C to +85 °C operation ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA I Packages offered: SO16, TSSOP16, HVQFN16 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 3. Applications I I I I I I I I LED signs and displays Servers Industrial control Medical equipment PLCs Cellular telephones Gaming machines Instrumentation and test measurement 4. Ordering information Table 1. Ordering information Topside mark 670 PCA9670D PCA9670 Package Name HVQFN16 SO16 TSSOP16 Description plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 × 3 × 0.85 mm plastic small outline package; 16 leads; body width 7.5 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT758-1 SOT162-1 SOT403-1 Type number PCA9670BS PCA9670D PCA9670PW 5. Block diagram PCA9670 AD0 AD1 AD2 SCL SDA INPUT FILTER I2C-BUS CONTROL SHIFT REGISTER 8 BITS I/O PORT P0 to P7 RESET VDD VSS POWER-ON RESET write pulse read pulse 002aac256 Fig 1. Block diagram of PCA9670 PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 2 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset write pulse Itrt(pu) data from Shift Register D FF CI S power-on reset D FF read pulse CI S Q Q 100 µA IOH VDD IOL P0 to P7 VSS data to Shift Register 002aac109 to interrupt logic Fig 2. Simplified schematic diagram of P0 to P7 6. Pinning information 6.1 Pinning AD0 AD1 AD2 P0 P1 P2 P3 VSS 1 2 3 4 5 6 7 8 002aac257 16 VDD 15 SDA 14 SCL 13 RESET 12 P7 11 P6 10 P5 9 P4 AD0 AD1 AD2 P0 P1 P2 P3 VSS 1 2 3 4 5 6 7 8 002aac258 16 VDD 15 SDA 14 SCL 13 RESET 12 P7 11 P6 10 P5 9 P4 PCA9670D PCA9670PW Fig 3. Pin configuration for SO16 16 AD1 15 AD0 terminal 1 index area Fig 4. Pin configuration for TSSOP16 13 SDA 12 SCL 11 RESET 10 P7 9 5 6 7 8 P6 P5 14 VDD P4 AD2 P0 P1 P2 1 2 PCA9670BS 3 4 P3 VSS 002aac261 Transparent top view Fig 5. Pin configuration for HVQFN16 PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 3 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 6.2 Pin description Table 2. Symbol AD0 AD1 AD2 P0 P1 P2 P3 VSS P4 P5 P6 P7 RESET SCL SDA VDD [1] Pin description Pin SO16, TSSOP16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HVQFN16 15 16 1 2 3 4 5 6[1] 7 8 9 10 11 12 13 14 address input 0 address input 1 address input 2 quasi-bidirectional I/O 0 quasi-bidirectional I/O 1 quasi-bidirectional I/O 2 quasi-bidirectional I/O 3 supply ground quasi-bidirectional I/O 4 quasi-bidirectional I/O 5 quasi-bidirectional I/O 6 quasi-bidirectional I/O 7 reset input (active LOW) serial clock line serial data line supply voltage Description HVQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region. PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 4 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 7. Functional description Refer to Figure 1 “Block diagram of PCA9670”. 7.1 Device address Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address of the PCA9670 is shown in Figure 6. Slave address pins AD2, AD1, and AD0 choose 1 of 64 slave addresses. To conserve power, no internal pull-up resistors are incorporated on AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in Table 3 “PCA9670 address map”. Remark: When using the PCA9670, reserved I2C-bus addresses must be used with caution since they can interfere with: • “reserved for future use” I2C-bus addresses (0000 011, 1111 101, 1111 110, 1111 111) • slave devices that use the 10-bit addressing scheme (1111 0xx) • High speed mode (Hs-mode) master code (0000 1xx) slave address A6 A5 A4 A3 A2 A1 A0 R/W programmable 002aab636 Fig 6. PCA9670 address The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. When AD2, AD1 and AD0 are held to VDD or VSS, the same address as the PCF8574 is applied. PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 5 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 7.1.1 Address maps Table 3. AD2 VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD VDD PCA9670 address map AD1 SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD AD0 VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA A6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 6 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset PCA9670 address map …continued AD1 SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD AD0 VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA A6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address A0h A2h A4h A6h A8h AAh ACh AEh B0h B2h B4h B6h B8h BAh BCh BEh C0h C2h C4h C6h C8h CAh CCh CEh E0h E2h E4h E6h E8h EAh ECh EEh Table 3. AD2 SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 7 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 7.2 Software Reset Call, and device ID addresses Two other different addresses can be sent to the PCA9670. • General Call address: allows to reset the PCA9670 through the I2C-bus upon reception of the right I2C-bus sequence. See Section 7.2.1 “Software Reset” for more information. • Device ID address: allows to read ID information from the device (manufacturer, part identification, revision). See Section 7.2.2 “Device ID (PCA9670 ID field)” for more information. R/W 0 0 0 0 0 0 0 0 002aac115 Fig 7. General Call address 1 1 1 1 1 0 0 R/W 002aac116 Fig 8. Device ID address 7.2.1 Software Reset The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up state value through a specific formatted I2C-bus command. To be performed correctly, it implies that the I2C-bus is functional and that there is no device hanging the bus. The Software Reset sequence is defined as following: 1. A START command is sent by the I2C-bus master. 2. The reserved General Call I2C-bus address ‘0000 000’ with the R/W bit set to 0 (write) is sent by the I2C-bus master. 3. The PCA9670 device(s) acknowledge(s) after seeing the General Call address ‘0000 0000’ (00h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I2C-bus master. 4. Once the General Call address has been sent and acknowledged, the master sends 1 byte. The value of the byte must be equal to 06h. a. The PCA9670 acknowledges this value only. If the byte is not equal to 06h, the PCA9670 does not acknowledge it. If more than 1 byte of data is sent, the PCA9670 does not acknowledge any more. 5. Once the right byte has been sent and correctly acknowledged, the master sends a STOP command to end the Software Reset sequence: the PCA9670 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time. If the master sends a Repeated START instead, no reset is performed. PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 8 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset The I2C-bus master must interpret a non-acknowledge from the PCA9670 (at any time) as a ‘Software Reset Abort’. The PCA9670 does not initiate a reset of its registers. The unique sequence that initiates a Software Reset is described in Figure 9. SWRST Call I2C-bus address S 0 0 0 0 0 0 0 0 R/W acknowledge from slave(s) A 0 SWRST data = 06h 0 0 0 0 1 1 0 A P START condition acknowledge from slave(s) PCA9670 is(are) reset. Registers are set to default power-up values. 002aac263 Fig 9. Software Reset sequence 7.2.2 Device ID (PCA9670 ID field) The Device ID field is a 3-byte read-only (24 bits) word giving the following information: • 8 bits with the manufacturer name, unique per manufacturer (for example, NXP). • 13 bits with the part identification, assigned by manufacturer, the 7 MSBs with the category ID and the 6 LSBs with the feature ID (for example, for example PCA9670 16-bit quasi-output I/O expander). • 3 bits with the die revision, assigned by manufacturer (for example, Rev X). The Device ID is read-only, hardwired in the device and can be accessed as follows: 1. START command 2. The master sends the Reserved Device ID I2C-bus address ‘1111 100’ with the R/W bit set to 0 (write). 3. The master sends the I2C-bus slave address of the slave device it needs to identify. The LSB is a ‘Don’t care’ value. Only one device must acknowledge this byte (the one that has the I2C-bus slave address). 4. The master sends a Re-START command. Remark: A STOP command followed by a START command will reset the slave state machine and the Device ID read cannot be performed. Remark: A STOP command or a Re-START command followed by an access to another slave device will reset the slave state machine and the Device ID read cannot be performed. 5. The master sends the Reserved Device ID I2C-bus address ‘1111 100’ with the R/W bit set to 1 (read). 6. The device ID read can be done, starting with the 8 manufacturer bits (first byte + 4 MSB of the second byte), followed by the 13 part identification bits and then the 3 die revision bits (3 LSB of the third byte). 7. The master ends the reading sequence by NACKing the last byte, thus resetting the slave device state machine and allowing the master to send the STOP command. Remark: The reading of the Device ID can be stopped anytime by sending a NACK command. PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 9 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset Remark: If the master continues to ACK the bytes after the third byte, the PCA9670 rolls back to the first byte and keeps sending the Device ID sequence until a NACK has been detected. For the PCA9670, the Device ID is as shown in Figure 10. manufacturer 0 0 0 0 0 0 0 0 part identification 0 0 0 0 0 0 1 0 1 0 0 1 1 category identification feature identification revision 0 0 0 002aac264 Fig 10. PCA9670 ID acknowledge from one or several slave(s) device ID address S 1 1 1 1 1 0 0 0 R/W don't care A A6 A5 A4 A3 A2 A1 A0 X I2C-bus slave address of the device to be identified acknowledge from master acknowledge from slave to be identified acknowledge from slave to be identified A 1 1 1 1 1 0 0 1 R/W A START condition device ID address acknowledge from master no acknowledge from master P M7 M6 M5 M4 M3 M2 M1 M0 A C6 C5 C4 C3 C2 C1 C0 F5 A F4 P3 P2 P1 P0 R2 R1 R0 A category identification = 0000001 revision = 000 feature identification = 010011 manufacturer name = 00000000 STOP condition 002aac267 If more than 2 bytes are read, the slave device loops back to the first byte (manufacturer byte) and keeps sending data until the master generates a ‘no acknowledge’. Fig 11. Device ID field reading PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 10 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 8. I/O programming 8.1 Quasi-bidirectional I/O architecture The PCA9670’s 8 ports (see Figure 2) are entirely independent and can be used either as input or output ports. Input data is transferred from the ports to the microcontroller in the Read mode (see Figure 13). Output data is transmitted to the ports in the Write mode (see Figure 12). This quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data directions. At power-on the I/Os are HIGH. In this mode only a current source (IOH) to VDD is active. An additional strong pull-up to VDD (Itrt(pu)) allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the write mode. Remark: If a HIGH is applied to an I/O which has been written earlier to LOW, a large current (IOL) will flow to VSS. 8.2 Writing to the port (Output mode) To write, the master (microcontroller) first addresses the slave device. By setting the last bit of the byte containing the slave address to logic 0 the write mode is entered. The PCA9670 acknowledges and the master sends the data byte for P7 to P0 and is acknowledged by the PCA9670. The 8-bit data is presented on the port lines after it has been acknowledged by the PCA9670. The number of data bytes that can be sent successively is not limited. The previous data is overwritten every time a data byte has been sent. SCL 1 2 3 4 5 6 7 8 9 data 1 data 2 slave address SDA S A6 A5 A4 A3 A2 A1 A0 0 START condition R/W A P7 P6 1 P4 P3 P2 P1 P0 A P7 0 P5 P4 P3 P2 P1 P0 A P5 acknowledge from slave P5 acknowledge from slave acknowledge from slave write to port tv(Q) data output from port P5 output voltage DATA 1 VALID tv(Q) DATA 2 VALID P5 pull-up output current Itrt(pu) IOH 002aac265 Fig 12. Write mode (output) PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 11 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 8.3 Reading from a port (Input mode) All ports programmed as input should be set to logic 1. To read, the master (microcontroller) first addresses the slave device after it receives the interrupt. By setting the last bit of the byte containing the slave address to logic 1 the Read mode is entered. The data bytes that follow on the SDA are the values on the ports. If the data on the input port changes faster than the master can read, this data may be lost. slave address SDA S A6 A5 A4 A3 A2 A1 A0 1 START condition read from port R/W A data from port DATA 1 A data from port DATA 4 no acknowledge from master 1 P STOP condition acknowledge from slave acknowledge from master DATA 2 data into port th(D) DATA 3 tsu(D) DATA 4 002aac266 A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (Output mode). Input data is lost. Fig 13. Read input port register 8.4 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9670 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9670 registers and I2C-bus/SMBus state machine will initialize to their default states. Thereafter VDD must be lowered below 0.2 V to reset the device. 8.5 RESET input A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCA9670 registers and I2C-bus state machine will be held in their default state until the RESET input is once again HIGH. PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 12 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 9. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 9.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 14). SDA SCL data line stable; data valid change of data allowed mba607 Fig 14. Bit transfer 9.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 15.) SDA SDA SCL S START condition P STOP condition SCL mba608 Fig 15. Definition of START and STOP conditions PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 13 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 9.2 System configuration A device generating a message is a ‘transmitter'; a device receiving is the ‘receiver'. The device that controls the message is the ‘master' and the devices which are controlled by the master are the ‘slaves' (see Figure 16). SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 16. System configuration 9.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition 1 2 8 clock pulse for acknowledgement 002aaa987 9 Fig 17. Acknowledgement on the I2C-bus PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 14 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 10. Application design-in information 10.1 Bidirectional I/O expander applications In the 8-bit I/O expander application shown in Figure 18, P0 and P1 are inputs, and P2 to P7 are outputs. When used in this configuration, during a write, the input (P0 and P1) must be written as HIGH so the external devices fully control the input ports. The desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P2 to P7). During a read, the logic levels of the external devices driving the input ports (P0 and P1) and the previous written logic level to the output ports (P2 to P7) will be read. The GPIO also has a reset line (RESET) that can be connected to an output pin of the microprocessor. Since the device does not have an interrupt output, changes of the I/Os can be monitored by reading the input register. If both a RESET and INT are needed, use the PCA9671. VDD VDD VDD CORE PROCESSOR SDA SCL RESET AD0 AD1 AD2 P0 P1 P2 P3 P4 P5 P6 P7 temperature sensor battery status control for latch control for switch control for audio control for camera control for MP3 002aac298 Fig 18. Bidirectional I/O expander application 10.2 High current-drive load applications The GPIO has a maximum sinking current of 25 mA per bit. In applications requiring additional drive, two port pins in the same octal may be connected together to sink up to 50 mA current. Both bits must then always be turned on or off together. Up to 8 pins (one octal) can be connected together to drive 200 mA. VDD VDD VDD CORE PROCESSOR SDA SCL RESET AD0 AD1 AD2 P0 P1 P2 P3 P4 P5 P6 P7 LOAD 002aac299 Fig 19. High current-drive load application PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 15 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 11. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IDD ISS VI II IO Ptot P/out Tstg Tamb [1] Parameter supply voltage supply current ground supply current input voltage input current output current total power dissipation power dissipation per output storage temperature ambient temperature Conditions Min −0.5 VSS − 0.5 [1] Max +6 ±100 ±400 5.5 ±20 ±50 400 100 +150 +85 Unit V mA mA V mA mA mW mW °C °C −65 operating −40 Total package (maximum) output current is 400 mA. PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 16 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 12. Static characteristics Table 5. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Supplies VDD IDD supply voltage supply current Operating mode; no load; VI = VDD or VSS; fSCL = 1 MHz; AD0, AD1, AD2 = static H or L Standby mode; no load; VI = VDD or VSS; fSCL = 0 kHz [1] Parameter Conditions Min 2.3 - Typ 266 Max 5.5 500 Unit V µA Istb VPOR VIL VIH IOL standby current power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current −0.5 0.7VDD 2.5 1.8 4 27 35 41 −250 −1.0 3 3 3 3 10 2.0 +0.3VDD 5.5 +1 10 200 −300 10 10 +0.8 5.5 +1 +1 5 +0.3VDD 5.5 +1 5 µA V V V mA mA mA µA pF mA mA mA mA µA mA pF pF V V µA µA pF V V µA pF Input SCL; input/output SDA VOL = 0.4 V; VDD = 2.3 V VOL = 0.4 V; VDD = 3.0 V VOL = 0.4 V; VDD = 4.5 V 20 25 30 −1 12 17 25 −30 −0.5 [3] [3] IL Ci IOL leakage current input capacitance LOW-level output current[2] VI = VDD or VSS VI = VSS VOL = 0.5 V; VDD = 2.3 V VOL = 0.5 V; VDD = 3.0 V VOL = 0.5 V; VDD = 4.5 V I/Os; P0 to P7 IOL(tot) IOH Itrt(pu) Ci Co VIL VIH ILI IOH Ci VIL VIH ILI Ci [1] [2] [3] total LOW-level output current[2] VOL = 0.5 V; VDD = 4.5 V VOH = VSS HIGH-level output current input capacitance output capacitance LOW-level input voltage HIGH-level input voltage input leakage current HIGH-level output current input capacitance LOW-level input voltage HIGH-level input voltage input leakage current input capacitance transient boosted pull-up current VOH = VSS; see Figure 12 −0.5 2 −1 −1 −0.5 0.7VDD −1 - Input RESET Inputs AD0, AD1, AD2 The power-on reset circuit resets the I2C-bus logic with VDD < VPOR and set all I/Os to logic 1 (with current source to VDD). Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal busing limits. The value is not tested, but verified on sampling basis. © NXP B.V. 2007. All rights reserved. PCA9670_2 Product data sheet Rev. 02 — 17 July 2007 17 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 13. Dynamic characteristics Table 6. Dynamic characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Standard mode I2C-bus Min fSCL tBUF SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data hold time data valid acknowledge time[1] data valid time[2] data set-up time LOW period of the SCL clock HIGH period of the SCL clock fall time of both SDA and SCL signals rise time of both SDA and SCL signals pulse width of spikes that must be suppressed by the input filter[6] data output valid time data input setup time data input hold time reset pulse width reset recovery time reset time [4][5] Fast mode I2C-bus Min 0 1.3 Max 400 - Fast-mode Plus Unit I2C-bus Min 0 0.5 Max 1000 kHz µs Max 100 - 0 4.7 tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tf tr tSP 4.0 4.7 4.0 0 0.3 300 250 4.7 4.0 - 3.45 300 1000 50 0.6 0.6 0.6 0 0.1 50 100 1.3 0.6 20 + 0.1Cb[3] 20 + 0.1Cb[3] - 0.9 300 300 50 0.26 0.26 0.26 0 0.05 50 50 0.5 0.26 - 0.45 450 120 120 50 µs µs µs ns µs ns ns µs µs ns ns ns Port timing; CL ≤ 100 pF (see Figure 13 and Figure 12) tv(Q) tsu(D) th(D) tw(rst) trec(rst) trst [1] [2] [3] [4] 0 4 4 0 100 4 - 0 4 4 0 100 4 - 0 4 4 0 100 4 - µs µs µs µs µs µs Reset timing (see Figure 21) tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. Cb = total capacitance of one bus line in pF. A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region SCL’s falling edge. PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 18 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset [5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns. [6] protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW tHIGH bit 6 (A6) bit 0 (R/W) acknowledge (A) STOP condition (P) 1/f SCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aab175 Rise and fall times refer to VIL and VIH. Fig 20. I2C-bus timing diagram START SCL ACK or read cycle SDA 30 % trst RESET 50 % trec(rst) tw(rst) trst IOx_y 50 % output off 002aac018 50 % 50 % Fig 21. Reset timing PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 19 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 14. Package outline HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm SOT758-1 D B A terminal 1 index area E A A1 c detail X e1 1/2 e C vMCAB wM C 8 y1 C y e 5 L 4 b 9 e Eh 1/2 e e2 1 12 terminal 1 index area 16 Dh 0 13 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.75 1.45 E (1) 3.1 2.9 Eh 1.75 1.45 e 0.5 e1 1.5 e2 1.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT758-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-03-25 02-10-21 Fig 22. Package outline SOT758-1 (HVQFN16) PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 20 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 D E A X c y HE vMA Z 16 9 Q A2 A1 pin 1 index Lp L 1 e bp 8 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT162-1 REFERENCES IEC 075E03 JEDEC MS-013 JEITA EUROPEAN PROJECTION A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 10.5 10.1 0.41 0.40 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 8o o 0 ISSUE DATE 99-12-27 03-02-19 Fig 23. Package outline SOT162-1 (SO16) PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 21 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 24. Package outline SOT403-1 (TSSOP16) PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 22 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 15. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits. 16. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering 16.3 Wave soldering Key characteristics in wave soldering are: PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 23 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 25) than a PbSn process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 7 and 8 Table 7. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 8. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 25. PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 24 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 17. Abbreviations Table 9. Acronym CDM CMOS ESD GPIO HBM LED IC I2C-bus ID LSB MM MSB PLC RAID Abbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor ElectroStatic Discharge General Purpose Input/Output Human Body Model Light Emitting Diode Integrated Circuit Inter IC bus Identification Least Significant Bit Machine Model Most Significant Bit Programmable Logic Controller Redundant Array of Independent Disks PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 25 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 18. Revision history Table 10. Revision history Release date 20070717 Data sheet status Product data sheet Change notice Supersedes PCA9670_1 Document ID PCA9670_2 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 1 “Ordering information”: – changed Topside mark for PCA9670BS from “9670” to “670” – changed Topside mark for PCA9670PW from “9670” to “PCA9670” • Table 5 “Static characteristics”, sub-section “Supplies”: – changed IDD (Typ) from “100 µA” to “266 µA” – changed IDD (Max) from “200 µA” to “500 µA” • • Table 5 “Static characteristics”, sub-section “Input SCL; input/output SDA”: changed Ci (Typ) from “5 pF” to “4 pF” Table 5 “Static characteristics”, sub-section “I/Os; P0 to P7”: – changed IOL (Typ) (VDD = 2.3 V) from “” to “27 mA” – changed IOL (Typ) (VDD = 3.0 V) from “” to “35 mA” – changed IOL (Typ) (VDD = 4.5 V) from “” to “41 mA” – changed IOH (Typ) from “” to “−250 µA” – changed Ci (Typ) from “” to “3 pF” – changed Co (Typ) from “” to “3 pF” • • Table 5 “Static characteristics”, sub-section “Inputs AD0, AD1, AD2”: changed Ci (Typ) from “3.5 pF” to “3 pF” Table 6 “Dynamic characteristics”: – changed tVD;DAT (Fast-mode Plus) (Min) from “” to “50 ns” – changed tVD;DAT (Fast-mode Plus) (Max) from “-” to “450 ns” – changed tSP (Fast-mode Plus) (Max) from “” to “50 ns” PCA9670_1 20060620 Objective data sheet - - PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 26 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 19. Legal information 19.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 19.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 20. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com PCA9670_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 July 2007 27 of 28 NXP Semiconductors PCA9670 Remote 8-bit I/O expander for Fm+ I2C-bus with reset 21. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.2 7.2.1 7.2.2 8 8.1 8.2 8.3 8.4 8.5 9 9.1 9.1.1 9.2 9.3 10 10.1 10.2 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 19 19.1 19.2 19.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 Address maps. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Software Reset Call, and device ID addresses. 8 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . 8 Device ID (PCA9670 ID field) . . . . . . . . . . . . . . 9 I/O programming . . . . . . . . . . . . . . . . . . . . . . . 11 Quasi-bidirectional I/O architecture . . . . . . . . 11 Writing to the port (Output mode) . . . . . . . . . . 11 Reading from a port (Input mode) . . . . . . . . . 12 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 12 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Characteristics of the I2C-bus. . . . . . . . . . . . . 13 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 START and STOP conditions . . . . . . . . . . . . . 13 System configuration . . . . . . . . . . . . . . . . . . . 14 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application design-in information . . . . . . . . . 15 Bidirectional I/O expander applications . . . . . 15 High current-drive load applications . . . . . . . . 15 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 Static characteristics. . . . . . . . . . . . . . . . . . . . 17 Dynamic characteristics . . . . . . . . . . . . . . . . . 18 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20 Handling information. . . . . . . . . . . . . . . . . . . . 23 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Introduction to soldering . . . . . . . . . . . . . . . . . 23 Wave and reflow soldering . . . . . . . . . . . . . . . 23 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 24 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 26 Legal information. . . . . . . . . . . . . . . . . . . . . . . 27 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 19.4 20 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Contact information . . . . . . . . . . . . . . . . . . . . 27 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 July 2007 Document identifier: PCA9670_2