PCA9952; PCA9955
2
16-channel Fm+ I C-bus 57 mA constant current LED driver
Rev. 7.2 — 26 October 2021
1
Product data sheet
General description
2
The PCA9952 and PCA9955 are I C-bus controlled 16-channel constant current LED
driver optimized for dimming and blinking 57 mA Red/Green/Blue/Amber (RGBA) LEDs
in amusement products. Each LEDn output has its own 8-bit resolution (256 steps)
fixed frequency individual PWM controller that operates at 31.25 kHz with a duty cycle
that is adjustable from 0 % to 99.6 % to allow the LED to be set to a specific brightness
value. An additional 8-bit resolution (256 steps) group PWM controller has both a fixed
frequency of 122 Hz and an adjustable frequency between 15 Hz to once every 16.8
seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to either dim
or blink all LEDs with the same value.
Each LEDn output can be off, on (no PWM control), set at its individual PWM controller
value or at both individual and group PWM controller values. The PCA9952 and
PCA9955 operate with a supply voltage range of 3 V to 5.5 V and the constant current
sink LEDn outputs allow up to 40 V for the LED supply. The output peak current is
adjustable with an 8-bit linear DAC from 225 μA to 57 mA.
These devices have built-in open, short load and overtemperature detection circuitry.
2
The error information from the corresponding register can be read via the I C-bus.
Additionally, a thermal shutdown feature protects the device when internal junction
temperature exceeds the limit allowed for the process.
2
The PCA9952 and PCA9955 devices have Fast-mode Plus (Fm+) I C-bus interface. Fm
+ devices offer higher frequency (up to 1 MHz) or more densely populated bus operation
(up to 4000 pF).
The PCA9952 is identical to PCA9955 except for the following differences:
• The PCA9952 has only three hardware address pins compared to four on PCA9955.
• The PCA9952 has an output enable pin (OE) and the PCA9955 does not.
The active LOW output enable input pin (OE), available only on PCA9952, blinks all the
LEDn outputs and can be used to externally PWM the outputs, which is useful when
multiple devices need to be dimmed or blinked together without using software control.
2
Software programmable LED Group and three Sub Call I C-bus addresses allow all
2
or defined groups of PCA9952/55 devices to respond to a common I C-bus address,
allowing for example, all red LEDs to be turned on or off at the same time or marquee
2
chasing effect, thus minimizing I C-bus commands. On power-up, PCA9952/55 will have
a unique Sub Call address to identify it as a 16-channel LED driver. This allows mixing
of devices with different channel widths. Four hardware address pins on PCA9955 allow
up to 16 devices on the same bus. In the case of PCA9952, three hardware address pins
allow up to 8 devices on the same bus.
The Software Reset (SWRST) function allows the master to perform a reset of the
2
PCA9952/55 through the I C-bus, identical to the Power-On Reset (POR) that initializes
the registers to their default state causing the output current switches to be OFF (LED
NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
off). This allows an easy and quick way to reconfigure all device registers to the same
condition.
2
Features and benefits
• 16 LED drivers. Each output programmable at:
– Off
– On
– Programmable LED brightness
– Programmable group dimming/blinking mixed with individual LED brightness
– Programmable LEDn output enable delay to reduce EMI and surge currents
• 16 constant current output channels can sink up to 57 mA, tolerate up to 40 V when
OFF
• Output current adjusted through an external resistor
• Output current accuracy
– ±6 % between output channels
– ±8 % between PCA9952/55 devices
• Open/short load/overtemperature detection mode to detect individual LED errors
2
• 1 MHz Fast-mode Plus compatible I C-bus interface with 30 mA high drive capability
on SDA output for driving high capacitive buses
• 256-step (8-bit) linear programmable brightness per LEDn output varying from fully off
(default) to maximum brightness using a 31.25 kHz PWM signal
• 256-step group brightness control allows general dimming (using a 122 Hz PWM
signal) from fully off to maximum brightness (default)
• 256-step group blinking with frequency programmable from 15 Hz to 16.8 s and duty
cycle from 0 % to 99.6 %
• Output state change programmable on the Acknowledge or the STOP Command to
update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).
• Active LOW Output Enable (OE) input pin (only on PCA9952) allows for hardware
blinking and dimming of the LEDs
• Four hardware address pins allow 16 PCA9955 devices to be connected to the same
2
I C-bus and to be individually programmed
2
• Four software programmable I C-bus addresses (one LED Group Call address and
three LED Sub Call addresses) allow groups of devices to be addressed at the same
time in any combination (for example, one register used for ‘All Call’ so that all the
2
PCA9952/55s on the I C-bus can be addressed at the same time and the second
1
register used for three different addresses so that ⁄3 of all devices on the bus can
be addressed at the same time in a group). Software enable and disable for each
2
programmable I C-bus address.
• Unique power-up default Sub Call address allows mixing of devices with different
channel widths
2
• Software Reset feature (SWRST Call) allows the device to be reset through the I C-bus
• 8 MHz internal oscillator requires no external components
• Internal power-on reset
• Noise filter on SDA/SCL inputs
• No glitch on LED on power-up
• Low standby current
• Operating power supply voltage (VDD) range of 3 V to 5.5 V
• 5.5 V tolerant inputs on non-LED pins
PCA9952_PCA9955
Product data sheet
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Rev. 7.2 — 26 October 2021
© NXP B.V. 2021. All rights reserved.
2 / 47
NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
• Operating temperature:
– -40 °C to +85 °C
• ESD protection exceeds 2000 V HBM per JESD22-A114, and 500 V CDM per JESD22C101
• Latch-up testing is done to JEDEC Standard JESD78 Class II, Level B
• Packages offered: HTSSOP28
3
Applications
•
•
•
•
•
•
•
4
Amusement products
RGB or RGBA LED drivers
LED status information
LED displays
LCD backlights
Keypad backlights for cellular phones or handheld devices
Automotive lighting
Ordering information
Table 1. Ordering information
Type number
Topside
marking
Package
Name
Description
[1]
PCA9952
HTSSOP28
plastic thermal enhanced thin shrink small outline package; SOT1172-2
28 leads; body width 4.4 mm; lead pitch 0.65 mm; exposed
die pad
[1]
PCA9955
HTSSOP28
plastic thermal enhanced thin shrink small outline package; SOT1172-2
28 leads; body width 4.4 mm; lead pitch 0.65 mm; exposed
die pad
PCA9952TW/Q900
PCA9955TW/Q900
[1]
Version
PCA9952TW/Q900 and PCA9955TW/Q900 are AEC-Q100 compliant.
4.1 Ordering options
Table 2. Ordering options
Type number
Orderable part
number
PCA9952TW/Q900
PCA9955TW/Q900
PCA9952_PCA9955
Product data sheet
Package
Packing method
Minimum
order
quantity
Temperature
PCA9952TW/Q900,118 HTSSOP28
Reel 13" Q1/T1
*standard mark SMD
2500
Tamb = -40 °C to +85 °C
PCA9955TW/Q900,118 HTSSOP28
Reel 13" Q1/T1
*standard mark SMD
2500
Tamb = -40 °C to +85 °C
All information provided in this document is subject to legal disclaimers.
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3 / 47
NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
5
Block diagram
A0 A1 A2 A3/OE(1)
REXT
LED0
LED1
LED14
LED15
I/O
REGULATOR
PCA9952/55
DAC0
SCL
INPUT FILTER
SDA
DAC1
individual LED
current setting
8-bit DACs
I2C-BUS
CONTROL
DAC
15
POWER-ON
RESET
VDD
VSS
DAC
14
OUTPUT DRIVER, DELAY CONTROL
AND ERROR DETECTION
200 kΩ
INPUT
FILTER
RESET
LED STATE
SELECT
REGISTER
PWM
REGISTER X
BRIGHTNESS
CONTROL
÷ 256
31.25 kHz
repetion rate 31.25 kHz
GRPFREQ
REGISTER
8 MHz
OSCILLATOR
DIM CLOCK
GRPPWM
REGISTER
(DUTY CYCLE
CONTROL)
MUX/
CONTROL
'0' - permanently OFF
'1' - permanently ON
002aae909
Dim repetition rate = 122 Hz.
Blink repetition rate = 15 Hz to every 16.8 seconds.
1. On PCA9955 this pin is address pin A3. On PCA9952 this pin is OE.
Figure 1. Block diagram of PCA9952/55
PCA9952_PCA9955
Product data sheet
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4 / 47
NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
6
Pinning information
6.1 Pinning
PCA9952TW/Q900
PCA9955TW/Q900
REXT
1
28 VDD
REXT
1
28 VDD
A0
2
27 SDA
A0
2
27 SDA
A1
3
26 SCL
A1
3
26 SCL
A2
4
25 RESET
A2
4
25 RESET
OE
5
24 VSS
A3
5
24 VSS
LED0
6
23 LED15
LED0
6
23 LED15
LED1
7
22 LED14
LED1
7
22 LED14
LED2
8
21 LED13
LED2
8
21 LED13
LED3
9
20 LED12
LED3
9
20 LED12
VSS 10
19 VSS
LED4 11
VSS 10
19 VSS
18 LED11
LED4 11
LED5 12
17 LED10
LED5 12
17 LED10
LED6 13
16 LED9
LED6 13
16 LED9
LED7 14
15 LED8
LED7 14
15 LED8
(1)
18 LED11
(1)
002aae911
002aae912
a. PCA9952TW/Q900
b. PCA9955TW/Q900
1. Thermal pad; connected to VSS.
Figure 2. Pin configuration for HTSSOP28
6.2 Pin description
Table 3. PCA9952 pin description
PCA9952_PCA9955
Product data sheet
Symbol
Pin
Type
Description
REXT
1
I
current set resistor input; resistor to ground
A0
2
I
address input 0
[1]
A1
3
I
address input 1
[1]
A2
4
I
address input 2
[1]
OE
5
I
active LOW output enable
LED0
6
O
LED driver 0
LED1
7
O
LED driver 1
LED2
8
O
LED driver 2
LED3
9
O
LED driver 3
LED4
11
O
LED driver 4
LED5
12
O
LED driver 5
LED6
13
O
LED driver 6
LED7
14
O
LED driver 7
LED8
15
O
LED driver 8
LED9
16
O
LED driver 9
LED10
17
O
LED driver 10
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5 / 47
NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
Table 3. PCA9952 pin description...continued
Symbol
Pin
Type
Description
LED11
18
O
LED driver 11
LED12
20
O
LED driver 12
LED13
21
O
LED driver 13
LED14
22
O
LED driver 14
LED15
23
O
LED driver 15
RESET
25
I
active LOW reset input
SCL
26
I
serial clock line
SDA
27
I/O
serial data line
[2]
VSS
10, 19, 24
ground
supply ground
VDD
28
power supply
supply voltage
[1]
[2]
In order to obtain the best system level ESD performance, a standard pull-up resistor (10 kΩ typical) is required for any
address pin connecting to VDD. For additional information on system level ESD performance, please refer to application
notes AN10897 and AN11131.
HTSSOP28 package supply ground is connected to both VSS pins and exposed center pad. VSS pins must be connected
to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed
pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction
through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.
Table 4. PCA9955 pin description
PCA9952_PCA9955
Product data sheet
Symbol
Pin
Type
Description
REXT
1
I
current set resistor input; resistor to ground
A0
2
I
address input 0
[1]
A1
3
I
address input 1
[1]
A2
4
I
address input 2
[1]
A3
5
I
address input 3
[1]
LED0
6
O
LED driver 0
LED1
7
O
LED driver 1
LED2
8
O
LED driver 2
LED3
9
O
LED driver 3
LED4
11
O
LED driver 4
LED5
12
O
LED driver 5
LED6
13
O
LED driver 6
LED7
14
O
LED driver 7
LED8
15
O
LED driver 8
LED9
16
O
LED driver 9
LED10
17
O
LED driver 10
LED11
18
O
LED driver 11
LED12
20
O
LED driver 12
LED13
21
O
LED driver 13
All information provided in this document is subject to legal disclaimers.
Rev. 7.2 — 26 October 2021
© NXP B.V. 2021. All rights reserved.
6 / 47
NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
Table 4. PCA9955 pin description...continued
Symbol
Pin
Type
Description
LED14
22
O
LED driver 14
LED15
23
O
LED driver 15
RESET
25
I
active LOW reset input
SCL
26
I
serial clock line
SDA
27
I/O
serial data line
VSS
10, 19, 24
ground
supply ground
VDD
28
power supply
supply voltage
[1]
[2]
7
[2]
In order to obtain the best system level ESD performance, a standard pull-up resistor (10 kΩ typical) is required for any
address pin connecting to VDD. For additional information on system level ESD performance, please refer to application
notes AN10897 and AN11131.
HTSSOP28 package supply ground is connected to both VSS pins and exposed center pad. VSS pins must be connected
to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed
pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction
through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.
Functional description
Refer to Figure 1.
7.1 Device addresses
Following a START condition, the bus master must output the address of the slave it is
accessing.
For PCA9955 there are a maximum of 16 possible programmable addresses using the 4
hardware address pins.
For PCA9952 there are a maximum of 8 possible programmable addresses using the 3
hardware address pins.
2
7.1.1 Regular I C-bus slave address
2
The I C-bus slave address of the PCA9955 is shown in Figure 3. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
2
they must be pulled HIGH or LOW externally. Figure 4 shows the I C-bus slave address
of the PCA9952.
2
Remark: Reserved I C-bus addresses must be used with caution since they can interfere
with:
•
•
•
•
PCA9952_PCA9955
Product data sheet
2
‘reserved for future use’ I C-bus addresses (0000 011, 1111 1XX)
slave devices that use the 10-bit addressing scheme (1111 0XX)
slave devices that are designed to respond to the General Call address (0000 000)
High-speed mode (Hs-mode) master code (0000 1XX)
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7 / 47
NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
slave address
1
1
0
A3
A2
fixed
slave address
A1
hardware
selectable
A0 R/W
1
1
fixed
002aae914
Figure 3. PCA9955 slave address
0
0
A2
A1
A0 R/W
hardware
selectable
002aae915
Figure 4. PCA9952 slave address
The last bit of the address byte defines the operation to be performed. When set to logic
1 a read is selected, while a logic 0 selects a write operation.
2
7.1.2 LED All Call I C-bus address
• Default power-up value (ALLCALLADR register): E0h or 1110 000X
2
• Programmable through I C-bus (volatile programming)
2
• At power-up, LED All Call I C-bus address is enabled. PCA9952/55 sends an ACK
when E0h (R/W = 0) or E1h (R/W = 1) is sent by the master.
See Section 7.3.10 for more detail.
2
Remark: The default LED All Call I C-bus address (E0h or 1110 000X) must not be used
2
as a regular I C-bus slave address since this address is enabled at power-up. All of the
2
2
PCA9952/55s on the I C-bus will acknowledge the address if sent by the I C-bus master.
2
7.1.3 LED bit Sub Call I C-bus addresses
2
• 3 different I C-bus addresses can be used
• Default power-up values:
– SUBADR1 register: ECh or 1110 110X
– SUBADR2 register: ECh or 1110 110X
– SUBADR3 register: ECh or 1110 110X
2
• Programmable through I C-bus (volatile programming)
2
• At power-up, SUBADR1 is enabled while SUBADR2 and SUBADR3 I C-bus addresses
are disabled.
Remark: At power-up SUBADR1 identifies this device as a 16-channel driver.
See Section 7.3.9 for more detail.
2
2
Remark: The default LED Sub Call I C-bus addresses may be used as regular I C-bus
slave addresses as long as they are disabled.
7.2 Control register
Following the successful acknowledgement of the slave address, LED All Call address or
LED Sub Call address, the bus master will send a byte to the PCA9952/55, which will be
stored in the Control register.
The lowest 7 bits are used as a pointer to determine which register will be accessed
(D[6:0]). The highest bit is used as Auto-Increment Flag (AIF). The AIF is active by
default at power-up.
This bit along with the MODE1 register bit 5 and bit 6 provide the Auto-Increment feature.
PCA9952_PCA9955
Product data sheet
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8 / 47
PCA9952; PCA9955
NXP Semiconductors
2
16-channel Fm+ I C-bus 57 mA constant current LED driver
register address
AIF
D6
D5
D4
D3
D2
Auto-Increment Flag
D1
D0
002aad850
reset state = 80h
2
Remark: The Control register does not apply to the Software Reset I C-bus address.
Figure 5. Control register
When the Auto-Increment Flag is set (AIF = logic 1), the seven low-order bits of the
Control register are automatically incremented after a read or write. This allows the user
to program the registers sequentially. Four different types of Auto-Increment are possible,
depending on AI1 and AI0 values of MODE1 register.
Table 5. Auto-Increment options
[1]
[1]
AIF AI1
AI0
Function
0
0
0
no Auto-Increment
1
0
0
Auto-Increment for registers (00h to 41h). D[6:0] roll over to 00h after the last
register 41h is accessed.
1
0
1
Auto-Increment for individual brightness registers only (0Ah to 19h). D[6:0]
roll over to 0Ah after the last register (19h) is accessed.
1
1
0
Auto-Increment for MODE1 to IREF15 control registers (00h to 31h). D[6:0]
roll over to 00h after the last register (31h) is accessed.
1
1
1
Auto-Increment for global control registers and individual brightness registers
(08h to 19h). D[6:0] roll over to 08h after the last register (19h) is accessed.
[1]
AI1 and AI0 come from MODE1 register.
Remark: Other combinations not shown in Table 5 (AIF + AI[1:0] = 001b, 010b and 011b)
are reserved and must not be used for proper device operation.
AIF + AI[1:0] = 000b is used when the same register must be accessed several times
2
during a single I C-bus communication, for example, changes the brightness of a single
LED. Data is overwritten each time the register is accessed during a write operation.
AIF + AI[1:0] = 100b is used when all the registers must be sequentially accessed, for
example, power-up programming.
AIF + AI[1:0] = 101b is used when the 16 LED drivers must be individually programmed
2
with different values during the same I C-bus communication, for example, changing
color setting to another color setting.
AIF + AI[1:0] = 110b is used when MODE1 to IREF15 registers must be programmed with
2
different settings during the same I C-bus communication.
AIF + AI[1:0] = 111b is used when the 16 LED drivers must be individually programmed
with different values in addition to global programming.
Only the 7 least significant bits D[6:0] are affected by the AIF, AI1 and AI0 bits.
When the Control register is written, the register entry point determined by D[6:0] is
the first register that will be addressed (read or write operation), and can be anywhere
between 00h and 41h (as defined in Table 6). When AIF = 1, the Auto-Increment Flag
is set and the rollover value at which the register increment stops and goes to the next
one is determined by AIF, AI1 and AI0. See Table 5 for rollover values. For example, if
PCA9952_PCA9955
Product data sheet
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9 / 47
NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
MODE1 register bit AI1 = 0 and AI0 = 1 and if the Control register = 1001 0000, then the
register addressing sequence will be (in hexadecimal): 10 → 11 → … → 19 → 0A → 0B
→ … → 19 → 0A → 0B → … as long as the master keeps sending or reading data.
If MODE1 register bit AI1 = 0 and AI0 = 0 and if the Control register = 1010 0010, then
the register addressing sequence will be (in hexadecimal): 22 → 23 → … → 41 → 00 →
01 → … → 19 → 0A → 0B → … as long as the master keeps sending or reading data.
If MODE1 register bit AI1 = 0 and AI0 = 1 and if the Control register = 1000 0101, then
the register addressing sequence will be (in hexadecimal): 05 → 06 → … → 19 → 0A →
0B → … → 19 → 0A → 0B → … as long as the master keeps sending or reading data.
Remark: Writing to registers marked ‘not used’ will return NACK.
7.3 Register definitions
[1]
Table 6. Register summary
Register
number
(hexadecimal)
D6
D5
D4
D3
D2
D1
D0
Name
Type
Function
00h
0
0
0
0
0
0
0
MODE1
read/write
Mode register 1
01h
0
0
0
0
0
0
1
MODE2
read/write
Mode register 2
02h
0
0
0
0
0
1
0
LEDOUT0
read/write
LEDn output state 0
03h
0
0
0
0
0
1
1
LEDOUT1
read/write
LEDn output state 1
04h
0
0
0
0
1
0
0
LEDOUT2
read/write
LEDn output state 2
05h
0
0
0
0
1
0
1
LEDOUT3
read/write
LEDn output state 3
06h
0
0
0
0
1
1
0
-
read/write
not used
[1]
07h
0
0
0
0
1
1
1
-
read/write
not used
[1]
08h
0
0
0
1
0
0
0
GRPPWM
read/write
group duty cycle control
09h
0
0
0
1
0
0
1
GRPFREQ
read/write
group frequency
0Ah
0
0
0
1
0
1
0
PWM0
read/write
brightness control LED0
0Bh
0
0
0
1
0
1
1
PWM1
read/write
brightness control LED1
0Ch
0
0
0
1
1
0
0
PWM2
read/write
brightness control LED2
0Dh
0
0
0
1
1
0
1
PWM3
read/write
brightness control LED3
0Eh
0
0
0
1
1
1
0
PWM4
read/write
brightness control LED4
0Fh
0
0
0
1
1
1
1
PWM5
read/write
brightness control LED5
10h
0
0
1
0
0
0
0
PWM6
read/write
brightness control LED6
11h
0
0
1
0
0
0
1
PWM7
read/write
brightness control LED7
12h
0
0
1
0
0
1
0
PWM8
read/write
brightness control LED8
13h
0
0
1
0
0
1
1
PWM9
read/write
brightness control LED9
14h
0
0
1
0
1
0
0
PWM10
read/write
brightness control LED10
15h
0
0
1
0
1
0
1
PWM11
read/write
brightness control LED11
16h
0
0
1
0
1
1
0
PWM12
read/write
brightness control LED12
17h
0
0
1
0
1
1
1
PWM13
read/write
brightness control LED13
PCA9952_PCA9955
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NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
[1]
...continued
Table 6. Register summary
Register
number
(hexadecimal)
D6
D5
D4
D3
D2
D1
D0
Name
Type
Function
18h
0
0
1
1
0
0
0
PWM14
read/write
brightness control LED14
19h
0
0
1
1
0
0
1
PWM15
read/write
brightness control LED15
1Ah to 21h
-
-
-
-
-
-
-
-
read/write
not used
22h
0
1
0
0
0
1
0
IREF0
read/write
output gain control register 0
23h
0
1
0
0
0
1
1
IREF1
read/write
output gain control register 1
24h
0
1
0
0
1
0
0
IREF2
read/write
output gain control register 2
25h
0
1
0
0
1
0
1
IREF3
read/write
output gain control register 3
26h
0
1
0
0
1
1
0
IREF4
read/write
output gain control register 4
27h
0
1
0
0
1
1
1
IREF5
read/write
output gain control register 5
28h
0
1
0
1
0
0
0
IREF6
read/write
output gain control register 6
29h
0
1
0
1
0
0
1
IREF7
read/write
output gain control register 7
2Ah
0
1
0
1
0
1
0
IREF8
read/write
output gain control register 8
2Bh
0
1
0
1
0
1
1
IREF9
read/write
output gain control register 9
2Ch
0
1
0
1
1
0
0
IREF10
read/write
output gain control register 10
2Dh
0
1
0
1
1
0
1
IREF11
read/write
output gain control register 11
2Eh
0
1
0
1
1
1
0
IREF12
read/write
output gain control register 12
2Fh
0
1
0
1
1
1
1
IREF13
read/write
output gain control register 13
30h
0
1
1
0
0
0
0
IREF14
read/write
output gain control register 14
31h
0
1
1
0
0
0
1
IREF15
read/write
output gain control register 15
32h to 39h
-
-
-
-
-
-
-
-
read/write
not used
3Ah
0
1
1
1
0
1
0
OFFSET
read/write
Offset/delay on LEDn outputs
3Bh
0
1
1
1
0
1
1
SUBADR1
read/write
I C-bus subaddress 1
3Ch
0
1
1
1
1
0
0
SUBADR2
read/write
I C-bus subaddress 2
3Dh
0
1
1
1
1
0
1
SUBADR3
read/write
I C-bus subaddress 3
3Eh
0
1
1
1
1
1
0
ALLCALLADR
read/write
All Call I C-bus address
3Fh
0
1
1
1
1
1
1
RESERVED1
read/write
reserved
40h
1
0
0
0
0
0
0
RESERVED2
read only
reserved
41h
1
0
0
0
0
0
1
RESERVED3
read only
reserved
42h
1
0
0
0
0
1
0
PWMALL
write only
brightness control for all LEDn
43h
1
0
0
0
0
1
1
IREFALL
write only
output gain control for all registers
IREF0 to IREF15
44h
1
0
0
0
1
0
0
EFLAG0
read only
output error flag 0
45h
1
0
0
0
1
0
1
EFLAG1
read only
output error flag 1
46h to 7Fh
-
-
-
-
-
-
-
-
read only
not used
[1]
[2]
[1]
[1]
2
2
2
2
[2]
[2]
[2]
[1]
Remark: Writing to registers marked ‘not used’ will return a NACK.
Remark: Writing to registers marked ‘reserved’ will not change any functionality in the chip.
PCA9952_PCA9955
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NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
7.3.1 MODE1 — Mode register 1
Table 7. MODE1 - Mode register 1 (address 00h) bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
AIF
read only
0
Register Auto-Increment disabled.
1*
Register Auto-Increment enabled.
0*
Auto-Increment bit 1 = 0. Auto-increment range as defined in Table 5.
1
Auto-Increment bit 1 = 1. Auto-increment range as defined in Table 5.
0*
Auto-Increment bit 0 = 0. Auto-increment range as defined in Table 5.
1
Auto-Increment bit 0 = 1. Auto-increment range as defined in Table 5.
0*
Normal mode .
1
Low-power mode. Oscillator off
0
PCA9952; PCA9955 does not respond to I C-bus subaddress 1.
1*
PCA9952; PCA9955 responds to I C-bus subaddress 1.
0*
PCA9952; PCA9955 does not respond to I C-bus subaddress 2.
1
PCA9952; PCA9955 responds to I C-bus subaddress 2.
0*
PCA9952; PCA9955 does not respond to I C-bus subaddress 3.
1
PCA9952; PCA9955 responds to I C-bus subaddress 3.
0
PCA9952; PCA9955 does not respond to LED All Call I C-bus
address.
1*
PCA9952; PCA9955 responds to LED All Call I C-bus address.
6
5
4
3
2
1
0
[1]
[2]
[3]
AI1
R/W
AI0
R/W
SLEEP
SUB1
R/W
R/W
SUB2
R/W
SUB3
R/W
ALLCALL
R/W
[1]
[2][3]
.
2
2
2
2
2
2
2
2
It takes 500 μs max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not guaranteed if PWMx,
GRPPWM or GRPFREQ registers are accessed within the 500 μs window.
No blinking or dimming is possible when the oscillator is off.
The device must be reset if the LED driver output state is set to LDRx=11 after the device is set back to Normal mode.
7.3.2 MODE2 — Mode register 2
Table 8. MODE2 - Mode register 2 (address 01h) bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
OVERTEMP
read only
0*
O.K.
1
overtemperature condition
0*
LED fault test complete
1
start fault test
0*
group control = dimming.
1
group control = blinking.
6
5
FAULTTEST
DMBLNK
R/W
R/W
4
-
read only
0*
reserved
3
OCH
R/W
0*
outputs change on STOP command
1
outputs change on ACK
1*
reserved
2
-
PCA9952_PCA9955
Product data sheet
read only
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NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
Table 8. MODE2 - Mode register 2 (address 01h) bit description...continued
Legend: * default value.
Bit
Symbol
Access
Value
Description
1
-
read only
0*
reserved
0
-
read only
1*
reserved
7.3.3 LEDOUT0 to LEDOUT3, LED driver output state
Table 9. LEDOUT0 to LEDOUT3 - LED driver output state registers (address 02h to 05h) bit
description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
02h
LEDOUT0
7:6
LDR3
R/W
00*
LED3 output state control
5:4
LDR2
R/W
00*
LED2 output state control
3:2
LDR1
R/W
00*
LED1 output state control
1:0
LDR0
R/W
00*
LED0 output state control
7:6
LDR7
R/W
00*
LED7 output state control
5:4
LDR6
R/W
00*
LED6 output state control
3:2
LDR5
R/W
00*
LED5 output state control
1:0
LDR4
R/W
00*
LED4 output state control
7:6
LDR11
R/W
00*
LED11 output state control
5:4
LDR10
R/W
00*
LED10 output state control
3:2
LDR9
R/W
00*
LED9 output state control
1:0
LDR8
R/W
00*
LED8 output state control
7:6
LDR15
R/W
00*
LED15 output state control
5:4
LDR14
R/W
00*
LED14 output state control
3:2
LDR13
R/W
00*
LED13 output state control
1:0
LDR12
R/W
00*
LED12 output state control
03h
04h
05h
LEDOUT1
LEDOUT2
LEDOUT3
LDRx = 00
LED driver x is off (default power-up state).
LDRx = 01
LED driver x is fully on (individual brightness and group dimming/blinking not controlled).
LDRx = 10
LED driver x individual brightness can be controlled through its PWMx register.
LDRx = 11
LED driver x individual brightness and group dimming/blinking can be controlled through
its PWMx register and the GRPPWM registers.
Remark: Setting the device in low power mode while being on group dimming/blinking
mode may cause the LED output state to be in an unknown state after the device is set
back to normal mode. The device must be reset and all register values reprogrammed.
PCA9952_PCA9955
Product data sheet
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NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
7.3.4 GRPPWM, group duty cycle control
Table 10. GRPPWM - Group brightness control register (address 08h) bit
description
Legend: * default value
Address
Register
Bit
Symbol
Access
Value
Description
08h
GRPPWM
7:0
GDC[7:0]
R/W
1111 1111*
GRPPWM register
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 122 Hz fixed
frequency signal is superimposed with the 31.25 kHz individual brightness control signal.
GRPPWM is then used as a global brightness control allowing the LEDn outputs to be
dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the 16 outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LEDn output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LEDn outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3
registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers
define a global blinking pattern, where GRPFREQ contains the blinking period (from 67
ms to 16.8 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
(1)
7.3.5 GRPFREQ, group frequency
Table 11. GRPFREQ - Group frequency register (address 09h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
09h
GRPFREQ
7:0
GFRQ[7:0]
R/W
0000 0000*
GRPFREQ register
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.
Applicable to LEDn outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3
registers).
Blinking period is controlled through 256 linear steps from 00h (67 ms, frequency 15 Hz)
to FFh (16.8 s).
(2)
7.3.6 PWM0 to PWM15, individual brightness control
Table 12. PWM0 to PWM15 - PWM registers 0 to 15 (address 0Ah to 19h) bit
description
Legend: * default value.
PCA9952_PCA9955
Product data sheet
Address
Register
Bit
Symbol
Access Value
0Ah
PWM0
7:0
IDC0[7:0]
R/W
0000 0000* PWM0 Individual Duty Cycle
0Bh
PWM1
7:0
IDC1[7:0]
R/W
0000 0000* PWM1 Individual Duty Cycle
0Ch
PWM2
7:0
IDC2[7:0]
R/W
0000 0000* PWM2 Individual Duty Cycle
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NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
Table 12. PWM0 to PWM15 - PWM registers 0 to 15 (address 0Ah to 19h) bit
description...continued
Legend: * default value.
Address
Register
Bit
Symbol
Access Value
Description
0Dh
PWM3
7:0
IDC3[7:0]
R/W
0000 0000* PWM3 Individual Duty Cycle
0Eh
PWM4
7:0
IDC4[7:0]
R/W
0000 0000* PWM4 Individual Duty Cycle
0Fh
PWM5
7:0
IDC5[7:0]
R/W
0000 0000* PWM5 Individual Duty Cycle
10h
PWM6
7:0
IDC6[7:0]
R/W
0000 0000* PWM6 Individual Duty Cycle
11h
PWM7
7:0
IDC7[7:0]
R/W
0000 0000* PWM7 Individual Duty Cycle
12h
PWM8
7:0
IDC8[7:0]
R/W
0000 0000* PWM8 Individual Duty Cycle
13h
PWM9
7:0
IDC9[7:0]
R/W
0000 0000* PWM9 Individual Duty Cycle
14h
PWM10
7:0
IDC10[7:0]
R/W
0000 0000* PWM10 Individual Duty Cycle
15h
PWM11
7:0
IDC11[7:0]
R/W
0000 0000* PWM11 Individual Duty Cycle
16h
PWM12
7:0
IDC12[7:0]
R/W
0000 0000* PWM12 Individual Duty Cycle
17h
PWM13
7:0
IDC13[7:0]
R/W
0000 0000* PWM13 Individual Duty Cycle
18h
PWM14
7:0
IDC14[7:0]
R/W
0000 0000* PWM14 Individual Duty Cycle
19h
PWM15
7:0
IDC15[7:0]
R/W
0000 0000* PWM15 Individual Duty Cycle
A 31.25 kHz fixed frequency signal is used for each output. Duty cycle is controlled
through 256 linear steps from 00h (0 % duty cycle = LEDn output off) to FFh (99.6 % duty
cycle = LEDn output at maximum brightness). Applicable to LEDn outputs programmed
with LDRx = 10 or 11 (LEDOUT0 to LEDOUT3 registers).
(3)
Remark: The first lower end 8 steps of PWM and the last (higher end) steps of PWM will
not have effective brightness control of LEDs due to edge rate control of LEDn output
pins.
7.3.7 IREF0 to IREF15, LEDn output current value registers
These registers reflect the gain settings for output current for LED0 to LED15.
Table 13. IREF0 to IREF15 - LEDn output gain control registers (address 22h to 31h) bit
description
Legend: * default value.
PCA9952_PCA9955
Product data sheet
Address
Register
Bit
Access
Value
Description
22h
IREF0
7:0
R/W
00h*
LED0 output current setting
23h
IREF1
7:0
R/W
00h*
LED1 output current setting
24h
IREF2
7:0
R/W
00h*
LED2 output current setting
25h
IREF3
7:0
R/W
00h*
LED3 output current setting
26h
IREF4
7:0
R/W
00h*
LED4 output current setting
27h
IREF5
7:0
R/W
00h*
LED5 output current setting
28h
IREF6
7:0
R/W
00h*
LED6 output current setting
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NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
Table 13. IREF0 to IREF15 - LEDn output gain control registers (address 22h to 31h) bit
description...continued
Legend: * default value.
Address
Register
Bit
Access
Value
Description
29h
IREF7
7:0
R/W
00h*
LED7 output current setting
2Ah
IREF8
7:0
R/W
00h*
LED8 output current setting
2Bh
IREF9
7:0
R/W
00h*
LED9 output current setting
2Ch
IREF10
7:0
R/W
00h*
LED10 output current setting
2Dh
IREF11
7:0
R/W
00h*
LED11 output current setting
2Eh
IREF12
7:0
R/W
00h*
LED12 output current setting
2Fh
IREF13
7:0
R/W
00h*
LED13 output current setting
30h
IREF14
7:0
R/W
00h*
LED14 output current setting
31h
IREF15
7:0
R/W
00h*
LED15 output current setting
7.3.8 OFFSET — LEDn output delay offset register
Table 14. OFFSET - LEDn output delay offset register (address 3Ah) bit description
Legend: * default value.
Address
Register
Bit
Access
Value
3Ah
OFFSET
7:4
read only 0000*
not used
3:0
R/W
LEDn output delay offset factor
1000*
Description
The OFFSET register should not be changed while the LEDn output is on and pulsing.
The PCA9955 can be programmed to have turn-on delay between LEDn outputs. This
helps to reduce peak current for the VDD supply and reduces EMI.
The order in which the LEDn outputs are enabled will always be the same (channel 0 will
enable first and channel 15 will enable last).
OFFSET control register bits [3:0] determine the delay used between the turn-on times
as follows:
0000 = no delay between outputs (all on, all off at the same time)
0001 = delay of 1 clock cycle (125 ns) between successive outputs
0010 = delay of 2 clock cycles (250 ns) between successive outputs
0011 = delay of 3 clock cycles (375 ns) between successive outputs
:
1111 = delay of 15 clock cycles (1.875 μs) between successive outputs
Example: If the value in the OFFSET register is 1000 the corresponding delay = 8 × 125
ns = 1 μs delay between successive outputs.
channel 0 turns on at time 0 μs
channel 1 turns on at time 1 μs
channel 2 turns on at time 2 μs
channel 3 turns on at time 3 μs
channel 4 turns on at time 4 μs
channel 5 turns on at time 5 μs
PCA9952_PCA9955
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NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
channel 6 turns on at time 6 μs
channel 7 turns on at time 7 μs
channel 8 turns on at time 8 μs
channel 9 turns on at time 9 μs
channel 10 turns on at time 10 μs
channel 11 turns on at time 11 μs
channel 12 turns on at time 12 μs
channel 13 turns on at time 13 μs
channel 14 turns on at time 14 μs
channel 15 turns on at time 15 μs
2
7.3.9 LED bit Sub Call I C-bus addresses for PCA9952/55
2
Table 15. SUBADR1 to SUBADR3 - I C-bus subaddress registers 1 to 3 (address 3Bh to
3Dh) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access Value
Description
3Bh
SUBADR1
7:1
A1[7:1]
R/W
1110 110*
I C-bus subaddress 1
0
A1[0]
R only
0*
reserved
7:1
A2[7:1]
R/W
1110 110*
I C-bus subaddress 2
0
A2[0]
R only
0*
reserved
7:1
A3[7:1]
R/W
1110 110*
I C-bus subaddress 3
0
A3[0]
R only
0*
reserved
3Ch
3Dh
SUBADR2
SUBADR3
2
2
2
Default power-up values are ECh, ECh, ECh. At power-up, SUBADR1 is enabled while
SUBADR2 and SUBADR3 are disabled. The power-up default bit subaddress of ECh
indicates that this device is a 16-channel LED driver.
All three subaddresses are programmable. Once subaddresses have been programmed
to their right values, SUBx bits need to be set to logic 1 in order to have the device
acknowledging these addresses (MODE1 register) (0). When SUBx is set to logic 1, the
2
2
corresponding I C-bus subaddress can be used during either an I C-bus read or write
sequence.
2
7.3.10 ALLCALLADR, LED All Call I C-bus address
2
Table 16. ALLCALLADR - LED All Call I C-bus address register (address 3Eh) bit
description
Legend: * default value.
Address
Register
Bit
Symbol
Access Value
Description
3Eh
ALLCALLADR
7:1
AC[7:1]
R/W
1110 000*
ALLCALL I C-bus
address register
0
AC[0]
R only
0*
reserved
2
2
The LED All Call I C-bus address allows all the PCA9952/55s on the bus to be
programmed at the same time (ALLCALL bit in register MODE1 must be equal to logic 1
2
(power-up default state)). This address is programmable through the I C-bus and can be
2
used during either an I C-bus read or write sequence. The register address can also be
programmed as a Sub Call.
PCA9952_PCA9955
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NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
2
Only the 7 MSBs representing the All Call I C-bus address are valid. The LSB in
ALLCALLADR register is a read-only bit (0).
If ALLCALL bit = 0, the device does not acknowledge the address programmed in
register ALLCALLADR.
7.3.11 RESERVED1
This register is reserved.
7.3.12 RESERVED2, RESERVED3
These registers are reserved.
7.3.13 PWMALL — brightness control for all LEDn outputs
When programmed, the value in this register will be used for PWM duty cycle for all the
LEDn outputs and will be reflected in PWM0 through PWM15 registers.
Write to any of the PWM0 to PWM15 registers will overwrite the value in corresponding
PWMn register programmed by PWMALL.
Table 17. PWMALL - brightness control for all LEDn outputs register (address 42h) bit
description
Legend: * default value.
Address
Register
Bit
Access
Value
Description
42h
PWMALL
7:0
write only
0000 0000*
duty cycle for all LEDn outputs
7.3.14 IREFALL register: output current value for all LEDn outputs
The output current setting for all outputs is held in this register. When this register is
written to or updated, all LEDn outputs will be set to a current corresponding to this
register value.
Write to IREF0 to IREF15 will overwrite the output current settings.
Table 18. IREFALL - Output gain control for all LEDn outputs (address 43h) bit
description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7:0
IREFALL
write only
00h*
Current gain setting for all LEDn outputs.
7.3.15 LED driver constant current outputs
In LED display applications, PCA9952/55 provides nearly no current variations from
channel to channel and from device to device. The maximum current skew between
channels is less than ±6 % and less than ±8 % between devices.
7.3.15.1 Adjusting output peak current
The PCA9952/55 scales up the reference current (Iref) set by the external resistor (Rext)
to sink the output current (IO) at each output port. The maximum output peak current
for the outputs can be set using Rext. In addition, the constant value for current drive at
each of the outputs is independently programmable using command registers IREF0 to
PCA9952_PCA9955
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NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
IREF15. Alternatively, programming the IREFALL register allows all outputs to be set at
one current value determined by the value in IREFALL register.
Equation 4 and Equation 5 can be used to calculate the minimum and maximum constant
current values that can be programmed for the outputs for a chosen Rext.
(4)
(5)
For a given IREFx setting,
.
Example 1: If Rext = 1 kΩ, IO_LED_LSB = 225 μA, IO_LED_MAX = 57.375 mA.
So each channel can be programmed with its individual IREFx in 256 steps and in 225
μA increments to a maximum output current of 57.375 mA independently.
Example 2: If Rext = 2 kΩ, IO_LED_LSB = 112.5 μA, IO_LED_MAX = 28.687 mA.
So each channel can be programmed with its individual IREFx in 256 steps and in 112.5
μA increments to a maximum output channel of 28.687 mA independently.
002aag288
80
IREFx = 255
IO(LEDn)
(mA)
60
40
20
0
1
2
3
4
5
6
7
8
9
10
Rext (k )
IO(LEDn) (mA) = IREFx × (0.9 / 4) / Rext (kΩ)
maximum IO(LEDn) (mA) = 255 × (0.9 / 4) / Rext (kΩ)
Remark: Default IREFx at power-up = 0.
Figure 6. Maximum ILED versus Rext
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PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
002aaf396
57.375(1)
IO(target)
(mA)
40
30
20
10
0
0
31
63
95
127
159
191
223
255
IREFx[7:0] value
1. Assuming Rext = 1 kΩ.
Figure 7. IO(target) versus IREFx value
7.3.16 LED error detection
The PCA9952/55 is capable of detecting an LED open or a short condition at its LEDn
output. To detect LED error status, user must initiate the LEDn output fault test. The
LEDout channel under test must be ON to conduct this test.
Setting MODE2[6] = 1 initiates the FAULTTEST. The entire test sequence takes up to 52
μs. Once the test cycle begins, all outputs will be turned off (no matter where they are in
the group or individual PWM cycle) until entire test sequence is finished and next register
read or write is activated. Then each output will be enabled at its previously defined
output current level based on IREFx for 1.25 μs. Only those channels with an LEDOUT
value other than 00h will be tested. If the output is selected to be fully on, individual
dim, or individual and group dim that channel will be tested; however, its operation
will be affected for one entire 32 μs individual PWM cycle. At the end of the test cycle
PCA9952/55 writes out the 16 error flag bits to EFLAGn.
Before reading the error flag register EFLAGn, user should verify if the FAULTTEST is
complete by reading MODE2 register. MODE2[6] = 0 indicates that the test is complete
and the error status is ready in EFLAG0 and EFLAG1.
The error flags in registers EFLAG0 and EFLAG1 can now be read.
Table 19. EFLAG0, EFLAG1 - Error flag registers (address 44h, 45h) bit description
Legend: * default value.
Address
Register
Bit
Access
Value
Description
44h
EFLAG0
7:0
R only
00h*
Error flag 0; lower 8-bit channel error status
45h
EFLAG1
7:0
R only
00h*
Error flag 1; upper 8-bit channel error status
Remark: The LED open and short-circuit error status bits share the same error flag
registers (EFLAG0/EFLAG1). If both LED open and short-circuit conditions exist on
different LED outputs, the error status bits in error flag registers report only the opencircuits first and disregards the short-circuits. If only one of the two conditions (that is,
LED open-circuits or short-circuits) exists, then the error status bits in error flag registers
will report all of those faulted channels. For all unused LED outputs, user must program
their LED outputs to the ‘OFF’ state (LDRx = 00) and IREFx value to 00h, and all unused
LED output pins must be pulled up to VDD with a recommended 100 kΩ shared resistor.
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PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
The states of the unused LED channels have no effect upon the FAULTTEST and always
return 0s in EFLAG0/EFLAG1 registers.
7.3.16.1 Open-circuit detection principle
The PCA9952/55 LED open-circuit detection compares the effective current level IO with
the open load detection threshold current Ith(det). If IO is below the threshold Ith(det), the
PCA9952/55 detects an open load condition. This error status can be read out as an
error flag through the registers EFLAG0 and EFLAG1. For open-circuit error detection of
an output channel, that channel must be ON.
Table 20. Open-circuit detection
State of output
port
Condition of output Error status code
current
Description
OFF
IO = 0 mA
0
detection not possible
1
open-circuit
channel n error status bit 0
normal
IO <
ON
[1]
Ith(det)
[1]
IO ≥ Ith(det)
[1]
Ith(det) = 0.5 × IO(target) (typical). This threshold may be different for each I/O and only depends on IREFx and Rext.
7.3.16.2 Short-circuit detection principle
The LED short-circuit detection compares the effective voltage level (VO) with the
shorted-load detection threshold voltages Vth(trig). If VO is above the Vth(trig) threshold,
the PCA9952/55 detects a shorted-load condition. If VO is below the Vth(trig) threshold,
no error is detected or error bit is reset. This error status can be read out as an error flag
through the registers EFLAG0 and EFLAG1. For short-circuit error detection, a channel
must be on.
Table 21. Shorted-load detection
State of output
port
Condition of output Error status code
voltage
Description
OFF
-
ON
[1]
0
detection not possible
VO ≥
[1]
Vth(trig)
1
short-circuit
VO <
[1]
Vth(trig)
channel n error status bit 0
normal
Vth ≅ 2.5 V.
Remark: The error status does not distinguish between an LED short condition and an
LED open condition. When an LED fault condition is noted, the LEDn outputs should be
turned off to prevent heat dissipation in the chip and the repair should be done.
7.3.17 Overtemperature protection
If the PCA9952/55 chip temperature exceeds its limit (Tth(otp), see Table 24), all output
channels will be disabled until the temperature drops below its limit minus a small
hysteresis (Thys, see Table 24). When an overtemperature situation is encountered,
the OVERTEMP flag (bit 7) is set in the MODE2 register. Once the die temperature
reduces below the Tth(otp) - Thys, the chip will return to the same condition it was prior to
the overtemperature event and the OVERTEMP flag will be cleared.
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16-channel Fm+ I C-bus 57 mA constant current LED driver
7.4 Active LOW output enable input
Remark: Only the PCA9952 has the OE pin.
The active LOW output enable (OE) pin on PCA9952 allows to enable or disable all the
LEDn outputs at the same time.
• When a LOW level is applied to OE pin, all the LEDn outputs are enabled.
• When a HIGH level is applied to OE pin, all the LEDn outputs are high-impedance.
The OE pin can be used as a synchronization signal to switch on/off several PCA9952
devices at the same time. This requires an external clock reference that provides blinking
period and the duty cycle.
The OE pin can also be used as an external dimming control signal. The frequency of the
external clock must be high enough not to be seen by the human eye, and the duty cycle
value determines the brightness of the LEDs.
Remark: Do not use OE as an external blinking control signal when internal global
blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an undefined
blinking pattern. Do not use OE as an external dimming control signal when internal
global dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an
undefined dimming pattern.
7.5 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCA9952/55 in a
reset condition until VDD has reached VPOR. At this point, the reset condition is released
2
and the PCA9952/55 registers and I C-bus state machine are initialized to their default
states (all zeroes) causing all the channels to be deselected. Thereafter, VDD must be
pulled lower than 1 V and stay LOW for longer than 20 μs. The device will reset itself,
and allow 2 ms for the device to fully wake up.
7.6 Hardware reset recovery
When a reset of PCA9952/55 is activated using an active LOW input on the RESET pin,
a reset pulse width of 2.5 μs minimum is required. The maximum wait time after RESET
pin is released is 1.5 ms.
7.7 Software reset
2
The Software Reset Call (SWRST Call) allows all the devices in the I C-bus to be reset
2
to the power-up state value through a specific formatted I C-bus command. To be
2
performed correctly, it implies that the I C-bus is functional and that there is no device
hanging the bus.
The maximum wait time after software reset is 1 ms.
The SWRST Call function is defined as the following:
2
1. A START command is sent by the I C-bus master.
2. The reserved General Call address ‘0000 000’ with the R/W bit set to ‘0’ (write) is
2
sent by the I C-bus master.
3. The PCA9952/55 device(s) acknowledge(s) after seeing the General Call address
‘0000 0000’ (00h) only. If the R/W bit is set to ‘1’ (read), no acknowledge is returned
2
to the I C-bus master.
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PCA9952; PCA9955
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16-channel Fm+ I C-bus 57 mA constant current LED driver
4. Once the General Call address has been sent and acknowledged, the master sends
1 byte with 1 specific value (SWRST data byte 1):
5. Byte 1 = 06h: the PCA9952/55 acknowledges this value only. If byte 1 is not equal to
06h, the PCA9952/55 does not acknowledge it.
If more than 1 byte of data is sent, the PCA9952/55 does not acknowledge any more.
1. Once the correct byte (SWRST data byte 1) has been sent and correctly
acknowledged, the master sends a STOP command to end the SWRST function:
the PCA9952/55 then resets to the default value (power-up value) and is ready to be
addressed again within the specified bus free time (tBUF).
General Call address
S
0
0
0
0
START condition
0
0
0
SWRST data byte 1
0
A
0
0
0
acknowledge
from slave
0
0
1
1
0
A
P
acknowledge
from slave
STOP
condition
002aac900
Figure 8. SWRST Call
2
The I C-bus master must interpret a non-acknowledge from the PCA9952/55 (at any
time) as a ‘SWRST Call Abort’. The PCA9952/55 does not initiate a reset of its registers.
This happens only when the format of the SWRST Call sequence is not correct.
7.8 Individual brightness control with group dimming/blinking
A 31.25 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is
used to control individually the brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can
be applied to the 16 LEDn outputs control registers LEDOUT0 to LEDOUT3):
• A lower 122 Hz fixed frequency signal with programmable duty cycle (8 bits, 256 steps)
is used to provide a global brightness control.
• A programmable frequency signal from 15 Hz to every 16.8 seconds (8 bits, 256 steps)
with programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking
control.
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PCA9952; PCA9955
NXP Semiconductors
2
16-channel Fm+ I C-bus 57 mA constant current LED driver
1
2
3
4
5
6
7
8
9 10 11 12
251
252
253
254
255
256
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9 10 11
Brightness Control signal (LEDn)
N × 125 ns
with N = (0 to 255)
(PWMx Register)
M × 256 × 125 ns
with M = (0 to 255)
(GRPPWM Register)
256 × 125 ns = 32 µs
(31.25 kHz)
Group Dimming signal
256 × 256 × 125 ns = 8.19 ms (122 Hz)
1
2
3
4
5
6
7
8
resulting Brightness + Group Dimming signal
002aaf935
Minimum pulse width for LEDn Brightness Control is 125 ns.
Minimum pulse width for Group Dimming is 32 μs.
When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal will have 1 pulse
of the LED Brightness Control signal (pulse width = N × 125 ns, with ‘N’ defined in PWMx register).
This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 8.
Figure 9. Brightness + Group Dimming signals
8
2
Characteristics of the I C-bus
2
The I C-bus is for 2-way, 2-line communication between different ICs or modules. The
two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at
this time will be interpreted as control signals (see Figure 10).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Figure 10. Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 11).
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PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
SDA
SCL
S
P
START condition
STOP condition
mba608
Figure 11. Definition of START and STOP conditions
8.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 12).
SDA
SCL
CONTROLLER
TRANSMITTER/
RECEIVER
TARGET
RECEIVER
TARGET
TRANSMITTER/
RECEIVER
CONTROLLER
TRANSMITTER
CONTROLLER
TRANSMITTER/
RECEIVER
I2C-BUS
MULTIPLEXER
TARGET
002aaa966
Figure 12. System configuration
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions
from transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception
of each byte. Also a master must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter. The device that acknowledges
has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during the HIGH period of the acknowledge related clock pulse; set-up time
and hold time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
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PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from controller
1
2
S
8
9
clock pulse for
acknowledgement
START
condition
002aaa987
2
Figure 13. Acknowledgement on the I C-bus
9
Bus transactions
slave address(1)
S
1
1
data for register D[7:0](2)
control register
0 A3 A2 A1 A0 0
START condition
A
R/W
X D6 D5 D4 D3 D2 D1 D0 A
Auto-Increment flag
A
acknowledge
from slave
acknowledge
from slave
P
acknowledge
from slave
STOP
condition
002aae918
1. Slave address shown for PCA9955.
2. See Table 6 for register definition.
Figure 14. Write to a specific register
slave address(1)
S
1
1
0 A3 A2 A1 A0 0
START condition
MODE1 register data(2)
control register
A
R/W
acknowledge
from slave
1
0
0
0
0
0
0
MODE1
register selection
Auto-Increment on
0
A
acknowledge
from slave
MODE2 register data
A
A
acknowledge
from slave
acknowledge
from slave
(cont.)
ALLCALLADR register data
(cont.)
A
P
acknowledge
from slave
STOP
condition
002aae919
1. Slave address shown for PCA9955.
2. AI1, AI0 = 00. See Table 5 for Auto-Increment options.
Remark: Care should be taken to load the appropriate value here in the AI1 and AI0 bits of the MODE1 register for
programming the part with the required Auto-Increment options.
Figure 15. Write to all registers using the Auto-Increment feature
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PCA9952; PCA9955
2
16-channel Fm+ I C-bus 57 mA constant current LED driver
slave address(1)
S
1
1
control register
0 A3 A2 A1 A0 0
START condition
A
0
0
0
1
0
1
0
PWM0
register selection
R/W
acknowledge
from slave
PWM14 register data
(cont.)
1
PWM0 register data
PWM1 register data
A
acknowledge
from slave
A
A
acknowledge
from slave
acknowledge
from slave
(cont.)
Auto-Increment on
register rollover
PWM15 register data
PWM0 register data
PWM14 register data
PWM15 register data
A
A
A
A
A
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
P
STOP
condition
002aae920
This example assumes that AIF + AI[1:0] = 101b.
1. Slave address shown for PCA9955.
Figure 16. Multiple writes to Individual Brightness registers only using the Auto-Increment feature
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PCA9952; PCA9955
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2
16-channel Fm+ I C-bus 57 mA constant current LED driver
slave address(1)
S
1
1
ReSTART
condition
control register
0 A3 A2 A1 A0 0
START condition
A
R/W
acknowledge
from slave
data from MODE2 register
(cont.)
1
0
0
0
0
0
0
0
MODE1
register selection
Auto-Increment on
A Sr 1
slave address(1)
1
0 A3 A2 A1 A0 1
acknowledge
from slave
A (cont.)
A
R/W
acknowledge
from master
acknowledge
from slave
data from
EFLAG1 register
data from LEDOUT0
data from MODE1 register
data from
MODE1 register
A
A
A
acknowledge
from master
acknowledge
from master
acknowledge
from master
A (cont.)
acknowledge
from master
data from last read byte
(cont.)
A
P
not acknowledge
from master
STOP
condition
002aae921
This example assumes that the MODE1[5] = 0 and MODE1[6] = 0.
1. Slave address shown for PCA9955.
Figure 17. Read all registers using the Auto-Increment feature
slave address(1)
S
1
1
data from register
0 A3 A2 A1 A0 1
START condition
data from register
A
A
acknowledge
from slave
acknowledge
from master
R/W
data from register
A
no acknowledge
from master
P
STOP
condition
002aae922
Remark: A read operation can be done without doing a write operation before it. In this case, the data sent out is from the
register pointed to by the control register (written to during the last write operation) with the Auto-Increment options in the
MODE1 register (written to during the last write operation).
1. Slave address shown for PCA9955.
Figure 18. Read of registers
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16-channel Fm+ I C-bus 57 mA constant current LED driver
slave address(1)(2)
sequence (A) S
1
1
new LED All Call I 2C address(3)
control register
0 A3 A2 A1 A0 0
START condition
A
1
0
1
1
1
1
1
0
A
ALLCALLADR
register selection
R/W
acknowledge
from slave
1
0
1
0
1
acknowledge
from slave
Auto-Increment on
0
1
X
A
P
acknowledge
from slave
STOP condition
the 16 LEDs are on at the acknowledge(4)
LED All Call I 2C address
sequence (B) S
1
0
1
0
1
0
1
START condition
control register
0
A
1
0
0
0
LEDOUT1 register (LED fully ON)
1
0
1
0
1
0
1
1
0
A
acknowledge
from the 4 devices
1
0
1
the 16 LEDs are on
at the acknowledge(4)
LEDOUT2 register (LED fully ON)
A
0
0
1
0
1
0
1
0
0
1
0
1
acknowledge
from the 4 devices
Auto-Increment on
the 16 LEDs are on
at the acknowledge(4)
0
0
LEDOUT0
register selection
R/W
acknowledge
from the 4 devices
(cont.)
0
LEDOUT0 register (LED fully ON)
1
A (cont.)
acknowledge
from the 4 devices
the 16 LEDs are on
at the acknowledge(4)
LEDOUT3 register (LED fully ON)
A
0
1
acknowledge
from the 4 devices
0
1
0
1
0
1
A
acknowledge
from the 4 devices
P
STOP condition
002aae923
1.
2.
3.
4.
Slave address shown for PCA9955.
In this example, several PCA9955s are used and the same sequence (A) (above) is sent to each of them.
ALLCALL bit in MODE1 register is previously set to 1 for this example.
OCH bit in MODE2 register is previously set to 1 for this example.
2
Figure 19. LED All Call I C-bus address programming and LED All Call sequence example
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16-channel Fm+ I C-bus 57 mA constant current LED driver
10 Application design-in information
VDD = 3.3 V or 5.0 V
1.6 k
1.6 k
I2C-BUS/SMBus
1.1 k
(optional)
up to 40 V
VDD
MASTER
SDA
SDA
SCL
SCL
RESET
LED0
LED1
RESET
PCA9955
LED2
LED3
LED4
LED5
LED6
LED7
REXT
LED8
ISET
LED9
10 k (1)
LED10
LED11
A0
LED12
A1
A2
LED13
A3
LED14
VSS
VSS
LED15
C
10 µF
002aae924
1. A standard 10 kΩ pull-up resistor is required to obtain the best system level ESD
performance.
Figure 20. Typical application (PCA9955)
10.1 Thermal considerations
Since the PCA9952/55 device integrates 16 linear current sources, thermal
considerations should be taken into account to prevent overheating, which can cause the
device to go into thermal shutdown.
Perhaps the major contributor for device’s overheating is the LED forward voltage
mismatch. This is because it can cause significant voltage differences between the
LED strings of the same type (e.g., 2 V to 3 V), which ultimately translates into higher
power dissipation in the device. The voltage drop across the LED channels of the device
is given by the difference between the supply voltage and the LED forward voltage of
each LED string. Reducing this to a minimum (e.g., 0.8 V) helps to keep the power
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16-channel Fm+ I C-bus 57 mA constant current LED driver
dissipation down. Therefore LEDs binning is recommended to minimize LED voltage
forward variation and reduce power dissipation in the device.
In order to ensure that the device will not go into thermal shutdown when operating under
certain application conditions, its junction temperature (Tj) should be calculated to ensure
that is below the overtemperature threshold limit (125 °C). The Tj of the device depends
on the ambient temperature (Tamb), device’s total power dissipation (Ptot), and thermal
resistance.
The device junction temperature can be calculated by using the following equation:
(6)
where:
Tj = junction temperature
Tamb = ambient temperature
Rth(j-a) = junction to ambient thermal resistance
Ptot = (device) total power dissipation
An example of this calculation is show below:
Conditions:
Tamb = 50 °C
Rth(j-a) = 31 °C/W (per JEDEC 51 standard for multilayer PCB)
ILED = 50 mA / channel
IDD(max) = 12 mA
VDD = 5 V
LEDs per channel = 10 LEDs / channel
LED VF(typ) = 3 V per LED (30 V total for 10 LEDs in series)
LED VF mismatch = 0.2 V per LED (2 V total for 10 LEDs in series)
Vreg(drv) = 0.8 V (This will be present only in the LED string with the highest LED
forward voltage.)
Vsup = LED VF(typ) + LED VF mismatch + Vreg(drv) = 30 V + 2 V + 0.8 V = 32.8 V
Ptot calculation:
Ptot = IC_power + LED drivers_power;
IC_power = (IDD × VDD) + [(SCL_VOL × IOL) + (SDA_VOL × IOL)]
IC_power = (0.012 A × 5 V) + [(0.4 V × 0.03 A) + (0.4 V × 0.03 A)] = 0.084 W
LED drivers_power = [(16 - 1) × (ILED) × (LED VF mismatch + Vreg(drv))] + (ILED ×
Vreg(drv))
LED drivers_power = [15 × 0.05 A × (2 V + 0.8 V)] + (0.05 A × 0.8 V) = 2.14 W
Ptot = 0.084 W + 2.14 W = 2.224 W
Tj calculation:
Tj = Tamb + Rth(j-a) × Ptot
Tj = 50 °C + (31 °C/W × 2.224 W) = 118.94 °C
This confirms that the junction temperature is below the minimum overtemperature
threshold of 125 °C, which ensures the device will not go into thermal shutdown under
these conditions.
It is important to mention that the value of the thermal resistance junction-to-ambient
(Rth(j-a)) strongly depends in the PCB design. Therefore, the thermal pad of the device
should be attached to a big enough PCB copper area to ensure proper thermal
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dissipation (similar to JEDEC 51 standard). Several thermal vias in the PCB thermal
pad should be used as well to increase the effectiveness of the heat dissipation (e.g., 15
thermal vias). The thermal vias should be distributed evenly in the PCB thermal pad.
Finally it is important to point out that this calculation should be taken as a reference only
and therefore evaluations should still be performed under the application environment
and conditions to confirm proper system operation.
11 Limiting values
Table 22. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
Conditions
Min
Max
Unit
supply voltage
-0.5
+6.0
V
VI/O
voltage on an input/output pin
VSS - 0.5
5.5
V
Vdrv(LED)
LED driver voltage
VSS - 0.5
40
V
IO(LEDn)
output current on pin LEDn
-
65
mA
ISS
ground supply current
-
1.0
A
-
90
mA
[1]
Ilu
latch-up current
JESD
Ptot
total power dissipation
Tamb = 25 °C
-
3.2
W
Tamb = 85 °C
-
1.3
W
-65
+150
°C
-40
+85
°C
-20
+125
°C
Tstg
storage temperature
Tamb
ambient temperature
operating
PCA9952TW/Q900, PCA9955TW/Q900
Tj
[1]
junction temperature
Class II, Level B for A1 (pin 3), A2 (pin 4). All other pins are Class II, Level A (±100 mA).
12 Thermal characteristics
Table 23. Thermal characteristics
Symbol
Rth(j-a)
[1]
Parameter
Conditions
thermal resistance from junction to ambient
[1]
HTSSOP28
Typ
Unit
31
°C/W
Per JEDEC 51 standard for multilayer PCB.
13 Static characteristics
Table 24. Static characteristics
VDD = 3 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
3
-
5.5
V
Supply
VDD
supply voltage
IDD
supply current
PCA9952_PCA9955
Product data sheet
on pin VDD; operating mode; no load;
fSCL = 1 MHz
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Table 24. Static characteristics...continued
VDD = 3 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; unless otherwise specified.
Symbol
IDD
Istb
VPOR
VPDR
Parameter
supply current
standby current
power-on reset voltage
power-down reset voltage
Conditions
Min
Typ
Max
Unit
VDD = 3.3 V
-
6.5
14
mA
VDD = 5.5 V
-
7.0
15
mA
Rext = open; LED[15:0] = off
-
0.7
14
mA
Rext = 2 kΩ; LED[15:0] = off
-
2
14
mA
Rext = 1 kΩ; LED[15:0] = off
-
3
15
mA
Rext = 2 kΩ; LED[15:0] = on
-
2
15
mA
Rext = 1 kΩ; LED[15:0] = on
-
3
16
mA
VDD = 3.3 V
-
100
600
μA
VDD = 5.5 V
-
100
700
μA
-
2.65
2.8
V
0.8
1.25
-
V
-
+0.3VDD V
on pin VDD; no load; fSCL = 0 Hz;
MODE1[4] = 1; VI = VDD
no load; VI = VDD or VSS
no load; VI = VDD or VSS
[1]
Input SCL; input/output SDA
VIL
LOW-level input voltage
-0.5
VIH
HIGH-level input voltage
0.7VDD -
5.5
V
IOL
LOW-level output current
VOL = 0.4 V; VDD = 3 V
20
-
-
mA
VOL = 0.4 V; VDD = 5.0 V
30
-
-
mA
IL
leakage current
VI = VDD or VSS
-1
-
+1
μA
Ci
input capacitance
VI = VSS
-
6
10
pF
Rext = 1 kΩ
52
57.5
62
mA
Rext = 2 kΩ
25.5
28.5
31.5
mA
between bits (different ICs, same
channel); Rext = 1 kΩ
-
±2.5
±8
%
between bits (2 channels, same
IC); Rext = 2 kΩ
-
±1.7
±5.8
%
Current controlled outputs (LED[15:0])
IO
ΔIO
output current
output current variation
VO = 0.8 V; IREFx = FFh
VO = 0.8 V; IREFx = FFh
Vreg(drv)
driver regulation voltage
minimum regulation voltage; IREFx =
FFh; Rext = 1 kΩ
0.8
1.0
40
V
IL(off)
off-state leakage current
VO = 40 V
-1.0
-
+1
μA
Vth(L)
LOW-level threshold voltage
open LED protection; Error flag will
trip during verification test if VO ≤ Vth(L)
-
0.35
-
V
Vth(H)
HIGH-level threshold voltage
short LED protection; Error flag will
trip during verification test if VO ≥
Vth(H)
-
2.5
-
V
Address inputs, OE input (PCA9952 only), RESET input
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Table 24. Static characteristics...continued
VDD = 3 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
VIL
Conditions
Min
Typ
Max
Unit
LOW-level input voltage
-0.5
-
+0.3VDD V
VIH
HIGH-level input voltage
0.7VDD -
5.5
V
ILI
input leakage current
-1
-
+1
μA
Ci
input capacitance
-
3.7
5
pF
rising
125
145
160
°C
hysteresis
-
20
-
°C
Overtemperature protection
Tth(otp)
[1]
overtemperature protection
threshold temperature
VDD must be lowered to 0.8 V in order to reset part.
14 Dynamic characteristics
Table 25. Dynamic characteristics
Symbol
Parameter
Conditions
Standard2
mode I C-bus
Fast-mode
2
I C-bus
Fast-mode Unit
2
Plus I C-bus
Min
Max
Min
Max
Min
0
100
0
400
0
Max
fSCL
SCL clock frequency
1000 kHz
tBUF
bus free time between a STOP
and START condition
4.7
-
1.3
-
0.5
-
μs
tHD;STA
hold time (repeated) START
condition
4.0
-
0.6
-
0.26
-
μs
tSU;STA
set-up time for a repeated
START condition
4.7
-
0.6
-
0.26
-
μs
tSU;STO
set-up time for STOP condition
4.0
-
0.6
-
0.26
-
μs
tHD;DAT
data hold time
-
ns
0
-
0
-
0
data valid acknowledge time
[1]
0.3
3.45
0.1
0.9
0.05
0.45 μs
tVD;DAT
data valid time
[2]
0.3
3.45
0.1
0.9
0.05
0.45 μs
tSU;DAT
data set-up time
250
-
100
-
50
-
ns
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
0.5
-
μs
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
tVD;ACK
[3][4]
tf
fall time of both SDA and SCL
signals
tr
rise time of both SDA and SCL
signals
tSP
pulse width of spikes that must
be suppressed by the input filter
tw(rst)
reset pulse width
tPLH
LOW to HIGH propagation
delay
PCA9952_PCA9955
Product data sheet
[6]
OE to LEDn
disable
[7]
-
0.26
-
μs
[5]
0.1Cb
300
-
120
ns
[5]
300
-
120
ns
-
300
20 +
-
1000
20 + 0.1Cb
-
50
-
50
-
50
ns
2.5
-
2.5
-
2.5
-
μs
-
1.2
-
1.2
-
1.2
μs
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Table 25. Dynamic characteristics...continued
Symbol
tPHL
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Parameter
Conditions
HIGH to LOW propagation
delay
OE to LEDn
enable
Standard2
mode I C-bus
[7]
Fast-mode
2
I C-bus
Fast-mode Unit
2
Plus I C-bus
Min
Max
Min
Max
Min
Max
-
1.2
-
1.2
-
1.2
μs
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the
undefined region of SCL’s falling edge.
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified at 250 ns. This
allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum
specified tf.
Cb = total capacitance of one bus line in pF.
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
Load resistor (RL) for LEDn is 100 Ω pull-up to VDD.
0.7 × VDD
SDA
0.3 × VDD
tr
tBUF
tf
tHD;STA
tSP
tLOW
0.7 × VDD
SCL
0.3 × VDD
P
S
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
Sr
tSU;STA
tSU;STO
P
002aaa986
Figure 21. Definition of timing
protocol
START
condition
(S)
tSU;STA
bit 7
MSB
(A7)
tLOW
bit 6
(A6)
tHIGH
bit 1
(D1)
bit 0
(D0)
acknowledge
(A)
STOP
condition
(P)
1 / fSCL
0.7 × VDD
SCL
tBUF
tr
0.3 × VDD
tf
0.7 × VDD
SDA
0.3 × VDD
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
002aab285
Rise and fall times refer to VIL and VIH.
2
Figure 22. I C-bus timing diagram
PCA9952_PCA9955
Product data sheet
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16-channel Fm+ I C-bus 57 mA constant current LED driver
OE
tPLH
tPHL
output data
002aag604
Figure 23. Output propagation delay
15 Test information
VDD
PULSE
GENERATOR
VI
DUT
VO
RT
RL
50
VLED
open
VSS
CL
50 pF
002aag289
RL = Load resistor for LEDn. RL for SDA = 165 Ω (30 mA or less current).
CL = Load capacitance includes jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generators.
Figure 24. Test circuitry for switching times
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16 Package outline
HTSSOP28: plastic thermal enhanced thin shrink small outline package; 28 leads;
body width 4.4 mm; lead pitch 0.65 mm; exposed die pad
SOT1172-2
D
E
A
X
c
y
exposed die pad side
Z
HE
v
A
Dh
28
15
Q
Eh
A2
pin 1 index
A
A1
A3
θ
Lp
1
L
14
e
w
bp
0
detail X
2.5
5 mm
scale
Dimensions
Unit
mm
max
nom
min
A
1.1
A1
A2
A3
bp
c
0.15 0.95
0.30 0.20
0.10 0.90 0.25 0.22 0.15
0.05 0.85
0.19 0.10
D(1)
Dh
E(2)
Eh
e
HE
L
9.8
9.7
9.6
5.6
5.5
5.4
4.5
4.4
4.3
2.3
2.2
2.1
0.65
6.6
6.4
6.2
1.0
Lp
Q
0.75 0.40
0.62 0.37
0.50 0.3
v
w
y
Z
θ
0.2
0.13
0.1
0.80
0.63
0.50
8°
4°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
References
Outline
version
IEC
JEDEC
JEITA
SOT1172-2
---
MO-153
---
sot1172-2_po
European
projection
Issue date
10-07-06
10-07-13
Figure 25. Package outline SOT1172-2 (HTSSOP28)
PCA9952_PCA9955
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17 Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
18 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
PCA9952_PCA9955
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• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
18.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 26) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 26 and Table 27
Table 26. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 27. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 26.
PCA9952_PCA9955
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16-channel Fm+ I C-bus 57 mA constant current LED driver
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 26. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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19 Soldering: PCB footprints
Footprint information for reflow soldering of HTSSOP28 package
SOT1172-2
Hx
Gx
P2
0.125
nSPx
SPSx
SPx
nSPy
Hy
By
0.125
SPy
SPSy
SLy SPy tot
Gy
Ay
SPx tot
C
D2
(4x)
P1
D1
SLx
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder land plus solder paste
occupied area
DIMENSIONS in mm
P1
P2
Ay
By
C
D1
D2
SLx
SLy
0.65
0.75
7.45
4.50
1.35
0.40
0.60
5.75
2.45
Issue date
SPx tot SPy tot
5.50
2.20
SPSx
SPSy
nSPx
nSPy
0.125
0.125
7
3
SPx
SPy
Gx
Gy
Hx
Hy
0.70
0.70
9.50
4.75
11.80
7.70
11-07-06
12-05-21
sot1172-2_fr
Figure 27. PCB footprint for SOT1172-2 (HTSSOP28); reflow soldering
PCA9952_PCA9955
Product data sheet
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20 Abbreviations
Table 28. Abbreviations
Acronym
Description
ACK
Acknowledge
CDM
Charged-Device Model
DAC
Digital-to-Analog Converter
DUT
Device Under Test
EMI
ElectroMagnetic Interference
ESD
ElectroStatic Discharge
HBM
Human Body Model
2
I C-bus
Inter-Integrated Circuit bus
LED
Light Emitting Diode
LSB
Least Significant Bit
MSB
Most Significant Bit
PCB
Printed-Circuit Board
PWM
Pulse Width Modulation
RGB
Red/Green/Blue
RGBA
Red/Green/Blue/Amber
SMBus
System Management Bus
21 References
22 Revision history
Table 29. Revision history
Document ID
Release date
Data sheet status
Change
notice
Supersedes
PCA9952_PCA9955 v.7.2
20211026
Product data sheet
-
PCA9952_PCA9955 v.7.1
Modifications:
• Removed commercial devices PCA9952TW and PCA9955TW. Discontinued DN74
Dec 2013
PCA9952_PCA9955 v.7.1
20150629
Product data sheet
-
PCA9952_PCA9955 v.7
PCA9952_PCA9955 v.7
20130527
Product data sheet
-
PCA9952_PCA9955 v.6
PCA9952Q900_PCA9955Q900 v.1
PCA9952Q900_PCA9955Q900 v.1 20130426
Product data sheet
-
-
PCA9952_PCA9955 v.6
20130422
Product data sheet
-
PCA9952_PCA9955 v.5
PCA9952_PCA9955 v.5
20121001
Product data sheet
-
PCA9952_PCA9955 v.4
PCA9952_PCA9955 v.4
20120813
Product data sheet
-
PCA9952_PCA9955 v.3
PCA9952_PCA9955 v.3
20120418
Product data sheet
-
PCA9952_PCA9955 v.2
PCA9952_PCA9955 v.2
20120312
Product data sheet
-
PCA9952_PCA9955 v.1
PCA9952_PCA9955
Product data sheet
All information provided in this document is subject to legal disclaimers.
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© NXP B.V. 2021. All rights reserved.
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PCA9952; PCA9955
NXP Semiconductors
2
16-channel Fm+ I C-bus 57 mA constant current LED driver
Table 29. Revision history...continued
Document ID
Release date
Data sheet status
Change
notice
Supersedes
PCA9952_PCA9955 v.1
20111202
Product data sheet
-
-
PCA9952_PCA9955
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7.2 — 26 October 2021
© NXP B.V. 2021. All rights reserved.
43 / 47
NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
23 Legal information
23.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
23.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
23.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
towards customer for the products described herein shall be limited in
accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their
applications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9952_PCA9955
Product data sheet
All information provided in this document is subject to legal disclaimers.
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NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
Suitability for use in automotive applications — This NXP product has
been qualified for use in automotive applications. If this product is used
by customer in the development of, or for incorporation into, products or
services (a) used in safety critical applications or (b) in which failure could
lead to death, personal injury, or severe physical or environmental damage
(such products and services hereinafter referred to as “Critical Applications”),
then customer makes the ultimate design decisions regarding its products
and is solely responsible for compliance with all legal, regulatory, safety,
and security related requirements concerning its products, regardless of
any information or support that may be provided by NXP. As such, customer
assumes all risk related to use of any products in Critical Applications and
NXP and its suppliers shall not be liable for any such use by customer.
Accordingly, customer will indemnify and hold NXP harmless from any
claims, liabilities, damages and associated costs and expenses (including
attorneys’ fees) that NXP may incur related to customer’s incorporation of
any product in a Critical Application.
PCA9952_PCA9955
Product data sheet
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
23.4 Trademarks
Notice: All referenced brands, product names, service names, and
trademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.
I2C-bus — logo is a trademark of NXP B.V.
All information provided in this document is subject to legal disclaimers.
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NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.
Tab. 11.
Tab. 12.
Tab. 13.
Tab. 14.
Ordering information ..........................................3
Ordering options ................................................3
PCA9952 pin description ...................................5
PCA9955 pin description ...................................6
Auto-Increment options ..................................... 9
Register summary ........................................... 10
MODE1 - Mode register 1 (address 00h) bit
description ....................................................... 12
MODE2 - Mode register 2 (address 01h) bit
description ....................................................... 12
LEDOUT0 to LEDOUT3 - LED driver output
state registers (address 02h to 05h) bit
description ....................................................... 13
GRPPWM - Group brightness control
register (address 08h) bit description .............. 14
GRPFREQ - Group frequency register
(address 09h) bit description ...........................14
PWM0 to PWM15 - PWM registers 0 to 15
(address 0Ah to 19h) bit description ................14
IREF0 to IREF15 - LEDn output gain
control registers (address 22h to 31h) bit
description ....................................................... 15
OFFSET - LEDn output delay offset
register (address 3Ah) bit description ..............16
Tab. 15.
Tab. 16.
Tab. 17.
Tab. 18.
Tab. 19.
Tab. 20.
Tab. 21.
Tab. 22.
Tab. 23.
Tab. 24.
Tab. 25.
Tab. 26.
Tab. 27.
Tab. 28.
Tab. 29.
SUBADR1 to SUBADR3 - I2C-bus
subaddress registers 1 to 3 (address 3Bh
to 3Dh) bit description ..................................... 17
ALLCALLADR - LED All Call I2Cbus address register (address 3Eh) bit
description ....................................................... 17
PWMALL - brightness control for all
LEDn outputs register (address 42h) bit
description ....................................................... 18
IREFALL - Output gain control for all LEDn
outputs (address 43h) bit description .............. 18
EFLAG0, EFLAG1 - Error flag registers
(address 44h, 45h) bit description ................... 20
Open-circuit detection ..................................... 21
Shorted-load detection .................................... 21
Limiting values ................................................ 32
Thermal characteristics ................................... 32
Static characteristics ....................................... 32
Dynamic characteristics .................................. 34
SnPb eutectic process (from J-STD-020D) ..... 39
Lead-free process (from J-STD-020D) ............ 39
Abbreviations ...................................................42
Revision history ...............................................42
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Fig. 14.
Fig. 15.
Block diagram of PCA9952/55 .......................... 4
Pin configuration for HTSSOP28 .......................5
PCA9955 slave address ....................................8
PCA9952 slave address ....................................8
Control register ..................................................9
Maximum ILED versus Rext ............................19
IO(target) versus IREFx value .........................20
SWRST Call .................................................... 23
Brightness + Group Dimming signals .............. 24
Bit transfer .......................................................24
Definition of START and STOP conditions ...... 25
System configuration .......................................25
Acknowledgement on the I2C-bus .................. 26
Write to a specific register ...............................26
Write to all registers using the AutoIncrement feature ............................................ 26
PCA9952_PCA9955
Product data sheet
Fig. 16.
Fig. 17.
Fig. 18.
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.
Fig. 24.
Fig. 25.
Fig. 26.
Fig. 27.
Multiple writes to Individual Brightness
registers only using the Auto-Increment
feature ............................................................. 27
Read all registers using the Auto-Increment
feature ............................................................. 28
Read of registers .............................................28
LED All Call I2C-bus address programming
and LED All Call sequence example ............... 29
Typical application (PCA9955) ........................ 30
Definition of timing .......................................... 35
I2C-bus timing diagram ................................... 35
Output propagation delay ................................36
Test circuitry for switching times ......................36
Package outline SOT1172-2 (HTSSOP28) ......37
Temperature profiles for large and small
components ..................................................... 40
PCB footprint for SOT1172-2 (HTSSOP28);
reflow soldering ............................................... 41
All information provided in this document is subject to legal disclaimers.
Rev. 7.2 — 26 October 2021
© NXP B.V. 2021. All rights reserved.
46 / 47
NXP Semiconductors
2
PCA9952; PCA9955
16-channel Fm+ I C-bus 57 mA constant current LED driver
Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.2
7.3
7.3.1
7.3.2
7.3.3
General description ............................................ 1
Features and benefits .........................................2
Applications .........................................................3
Ordering information .......................................... 3
Ordering options ................................................ 3
Block diagram ..................................................... 4
Pinning information ............................................ 5
Pinning ............................................................... 5
Pin description ................................................... 5
Functional description ........................................7
Device addresses .............................................. 7
Regular I2C-bus slave address ......................... 7
LED All Call I2C-bus address ............................8
LED bit Sub Call I2C-bus addresses ................. 8
Control register .................................................. 8
Register definitions .......................................... 10
MODE1 — Mode register 1 ............................. 12
MODE2 — Mode register 2 ............................. 12
LEDOUT0 to LEDOUT3, LED driver output
state ................................................................. 13
7.3.4
GRPPWM, group duty cycle control ................ 14
7.3.5
GRPFREQ, group frequency ........................... 14
7.3.6
PWM0 to PWM15, individual brightness
control .............................................................. 14
7.3.7
IREF0 to IREF15, LEDn output current
value registers ................................................. 15
7.3.8
OFFSET — LEDn output delay offset
register ............................................................. 16
7.3.9
LED bit Sub Call I2C-bus addresses for
PCA9952/55 .....................................................17
7.3.10
ALLCALLADR, LED All Call I2C-bus
address ............................................................ 17
7.3.11
RESERVED1 ................................................... 18
7.3.12
RESERVED2, RESERVED3 ........................... 18
7.3.13
PWMALL — brightness control for all LEDn
outputs ............................................................. 18
7.3.14
IREFALL register: output current value for
all LEDn outputs .............................................. 18
7.3.15
LED driver constant current outputs ................ 18
7.3.15.1 Adjusting output peak current ..........................18
7.3.16
LED error detection ......................................... 20
7.3.16.1 Open-circuit detection principle ....................... 21
7.3.16.2 Short-circuit detection principle ........................21
7.3.17
Overtemperature protection ............................. 21
7.4
Active LOW output enable input ...................... 22
7.5
Power-on reset ................................................ 22
7.6
Hardware reset recovery ................................. 22
7.7
Software reset ................................................. 22
7.8
Individual brightness control with group
dimming/blinking .............................................. 23
8
Characteristics of the I2C-bus ......................... 24
8.1
Bit transfer ....................................................... 24
8.1.1
START and STOP conditions .......................... 24
8.2
8.3
9
10
10.1
11
12
13
14
15
16
17
18
18.1
18.2
18.3
18.4
19
20
21
22
23
System configuration ....................................... 25
Acknowledge ....................................................25
Bus transactions ............................................... 26
Application design-in information ................... 30
Thermal considerations ................................... 30
Limiting values .................................................. 32
Thermal characteristics ....................................32
Static characteristics ........................................ 32
Dynamic characteristics ...................................34
Test information ................................................ 36
Package outline .................................................37
Handling information ........................................ 38
Soldering of SMD packages .............................38
Introduction to soldering .................................. 38
Wave and reflow soldering .............................. 38
Wave soldering ................................................ 38
Reflow soldering .............................................. 39
Soldering: PCB footprints ................................ 41
Abbreviations .................................................... 42
References ......................................................... 42
Revision history ................................................ 42
Legal information .............................................. 44
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 26 October 2021
Document identifier: PCA9952_PCA9955
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