PCA9957HNMP

PCA9957 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Rev. 2.1 — 22 October 2021 1 Product data sheet General description The PCA9957 is a daisy-chain SPI-compatible 4-wire serial bus controlled 24-channel constant current LED driver optimized for dimming and blinking 32 mA Red/Green/Blue/ Amber (RGBA) LEDs. Each LED output has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller that operates at 31.25 kHz with a duty cycle that is adjustable from 0 % to 100 % to allow the LED to be set to a specific brightness value. An additional 8-bit resolution (256 steps) group PWM controller has both a fixed frequency of 122 Hz and an adjustable frequency between 15 Hz to once every 16.8 seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to either dim or blink all LEDs with the same value. Each LED output can be off, on (no PWM control), set at its individual PWM controller value or at both individual and group PWM controller values. The PCA9957 operates with a supply voltage range of 2.7 V to 5.5 V and the constant current sink LED outputs allow up to 5 V for the LED supply. The output peak current is adjustable with an 8-bit linear DAC from 125 µA to 31.875 mA with REXT = 2 kΩ. Gradation control for all current sources is achieved via the 4-wire serial bus interface and allows user to ramp current automatically without MCU intervention. 8-bit DACs are available to adjust brightness levels for each LED current source. There are six selectable gradation control groups and each group has four independent registers to control ramp-up and ramp-down rate, step time, hold ON/OFF time and final hold ON output current. Two gradation operation modes are available for each group: single shot mode (output pattern once) and continuous mode (output pattern repeat). Each channel can be set to either gradation mode or normal mode and assigned to any one of these six gradation control groups. This device has built-in open, short load and overtemperature detection circuitry. The error information from the corresponding register can be read via the 4-wire serial bus. Additionally, a thermal shutdown feature protects the device when internal junction temperature exceeds the limit allowed for the process. The PCA9957 device is designed to use 4-wire read/write serial bus with higher data clock frequency (up to 10 MHz). The active LOW output enable input pin (OE) blinks all the LED outputs and can be used to externally PWM the outputs, which is useful when multiple devices need to be dimmed or blinked together without using software control. PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 2 Features and benefits • 24 LED drivers. Each output programmable at: – Off – On – 8 bits programmable LED brightness – 8 bits programmable group dimming/blinking mixed with individual LED brightness – Programmable LED output delay to reduce EMI and surge currents • Gradation control for all channels – Each channel can be assigned to one of six gradation control groups – Programmable gradation time and rate for ramp-up and/or ramp-down operations – Programmable step time (6-bit) from 0.5 ms (minimum) to 512 ms (maximum) – Programmable hold-on time after ramp-up and hold-off time after ramp-down (3-bit) from 0 s to 6 s – Programmable final ramp-up and hold-on current – Programmable brightness current output adjustment, either linear or exponential curve • 24 constant current output channels can sink up to 32 mA, and tolerate up to 5.5 V when OFF • Output current adjusted through an external resistor (REXT input) • Output current accuracy – ±6.5 % absolute accuracy with 30 mA output current – Maximum ±4 % channel to channel variation – Maximum ±6 % device to device variation • Open/short load/overtemperature detection mode to detect individual LED errors • 4-wire serial bus interface with 10 MHz data clock rate • 256-step (8-bit) linear programmable brightness per LED output varying from fully off (default) to maximum brightness fully ON using a 31.25 kHz PWM signal • 256-step group brightness control allows general dimming (using a 122 Hz PWM signal) from fully off to maximum brightness (default) • 256-step group blinking with frequency programmable from 15 Hz to 16.8 s and duty cycle from 0 % to 99.6 % • Active LOW Output Enable (OE) input pin allows for hardware blinking and dimming of the LEDs • 8 MHz internal oscillator requires no external components • Internal power-on reset • No glitch on LEDn outputs on power-up • Low standby current • Operating power supply voltage (VDD) range of 2.7 V to 5.5 V • 5.5 V tolerant inputs on non-LED pins • -40 °C to +85 °C operation • Latch-up performance exceeds 100 mA per JESD 78, Class II • ESD protection exceeds per JESD22: – 2 kV Human-Body Model (A114-A) – 1 kV Charged-Device Model (C101) • Package offered: HVQFN40 PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 2 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 3 Applications • • • • • • 4 RGB or RGBA LED drivers LED status information LED displays LCD backlights Keypad backlights for cellular phones or handheld devices Fade-in and fade-out for breathlight control Ordering information Table 1. Ordering information Type number PCA9957HN Topside mark P9957 Package Name Description Version HVQFN40 Plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 5 x 5 x 0.85 mm SOT1369-5 4.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method Minimum order quantity Temperature PCA9957HN PCA9957HNMP HVQFN40 Reel 13" Q2/T3 DP 6000 Tamb = -40 °C to +85 °C PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 3 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 5 Block diagram REXT LED0 LED1 LED22 LED23 I/O REGULATOR PCA9957 VDDIO DAC0 SCLK INPUT FILTER SDI DAC1 CS individual LED current setting 8-bit DACs 4-WIRE SERIAL BUS CONTROL SDO DAC 22 DAC 23 POWER-ON RESET VDD OUTPUT DRIVER, DELAY CONTROL, AND THERMAL SHUTDOWN VSS INPUT FILTER RESET LED STATE SELECT REGISTER PWM REGISTER X BRIGHTNESS CONTROL ÷ 256 31.25 kHz 8 MHz OSCILLATOR GRADATION CONTROL GRPFREQ REGISTER DIM CLOCK GRPPWM REGISTER MUX/ CONTROL '0' - permanently OFF '1' - permanently ON OE aaa-034472 Dim repetition rate = 122 Hz Blink repetition rate = 15 Hz to every 16.8 seconds Figure 1. Block diagram of PCA9957 PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 4 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 6 Pinning information 31 LED16 32 LED17 33 LED18 34 LED19 35 LED20 36 LED21 37 LED22 38 LED23 39 REXT 40 VSS 6.1 Pinning VDD 1 30 LED15 RESET VDDIO 2 29 LED14 3 28 LED13 SDO 4 27 LED12 SCLK 5 SDI 6 CS 7 24 LED9 OE 8 VSS 23 LED8 9 22 N/C N/C 10 21 VSS 26 LED11 LED7 20 LED6 19 25 LED10 LED5 18 LED4 17 LED3 16 LED2 15 LED1 14 LED0 13 N/C 12 TEST 11 PCA9957 aaa-034474 1. Thermal pad; connected to VSS. Figure 2. Pin configuration for HVQFN40 6.2 Pin description Table 3. Pin description PCA9957 Product data sheet Symbol Pin Type Description REXT 39 I current set resistor input; resistor to ground SDO 4 O serial data output CS 7 I active LOW chip select - when held HIGH the SDO pin is held LOW OE 8 I active LOW output enable for LEDs LED0 13 O LED driver 0 LED1 14 O LED driver 1 LED2 15 O LED driver 2 LED3 16 O LED driver 3 LED4 17 O LED driver 4 LED5 18 O LED driver 5 LED6 19 O LED driver 6 LED7 20 O LED driver 7 LED8 23 O LED driver 8 LED9 24 O LED driver 9 LED10 25 O LED driver 10 LED11 26 O LED driver 11 All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 5 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Table 3. Pin description...continued Symbol Pin Type Description LED12 27 O LED driver 12 LED13 28 O LED driver 13 LED14 29 O LED driver 14 LED15 30 O LED driver 15 LED16 31 O LED driver 16 LED17 32 O LED driver 17 LED18 33 O LED driver 18 LED19 34 O LED driver 19 LED20 35 O LED driver 20 LED21 36 O LED driver 21 LED22 37 O LED driver 22 LED23 38 O LED driver 23 RESET 2 I active LOW reset input with external 10 kΩ pull-up resistor SCLK 5 I serial clock line SDI 6 I serial data input ground supply ground VSS 9, 21, 40 VDDIO 3 power supply supply rail of SPI interface VDD 1 power supply supply voltage N/C 10, 12, 22 N/A no connection TEST 11 factory test internal pull down - connect to GND or leave floating [1] 7 [1] HVQFN40 package supply ground is connected to both VSS pins and exposed center pad. VSS pins must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. Functional description Refer to Figure 1. 7.1 Register address and data Following a chip select (CS) asserted condition (from HIGH to LOW), the data transfers are (16 × n) bits wide (where ‘n’ is the number of slaves in the chain) with MSB transferred first. The first 7 bits are the address of the register to be accessed. The eighth bit indicates the types of access — read (= 1) or write (= 0). The second group of 8 bits consists of data as shown in Figure 3. See Section 8 for more detail. PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 6 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 7-bit register address D15 D14 D13 D12 D11 D10 D9 data byte D8 D7 D6 D5 D4 D3 D2 D1 (MSB) D0 (LSB) R/W aaa-011888 Figure 3. Register address and data format for each slave 7.2 Register definitions Table 4. Register summary - default values Register # (hex) D7 D6 D5 D4 D3 D2 D1 D0 Name Type 00h 0 0 0 0 0 0 0 0 MODE1 read/write Mode register 1 01h 0 0 0 0 0 0 0 1 MODE2 read/write Mode register 2 02h 0 0 0 0 0 0 0 0 EFLAG0 read only output error flag 0 03h 0 0 0 0 0 0 0 0 EFLAG1 read only output error flag 1 04h 0 0 0 0 0 0 0 0 EFLAG2 read only output error flag 2 05h 0 0 0 0 0 0 0 0 EFLAG3 read only output error flag 3 06h 0 0 0 0 0 0 0 0 EFLAG4 read only output error flag 4 07h 0 0 0 0 0 0 0 0 EFLAG5 read only output error flag 5 08h 1 0 1 0 1 0 1 0 LEDOUT0 read/write LED output state 0 09h 1 0 1 0 1 0 1 0 LEDOUT1 read/write LED output state 1 0Ah 1 0 1 0 1 0 1 0 LEDOUT2 read/write LED output state 2 0Bh 1 0 1 0 1 0 1 0 LEDOUT3 read/write LED output state 3 0Ch 1 0 1 0 1 0 1 0 LEDOUT4 read/write LED output state 4 0Dh 1 0 1 0 1 0 1 0 LEDOUT5 read/write LED output state 5 0Eh 1 1 1 1 1 1 1 1 GRPPWM read/write group duty cycle control 0Fh 0 0 0 0 0 0 0 0 GRPFREQ read/write group frequency 10h 0 0 0 0 0 0 0 0 PWM0 read/write brightness control LED0 11h 0 0 0 0 0 0 0 0 PWM1 read/write brightness control LED1 12h 0 0 0 0 0 0 0 0 PWM2 read/write brightness control LED2 13h 0 0 0 0 0 0 0 0 PWM3 read/write brightness control LED3 14h 0 0 0 0 0 0 0 0 PWM4 read/write brightness control LED4 15h 0 0 0 0 0 0 0 0 PWM5 read/write brightness control LED5 16h 0 0 0 0 0 0 0 0 PWM6 read/write brightness control LED6 17h 0 0 0 0 0 0 0 0 PWM7 read/write brightness control LED7 18h 0 0 0 0 0 0 0 0 PWM8 read/write brightness control LED8 19h 0 0 0 0 0 0 0 0 PWM9 read/write brightness control LED9 1Ah 0 0 0 0 0 0 0 0 PWM10 read/write brightness control LED10 1Bh 0 0 0 0 0 0 0 0 PWM11 read/write brightness control LED11 1Ch 0 0 0 0 0 0 0 0 PWM12 read/write brightness control LED12 PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 Function © NXP B.V. 2021. All rights reserved. 7 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Table 4. Register summary - default values...continued Register # (hex) D7 D6 D5 D4 D3 D2 D1 D0 Name Type 1Dh 0 0 0 0 0 0 0 0 PWM13 read/write brightness control LED13 1Eh 0 0 0 0 0 0 0 0 PWM14 read/write brightness control LED14 1Fh 0 0 0 0 0 0 0 0 PWM15 read/write brightness control LED15 20h 0 0 0 0 0 0 0 0 PWM16 read/write brightness control LED16 21h 0 0 0 0 0 0 0 0 PWM17 read/write brightness control LED17 22h 0 0 0 0 0 0 0 0 PWM18 read/write brightness control LED18 23h 0 0 0 0 0 0 0 0 PWM19 read/write brightness control LED19 24h 0 0 0 0 0 0 0 0 PWM20 read/write brightness control LED20 25h 0 0 0 0 0 0 0 0 PWM21 read/write brightness control LED21 26h 0 0 0 0 0 0 0 0 PWM22 read/write brightness control LED22 27h 0 0 0 0 0 0 0 0 PWM23 read/write brightness control LED23 28h 0 0 0 0 0 0 0 0 IREF0 read/write output gain control register 0 29h 0 0 0 0 0 0 0 0 IREF1 read/write output gain control register 1 2Ah 0 0 0 0 0 0 0 0 IREF2 read/write output gain control register 2 2Bh 0 0 0 0 0 0 0 0 IREF3 read/write output gain control register 3 2Ch 0 0 0 0 0 0 0 0 IREF4 read/write output gain control register 4 2Dh 0 0 0 0 0 0 0 0 IREF5 read/write output gain control register 5 2Eh 0 0 0 0 0 0 0 0 IREF6 read/write output gain control register 6 2Fh 0 0 0 0 0 0 0 0 IREF7 read/write output gain control register 7 30h 0 0 0 0 0 0 0 0 IREF8 read/write output gain control register 8 31h 0 0 0 0 0 0 0 0 IREF9 read/write output gain control register 9 32h 0 0 0 0 0 0 0 0 IREF10 read/write output gain control register 10 33h 0 0 0 0 0 0 0 0 IREF11 read/write output gain control register 11 34h 0 0 0 0 0 0 0 0 IREF12 read/write output gain control register 12 35h 0 0 0 0 0 0 0 0 IREF13 read/write output gain control register 13 36h 0 0 0 0 0 0 0 0 IREF14 read/write output gain control register 14 37h 0 0 0 0 0 0 0 0 IREF15 read/write output gain control register 15 38h 0 0 0 0 0 0 0 0 IREF16 read/write output gain control register 16 39h 0 0 0 0 0 0 0 0 IREF17 read/write output gain control register 17 3Ah 0 0 0 0 0 0 0 0 IREF18 read/write output gain control register 18 3Bh 0 0 0 0 0 0 0 0 IREF19 read/write output gain control register 19 3Ch 0 0 0 0 0 0 0 0 IREF20 read/write output gain control register 20 3Dh 0 0 0 0 0 0 0 0 IREF21 read/write output gain control register 21 3Eh 0 0 0 0 0 0 0 0 IREF22 read/write output gain control register 22 3Fh 0 0 0 0 0 0 0 0 IREF23 read/write output gain control register 23 PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 Function © NXP B.V. 2021. All rights reserved. 8 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Table 4. Register summary - default values...continued Register # (hex) D7 D6 D5 D4 D3 D2 D1 D0 Name 40h 0 0 0 0 0 0 0 0 RAMP_RATE_GRP0 read/write ramp enable and rate control for group 0 41h 0 0 0 0 0 0 0 0 STEP_TIME_GRP0 42h 0 0 0 0 0 0 0 0 HOLD_CNTL_GRP0 read/write hold ON/OFF time control for group 0 43h 0 0 0 0 0 0 0 0 IREF_GRP0 44h 0 0 0 0 0 0 0 0 RAMP_RATE_GRP1 read/write ramp enable and rate control for group 1 45h 0 0 0 0 0 0 0 0 STEP_TIME_GRP1 46h 0 0 0 0 0 0 0 0 HOLD_CNTL_GRP1 read/write hold ON/OFF time control for group 1 47h 0 0 0 0 0 0 0 0 IREF_GRP1 48h 0 0 0 0 0 0 0 0 RAMP_RATE_GRP2 read/write ramp enable and rate control for group 2 49h 0 0 0 0 0 0 0 0 STEP_TIME_GRP2 4Ah 0 0 0 0 0 0 0 0 HOLD_CNTL_GRP2 read/write hold ON/OFF time control for group 2 4Bh 0 0 0 0 0 0 0 0 IREF_GRP2 4Ch 0 0 0 0 0 0 0 0 RAMP_RATE_GRP3 read/write ramp enable and rate control for group 3 4Dh 0 0 0 0 0 0 0 0 STEP_TIME_GRP3 4Eh 0 0 0 0 0 0 0 0 HOLD_CNTL_GRP3 read/write hold ON/OFF time control for group 3 4Fh 0 0 0 0 0 0 0 0 IREF_GRP3 50h 0 0 0 0 0 0 0 0 RAMP_RATE_GRP4 read/write ramp enable and rate control for group 4 51h 0 0 0 0 0 0 0 0 STEP_TIME_GRP4 52h 0 0 0 0 0 0 0 0 HOLD_CNTL_GRP4 read/write hold ON/OFF time control for group 4 53h 0 0 0 0 0 0 0 0 IREF_GRP4 54h 0 0 0 0 0 0 0 0 RAMP_RATE_GRP5 read/write ramp enable and rate control for group 5 55h 0 0 0 0 0 0 0 0 STEP_TIME_GRP5 56h 0 0 0 0 0 0 0 0 HOLD_CNTL_GRP5 read/write hold ON/OFF time control for group 5 57h 0 0 0 0 0 0 0 0 IREF_GRP5 58h 0 0 0 0 0 0 0 0 GRAD_MODE_SEL0 read/write gradation mode select register for channel 7 to channel 0 59h 0 0 0 0 0 0 0 0 GRAD_MODE_SEL1 read/write gradation mode select register for channel 15 to channel 8 PCA9957 Product data sheet Type read/write step time control for group 0 read/write output gain control for group 0 read/write step time control for group 1 read/write output gain control for group 1 read/write step time control for group 2 read/write output gain control for group 2 read/write step time control for group 3 read/write output gain control for group 3 read/write step time control for group 4 read/write output gain control for group 4 read/write step time control for group 5 read/write output gain control for group 5 All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 Function © NXP B.V. 2021. All rights reserved. 9 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Table 4. Register summary - default values...continued Register # (hex) D7 D6 D5 D4 D3 D2 D1 D0 Name Type Function 5Ah 0 0 0 0 0 0 0 0 GRAD_MODE_SEL2 read/write gradation mode select register for channel 23 to channel 16 5Bh 0 0 0 0 0 0 0 0 GRAD_GRP_SEL0 read/write gradation group select for channel 1 to channel 0 5Ch 0 0 0 0 0 0 0 0 GRAD_GRP_SEL1 read/write gradation group select for channel 3 to channel 2 5Dh 0 0 0 1 0 0 0 1 GRAD_GRP_SEL2 read/write gradation group select for channel 5 to channel 4 5Eh 0 0 0 1 0 0 0 1 GRAD_GRP_SEL3 read/write gradation group select for channel 7 to channel 6 5Fh 0 0 1 0 0 0 1 0 GRAD_GRP_SEL4 read/write gradation group select for channel 9 to channel 8 60h 0 0 1 0 0 0 1 0 GRAD_GRP_SEL5 read/write gradation group select for channel 11 to channel 10 61h 0 0 1 1 0 0 1 1 GRAD_GRP_SEL6 read/write gradation group select for channel 13 to channel 12 62h 0 0 1 1 0 0 1 1 GRAD_GRP_SEL7 read/write gradation group select for channel 15 to channel 14 63h 0 1 0 0 0 1 0 0 GRAD_GRP_SEL8 read/write gradation group select for channel 17 to channel 16 64h 0 1 0 0 0 1 0 0 GRAD_GRP_SEL9 read/write gradation group select for channel 19 to channel 18 65h 0 1 0 1 0 1 0 1 GRAD_GRP_SEL10 read/write gradation group select for channel 21 to channel 20 66h 0 1 0 1 0 1 0 1 GRAD_GRP_SEL11 read/write gradation group select for channel 23 to channel 22 67h 0 0 0 0 0 0 0 0 GRAD_CNTL0 read/write gradation control register for group 3 to group 0 68h 0 0 0 0 0 0 0 0 GRAD_CNTL1 read/write gradation control register for group 5 to group 4 69h 0 0 0 0 1 0 0 0 OFFSET read/write Offset/delay on LEDn outputs 6Ah 0 0 0 0 0 0 0 0 PWMALL write only brightness control for all LEDn 6Bh 0 0 0 0 0 0 0 0 IREFALL write only output gain control for all registers IREF0 to IREF23 : : : : : : : : reserved 6Ch to [1] read only not used 7Fh [1] Reserved registers should not be written to - default is 0 PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 10 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 7.2.1 MODE1 — Mode register 1 Table 5. MODE1 - Mode register 1 (address 00h) bit description Legend: * default value. Bit Symbol Access Value Description 7 - read only 0* reserved 6 - R/W 0* reserved 5 - R/W 0* reserved 4 SLEEP R/W 0* Normal mode . 1 Low-power mode. Oscillator off [1] 3 - R/W 0* reserved 2 - R/W 0* reserved 1 - R/W 0* reserved 0 - R/W 0* reserved [1] [2] [3] [2][3] . It takes 500 µs max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 µs window. No blinking, dimming or gradation control is possible when the oscillator is off. The device must be reset if the LED driver output state is set to LDRx=11 after the device is set back to Normal mode. 7.2.2 MODE2 — Mode register 2 Table 6. MODE2 - Mode register 2 (address 01h) bit description Legend: * default value. Bit Symbol Access Value Description 7 OVERTEMP read only 0* O.K. 1 overtemperature condition 0* no error at LED outputs 1 any open or short-circuit detected in error flag registers (EFLAGn) 0* group control = dimming 1 group control = blinking 0* self clear after write ‘1’ 1 Write ‘1’ to clear all error status bits in EFLAGn register and ERROR (bit 6). The EFLAGn and ERROR bit will set to ‘1’ if open or short-circuit is detected again. 0* Disable the channel for which open or short error is detected and enable it again when write 1 to CLRERR, clears all error status bits in EFLAGn registers and ERROR bit 1 The channel won’t be turned off when open/short detected 0* linear adjustment for gradation control 1 exponential adjustment for gradation control 6 5 4 3 2 PCA9957 Product data sheet ERROR DMBLNK CLRERR read only R/W write only AUTO_ R/W SWITCHOFF_ DIS EXP_EN R/W All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 11 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Table 6. MODE2 - Mode register 2 (address 01h) bit description...continued Legend: * default value. Bit Symbol Access Value Description 1 - read only 0* reserved 0 - read only 1* reserved Brightness adjustment for gradation control is either linear or exponential by setting the EXP_EN bit as shown in Figure 4. When EXP_EN = 0, linear adjustment scale is used. When EXP_EN = 1, exponential scale is used. 002aah635 255 IREF_OUT 200 EXP_EN = 0 150 100 EXP_EN = 1 50 0 0 50 100 150 200 IREF_IN 255 Figure 4. Linear and exponential adjustment curves 7.2.3 LEDOUT0 to LEDOUT5, LED driver output state Table 7. LEDOUT0 to LEDOUT5 - LED driver output state registers (address 08h to 0Dh) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 08h LEDOUT0 7:6 LDR3 R/W 10* LED3 output state control 5:4 LDR2 R/W 10* LED2 output state control 3:2 LDR1 R/W 10* LED1 output state control 1:0 LDR0 R/W 10* LED0 output state control 7:6 LDR7 R/W 10* LED7 output state control 5:4 LDR6 R/W 10* LED6 output state control 3:2 LDR5 R/W 10* LED5 output state control 1:0 LDR4 R/W 10* LED4 output state control 7:6 LDR11 R/W 10* LED11 output state control 09h 0Ah PCA9957 Product data sheet LEDOUT1 LEDOUT2 All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 12 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Table 7. LEDOUT0 to LEDOUT5 - LED driver output state registers (address 08h to 0Dh) bit description...continued Legend: * default value. Address 0Bh 0Ch 0Dh Register LEDOUT3 LEDOUT4 LEDOUT5 Bit Symbol Access Value Description 5:4 LDR10 R/W 10* LED10 output state control 3:2 LDR9 R/W 10* LED9 output state control 1:0 LDR8 R/W 10* LED8 output state control 7:6 LDR15 R/W 10* LED15 output state control 5:4 LDR14 R/W 10* LED14 output state control 3:2 LDR13 R/W 10* LED13 output state control 1:0 LDR12 R/W 10* LED12 output state control 7:6 LDR19 R/W 10* LED19 output state control 5:4 LDR18 R/W 10* LED18 output state control 3:2 LDR17 R/W 10* LED17 output state control 1:0 LDR16 R/W 10* LED16 output state control 7:6 LDR23 R/W 10* LED23 output state control 5:4 LDR22 R/W 10* LED22 output state control 3:2 LDR21 R/W 10* LED21 output state control 1:0 LDR20 R/W 10* LED20 output state control LDRx = 00 LED driver x is off (x = 0 to 23). LDRx = 01 LED driver x is fully on (individual brightness and group dimming/blinking not controlled). The OE pin can be used as external dimming/blinking control in this state. LDRx = 10 LED driver x individual brightness can be controlled through its PWMx register (default power-up state) or PWMALL register for all LEDn outputs. LDRx = 11 LED driver x individual brightness and group dimming/blinking can be controlled through its PWMx register and the GRPPWM registers. Remark: Setting the device in low power mode while being on group dimming/blinking mode (LDRx = 11) may cause the LED output state to be in an unknown state after the device is set back to normal mode. The device must be reset and all register values reprogrammed. PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 13 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 7.2.4 GRPPWM, group duty cycle control Table 8. GRPPWM - Group brightness control register (address 0Eh) bit description Legend: * default value Address Register Bit Symbol Access Value Description 0Eh GRPPWM 7:0 GDC[7:0] R/W 1111 1111* GRPPWM register When DMBLNK bit (MODE2 register) is programmed with logic 0, a 122 Hz fixed frequency signal is superimposed with the 31.25 kHz individual brightness control signal. GRPPWM is then used as a global brightness control allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’. General brightness for the 24 outputs is controlled through 255 linear steps from 00h (0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness). Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3 registers). When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPFREQ contains the blinking period (from 67 ms to 16.8 s) and GRPPWM the duty cycle (ON/OFF ratio in %). (1) 7.2.5 GRPFREQ, group frequency Table 9. GRPFREQ - Group frequency register (address 0Fh) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 0Fh GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000* GRPFREQ register GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2 register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0. Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3 registers). Blinking period is controlled through 256 linear steps from 00h (67 ms, frequency 15 Hz) to FFh (16.8 s). (2) 7.2.6 PWM0 to PWM23, individual brightness control Table 10. PWM0 to PWM23 - PWM registers 0 to 23 (address 10h to 27h) bit description Legend: * default value. PCA9957 Product data sheet Address Register Bit Symbol Access Value 10h PWM0 7:0 IDC0[7:0] R/W 0000 0000* PWM0 Individual Duty Cycle 11h PWM1 7:0 IDC1[7:0] R/W 0000 0000* PWM1 Individual Duty Cycle 12h PWM2 7:0 IDC2[7:0] R/W 0000 0000* PWM2 Individual Duty Cycle All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 Description © NXP B.V. 2021. All rights reserved. 14 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Table 10. PWM0 to PWM23 - PWM registers 0 to 23 (address 10h to 27h) bit description...continued Legend: * default value. Address Register Bit Symbol Access Value Description 13h PWM3 7:0 IDC3[7:0] R/W 0000 0000* PWM3 Individual Duty Cycle 14h PWM4 7:0 IDC4[7:0] R/W 0000 0000* PWM4 Individual Duty Cycle 15h PWM5 7:0 IDC5[7:0] R/W 0000 0000* PWM5 Individual Duty Cycle 16h PWM6 7:0 IDC6[7:0] R/W 0000 0000* PWM6 Individual Duty Cycle 17h PWM7 7:0 IDC7[7:0] R/W 0000 0000* PWM7 Individual Duty Cycle 18h PWM8 7:0 IDC8[7:0] R/W 0000 0000* PWM8 Individual Duty Cycle 19h PWM9 7:0 IDC9[7:0] R/W 0000 0000* PWM9 Individual Duty Cycle 1Ah PWM10 7:0 IDC10[7:0] R/W 0000 0000* PWM10 Individual Duty Cycle 1Bh PWM11 7:0 IDC11[7:0] R/W 0000 0000* PWM11 Individual Duty Cycle 1Ch PWM12 7:0 IDC12[7:0] R/W 0000 0000* PWM12 Individual Duty Cycle 1Dh PWM13 7:0 IDC13[7:0] R/W 0000 0000* PWM13 Individual Duty Cycle 1Eh PWM14 7:0 IDC14[7:0] R/W 0000 0000* PWM14 Individual Duty Cycle 1Fh PWM15 7:0 IDC15[7:0] R/W 0000 0000* PWM15 Individual Duty Cycle 20h PWM16 7:0 IDC8[7:0] R/W 0000 0000* PWM16 Individual Duty Cycle 21h PWM17 7:0 IDC9[7:0] R/W 0000 0000* PWM17 Individual Duty Cycle 22h PWM18 7:0 IDC10[7:0] R/W 0000 0000* PWM18 Individual Duty Cycle 23h PWM19 7:0 IDC11[7:0] R/W 0000 0000* PWM19 Individual Duty Cycle 24h PWM20 7:0 IDC12[7:0] R/W 0000 0000* PWM20 Individual Duty Cycle 25h PWM21 7:0 IDC13[7:0] R/W 0000 0000* PWM21 Individual Duty Cycle 26h PWM22 7:0 IDC14[7:0] R/W 0000 0000* PWM22 Individual Duty Cycle 27h PWM23 7:0 IDC15[7:0] R/W 0000 0000* PWM23 Individual Duty Cycle A 31.25 kHz fixed frequency signal is used for each output. Duty cycle is controlled through 255 linear steps from 00h (0 % duty cycle = LED output off) to FEh (99.2 % duty cycle = LED output at maximum brightness) and FFh (100 % duty cycle = LED output completed ON). Applicable to LED outputs programmed with LDRx = 10 or 11 (LEDOUT0 to LEDOUT3 registers). (3) Remark: The first lower end 8 steps of PWM and the last (higher end) steps of PWM will not have effective brightness control of LEDs due to edge rate control of LED output pins. 7.2.7 IREF0 to IREF23, LED output current value registers These registers reflect the gain settings for output current for LED0 to LED23. PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 15 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Table 11. IREF0 to IREF23 - LED output gain control registers (address 28h to 3Fh) bit description Legend: * default value. Address Register Bit Access Value Description 28h IREF0 7:0 R/W 00h* LED0 output current setting 29h IREF1 7:0 R/W 00h* LED1 output current setting 2Ah IREF2 7:0 R/W 00h* LED2 output current setting 2Bh IREF3 7:0 R/W 00h* LED3 output current setting 2Ch IREF4 7:0 R/W 00h* LED4 output current setting 2Dh IREF5 7:0 R/W 00h* LED5 output current setting 2Eh IREF6 7:0 R/W 00h* LED6 output current setting 2Fh IREF7 7:0 R/W 00h* LED7 output current setting 30h IREF8 7:0 R/W 00h* LED8 output current setting 31h IREF9 7:0 R/W 00h* LED9 output current setting 32h IREF10 7:0 R/W 00h* LED10 output current setting 33h IREF11 7:0 R/W 00h* LED11 output current setting 34h IREF12 7:0 R/W 00h* LED12 output current setting 35h IREF13 7:0 R/W 00h* LED13 output current setting 36h IREF14 7:0 R/W 00h* LED14 output current setting 37h IREF15 7:0 R/W 00h* LED15 output current setting 38h IREF16 7:0 R/W 00h* LED16 output current setting 39h IREF17 7:0 R/W 00h* LED17 output current setting 3Ah IREF18 7:0 R/W 00h* LED18 output current setting 3Bh IREF19 7:0 R/W 00h* LED19 output current setting 3Ch IREF20 7:0 R/W 00h* LED20 output current setting 3Dh IREF21 7:0 R/W 00h* LED21 output current setting 3Eh IREF22 7:0 R/W 00h* LED22 output current setting 3Fh IREF23 7:0 R/W 00h* LED23 output current setting 7.2.8 Gradation control Gradation control is designed to use six independent groups of registers to program the full cycle of the gradation timing to implement on each selected channel. Each group has four registers to define the ramp rate, step time, hold ON/OFF time, and final hold ON current, as shown in Figure 5. PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 16 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver output current (mA) final current set in IREF_GRPx hold ON ramp-up ramp-down hold OFF T1 T2 T3 T4 full cycle T1 time (second) 002aah636 Figure 5. Gradation timing • The ‘final’ and ‘hold ON’ current is defined in IREF_GRPx register value × (125 µA if REXT = 2 kΩ). • Ramp rate value and enable/disable ramp operation is defined in RAMP_RATE_GRPx register. • Total number of ramp steps (or level changes) is calculated as ‘IREF_GRPx value’ ÷ ‘ramp rate value in RAMP_RATE_GRPx’. Rounds a number up to the next integer if the total number is not an integer. • Time for each step is calculated as ‘cycle time’ × ‘multiple factor’ bits in STEP_TIME_GRPx register. Minimum time for one step is 0.5 ms (0.5 ms × 1) and maximum time is 512 ms (8 ms × 64). • The ramp-up or ramp-down time (T1 or T3) is calculated as ‘(total steps + 1)’ × ‘step time’. • Hold ON or OFF time (T2 or T4) is defined in HOLD_CNTL_GRPx register in the range of 0/0.25/0.5/0.75/1/2/4/6 seconds. • Gradation start or stop with single shot mode (one full cycle only) or continuous mode (repeat full cycle) is defined in the GRAD_CNTL register for all groups. • Each channel can be assigned to one of these six groups in the GRAD_GRP_SELx register. • Each channel can set either normal mode or gradation mode operation in the GRAD_MODE_SELx register. To enable the gradation operation, the following steps are required: 1. Program all gradation control registers except the gradation start bit in GRAD_CNTL register. 2. Program either LDRx = 01 (LED fully ON mode) only, or LDRx = 10 or 11 (PWM control mode) with individual brightness control PWMx register for duty cycle. 3. Program output current value IREFx register to non-zero, which enables LED output. 4. Set the gradation start bit in GRAD_CNTL register for enabling gradation operation. PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 17 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 7.2.8.1 RAMP_RATE_GRP0 to RAMP_RATE_GRP5, ramp rate control registers Table 12. RAMP_RATE_GRP[0:3] - Ramp enable and rate control registers (address 40h, 44h, 48h, 4Ch, 50h, 54h) for each group bit description Legend: * default value. Address Register Bit Access Value Description 40h 44h 48h 4Ch 50h 54h RAMP_RATE_GRP0 RAMP_RATE_GRP1 RAMP_RATE_GRP2 RAMP_RATE_GRP3 RAMP_RATE_GRP4 RAMP_RATE_GRP5 7 R/W 0* Ramp-up disable 1 Ramp-up enable 0* Ramp-down disable 1 Ramp-down enable 0x00* Ramp rate value per step is defined [1][2] from 1 (00h) to 64 (3Fh) [1] [2] 6 5:0 R/W R/W Total number of ramp steps is defined as ‘IREF_GRP[7:0]’ ÷ ‘ramp_rate[5:0]’. (Round up to next integer if it is not an integer number.) Per step current increment or decrement is calculated by the (ramp_rate × Iref), where the Iref reference current is 125 µA (REXT = 2 kΩ). 7.2.8.2 STEP_TIME_GRP0 to STEP_TIME_GRP5, step time control registers Table 13. STEP_TIME_GRP[0:3] - Step time control registers (address 41h, 45h, 49h, 4Dh, 51h, 55h) for each group bit description Legend: * default value. Address Register Bit Access Value Description 41h 45h 49h 4Dh 51h 55h STEP_TIME_GRP0 STEP_TIME_GRP1 STEP_TIME_GRP2 STEP_TIME_GRP3 STEP_TIME_GRP4 STEP_TIME_GRP5 7 read only 0* reserved 6 R/W 0* Cycle time is set to 0.5 ms 1 Cycle time is set to 8 ms 0x00* Multiple factor per step, the multiple factor is defined from 1 [1] (00h) to 64 (3Fh) [1] PCA9957 Product data sheet 5:0 R/W Step time = cycle time (0.5 ms or 8 ms) × multiple factor (1 ~ 64); minimum step time is 0.5 ms and maximum step time is 512 ms. All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 18 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 7.2.8.3 HOLD_CNTL_GRP0 to HOLD_CNTL_GRP5, hold ON and OFF control registers Table 14. HOLD_CNTL_GRP[0:3] - Hold ON and OFF enable and time control registers (address 42h, 46h, 4Ah, 4Eh, 52h, 56h) for each group bit description Legend: * default value. Address Register Bit Access Value Description 42h 46h 4Ah 4Eh 52h 56h HOLD_CNTL_GRP0 HOLD_CNTL_GRP1 HOLD_CNTL_GRP2 HOLD_CNTL_GRP3 HOLD_CNTL_GRP4 HOLD_CNTL_GRP5 7 R/W 0* Hold ON disable 1 Hold ON enable 0* Hold OFF disable 1 Hold OFF enable [1] 6 R/W [1] 5:3 R/W 000* Hold ON time select: 000: 0 s 001: 0.25 s 010: 0.5 s 011: 0.75 s 100: 1 s 101: 2 s 110: 4 s 111: 6 s 2:0 R/W 000* Hold OFF time select: 000: 0 s 001: 0.25 s 010: 0.5 s 011: 0.75 s 100: 1 s 101: 2 s 110: 4 s 111: 6 s [1] Hold ON or OFF minimum time is 0 s and maximum time is 6 s. 7.2.8.4 IREF_GRP0 to IREF_GRP5, output gain control Table 15. IREF_GRP[0:3] - Final and hold ON output gain setting registers (address 43h, 47h, 4Bh, 4Fh, 53h, 57h) for each group bit description Legend: * default value. Address Register Bit Access Value Description 43h 47h 4Bh 4Fh 53h 57h IREF_GRP0 IREF_GRP1 IREF_GRP2 IREF_GRP3 IREF_GRP4 IREF_GRP5 7:0 R/W 00h* Final ramp-up and hold ON output [1] current gain setting [1] PCA9957 Product data sheet Output current = Iref × IREF_GRPx[7:0], where Iref is reference current. Iref = 125 µA if REXT = 2 kΩ, All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 19 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 7.2.8.5 GRAD_MODE_SEL0 to GRAD_MODE_SEL2, Gradation mode select registers Table 16. GRAD_MODE_SEL[0:1] - Gradation mode select register for channel 23 to channel 0 (address 58h, 59h, 5Ah) bit description Legend: * default value. Address Register 58h GRAD_MODE_SEL0 7:0 59h GRAD_MODE_SEL1 7:0 5Ah [1] [2] Bit GRAD_MODE_SEL2 7:0 [1][2] Access Value Description R/W 00* Normal operation mode for channel 7 to channel 0 FFh Gradation operation mode for channel 7 to channel 0 00* Normal operation mode for channel 15 to channel 8 FFh Gradation operation mode for channel 15 to channel 8 00* Normal operation mode for channel 23 to channel 16 FFh Gradation operation mode for channel 23 to channel 16 R/W R/W Each bit represents one channel that can set either 0 for normal mode (use IREFx to set individual LED output current), or 1 for gradation mode (use IREF_GRPx to set group LEDs output current.). In gradation mode, it only affects the source of the IREF current level and does not affect the PWMx operation or LEDOUTx registers’ function. It is possible to use the gradation feature, individual PWMx and group PWM simultaneously. 7.2.8.6 GRAD_GRP_SEL0 to GRAD_GRP_SEL11, Gradation group select registers Table 17. GRAD_GRP_SEL[0:3] - Gradation group select register for channel 23 to channel 0 (address 5Bh, 5Ch, 5Dh, 5Eh, 5Fh, 60h, 61h, 62h, 63h, 64h, 65h, 66h) bit description Legend: * default value. Bit Access Value Description 5Bh 7 R/W 0* Reserved 6:4 R/W 000* Gradation group select for LED1 output 3 R/W 0* Reserved 2:0 R/W 000* Gradation group select for LED0 output 7 R/W 0* Reserved 6:4 R/W 000* Gradation group select for LED3 output 3 R/W 0* Reserved 2:0 R/W 000* Gradation group select for LED2 output 7 R/W 0* Reserved 6:4 R/W 001* Gradation group select for LED5 output 3 R/W 0* Reserved 2:0 R/W 001* Gradation group select for LED4 output 7 R/W 0* Reserved 6:4 R/W 001* Gradation group select for LED7 output 3 R/W 0* Reserved 5Ch 5Dh 5Eh PCA9957 Product data sheet [1] Address Register GRAD_GRP_SEL0 GRAD_GRP_SEL1 GRAD_GRP_SEL2 GRAD_GRP_SEL3 All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 20 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Table 17. GRAD_GRP_SEL[0:3] - Gradation group select register for channel 23 to channel 0 (address 5Bh, 5Ch, 5Dh, 5Eh, 5Fh, 60h, 61h, 62h, 63h, 64h, 65h, 66h) bit description...continued Legend: * default value. Address Register 5Fh 60h 61h 62h 63h 64h 65h 66h PCA9957 Product data sheet GRAD_GRP_SEL4 GRAD_GRP_SEL5 GRAD_GRP_SEL6 GRAD_GRP_SEL7 GRAD_GRP_SEL8 GRAD_GRP_SEL9 [1] Bit Access Value Description 2:0 R/W 001* Gradation group select for LED6 output 7 R/W 0* Reserved 6:4 R/W 010* Gradation group select for LED9 output 3 R/W 0* Reserved 2:0 R/W 010* Gradation group select for LED8 output 7 R/W 0* Reserved 6:4 R/W 010* Gradation group select for LED11 output 3 R/W 0* Reserved 2:0 R/W 010* Gradation group select for LED10 output 7 R/W 0* Reserved 6:4 R/W 011* Gradation group select for LED13 output 3 R/W 0* Reserved 2:0 R/W 011* Gradation group select for LED12 output 7 R/W 0* Reserved 6:4 R/W 011* Gradation group select for LED15 output 3 R/W 0* Reserved 2:0 R/W 011* Gradation group select for LED14 output 7 R/W 0* Reserved 6:4 R/W 100* Gradation group select for LED17 output 3 R/W 0* Reserved 2:0 R/W 100* Gradation group select for LED16 output 7 R/W 0* Reserved 6:4 R/W 100* Gradation group select for LED19 output 3 R/W 0* Reserved 2:0 R/W 100* Gradation group select for LED18 output R/W 0* Reserved 6:4 R/W 101* Gradation group select for LED21 output 3 R/W 0* Reserved 2:0 R/W 101* Gradation group select for LED20 output R/W 0* Reserved 6:4 R/W 101* Gradation group select for LED23 output 3 R/W 0* Reserved 2:0 R/W 101* Gradation group select for LED22 output GRAD_GRP_SEL10 7 GRAD_GRP_SEL11 7 All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 21 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver [1] LED[3:0] outputs default assigned to group 0; LED[7:4] outputs default assigned to group 1; LED[11:8] outputs default assigned to group 2; LED[15:12] outputs default assigned to group 3; LED[19:16] outputs default assigned to group 4; LED[23:20] outputs default assigned to group 5. 7.2.8.7 GRAD_CNTL, Gradation control register Table 18. GRAD_CNTL[0:1] - Gradation control register for group 5 to group 0 (address 67h, 68h) bit description Legend: * default value. Address Register Bit Access Value Description 67h GRAD_CNTL0 7 R/W 0* Gradation stop or done for group 3 1 Gradation start for group 3 0* Single shot operation for group 3 1 Continuous operation for group 3 0* Gradation stop or done for group 2 1 Gradation start for group 2 0* Single shot operation for group 2 1 Continuous operation for group 2 0* Gradation stop or done for group 1 1 Gradation start for group 1 0* Single shot operation for group 1 1 Continuous operation for group 1 0* Gradation stop or done for group 0 1 Gradation start for group 0 0* Single shot operation for group 0 1 Continuous operation for group 0 0* Gradation stop or done for group 5 1 Gradation start for group 5 0* Single shot operation for group 5 1 Continuous operation for group 5 0* Gradation stop or done for group 4 1 Gradation start for group 4 0* Single shot operation for group 4 1 Continuous operation for group 4 0* Reserved 6 5 4 3 2 1 0 68h GRAD_CNTL1 7 6 5 4 3:0 [1] [2] PCA9957 Product data sheet R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R [1] [2] [1] [2] [1] [2] [1] [2] [1] [2] [1] [2] When the gradation operation is forced to stop, the output current stops immediately and is frozen at the last output level. This bit will be self-cleared when single mode is completed, and writing 0 to this bit will force to stop the gradation operation when single mode is not completed or continuous mode is running. All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 22 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 7.2.8.8 Ramp control — equation and calculation example IREF_GRPx (max. = 255) 125 µA × 250 = 31.25 mA 250 200 150 s1 100 50 (step time) (32 ms) 0 Start from current zero (step current) (6.25 mA) End with current zero t1 ramp-up hold ON ramp-down hold OFF (T = 192 ms) (0.25 s) (T = 192 ms) (0.5 s) full cycle time aaa-034477 Figure 6. Ramp calculation example 1 • t1 (step time) = cycle time × multiple factor, where: – Cycle time = 0.5 ms (fast ramp) or 8 ms (slow ramp) in STEP_TIME_GRPx[6] – Multiple factor = 6-bit, from 1 (00h) to 64 (3Fh) counts in STEP_TIME_GRPx[5:0] • s1 (step current) = ramp_rate × Iref, where: – ramp_rate = 6-bit, from 1 (00h) to 64 (3Fh) counts in RAMP_RATE_GRPx[5:0] – Iref = reference current of 125 µA if REXT = 2 kΩ • S (total steps) = (IREF_GRPx / ramp_rate), where: – IREF_GRPx = output current gain setting, 8-bit, up to 255 counts – ramp_rate = 6-bit, up to 64 counts in RAMP_RATE_GRPx[5:0] – If it is not an integer, then round up to next integer number. • T (ramp time) = (S (total steps) + 1) × t1 (step time) – Ramp-up time starts from zero current and ends at the maximum current – Ramp-down time starts from the maximum current and ends at the zero current Calculation example 1 (Figure 6): • Assumption: – Iref = 125 µA if REXT = 2 kΩ – Output hold ON current = 125 µA × 250 = 31.25 mA (IREF_GRPx[7:0] = FAh) – Cycle time = 0.5 ms (STEP_TIME_GRPx[6] = 0) – Multiple factor = 64 (STEP_TIME_GRPx[5:0] = 3Fh) – Ramp rate = 50 (RAMP_RATE_GRPx[5:0] = 31h) – Hold ON = 0.25 s (HOLD_CNTL_GRPx[5:3] = 001) – Hold OFF = 0.5 s (HOLD_CNTL_GRPx[2:0] = 010) • t1 (step time) = cycle time (0.5 ms) × multiple (64) = 32 ms • Step current = ramp_rate × Iref = 50 × 125 µA = 6.25 mA • S (total steps) = (IREF_GRPx ÷ ramp_rate) = (250 ÷ 50) = 5 steps • T (ramp time) = (S + 1) × t1 = 6 × 32 ms = 192 ms PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 23 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver IREF_GRPx (max. = 255) 240 (30 mA) 200 t1 (step time) (32 ms) 150 190 140 s1 100 (step current) 50 (6.25 mA) 0 90 40 ramp-up hold ON ramp-down hold OFF (T = 192 ms) (0.25 s) (T = 192 ms) (0.5 s) full cycle time aaa-034484 Figure 7. Ramp calculation example 2 Calculation example 2: • Assumption: – Iref = 125 µA if REXT = 2 kΩ – Output hold ON current = 125 µA × 240 = 30 mA (IREF_GRPx[7:0] = F0h) – Cycle time = 0.5 ms (STEP_TIME_GRPx[6] = 0) – Multiple factor = 64 (STEP_TIME_GRPx[5:0] = 3Fh) – Ramp rate = 50 (RAMP_RATE_GRPx[5:0] = 31h) – Hold ON = 0.25 s (HOLD_CNTL_GRPx[5:3] = 001) – Hold OFF = 0.5 s (HOLD_CNTL_GRPx[2:0] = 010) • t1 (step time) = cycle time (0.5 ms) × multiple (64) = 32 ms • Step current = ramp_rate × Iref = 50 × 125 µA = 6.25 mA (except the last one) • S (total steps) = IREF_GRPx ÷ ramp_rate = 240 ÷ 50 = 4.8 steps (round up to next integer) = 5 steps • T (ramp time) = (S + 1) × t1 = 6 × 32 ms = 192 ms PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 24 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver (enable bit) Ramp UP (enable bit) Hold ON (enable bit) Ramp DOWN (enable bit) Hold OFF 1 0 0 0 0 2 1 0 0 0 3 0 1 0 0 4 1 1 0 0 5 0 0 1 0 6 1 0 1 0 7 0 1 1 0 8 1 1 1 0 9 0 0 0 1 10 1 0 0 1 11 0 1 0 1 12 1 1 0 1 13 0 0 1 1 14 1 0 1 1 15 0 1 1 1 16 1 1 1 1 Single shot waveform Continuous waveform wavefrom when initial current is not zero the moment when START bit changes to 0 (single shot sequence ends) aaa-009234 Figure 8. Gradation output waveform in single shot or continuous mode 7.2.9 OFFSET — LEDn output delay offset register Table 19. OFFSET - LEDn output delay offset register (address 69h) bit description Legend: * default value. Address Register Bit Access Value Description 69h OFFSET 7:4 read only 0000* not used 3:0 R/W 1000* LEDn output delay offset factor (0000 1011) The PCA9957 can be programmed to have turn-on delay between LED outputs. This helps to reduce peak current for the VDD supply and reduces EMI. This turn-on delay also applies to OE pin when becomes low. The order in which the LED outputs are enabled will always be the same (channel 0 will enable first and channel 23 will enable last). OFFSET control register bits [3:0] determine the delay used between the turn-on times as follows, and the valid number is 0000 – 1011. The number greater than 1011 (such as 1100 - 1111) will have the same turn-on delay as 1011 setting (1.375 µS), and read back value will be changed to 1011: PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 25 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 0000 = no delay between outputs (all on, all off at the same time) 0001 = delay of 1 clock cycle (125 ns) between successive outputs 0010 = delay of 2 clock cycles (250 ns) between successive outputs 0011 = delay of 3 clock cycles (375 ns) between successive outputs : 1011 = delay of 11 clock cycles (1.375 µs) between successive outputs : 1111 = delay of 11 clock cycles (1.375 µs) between successive outputs Example: If the value in the OFFSET register is 1000, the corresponding delay = 8 × 125 ns = 1 µs delay between successive outputs. channel 0 turns on at time 0 µs channel 1 turns on at time 1 µs channel 2 turns on at time 2 µs channel 3 turns on at time 3 µs channel 4 turns on at time 4 µs channel 5 turns on at time 5 µs channel 6 turns on at time 6 µs channel 7 turns on at time 7 µs channel 8 turns on at time 8 µs channel 9 turns on at time 9 µs channel 10 turns on at time 10 µs channel 11 turns on at time 11 µs channel 12 turns on at time 12 µs channel 13 turns on at time 13 µs channel 14 turns on at time 14 µs channel 15 turns on at time 15 µs channel 16 turns on at time 16 µs channel 17 turns on at time 17 µs channel 18 turns on at time 18 µs channel 19 turns on at time 19 µs channel 20 turns on at time 20 µs channel 21 turns on at time 21 µs channel 22 turns on at time 22 µs channel 23 turns on at time 23 µs 7.2.10 PWMALL — brightness control for all LEDn outputs When programmed, the value in this register will be used for PWM duty cycle for all the LEDn outputs and will be reflected in PWM0 through PWM23 registers. Table 20. PWMALL - brightness control for all LEDn outputs register (address 6Ah) bit description Legend: * default value. Address Register Bit Access Value Description 6Ah PWMALL 7:0 write only 0000 0000* duty cycle for all LEDn outputs Remark: Write to any of the PWM0 to PWM23 registers will overwrite the value in corresponding PWMn register programmed by PWMALL. PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 26 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 7.2.11 IREFALL register: output current value for all LED outputs The output current setting for all outputs is held in this register. When this register is written to or updated, all LED outputs will be set to a current corresponding to this register value. Writes to IREF0 to IREF23 will overwrite the output current settings. Table 21. IREFALL - Output gain control for all LED outputs (address 6Bh) bit description Legend: * default value. Address Register Bit Access Value Description 6Bh IREFALL 7:0 write only 00h* Current gain setting for all LED outputs. 7.2.12 LED driver constant current outputs In LED display applications, PCA9957 provides nearly no current variations, the absolute accuracy is less than ± 6.5 %. 7.2.12.1 Adjusting output current The PCA9957 scales up the reference current (Iref) set by the external resistor (Rext) to sink the output current (IO) at each output port. The maximum output current for the outputs can be set using Rext. In addition, the constant value for current drive at each of the outputs is independently programmable using command registers IREF0 to IREF23. Alternatively, programming the IREFALL register allows all outputs to be set at one current value determined by the value in IREFALL register. Equation 4 and Equation 5 can be used to calculate the minimum and maximum constant current values that can be programmed for the outputs for a chosen Rext. (4) (5) For a given IREFx setting: PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 27 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver aaa-034486 80 IREFx = 255 IO(LEDn) (mA) 30 20 10 0 1 2 3 4 5 6 7 8 9 10 Rext (k ) IO(LEDn) (mA) = IREFx × (1 / 4) / Rext (kΩ) maximum IO(LEDn) (mA) = 255 × (1 / 4) / Rext (kΩ) Remark: Default IREFx at power-up = 0. Figure 9. Maximum ILED versus Rext Example 1: If Rext = 2 kΩ, IO_LED_MIN = 125.0 µA, IO_LED_MAX = 31.875 mA (as shown in Figure 10). So each channel can be programmed with its individual IREFx in 256 steps and in 125 µA increments to a maximum output current of 31.875 mA independently. aaa-034487 32 30 IO(target) (mA) 25 20 15 10 5 0 0 31 63 95 127 159 191 223 IREF[7:0] value 255 Figure 10. IO(target) versus IREFx value with Rext = 2 kΩ 7.2.13 LED error detection The PCA9957 is capable of detecting an LED open or a short condition at its open-drain LED outputs. Users will recognize these faults by reading the status of a pair of error bits (ERRx) in error flag registers (EFLAGn) for each channel. Both LDRx value in LEDOUTx registers and IREFx value must be set to ‘00’ for those unused LED output channels. If the output is selected to be fully on, individual dim, or individual and group dim, that channel will be tested. The user can poll the ERROR status bit (bit 6 in MODE2 register) to check if there is a fault condition in any of the 24 channels. The EFLAGn registers can then be read to determine which channels are at fault and the type of fault in those channels. PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 28 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver The error status reported by the EFLAGn register is real time information, when AUTO_SWITCHOFF_DIS = 1, it will get self cleared once the error is fixed or write ‘1’ to CLRERR bit (bit 4 in MODE2 register), when AUTO_SWITCHOFF_DIS = 0, PCA9957 will stop detection once error occurs, the EFLAGn register will keep the last error status until write ‘1’ to CLRERR bit or get reset. Remark: When LED outputs programmed with LDRx = 10 or 11 in LEDOUT[3:0] registers, checks for open and short-circuit will not occur if the PWM value in PWM0 to PWM23 registers is less than 8 or 255 (100 % duty cycle). Table 22. EFLAG0 to EFLAG5 - Error flag registers (address 02h to 07h) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 02h EFLAG0 7:6 ERR3 R only 00* Error status for LED3 output 5:4 ERR2 R only 00* Error status for LED2 output 3:2 ERR1 R only 00* Error status for LED1 output 1:0 ERR0 R only 00* Error status for LED0 output 7:6 ERR7 R only 00* Error status for LED7 output 5:4 ERR6 R only 00* Error status for LED6 output 3:2 ERR5 R only 00* Error status for LED5 output 1:0 ERR4 R only 00* Error status for LED4 output 7:6 ERR11 R only 00* Error status for LED11 output 5:4 ERR10 R only 00* Error status for LED10 output 3:2 ERR9 R only 00* Error status for LED9 output 1:0 ERR8 R only 00* Error status for LED8 output 7:6 ERR15 R only 00* Error status for LED15 output 5:4 ERR14 R only 00* Error status for LED14 output 3:2 ERR13 R only 00* Error status for LED13 output 1:0 ERR12 R only 00* Error status for LED12 output 7:6 ERR19 R only 00* Error status for LED19 output 5:4 ERR18 R only 00* Error status for LED18 output 3:2 ERR17 R only 00* Error status for LED17 output 1:0 ERR16 R only 00* Error status for LED16 output 7:6 ERR23 R only 00* Error status for LED23 output 5:4 ERR22 R only 00* Error status for LED22 output 3:2 ERR21 R only 00* Error status for LED21 output 1:0 ERR20 R only 00* Error status for LED20 output 03h 04h 05h 06h 07h PCA9957 Product data sheet EFLAG1 EFLAG2 EFLAG3 EFLAG4 EFLAG5 All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 29 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Table 23. ERRx bit description LED error detection status ERRx Description Bit 1 Bit 0 No error 0 0 In normal operation and no error Short-circuit 0 1 Detected LED short-circuit condition Open-circuit 1 0 Detected LED open-circuit condition DNE (Do Not Exist) 1 1 This condition does not exist 7.2.13.1 Open-circuit detection principle The PCA9957 LED open-circuit detection compares the effective current level IO with the open load detection threshold current Ith(det). If IO is below the threshold Ith(det), the PCA9957 detects an open load condition. This error status can be read out as an error flag through the EFLAGn registers. For open-circuit error detection of an output channel, that channel must be ON. Table 24. Open-circuit detection State of output port Condition of output Error status code current Description OFF IO = 0 mA ON [1] 0 detection not possible IO < [1] Ith(det) 1 open-circuit IO ≥ [1] Ith(det) this channel open error status normal bit is 0 Ith(det) = 0.5 × IO(target) (typical). This threshold may be different for each I/O and only depends on IREFx and Rext. 7.2.13.2 Short-circuit detection principle The LED short-circuit detection compares the effective output voltage level (VO) with the shorted-load detection threshold voltages Vth(trig). If VO is above the Vth(trig) threshold, the PCA9957 detects a shorted-load condition. If VO is below the Vth(trig) threshold, no error is detected and error bit is set to ‘0’. This error status can be read out as an error flag through the EFLAGn registers. For short-circuit error detection of an output channel, that channel must be ON. Table 25. Short-circuit detection State of output port Condition of output Error status code voltage Description OFF - ON [1] 0 detection not possible VO ≥ [1] Vth(trig) 1 short-circuit VO < [1] Vth(trig) this channel short error status normal bit is 0 Vth ≅ 1.96 V. Remark: The error status distinguishes between an LED short condition and an LED open condition. Upon detecting an LED short or open, the corresponding LED outputs should be turned OFF to prevent heat dissipation for a short in the chip. Although an open event will not be harmful, the outputs should be turned OFF for both occasions to repair the LED string. PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 30 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 7.2.14 Overtemperature protection If the PCA9957 chip temperature exceeds its limit (Tth(otp) (rising) maximum, see Table 28), all output channels will be disabled until the temperature drops below its limit minus a small hysteresis (Tth(otp) (hysteresis) maximum, see Table 28). When an overtemperature situation is encountered, the OVERTEMP flag (bit 7) is set in the MODE2 register. Once the die temperature reduces below the Tth(otp) rising - Tth(otp) hysteresis, the chip will return to the same condition it was prior to the overtemperature event and the OVERTEMP flag will be cleared. 7.3 Active LOW output enable input The active LOW output enable (OE) pin on PCA9957 allows to enable or disable all the LED outputs at the same time. • When a LOW level is applied to OE pin, all the LED outputs are enabled, LEDn output delay applies to this sequence. • When a HIGH level is applied to OE pin, all the LED outputs are high-impedance. The OE pin can be used as a synchronization signal to switch on/off several PCA9957 devices at the same time when LED drive output state is set fully ON (LDRx = 01 in LEDOUTx register) in these devices. This requires an external clock reference that provides blinking period and the duty cycle. The OE pin can also be used as an external dimming control signal. The frequency of the external clock must be high enough not to be seen by the human eye, and the duty cycle value determines the brightness of the LEDs. LEDn output delay controlled by register OFFSET also applies OE control. Remark: Do not use OE as an external blinking control signal when internal global blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an undefined blinking pattern. Do not use OE as an external dimming control signal when internal global dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an undefined dimming pattern. 7.4 Power-on reset When power is applied to VDD, an internal power-on reset holds the PCA9957 in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the PCA9957 registers and serial bus state machine are initialized to their default states (all zeroes) causing all the channels to be deselected. Thereafter, VDD must be pulled lower than 1 V and stay LOW for longer than 20 µs. The device will reset itself, and allow 2 ms for the device to fully wake up. 7.5 Hardware reset recovery When a reset of PCA9957 is activated using an active LOW input on the RESET pin, a reset pulse width of 2.5 µs minimum is required. The maximum wait time after RESET pin is released is 1.5 ms. 7.6 Individual brightness control with group dimming/blinking A 31.25 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control individually the brightness for each LED. PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 31 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver On top of this signal, one of the following signals can be superimposed (this signal can be applied to the 24 LED outputs LED0 to LED23). • A lower 122 Hz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to provide a global brightness control. • A programmable frequency signal from 15 Hz to every 16.8 seconds (8 bits, 256 steps) with programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking control. 1 2 3 4 5 6 7 8 9 10 11 12 251 252 253 254 255 256 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 Brightness Control signal (LEDn) N × 125 ns with N = (0 to 255) (PWMx Register) M × 256 × 125 ns with M = (0 to 255) (GRPPWM Register) 256 × 125 ns = 32 µs (31.25 kHz) Group Dimming signal 256 × 256 × 125 ns = 8.19 ms (122 Hz) 1 2 3 4 5 6 7 8 resulting Brightness + Group Dimming signal 002aaf935 Minimum pulse width for LEDn Brightness Control is 125 ns. Minimum pulse width for Group Dimming is 32 µs. When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal will have 1 pulse of the LED Brightness Control signal (pulse width = N × 125 ns, with ‘N’ defined in PWMx register). This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 8. Figure 11. Brightness + Group Dimming signals 8 Characteristics of the 4-wire SPI serial-bus interface The PCA9957 communicates through a daisy-chain SPI-compatible 4-wire serial interface. The interface has three inputs and one output: serial clock (SCLK), active LOW chip select (CS), serial data in (SDI) and serial data output (SDO). CS must be LOW to clock data into the device, and SDI must be stable when sampled on the rising edge of SCLK. The PCA9957 ignores all activity on SCLK and SDI except when CS is LOW. 8.1 SPI-compatible 4-wire serial interface signals CS The active LOW chip select line is used to activate and access the SPI slaves. As long as CS is HIGH, all slaves will not accept the clock signal or data, and output SDO is driven LOW, therefore SPI parallel connection is not supported. Whenever this pin is in a logic LOW state, data can be transferred between the master (controller) and all slaves (targets). SCLK Serial clock is provided by SPI master and determines the speed of the data transfer. All receiving and sending data are done synchronously (clocks the internal SPI shift register and the output driver) to this clock. PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 32 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver SDI Serial Data In is read on the rising edge of SCLK into the internal 16-bit shift registers. On the rising edge of CS, the input data is latched into the internal registers of the device. The device ignores all activity on SDI when CS is deasserted. SDO Serial Data Out is the pin on which the internal 16-bit shift registers data is shifted out serially. SDO is driven LOW until the CS pin goes to a logic LOW state. New data appears at the SDO pin following the falling edge of SCLK. All slave devices can be daisy-chained by connecting the SDO of one device to the SDI of the next device, and driving SCLK and CS lines in parallel. Figure 12 depicts how the slaves are connected to the master. All slave devices are accessed at the same time with CS. An access requires (16 × n) clock cycles, where ‘n’ is the number of slave devices. As long as CS is LOW, the SPI registers are working as simple shift registers and shifting through the SDI data without interpreting the different control and data bits. When CS goes back to HIGH, the bits in the SPI registers are interpreted and the SPI logic is activated. Only the first slave in the chain receives the control and data bits directly from the SPI Master. Every other slave in the network receives its SDI data from the SDO output of the preceding slave in the chain, and the SDO of the last slave is then connected to the data input (MISO) of SPI Master. Each slave has 16-bit shift registers shifted in from SDI and shifted out to SDO, along with the SCLK clock. The whole chain acts as a 48-bit (n × 16bit, where ‘n’ is number of slaves) big shift register. CS SPI MASTER CS SCLK MOSI MISO CS PCA9957 SCLK SDI (slave 1) PCA9957 SCLK SDI SDO (slave 2) SDO CS PCA9957 SCLK SDI (slave 3) SDO aaa-034488 Figure 12. System level connection 8.2 Data format As shown in Figure 13, the data transfers are 16-bit × n bits wide (where ‘n’ is the number of slaves) with MSB transferred first. The first 7 bits, D[15:9], form the address of the register to be accessed, the eighth bit (D8) indicates the types of access, either read (= 1) or write (= 0), and the last 8 bits, D[7:0], consist of data. Register read and write sequences (described in the following sections) always begin from the bus idle condition. The bus idle condition refers to CS being HIGH and SCLK being in a LOW state. first byte second byte D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB register address MSB R/W LSB data aaa-011890 Figure 13. Data format PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 33 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 8.3 Write access sequence The registers are written using the following write sequence (from a bus idle condition) when the system has three slaves daisy-chained together: 1. All the slave devices in chain will be involved in a write or read operation. Every slave device in the chain is a portion of one big shift register. 2. Drive CS LOW. This enables the internal 16-bit shift register. 3. Shift 16 × n bits of data (where ‘n’ is the number of slaves) into the first slave device in a MSB-first fashion. Data is shifted on the rising edge of SCLK and must be stable during the rising edge of SCLK. 4. The 8th bit of the data for every 16 bits (each device) must be a ‘0’, indicating it is a write transfer. 5. After the last bit of data is transferred, drive SCLK LOW and deassert CS (drive it HIGH). 6. When CS goes from LOW to HIGH, the data in the shift register is latched into the device registers. If fewer than 16 bits of data are transferred before deasserting CS, then the data is ignored and the register will not be updated. The write transfer format is shown in Figure 14. CS SCLK SDI 16 clocks 16 clocks 16 clocks WR (slave 3) WR (slave 2) WR (slave 1) WR (slave 3) WR (slave 2) SDO (slave 1) SDO (slave 2) WR (slave 3) SDO (slave 3) aaa-011891 Figure 14. Write access 8.4 Read access sequence The registers are read using the following read sequence (from a bus idle condition) when the system has three slaves daisy-chained as shown in Figure 15. 1. The master sends the first three 2-byte read instructions with 48 clocks, where the first byte is a 7-bit register address, an eighth bit set to one, followed by dummy data byte (all ones). 2. The Read instruction is decoded when CS is deasserted (from LOW to HIGH). 3. The read data is shifted out on SDO when CS is asserted again (from HIGH to LOW). 4. The master sends the second three 2-byte ‘No Operation’ (NOP) operations (all ones) with 48 clocks and reads the requested data on MISO in sequence where the first byte is dummy data (don’t care), followed by the read data byte. 5. A read cycle consists of asserting and deasserting of CS twice. PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 34 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver MOSI 11111111 (NOP) MISO XXXXXXXX 11111111 (NOP) 11111111 (NOP) 11111111 (NOP) 11111111 (NOP) 11111111 (NOP) Data 3 XXXXXXXX Data 2 XXXXXXXX Data 1 CS SCLK MOSI 16 clocks 16 clocks 16 clocks RD slave 3 RD slave 2 RD slave 1 MISO 16 clocks 16 clocks 16 clocks NOP NOP NOP Slave 3 OUT Slave 2 OUT Slave 1 OUT aaa-011892 Figure 15. Read access 8.5 Overlapped read and write access sequence The registers are read and write overlapped using the following sequence (from a bus idle condition) when the system has three slaves daisy-chained as shown in Figure 16. 1. The second phase of the read cycle can be used to send in write data or the next read instruction. This increases the bus utility and hence efficiency. 2. The master sends the first three 2-byte read instructions with 48 clocks, where the first byte is a 7-bit register address, the eighth bit is set to one, followed by dummy data byte (all ones). 3. The read instruction is decoded when CS is deasserted (from LOW to HIGH). 4. Start to shift read data out on SDO when CS is asserted again (from HIGH to LOW) and start to send in the next read or write instruction on the SDI line. MOSI Write 3 MISO XXXXXXXX WR Data 3 Write 2 WR Data 2 Write 1 WR Data 1 RD Data 3 XXXXXXXX RD Data 2 XXXXXXXX RD Data 1 CS SCLK MOSI 16 clocks 16 clocks 16 clocks 16 clocks 16 clocks 16 clocks RD slave 3 RD slave 2 RD slave 1 WR slave 3 WR slave 2 WR slave 1 Slave 3 OUT Slave 2 OUT Slave 1 OUT MISO aaa-011893 Figure 16. Overlapped read and write access PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 35 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 9 Application design-in information VDDIO = 1.65 V ~ 5.5 V VDD = 2.7 V ~ 5.5 V 10 k (1) SPI SERIAL BUS MASTER 10 k (2) up to 5.5 V VDDIO VDD CS LED0 LED1 CS MISO SDO MOSI SDI SCLK SCLK OE LED2 LED3 OE RESET LED4 RESET LED5 PCA9957 LED6 LED7 REXT LED8 ISET LED9 LED10 LED11 LED12 LED13 LED n VSS VSS LED23 C 10 µF aaa-034489 1. OE requires pull-up resistor if control signal from the master is open-drain 2. RESET requires a pull-up resistor of = 20h Rext = 2 kΩ; refer to ideal value; guaranteed by design ±6.5 % VO = 0.4 V; all channels on; IREFx < 20h; Rext = 2 kΩ; refer to ideal value; guaranteed by design ±8 % ±6 % all channels on; IREFx = FFh. Rext = 2 kΩ; VO = 0.4 V; average value of 24 output current of each device, comparing to ideal value All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 [4] - - © NXP B.V. 2021. All rights reserved. 39 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Table 28. Static characteristics...continued VDD = 2.7 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions [5] Min Typ - - [1] Max Unit ±4 % 5.5 V ΔIO_mis_c2c channel to channel output current mismatch all channels on; IREFx = FFh. Rext = 2 kΩ; VO = 0.4 V; each channel current comparing to average current of 24 channels Vreg(drv) driver regulation voltage minimum regulation voltage; IREFx = FFh; Rext = 2 kΩ 0.4 IL(off) off-state leakage current VO = 5 V - - 1 µA Vtrip trip voltage short LED protection; Error flag trips during verification test if VO ≥ Vtrip; Rext = 2 kΩ 1.85 1.96 - V - +0.3VDDIO V OE input, RESET input VIL LOW-level input voltage -0.5 VIH HIGH-level input voltage 0.7VDDIO - 5.5 V ILI input leakage current Ci -1 - +1 µA [3] - 3.7 5 pF rising [3] 130 - 150 °C hysteresis [3] 15 - 30 °C input capacitance Overtemperature protection Tth(otp) overtemperature protection threshold temperature [1] [2] [3] [4] Typical limits at VDD = 3.3 V, Tamb = 25 °C. VDD must be lowered to 1 V in order to reset part. Value not tested in production, but guaranteed by design and characterization. Part-to-part mismatch is calculated: [5] where ‘ideal output current’ = 31.875 mA (Rext = 2 kΩ, IREFx = FFh). Channel-to-channel mismatch is calculated: 13 Dynamic characteristics Table 29. Dynamic characteristics Symbol Parameter fSCLK [1] Min Typ Max Unit SCLK clock frequency 0 - 10 MHz tLOW LOW period of the SCLK clock 50 - - ns tHIGH HIGH period of the SCLK clock 50 - - ns tDS data set-up time 10 - - ns tDH data hold time 20 - - ns tCSS chip select asserted to SCLK rise set-up time 10 - - ns tCSH SCLK fall to chip select deasserted hold time 0 - - ns tCS_HI minimum chip select deasserted HIGH time 40 - - ns PCA9957 Product data sheet Conditions All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 40 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Table 29. Dynamic characteristics [1] ...continued Symbol Parameter Conditions Min Typ Max Unit td(SDO) SDO delay time CL = 50 pF - - 40 ns td(LED0) The latency time between OE pin assertion to LED channel 0 output on - - 1 tOE(disable) tOE(enable) OE pin disable (HIGH) period time OE pin enable (LOW) period time 250 250 - - [1] [2] [2] µs ns ns All parameters tested at VDD = 3 V to 5.5 V; VSS = 0 V; Tamb = +25 °C. Specifications over temperature are guaranteed by design. Guaranteed by design. CS 50% 50% tLOW tHIGH tCSS 50% SCLK tDS tDH SDI tCSH D15 50% 50% 50% tCS_HI 50% 1 / fSCLK D14 D13 D2 D1 D0 D15 td(SDO) SDO D4 D3 D2 D1 D0 50% aaa-011895 Figure 18. Definition of timing LED0- 23 OE tOE(enable) tOE(disable) aaa-040787 Figure 19. OE pin timing PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 41 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 14 Test information VDD PULSE GENERATOR VI DUT VO RT RL 100 VDD or VLED open VSS CL 50 pF 002aag359 RL = Load resistor for LEDn. CL = Load capacitance includes jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generators. Figure 20. Test circuitry for switching times PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 42 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 15 Package outline Figure 21. Package outline SOT1369-5 (HVQFN40) (1 of 3) PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 43 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Figure 22. Package outline SOT1369-5 (HVQFN40) (2 of 3) PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 44 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Figure 23. Package outline SOT1369-5 (HVQFN40) (3 of 3) PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 45 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 16 Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17 Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 17.3 Wave soldering Key characteristics in wave soldering are: PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 46 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 24) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 30 and Table 31 Table 30. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 31. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 24. PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 47 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Figure 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 48 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 18 Soldering: PCB footprints Figure 25. PCB footprint for SOT1369-5 (HVQFN40); solder mask opening pattern PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 49 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Figure 26. PCB footprint for SOT1369-5 (HVQFN40); I/O pads and solderable area PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 50 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Figure 27. PCB footprint for SOT1369-5 (HVQFN40); solder paste stencil PCA9957 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 51 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 19 Abbreviations Table 32. Abbreviations Acronym Description CDM Charged-Device Model DAC Digital-to-Analog Converter DUT Device Under Test ESD ElectroStatic Discharge FET Field-Effect Transistor HBM Human Body Model LED Light Emitting Diode LSB Least Significant Bit MCU MicroController Unit MISO Master In, Slave Out MOSI Master Out, Slave In MSB Most Significant Bit NMOS Negative-channel Metal-Oxide Semiconductor PCB Printed-Circuit Board PMOS Positive-channel Metal-Oxide Semiconductor PWM Pulse Width Modulation RGB Red/Green/Blue RGBA Red/Green/Blue/Amber SMBus System Management Bus SPI Serial Peripheral Interface 20 Revision history Table 33. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9957 v.2.1 20211022 Product data sheet 202110025I PCA9957 v.2.0 Modifications: • Table 3: Updated description for CS • Section 8.1: Updated SDO information in sections CS and SDO PCA9957 v.2.0 20210225 Modifications: • Added Vtrip minimum of 1.85 V • Section 7.2.13 "LED error detection": Corrected "if there is a fault condition in any of the 16 channels" to "if there is a fault condition in any of the 24 channels" • Section 7.2.9 "OFFSET — LEDn output delay offset register": Updated register description information for bits 3:0 • Section 13 "Dynamic characteristics": Added OE pin enable/disable min time and chart PCA9957 v.1.0 20191024 PCA9957 Product data sheet Product data sheet Product data sheet - - All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 PCA9957 v.1.0 - © NXP B.V. 2021. All rights reserved. 52 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver 21 Legal information 21.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 21.2 Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 21.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PCA9957 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 53 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. PCA9957 Product data sheet Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. 21.4 Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 54 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Tab. 6. Tab. 7. Tab. 8. Tab. 9. Tab. 10. Tab. 11. Tab. 12. Tab. 13. Tab. 14. Tab. 15. Ordering information ..........................................3 Ordering options ................................................3 Pin description ...................................................5 Register summary - default values ....................7 MODE1 - Mode register 1 (address 00h) bit description ....................................................... 11 MODE2 - Mode register 2 (address 01h) bit description ....................................................... 11 LEDOUT0 to LEDOUT5 - LED driver output state registers (address 08h to 0Dh) bit description ....................................................... 12 GRPPWM - Group brightness control register (address 0Eh) bit description ..............14 GRPFREQ - Group frequency register (address 0Fh) bit description ...........................14 PWM0 to PWM23 - PWM registers 0 to 23 (address 10h to 27h) bit description ................ 14 IREF0 to IREF23 - LED output gain control registers (address 28h to 3Fh) bit description ....................................................... 16 RAMP_RATE_GRP[0:3] - Ramp enable and rate control registers (address 40h, 44h, 48h, 4Ch, 50h, 54h) for each group bit description ....................................................... 18 STEP_TIME_GRP[0:3] - Step time control registers (address 41h, 45h, 49h, 4Dh, 51h, 55h) for each group bit description ..................18 HOLD_CNTL_GRP[0:3] - Hold ON and OFF enable and time control registers (address 42h, 46h, 4Ah, 4Eh, 52h, 56h) for each group bit description ...............................19 IREF_GRP[0:3] - Final and hold ON output gain setting registers (address 43h, 47h, Tab. 16. Tab. 17. Tab. 18. Tab. 19. Tab. 20. Tab. 21. Tab. 22. Tab. 23. Tab. 24. Tab. 25. Tab. 26. Tab. 27. Tab. 28. Tab. 29. Tab. 30. Tab. 31. Tab. 32. Tab. 33. 4Bh, 4Fh, 53h, 57h) for each group bit description ....................................................... 19 GRAD_MODE_SEL[0:1] - Gradation mode select register for channel 23 to channel 0 (address 58h, 59h, 5Ah) bit description ...........20 GRAD_GRP_SEL[0:3] - Gradation group select register for channel 23 to channel 0 (address 5Bh, 5Ch, 5Dh, 5Eh, 5Fh, 60h, 61h, 62h, 63h, 64h, 65h, 66h) bit description ....................................................... 20 GRAD_CNTL[0:1] - Gradation control register for group 5 to group 0 (address 67h, 68h) bit description ..................................22 OFFSET - LEDn output delay offset register (address 69h) bit description .............. 25 PWMALL - brightness control for all LEDn outputs register (address 6Ah) bit description ....................................................... 26 IREFALL - Output gain control for all LED outputs (address 6Bh) bit description ..............27 EFLAG0 to EFLAG5 - Error flag registers (address 02h to 07h) bit description ................ 29 ERRx bit description ....................................... 30 Open-circuit detection ..................................... 30 Short-circuit detection ......................................30 Limiting values ................................................ 38 Thermal characteristics ................................... 38 Static characteristics ....................................... 38 Dynamic characteristics .................................. 40 SnPb eutectic process (from J-STD-020D) ..... 47 Lead-free process (from J-STD-020D) ............ 47 Abbreviations ...................................................52 Revision history ...............................................52 Figures Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. Fig. 6. Fig. 7. Fig. 8. Fig. 9. Fig. 10. Fig. 11. Fig. 12. Fig. 13. Fig. 14. Fig. 15. Fig. 16. Block diagram of PCA9957 ...............................4 Pin configuration for HVQFN40 .........................5 Register address and data format for each slave .................................................................. 7 Linear and exponential adjustment curves ...... 12 Gradation timing .............................................. 17 Ramp calculation example 1 ........................... 23 Ramp calculation example 2 ........................... 24 Gradation output waveform in single shot or continuous mode ........................................ 25 Maximum ILED versus Rext ............................28 IO(target) versus IREFx value with Rext = 2 kΩ .................................................................... 28 Brightness + Group Dimming signals .............. 32 System level connection ................................. 33 Data format ..................................................... 33 Write access ....................................................34 Read access ................................................... 35 Overlapped read and write access ..................35 PCA9957 Product data sheet Fig. 17. Fig. 18. Fig. 19. Fig. 20. Fig. 21. Fig. 22. Fig. 23. Fig. 24. Fig. 25. Fig. 26. Fig. 27. Typical application ........................................... 36 Definition of timing .......................................... 41 OE pin timing .................................................. 41 Test circuitry for switching times ......................42 Package outline SOT1369-5 (HVQFN40) (1 of 3) .................................................................43 Package outline SOT1369-5 (HVQFN40) (2 of 3) .................................................................44 Package outline SOT1369-5 (HVQFN40) (3 of 3) .................................................................45 Temperature profiles for large and small components ..................................................... 48 PCB footprint for SOT1369-5 (HVQFN40); solder mask opening pattern ...........................49 PCB footprint for SOT1369-5 (HVQFN40); I/O pads and solderable area ..........................50 PCB footprint for SOT1369-5 (HVQFN40); solder paste stencil ......................................... 51 All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 22 October 2021 © NXP B.V. 2021. All rights reserved. 55 / 56 PCA9957 NXP Semiconductors 24-channel SPI serial bus 32 mA/5.5 V constant current LED driver Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.2.1 7.2.2 7.2.3 General description ............................................ 1 Features and benefits .........................................2 Applications .........................................................3 Ordering information .......................................... 3 Ordering options ................................................ 3 Block diagram ..................................................... 4 Pinning information ............................................ 5 Pinning ............................................................... 5 Pin description ................................................... 5 Functional description ........................................6 Register address and data ................................ 6 Register definitions ............................................ 7 MODE1 — Mode register 1 ............................. 11 MODE2 — Mode register 2 ............................. 11 LEDOUT0 to LEDOUT5, LED driver output state ................................................................. 12 7.2.4 GRPPWM, group duty cycle control ................ 14 7.2.5 GRPFREQ, group frequency ........................... 14 7.2.6 PWM0 to PWM23, individual brightness control .............................................................. 14 7.2.7 IREF0 to IREF23, LED output current value registers ........................................................... 15 7.2.8 Gradation control ............................................. 16 7.2.8.1 RAMP_RATE_GRP0 to RAMP_RATE_ GRP5, ramp rate control registers ................... 18 7.2.8.2 STEP_TIME_GRP0 to STEP_TIME_GRP5, step time control registers ............................... 18 7.2.8.3 HOLD_CNTL_GRP0 to HOLD_CNTL_ GRP5, hold ON and OFF control registers ...... 19 7.2.8.4 IREF_GRP0 to IREF_GRP5, output gain control .............................................................. 19 7.2.8.5 GRAD_MODE_SEL0 to GRAD_MODE_ SEL2, Gradation mode select registers ........... 20 7.2.8.6 GRAD_GRP_SEL0 to GRAD_GRP_SEL11, Gradation group select registers ......................20 7.2.8.7 GRAD_CNTL, Gradation control register .........22 7.2.8.8 Ramp control — equation and calculation example ........................................................... 23 7.2.9 OFFSET — LEDn output delay offset register ............................................................. 25 7.2.10 PWMALL — brightness control for all LEDn outputs ............................................................. 26 7.2.11 IREFALL register: output current value for all LED outputs ................................................ 27 7.2.12 LED driver constant current outputs ................ 27 7.2.12.1 Adjusting output current ...................................27 7.2.13 LED error detection ......................................... 28 7.2.13.1 Open-circuit detection principle ....................... 30 7.2.13.2 Short-circuit detection principle ........................30 7.2.14 Overtemperature protection ............................. 31 7.3 Active LOW output enable input ...................... 31 7.4 Power-on reset ................................................ 31 7.5 Hardware reset recovery ................................. 31 7.6 8 8.1 8.2 8.3 8.4 8.5 9 9.1 10 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 20 21 Individual brightness control with group dimming/blinking .............................................. 31 Characteristics of the 4-wire SPI serial-bus interface ............................................................. 32 SPI-compatible 4-wire serial interface signals ..............................................................32 Data format ......................................................33 Write access sequence ................................... 34 Read access sequence ................................... 34 Overlapped read and write access sequence ......................................................... 35 Application design-in information ................... 36 Thermal considerations ................................... 36 Limiting values .................................................. 38 Thermal characteristics ....................................38 Static characteristics ........................................ 38 Dynamic characteristics ...................................40 Test information ................................................ 42 Package outline .................................................43 Handling information ........................................ 46 Soldering of SMD packages .............................46 Introduction to soldering ............................. Wave and reflow soldering ......................... Wave soldering ........................................... Reflow soldering ......................................... Soldering: PCB footprints ................................ 49 Abbreviations .................................................... 52 Revision history ................................................ 52 Legal information .............................................. 53 © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 October 2021 Document identifier: PCA9957