PCAL6408A
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt
output, reset, and configuration registers
Rev. 3.3 — 14 October 2024
Product data sheet
1 General description
The PCAL6408A is an 8-bit general-purpose I/O expander that provides remote I/O expansion for most
2
microcontroller families via the I C-bus interface.
NXP I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections
to a minimum, for example, in battery-powered mobile applications for interfacing to sensors, push buttons,
keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running
at one voltage level to I/O devices operating at a different (usually higher) voltage level. The PCAL6408A has
built-in level shifting feature that makes these devices extremely flexible in mixed signal environments where
communication between incompatible I/O voltages is required.
Its wide VDD range of 1.65 V to 5.5 V on the dual power rail allows seamless communications with nextgeneration low voltage microprocessors and microcontrollers on the interface side (SDA/SCL) and peripherals
at a higher voltage on the port side.
There are two supply voltages for PCAL6408A: VDD(I2C-bus) and VDD(P). VDD(I2C-bus) provides the supply voltage
for the interface at the controller side (for example, a microcontroller) and the VDD(P) provides the supply for core
circuits and Port P. The bidirectional voltage level translation in the PCAL6408A is provided through VDD(I2C-bus).
VDD(I2C-bus) should be connected to the VDD of the external SCL/SDA lines. This indicates the VDD level of the
2
I C-bus to the PCAL6408A, while the voltage level on Port P of the PCAL6408A is determined by the VDD(P).
The PCAL6408A contains the PCA6408A register set of 8-bit Configuration, Input, Output, and Polarity
Inversion registers and additionally, the PCAL6408A has Agile I/O, which are additional features specifically
designed to enhance the I/O. These additional features are: programmable output drive strength, latchable
inputs, programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register, programmable
open-drain or push-pull outputs. The PCAL6408A is a pin-to-pin replacement to the PCA6408A, however, the
PCAL6408A powers up with all I/O interrupts masked. This mask default allows for a board bring-up free of
spurious interrupts at power-up.
At power-on, the I/Os are configured as inputs. However, the system controller can enable the I/Os as either
inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the
corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity
Inversion register, saving external logic gates. Programmable pull-up and pull-down resistors eliminate the need
for discrete components.
The system controller can reset the PCAL6408A in the event of a time-out or other improper operation by
asserting a LOW in the RESET input. The power-on reset puts the registers in their default state and initializes
2
the I C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.
PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
The PCAL6408A open-drain interrupt (INT) output is activated when any input state differs from its
corresponding Input Port register state and is used to indicate to the system controller that an input state has
changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate
2
via the I C-bus. Thus, the PCAL6408A can remain a simple target device. The input latch feature holds or
latches the input pin state and keeps the logic values that created the interrupt until the controller can service
the interrupt. This minimizes the host’s interrupt service response for fast moving inputs.
The device Port P outputs have 25 mA sink capabilities for directly driving LEDs while consuming low device
current.
2
One hardware pin (ADDR) can be used to program and vary the fixed I C-bus address and allow up to two
2
devices to share the same I C-bus or SMBus.
PCAL6408A
Product data sheet
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NXP Semiconductors
2
PCAL6408A
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
2 Features and benefits
2
• I C-bus to parallel port expander
• Operating power supply voltage range of 1.65 V to 5.5 V
• Allows bidirectional voltage-level translation and GPIO expansion between:
– 1.8 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
– 2.5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
– 3.3 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
– 5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
• Low standby current consumption of 1 μA
• Schmitt-trigger action allows slow input transition and better switching noise immunity at the SCL and SDA
inputs
– Vhys = 0.18 V (typical) at 1.8 V
– Vhys = 0.25 V (typical) at 2.5 V
– Vhys = 0.33 V (typical) at 3.3 V
– Vhys = 0.5 V (typical) at 5 V
• 5 V tolerant I/O ports
• Active LOW reset input (RESET)
• Open-drain active LOW interrupt output (INT)
2
• 400 kHz Fast-mode I C-bus
• Internal power-on reset
• Power-up with all channels configured as inputs
• No glitch on power-up
• Noise filter on SCL/SDA inputs
• Latched outputs with 25 mA drive maximum capability for directly driving LEDs
• Latch-up performance exceeds 100 mA per JESD 78, Class II
• ESD protection exceeds JESD 22
– 2000 V Human-Body Model (A114-A)
– 1000 V Charged-Device Model (C101)
• Packages offered: HVQFN16, TSSOP16, XQFN16, XFBGA16 (1.6 mm × 1.6 mm × 0.5 mm), X2QFN16 (LGA,
Land Grid Array) 1.6 mm x 1.6 mm x 0.35 mm
2.1 Agile I/O features
•
•
•
•
•
Software backward compatible with PCA6408A with interrupts disabled at power-up
Pin-to-pin drop-in replacement for PCA6408A
Output port configuration: bank selectable push-pull or open-drain output stages
Interrupt status: read-only register identifies the source of an interrupt
Bit-wise I/O programming features:
– Output drive strength: four programmable drive strengths to reduce rise and fall times in low-capacitance
applications
– Input latch: Input Port register values changes are kept until the Input Port register is read
– Pull-up/pull-down enable: floating input or pull-up/pull-down resistor enable
– Pull-up/pull-down selection: 100 kΩ pull-up/pull-down resistor selection
– Interrupt mask: mask prevents the generation of the interrupt when input changes state to prevent spurious
interrupts
PCAL6408A
Product data sheet
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
3 Ordering information
Table 1. Ordering information
Type number
Topside
marking
Package
Name
Description
Version
L8A
HVQFN16
plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3 × 3 × 0.85 mm
SOT758-1
PCAL6408APW PL6408A
TSSOP16
plastic thin shrink small outline package; 16 leads; body width
4.4 mm
SOT403-1
PCAL6408AHK
L8
XQFN16
plastic, extremely thin quad flat package; no leads; 16 terminals;
body 1.80 × 2.60 × 0.50 mm
SOT1161-1
PCAL6408AEX
L8
XFBGA16
plastic, extremely thin fine-pitch ball grid array package; 16 balls; SOT1354-1
body 1.6 × 1.6 × 0.5 mm
X2QFN16
plastic, thermal enhanced super thin quad flat package; no leads; SOT1896-1
16 terminals; 1.6 mm x 1.6 mm x 0.35 mm body
PCAL6408ABS
PCAL6408AEX1 18X
[1]
[2]
[1]
[2]
XFBGA16 package is discontinued with lifetime buy November 2016; new designs must use X2QFN16 package.
"X" rotates from 1 to 5 and indicates the work week of the indicated month
3.1 Ordering options
Table 2. Ordering options
Type number
Orderable part
number
Package
Packing method
Minimum
order quantity
Temperature
PCAL6408ABS
PCAL6408ABSHP
HVQFN16
Reel 13" Q2/T3
*standard mark SMD
6000
Tamb = -40 °C to +85 °C
PCAL6408APW
PCAL6408APWJ
TSSOP16
Reel 13" Q1/T1
*standard mark SMD
2500
Tamb = -40 °C to +85 °C
PCAL6408AHK
PCAL6408AHKX
XQFN16
Reel 7" Q1/T1
*standard mark SMD
4000
Tamb = -40 °C to +85 °C
PCAL6408AEX
PCAL6408AEXX
XFBGA16
Reel 7" Q1/T1
*standard mark SMD
5000
Tamb = -40 °C to +85 °C
PCAL6408AEX1
PCAL6408AEX1Z
X2QFN16
Reel 7" Q2/T1
*standard mark SMD
5000
Tamb = -40 °C to +85 °C
[1]
[1]
XFBGA16 package is discontinued with lifetime buy November 2016; new designs must use X2QFN16 package.
PCAL6408A
Product data sheet
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Rev. 3.3 — 14 October 2024
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
4 Block diagram
INT
PCAL6408A
INTERRUPT
LOGIC
LP FILTER
ADDR
SCL
SDA
I2C-BUS
CONTROL
INPUT
FILTER
VDD(I2C-bus)
VDD(P)
RESET
POWER-ON
RESET
SHIFT
REGISTER
8 BITS
I/O
PORT
P0 to P7
write pulse
read pulse
I/O control
VSS
002aah085
All I/Os are set to inputs at reset.
Figure 1. Block diagram (positive logic)
PCAL6408A
Product data sheet
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
5 Pinning information
5.1 Pinning
VDD(I2C-bus)
1
ADDR
2
16 VDD(P)
15 SDA
RESET
3
14 SCL
P0
4
P1
5
P2
6
11 P6
P3
7
10 P5
VSS
8
13 INT
PCAL6408APW
12 P7
9
P4
002aah086
The exposed center pad, if used, must be connected only as a secondary VSS or must be left electrically open.
4
14 VDD(P)
13 SDA
10 P7
9
8
P2
P5
3
7
P1
11 INT
PCAL6408ABS
P4
2
6
P0
12 SCL
VSS
1
5
RESET
P3
terminal 1
index area
15 VDD(I2C-bus)
16 ADDR
Figure 2. Pin configuration for TSSOP16
P6
002aah087
Transparent top view
Figure 3. Pin configuration for HVQFN16
13 SDA
14 VDD(P)
15 VDD(I2C-bus)
terminal 1
index area
16 ADDR
PCAL6408AHK
RESET 1
12 SCL
P2 4
9 P6
P5 8
10 P7
P4 7
P1 3
VSS 6
11 INT
P3 5
P0 2
002aah088
Transparent top view
Figure 4. Pin configuration for XQFN16
PCAL6408A
Product data sheet
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
ball A1
index area
1
PCAL6408AEX
2
3
4
A
B
C
D
002aah675
Transparent top view
Figure 5. Pin configuration for 1.6 mm × 1.6 mm XFBGA16
PCAL6408AEX1
terminal 1
index area
1
2
3
4
A
B
C
D
aaa-026716
Transparent top view
Figure 6. Pin configuration for 1.6 mm × 1.6 mm X2QFN16 EX1 land grid array
1
2
3
4
A
RESET
VDD(I2C-bus)
VDD(P)
SCL
B
P0
ADDR
SDA
INT
C
P2
P1
P7
P6
D
P3
VSS
P4
P5
Transparent top view
002aah676
Figure 7. Ball mapping for 1.6 mm × 1.6 mm XFBGA16/X2QFN16
5.2 Pin description
Table 3. Pin description
Symbol
Pin
Description
TSSOP16
HVQFN16
XQFN16
XFBGA16,
X2QFN16
VDD(I2C-bus)
1
15
15
A2
Supply voltage of I C-bus. Connect directly to the VDD of the
2
external I C controller. Provides voltage-level translation.
ADDR
2
16
16
B2
Address input. Connect directly to VDD(P) or ground.
RESET
3
1
1
A1
Active LOW reset input. Connect to VDD(I2C-bus) through a pull-up
resistor if no active connection is used.
P0
[1]
4
2
2
B1
Port P input/output 0.
P1
[1]
5
3
3
C2
Port P input/output 1.
PCAL6408A
Product data sheet
2
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Table 3. Pin description...continued
Symbol
Pin
Description
TSSOP16
HVQFN16
XQFN16
XFBGA16,
X2QFN16
P2
[1]
6
4
4
C1
Port P input/output 2.
P3
[1]
7
5
5
D1
Port P input/output 3.
VSS
8
6
6
D2
Ground.
P4
[1]
9
7
7
D3
Port P input/output 4.
P5
[1]
10
8
8
D4
Port P input/output 5.
P6
[1]
11
9
9
C4
Port P input/output 6.
P7
[1]
12
10
10
C3
Port P input/output 7.
INT
13
11
11
B4
Interrupt output. Connect to VDD(I2C-bus) through a pull-up
resistor.
SCL
14
12
12
A4
Serial clock bus. Connect to VDD(I2C-bus) through a pull-up
resistor.
SDA
15
13
13
B3
Serial data bus. Connect to VDD(I2C-bus) through a pull-up
resistor.
VDD(P)
16
14
14
A3
Supply voltage of PCAL6408A for Port P.
[1]
All I/O are configured as input at power-on.
PCAL6408A
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
6 Voltage translation
2
Table 4 shows how to set up VDD levels for the necessary voltage translation between the I C-bus and the
PCAL6408A.
Table 4. Voltage translation
2
VDD(I2C-bus) (SDA and SCL of I C controller)
VDD(P) (Port P)
1.8 V
1.8 V
1.8 V
2.5 V
1.8 V
3.3 V
1.8 V
5V
2.5 V
1.8 V
2.5 V
2.5 V
2.5 V
3.3 V
2.5 V
5V
3.3 V
1.8 V
3.3 V
2.5 V
3.3 V
3.3 V
3.3 V
5V
5V
1.8 V
5V
2.5 V
5V
3.3 V
5V
5V
PCAL6408A
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
7 Functional description
Refer to Figure 1.
7.1 Device address
The address of the PCAL6408A is shown in Figure 8.
target address
0
1
0
0
0
0
AD R/W
DR
fixed
programmable
002aaf539
Figure 8. Device address
ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW (logic 0) to assign one
of the two possible target addresses. The last bit of the target address defines the operation (read or write) to be
performed. A HIGH (logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
7.2 Interface definition
Table 5. Interface definition
Byte
Bit
7 (MSB)
6
5
4
3
2
1
0 (LSB)
L
H
L
L
L
L
ADDR
R/W
P7
P6
P5
P4
P3
P2
P1
P0
2
I C-bus target address
I/O data bus
7.3 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus controller sends a command byte,
which is stored in the Pointer register in the PCAL6408A. 2 bits of this data byte state the operation (read or
write) and the internal registers (Input, Output, Polarity Inversion, or Configuration) that are affected. Bit 6 in
conjunction with the lower 3 bits of the Command byte are used to point to the extended features of the device
(Agile I/O). This register is ‘write only’.
B7
B6
B5
B4
B3
B2
B1
B0
002aaf540
Figure 9. Pointer register bits
Table 6. Command byte
Pointer register bits
Command byte Register
Protocol
Power-up
default
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
0
00h
Input port
read byte
xxxx xxxx
0
0
0
0
0
0
0
1
01h
Output port
read/write byte
1111 1111
0
0
0
0
0
0
1
0
02h
Polarity Inversion
read/write byte
0000 0000
0
0
0
0
0
0
1
1
03h
Configuration
read/write byte
1111 1111
0
1
0
0
0
0
0
0
40h
Output drive strength 0
read/write byte
1111 1111
PCAL6408A
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Table 6. Command byte...continued
Pointer register bits
Command byte Register
Protocol
Power-up
default
B7
B6
B5
B4
B3
B2
B1
B0
0
1
0
0
0
0
0
1
41h
Output drive strength 1
read/write byte
1111 1111
0
1
0
0
0
0
1
0
42h
Input latch
read/write byte
0000 0000
0
1
0
0
0
0
1
1
43h
Pull-up/pull-down enable
read/write byte
0000 0000
0
1
0
0
0
1
0
0
44h
Pull-up/pull-down selection read/write byte
1111 1111
0
1
0
0
0
1
0
1
45h
Interrupt mask
read/write byte
1111 1111
0
1
0
0
0
1
1
0
46h
Interrupt status
read byte
0000 0000
0
1
0
0
1
1
1
1
4Fh
Output port configuration
read/write byte
0000 0000
[1]
Undefined.
7.4 Register descriptions
7.4.1 Input port register (00h)
The Input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration register. The Input port register is read only; writes to this
register have no effect. The default value ‘X’ is determined by the externally applied logic level. An Input port
register read operation is performed as described in Section 8.2.
Table 7. Input port register (address 00h)
Bit
7
6
5
4
3
2
1
0
Symbol
I7
I6
I5
I4
I3
I2
I1
I0
Default
X
X
X
X
X
X
X
X
7.4.2 Output port register (01h)
The Output port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from
this register reflect the value that was written to this register, not the actual pin value.
Table 8. Output port register (address 01h)
Bit
7
6
5
4
3
2
1
0
Symbol
O7
O6
O5
O4
O3
O2
O1
O0
Default
1
1
1
1
1
1
1
1
7.4.3 Polarity inversion register (02h)
The Polarity inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with ‘1’), the corresponding port pin’s polarity is inverted. If a bit in
this register is cleared (written with a ‘0’), the corresponding port pin’s original polarity is retained.
Table 9. Polarity inversion register (address 02h)
Bit
Symbol
PCAL6408A
Product data sheet
7
6
5
4
3
2
1
0
N7
N6
N5
N4
N3
N2
N1
N0
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Table 9. Polarity inversion register (address 02h)...continued
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
7.4.4 Configuration register (03h)
The Configuration register (register 3) configures the direction of the I/O pins. If a bit in this register is set to
1, the corresponding port pin is enabled as a high-impedance input. If a bit in this register is cleared to 0, the
corresponding port pin is enabled as an output.
Table 10. Configuration register (address 03h)
Bit
7
6
5
4
3
2
1
0
Symbol
C7
C6
C5
C4
C3
C2
C1
C0
Default
1
1
1
1
1
1
1
1
7.4.5 Output drive strength registers (40h, 41h)
The Output drive strength registers control the output drive level of the GPIO. Each GPIO can be configured
independently to a certain output current level by two register control bits. For example, Port 7 is controlled
by register 41 CC7 (bits [7:6]), Port 6 is controlled by register 41 CC6 (bits [5:4]). The output drive level of the
GPIO is programmed 00b = 0.25×, 01b = 0.5×, 10b = 0.75× or 11b = 1× of the drive capability of the I/O. See
Section 9.2 for more details.
Table 11. Current control register (address 40h)
Bit
7
Symbol
Default
6
5
4
CC3
1
3
CC2
1
1
2
1
CC1
0
CC0
1
1
1
1
1
4
3
2
1
0
Table 12. Current control register (address 41h)
Bit
7
Symbol
Default
6
5
CC7
1
CC6
1
1
CC5
1
1
CC4
1
1
1
7.4.6 Input latch register (42h)
The Input latch register enables and disables the input latch of the I/O pins. These registers are effective only
when the pin is configured as an input port. When an input latch register bit is 0, the corresponding input pin
state is not latched. A state change in the corresponding input pin generates an interrupt. A read of the input
port register clears the interrupt. If the input goes back to its initial logic state before the input port register is
read, then the interrupt is cleared. See Figure 14.
When an input latch register bit is 1, the corresponding input pin state is latched. A change of state of the input
generates an interrupt and the input logic value is loaded into the corresponding bit of the input port register
(registers 0). A read of the input port register clears the interrupt. If the input pin returns to its initial logic state
before the input port register is read, then the interrupt is not cleared and the corresponding bit of the input
port register keeps the logic value that initiated the interrupt. See Figure 15. For example, if the P4 input was
as logic 0 and the input goes to logic 1 then back to logic 0, the input port register captures this change and
an interrupt is generated (if unmasked). When the read is performed on the input port register, the interrupt is
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Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
cleared, assuming there were no additional input(s) that have changed, and bit 4 of the input port register reads
‘1’. The next read of the input port register bit 4 should now read ‘0’.
An interrupt remains active when a non-latched input simultaneously switches state with a latched input and
then returns to its original state. A read of the input port register reflects only the change of state of the latched
input and also clears the interrupt. The interrupt is not cleared if the input latch register changes from latched to
non-latched configuration.
If the input pin is changed from latched to non-latched input, a read from the input port register reflects the
current port logic level. If the input pin is changed from non-latched to latched input, the read from the input port
register reflects the latched logic level.
Table 13. Input latch register (address 42h)
Bit
7
6
5
4
3
2
1
0
Symbol
L7
L6
L5
L4
L3
L2
L1
L0
Default
0
0
0
0
0
0
0
0
7.4.7 Pull-up/pull-down enable register (43h)
This register allows the user to enable or disable pull-up/pull-down resistors on the I/O pins. Setting the bit to
logic 1 enables the selection of pull-up/pull-down resistors. Setting the bit to logic 0 disconnects the pull-up/pulldown resistors from the I/O pins. Also, the resistors are disconnected when the outputs are configured as opendrain outputs (see Section 7.4.11). Use the pull-up/pull-down selection registers to select either a pull-up or pulldown resistor.
Table 14. Pull-up/pull-down enable register (address 43h)
Bit
7
6
5
4
3
2
1
0
Symbol
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Default
0
0
0
0
0
0
0
0
7.4.8 Pull-up/pull-down selection register (44h)
The I/O port can be configured to have pull-up or pull-down resistor by programming the pull-up/pull-down
selection register. Setting a bit to logic 1 selects a 100 kΩ pull-up resistor for that I/O pin. Setting a bit to logic
0 selects a 100 kΩ pull-down resistor for that I/O pin. If the pull-up/down feature is disconnected, writing to this
register has no effect on I/O pin. Typical value is 100 kΩ with minimum of 50 kΩ and maximum of 150 kΩ.
Table 15. Pull-up/pull-down selection register (address 44h)
Bit
7
6
5
4
3
2
1
0
Symbol
PUD7
PUD6
PUD5
PUD4
PUD3
PUD2
PUD1
PUD0
Default
1
1
1
1
1
1
1
1
7.4.9 Interrupt mask register (45h)
Interrupt mask register is set to logic 1 upon power-on, disabling interrupts during system start-up. Interrupts
may be enabled by setting corresponding mask bits to logic 0. If an input changes state and the corresponding
bit in the Interrupt mask register is set to 1, the interrupt is masked and the interrupt pin (INT) is not asserted. If
the corresponding bit in the Interrupt mask register is set to 0, the interrupt pin is asserted.
When an input changes state and the resulting interrupt is masked (interrupt mask bit is 1), setting the input
mask register bit to 0 causes the interrupt pin to be asserted. If the interrupt mask bit of an input that is currently
the source of an interrupt is set to 1, the interrupt pin is de-asserted.
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PCAL6408A
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Table 16. Interrupt mask register (address 45h)
Bit
7
6
5
4
3
2
1
0
Symbol
M7
M6
M5
M4
M3
M2
M1
M0
Default
1
1
1
1
1
1
1
1
7.4.10 Interrupt status register (46h)
This read-only register is used to identify the source of an interrupt. When read, a logic 1 indicates that the
corresponding input pin was the source of the interrupt. A logic 0 indicates that the input pin is not the source of
an interrupt.
When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt status bit returns logic
0.
Table 17. Interrupt status register (address 46h)
Bit
7
6
5
4
3
2
1
0
Symbol
S7
S6
S5
S4
S3
S2
S1
S0
Default
0
0
0
0
0
0
0
0
7.4.11 Output port configuration register (4Fh)
The output port configuration register selects port-wise push-pull or open-drain I/O stage. A logic 0 configures
the I/O as push-pull (Q1 and Q2 are active, see Figure 10). A logic 1 configures the I/O as open-drain (Q1 is
disabled, Q2 is active) and the recommended command sequence is to program this register (4Fh) before the
Configuration register (03h) sets the port pins as outputs.
Table 18. Output port configuration register (address 4Fh)
Bit
7
6
5
Symbol
Default
4
3
2
1
ODEN
reserved
0
0
0
0
0
0
0
0
0
7.5 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output port register.
In this case, there are low-impedance paths between the I/O pin and either VDD(P) or VSS. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
data from
shift register
output port
register data
configuration
register
data from
shift register
D
write
configuration
pulse
CK
VDD(P)
Q
Q1
ESD
protection
diode
Q2
ESD
protection
diode
FF
Q
D
Q
P0 to P7
FF
write pulse
CK
output port
register
VSS
D
Q
input port
register data
FF
read pulse
CK
VDD(P)
PULL-UP/PULL-DOWN
CONTROL
INTERRUPT
MASK
input port
register
100 k
D
input latch
register
data from
shift register
write input
latch pulse
D
Q
LATCH
Q
read pulse
FF
CK
to INT
polarity inversion
register
data from
shift register
D
write polarity
pulse
CK
EN
input port
latch
Q
FF
002aah089
On power-up or reset, all registers return to default values.
Figure 10. Simplified schematic of the I/Os (P0 to P7)
7.6 Power-on reset
When power (from 0 V) is applied to VDD(P), an internal power-on reset holds the PCAL6408A in a reset
condition until VDD(P) has reached VPOR. At that time, the reset condition is released and the PCAL6408A
2
registers and I C-bus/SMBus state machine initialize to their default states. After that, VDD(P) must be lowered to
below VPOR and back up to the operating voltage for a power-reset cycle. See Section 9.3requirements".
7.7 Reset input (RESET)
The RESET input can be asserted to initialize the system while keeping the VDD(P) at its operating level. A reset
can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCAL6408A registers and
2
I C-bus/SMBus state machine are changed to their default state once RESET is LOW (0). When RESET is
HIGH (1), the I/O levels at the P port can be changed externally or through the controller. This input requires a
pull-up resistor to VDD(I2C-bus) if no active connection is used.
7.8 Interrupt output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode. After time tv(INT), the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting or when data is read from the port that generated the interrupt (see Figure 14). Resetting occurs in the
Read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
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PCAL6408A
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of
the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause
a false interrupt to occur, if the state of the pin does not match the contents of the Input port register.
The INT output has an open-drain structure and requires a pull-up resistor to VDD(P) or VDD(I2C-bus) depending
on the application. INT should be connected to the voltage source of the device that requires the interrupt
information. When using the input latch feature, the input pin state is latched. The interrupt is reset only when
data is read from the port that generated the interrupt. The reset occurs in the Read mode at the acknowledge
(ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
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PCAL6408A
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
8 Bus transactions
2
The PCAL6408A is an I C-bus target device. Data is exchanged between the controller and PCAL6408A
2
through write and read commands using I C-bus. The two communication lines are a serial data line (SDA)
and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Write commands
Data is transmitted to the PCAL6408A by sending the device address and setting the Least Significant Bit (LSB)
to a logic 0 (see Figure 8 for device address). The command byte is sent after the address and determines
which register receives the data that follows the command byte. There is no limitation on the number of data
bytes sent in one write transmission.
SCL
1
2
3
4
5
6
7
8
9
target address
SDA S
0
1
0
0
command byte
AD
0
0 DR 0
START condition
A
R/W
0
0
0
0
0
0
STOP
condition
data to port
0
1
acknowledge
from target
A
DATA 1
A
acknowledge
from target
P
acknowledge
from target
write to port
tv(Q)
data out from port
DATA 1 VALID
002aaf825
Figure 11. Write to Output port register
SCL
1
2
3
4
5
6
7
8
9
target address
SDA S
0
1
0
0
START condition
0
command byte
AD
0 DR 0
R/W
A
0 1/0 0
0
0 1/0 1/0 1/0 A
acknowledge
from target
STOP
condition
data to register
acknowledge
from target
DATA 1
A
P
acknowledge
from target
002aah090
Figure 12. Write to Configuration or Polarity inversion registers
8.2 Read commands
To read data from the PCAL6408A, the bus controller must first send the PCAL6408A address with the least
significant bit set to a logic 0 (see Figure 8 for device address). The command byte is sent after the address and
determines which register is to be accessed.
After a restart the device address is sent again, but this time the LSB is set to a logic 1. Data from the register
defined by the command byte then is sent by the PCAL6408A (see Figure 13 and Figure 14).
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limit on the number
of data bytes received in one read transmission, but on the final byte received the bus controller must not
acknowledge the data.
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
target address
SDA S
0
1
0
0
command byte
0 AD 0
0
A
DR
START condition
0
0
0
0
R/W
target address
0
1
0
0
0
(repeated)
START condition
0
1 1/0 A
(cont.)
acknowledge
from target
acknowledge
from target
(cont.) S
0
data from register
0 AD 1
A
DR
DATA (first byte)
data from register
A
R/W
DATA (last byte)
acknowledge
from controller
acknowledge
from target
NA P
no acknowledge
from controller
at this moment controller-transmitter becomes controller-receiver
and target-receiver becomes target-transmitter
STOP
condition
002aaf827
Figure 13. Read from register
SCL
1
2
3
4
5
6
7
8
9
target address
SDA S
0
1
0
0
START condition
0
data from port
0 AD 1
DR
R/W
A
DATA 1
data from port
A
acknowledge from target
DATA 4
acknowledge from controller
read from
port
data into
port
DATA 1
DATA 2
th(D)
DATA 3
tsu(D)
INT
tv(INT)
trst(INT)
DATA 4
no acknowledge
from controller
1
P
STOP
condition
DATA 5
INT is cleared by
read from port
STOP not needed
to clear INT
002aaf828
Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte has previously been programmed with
00h (read Input port register).
This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call
and actual data transfer from P port (see Figure 13).
Figure 14. Read Input port register (non-latched)
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
SCL
1
2
3
4
5
6
7
8
9
target address
SDA S
0
1
0
0
START condition
0
data from port
0 AD 1
DR
R/W
A
DATA 1
data from port
A
acknowledge from target
DATA 2
acknowledge from controller
read from
port
data into
port
DATA 1
DATA 2
INT
tv(INT)
1
P
STOP
condition
DATA 1
tsu(D)
th(D)
no acknowledge
from controller
trst(INT)
INT is cleared by
read from port
STOP not needed
to clear INT
002aah091
Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte has previously been programmed with
00h (read Input port register).
This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call
and actual data transfer from P port (see Figure 13).
Figure 15. Read Input port register (latch enabled)
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Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
9 Application design-in information
VDD(I2C-bus)
VDD(P)
VDD(I2C-bus) = 1.8 V
10 kΩ
10 kΩ
10 kΩ
10 kΩ
VDD
10 kΩ (× 3)
VDD(I2C-bus) VDD(P)
CONTROLLER
P0
SCL
SDA
SCL
SDA
INT
RESET
SUBSYSTEM 1
(e.g., alarm system)
A
INT
RESET
VSS
ALARM(1)
P1
controlled
switch
enable
B
PCAL6408A
P2
P3
ADDR
P4
P5
KEYPAD
P6
VSS
P7
002aah092
Device address configured as 0100 000x for this example.
P0 and P2 through P4 are configured as inputs.
P1 and P5 through P7 are configured as outputs.
1. Resistors are required for inputs (on P port) that may float. If a driver to an input will never let the input float, a resistor
is not needed. Outputs (in the P port) do not need pull-up resistors.
Figure 16. Typical application
9.1 Minimizing IDD when I/Os control LEDs
When the I/Os are used to control LEDs, normally they are connected to VDD through a resistor as shown in
Figure 16. The LED acts as a diode, so when the LED is off, the I/O VI is about 1.2 V less than VDD. The ΔIDD
parameter in Table 23 shows how IDD increases as VI becomes lower than VDD. Designs that must minimize
current consumption, such as battery power applications, should consider maintaining the I/O pins greater than
or equal to VDD when the LED is off.
Figure 17 shows a high-value resistor in parallel with the LED. Figure 18 shows VDD less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevent additional
supply current consumption when the LED is off.
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Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
VDD
VDD(P)
LED
Pn
002aah278
Figure 17. High-value resistor in parallel with the LED
3.3 V
5V
VDD(P)
LED
Pn
002aah279
Figure 18. Device supplied by a lower voltage
9.2 Output drive strength control
The Output drive strength registers allow the user to control the output drive level of the GPIO. Each GPIO can
be configured independently to one of the four possible output current levels. By programming these bits the
user is changing the number of transistor pairs or ‘fingers’ that drive the I/O pad.
Figure 19 shows a simplified output stage. The behavior of the pad is affected by the Configuration register, the
output port data, and the current control register. When the Current Control register bits are programmed to 10b,
then only two of the fingers are active, reducing the current drive capability by 50 %.
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
PMOS_EN0
Current Control
register
DECODER
PMOS_EN[3:0]
NMOS_EN[3:0]
Configuration
register
VDD(P)
PMOS_EN1
PMOS_EN2
PMOS_EN3
P0 to P7
Output port
register
NMOS_EN3
NMOS_EN2
NMOS_EN1
NMOS_EN0
002aah093
Figure 19. Simplified output stage
Reducing the current drive capability may be desirable to reduce system noise. When the output switches
(transitions from H/L), there is a peak current that is a function of the output drive selection. This peak
current runs through VDD and VSS package inductance and creates noise (some radiated, but more critically
Simultaneous Switching Noise (SSN)). In other words, switching many outputs at the same time creates ground
and supply noise. The output drive strength control through the Output Drive Strength registers allows the user
to mitigate SSN issues without the need of additional external components.
9.3 Power-on reset requirements
In the event of a glitch or data corruption, PCAL6408A can be reset to its default conditions by using the poweron reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 20 and Figure 21.
VDD(P)
ramp-up
ramp-down
re-ramp-up
td(rst)
(dV/dt)r
(dV/dt)f
time to re-ramp
when VDD(P) drops
below 0.2 V or to VSS
(dV/dt)r
time
002aag960
Figure 20. VDD is lowered below 0.2 V or 0 V and then ramped up to VDD
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
VDD(P)
ramp-down
ramp-up
td(rst)
VI drops below POR levels
(dV/dt)f
time to re-ramp
when VDD(P) drops
to VPOR(min) - 50 mV
time
(dV/dt)r
002aag961
Figure 21. VDD is lowered below the POR threshold, then ramped back up to VDD
Table 19 specifies the performance of the power-on reset feature for PCAL6408A for both types of power-on
reset.
Table 19. Recommended supply sequencing and ramp rates
Tamb = 25 °C (unless otherwise noted). Not tested; specified by design.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
(dV/dt)f
fall rate of change of voltage
Figure 20
0.1
-
2000
ms
(dV/dt)r
rise rate of change of voltage
Figure 20
0.1
-
2000
ms
td(rst)
reset delay time
Figure 20; re-ramp time when
VDD(P) drops below 0.2 V or to VSS
1
-
-
μs
Figure 21; re-ramp time when
VDD(P) drops to VPOR(min) - 50 mV
1
-
-
μs
ΔVDD(gl)
glitch supply voltage difference
Figure 22
[1]
-
-
1.0
V
[2]
-
-
10
μs
tw(gl)VDD
supply voltage glitch pulse width
Figure 22
VPOR(trip)
power-on reset trip voltage
falling VDD(P)
0.7
-
-
V
rising VDD(P)
-
-
1.4
V
[1]
[2]
Level that VDD(P) can glitch down to with a ramp rate of 0.4 μs/V, but not cause a functional disruption when tw(gl)VDD < 1 μs.
Glitch width that will not cause a functional disruption when ΔVDD(gl) = 0.5 × VDD(P).
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch
width (tw(gl)VDD) and glitch height (ΔVDD(gl)) are dependent on each other. The bypass capacitance, source
impedance, and device impedance are factors that affect power-on reset performance. Figure 22 and Table 19
provide more information on how to measure these specifications.
VDD(P)
VDD(gl)
tw(gl)VDD
time
002aag962
Figure 22. Glitch width and glitch height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all
2
the registers and the I C-bus/SMBus state machine are initialized to their default states. The value of VPOR
differs based on the VDD being lowered to or from 0 V. Figure 23 and Table 19 provide more details on this
specification.
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PCAL6408A
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
VDD(P)
VPOR (rising VDD(P))
VPOR (falling VDD(P))
time
POR
time
002aag963
Figure 23. Power-on reset voltage (VPOR)
9.4 Device current consumption with internal pull-up and pull-down resistors
The PCAL6408A integrates programmable pull-up and pull-down resistors to eliminate external components
when pins are configured as inputs and pull-up or pull-down resistors are required (for example, nothing is
driving the inputs to the power supply rails. Since these pull-up and pull-down resistors are internal to the device
itself, they contribute to the current consumption of the device and must be considered in the overall system
design.
The pull-up or pull-down function is selected in register 44h, while the resistor is connected by the enable
register 43h. The configuration of the resistors is shown in Figure 10.
If the resistor is configured as a pull-up, that is, connected to VDD, a current flows from the VDD(P) pin through
the resistor to ground when the pin is held LOW. This current appears as additional IDD upsetting any current
consumption measurements.
In the same manner, if the resistor is configured as a pull-down and the pin is held HIGH, current flows from
the power supply through the pin to the VSS pin. While this current is not measured as part of IDD, one must be
mindful of the 200 mA limiting value through VSS.
The pull-up and pull-down resistors are simple resistors and the current is linear with voltage. The resistance
specification for these devices spans from 50 kΩ with a nominal 100 kΩ value. Any current flow through these
resistors is additive by the number of pins held HIGH or LOW and the current can be calculated by Ohm’s law.
See Figure 27 for a graph of supply current versus the number of pull-up resistors.
PCAL6408A
Product data sheet
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NXP Semiconductors
2
PCAL6408A
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
10 Limiting values
Table 20. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
2
VDD(I2C-bus)
I C-bus supply voltage
VDD(P)
supply voltage port P
Min
Max
Unit
-0.5
+6.5
V
-0.5
+6.5
V
input voltage
[1]
-0.5
+6.5
V
VO
output voltage
[1]
-0.5
+6.5
V
IIK
input clamping current
ADDR, RESET, SCL; VI < 0 V
-
±20
mA
IOK
output clamping current
INT; VO < 0 V
-
±20
mA
IIOK
input/output clamping current
P port; VO < 0 V or VO > VDD(P)
-
±20
mA
SDA; VO < 0 V or VO > VDD(I2C-bus)
-
±20
mA
continuous; P port; VO = 0 V to VDD(P)
-
50
mA
continuous; SDA, INT; VO = 0 V to VDD(I2C-bus)
-
25
mA
VI
IOL
LOW-level output current
IOH
HIGH-level output current
continuous; P port; VO = 0 V to VDD(P)
-
25
mA
IDD
supply current
continuous through VSS
-
200
mA
IDD(P)
supply current port P
continuous through VDD(P)
-
160
mA
continuous through VDD(I2C-bus)
-
10
mA
-65
+150
°C
2
IDD(I2C-bus)
I C-bus supply current
Tstg
storage temperature
[1]
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
PCAL6408A
Product data sheet
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
11 Recommended operating conditions
Table 21. Operating conditions
Symbol
Parameter
Conditions
2
Min
Max
Unit
VDD(I2C-bus)
I C-bus supply voltage
1.65
5.5
V
VDD(P)
supply voltage port P
1.65
5.5
V
VIH
HIGH-level input voltage
SCL, SDA, RESET
0.7 × VDD(I2C-bus)
5.5
V
ADDR, P7 to P0
0.7 × VDD(P)
5.5
V
SCL, SDA, RESET
-0.5
0.3 × VDD(I2C-bus)
V
ADDR, P7 to P0
-0.5
0.3 × VDD(P)
V
VIL
LOW-level input voltage
IOH
HIGH-level output current
P7 to P0
-
10
mA
IOL
LOW-level output current
P7 to P0
-
25
mA
Tamb
ambient temperature
operating in free air
-40
+85
°C
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
12 Thermal characteristics
Table 22. Thermal characteristics
Symbol
Zth(j-a)
[1]
Parameter
Conditions
transient thermal impedance from junction to ambient
Max
Unit
TSSOP16 package
[1]
108
K/W
HVQFN16 package
[1]
53
K/W
XQFN16 package
[1]
184
K/W
The package thermal impedance is calculated in accordance with JESD 51-7.
PCAL6408A
Product data sheet
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
13 Static characteristics
Table 23. Static characteristics
Tamb = -40 °C to +85 °C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified.
Symbol
Parameter
Conditions
VIK
input clamping voltage
II = -18 mA; VDD(P) = 1.65 V to 5.5 V
Unit
-
-
V
-
1
1.4
V
VDD(P) = 1.65 V
1.2
-
-
V
VDD(P) = 2.3 V
1.8
-
-
V
VDD(P) = 3 V
2.6
-
-
V
VDD(P) = 4.5 V
4.1
-
-
V
VDD(P) = 1.65 V
1.1
-
-
V
VDD(P) = 2.3 V
1.7
-
-
V
VDD(P) = 3 V
2.5
-
-
V
VDD(P) = 4.5 V
4.0
-
-
V
VDD(P) = 1.65 V
-
-
0.45
V
VDD(P) = 2.3 V
-
-
0.25
V
VDD(P) = 3 V
-
-
0.25
V
VDD(P) = 4.5 V
-
-
0.2
V
VDD(P) = 1.65 V
-
-
0.5
V
VDD(P) = 2.3 V
-
-
0.3
V
VDD(P) = 3 V
-
-
0.25
V
-
-
0.2
V
3
-
-
mA
-
mA
VPOR
power-on reset voltage
VI = VDD(P) or VSS; IO = 0 mA; VDD(P) = 1.65 V to
5.5 V
VOH
HIGH-level output
[3]
voltage
P port; IOH = -8 mA; CCX = 11b
Typ
-1.2
[1]
Max
[2]
Min
P port; IOH = -2.5 mA and CCX = 00b;
IOH = -5 mA and CCX = 01b;
IOH = -7.5 mA and CCX = 10b;
IOH = -10 mA and CCX = 11b;
VOL
LOW-level output
[3]
voltage
P port; IOL = 8 mA; CCX = 11b
P port; IOL = 2.5 mA and CCX = 00b;
IOL = 5 mA and CCX = 01b;
IOL = 7.5 mA and CCX = 10b;
IOL = 10 mA and CCX = 11b;
VDD(P) = 4.5 V
IOL
LOW-level output current
VOL = 0.4 V; VDD(P) = 1.65 V to 5.5 V
SDA
INT
II
input current
PCAL6408A
Product data sheet
[4]
[5]
3
15
SCL, SDA, RESET; VI = VDD(I2C-bus) or VSS
-
-
±1
μA
ADDR; VI = VDD(P) or VSS
-
-
±1
μA
VDD(P) = 1.65 V to 5.5 V
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Table 23. Static characteristics...continued
Tamb = -40 °C to +85 °C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
IIH
HIGH-level input current
P port; VI = VDD(P); VDD(P) = 1.65 V to 5.5 V
-
IIL
LOW-level input current
P port; VI = VSS; VDD(P) = 1.65 V to 5.5 V
IDD
supply current
IDD(I2C-bus) + IDD(P); Operating mode;
SDA, P port, ADDR, RESET;
VI on SDA and RESET = VDD(I2C-bus) or VSS; VI on
P port and ADDR = VDD(P) or VSS; IO = 0 mA; I/O
= inputs; fSCL = 400 kHz
[1]
Max
Unit
-
1
μA
-
-
1
μA
VDD(P) = 3.6 V to 5.5 V
-
10
25
μA
VDD(P) = 2.3 V to 3.6 V
-
6.5
15
μA
VDD(P) = 1.65 V to 2.3 V
-
4
9
μA
VDD(P) = 3.6 V to 5.5 V
-
1.5
7
μA
VDD(P) = 2.3 V to 3.6 V
-
1
3.2
μA
VDD(P) = 1.65 V to 2.3 V
-
0.5
1.7
μA
VDD(P) = 3.6 V to 5.5 V
-
60
125
μA
VDD(P) = 2.3 V to 3.6 V
-
40
75
μA
VDD(P) = 1.65 V to 2.3 V
-
20
45
μA
-
0.55
0.75
mA
SCL, SDA, RESET;
one input at VDD(I2C-bus) - 0.6 V,
other inputs at VDD(I2C-bus) or VSS;
VDD(P) = 1.65 V to 5.5 V
-
-
25
μA
P port, ADDR;
one input at VDD(P) - 0.6 V,
other inputs at VDD(P) or VSS;
-
-
80
μA
IDD(I2C-bus) + IDD(P); Standby mode;
SCL, SDA, P port, ADDR, RESET;
VI on SCL, SDA and RESET = VDD(I2C-bus) or VSS;
VI on P port and ADDR = VDD(P); IO = 0 mA; I/O =
inputs; fSCL = 0 kHz
Active mode; IDD(I2C-bus) + IDD(P);
P port, ADDR, RESET;
VI on RESET = VDD(I2C-bus);
VI on P port and ADDR = VDD(P);
IO = 0 mA; I/O = inputs;
fSCL = 400 kHz, continuous register read
with pull-ups enabled;
IDD(I2C-bus) + IDD(P); P port, ADDR, RESET;
VI on SCL, SDA and RESET = VDD(I2C-bus) or VSS;
VI on P port = VSS;
VI on ADDR = VDD(I2C-bus) or VSS;
IO = 0 mA; I/O = inputs with pull-up enabled; fSCL
= 0 kHz
VDD(P) = 1.65 V to 5.5 V
ΔIDD
additional quiescent
[6]
supply current
PCAL6408A
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PCAL6408A
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Table 23. Static characteristics...continued
Tamb = -40 °C to +85 °C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
[1]
Max
Unit
VDD(P) = 1.65 V to 5.5 V
Ci
input capacitance
SCL; VI = VDD(I2C-bus) or VSS;
VDD(P) = 1.65 V to 5.5 V
-
6
7
pF
Cio
input/output capacitance
SDA; VI/O = VDD(I2C-bus) or VSS;
VDD(P) = 1.65 V to 5.5 V
-
7
8
pF
P port; VI/O = VDD(P) or VSS;
VDD(P) = 1.65 V to 5.5 V
-
7.5
8.5
pF
Rpu(int)
internal pull-up resistance input/output
50
100
150
kΩ
Rpd(int)
internal pull-down
resistance
50
100
150
kΩ
[1]
[2]
[3]
[4]
[5]
[6]
input/output
All typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V or 5 V VDD) and Tamb = 25 °C.
When power (from 0 V) is applied to VDD(P), an internal power-on reset holds the PCAL6408A in a reset condition until VDD(P) has reached VPOR. At that
2
time, the reset condition is released, and the PCAL6408A registers and I C-bus/SMBus state machine initialize to their default states. After that, VDD(P)
must be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle.
The total current sourced by all I/Os must be limited to 80 mA.
Each I/O must be externally limited to a maximum of 25 mA, for a device total of 200 mA.
Typical value for Tamb = 25 °C. VOL = 0.4 V and VDD = 3.3 V. Typical value for VDD < 2.5 V, VOL = 0.6 V.
Internal pull-up/pull-down resistor disabled.
13.1 Typical characteristics
IDD
(µA)
002aag973
20
16
VDD(P) = 5.5 V
5.0 V
3.6 V
12
3.3 V
2.5 V
2.3 V
8
4
0
- 40
VDD(P) = 1.8 V
1.65 V
- 15
10
35
60
85
Tamb (°C)
Figure 24. Supply current versus ambient temperature
PCAL6408A
Product data sheet
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
002aag974
1400
IDD(stb)
(nA)
VDD(P) = 5.5 V
5.0 V
3.6 V
3.3 V
1000
800
600
400
2.5 V
2.3 V
1.8 V
1.65 V
200
0
- 40
- 15
10
35
60
85
Tamb (°C)
Figure 25. Standby supply current versus ambient temperature
002aag975
20
IDD
(µA)
16
12
8
4
0
1.5
2.5
3.5
4.5
5.5
VDD(P) (V)
Tamb = 25 °C
Figure 26. Supply current versus supply voltage
002aah245
600
Tamb = - 40 °C
25 °C
85 °C
IDD(P)
(µA)
400
200
0
0
2
4
6
8
number of I/O held LOW
VDD(P) = 5 V
Figure 27. Supply current versus number of I/O held LOW
PCAL6408A
Product data sheet
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NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Isink
(mA)
002aaf578
35
30
Tamb = - 40 °C
25 °C
85 °C
25
20
15
10
5
0
0
0.1
0.2
VOL (V)
0.3
a. VDD(P) = 1.65 V
Isink
(mA)
002aaf579
35
30
Tamb = - 40 °C
25 °C
85 °C
25
20
15
10
5
0
0
0.1
0.2
VOL (V)
0.3
b. VDD(P) = 1.8 V
Isink
(mA)
002aaf580
50
40
Tamb = - 40 °C
25 °C
85 °C
30
20
10
0
0
0.1
0.2
VOL (V)
0.3
c. VDD(P) = 2.5 V
002aaf581
60
Isink
(mA)
Tamb = - 40 °C
25 °C
85 °C
40
20
PCAL6408A
Product data sheet
All information provided in this document is subject to legal disclaimers.
0
0
Rev. 3.3 — 14 October 2024
0.1
0.2
VOL (V)
0.3
d. VDD(P) = 3.3 V
70
002aaf582
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PCAL6408A
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
002aaf561
30
Isource
(mA)
Tamb = - 40 °C
25 °C
85 °C
20
10
0
0
0.2
0.4
0.6
VDD(P) - VOH (V)
a. VDD(P) = 1.65 V
Isource
(mA)
002aaf562
35
Tamb = - 40 °C
25 °C
85 °C
30
25
20
15
10
5
0
0
0.2
0.4
0.6
VDD(P) - VOH (V)
b. VDD(P) = 1.8 V
002aaf563
60
Isource
(mA)
Tamb = - 40 °C
25 °C
85 °C
40
20
0
0
0.2
0.4
0.6
VDD(P) - VOH (V)
c. VDD(P) = 2.5 V
Isource
(mA)
002aaf564
70
Tamb = - 40 °C
25 °C
85 °C
60
50
40
30
20
10
PCAL6408A
Product data sheet
All information provided in this document is subject to legal disclaimers.
0
0
Rev. 3.3 — 14 October 2024
0.2
0.4
0.6
VDD(P) - VOH (V)
d. VDD(P) = 3.3 V
90
002aaf565
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
VOL
(mV)
002aah056
120
100
(1)
80
60
(2)
40
(4)
20
(3)
0
- 40
1.
2.
3.
4.
- 15
10
35
60
85
Tamb (°C)
VDD(P) = 1.8 V; Isink = 10 mA
VDD(P) = 5 V; Isink = 10 mA
VDD(P) = 1.8 V; Isink = 1 mA
VDD(P) = 5 V; Isink = 1 mA
Figure 30. LOW-level output voltage versus temperature
002aah057
200
VDD(P) - VOH (mV)
160
120
VDD(P) = 1.8 V
5V
80
40
0
- 40
- 15
10
35
60
85
Tamb (°C)
Isource = -10 mA
Figure 31. I/O high voltage versus temperature
PCAL6408A
Product data sheet
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PCAL6408A
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
14 Dynamic characteristics
2
Table 24. I C-bus interface timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 32.
Symbol
Parameter
Conditions
Standard2
mode I C-bus
2
Fast-mode I C-bus
Min
Max
Min
Max
Unit
fSCL
SCL clock frequency
0
100
0
400
kHz
tHIGH
HIGH period of the SCL clock
4
-
0.6
-
μs
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
μs
tSP
pulse width of spikes that must be
suppressed by the input filter
0
50
0
50
ns
tSU;DAT
data set-up time
250
-
100
-
ns
tHD;DAT
data hold time
0
-
0
-
ns
tr
rise time of both SDA and SCL signals
-
1000
20
300
ns
tf
fall time of both SDA and SCL signals
-
300
20 × (VDD
/ 5.5 V)
300
ns
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
μs
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
μs
tHD;STA
hold time (repeated) START condition
4
-
0.6
-
μs
tSU;STO
set-up time for STOP condition
4
-
0.6
-
μs
tVD;DAT
data valid time
SCL LOW to
SDA output valid
-
3.45
-
0.9
μs
tVD;ACK
data valid acknowledge time
ACK signal from
SCL LOW to
SDA (out) LOW
-
3.45
-
0.9
μs
Table 25. Reset timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 35.
Symbol
Parameter
Conditions
Standard2
mode I C-bus
Fast-mode
2
I C-bus
Min
Max
Min
Max
Unit
tw(rst)
reset pulse width
30
-
30
-
ns
trec(rst)
reset recovery time
200
-
200
-
ns
trst
reset time
600
-
600
-
ns
PCAL6408A
Product data sheet
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Table 26. Switching characteristics
Over recommended operating free air temperature range; CL ≤ 100 pF; unless otherwise specified. See Figure 34.
Symbol
Parameter
Conditions
Standard2
mode I C-bus
Fast-mode
2
I C-bus
Min
Max
Min
Max
Unit
tv(INT)
valid time on pin INT
from P port to INT
-
1
-
1
μs
trst(INT)
reset time on pin INT
from SCL to INT
-
1
-
1
μs
tv(Q)
data output valid time
from SCL to P port
-
400
-
400
ns
tsu(D)
data input set-up time
from P port to SCL
0
-
0
-
ns
th(D)
data input hold time
from P port to SCL
300
-
300
-
ns
PCAL6408A
Product data sheet
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
15 Parameter measurement information
VDD(I2C-bus)
RL = 1 k
DUT
SDA
CL = 50 pF
002aag977
a. SDA load configuration
two bytes for read Input port register(1)
STOP
START
condition condition
(P)
(S)
Address
Bit 7
(MSB)
Address
Bit 1
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
STOP
condition
(P)
002aag952
b. Transaction format
tHIGH
tLOW
tSP
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)
SCL
tBUF
tr
tVD;DAT
tf
tf(o)
tVD;ACK
tSU;STA
SDA
tf
tr
tHD;STA
tSU;DAT
tHD;DAT
tSU;STO
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)
tVD;ACK
repeat START condition
STOP condition
002aag978
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr/tf ≤ 30 ns.
All parameters and waveforms are not applicable to all devices.
2
Byte 1 = I C-bus address; Byte 2, byte 3 = P port data.
1. See Figure 14.
c. Voltage waveforms
2
Figure 32. I C-bus interface load circuit and voltage waveforms
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
VDD(I2C-bus)
RL = 4.7 k
INT
DUT
CL = 100 pF
002aag979
a. Interrupt load configuration
acknowledge
from target
START condition
R/W
8 bits (one data byte)
from port
target address
SDA S
SCL
0
1
1
2
0
0
3
4
0
5
0 AD 1
DR
6
7
8
acknowledge
from target
A
DATA 1
no acknowledge
from controller
STOP
condition
data from port
A
DATA 2
1
P
9
B
trst(INT) B
trst(INT)
INT
tv(INT)
data into
port
A
A
tsu(D)
ADDRESS
INT
DATA 1
0.5 × VDD(I2C-bus)
SCL
DATA 2
R/W
tv(INT)
0.3 × VDD(I2C-bus)
trst(INT)
0.5 × VDD(P)
Pn
0.7 × VDD(I2C-bus)
A
0.5 × VDD(I2C-bus)
INT
View A - A
View B - B
002aag980
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr/tf ≤ 30 ns.
All parameters and waveforms are not applicable to all devices.
b. Voltage waveforms
Figure 33. Interrupt load circuit and voltage waveforms
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Pn
DUT
500
CL = 50 pF
2 × VDD(P)
500
002aag981
a. P port load configuration
SCL
P0
A
P7
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)
SDA
tv(Q)
Pn
unstable
data
last stable bit
A
P7
002aag982
b. Write mode (R/W = 0)
SCL
P0
tsu(D)
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)
th(D)
Pn
0.5 × VDD(P)
002aag983
CL includes probe and jig capacitance.
tv(Q) is measured from 0.7 × VDD(I2C-bus) on SCL to 50 % I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr/tf ≤ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
c. Read mode (R/W = 1)
Figure 34. P port load circuit and voltage waveforms
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
VDD(I2C-bus)
RL = 1 k
SDA
DUT
CL = 50 pF
002aag977
a. SDA load configuration
DUT
Pn
500
CL = 50 pF
2 × VDD(P)
500
002aag981
b. P port load configuration
START
SCL
ACK or read cycle
SDA
0.3 × VDD(I2C-bus)
trst
RESET
0.5 × VDD(I2C-bus)
trec(rst)
tw(rst)
trst
Pn
trec(rst)
0.5 × VDD(P)
002aag984
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr/tf ≤ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
I/Os are configured as inputs.
All parameters and waveforms are not applicable to all devices.
c. RESET timing
Figure 35. Reset load circuits and voltage waveforms
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
16 Package outline
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
D
SOT403-1
E
A
X
c
y
HE
v M A
Z
9
16
Q
A2
pin 1 index
(A 3 )
A1
A
θ
Lp
1
L
8
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Figure 36. Package outline SOT403-1 (TSSOP16)
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3 x 3 x 0.85 mm
B
D
SOT758-1
A
terminal 1
index area
A
E
A1
c
detail X
e1
C
1/2 e
e
5
8
y
y1 C
v M C A B
w M C
b
L
4
9
e
e2
Eh
1/2 e
12
1
16
terminal 1
index area
13
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A (1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1
2.9
1.75
1.45
3.1
2.9
1.75
1.45
0.5
1.5
1.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
2. Terminal 1 feature shape, size and location may vary.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT758-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-21
24-05-24
Figure 37. Package outline SOT758-1 (HVQFN16)
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
XQFN16: plastic, extremely thin quad flat package; no leads;
16 terminals; body 1.80 x 2.60 x 0.50 mm
SOT1161-1
X
B
D
A
terminal 1
index area
E
A
A1
A3
detail X
e1
e
b
5
v
w
8
C
C A B
C
y1 C
y
L
4
9
e
e2
1
terminal 1
index area
12
16
L1
13
0
1
Dimensions
Unit(1)
mm
max
nom
min
2 mm
scale
A
A1
0.5
0.05
A3
b
0.25
0.127 0.20
0.00
0.15
D
E
e
e1
e2
1.9
1.8
1.7
2.7
2.6
2.5
0.4
1.2
1.2
L
L1
0.45 0.55
0.40 0.50
0.35 0.45
v
0.1
w
y
y1
0.05 0.05 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
References
Outline
version
IEC
JEDEC
JEITA
SOT1161-1
---
---
---
sot1161-1_po
European
projection
Issue date
09-12-28
09-12-29
Figure 38. Package outline SOT1161-1 (XQFN16)
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
XFBGA16: plastic, extremely thin fine-pitch ball grid array package; 16 balls
D
B
SOT1354-1
A
ball A1
index area
A2
A
E
A1
detail X
e1
C
e
Øv
Øw
b
C A B
C
y1 C
y
D
e
C
e2
B
A
ball A1
index area
1
2
3
4
X
0
2 mm
scale
Dimensions (mm are the original dimensions)
Unit
mm
max
nom
min
A
0.5
A1
A2
b
D
0.15 0.35 0.205 1.7
0.10 0.34 0.175 1.6
0.05 0.33 0.145 1.5
E
e
e1
e2
1.7
1.6
1.5
0.4
1.2
1.2
v
w
y
0.15 0.05 0.08
y1
0.1
sot1354-1_po
References
Outline
version
IEC
JEDEC
JEITA
SOT1354-1
---
---
---
European
projection
Issue date
13-03-26
13-08-27
Figure 39. Package outline SOT1354-1 (XFBGA16)
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PCAL6408A
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Figure 40. Package outline SOT1896-1 (X2QFN16)
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PCAL6408A
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
17 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can
be found in Application Note AN10365 “Surface mount reflow soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards
(PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection.
There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when
through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with
increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of
liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have
solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch
smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by component placement and
exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all
reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave
parameters, and the time during which components are exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak
temperatures (see Figure 41) than a SnPb process, thus reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large
and small components on one board
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Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak
temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to
make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low
enough that the packages and/or boards are not damaged. The peak temperature of the package depends on
package thickness and volume and is classified in accordance with Table 27 and Table 28
Table 27. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 28. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.
Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 41.
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 41. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow
soldering description”.
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Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
18 Soldering: PCB footprints
Footprint information for reflow soldering of HVQFN16 package
SOT758-1
Hx
Gx
D
P
0.025
0.025
C
(0.105)
SPx
Hy
SPy tot
nSPx
Gy
SPy
nSPy
SLy
By
Ay
SPx tot
SLx
Bx
Ax
solder land
solder paste deposit
solder land plus solder paste
occupied area
nSPx
nSPy
2
2
Dimensions in mm
P
Ax
Ay
Bx
By
C
D
SLx
SLy
0.50
4.00
4.00
2.20
2.20
0.90
0.24
1.50
1.50
Issue date
SPx tot SPy tot
0.90
0.90
SPx
SPy
Gx
Gy
Hx
Hy
0.30
0.30
3.30
3.30
4.25
4.25
12-03-07
12-03-08
sot758-1_fr
Figure 42. PCB footprint for SOT758-1 (HVQFN16); reflow soldering
PCAL6408A
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Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Footprint information for reflow soldering of TSSOP16 package
SOT403-1
Hx
Gx
P2
(0.125)
Hy
Gy
(0.125)
By
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650
0.750
7.200
4.500
1.350
0.400
0.600
5.600
5.300
5.800
7.450
sot403-1_fr
Figure 43. PCB footprint for SOT403-1 (TSSOP16); reflow soldering
PCAL6408A
Product data sheet
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2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Footprint information for reflow soldering of XQFN16 package
SOT1161-1
2.35
2.1 CU
1.65
0.4 (12×)
0.45
0.22
CU
(16×)
3.15
1.8
CU
1.65
2.9
CU
0.9
CU
1
CU
placement area
solder land plus solder paste
solder land
solder resist, 0.0625 around copper
solder paste deposit, - 0.02 around copper,
stencil thickness 0.1
clearance, 0.125 around occupied area
occupied area
Dimensions in mm
sot1161-1_fr
Figure 44. PCB footprint for SOT1161-1 (XQFN16); reflow soldering
PCAL6408A
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Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Footprint information for reflow soldering of X2QFN16 package
SOT1896-1
1.81
0.37
pin A1
0.3
0.32
0.425
0.4
0.25
0.37 0.3
0.25 0.32
0.425
1.81
0.08
0.4
0.15
0.15
occupied area
solder resist
solder lands
solder paste
0.08
Dimensions in mm
Issue date
16-08-12
16-09-06
sot1896-1_fr
Figure 45. PCB footprint for SOT1896-1 (X2QFN16); reflow soldering
PCAL6408A
Product data sheet
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Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
19 Abbreviations
Table 29. Abbreviations
Acronym
Description
ESD
ElectroStatic Discharge
FET
Field-Effect Transistor
GPIO
General-Purpose Input/Output
2
I C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
LED
Light-Emitting Diode
LSB
Least Significant Bit
MSB
Most Significant Bit
PCB
Printed-Circuit Board
POR
Power-On Reset
SMBus
System Management Bus
PCAL6408A
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Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
20 Revision history
Table 30. Revision history
Document ID
Release date
Description
PCAL6408A v.3.3
14 October 2024
• Updated Figure 37 and Figure 40
• Updated data sheet look and feel to comply with NXP brand
identity guidelines
• Updated the terms "master/slave" with "controller/target"
throughout to align with NXPs inclusive language policy
PCAL6408A v.3.2
19 April 2017
• Removed “PCAL6408AEX1/X2QFN16” from Figure 5 “Pin
configuration for 1.6 mm x 1.6 mm
XFBGA16”
• Added Figure 6 “Pin configuration for 1.6 mm x 1.6 mm
X2QFN16 EX1 land grid array”
• Table 1 “Ordering information”, PCAL6408AEX1 topside mark
changed from “18” to “18X”;
added Table note 2 indicating topside marking work week;
added “land grid array” to
description
• Table 3 “Pin description”, XFBGA16, X2QFN16: Corrected pin
assignment from “D5” to “D4”
PCAL6408A v.3.1
2 November 2016
• Added PCAL6408AEX1
PCAL6408A v.3
18 September 2013
• Section 2 “Features and benefits”, 17th bullet item: added
“XFBGA16”
• Table 1 “Ordering information”: added Type number PCAL6408
AEX
• Table 2 “Ordering options”: added Type number PCAL6408AEX
• Added (new) Figure 5 “Pin configuration for 1.6 mm 1.6 mm
XFBGA16”
• Added (new) Figure 6 “Ball mapping for 1.6 mm 1.6 mm
XFBGA16”
• Table 3 “Pin description”: added column “XFBGA16”
• Table 6 “Command byte”, register “Output port configuration”:
– Pointer register bits corrected from “0100 0111” to “0100
1111” (correction to documentation,
no functional change to device)
– Command byte corrected from “47h” to “4Fh” (correction to
documentation, no functional
change to device)
• Section 7.4.11 “Output port configuration register (4Fh)”:
– register number corrected from “47h” to “4Fh” in Section title
(correction to documentation,
no functional change to device)
– first paragraph, third sentence: register number corrected
from “(47h)” to “(4Fh)” (correction
to documentation, no functional change to device)
– register number corrected from “47h” to “4Fh” in title of Table
18 (correction to
documentation, no functional change to device)
• Added (new) Figure 39 “Package outline SOT1354-1
(XFBGA16)”
Product data sheet
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Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Table 30. Revision history...continued
Document ID
Release date
Description
PCAL6408A v.2
6 December 2012
Product data sheet
PCAL6408A v.1
6 September 2012
Product data sheet
PCAL6408A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 14 October 2024
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Legal information
Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL https://www.nxp.com.
Definitions
Draft — A draft status on a document indicates that the content is still
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in modifications or additions. NXP Semiconductors does not give any
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liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
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Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
towards customer for the products described herein shall be limited in
accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
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make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCAL6408A
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their
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whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
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associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at https://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 14 October 2024
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use in non-automotive qualified products — Unless
this document expressly states that this specific NXP Semiconductors
product is automotive qualified, the product is not suitable for automotive
use. It is neither qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts no liability for
inclusion and/or use of non-automotive qualified products in automotive
equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warranty
of the product for such automotive applications, use and specifications, and
(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
HTML publications — An HTML version, if available, of this document is
provided as a courtesy. Definitive information is contained in the applicable
document in PDF format. If there is a discrepancy between the HTML
document and the PDF document, the PDF document has priority.
Security — Customer understands that all NXP products may be subject to
unidentified vulnerabilities or may support established security standards or
specifications with known limitations. Customer is responsible for the design
and operation of its applications and products throughout their lifecycles
to reduce the effect of these vulnerabilities on customer’s applications
and products. Customer’s responsibility also extends to other open and/or
proprietary technologies supported by NXP products for use in customer’s
applications. NXP accepts no liability for any vulnerability. Customer should
regularly check security updates from NXP and follow up appropriately.
Customer shall select products with security features that best meet rules,
regulations, and standards of the intended application and make the
ultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may be
provided by NXP.
NXP has a Product Security Incident Response Team (PSIRT) (reachable
at PSIRT@nxp.com) that manages the investigation, reporting, and solution
release to security vulnerabilities of NXP products.
NXP B.V. — NXP B.V. is not an operating company and it does not distribute
or sell products.
Trademarks
Notice: All referenced brands, product names, service names, and
trademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.
I2C-bus — logo is a trademark of NXP B.V.
Translations — A non-English (translated) version of a document, including
the legal information in that document, is for reference only. The English
version shall prevail in case of any discrepancy between the translated and
English versions.
PCAL6408A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 14 October 2024
© 2024 NXP B.V. All rights reserved.
Document feedback
56 / 59
PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.
Tab. 11.
Tab. 12.
Tab. 13.
Tab. 14.
Tab. 15.
Ordering information ..........................................4
Ordering options ................................................4
Pin description ...................................................7
Voltage translation .............................................9
Interface definition ........................................... 10
Command byte ................................................10
Input port register (address 00h) .....................11
Output port register (address 01h) .................. 11
Polarity inversion register (address 02h) ......... 11
Configuration register (address 03h) ............... 12
Current control register (address 40h) .............12
Current control register (address 41h) .............12
Input latch register (address 42h) ................... 13
Pull-up/pull-down enable register (address
43h) ................................................................. 13
Pull-up/pull-down selection register
(address 44h) .................................................. 13
PCAL6408A
Product data sheet
Tab. 16.
Tab. 17.
Tab. 18.
Tab. 19.
Tab. 20.
Tab. 21.
Tab. 22.
Tab. 23.
Tab. 24.
Tab. 25.
Tab. 26.
Tab. 27.
Tab. 28.
Tab. 29.
Tab. 30.
Interrupt mask register (address 45h) ............. 14
Interrupt status register (address 46h) ............ 14
Output port configuration register (address
4Fh) ................................................................. 14
Recommended supply sequencing and
ramp rates ....................................................... 23
Limiting values ................................................ 25
Operating conditions ....................................... 26
Thermal characteristics ................................... 27
Static characteristics ....................................... 28
I2C-bus interface timing requirements .............35
Reset timing requirements .............................. 35
Switching characteristics ................................. 36
SnPb eutectic process (from J-STD-020D) ..... 47
Lead-free process (from J-STD-020D) ............ 47
Abbreviations ...................................................52
Revision history ...............................................53
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 14 October 2024
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Fig. 14.
Fig. 15.
Fig. 16.
Fig. 17.
Fig. 18.
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.
Fig. 24.
Fig. 25.
Block diagram (positive logic) ........................... 5
Pin configuration for TSSOP16 ......................... 6
Pin configuration for HVQFN16 .........................6
Pin configuration for XQFN16 ........................... 6
Pin configuration for 1.6 mm × 1.6 mm
XFBGA16 .......................................................... 7
Pin configuration for 1.6 mm × 1.6 mm
X2QFN16 EX1 land grid array .......................... 7
Ball mapping for 1.6 mm × 1.6 mm
XFBGA16/X2QFN16 ......................................... 7
Device address ............................................... 10
Pointer register bits ......................................... 10
Simplified schematic of the I/Os (P0 to P7) ..... 15
Write to Output port register ............................17
Write to Configuration or Polarity inversion
registers ...........................................................17
Read from register .......................................... 18
Read Input port register (non-latched) .............18
Read Input port register (latch enabled) .......... 19
Typical application ........................................... 20
High-value resistor in parallel with the LED ..... 21
Device supplied by a lower voltage .................21
Simplified output stage ....................................22
VDD is lowered below 0.2 V or 0 V and
then ramped up to VDD .................................. 22
VDD is lowered below the POR threshold,
then ramped back up to VDD ......................... 23
Glitch width and glitch height .......................... 23
Power-on reset voltage (VPOR) ......................24
Supply current versus ambient temperature ....30
Standby supply current versus ambient
temperature ..................................................... 31
PCAL6408A
Product data sheet
Fig. 26.
Fig. 27.
Fig. 28.
Fig. 29.
Fig. 30.
Fig. 31.
Fig. 32.
Fig. 33.
Fig. 34.
Fig. 35.
Fig. 36.
Fig. 37.
Fig. 38.
Fig. 39.
Fig. 40.
Fig. 41.
Fig. 42.
Fig. 43.
Fig. 44.
Fig. 45.
Supply current versus supply voltage ..............31
Supply current versus number of I/O held
LOW ................................................................ 31
I/O sink current versus LOW-level output
voltage with CCX.X = 11b ............................... 32
I/O source current versus HIGH-level
output voltage with CCX.X = 11b .................... 33
LOW-level output voltage versus
temperature ..................................................... 34
I/O high voltage versus temperature ............... 34
I2C-bus interface load circuit and voltage
waveforms ....................................................... 37
Interrupt load circuit and voltage
waveforms ....................................................... 38
P port load circuit and voltage waveforms ....... 39
Reset load circuits and voltage waveforms ..... 40
Package outline SOT403-1 (TSSOP16) ..........41
Package outline SOT758-1 (HVQFN16) ......... 42
Package outline SOT1161-1 (XQFN16) .......... 43
Package outline SOT1354-1 (XFBGA16) ........ 44
Package outline SOT1896-1 (X2QFN16) ........ 45
Temperature profiles for large and small
components ..................................................... 47
PCB footprint for SOT758-1 (HVQFN16);
reflow soldering ............................................... 48
PCB footprint for SOT403-1 (TSSOP16);
reflow soldering ............................................... 49
PCB footprint for SOT1161-1 (XQFN16);
reflow soldering ............................................... 50
PCB footprint for SOT1896-1 (X2QFN16);
reflow soldering ............................................... 51
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 14 October 2024
© 2024 NXP B.V. All rights reserved.
Document feedback
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PCAL6408A
NXP Semiconductors
2
Low-voltage translating, 8-bit I C-bus/SMBus I/O expander with interrupt output, reset, and
configuration registers
Contents
1
2
2.1
3
3.1
4
5
5.1
5.2
6
7
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
7.4.11
7.5
7.6
7.7
7.8
8
8.1
8.2
9
9.1
9.2
9.3
9.4
10
11
12
13
13.1
14
15
16
17
17.1
17.2
17.3
17.4
18
General description ......................................... 1
Features and benefits ..................................... 3
Agile I/O features ...............................................3
Ordering information .......................................4
Ordering options ................................................ 4
Block diagram ..................................................5
Pinning information .........................................6
Pinning ............................................................... 6
Pin description ................................................... 7
Voltage translation ...........................................9
Functional description .................................. 10
Device address ................................................10
Interface definition ........................................... 10
Pointer register and command byte .................10
Register descriptions ....................................... 11
Input port register (00h) ...................................11
Output port register (01h) ................................ 11
Polarity inversion register (02h) ....................... 11
Configuration register (03h) ............................. 12
Output drive strength registers (40h, 41h) ....... 12
Input latch register (42h) ................................. 12
Pull-up/pull-down enable register (43h) ........... 13
Pull-up/pull-down selection register (44h) ........ 13
Interrupt mask register (45h) ........................... 13
Interrupt status register (46h) .......................... 14
Output port configuration register (4Fh) ...........14
I/O port .............................................................14
Power-on reset ................................................ 15
Reset input (RESET) ....................................... 15
Interrupt output (INT) ....................................... 15
Bus transactions ............................................17
Write commands ..............................................17
Read commands ............................................. 17
Application design-in information ................20
Minimizing IDD when I/Os control LEDs .......... 20
Output drive strength control ........................... 21
Power-on reset requirements .......................... 22
Device current consumption with internal
pull-up and pull-down resistors ........................24
Limiting values ...............................................25
Recommended operating conditions ...........26
Thermal characteristics ................................ 27
Static characteristics .....................................28
Typical characteristics ......................................30
Dynamic characteristics ............................... 35
Parameter measurement information .......... 37
Package outline ............................................. 41
Soldering of SMD packages ......................... 46
Introduction to soldering .................................. 46
Wave and reflow soldering .............................. 46
Wave soldering ................................................ 46
Reflow soldering .............................................. 46
Soldering: PCB footprints .............................48
19
20
Abbreviations ................................................. 52
Revision history .............................................53
Legal information ...........................................55
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© 2024 NXP B.V.
For more information, please visit: https://www.nxp.com
All rights reserved.
Document feedback
Date of release: 14 October 2024
Document identifier: PCAL6408A
