PCE85133AUG
Universal 80 × 4 LCD driver for low multiplex rates
Rev. 2 — 22 July 2015
Product data sheet
1. General description
The PCE85133AUG is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 80 segments. The
PCE85133AUG is compatible with most microcontrollers and communicates via the
two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM
with auto-incremental addressing and by display memory switching (static and duplex
drive modes).
For a selection of NXP LCD segment drivers, see Table 23 on page 42.
2. Features and benefits
1.
Single-chip LCD controller and driver
Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
Selectable display bias configuration: static, 1⁄2, or 1⁄3
Frame frequency: 150 Hz
Internal LCD bias generation with voltage-follower buffers
80 segment drives:
Up to 40 7-segment alphanumeric characters
Up to 20 14-segment alphanumeric characters
Any graphics of up to 320 segments/elements
80 4 RAM for display data storage
Display memory bank switching in static and duplex drive modes
Independent supplies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide LCD supply range:
From 2.5 V for low-threshold LCDs
Up to 5.5 V for high-threshold twisted nematic LCDs
Low power consumption
400 kHz I2C-bus interface
No external components needed
Compatible with Chip-On-Glass (COG) technology
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 18.
PCE85133AUG
NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
3. Ordering information
Table 1.
Ordering information
Type number
Package
PCE85133AUG
Name
Description
Version
bare die
110 bumps
PCE85133AUG
3.1 Ordering options
Table 2.
Ordering options
Product type number
Orderable part number Sales item
(12NC)
Delivery form
IC
revision
PCE85133AUG/DA
PCE85133AUG/DAZ
chip with hard bumps in tray[1]
1
[1]
935306039033
Bump hardness see Table 20.
4. Block diagram
S0 to S79
BP0 BP1 BP2 BP3
80
VLCD
BACKPLANE
OUTPUTS
LCD
VOLTAGE
SELECTOR
DISPLAY SEGMENT OUTPUTS
DISPLAY REGISTER
OUTPUT BANK SELECT
AND BLINK CONTROL
DISPLAY
CONTROL
LCD BIAS
GENERATOR
VSS
PCE85133
CLK
CLOCK SELECT
AND TIMING
OSC
OSCILLATOR
SCL
INPUT
FILTERS
SDA
DISPLAY
RAM
BLINKER
TIMEBASE
COMMAND
DECODE
WRITE DATA
CONTROL
DATA POINTER AND
AUTO INCREMENT
I2C-BUS
CONTROLLER
SA0
SDAACK
T1 to T5
VDD
aaa-015841
Fig 1.
Block diagram of PCE85133AUG
PCE85133AUG
Product data sheet
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Rev. 2 — 22 July 2015
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PCE85133AUG
NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
5. Pinning information
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6
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5.1 Pinning
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Viewed from active side. For mechanical details, see Figure 27.
Fig 2.
Pin configuration for PCE85133AUG
PCE85133AUG
Product data sheet
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Rev. 2 — 22 July 2015
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PCE85133AUG
NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
5.2 Pin description
Table 3.
Pin description overview
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
Symbol
Pin
Description
SDAACK
1 to 3
I2C-bus acknowledge output
SDA
4 to 6
I2C-bus serial data input
SCL
7 to 9
I2C-bus serial clock input
CLK
10
clock input and output
VDD
11 to 13
supply voltage
T1
14
test pin; must be left open
OSC
15
oscillator select
•
•
16
test pin; must be tied to VDD
T3 to T5
17 to 19
test pins; must be tied to VSS
SA0
20
I2C-bus slave address input
connect to VDD for logic 1
connect to VSS for logic 0
VSS[1]
21 to 23
ground supply voltage
VLCD
24 to 26
LCD supply voltage
BP2
27
LCD backplane output
BP0
28
BP3
109
BP1
110
S0 to S79
D1 to
Product data sheet
connect to VSS for internal clock
T2
•
•
PCE85133AUG
connect to VDD for external clock
D9[2]
29 to 108
LCD segment output
-
dummy pins
[1]
The substrate (rear side of the die) is at VSS potential and should be electrically isolated.
[2]
The dummy pads are connected to VSS but not tested.
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PCE85133AUG
NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
6. Functional description
6.1 Commands of PCE85133AUG
The command decoder identifies command bytes that arrive on the I2C-bus. The
commands available to the PCE85133AUG are defined in Table 4.
Table 4.
Definition of commands
Command
Operation code
Bit
7
6
5
4
3
2
1
mode-set
1
1
0
0
E
B
M[1:0]
initialize-RAM
1
1
1
0
0
0
0
load-datapointer
0
P[6:0]
bank-select
1
1
Table 5.
Bit
Reference
1
7 to 4
-
1100
3
E
[1]
0
Table 6
1
1
0
I
O
Table 8
Mode-set command bit description
Value
Description
fixed value
display status[1]
0
disabled (blank)[2]
1
enabled
LCD bias configuration[3]
B
1 to 0
Table 5
Table 7
Symbol
2
0
0
1⁄
3
bias
1
1⁄
2
bias
M[1:0]
LCD drive mode selection
01
static; 1 backplane (BP0)
10
1:2 multiplex; 2 backplanes (BP0 and BP1)
11
1:3 multiplex; 3 backplanes (BP0 to BP2)
00
1:4 multiplex; 4 backplanes (BP0 to BP3)
The possibility to disable the display allows implementation of blinking under external control.
[2]
The display is disabled by setting all backplane and segment outputs to VLCD.
[3]
Not applicable for static drive mode.
Table 6.
Initialize-RAM command bit description
See Section 6.3.1.
PCE85133AUG
Product data sheet
Bit
Symbol
Value
Description
7 to 0
-
11100000
initializing the RAM access
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PCE85133AUG
NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
Table 7.
Load-data-pointer command bit description
See Section 6.3.1.
Bit
Symbol
Value
Description
7
6 to 0
-
0
fixed value
P[6:0]
0000000 to
1001111
data pointer
7-bit binary value of 0 to 79, transferred to the
data pointer to define one of 80 display RAM
addresses
Table 8.
Bank-select command bit description[1]
See Section 6.3.4 and Section 6.3.5.
Bit
Symbol
Value
Description
Static
7 to 2
-
1
I
0
[1]
111110
1:2 multiplex
fixed value
input bank selection: storage of arriving
display data
0
RAM row 0
RAM rows 0 and 1
1
RAM row 2
RAM rows 2 and 3
O
output bank selection: retrieval of LCD display
data
0
RAM row 0
RAM rows 0 and 1
1
RAM row 2
RAM rows 2 and 3
The bank-select command has no effect in 1:3 or 1:4 multiplex drive modes.
6.2 Clock and frame frequency
6.2.1 Oscillator
The internal logic and the LCD drive signals of the PCE85133AUG are timed by a
frequency fclk which either is derived from the built-in oscillator frequency fosc:
f osc
f clk = -------64
(1)
or equals an external clock frequency fclk(ext):
(2)
f clk = f clk ext
6.2.1.1
Internal clock
The internal oscillator is enabled by connecting pin OSC to VSS.
6.2.1.2
External clock
Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the
external clock input.
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
PCE85133AUG
Product data sheet
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Rev. 2 — 22 July 2015
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PCE85133AUG
NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
6.2.2 Frame frequency
The clock frequency fclk determines the LCD frame frequency ffr and is calculated as
follows:
f clk
f fr = -------24
(3)
6.3 Display RAM
The display RAM is a static 80 4 RAM which stores LCD data.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD segments/elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bit map, Figure 3, shows rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and columns 0 to 79 which correspond with the segment
outputs S0 to S79. In multiplexed LCD applications the segment data of the 1st, 2nd, 3rd
and 4th row of the display RAM are time-multiplexed with BP0, BP1, BP2, and BP3
respectively.
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The display RAM bitmap shows the direct relationship between the display RAM addresses and
the segment outputs and between the bits in a RAM word and the backplane outputs.
Fig 3.
PCE85133AUG
Product data sheet
Display RAM bitmap
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Rev. 2 — 22 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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Fig 4.
Relationships between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus
PCE85133AUG
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Universal 80 × 4 LCD driver for low multiplex rates
Rev. 2 — 22 July 2015
All information provided in this document is subject to legal disclaimers.
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NXP Semiconductors
PCE85133AUG
Product data sheet
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PCE85133AUG
NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
When display data is transmitted to the PCE85133AUG, the received display bytes are
stored in the display RAM in accordance with the selected LCD drive mode. The data is
stored as it arrives and depending on the current multiplex drive mode the bits are stored
singularly, in pairs, triples or quadruples. To illustrate the filling order, an example of a
7-segment display showing all drive modes is given in Figure 4; the RAM filling
organization depicted applies equally to other LCD types.
The following applies to Figure 4:
• In static drive mode, the eight transmitted data bits are placed into row 0 as 1 byte.
• In 1:2 multiplex drive mode, the eight transmitted data bits are placed in pairs into
row 0 and 1 as two successive 4-bit RAM words.
• In 1:3 multiplex drive mode, the 8 bits are placed in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address, but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see Section 6.3.2).
• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words.
6.3.1 Writing to RAM
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM.
The sequence always commences with the initialize-RAM command (see Table 6).
Following this command, the data pointer has to be set to the desired RAM address using
the load-data-pointer command (see Table 7). After this, an arriving data byte is stored at
the display RAM address indicated by the data pointer. The RAM writing procedure is
illustrated in Figure 5 and the filling order of the RAM is shown in Figure 4.
PCE85133AUG
Product data sheet
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Rev. 2 — 22 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
9 of 50
PCE85133AUG
NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
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Fig 5.
RAM writing procedure
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
•
•
•
•
In static drive mode by eight.
In 1:2 multiplex drive mode by four.
In 1:3 multiplex drive mode by three.
In 1:4 multiplex drive mode by two.
If an I2C-bus data access terminates early, then the state of the data pointer is unknown.
So, the data pointer must be rewritten before further RAM accesses.
6.3.2 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 9 (see Figure 4 as well).
Table 9.
Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any segments/elements on the
display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
0
a7
a4
a1
b7
b4
b1
c7
c4
c1
d7
:
1
a6
a3
a0
b6
b3
b0
c6
c3
c0
d6
:
2
a5
a2
-
b5
b2
-
c5
c2
-
d5
:
3
-
-
-
-
-
-
-
-
-
-
:
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 10.
PCE85133AUG
Product data sheet
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PCE85133AUG
NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
Table 10. Entire RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to segments/elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
0
a7
a4
a1/b7 b4
b1/c7 c4
1
a6
a3
a0/b6 b3
2
a5
a2
b5
b2
3
-
-
-
-
3
4
5
6
7
8
9
:
c1/d7 d4
d1/e7 e4
:
b0/c6 c3
c0/d6 d3
d0/e6 e3
:
c5
c2
d5
d2
e5
e2
:
-
-
-
-
-
-
:
In the case described in Table 10 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8 etc. have to be connected to segments/elements on the display. This can be
achieved by a combination of writing and rewriting the RAM like follows:
• In the first write to the RAM, bits a7 to a0 are written.
• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6.
• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6.
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some segments/elements remain unused or can be used, but it has to be considered in
the module layout process as well as in the driver software design.
6.3.3 Writing over the RAM address boundary
In all multiplex drive modes, depending on the setting of the data pointer, it is possible to
fill the RAM over the RAM address boundary. In this case, the additional bits are
discarded.
6.3.4 Output bank selector
The output bank selector (see Table 8) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
selected LCD drive mode in operation and on the instant in the multiplex sequence.
• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the contents of row 1, 2, and then 3
• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
• In 1:2 multiplex mode, rows 0 and 1 are selected
• In static mode, row 0 is selected
The PCE85133AUG includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. In the static drive mode, the bank-select command may request the contents
of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex
mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives
the provision for preparing display information in an alternative bank and to be able to
switch to it once it is assembled.
PCE85133AUG
Product data sheet
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Rev. 2 — 22 July 2015
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PCE85133AUG
NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
6.3.5 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode
or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see
Table 8). The input bank selector functions independently to the output bank selector.
6.4 Initialization
At power-on, the status of the I2C-bus and the registers of the PCE85133AUG is
undefined. Therefore the PCE85133AUG should be initialized as quickly as possible after
power-on to ensure a proper bus communication and to avoid display artifacts. The
following instructions should be accomplished for initialization:
• I2C-bus (see Section 7) initialization
– generating a START condition
– sending 0h and ignoring the acknowledge
– generating a STOP condition
• Mode-set command (see Table 5), setting
– bit E = 0
– bit B to the required LCD bias configuration
– bits M[1:0] to the required LCD drive mode
• Initialize-RAM command (see Table 6)
• Load-data-pointer command (see Table 7), setting
– bits P[6:0] to 0h (or any other required address)
• Bank-select command (see Table 8), setting
– bit I to 0
– bit O to 0
• writing meaningful information (for example, a logo) into the display RAM (see
Section 6.3 on page 7)
After the initialization, the display can be switched on by setting bit E = 1 with the
mode-set command.
6.5 Possible display configurations
The display configurations possible with the PCE85133AUG depend on the required
number of active backplane outputs. A selection of display configurations is given in
Table 11.
All of the display configurations given in Table 11 can be implemented in a typical system
as shown in Figure 7.
PCE85133AUG
Product data sheet
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Rev. 2 — 22 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCE85133AUG
NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
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Fig 6.
Example of displays suitable for PCE85133AUG
Table 11.
Selection of possible display configurations
Number of
Backplanes
Icons
Digits/Characters
7-segment[1]
14-segment[2]
Dot matrix:
segments/
elements
4
320
40
20
320 (4 80)
3
240
30
15
240 (3 80)
2
160
20
10
160 (2 80)
1
80
10
5
80 (1 80)
[1]
7 segment display has 8 segments/elements including the decimal point.
[2]
14 segment display has 16 segments/elements including decimal point and accent dot.
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Fig 7.
PCE85133AUG
Product data sheet
Typical system configuration
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PCE85133AUG
NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
The host microcontroller maintains the 2-line I2C-bus communication channel with the
PCE85133AUG. The internal oscillator is enabled by connecting pin OSC to pin VSS. The
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
The only other connections required to complete the system are the power supplies (VDD,
VSS, and VLCD) and the LCD panel chosen for the application.
6.6 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
impedances connected between pins VLCD and VSS. The center impedance is bypassed
by switch if the 1⁄2 bias voltage level for the 1:2 multiplex drive mode configuration is
selected.
6.7 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
VLCD and the resulting discrimination ratios (D) are given in Table 12.
Discrimination is a term which is defined as the ratio of the on and off RMS voltage across
a segment. It can be thought of as a measurement of contrast.
Table 12.
Biasing characteristics
LCD drive
mode
Number of:
LCD bias
Backplanes Levels configuration
V off RMS
------------------------V LCD
V on RMS
-----------------------V LCD
static
V on RMS
D = -----------------------V off RMS
1
2
static
0
1
1:2 multiplex 2
3
1⁄
2
0.354
0.791
2.236
1:2 multiplex 2
4
1⁄
3
0.333
0.745
2.236
4
1⁄
3
0.333
0.638
1.915
4
1⁄
3
0.333
0.577
1.732
1:3 multiplex 3
1:4 multiplex 4
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode, a suitable choice is VLCD > 3Vth(off).
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
1
Bias is calculated by ------------- , where the values for a are
1+a
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 4:
V on RMS =
V LCD
a 2 + 2a + n
-----------------------------2
n 1 + a
(4)
where the values for n are
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Universal 80 × 4 LCD driver for low multiplex rates
n = 1 for static drive mode
n = 2 for 1:2 multiplex drive mode
n = 3 for 1:3 multiplex drive mode
n = 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 5:
V off RMS =
V LCD
a 2 – 2a + n
-----------------------------2
n 1 + a
(5)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 6:
V on RMS
D = ----------------------- =
V off RMS
2
a + 2a + n
--------------------------2
a – 2a + n
(6)
Using Equation 6, the discrimination for an LCD drive mode of 1:3 multiplex with
1⁄
2
bias is
1⁄
2
21
bias is ---------- = 1.528 .
3
3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
• 1:3 multiplex (1⁄2 bias): V LCD =
6 V off RMS = 2.449V off RMS
4 3
- = 2.309V off RMS
• 1:4 multiplex (1⁄2 bias): V LCD = --------------------3
These compare with V LCD = 3V off RMS when 1⁄3 bias is used.
VLCD is sometimes referred as the LCD operating voltage.
6.7.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel is switched on or off, determine the transmissibility of the
pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 8. For a good contrast performance, the following rules should be followed:
V on RMS V th on
(7)
V off RMS V th off
(8)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a, n (see Equation 4 to Equation 6) and the VLCD voltage.
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Universal 80 × 4 LCD driver for low multiplex rates
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
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PCE85133AUG
Product data sheet
Electro-optical characteristic: relative transmission curve of the liquid
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Universal 80 × 4 LCD driver for low multiplex rates
6.8 LCD drive mode waveforms
6.8.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
Backplane and segment drive waveforms for this mode are shown in Figure 9.
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Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = VLCD.
Vstate2(t) = V(Sn + 1)(t) VBP0(t).
Voff(RMS) = 0 V.
Fig 9.
PCE85133AUG
Product data sheet
Static drive mode waveforms
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Universal 80 × 4 LCD driver for low multiplex rates
6.8.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCE85133AUG allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 10
and Figure 11.
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Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.791VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.354VLCD.
Fig 10. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
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Product data sheet
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NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
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Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.745VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 11. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
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Product data sheet
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Universal 80 × 4 LCD driver for low multiplex rates
6.8.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as
shown in Figure 12.
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Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.638VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 12. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
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Universal 80 × 4 LCD driver for low multiplex rates
6.8.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as
shown in Figure 13.
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Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.577VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 13. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias
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Universal 80 × 4 LCD driver for low multiplex rates
6.9 Backplane outputs
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated in accordance with the selected LCD drive mode.
• In the 1:4 multiplex drive mode, BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required, the unused outputs can be left
open-circuit.
• In 1:3 multiplex drive mode: BP3 carries the same signal as BP1; therefore, these two
adjacent outputs can be tied together to give enhanced drive capabilities.
• In 1:2 multiplex drive mode: BP0 and BP2, respectively, BP1 and BP3 carry the same
signals and can also be paired to increase the drive capabilities.
• In static drive mode: The same signal is carried by all four backplane outputs; and
they can be connected in parallel for very high drive requirements.
6.10 Segment outputs
The LCD drive section includes 80 segment outputs (S0 to S79) which must be connected
directly to the LCD. The segment output signals are generated in accordance with the
multiplexed backplane signals and with data residing in the display register. When less
than 80 segment outputs are required, the unused segment outputs must be left
open-circuit.
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Universal 80 × 4 LCD driver for low multiplex rates
7. Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
By connecting pin SDAACK to pin SDA on the PCE85133AUG, the SDA line becomes
fully I2C-bus compatible. In COG applications where the track resistance from the
SDAACK pin to the system SDA line can be significant, possibly a voltage divider is
generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As
a consequence, it may be possible that the acknowledge generated by the
PCE85133AUG cannot be interpreted as logic 0 by the master. In COG applications
where the acknowledge cycle is required, it is therefore necessary to minimize the track
resistance from the SDAACK pin to the system SDA line to guarantee a valid LOW level.
By separating the acknowledge output from the serial data line (having the SDAACK open
circuit), design efforts to generate a valid acknowledge level can be avoided. However, in
that case the I2C-bus master has to be set up in such a way that it ignores the
acknowledge cycle.2
The following definition assumes that SDA and SDAACK are connected and refers to the
pair as SDA.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as a control signal (see Figure 14).
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Fig 14. Bit transfer
7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START
condition (S).
A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP
condition (P).
2.
For further information, consider the NXP application note: Ref. 1 “AN10170”.
PCE85133AUG
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Universal 80 × 4 LCD driver for low multiplex rates
The START and STOP conditions are shown in Figure 15.
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Fig 15. Definition of START and STOP conditions
7.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 16.
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Fig 16. System configuration
7.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 17.
PCE85133AUG
Product data sheet
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PCE85133AUG
NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
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Fig 17. Acknowledgement on the I2C-bus
7.5 I2C-bus controller
The PCE85133AUG acts as an I2C-bus slave receiver. It does not initiate I2C-bus
transfers or transmit data to an I2C-bus master receiver. The only data output from the
PCE85133AUG are the acknowledge signals from the selected devices. Device selection
depends on the I2C-bus slave address, on the transferred command data, and on the
hardware subaddress.
7.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
7.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the
PCE85133AUG. The entire I2C-bus slave address byte is shown in Table 13.
Table 13.
I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
MSB
0
0
LSB
1
1
1
0
0
SA0
R/W
The PCE85133AUG is a write-only device and will not respond to a read access, therefore
bit 0 should always be logic 0. Bit 1 of the slave address byte that a PCE85133AUG will
respond to, is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).
The I2C-bus protocol is shown in Figure 18. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by the PCE85133AUG slave
addresses.
PCE85133AUG
Product data sheet
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NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
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Fig 18. I2C-bus protocol
After acknowledgement, the control byte is sent, defining if the next byte is a RAM or
command information. The control byte also defines if the next byte is a control byte or
further RAM or command data (see Figure 19 and Table 14). In this way, it is possible to
configure the device and then fill the display RAM with little overhead.
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Fig 19. Control byte format
Table 14.
Control byte description
Bit
Symbol
7
CO
6
Value
continue bit
0
last control byte
1
control bytes continue
RS
register selection
0
1
5 to 0
-
Description
command register
data register
not relevant
The command bytes and control bytes are also acknowledged by the PCE85133AUG.
The display bytes are stored in the display RAM at the address specified by the data
pointer and the subaddress counter. Both data pointer and subaddress counter are
automatically updated. After the last display byte, the I2C-bus master issues a STOP
condition (P). Alternatively a START may be asserted to RESTART an I2C-bus access.
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Universal 80 × 4 LCD driver for low multiplex rates
8. Internal circuitry
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Fig 20. Device protection diagram
9. Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
CAUTION
Semiconductors are light sensitive. Exposure to light sources can cause the IC to
malfunction. The IC must be protected against light. The protection must be applied to all
sides of the IC.
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Universal 80 × 4 LCD driver for low multiplex rates
10. Limiting values
Table 15. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Conditions
Min
Max
VDD
supply voltage
VLCD
LCD supply voltage
0.5
+6.5
V
Vi(n)
voltage on any input
VDD related inputs
0.5
+6.5
V
Vo(n)
voltage on any output
VLCD related outputs
0.5
+6.5
V
II
input current
10
+10
mA
IO
output current
10
+10
mA
IDD
supply current
50
+50
mA
ISS
ground supply current
50
+50
mA
IDD(LCD)
LCD supply current
50
+50
mA
0.5
+6.5
Unit
V
Ptot
total power dissipation
-
400
mW
P/out
power dissipation per
output
-
100
mW
VESD
electrostatic discharge
voltage
[2]
-
4000
V
Ilu
latch-up current
[3]
-
100
mA
Tstg
storage temperature
[4]
65
+150
C
Tamb
ambient temperature
40
+85
C
[1]
HBM
operating device
Stresses above these values listed may cause permanent damage to the device.
[2]
Pass level; Human Body Model (HBM) according to Ref. 7 “JESD22-A114”.
[3]
Pass level; latch-up testing, according to Ref. 8 “JESD78” at maximum ambient temperature (Tamb(max)).
[4]
According to the store and transport requirements (see Ref. 11 “UM10569”) the devices have to be stored at a temperature of +8 C to
+45 C and a humidity of 25 % to 75 %.
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Universal 80 × 4 LCD driver for low multiplex rates
11. Static characteristics
Table 16. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
1.8
-
5.5
V
VLCD
LCD supply voltage
2.5
-
5.5
V
-
3
6
A
-
22
45
A
IDD
supply current
fclk(ext) = 1536 Hz;
VDD = 5.5 V; see Figure 21
[1]
IDD(LCD)
LCD supply current
fclk(ext) = 1536 Hz;
VDD = 5.5 V;VLCD = 8.0 V;
see Figure 21
[1]
Logic
VI
input voltage
VSS 0.5
-
VDD + 0.5
V
VIH
HIGH-level input voltage
on pins CLK, OSC, T1 to T5,
SA0
0.7VDD
-
VDD
V
VIL
LOW-level input voltage
on pins CLK, OSC, T1 to T5,
SA0
VSS
-
0.3VDD
V
VOH
HIGH-level output voltage
0.8VDD
-
-
V
VOL
LOW-level output voltage
-
-
0.2VDD
V
IOH
HIGH-level output current
output source current;
on pin CLK;
VOH = 4.6 V; VDD = 5 V
1
-
-
mA
IOL
LOW-level output current
output sink current;
on pin CLK, T1;
VOL = 0.4 V; VDD = 5 V
1
-
-
mA
IL
leakage current
on pins OSC, CLK, SCL,
SDA, T2 to T5, SA0;
VI = VDD or VSS
1
-
+1
A
CI
input capacitance
-
-
7
pF
[3]
I2C-bus[2]
Input on pins SDA and SCL
VI
input voltage
VSS 0.5
-
5.5
V
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
VIL
LOW-level input voltage
VSS
-
0.3VDD
V
-
-
7
pF
3
-
-
mA
CI
input capacitance
IOL(SDA)
LOW-level output current
on pin SDA
PCE85133AUG
Product data sheet
[3]
output sink current;
VOL = 0.4 V; VDD = 5 V
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
29 of 50
PCE85133AUG
NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
Table 16. Static characteristics …continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
on pins BP0 to BP3; Cbpl =
35 nF
100
-
+100
mV
on pins S0 to S79; Csgm = 5
nF
100
-
+100
mV
LCD outputs
VO
output voltage variation
output resistance
RO
VLCD = 5 V
on pins BP0 to BP3
[4]
-
1.5
10
k
on pins S0 to S79
[4]
-
6.0
13.5
k
[1]
LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[2]
The I2C-bus interface of PCE85133AUG is 5 V tolerant.
[3]
Not tested, design specification only.
[4]
Outputs measured individually and sequentially.
DDD
,''
$
,'' /&'
$
IFON H[W N+]
Conditions: VDD = 5.5 V; VLCD = 8 V; Tamb = 27 C; all RAM filled with 0.
(1) IDD(LCD).
(2) IDD.
Fig 21. Current consumption with respect to external clock frequency
PCE85133AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
30 of 50
PCE85133AUG
NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
12. Dynamic characteristics
Table 17. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2630
3600
4680
Hz
Clock
Internal: output pin CLK
[1]
fclk
clock frequency
ffr
frame frequency
-
150
-
Hz
ffr
frame frequency variation
110
150
195
Hz
External: input pin CLK
fclk(ext)
external clock frequency
800
-
7000
Hz
tclk(H)
HIGH-level clock time
90
-
-
s
tclk(L)
LOW-level clock time
90
-
-
s
-
-
30
s
Outputs: pins BP0 to BP3 and S0 to S79
tPD(drv)
I2C-bus:
driver propagation delay
VLCD = 5 V
timing[2]
Pin SCL
fSCL
SCL clock frequency
-
-
400
kHz
tHIGH
HIGH period of the SCL
clock
0.6
-
-
s
tLOW
LOW period of the SCL
clock
1.3
-
-
s
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
Pin SDA
Pins SCL and SDA
tBUF
bus free time between a
STOP and START
condition
1.3
-
-
s
tSU;STO
set-up time for STOP
condition
0.6
-
-
s
tHD;STA
hold time (repeated)
START condition
0.6
-
-
s
tSU;STA
set-up time for a repeated
START condition
0.6
-
-
s
tr
rise time of both SDA and
SCL signals
fSCL = 400 kHz
-
-
0.3
s
fSCL < 125 kHz
-
-
1.0
s
tf
fall time of both SDA and
SCL signals
-
-
0.3
s
Cb
capacitive load for each
bus line
-
-
400
pF
tw(spike)
spike pulse width
-
-
50
ns
on bus
[1]
Typical output duty cycle of 50 %.
[2]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD. For I2C-bus timings, see Figure 24.
PCE85133AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
31 of 50
PCE85133AUG
NXP Semiconductors
Universal 80 × 4 LCD driver for low multiplex rates
DDD
IIU
+]
7DPE &
(1) VDD = 5.5 V.
(2) VDD = 1.8 V.
Fig 22. Frame frequency with respect to temperature
I&/.
WFON +
WFON /
9''
&/.
9''
9''
6
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