PCF2123U/12HA/1,00

PCF2123 SPI Real time clock/calendar Rev. 6 — 15 July 2013 Product data sheet 1. General description The PCF2123 is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low power applications. Data is transferred serially via a Serial Peripheral Interface (SPI-bus) with a maximum data rate of 6.25 Mbit/s. An alarm and timer function is also available providing the possibility to generate a wake-up signal on an interrupt pin. An offset register allows fine tuning of the clock. 2. Features and benefits  Real time clock provides year, month, day, weekday, hours, minutes, and seconds based on a 32.768 kHz quartz crystal  Low backup current while running: typical 100 nA at VDD = 2.0 V and Tamb = 25 C  Resolution: seconds to years  Watchdog functionality  Freely programmable timer and alarm with interrupt capability  Clock operating voltage: 1.1 V to 5.5 V  3 line SPI-bus with separate, but combinable data input and output  Serial interface at VDD = 1.8 V to 5.5 V  1 second or 1 minute interrupt output  Integrated oscillator load capacitors for CL = 7 pF  Internal Power-On Reset (POR)  Open-drain interrupt and clock output pins  Programmable offset register for frequency adjustment 3. Applications       1. Time keeping application Battery powered devices Metering High duration timers Daily alarms Low standby power applications The definition of the abbreviations and acronyms used in this data sheet can be found in Section 22. PCF2123 NXP Semiconductors SPI Real time clock/calendar 4. Ordering information Table 1. Ordering information Type number Package Name Description Version PCF2123BS HVQFN16 plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3  3  0.85 mm SOT758-1 PCF2123TS TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 PCF2123U/10AA wire bond die 12 bonding pads PCF2123U/10 PCF2123U/12AA WLCSP12 wafer level chip size package; 12 bumps PCF2123U/12 PCF2123U/12HA WLCSP12 wafer level chip size package; 12 bumps PCF2123U/12 PCF2123U/5GA wire bond die 12 bonding pads PCF2123U/10 4.1 Ordering options Table 2. Ordering options Product type number Sales item (12NC) PCF2123BS/1 935286382512 PCF2123BS/1,512 1 tube, dry pack 935286382518 PCF2123BS/1,518 1 tape and reel, 13 inch, dry pack 935286384112 PCF2123TS/1,112 1 tube 935286384118 PCF2123TS/1,118 1 tape and reel, 13 inch PCF2123U/10AA/1 935287542005 PCF2123U/10AA/1,00 1 sawn 6 inch wafer on Film Frame Carrier (FFC) for 6 inch wafer PCF2123U/12AA/1 935290647005 PCF2123U/12AA/1,00 1 sawn 6 inch wafer on plastic Film Frame Carrier (FFC) for 8 inch wafer PCF2123U/12HA/1 935292966005 PCF2123U/12HA/1,00 1 sawn 6 inch wafer on plastic Film Frame Carrier (FFC) for 8 inch wafer PCF2123U/5GA/1 935295429015 PCF2123U/5GA/1,015 1 wafer, unsawn PCF2123TS/1 Orderable part number IC revision Delivery form 5. Marking Table 3. PCF2123 Product data sheet Marking codes Type number Marking code PCF2123BS 123 PCF2123TS PCF2123 PCF2123U/10AA PC2123-1 PCF2123U/12AA PC2123-1 PCF2123U/12HA PC2123-1 PCF2123U/5GA PC2123-1 All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 2 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 6. Block diagram OSCI CLKOE COSCI OSCILLATOR 32.768 kHz DIVIDER CLOCK OUT CLKOUT OSCO COSCO MONITOR OFFSET FUNCTION 0Dh Offset_register TIMER FUNCTION TEST VDD 0Eh Timer_clkout 0Fh Countdown_timer VSS CONTROL POWER ON RESET 00h Control_1 01h Control_2 TIME WATCH DOG SDO SPI INTERFACE SDI SCL 02h Seconds 03h Minutes 04h Hours 05h Days 06h Weekdays 07h Months 08h Years ALARM FUNCTION CE Rpd PCF2123 09h Minute_alarm 0Ah Hour_alarm 0Bh Day_alarm 0Ch Weekday_alarm INT INTERRUPT 013aaa223 Fig 1. Block diagram of PCF2123 PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 3 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 7. Pinning information OSCO 1 TEST 2 13 VDD 14 n.c. terminal 1 index area 15 n.c. 16 OSCI 7.1 Pinning 12 CLKOUT 11 CLKOE PCF2123BS 10 SCL 6 7 8 n.c. SDO 9 n.c. 4 5 CE 3 VSS INT SDI 001aai550 OSCI 1 14 VDD OSCO 2 13 CLKOUT n.c. 3 TEST 4 INT 5 10 SCL CE 6 9 SDI VSS 7 8 SDO 12 CLKOE PCF2123TS Transparent top view 001aai551 For mechanical details, see Figure 31 on page 45. Fig 2. 11 n.c. Top view. For mechanical details, see Figure 32 on page 46. Pin configuration for HVQFN16 (PCF2123BS/1) OSCI 7 OSCO 8 TEST 9 INT 10 CE 11 VSS 12 Fig 3. Pin configuration for TSSOP14 (PCF2123TS/1) 6 VDD 5 CLKOUT 4 CLKOE 3 SCL 2 SDI 1 SDO PCF2123U 001aai544 Viewed from active side. For mechanical details, see Figure 33 on page 47 and Figure 34 on page 48. Fig 4. PCF2123 Product data sheet Pin configuration for PCF2123Ux (bare die) All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 4 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 7.2 Pin description Table 4. Pin description Symbol Pin Description HVQFN16 TSSOP14 PCF2123Ux (PCF2123BS/1) (PCF2123TS/1) (bare die) OSCI 16 1 7 oscillator input; high-impedance node; minimize wire length between quartz and package OSCO 1 2 8 oscillator output; high-impedance node; minimize wire length between quartz and package n.c. 6, 7, 14, 15 3, 11 - do not connect and do not use as feed through; connect to VDD if floating pins are not allowed TEST 2 4 9 test pin; not user accessible; connect to VSS or leave floating (internally pulled down) INT 3 5 10 interrupt output (open-drain; active LOW) CE 4 6 11 chip enable input (active HIGH) with internal pull down VSS 5[1] 7 12[2] ground SDO 8 8 1 serial data output, push-pull; high-impedance when not driving; can be connected to SDI for single wire data line SDI 9 9 2 serial data input; may float when CE is inactive SCL 10 10 3 serial clock input; may float when CE is inactive CLKOE 11 12 4 CLKOUT enable or disable pin; enable is active HIGH CLKOUT 12 13 5 clock output (open-drain) 13 14 6 supply voltage; positive or negative steps in VDD may affect oscillator performance; recommend 100 nF decoupling close to the device (see Figure 30) VDD [1] The die paddle (exposed pad) is wired to VSS and should be electrically isolated. [2] The substrate (rear side of the die) is wired to VSS and should be electrically isolated. PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 5 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 8. Functional description The PCF2123 contains 16 8-bit registers with an auto-incrementing address counter, an on-chip 32.768 kHz oscillator with two integrated load capacitors, a frequency divider which provides the source clock for the Real Time Clock (RTC), a programmable clock output, and a 6.25 Mbit/s SPI-bus. An offset register allows fine tuning of the clock. All 16 registers are designed as addressable 8-bit parallel registers although not all bits are implemented. • The first two registers (memory address 00h and 01h) are used as control registers. • The memory addresses 02h through 08h are used as counters for the clock function (seconds up to years). The registers Seconds, Minutes, Hours, Days, Weekdays, Months, and Years are all coded in Binary Coded Decimal (BCD) format. When one of the RTC registers is written or read the contents of all counters are frozen. Therefore, faulty writing or reading of the clock and calendar during a carry condition is prevented. • • • • Addresses 09h through 0Ch define the alarm condition. Address 0Dh defines the offset calibration. Address 0Eh defines the clock out and timer mode. Address registers 0Eh and 0Fh are used for the countdown timer function. The countdown timer has four selectable source clocks allowing for countdown periods in the range from 244 s up to four hours. There are also two pre-defined timers which can be used to generate an interrupt once per second or once per minute. These are defined in register Control_2 (01h). 8.1 Low power operation Minimum power operation will be achieved by reducing the number and frequency of switching signals inside the IC, i.e., low frequency timer clocks and a low frequency CLKOUT will result in lower operating power. A second prime consideration is the series resistance Rs of the quartz used. 8.1.1 Power consumption with respect to quartz series resistance The series resistance acts as a loss element. Low Rs will reduce current consumption further. PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 6 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 001aai558 250 IDD(1) (nA) 210 170 130 90 50 0 20 40 60 80 Rs(2) (kΩ) 100 Configuration: CLKOUT disabled, VDD = 3 V, timer clock set to 1⁄60 Hz. (1) IDD (nA) minimum power mode. (2) Maximum value for RS is 100 k. Fig 5. IDD with respect to quartz RS 8.1.2 Power consumptions with respect to timer mode Four source clocks are possible for the timer. The 4.096 kHz source clock will add the greatest part to the power consumption. The selection of 64 Hz, 1 Hz, or 1⁄60 Hz will be almost indistinguishable and add very little. 001aai559 400 IDD(1) (nA) 300 (2) 200 (3) 100 0 0 2 4 6 VDD (V) Configuration: CLKOUT disabled, quartz RS = 15 k. (1) IDD (nA) minimum power mode. (2) Timer clock = 4 kHz. (3) Timer clock = 64 Hz, 1 Hz, 1⁄60 Hz. Fig 6. PCF2123 Product data sheet IDD with respect to timer clock selection All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 7 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 8.2 Register overview 16 registers are available. The time registers are encoded in the Binary Coded Decimal (BCD) format to simplify application use. Other registers are either bit-wise or standard binary. Table 5. Registers overview Bit positions labelled as - are not implemented and will return a 0 when read. The bit position labelled as -- is not implemented and will return a 0 or 1 when read. Bit positions labelled with N should always be written with logic 0[1]. Address Register name Bit 7 6 5 4 3 2 1 0 Control and status registers 00h Control_1 EXT_TEST N STOP SR N 12_24 CIE N 01h Control_2 MI SI MSF TI_TP AF TF AIE TIE Time and date registers 02h Seconds OS SECONDS (0 to 59) 03h Minutes -- MINUTES (0 to 59) 04h Hours - - AMPM HOURS (1 to 12) in 12 h mode HOURS (0 to 23) in 24 h mode 05h Days - - DAYS (1 to 31) 06h Weekdays - - - - 07h Months - - - MONTHS (1 to 12) 08h Years YEARS (0 to 99) - WEEKDAYS (0 to 6) Alarm registers 09h Minute_alarm AE_M MINUTE_ALARM (0 to 59) 0Ah Hour_alarm AE_H - AMPM HOUR_ALARM (1 to 12) in 12 h mode HOUR_ALARM (0 to 23) in 24 h mode 0Bh Day_alarm AE_D - DAY_ALARM (1 to 31) 0Ch Weekday_alarm AE_W - - MODE OFFSET[6:0] COF[2:0] - - WEEKDAY_ALARM (0 to 6) TE - Offset register 0Dh Offset_register Timer registers 0Eh Timer_clkout - 0Fh Countdown_timer COUNTDOWN_TIMER[7:0] [1] CTD[1:0] Except in the case of software reset, see Section 8.3.1.1. PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 8 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 8.3 Control registers 8.3.1 Register Control_1 Table 6. Bit 7 Control_1 - control and status register 1 (address 00h) bit description Symbol Value Description Reference EXT_TEST 0[1] normal mode Section 8.10 1 external clock test mode 6 N - unused - 5 STOP 0[1] the RTC source clock runs Section 8.11 1 the RTC clock is stopped; RTC divider chain flip-flops are asynchronously set to logic 0; CLKOUT at 32.768 kHz, 16.384 kHz or 8.192 kHz is still available 4 SR 0[1] 1 no software reset initiate software Section 8.3.1.1 reset[2]; this register will always return a 0 when read 3 N - unused - 2 12_24 0[1] 24 hour mode is selected - 1 12 hour mode is selected 1 CIE 0[1] no correction interrupt generated 1 interrupt pulses will be generated at every correction cycle - unused 0 8.3.1.1 N Section 8.9 - [1] Default value. [2] For a software reset, 01011000 (58h) must be sent to register Control_1 (see Section 8.3.1.1). Reset A reset is automatically generated at power-on. A reset can also be initiated with the software reset command. It is generally recommended to make a software reset after power-on. A software reset can be initiated by setting the bits 6, 4 and 3 in register Control_1 logic 1 and all other bits logic 0 by sending the bit sequence 01011000 (58h), see Figure 7. If this bit sequence is not correct, the software reset instruction will be ignored to protect the device from accidently being reset. When sending the software instruction, the other bits are not written. PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 9 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar R/W b7 0 addr 00HEX b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 software reset 58HEX b0 0 b7 0 b6 1 b5 0 b4 1 b3 1 b2 0 b1 0 b0 0 SCL CE (1) internal reset signal 001aai562 (1) When CE is inactive, the interface is reset. Fig 7. Software reset command After reset, the following mode is entered: • • • • • • 32.768 kHz on pin CLKOUT active 24 hour mode is selected Offset register is set to 0 No alarms set Timer disabled No interrupts enabled Table 7. Register reset values Bits labeled as - are not implemented. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Address PCF2123 Product data sheet Register name Bit 7 6 5 4 3 2 1 0 00h Control_1 0 0 0 0 0 0 0 0 01h Control_2 0 0 0 0 0 0 0 0 02h Seconds 1 X X X X X X X 03h Minutes - X X X X X X X 04h Hours - - X X X X X X 05h Days - - X X X X X X 06h Weekdays - - - - - X X X 07h Months - - - X X X X X 08h Years X X X X X X X X 09h Minute_alarm 1 X X X X X X X 0Ah Hour_alarm 1 - X X X X X X 0Bh Day_alarm 1 - X X X X X X 0Ch Weekday_alarm 1 - - - - X X X 0Dh Offset_register 0 0 0 0 0 0 0 0 0Eh Timer_clkout - 0 0 0 0 - 1 1 0Fh Countdown_timer X X X X X X X X All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 10 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 8.3.2 Register Control_2 Table 8. Bit Control_2 - control and status register 2 (address 01h) bits description Symbol Value Description Reference 7 MI 0[1] minute interrupt is disabled Section 8.6.3 1 minute interrupt is enabled 6 SI 0[1] second interrupt is disabled 1 second interrupt is enabled 0[1] no minute or second interrupt generated 1 flag set when minute or second interrupt generated; 5 MSF flag must be cleared to clear interrupt when TI_IP = 0 4 3 TI_TP AF 0[1] interrupt pin follows timer flags 1 interrupt pin generates a pulse 0[1] no alarm interrupt generated 1 flag set when alarm triggered; Section 8.7.2 Section 8.5.5 flag must be cleared to clear interrupt 2 TF 0[1] no countdown timer interrupt generated 1 flag set when countdown timer interrupt generated; Section 8.6.4 flag must be cleared to clear interrupt when TI_IP = 0 1 0 [1] PCF2123 Product data sheet AIE TIE 0[1] no interrupt generated from the alarm flag 1 interrupt generated when alarm flag set 0[1] no interrupt generated from the countdown Section 8.7.2 timer 1 interrupt generated by the countdown timer Section 8.7.3 Default value. All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 11 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 8.4 Time and date function The majority of the registers are coded in the Binary Coded Decimal (BCD) format. BCD is used to simplify application use. An example is shown for the seconds in Table 10. 8.4.1 Register Seconds Table 9. Seconds - seconds register (address 02h) bit description Bit Symbol Value Place value Description 7 OS 0 - clock integrity is guaranteed 1[1] - clock integrity is not guaranteed; oscillator has stopped or has been interrupted 0 to 5 ten’s place 0 to 9 unit place actual seconds coded in BCD format, see Table 10 6 to 4 SECONDS 3 to 0 [1] Default value. Table 10. 8.4.1.1 Seconds coded in BCD format Seconds value (decimal) Upper-digit (ten’s place) Digit (unit place) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 1 02 0 0 0 0 0 0 1 0 : : : : : : : : : 09 0 0 0 0 1 0 0 1 10 0 0 0 1 0 0 0 0 : : : : : : : : : 58 0 1 0 1 1 0 0 0 59 0 1 0 1 1 0 0 1 OS flag The PCF2123 includes a flag (OS in register Seconds, see Table 9) which is set whenever the oscillator is stopped (see Figure 8 and Figure 9). The flag will remain set until cleared by software. If the flag cannot be cleared, then the PCF2123 oscillator is not running. This method can be used to monitor the oscillator and to determine if the supply voltage has reduced to the point where oscillation fails. main supply VDD battery operation VOSC(MIN) t 001aai561 Fig 8. PCF2123 Product data sheet OS set by failing VDD All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 12 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar OS = 1 and flag can not be cleared OS = 1 and flag can be cleared VDD oscillation OS flag OS flag cleared by software OS flag set when oscillation stops t oscillation now stable 001aai553 Fig 9. OS flag The oscillator may be stopped, for example, by grounding one of the oscillator pins, OSCI or OSCO. The oscillator is also considered to be stopped during the time between power-on and stable crystal resonance. This time may be in the range of 200 ms to 2 s depending on crystal type, temperature and supply voltage. At power-on the OS flag is always set. 8.4.2 Register Minutes Table 11. Minutes - minutes register (address 03h) bit description Bit Symbol Value Place value Description 7 - - - unused 6 to 4 MINUTES 0 to 5 ten’s place 0 to 9 unit place actual minutes coded in BCD format 3 to 0 8.4.3 Register Hours Table 12. Hours - hours register (address 04h) bit description Bit Symbol Value Place value Description 7 to 6 - - - unused 12 hour mode[1] 5 AMPM 0 - indicates AM 1 - indicates PM 0 to 1 ten’s place 0 to 9 unit place actual hours in 12 hour mode coded in BCD format 0 to 2 ten’s place 0 to 9 unit place 4 HOURS 3 to 0 24 hour mode[1] 5 to 4 3 to 0 [1] PCF2123 Product data sheet HOURS actual hours in 24 hour mode coded in BCD format Hour mode is set by the 12_24 bit in register Control_1. All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 13 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 8.4.4 Register Days Table 13. Days - days register (address 05h) bit description Bit Symbol Value Place value Description 7 to 6 - - - unused 5 to 4 DAYS[1] 0 to 3 ten’s place actual day coded in BCD format 0 to 9 unit place 3 to 0 [1] The PCF2123 compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year 00. 8.4.5 Register Weekdays Table 14. Weekdays - weekdays register (address 06h) bit description Bit Symbol Value Description 7 to 3 - - unused 2 to 0 WEEKDAYS 0 to 6 actual weekday values, see Table 15 Table 15. Weekday assignments Day[1] Bit 2 1 0 Sunday 0 0 0 Monday 0 0 1 Tuesday 0 1 0 Wednesday 0 1 1 Thursday 1 0 0 Friday 1 0 1 Saturday 1 1 0 [1] Definition may be re-assigned by the user. 8.4.6 Register Months Table 16. Symbol Value Place value Description 7 to 5 - - - unused 4 MONTHS 0 to 1 ten’s place 0 to 9 unit place actual month coded in BCD format, see Table 17 3 to 0 PCF2123 Product data sheet Months - months register (address 07h) bit description Bit All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 14 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 17. Month assignments in BCD format Month Upper-digit (ten’s place) Digit (unit place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 January 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April 0 0 1 0 0 May 0 0 1 0 1 June 0 0 1 1 0 July 0 0 1 1 1 August 0 1 0 0 0 September 0 1 0 0 1 October 1 0 0 0 0 November 1 0 0 0 1 December 1 0 0 1 0 8.4.7 Register Years Table 18. Years - years register (08h) bit description Bit Symbol 7 to 4 YEARS 3 to 0 Value Place value Description 0 to 9 ten’s place 0 to 9 unit place actual year coded in BCD format 8.4.8 Setting and reading the time Figure 10 shows the data flow and data dependencies starting from the 1 Hz clock tick. 1 Hz tick SECONDS MINUTES 12_24 hour mode HOURS LEAP YEAR CALCULATION DAYS WEEKDAY MONTHS YEARS 001aaf901 Fig 10. Data flow of the time function PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 15 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar During read/write operations, the time counting circuits (memory locations 02h through 08h) are blocked. This prevents • Faulty reading of the clock and calendar during a carry condition • Incrementing the time registers during the read cycle After this read/write access is completed, the time circuit is released again and any pending request to increment the time counters that occurred during the read/write access is serviced. A maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see Figure 11). t1 4096 1⁄ 8192 1⁄ 4096 64 1⁄ 128 1⁄ 64 1 1⁄ 64 1⁄ 64 1⁄ 60 1⁄ 64 1⁄ 64 [1] n = loaded countdown value. Timer stopped when n = 0. If the TF flag is cleared before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately it is serviced, i.e., the system does not have to wait for the completion of the pulse before continuing (see Figure 18). Instructions for clearing MSF can be found in Section 8.6.5. PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 26 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar countdown counter 01 n CDTF INT (1) SCL 8th clock instruction CLEAR INSTRUCTION 001aaf909 (1) Indicates normal duration of INT pulse (bit TI_TP = 1). Fig 18. Example of shortening the INT pulse by clearing the TF flag The timing shown for clearing bit TF in Figure 18 is also valid for the non-pulsed interrupt mode, i.e., when bit TI_TP = 0; INT may be shortened by setting bit TIE to logic 0. 8.7.3 Alarm interrupts The generation of interrupts from the alarm function is controlled via bit AIE (see Table 8). If bit AIE is enabled, the INT pin follows the condition of bit AF. Clearing bit AF will immediately clear INT. No pulse generation is possible for alarm interrupts (see Figure 19). minute counter 44 minute alarm 45 45 AF INT SCL 8th clock instruction CLEAR INSTRUCTION 001aaf910 Example where only the minute alarm is used and no other interrupts are enabled. Fig 19. AF timing 8.7.3.1 Correction pulse interrupts Interrupt pulses generated by correction events can be shortened by writing logic 1 to bit CIE in register Control_1. PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 27 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 8.8 Clock output A programmable square wave is available at pin CLKOUT. Operation is controlled by the COF[2:0] bits in the register Timer_clkout. Frequencies of 32.768 kHz (default) down to 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. Pin CLKOUT is an open-drain output and enabled at power-on. When disabled the output is high-impedance. The duty cycle of the selected clock is not controlled. However, due to the nature of the clock generation, all will be 50 : 50 except the 32.768 kHz frequencies. The STOP bit function can also affect the CLKOUT signal, depending on the selected frequency. When the STOP bit is set logic 1, the CLKOUT pin will generate a continuous LOW for those frequencies that can be stopped. For more details of the STOP bit function see Section 8.11. Table 36. CLKOUT frequency selection Bits COF[2:0] CLKOUT frequency (Hz) Typical duty cycle[1] Effect of STOP bit 000 32768 60 : 40 to 40 : 60 no effect 001 16384 50 : 50 no effect 010 8192 50 : 50 no effect 011 4096 50 : 50 CLKOUT = LOW 100 2048 50 : 50 CLKOUT = LOW 101 1024 50 : 50 CLKOUT = LOW 110 1[2] 50 : 50 CLKOUT = LOW 111 CLKOUT = high-Z - - [1] Duty cycle definition: % HIGH-level time : % LOW-level time. [2] 1 Hz clock pulses will be affected by offset correction pulses. 8.8.1 CLKOE pin The CLKOE pin can be used to block the CLKOUT function and force the CLKOUT pin to a high-impedance state. The effect is the same as setting COF[2:0] = 111. PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 28 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 8.9 Offset register The PCF2123 incorporates an offset register (address 0Dh) which can be used to implement several functions, such as: • Ageing adjustment • Temperature compensation • Accuracy tuning The offset is made once every two hours in the normal mode, or once every hour in the course mode. Each LSB will introduce an offset of 2.17 ppm for normal mode and 4.34 ppm for course mode. The values of 2.17 ppm and 4.34 ppm are based on a nominal 32.768 kHz clock. The offset value is coded in two’s complement giving a range of +63 LSB to 64 LSB. Table 37. Register Offset_register OFFSET[6:0] Offset value in decimal Offset value in ppm Normal mode MODE = 0 Course mode MODE = 1 0 1 1 1 1 1 1 +63 +136.71 +273.42 0 1 1 1 1 1 0 +62 +134.54 +269.08 : : : 0 0 0 0 0 1 0 +2 +4.34 +8.68 0 0 0 0 0 0 1 +1 +2.17 +4.34 0 0 0 0 0 0 0 0[1] 0 0 1 1 1 1 1 1 1 1 2.17 4.34 1 1 1 1 1 1 0 2 4.34 8.68 : : : : 1 0 0 0 0 0 1 : 63 136.71 273.42 1 0 0 0 0 0 0 64 138.88 277.76 [1] Default mode. The correction is made by adding or subtracting 64 Hz clock correction pulses, thereby changing the period of a single second. Table 38. Example of converting the offset in ppm to seconds Offset in ppm Seconds per Day Week Month Year 2.17 0.187 1.31 5.69 68.2 4.34 0.375 2.62 11.4 136 In normal mode, the correction is triggered once per two hours and then correction pulses are applied once per minute until the programmed correction values have been implement. In course mode, the correction is triggered once per hour and then correction pulses are applied once per minute up to a maximum of 60 minutes. When correction values greater than 60 are used, additional correction pulses are made in the 59th minute (see Table 39). PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 29 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 39. Correction pulses for course mode Correction value +1 or 1 +2 or 2 +3 or 3 Hour:Minute[1] Correction pulses on INT per minute[2] 02:00 1 02:01 to 02:59 0 02:00 1 02:01 1 02:02 to 02:59 0 02:00 1 02:01 1 02:02 1 02:03 to 02:59 0 : : : +59 or 59 02:00 to 02:58 1 02:59 0 +60 or 60 02:00 to 02:59 1 +61 or 61 02:00 to 02:58 1 02:59 2 02:00 to 02:58 1 02:59 3 02:00 to 02:58 1 02:59 4 02:00 to 02:58 1 02:59 5 +62 or 62 +63 or 63 64 [1] Example is given in a time range from 2:00 to 2:59. [2] Correction INT pulses are 1⁄128 s wide. For multiple pulses they are repeated at 1⁄64 s interval. It is possible to monitor when correction pulses are applied. The correction interrupt enable mode (bit CIE) will generate a 1⁄128 second pulse on INT for every correction applied. In the case where multiple correction pulses are applied, a 1⁄128 second interrupt pulse will be generated and repeated every 1⁄64 seconds. Correction is applied to the 1 Hz clock. Any timer or clock output using a frequency of 1 Hz or below will also be affected by the correction pulses. PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 30 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 40. Effect of correction pulses Frequency (Hz) Effect of correction CLKOUT 32768 no effect 16384 no effect 8192 no effect 4096 no effect 2048 no effect 1024 no effect 1 affected Time source clock 4096 no effect 64 no effect 1 affected 1⁄ 60 affected 8.9.1 Offset calibration workflow The calibration offset has to be calculated based on the time. Figure 20 shows the workflow how the offset register values can be calculated: Measure the frequency on pin CLKOUT: fmeas Convert to time: tmeas = 1 / fmeas Calculate the difference to the ideal period of 1 / 32768.00: Dmeas = 1 / 32768 - tmeas Calculate the ppm deviation compared to the measured value: Eppm = 1000000 × Dmeas / tmeas Calculate the offset register value: Mode = 0 (normal mode): Offset value = Eppm / 2.17 Mode = 1 (course mode) Offset value = Eppm / 4.34 013aaa684 Fig 20. Offset calibration calculation workflow PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 31 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 8.10 External clock test mode A test mode is available which allows for on-board testing. In this mode it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit EXT_TEST in register Control_1. Then pin CLKOUT becomes an input. The test mode replaces the internal clock signal with the signal applied to pin CLKOUT. The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a maximum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided down to 1 Hz by a 26 divide chain called a prescaler. The prescaler can be set into a known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0. (STOP must be cleared before the prescaler can operate again.) From a stop condition, the first 1 second increment will take place after 32 positive edges on pin CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment. Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assumption as to the state of the prescaler can be made. Operation example: 1. Set EXT_TEST test mode (register Control_1, bit EXT_TEST = 1). 2. Set STOP (Control_1, bit STOP = 1). 3. Clear STOP (Control_1, bit STOP = 0). 4. Set time registers to desired value. 5. Apply 32 clock pulses to pin CLKOUT. 6. Read time registers to see the first change. 7. Apply 64 clock pulses to pin CLKOUT. 8. Read time registers to see the second change. Repeat 7 and 8 for additional increments. PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 32 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 8.11 STOP bit function The function of the STOP bit is to allow for accurate starting of the time circuits. The STOP bit function will cause the upper part of the prescaler (F2 to F14) to be held in reset and thus no 1 Hz ticks will be generated. The time circuits can then be set and will not increment until the STOP bit is released (see Figure 22 and Table 41). The STOP bit function will not affect the output of 32.768 kHz, 16.384 kHz, or 8.192 kHz (see Section 8.8). F2 RESET F13 RESET 2 Hz oscillator stop flag 4096 Hz F1 8192 Hz F0 16384 Hz OSCILLATOR 32768 Hz OSCILLATOR STOP DETECTOR F14 1 Hz tick RESET stop 1 Hz 1024 Hz CLKOUT source 8192 Hz 16384 Hz 001aai556 Fig 21. STOP bit functional diagram The lower two stages of the prescaler (F0 and F1) are not reset and because the SPI-bus is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be between 0 and one 8.192 kHz cycle (see Figure 22). 8192 Hz stop released 0 μs to 122 μs 001aaf912 Fig 22. STOP bit release timing The first increment of the time circuits is between 0.499878 s and 0.500000 s after STOP bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset (see Table 41). PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 33 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 41. First increment of time circuits after STOP bit release Bit Prescaler bits[1] STOP F0F1-F2 to F14 1 Hz tick Time Comment hh:mm:ss Clock is running normally 0 12:45:12 01-0 0001 1101 0100 prescaler counting normally STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally 1 12:45:12 prescaler is reset; time circuits are frozen 08:00:00 prescaler is reset; time circuits are frozen XX-0 0000 0000 0000 08:00:00 prescaler is now running XX-1 0000 0000 0000 08:00:00 - 08:00:00 - 08:00:00 - : : XX-0 0000 0000 0000 New time is set by user 1 XX-0 0000 0000 0000 XX-0 1000 0000 0000 XX-1 1000 0000 0000 : 08:00:00 - 08:00:01 0 to 1 transition of F14 increments the time circuits 10-0 0000 0000 0001 08:00:01 - : : : 11-1 1111 1111 1111 08:00:01 - 08:00:01 - 10-0 0000 0000 0000 08:00:01 - : : : 11-1 1111 1111 1110 08:00:01 - 00-0 0000 0000 0001 08:00:02 0 to 1 transition of F14 increments the time circuits 11-1 1111 1111 1110 00-0 0000 0000 0001 00-0 0000 0000 0000 1s 0 0.499878 s to 0.500000 s STOP bit is released by user 013aaa352 [1] F0 is clocked at 32.768 kHz. PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 34 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 9. 3-line serial interface Data transfer to and from the device is made via a 3-wire SPI-bus (see Table 42). The data lines for input and output are split. The data input and output lines can be connected together to facilitate a bidirectional data bus. The chip enable signal is used to identify the transmitted data. Each data transfer is a byte, with the Most Significant Bit (MSB) sent first (see Figure 24). Table 42. Serial interface Symbol Function Description CE chip enable input when LOW, the interface is reset; pull-down resistor included; active input may be higher than VDD, but may not be wired permanently HIGH SCL serial clock input when CE is LOW, this input may float; input may be higher than VDD SDI serial data input when CE is LOW, input may float; input may be higher than VDD; input data is sampled on the rising edge of SCL SDO serial data output push-pull output; drives from VSS to VDD; output data is changed on the falling edge of SCL; will be high-Z when not driving; may be connected directly to SDI SDI SDI SDO SDO two wire mode single wire mode 001aai560 Fig 23. SDI, SDO configurations The transmission is controlled by the active HIGH chip enable signal CE. The first byte transmitted is the command byte. Subsequent bytes will be either data to be written or data to be read. Data is sampled on the rising edge of the clock and transferred internally on the falling edge. data bus COMMAND DATA DATA DATA chip enable 001aaf914 Fig 24. Data transfer overview The command byte defines the address of the first register to be accessed and the read/write mode. The address counter will auto increment after every access and will rollover to zero after the last register is accessed. The read/write bit (R/W) defines if the following bytes will be read or write information. PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 35 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 43. Command byte definition Bit Symbol 7 R/W Value Description data read or data write selection 0 write data 1 read data 6 to 4 SA 001 subaddress; other codes will cause the device to ignore data transfer 3 to 0 RA 0h to Fh register address range In Figure 25, the register Seconds is set to 45 seconds and the register Minutes is set to 10 minutes. R/W b7 0 addr 02HEX b6 0 b5 0 b4 1 b3 0 b2 0 b1 1 minutes data 10BCD seconds data 45BCD b0 0 b7 0 b6 1 b5 0 b4 0 b3 0 b2 1 b1 0 b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 0 SCL SDI CE address counter xx 02 03 04 001aaf915 Fig 25. Serial bus write example R/W b7 1 months data 11BCD addr 07HEX b6 0 b5 0 b4 1 b3 0 b2 1 b1 1 b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 years data 06BCD b1 0 b0 1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 1 b1 1 b0 0 SCL SDI SDO CE address counter xx 07 08 09 001aaf916 Fig 26. Serial bus read example PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 36 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar In Figure 26, the Months and Years registers are read. In this example, pins SDI and SDO are not connected together. For this configuration, it is important that pin SDI is never left floating. It must always be driven either HIGH or LOW. If pin SDI is left open, high IDD currents may result. Short transition periods in the order of 200 ns will not cause any problems. 9.1 Interface watchdog timer During read/write operations, the time counting circuits are frozen. To prevent a situation where the accessing device becomes locked and does not clear the interface by setting pin CE LOW, the PCF2123 has a built in watchdog timer. Should the interface be active for more than 1 s from the time a valid subaddress is transmitted, then the PCF2123 will automatically clear the interface and allow the time counting circuits to continue counting. CE must return LOW once more before a new data transfer can be executed. tw(CE) < 1 s CE data valid sub-address data WD timer time counters data data WD timer running running time counters frozen running 001aai563 a. Correct data transfer: read or write 1 s < tw(CE) < 2 s CE data valid sub-address data WD timer time counters data data data transfer fail WD timer running running time counters frozen WD trips running 001aai564 b. Incorrect data transfer: read or write Fig 27. Interface watchdog timer The watchdog is implemented to prevent the excessive loss of time due to interface access failure e.g. if main power is removed from a battery backed-up system during an interface access. Each time the watchdog period is exceeded, 1 s will be lost from the time counters. The watchdog will trigger between 1 s and 2 s after receiving a valid subaddress. PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 37 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 10. Internal circuitry PCF2123 VDD OSCI CLKOE OSCO CLKOUT TEST SCL INT SDI CE SDO VSS 001aai552 Fig 28. Device diode protection diagram of PCF2123 11. Safety notes CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices. Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or equivalent standards. CAUTION Semiconductors are light sensitive. Exposure to light sources can cause the IC to malfunction. The IC must be protected against light. The protection must be applied to all sides of the IC. PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 38 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 12. Limiting values Table 44. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol PCF2123 Product data sheet Parameter Conditions [1] Min Max Unit 0.5 +6.5 V VDD supply voltage IDD supply current 50 +50 mA VI input voltage [1] 0.5 +6.5 V VO output voltage [1] 0.5 +6.5 V II input current 10 +10 mA IO output current 10 +10 mA Ptot total power dissipation - 300 mW VESD electrostatic discharge voltage [2] - 3000 V Ilu latch-up current [3] - 200 mA Tstg storage temperature [4] 65 +150 C Tamb ambient temperature 40 +85 C HBM operating device [1] With respect to VSS. [2] Pass level; Human Body Model (HBM) according to Ref. 9 “JESD22-A114” [3] Pass level; latch-up testing, according to Ref. 10 “JESD78” at maximum ambient temperature (Tamb(max)). [4] According to the store and transport requirements (see Ref. 14 “UM10569”) the devices have to be stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 39 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 13. Static characteristics Table 45. Static characteristics VDD = 1.1 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 15 k; CL = 7 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit supply voltage for clock data integrity; SPI-bus inactive 1.1 - 5.5 V Tamb = 25 C - 0.9 - V SPI-bus active 1.8 - 5.5 V fSCL = 4.5 MHz; VDD = 5 V - 250 400 A fSCL = 1.0 MHz; VDD = 3 V - 30 80 A Tamb = 25 C; VDD = 2.0 V - 100 - nA Tamb = 25 C; VDD = 3.0 V - 110 - nA Tamb = 25 C; VDD = 5.0 V - 120 - nA VDD = 2.0 V - - 330 nA VDD = 3.0 V - - 350 nA VDD = 5.0 V - - 380 nA VDD = 2.0 V - 260 - nA VDD = 3.0 V - 340 - nA VDD = 5.0 V - 520 - nA VDD = 2.0 V - - 450 nA VDD = 3.0 V - - 550 nA VDD = 5.0 V - - 750 nA Supplies VDD IDD supply current [1] SPI-bus active SPI-bus inactive; CLKOUT disabled SPI-bus inactive; CLKOUT disabled; Tamb = 40 C to +85 C [2] [2] SPI-bus inactive; CLKOUT enabled at 32 kHz; Tamb = 25 C SPI-bus inactive; CLKOUT enabled at 32 kHz; Tamb = 40 C to +85 C PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 40 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 45. Static characteristics …continued VDD = 1.1 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 15 k; CL = 7 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Inputs VIL LOW-level input voltage - - 0.3VDD V VIH HIGH-level input voltage 0.7VDD - - V VI input voltage on pins CE, SDI, SCL, OSCI, CLKOE, CLKOUT 0.5 - +5.5 V ILI input leakage current VI = VDD or VSS on pins SDI, SCL, OSCI, CLKOE, CLKOUT - 0 - A 1 0 - A [3] VI = VSS on pin CE pull-down resistance Rpd Ci on pin CE input capacitance on pins SDI, SCL, CLKOE and CE [4] output voltage on pins CLKOUT and INT [5] - 240 550 k - - 7 pF 0.5 - +5.5 V Outputs VO on pin OSCO 0.5 - +5.5 V on pin SDO 0.5 - VDD + 0.5 V VOH HIGH-level output voltage on pin SDO 0.8VDD - VDD V VOL LOW-level output voltage on pin SDO VSS - 0.2VDD V on pins CLKOUT and INT; VDD = 5 V; IOL = 1.5 mA VSS - 0.4 V IOH HIGH-level output current output source current; VOH = 4.6 V; VDD = 5 V on pin SDO 1.5 - - mA IOL LOW-level output current output sink current; VOL = 0.4 V; VDD = 5 V on pins INT, SDO and CLKOUT 1.5 - - mA ILO output leakage current VO = VDD or VSS [3] - 0 - A on pins OSCO and OSCI [6] 3.3 7 14 pF - - 100 k CL(itg) integrated load capacitance Rs series resistance [1] For reliable oscillator start at power-on: VDD = VDD(min) + 0.3 V. [2] Timer source clock = 1⁄60 Hz, level of pins CE, SDI, and SCL is VDD or VSS. [3] In case of an ESD event, the value may increase slightly. [4] Implicit by design. [5] Refers to external pull-up voltage. [6] Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series: C L  itg  = -------------------------------------------- .  C OSCI + C OSCO  PCF2123 Product data sheet  C OSCI  C OSCO  All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 41 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 14. Dynamic characteristics Table 46. SPI-bus characteristics VSS = 0 V; Tamb = 40 C to +85 C. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and VIH with an input voltage swing of VSS to VDD. Symbol Parameter Conditions VDD = 1.8 V VDD = 2.4 V VDD = 3.3 V VDD = 5.0 V Min Max Min Max Min Max Min Max Unit Timing characteristics (see Figure 29) fclk(SCL) SCL clock frequency - 2.9 - 4.54 - 5.71 - 8.0 MHz tSCL SCL time 345 - 220 - 175 - 125 - ns tclk(H) clock HIGH time 90 - 50 - 45 - 40 - ns tclk(L) clock LOW time 200 - 120 - 95 - 70 - ns tr rise time for SCL signal - 100 - 100 - 100 - 100 ns tf fall time for SCL signal - 100 - 100 - 100 - 100 ns tsu(CE) CE set-up time 40 - 35 - 30 - 25 - ns th(CE) CE hold time 40 - 30 - 25 - 15 - ns trec(CE) CE recovery time 30 - 25 - 20 - 15 - ns tw(CE) CE pulse width measured after valid subaddress is received - 0.99 - 0.99 - 0.99 - 0.99 s tsu set-up time set-up time for SDI data 10 - 5 - 3 - 2 - ns th hold time hold time for SDI data 25 - 10 - 8 - 5 - ns td(R)SDO SDO read delay time bus load = 50 pF 190 - 108 - 85 - 60 ns tdis(SDO) SDO disable time no load value; bus will be held up by bus capacitance; use RC time constant with application values 70 - 45 - 40 - 27 ns to avoid bus conflict - 0 - 0 - 0 - ns tt(SDI-SDO) transition time from SDI to SDO PCF2123 Product data sheet - 0 All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 42 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar tw(CE) CE tsu(CE) tSCL tclk(H) tclk(L) tr tf trec(CE) th(CE) 80% SCL 20% WRITE tsu th SDI SDO R/W SA2 RA0 b6 b0 b7 b6 b0 Hi Z READ SDI b7 tt(SDI-SDO) tdis(SDO) td(R)SDO SDO Hi Z b7 b6 b0 001aai554 Fig 29. SPI-bus timing PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 43 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 15. Application information 1F supercapacitor 100 nF VDD CLKOE CLKOUT INT CE OSCI PCF2123 SCL OSCO VSS SDO SDI 001aai557 A 1 farad super capacitor combined with a low VF diode can be used as a standby or back-up supply. With the RTC in its minimum power configuration i.e. timer off and CLKOUT off, the RTC may operate for weeks. Fig 30. Typical application diagram PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 44 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 16. Package outline HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm A B D SOT758-1 terminal 1 index area A E A1 c detail X e1 C 1/2 e e 5 y y1 C v M C A B w M C b 8 L 4 9 e e2 Eh 1/2 e 12 1 16 terminal 1 index area 13 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.1 2.9 1.75 1.45 3.1 2.9 1.75 1.45 0.5 1.5 1.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT758-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 02-03-25 02-10-21 Fig 31. Package outline SOT758-1 (HVQFN16) of PCF2123BS/1 PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 45 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 32. Package outline SOT402-1 (TSSOP14) of PCF2123TS/1 PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 46 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 17. Bare die outline Wire bond die; 12 bonding pads PCF2123U/10 D A 6 7 5 8 9 10 11 12 P4 P3 4 x 0 E 3 0 y 2 P2 1 P1 X eD detail X 0 1 mm scale OUTLINE VERSION REFERENCES IEC JEDEC EUROPEAN PROJECTION JEITA ISSUE DATE 08-07-24 11-04-06 PCF2123U/10 Fig 33. Bare die outline PCF2123U/10 of PCF2123U/5GA/1 and PCF2123U/10AA/1 (for dimensions see Table 47) Table 47. Dimensions of PCF2123U/10 Original dimensions are in mm. Unit (mm) A[1] D[2] E[2] eD P1[3] P2[4] P3[3] P4[4] 1.492 1.449 1.296 0.09 0.081 0.09 0.081 1.492 1.449 1.296 0.09 0.081 0.09 0.081 PCF2123U/5GA/1 nom 0.20 PCF2123U/10AA/1 nom PCF2123 Product data sheet 0.20 [1] Nominal die thickness. Compare with wafer thickness given in Table 51. [2] Dimension includes saw lane. [3] P1 and P3: pad size. [4] P2 and P4: passivation opening. All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 47 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar WLCSP12: wafer level chip size package; 12 bumps. PCF2123U/12 D 6 7 PC2123-1 5 8 4 9 x0 10 E 0 y 3 2 11 e 12 1 Y e X P4 P3 A1 P2 A2 P1 A detail Y detail X 0 0.5 1 mm scale pcf2123u_12_do References Outline version IEC JEDEC JEITA PCF2123U/12 --- --- --- European projection Issue date 10-07-13 11-04-06 Fig 34. Bare die outline PCF2123U/12 of PCF2123U/12AA/1 and PCF2123U/12HA/1 (for dimensions see Table 48) PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 48 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 48. Dimensions of PCF2123U/12 Original dimensions are in mm. Unit (mm) A[1] A1 A2[1] D[2] E[2] e P1[3] P2[4] P3[3] P4[4] PCF2123U/12AA max - 0.018 - - - 1.296 - 0.084 - 0.084 nom 0.22 0.015 0.2 1.492 1.449 - 0.09 0.081 0.09 0.081 min - 0.012 - - - 0.198 - 0.078 - 0.078 PCF2123U/12HA max - 0.018 - - - 1.296 - 0.084 - 0.084 nom 0.17 0.015 0.15 1.492 1.449 - 0.09 0.081 0.09 0.081 min - 0.012 - - - 0.198 - 0.078 - 0.078 [1] Nominal die thickness. Compare with wafer thickness given in Table 51. [2] Dimension includes saw lane. [3] P1 and P3: pad size. [4] P2 and P4: bump size. Table 49. Bump locations of all PCF2123U types All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see Figure 33 and Figure 34. Symbol PCF2123 Product data sheet Bump Coordinates x y SDO 1 648.0 575.0 SDI 2 648.0 377.0 SCL 3 648.0 179.0 CLKOE 4 648.0 171.2 CLKOUT 5 648.0 369.2 VDD 6 648.0 625.7 OSCI 7 648.0 639.0 OSCO 8 648.0 421.9 TEST 9 648.0 25.9 INT 10 648.0 223.9 CE 11 648.0 441.0 VSS 12 648.0 639.0 All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 49 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 50. Alignment mark dimension and location of all PCF2123U types Coordinates x y Location[1] 516.2 693 Dimension[2] 16 m 13 m [1] The x/y coordinates of the alignment mark location represent the position of the REF point (see Figure 35) with respect to the center (x/y = 0) of the chip; see Figure 33 and Figure 34. [2] The x/y values of the dimensions represent the extensions of the alignment mark in direction of the coordinate axis (see Figure 35). REF y x 013aaa231 Fig 35. Alignment mark PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 50 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 18. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 19. Packing information 1.492 mm (1) ~18 μm 1 1 1.449 mm 45 μm Saw lane ~18 μm X 1 1 70 μm detail X straight edge of the wafer 013aaa232 (1) Die marking code. Seal ring plus gap to active circuit ~18 m. Fig 36. PCF2123Ux wafer information Table 51. Type number Wafer thickness (m) Wafer diameter Marking of bad die PCF2123U/5GA/1 687 6 inch wafer mapping[1] PCF2123U/10AA/1 200 6 inch inking PCF2123U/12AA/1 200 6 inch wafer mapping[1] PCF2123U/12HA/1 150 6 inch inking [1] PCF2123 Product data sheet PCF2123Ux wafer information Wafer mapping information will be distributed to customer’s ftp server. All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 51 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar PP PP PP PP PHWDOIUDPH  VWUDLJKWHGJH RIWKHZDIHU PP ‘PP ‘     P P SODVWLFILOP DDD Fig 37. Film Frame Carrier (FFC) for 6 inch wafer (PCF2123U/10AA/1) PP PP PP PPSODVWLN PPPHWDOO IUDPH  VWUDLJKWHGJH RIWKHZDIHU PP ‘PP ‘   P P SODVWLFILOP DDD Fig 38. Film Frame Carrier (FFC) for 8 inch wafer (PCF2123U/12AA/1 and PCF2123U/12HA/1) PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 52 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 20. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 20.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 20.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 20.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 53 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 20.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 39) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 52 and 53 Table 52. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 53. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 39. PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 54 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 39. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 55 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 21. Footprint information for reflow soldering Footprint information for reflow soldering of HVQFN16 package SOT758-1 Hx Gx D P 0.025 0.025 C (0.105) SPx Hy SPy tot nSPx Gy SPy nSPy SLy By Ay SPx tot SLx Bx Ax solder land solder paste deposit solder land plus solder paste occupied area nSPx nSPy 2 2 Dimensions in mm P Ax Ay Bx By C D SLx SLy 0.50 4.00 4.00 2.20 2.20 0.90 0.24 1.50 1.50 Issue date SPx tot SPy tot 0.90 0.90 SPx SPy Gx Gy Hx Hy 0.30 0.30 3.30 3.30 4.25 4.25 12-03-07 12-03-08 sot758-1_fr Fig 40. Footprint information for reflow soldering of SOT758-1 (HVQFN16) package of PCF2123BS/1 PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 56 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar Footprint information for reflow soldering of TSSOP14 package SOT402-1 Hx Gx P2 (0.125) (0.125) Hy By Gy Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.750 7.200 4.500 1.350 0.400 0.600 4.950 5.300 5.800 7.450 sot402-1_fr Fig 41. Footprint information for reflow soldering of SOT402-1 (TSSOP14) package of PCF2123TS/1 PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 57 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 22. Abbreviations Table 54. PCF2123 Product data sheet Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor BCD Binary Coded Decimal ESD ElectroStatic Discharge FFC Film Frame Carrier HBM Human Body Model LSB Least Significant Bit MM Machine Model MOS Metal Oxide Semiconductor MSB Most Significant Bit MSL Moisture Sensitivity Level PCB Printed-Circuit Board RTC Real Time Clock SMD Surface Mount Device SPI Serial Peripheral Interface All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 58 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 23. References [1] AN10365 — Surface mount reflow soldering description [2] AN10366 — HVQFN application information [3] AN10706 — Handling bare die [4] AN10853 — Handling precautions of ESD sensitive devices [5] AN11247 — Improved timekeeping accuracy with PCF85063, PCF8523 and PCF2123 using an external temperature sensor [6] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [7] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [8] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [9] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [10] JESD78 — IC Latch-Up Test [11] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [12] SNV-FA-01-02 — Marking Formats Integrated Circuits [13] UM10301 — User Manual for NXP Real Time Clocks PCF85x3, PCA8565 and PCF2123, PCA2125 [14] UM10569 — Store and transport requirements 24. Revision history Table 55. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF2123 v.6 20130715 Product data sheet - PCF2123 v.5 Modifications: • • • • Changed spec value in Table 45 for SPI-bus active to 1.8 V Added Section 8.9.1 Adjusted raise and fall time values of the SPI-bus in Table 46 Added ordering options in Table 2 PCF2123 v.5 20110427 Product data sheet - PCF2123 v.4 PCF2123 v.4 20101222 Product data sheet - PCF2123 v.3 PCF2123 v.3 20101005 Product data sheet - PCF2123_2 PCF2123_2 20091204 Product data sheet - PCF2123_1 PCF2123_1 20081119 Product data sheet - - PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 59 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 25. Legal information 25.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 25.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 25.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PCF2123 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 60 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. 25.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 26. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 61 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 27. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2 Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Registers overview . . . . . . . . . . . . . . . . . . . . . .8 Control_1 - control and status register 1 (address 00h) bit description . . . . . . . . . . . . . . .9 Register reset values . . . . . . . . . . . . . . . . . . . .10 Control_2 - control and status register 2 (address 01h) bits description . . . . . . . . . . . . . 11 Seconds - seconds register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .12 Seconds coded in BCD format . . . . . . . . . . . .12 Minutes - minutes register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .13 Hours - hours register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .13 Days - days register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .14 Weekdays - weekdays register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .14 Weekday assignments . . . . . . . . . . . . . . . . . . .14 Months - months register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .14 Month assignments in BCD format . . . . . . . . . .15 Years - years register (08h) bit description . . . .15 Minute_alarm - minute alarm register (address 09h) bit description . . . . . . . . . . . . . .17 Hour_alarm - hour alarm register (address 0Ah) bit description . . . . . . . . . . . . . .17 Day_alarm - day alarm register (address 0Bh) bit description . . . . . . . . . . . . . .17 Weekday_alarm - weekday alarm register (address 0Ch) bit description . . . . . . . . . . . . . .18 Flag location in register Control_2 . . . . . . . . . .19 Example to clear only AF (bit 3) in register Control_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Timer_clkout - timer control register (address 0Eh) bit description . . . . . . . . . . . . . .20 Countdown_timer - countdown timer register (address 0Ah) bit description . . . . . . . . . . . . . .20 Effect of bits MI and SI on INT generation . . . .21 Effect of MI and SI on MSF . . . . . . . . . . . . . . .21 Bits CTD0 and CTD1 for timer frequency selection and countdown timer durations . . . . .22 First period delay for timer counter value n . . .23 Flag location in register Control_2 . . . . . . . . . .24 Example to clear only TF (bit 2) in register Control_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Example to clear only MSF (bit 5) in register Control_2 . . . . . . . . . . . . . . . . . . . .24 Example to clear both TF and MSF (bit 2 and bit 5) in register Control_2 . . . . . . . .24 INT operation (bit TI_TP = 1) . . . . . . . . . . . . . .26 CLKOUT frequency selection . . . . . . . . . . . . .28 Register Offset_register . . . . . . . . . . . . . . . . . .29 PCF2123 Product data sheet Table 38. Example of converting the offset in ppm to seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 39. Correction pulses for course mode . . . . . . . . . 30 Table 40. Effect of correction pulses . . . . . . . . . . . . . . . . 31 Table 41. First increment of time circuits after STOP bit release . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 42. Serial interface . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 43. Command byte definition . . . . . . . . . . . . . . . . 36 Table 44. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 45. Static characteristics . . . . . . . . . . . . . . . . . . . . 40 Table 46. SPI-bus characteristics . . . . . . . . . . . . . . . . . . 42 Table 47. Dimensions of PCF2123U/10 . . . . . . . . . . . . . 47 Table 48. Dimensions of PCF2123U/12 . . . . . . . . . . . . . 49 Table 49. Bump locations of all PCF2123U types . . . . . 49 Table 50. Alignment mark dimension and location of all PCF2123U types . . . . . . . . . . . . . . . . . . . 50 Table 51. PCF2123Ux wafer information. . . . . . . . . . . . . 51 Table 52. SnPb eutectic process (from J-STD-020D) . . . 54 Table 53. Lead-free process (from J-STD-020D) . . . . . . 54 Table 54. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 55. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 59 All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 62 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 28. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. Fig 29. Fig 30. Fig 31. Fig 32. Fig 33. Fig 34. Fig 35. Fig 36. Fig 37. Fig 38. Fig 39. Fig 40. Fig 41. Block diagram of PCF2123 . . . . . . . . . . . . . . . . . .3 Pin configuration for HVQFN16 (PCF2123BS/1) . .4 Pin configuration for TSSOP14 (PCF2123TS/1) . .4 Pin configuration for PCF2123Ux (bare die) . . . . .4 IDD with respect to quartz RS . . . . . . . . . . . . . . . . .7 IDD with respect to timer clock selection . . . . . . . .7 Software reset command . . . . . . . . . . . . . . . . . . .10 OS set by failing VDD . . . . . . . . . . . . . . . . . . . . . .12 OS flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Data flow of the time function. . . . . . . . . . . . . . . .15 Access time for read/write operations . . . . . . . . .16 Alarm function block diagram. . . . . . . . . . . . . . . .18 Alarm flag timing . . . . . . . . . . . . . . . . . . . . . . . . .19 INT example for MI and SI . . . . . . . . . . . . . . . . . .21 General countdown timer behavior . . . . . . . . . . .22 Interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . .25 Example of shortening the INT pulse by clearing the MSF flag . . . . . . . . . . . . . . . . . . .26 Example of shortening the INT pulse by clearing the TF flag . . . . . . . . . . . . . . . . . . . . .27 AF timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Offset calibration calculation workflow . . . . . . . . .31 STOP bit functional diagram . . . . . . . . . . . . . . . .33 STOP bit release timing . . . . . . . . . . . . . . . . . . . .33 SDI, SDO configurations . . . . . . . . . . . . . . . . . . .35 Data transfer overview . . . . . . . . . . . . . . . . . . . . .35 Serial bus write example . . . . . . . . . . . . . . . . . . .36 Serial bus read example . . . . . . . . . . . . . . . . . . .36 Interface watchdog timer . . . . . . . . . . . . . . . . . . .37 Device diode protection diagram of PCF2123 . . .38 SPI-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Typical application diagram . . . . . . . . . . . . . . . . .44 Package outline SOT758-1 (HVQFN16) of PCF2123BS/1 . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Package outline SOT402-1 (TSSOP14) of PCF2123TS/1 . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Bare die outline PCF2123U/10 of PCF2123U/5GA/1 and PCF2123U/10AA/1 (for dimensions see Table 47) . . . . . . . . . . . . . . .47 Bare die outline PCF2123U/12 of PCF2123U/12AA/1 and PCF2123U/12HA/1 (for dimensions see Table 48) . . . . . . . . . . . . . . .48 Alignment mark . . . . . . . . . . . . . . . . . . . . . . . . . .50 PCF2123Ux wafer information. . . . . . . . . . . . . . .51 Film Frame Carrier (FFC) for 6 inch wafer (PCF2123U/10AA/1) . . . . . . . . . . . . . . . . . . . . . .52 Film Frame Carrier (FFC) for 8 inch wafer (PCF2123U/12AA/1 and PCF2123U/12HA/1) . . .52 Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Footprint information for reflow soldering of SOT758-1 (HVQFN16) package of PCF2123BS/1 . . . . . . . . . . . . . . . . . . . . . . . . .56 Footprint information for reflow soldering of SOT402-1 (TSSOP14) package of PCF2123TS/1 . . . . . . . . . . . . . . . . . . . . . . . . .57 PCF2123 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 63 of 64 PCF2123 NXP Semiconductors SPI Real time clock/calendar 29. Contents 1 2 3 4 4.1 5 6 7 7.1 7.2 8 8.1 8.1.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Low power operation . . . . . . . . . . . . . . . . . . . . 6 Power consumption with respect to quartz series resistance . . . . . . . . . . . . . . . . 6 8.1.2 Power consumptions with respect to timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.2 Register overview . . . . . . . . . . . . . . . . . . . . . . . 8 8.3 Control registers . . . . . . . . . . . . . . . . . . . . . . . . 9 8.3.1 Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 9 8.3.1.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.3.2 Register Control_2 . . . . . . . . . . . . . . . . . . . . . 11 8.4 Time and date function . . . . . . . . . . . . . . . . . . 12 8.4.1 Register Seconds . . . . . . . . . . . . . . . . . . . . . . 12 8.4.1.1 OS flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.4.2 Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 13 8.4.3 Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 13 8.4.4 Register Days . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.4.5 Register Weekdays. . . . . . . . . . . . . . . . . . . . . 14 8.4.6 Register Months . . . . . . . . . . . . . . . . . . . . . . . 14 8.4.7 Register Years . . . . . . . . . . . . . . . . . . . . . . . . 15 8.4.8 Setting and reading the time. . . . . . . . . . . . . . 15 8.5 Alarm function. . . . . . . . . . . . . . . . . . . . . . . . . 17 8.5.1 Register Minute_alarm . . . . . . . . . . . . . . . . . . 17 8.5.2 Register Hour_alarm . . . . . . . . . . . . . . . . . . . 17 8.5.3 Register Day_alarm . . . . . . . . . . . . . . . . . . . . 17 8.5.4 Register Weekday_alarm . . . . . . . . . . . . . . . . 18 8.5.5 Alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.6 Timer functions . . . . . . . . . . . . . . . . . . . . . . . . 20 8.6.1 Register Timer_clkout. . . . . . . . . . . . . . . . . . . 20 8.6.2 Register Countdown_timer . . . . . . . . . . . . . . . 20 8.6.3 Minute and second interrupt . . . . . . . . . . . . . . 20 8.6.4 Countdown timer function . . . . . . . . . . . . . . . . 22 8.6.5 Timer flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.7 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 25 8.7.1 Minute and second interrupts . . . . . . . . . . . . . 26 8.7.2 Countdown timer interrupts. . . . . . . . . . . . . . . 26 8.7.3 8.7.3.1 8.8 8.8.1 8.9 8.9.1 8.10 8.11 9 9.1 10 11 12 13 14 15 16 17 18 19 20 20.1 20.2 20.3 20.4 21 22 23 24 25 25.1 25.2 25.3 25.4 26 27 28 29 Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . Correction pulse interrupts . . . . . . . . . . . . . . . Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . Offset register . . . . . . . . . . . . . . . . . . . . . . . . Offset calibration workflow . . . . . . . . . . . . . . . External clock test mode . . . . . . . . . . . . . . . . STOP bit function . . . . . . . . . . . . . . . . . . . . . . 3-line serial interface . . . . . . . . . . . . . . . . . . . Interface watchdog timer . . . . . . . . . . . . . . . . Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Footprint information for reflow soldering . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 28 28 29 31 32 33 35 37 38 38 39 40 42 44 45 47 51 51 53 53 53 53 54 56 58 59 59 60 60 60 60 61 61 62 63 64 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 July 2013 Document identifier: PCF2123