PCF2127AT/1,512

PCF2127AT Integrated RTC, TCXO and quartz crystal Rev. 6 — 11 July 2013 Product data sheet 1. General description The PCF2127AT1 is a CMOS2 Real Time Clock (RTC) and calendar with an integrated Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal optimized for very high accuracy and very low power consumption. The PCF2127AT has 512 bytes of general purpose static RAM, a selectable I2C-bus or SPI-bus, a backup battery switch-over circuit, a programmable watchdog function, a timestamp function, and many other features. 2. Features and benefits                     Temperature Compensated Crystal Oscillator (TCXO) with integrated capacitors Typical accuracy: 3 ppm from 15 C to +60 C Integration of a 32.768 kHz quartz crystal and oscillator in the same package Provides year, month, day, weekday, hours, minutes, seconds, and leap year correction 512 bytes of general purpose static RAM Timestamp function  with interrupt capability  detection of two different events on one multilevel input pin (for example, for tamper detection) Two line bidirectional 400 kHz Fast-mode I2C-bus interface (IOL = 3 mA at pin SDA/CE) 3 line SPI-bus with separate data input and output (maximum speed 6.5 Mbit/s) Battery backup input pin and switch-over circuitry Battery backed output voltage Battery low detection function Extra power fail detection function with input and output pins Power-On Reset Override (PORO) Oscillator stop detection function Interrupt output and system reset pin (open-drain) Programmable 1 second or 1 minute interrupt Programmable countdown timer with interrupt capability Programmable watchdog timer with interrupt and reset capability Programmable alarm function with interrupt capability Programmable square wave open-drain output pin 1. As well as the PCF2129. 2. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 20. PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal  Clock operating voltage: 1.2 V to 4.2 V  Low supply current: typical 0.65 A at VDD = 3.0 V and Tamb = 25 C 3. Applications       Electronic metering for electricity, water, and gas Precision timekeeping Access to accurate time of the day GPS equipment to reduce time to first fix Applications that require an accurate process timing Products with long automated unattended operation time 4. Ordering information Table 1. Ordering information Type number Package PCF2127AT Name Description Version SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 4.1 Ordering options Table 2. Ordering options Product type number IC revision Sales item (12NC) Delivery form PCF2127AT/1[1] 1 935290953512 tube, dry pack 935290953518 tape and reel, 13 inch, dry pack 935299867518 tape and reel, 13 inch, dry pack PCF2127AT/2 [1] 2 Not to be used for new designs. Replacement part is PCF2127AT/2. 5. Marking Table 3. PCF2127AT Product data sheet Marking codes Product type number Marking code PCF2127AT/1 PCF2127AT PCF2127AT/2 PCF2127AT All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 2 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 6. Block diagram INT TCXO OSCI Control_1 00h Control_2 01h Control_3 02h Seconds 03h Minutes 04h Hours 05h Days 06h Weekdays 07h Months 08h Years 09h Second_alarm 0Ah Minute_alarm 0Bh Hour_alarm 0Ch Day_alarm 0Dh Weekday_alarm 0Eh CLKOUT_ctl 0Fh Watchdg_tim_ctl 10h Watchdg_tim_val 11h Timestp_ctl 12h Sec_timestp 13h Min_timestp 14h Hour_timestp 15h Day_timestp 16h Mon_timestp 17h SCL Year_timestp 18h SDO Aging_offset 19h RAM_addr_MSB 1Ah RAM_addr_LSB 1Bh RAM_wrt_cmd 1Ch RAM_rd_cmd 1Dh DIVIDER AND TIMER 32.768 kHz OSCO CLKOUT BBS VDD BATTERY BACK UP SWITCH-OVER CIRCUITRY VBAT VSS OSCILLATOR MONITOR internal power supply TEMP 1 Hz LOGIC CONTROL RESET RST SPI-BUS INTERFACE ADDRESS REGISTER SDA/CE SERIAL BUS INTERFACE SELECTOR SDO SDI SCL IFS I2C-BUS INTERFACE PCF2127AT RPU TS SDI 512 BYTES STATIC RAM SDA/CE PFI TEMP 1.25 V (internal) TEMPERATURE SENSOR PFO Fig 1. TEST 001aaj675 Block diagram of PCF2127AT PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 3 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 7. Pinning information 7.1 Pinning SCL 1 SDI 2 20 VDD 19 VBAT SDO 3 18 BBS SDA/CE 4 17 INT IFS 5 TS 6 CLKOUT 7 14 PFO VSS 8 13 TEST n.c. 9 12 n.c. n.c. 10 11 n.c. PCF2127AT 16 RST 15 PFI 001aaj676 Top view. For mechanical details, see Figure 53. Fig 2. Pin configuration for SO20 (PCF2127AT) 7.2 Pin description Table 4. Pin description of SO20 (PCF2127AT) Symbol Pin Description SCL 1 combined serial clock input for both I2C-bus and SPI-bus SDI 2 serial data input for SPI-bus; connect to pin VSS if I2C-bus is selected SDO 3 serial data output for SPI-bus, push-pull SDA/CE 4 combined serial data input and output for the I2C-bus and chip enable input (active LOW) for the SPI-bus IFS 5 interface selector input connect to pin VSS to select the SPI-bus connect to pin BBS to select the I2C-bus PCF2127AT Product data sheet TS 6 timestamp input (active LOW) with 200 k internal pull-up resistor (RPU) CLKOUT 7 clock output (open-drain) VSS 8 ground supply voltage n.c. 9 to 12 not connected; do not connect; do not use as feed through TEST 13 do not connect; do not use as feed through PFO 14 power fail output (open-drain; active LOW) PFI 15 power fail input RST 16 reset output (open-drain; active LOW) INT 17 interrupt output (open-drain; active LOW) All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 4 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal Table 4. Pin description of SO20 (PCF2127AT) …continued Symbol Pin Description BBS 18 output voltage (battery backed) VBAT 19 battery supply voltage (backup) VDD 20 supply voltage connect to VSS if battery switch over is not used PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 5 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8. Functional description The PCF2127AT is a Real Time Clock (RTC) and calendar with an on-chip Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal integrated into the same package (see Section 8.3.2). Address and data are transferred by a selectable 400 kHz Fast-mode I2C-bus or a 3 line SPI-bus with separate data input and output (see Section 9). The maximum speed of the SPI-bus is 6.5 Mbit/s. The PCF2127AT has a backup battery input pin and backup battery switch-over circuit which monitors the main power supply. The backup battery switch-over circuit automatically switches to the backup battery when a power failure condition is detected (see Section 8.6.1). Accurate timekeeping is maintained even when the main power supply is interrupted. A battery low detection circuit monitors the status of the battery (see Section 8.6.3). When the battery voltage drops below a certain threshold value, a flag is set to indicate that the battery must be replaced soon. This ensures the integrity of the data during periods of battery backup. 8.1 Register overview The PCF2127AT contains an auto-incrementing address register: the built-in address register will increment automatically after each read or write of a data byte up to the register 1Bh. After register 1Bh, the auto-incrementing will wrap around to address 00h (see Figure 3). address register 00h 01h 02h auto-increment 03h ... 19h 1Ah wrap around 1Bh 1Ch not reachable by auto-inc. - needs to be addressed directly 1Dh not reachable by auto-inc. - needs to be addressed directly 001aaj307 Fig 3. Handling address registers • The first three registers (memory address 00h, 01h, and 02h) are used as control registers (see Section 8.2). • The registers at addresses 03h through to 09h are used as counters for the clock function (seconds up to years). The date is automatically adjusted for months with fewer than 31 days, including corrections for leap years. The clock can operate in 12-hour mode with an AM/PM indication or in 24-hour mode (see Section 8.9). • The registers at addresses 0Ah through 0Eh define the alarm function. It can be selected that an interrupt is generated when an alarm event occurs (see Section 8.10). PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 6 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal • The register at address 0Fh defines the temperature measurement period and the clock out mode. The temperature measurement can be selected from every 4 minutes (default) down to every 30 seconds (see Table 10). CLKOUT frequencies of 32.768 kHz (default) down to 1 Hz for use as system clock, microcontroller clock, and so on, can be chosen (see Table 11). • The registers at addresses 10h and 11h are used for the watchdog and countdown timer functions. The watchdog timer has four selectable source clocks allowing for timer periods from less than 1 ms to greater than 4 hours (see Table 37). Either the watchdog timer or the countdown timer can be enabled (see Section 8.11). For the watchdog timer, it is possible to select whether an interrupt or a pulse on the reset pin will be generated when the watchdog times out. For the countdown timer, it is only possible that an interrupt will be generated at the end of the countdown. • The registers at addresses 12h to 18h are used for the timestamp function. When the trigger event happens, the actual time is saved in the timestamp registers (see Section 8.12). • The register at address 19h is used for the correction of the crystal aging effect (see Section 8.4.1). • The registers at addresses 1Ah and 1Bh define the RAM address. The register at address 1Ch (RAM_wrt_cmd) is the RAM write command; the register at 1Dh (RAM_rd_cmd) is the RAM read command. Data is transferred to or from the RAM by the serial interface (see Section 8.5). • The registers Seconds, Minutes, Hours, Days, Months, and Years are all coded in Binary Coded Decimal (BCD) format to simplify application use. Other registers are either bit-wise or standard binary. When one of the RTC registers is written or read, the content of all counters is temporarily frozen. This prevents a faulty writing or reading of the clock and calendar during a carry condition (see Section 8.9.8). PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 7 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal Table 5. Register overview Bit positions labeled as - are not implemented and will return a 0 when read. Bit T must always be written with logic 0. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Address Register name Bit Reset value 7 6 5 4 3 2 1 0 Control registers 00h Control_1 EXT_ TEST T STOP TSF1 POR_ OVRD 12_24 MI SI 0000 0000 01h Control_2 MSF WDTF TSF2 AF CDTF TSIE AIE CDTIE 0000 0000 02h Control_3 PWRMNG[2:0] BTSE BF BLF BIE BLIE 0000 0000 Time and date registers 03h Seconds OSF SECONDS (0 to 59) 1XXX XXXX 04h Minutes - MINUTES (0 to 59) - XXX XXXX 05h Hours - - AMPM HOURS (1 to 12) in 12 h mode - - XX XXXX HOURS (0 to 23) in 24 h mode 06h Days - - 07h Weekdays - - - 08h Months - - - 09h Years - - XX XXXX DAYS (1 to 31) - - - - XX XXXX WEEKDAYS (0 to 6) MONTHS (1 to 12) - - - - - XXX - - - X XXXX YEARS (0 to 99) XXXX XXXX Alarm registers 0Ah Second_alarm AE_S SECOND_ALARM (0 to 59) 1XXX XXXX 0Bh Minute_alarm AE_M MINUTE_ALARM (0 to 59) 1XXX XXXX 0Ch Hour_alarm AE_H - 0Dh Day_alarm AE_D - 0Eh Weekday_alarm AE_W - AMPM - HOUR_ALARM (1 to 12) in 12 h mode HOUR_ALARM (0 to 23) in 24 h mode 1 - XX XXXX 1 - XX XXXX DAY_ALARM (1 to 31) 1 - XX XXXX - - - WEEKDAY_ALARM (0 to 6) 1 - - - - XXX TCR[1:0] - - - COF[2:0] WD_CD[1:0] TI_TP - - - CLKOUT control register 0Fh CLKOUT_ctl 00 - - - 000 Watchdog registers 10h Watchdg_tim_ctl 11h Watchdg_tim_val WATCHDG_TIM_VAL[7:0] TF[1:0] 000 - - - 11 XXXX XXXX Timestamp registers 12h Timestp_ctl TSM TSOFF - 1_O_16_TIMESTP[4:0] 13h Sec_timestp - SECOND_TIMESTP (0 to 59) - XXX XXXX 14h Min_timestp - MINUTE_TIMESTP (0 to 59) - XXX XXXX 15h Hour_timestp - - AMPM HOUR_TIMESTP (1 to 12) in 12 h mode 00 - X XXXX - - XX XXXX HOUR_TIMESTP (0 to 23) in 24 h mode - - XX XXXX 16h Day_timestp - - DAY_TIMESTP (1 to 31) - - XX XXXX 17h Mon_timestp - - - - - - X XXXX 18h Year_timestp YEAR_TIMESTP (0 to 99) MONTH_TIMESTP (1 to 12) XXXX XXXX Aging offset register 19h Aging_offset PCF2127AT Product data sheet - - - - AO[3:0] All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 - - - - 1000 © NXP B.V. 2013. All rights reserved. 8 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal Table 5. Register overview …continued Bit positions labeled as - are not implemented and will return a 0 when read. Bit T must always be written with logic 0. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Address Register name Bit Reset value 7 6 5 4 3 2 1 0 1Ah RAM_addr_MSB - - - - - - - RA8 1Bh RAM_addr_LSB RA[7:0] 1Ch RAM_wrt_cmd X X X X X X X X XXXX XXXX 1Dh RAM_rd_cmd X X X X X X X X XXXX XXXX RAM registers PCF2127AT Product data sheet ---- ---0 0000 0000 All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 9 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.2 Control registers The first 3 registers of the PCF2127AT, with the addresses 00h, 01h, and 02h, are used as control registers. 8.2.1 Register Control_1 Table 6. Bit 7 Control_1 - control and status register 1 (address 00h) bit description Symbol Value EXT_TEST 0 [1] 1 6 5 T STOP Description Reference normal mode Section 8.14 external clock test mode 0 [2] unused - 0 [1] RTC source clock runs Section 8.15 1 RTC clock is stopped; RTC divider chain flip-flops are asynchronously set logic 0; CLKOUT at 32.768 kHz, 16.384 kHz, or 8.192 kHz is still available 4 TSF1 0 [1] 1 no timestamp interrupt generated Section 8.12.1 flag set when TS input is driven to an intermediate level between power supply and ground; flag must be cleared to clear interrupt 3 POR_OVRD 0 [1] Power-On Reset Override (PORO) facility disabled; Section 8.8.2 set logic 0 for normal operation 1 2 12_24 0 1 MI 0 Power-On Reset Override (PORO) sequence reception enabled [1] 1 SI 0 1 PCF2127AT Product data sheet Table 23 12 hour mode selected [1] 1 0 24 hour mode selected minute interrupt disabled Section 8.13 minute interrupt enabled [1] second interrupt disabled second interrupt enabled [1] Default value. [2] When writing to the register this bit always has to be set logic 0. All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 10 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.2.2 Register Control_2 Table 7. Bit 7 Control_2 - control and status register 2 (address 01h) bit description Symbol MSF Value 0 [1] 1 Description Reference no minute or second interrupt generated Section 8.13 flag set when minute or second interrupt generated; flag must be cleared to clear interrupt 6 WDTF 0 [1] 1 no watchdog timer interrupt or reset generated Section 8.13.4 flag set when watchdog timer interrupt or reset generated; flag cannot be cleared by command (read-only) 5 TSF2 0 [1] 1 no timestamp interrupt generated Section 8.12.1 flag set when TS input is driven to ground; flag must be cleared to clear interrupt 4 AF 0 [1] 1 no alarm interrupt generated Section 8.10.6 flag set when alarm triggered; flag must be cleared to clear interrupt 3 CDTF 0 [1] 1 no countdown timer interrupt generated Section 8.11.4 flag set when countdown timer interrupt generated; flag must be cleared to clear interrupt 2 TSIE 0 [1] 1 1 AIE 0 [1] 1 0 CDTIE 0 1 [1] PCF2127AT Product data sheet no interrupt generated from timestamp flag Section 8.13.6 interrupt generated when timestamp flag set no interrupt generated from the alarm flag Section 8.13.5 interrupt generated when alarm flag set [1] no interrupt generated from countdown timer Section 8.13.2 flag interrupt generated when countdown timer flag set Default value. All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 11 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.2.3 Register Control_3 Table 8. Bit Control_3 - control and status register 3 (address 02h) bit description Symbol Value Description 7 to 5 PWRMNG[2:0] [1] control of the battery switch-over, battery low Section 8.6 detection, and extra power fail detection functions 4 0 BTSE [2] 1 3 BF 0 Reference no timestamp when battery switch-over occurs Section 8.12.4 time-stamped when battery switch-over occurs [2] 1 no battery switch-over interrupt generated Section 8.6.1 flag set when battery switch-over occurs; flag must be cleared to clear interrupt 2 BLF 0 [2] battery status ok; Section 8.6.3 no battery low interrupt generated 1 battery status low; flag cannot be cleared by command 1 BIE 0 [2] 1 0 BLIE 0 1 PCF2127AT Product data sheet [1] Values see Table 18. [2] Default value. no interrupt generated from the battery flag (BF) Section 8.13.7 interrupt generated when BF is set [2] no interrupt generated from battery low flag (BLF) Section 8.13.8 interrupt generated when BLF is set All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 12 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.3 Register CLKOUT_ctl Table 9. Bit CLKOUT_ctl - CLKOUT control register (address 0Fh) bit description Symbol Value Description 7 to 6 TCR[1:0] see Table 10 temperature measurement period 5 to 3 - - 2 to 0 COF[2:0] see Table 11 CLKOUT frequency selection unused 8.3.1 Temperature compensated crystal oscillator The frequency of tuning fork quartz crystal oscillators is temperature-dependent. In the PCF2127AT, the frequency deviation caused by temperature variation is corrected by adjusting the load capacitance of the crystal oscillator. The load capacitance is changed by switching between two load capacitance values using a modulation signal with a programmable duty cycle. In order to compensate the spread of the quartz parameters every chip is factory calibrated. The frequency accuracy can be evaluated by measuring the frequency of the square wave signal available at the output pin CLKOUT. However, the selection of fCLKOUT = 32.768 kHz (default value) leads to inaccurate measurements. Accurate frequency measurement occurs when fCLKOUT = 16.384 kHz or lower is selected (see Table 11). 8.3.1.1 Temperature measurement The PCF2127AT has a temperature sensor circuit used to perform the temperature compensation of the frequency. The temperature is measured immediately after power-on and then periodically with a period set by the temperature conversion rate TCR[1:0] in the register CLKOUT_ctl. Table 10. Temperature measurement period TCR[1:0] Temperature measurement period [1] 00 01 4 min 2 min 10 1 min 11 30 seconds [1] Default value. 8.3.2 Clock output A programmable square wave is available at pin CLKOUT. Operation is controlled by the COF[2:0] control bits in register CLKOUT_ctl. Frequencies of 32.768 kHz (default) down to 1 Hz can be generated for use as system clock, microcontroller clock, charge pump input, or for calibrating the oscillator. CLKOUT is an open-drain output and enabled at power-on. When disabled, the output is high-impedance. The duty cycle of the selected clock is not controlled, however, due to the nature of the clock generation all but the 32.768 kHz frequencies will be 50 : 50. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 13 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal Table 11. PCF2127AT Product data sheet CLKOUT frequency selection COF[2:0] CLKOUT frequency (Hz) Typical duty cycle[1] 000[2][3] 32768 60 : 40 to 40 : 60 001 16384 50 : 50 010 8192 50 : 50 011 4096 50 : 50 100 2048 50 : 50 101 1024 50 : 50 110 1 50 : 50 111 CLKOUT = high-Z - [1] Duty cycle definition: % HIGH-level time : % LOW-level time. [2] Default value. [3] The specified accuracy of the RTC can be only achieved with CLKOUT frequencies not equal to 32.768 kHz or if CLKOUT is disabled. All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 14 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.4 Register Aging_offset Table 12. Bit Aging_offset - crystal aging offset register (address 19h) bit description Symbol Value Description 7 to 4 - - unused 3 to 0 AO[3:0] see Table 13 aging offset value 8.4.1 Crystal aging correction The PCF2127AT has an offset register Aging_offset to correct the crystal aging effects3. The accuracy of the frequency of a quartz crystal depends on its aging. The aging offset adds an adjustment, positive or negative, in the temperature compensation circuit which allows correcting the aging effect. At 25 C, the aging offset bits allow a frequency correction of typically 1 ppm per AO[3:0] value, from 7 ppm to +8 ppm. Table 13. Frequency correction at 25C, typical AO[3:0] Binary 0 0000 +8 1 0001 +7 2 0010 +6 3 0011 +5 4 0100 +4 5 0101 +3 6 0110 +2 7 0111 +1 [1] 0 8 1000 9 1001 1 10 1010 2 11 1011 3 12 1100 4 13 1101 5 14 1110 6 15 1111 7 [1] 3. ppm Decimal Default value. For further information, refer to the application note Ref. 3 “AN10857”. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 15 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.5 General purpose 512 bytes static RAM The PCF2127AT contains a general purpose 512 bytes static RAM. This integrated SRAM is battery backed and can therefore be used to store data which is essential for the application to survive a power outage. 9 bits, RA[8:0], define the RAM address pointer in registers RAM_addr_MSB and RAM_addr_LSB. The register address pointer increments after each read or write automatically up to 1Bh and then wraps around to address 00h (see Figure 3 on page 6). Data is transferred to or from the RAM by the interface. To write to the RAM, the register RAM_wrt_cmd, to read from the RAM the register RAM_rd_cmd must be addressed explicitly. 8.5.1 Register RAM_addr_MSB Table 14. RAM_addr_MSB - RAM address MSB register (address 1Ah) bit description Bit Symbol Description 7 to 1 - unused 0 RA8 RAM address, MSB (9th bit) 8.5.2 Register RAM_addr_LSB Table 15. RAM_addr_LSB - RAM address LSB register (address 1Bh) bit description Bit Symbol Description 7 to 0 RA[7:0] RAM address, LSB (1st to 8th bit) 8.5.3 Register RAM_wrt_cmd Table 16. RAM_wrt_cmd - RAM write command register (address 1Ch) bit description Bit Symbol Description 7 to 0 - data to be written into RAM 8.5.4 Register RAM_rd_cmd Table 17. PCF2127AT Product data sheet RAM_rd_cmd - RAM read command register (address 1Dh) bit description Bit Symbol Description 7 to 0 - data to be read from RAM All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 16 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.5.5 Operation examples 8.5.5.1 Writing to the RAM 1. Set RAM address: – Select register RAM_addr_MSB (send address 1Ah). – Set value for bit RA8 (data byte of register 1Ah). Note: register address will be incremented automatically to 1Bh. – Set value for array RA[7:0] (data byte of register 1Bh). 2. Send RAM write command: – Select register RAM_wrt_cmd (send address 1Ch). 3. Write data into the RAM: – Write n data byte into RAM. For details, see Figure 44 on page 62. 8.5.5.2 Reading from the RAM 1. Set RAM address: – Select register RAM_addr_MSB (send address 1Ah). – Set value for bit RA8 (data byte of register 1Ah). Note: register address will be incremented automatically to 1Bh. – Set value for array RA[7:0] (data byte of register 1Bh). 2. Send RAM read command: – Select register RAM_rd_cmd (send address 1Dh). 3. Read from the RAM: – Read n data byte from the RAM. For details, see Figure 45 on page 63. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 17 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.6 Power management functions The PCF2127AT has two power supply pins and one power output pin: • VDD - the main power supply input pin • VBAT - the battery backup input pin • BBS - battery backed output voltage pin (equal to the internal power supply) The PCF2127AT has three power management functions implemented: • Battery switch-over function • Battery low detection function • Extra power fail detection function The power management functions are controlled by the control bits PWRMNG[2:0] in register Control_3: Table 18. Power management control bit description PWRMNG[2:0] Function [1] 000 battery switch-over function is enabled in standard mode; battery low detection function is enabled; extra power fail detection function is enabled 001 battery switch-over function is enabled in standard mode; battery low detection function is disabled; extra power fail detection function is enabled 010 battery switch-over function is enabled in standard mode; battery low detection function is disabled; extra power fail detection function is disabled 011 battery switch-over function is enabled in direct switching mode; battery low detection function is enabled; extra power fail detection function is enabled 100 battery switch-over function is enabled in direct switching mode; battery low detection function is disabled; extra power fail detection function is enabled 101 battery switch-over function is enabled in direct switching mode; battery low detection function is disabled; extra power fail detection function is disabled [2] 110 battery switch-over function is disabled - only one power supply (VDD); battery low detection function is disabled; extra power fail detection function is enabled [2] 111 battery switch-over function is disabled - only one power supply (VDD); battery low detection function is disabled; extra power fail detection function is disabled PCF2127AT Product data sheet [1] Default value. [2] When the battery switch-over function is disabled, the PCF2127AT works only with the power supply VDD; VBAT must be put to ground and the battery low detection function is disabled. All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 18 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.6.1 Battery switch-over function The PCF2127AT has a backup battery switch-over circuit which monitors the main power supply VDD. When a power failure condition is detected, it automatically switches to the backup battery. One of two operation modes can be selected: • Standard mode: the power failure condition happens when: VDD < VBAT AND VDD < Vth(sw)bat Vth(sw)bat is the battery switch threshold voltage. Typical value is 2.5 V. The battery switch-over in standard mode works only for VDD > 2.5 V. • Direct switching mode: the power failure condition happens when VDD < VBAT. Direct switching from VDD to VBAT without requiring VDD to drop below Vth(sw)bat When a power failure condition occurs and the power supply switches to the battery, the following sequence occurs: 1. The battery switch flag BF (register Control_3) is set logic 1. 2. An interrupt is generated if the control bit BIE (register Control_3) is enabled (see Section 8.13.7). 3. If the control bit BTSE (register Control_3) is logic 1, the timestamp registers store the time and date when the battery switch occurred (see Section 8.12.4). 4. The battery switch flag BF is cleared by command; it must be cleared to clear the interrupt. The interface is disabled in battery backup operation: • Interface inputs are not recognized, preventing extraneous data being written to the device • Interface outputs are high-impedance PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 19 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.6.1.1 Standard mode If VDD > VBAT OR VDD > Vth(sw)bat, the internal power supply is VDD. If VDD < VBAT AND VDD < Vth(sw)bat, the internal power supply is VBAT. backup battery operation VDD VBBS VBAT VBBS internal power supply (= VBBS) Vth(sw)bat (= 2.5 V) VDD (= 0 V) BF INT cleared via interface 001aaj311 Vth(sw)bat is the battery switch threshold voltage. Typical value is 2.5 V. In standard mode, the battery switch-over works only for VDD > 2.5 V. VDD may be lower than VBAT (for example VDD = 3 V, VBAT = 4.1 V). Fig 4. PCF2127AT Product data sheet Battery switch-over behavior in standard mode with bit BIE set logic 1 (enabled) All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 20 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.6.1.2 Direct switching mode If VDD > VBAT, the internal power supply is VDD. If VDD < VBAT, the internal power supply is VBAT. The direct switching mode is useful in systems where VDD is higher than VBAT at all times. This mode is not recommended if the VDD and VBAT values are similar (for example, VDD = 3.3 V, VBAT  3.0 V). In direct switching mode, the power consumption is reduced compared to the standard mode because the monitoring of VDD and Vth(sw)bat is not performed. backup battery operation VDD VBBS VBAT VBBS internal power supply (= VBBS) Vth(sw)bat (= 2.5 V) VDD (= 0 V) BF INT cleared via interface 001aaj312 Fig 5. 8.6.1.3 Battery switch-over behavior in direct switching mode with bit BIE set logic 1 (enabled) Battery switch-over disabled: only one power supply (VDD) When the battery switch-over function is disabled: • • • • PCF2127AT Product data sheet The power supply is applied on the VDD pin The VBAT pin must be connected to ground The internal power supply, available at the output pin BBS, is equal to VDD The battery flag (BF) is always logic 0 All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 21 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.6.1.4 Battery switch-over architecture The architecture of the battery switch-over circuit is shown in Figure 6. comparators logic switches VDD(int) VCC VDD Vth(sw)bat VDD VDD(int) VCC VBBS (internal power supply) LOGIC Vth(sw)bat VBAT VBAT 001aag061 VDD(int) Fig 6. Battery switch-over circuit, simplified block diagram The internal power supply (available on pin BBS) is equal to VDD or VBAT. It has to be assured that there are decoupling capacitors on the pins VDD, VBAT, and BBS. 8.6.2 Battery backup supply The VBBS voltage on the output pin BBS is equal to the internal power supply, depending on the selected battery switch-over function mode: Table 19. Output pin BBS Battery switch-over function mode standard direct switching disabled Conditions VBBS equals VDD > VBAT OR VDD > Vth(sw)bat VDD VDD < VBAT AND VDD < Vth(sw)bat VBAT VDD > VBAT VDD VDD < VBAT VBAT only VDD available, VBAT must be put to ground VDD The output pin BBS can be used as a supply for external devices with battery backup needs, such as SRAM (see Ref. 3 “AN10857”). For this case, Figure 7 shows the typical driving capability when VBBS is driven from VDD. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 22 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 001aaj327 0 VBBS − VDD (mV) −200 VDD = 4.2 V −400 VDD = 3 V VDD = 2 V −600 −800 0 2 4 6 8 IBBS (mA) Fig 7. Typical driving capability of VBBS: (VBBS  VDD) with respect to the output load current IBBS 8.6.3 Battery low detection function The PCF2127AT has a battery low detection circuit which monitors the status of the battery VBAT. When VBAT drops below the threshold value Vth(bat)low (typically 2.5 V), the BLF flag (register Control_3) is set to indicate that the battery is low and that it must be replaced. Monitoring of the battery voltage also occurs during battery operation. An unreliable battery cannot prevent that the supply voltage drops below Vlow (typical 1.2 V) and with that the data integrity gets lost. When VBAT drops below the threshold value Vth(bat)low, the following sequence occurs (see Figure 8): 1. The battery low flag BLF is set logic 1. 2. An interrupt is generated if the control bit BLIE (register Control_3) is enabled (see Section 8.13.8). 3. The flag BLF remains logic 1 until the battery is replaced. BLF cannot be cleared by command. It is cleared automatically by the battery low detection circuit when the battery is replaced. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 23 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal VDD = VBBS internal power supply (= VBBS) VBAT Vth(bat)low (= 2.5 V) VBAT BLF INT 001aaj322 Fig 8. Battery low detection behavior with bit BLIE set logic 1 (enabled) 8.6.4 Extra power fail detection function The PCF2127AT has an extra power fail detection circuit which compares the voltage at the power fail input pin PFI to an internal reference voltage equal to 1.25 V. If VPFI < 1.25 V, the power fail output PFO is driven LOW. PFO is an open-drain, active LOW output which requires an external pull-up resistor in any application. The extra power fail detection function is typically used as a low voltage detection for the main power supply VDD (see Figure 9). VDD PCF2127AT R1 RPU 1.25 V (internal) 15 PFI 14 PFO R2 VSS 001aaj678 Fig 9. Typical application of the extra power fail detection function Usually R1 and R2 should be chosen such that the voltage at pin PFI • is higher than 1.25 V at start-up • falls below 1.25 V when VDD falls below a desired threshold voltage, Vth(uvp), defined by Equation 1: PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 24 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal R1 V th  uvp  =  ------ + 1  1.25V  R2  (1) Vth(uvp) value is usually set to a value that there are several milliseconds before VDD falls below the minimum operating voltage of the system, in order to allow the microcontroller to perform early backup operations. If the extra power fail detection function is not used, pin PFI must be connected to VSS and pin PFO must be left open circuit. 8.6.4.1 Extra power fail detection when the battery switch over function is enabled • When the power switches to the backup battery supply VBAT, the power fail comparator is switched off and the power fail output at pin PFO goes (or remains) LOW • When the power switches back to the main VDD, the pin PFO is not driven LOW anymore and is pulled HIGH through the external pull-up resistance for a certain time (trec = 15.63 ms to 31.25 ms) and then the power fail comparator is enabled again For illustration, see Figure 10 and Figure 11. VDD Vth(uvp) VBAT internal power supply (= VBBS) VBBS VBBS Vth(sw)bat (= 2.5 V) VDD (= 0 V) comparator enabled comparator disabled comparator enabled PF0 trec = [15.63 : 31.25] ms 001aaj319 Fig 10. PFO signal behavior when battery switch-over is enabled in standard mode and Vth(uvp) > (VBAT, Vth(sw)bat) PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 25 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal VDD VBBS VBAT VBBS internal power supply (= VBBS) Vth(uvp) Vth(sw)bat (= 2.5 V) VDD (= 0 V) comparator enabled comparator disabled comparator enabled PF0 trec 001aaj320 Fig 11. PFO signal behavior when battery switch-over is enabled in direct switching mode and Vth(uvp) < VBAT 8.6.4.2 Extra power fail detection when the battery switch-over function is disabled If the battery switch-over function is disabled and the power fail comparator is enabled, the power fail output at pin PFO depends only on the result of the comparison between VPFI and 1.25 V: • If VPFI > 1.25 V, PFO = HIGH (through the external pull-up resistor) • If VPFI < 1.25 V, PFO = LOW VDD Vth(uvp) Vth(sw)bat (= 2.5 V) comparator always enabled PF0 001aaj321 Fig 12. PFO signal behavior when battery switch-over is disabled PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 26 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.7 Oscillator stop detection function The PCF2127AT has an on-chip oscillator detection circuit which monitors the status of the oscillation: whenever the oscillation stops, a reset occurs and the oscillator stop flag OSF (in register Seconds) is set logic 1. • Power-on: a. The oscillator is not running, the chip is in reset (pin RST is LOW and flag OSF is logic 1). b. When the oscillator starts running and is stable after power-on, the chip exits from reset (pin RST is HIGH). c. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) by command. • Power supply failure: a. When the power supply of the chip (VBBS, see Section 8.6.2) drops below a certain value (Vlow), typically 1.2 V, the oscillator stops running and a reset occurs. b. When the power supply returns to normal operation, the oscillator starts running again, the chip exits from reset. c. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) by command. VDD VDD VBBS VBAT VBBS VBBS Vth(sw)bat (= 2.5 V) VBBS battery discharge internal power supply Vlow (= 1.2 V) VBAT VSS VSS (1) (2) OSF 001aaj409 (1) Theoretical state of the signals since there is no power. (2) The oscillator stop flag (OSF), set logic 1, indicates that the oscillation has stopped and a reset has occurred since the flag was last cleared (OSF set logic 0). In this case, the integrity of the clock information is not guaranteed. The OSF flag is cleared by command. Fig 13. Power failure event due to battery discharge: reset occurs PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 27 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.8 Reset function The PCF2127AT has a Power-On Reset (POR) and a Power-On Reset Override (PORO) function implemented. 8.8.1 Power-On Reset (POR) The POR is active whenever the oscillator is stopped. The oscillator is also considered to be stopped during the time between power-on and stable crystal resonance (see Figure 14). This time may be in the range of 200 ms to 2 s depending on temperature and supply voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF set logic 1). chip in reset chip not in reset VDD oscillation RST t 013aaa243 Fig 14. Dependency between POR and oscillator After POR, the following mode is entered: • • • • • • 32.768 kHz CLKOUT active Power-On Reset Override (PORO) available to be set 24 hour mode is selected Battery switch-over is enabled Battery low detection is enabled Extra power fail detection is enabled The register values after power-on are shown in Table 5. 8.8.2 Power-On Reset Override (PORO) The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and therefore speed up the on-board test of the device. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 28 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal OSCILLATOR SCL SDA/CE RESET OVERRIDE osc stopped 0 = stopped, 1 = running reset 0 = override inactive 1 = override active CLEAR POR_OVRD 0 = clear override mode 1 = override possible 001aaj324 Fig 15. Power-On Reset (POR) system The setting of the PORO mode requires that POR_OVRD in register Control_1 is set logic 1 and that the signals at the interface pins SDA/CE and SCL are toggled as illustrated in Figure 16. All timings shown are required minimum. power up 8 ms minimum 500 ns minimum 2000 ns SDA/CE SCL reset override 001aaj326 Fig 16. Power-On Reset Override (PORO) sequence, valid for both I2C-bus and SPI-bus Once the override mode is entered, the device is immediately released from the reset state and the set-up operation can commence. The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0 during normal operation has no effect except to prevent accidental entry into the PORO mode. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 29 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.9 Time and date function Most of these registers are coded in the Binary Coded Decimal (BCD) format. 8.9.1 Register Seconds Table 20. Seconds - seconds and clock integrity register (address 03h) bit description Bit Symbol Value Place value Description 7 OSF 0 - clock integrity is guaranteed 1[1] - clock integrity is not guaranteed: oscillator has stopped and chip reset has occurred since flag was last cleared 6 to 4 SECONDS 0 to 5 ten’s place 3 to 0 0 to 9 unit place [1] actual seconds coded in BCD format Start-up value. Table 21. Seconds coded in BCD format Seconds value in decimal Upper-digit (ten’s place) Digit (unit place) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0 0 0 0 0 0 0 01 0 0 0 0 0 0 1 02 0 0 0 0 0 1 0 : : : : : : : : 09 0 0 0 1 0 0 1 10 0 0 1 0 0 0 0 : : : : : : : : 58 1 0 1 1 0 0 0 59 1 0 1 1 0 0 1 8.9.2 Register Minutes Table 22. PCF2127AT Product data sheet Minutes - minutes register (address 04h) bit description Bit Symbol Value Place value Description 7 - - - unused 6 to 4 MINUTES 0 to 5 ten’s place actual minutes coded in BCD format 3 to 0 0 to 9 unit place All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 30 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.9.3 Register Hours Table 23. Bit Hours - hours register (address 05h) bit description Symbol Value Place value Description - - unused 0 - indicates AM 1 - indicates PM 0 to 1 ten’s place 0 to 9 unit place actual hours coded in BCD format when in 12 hour mode 5 to 4 HOURS 0 to 2 ten’s place 3 to 0 0 to 9 unit place 7 to 6 12 hour 5 mode[1] AMPM 4 HOURS 3 to 0 24 hour mode[1] [1] actual hours coded in BCD format when in 24 hour mode Hour mode is set by the bit 12_24 in register Control_1. 8.9.4 Register Days Table 24. Bit Days - days register (address 06h) bit description Symbol 7 to 6 5 to 4 DAYS[1] 3 to 0 [1] Value Place value Description - - unused 0 to 3 ten’s place actual day coded in BCD format 0 to 9 unit place If the year counter contains a value which is exactly divisible by 4, including the year 00, the RTC compensates for leap years by adding a 29th day to February. 8.9.5 Register Weekdays Table 25. Bit Weekdays - weekdays register (address 07h) bit description Symbol Value Description 7 to 3 - - unused 2 to 0 WEEKDAYS 0 to 6 actual weekday value, see Table 26 Although the association of the weekdays counter to the actual weekday is arbitrary, the PCF2127AT will assume that Sunday is 000 and Monday is 001 for the purposes of determining the increment for calendar weeks. Table 26. Weekday assignments Day[1] 2 1 0 Sunday 0 0 0 Monday 0 0 1 Tuesday 0 1 0 Wednesday 0 1 1 Thursday 1 0 0 Friday 1 0 1 Saturday 1 1 0 [1] PCF2127AT Product data sheet Bit Definition may be reassigned by the user. All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 31 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.9.6 Register Months Table 27. Bit Months - months register (address 08h) bit description Symbol 7 to 5 4 MONTHS 3 to 0 Table 28. Value Place value Description - - unused 0 to 1 ten’s place 0 to 9 unit place actual month coded in BCD format, see Table 28 Month assignments in BCD format Month Upper-digit (ten’s place) Digit (unit place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 January 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April 0 0 1 0 0 May 0 0 1 0 1 June 0 0 1 1 0 July 0 0 1 1 1 August 0 1 0 0 0 September 0 1 0 0 1 October 1 0 0 0 0 November 1 0 0 0 1 December 1 0 0 1 0 8.9.7 Register Years Table 29. Bit Years - years register (address 09h) bit description Symbol Value Place value Description 7 to 4 YEARS 0 to 9 ten’s place 3 to 0 0 to 9 unit place actual year coded in BCD format 8.9.8 Setting and reading the time Figure 17 shows the data flow and data dependencies starting from the 1 Hz clock tick. During read/write operations, the time counting circuits (memory locations 03h through 09h) are blocked. This prevents • Faulty reading of the clock and calendar during a carry condition • Incrementing the time registers during the read cycle PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 32 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 1 Hz tick SECONDS MINUTES 12_24 hour mode HOURS LEAP YEAR CALCULATION DAYS WEEKDAY MONTHS YEARS 001aaf901 Fig 17. Data flow of the time function After this read/write access is completed, the time circuit is released again. Any pending request to increment the time counters that occurred during the read/write access is serviced. A maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see Figure 18). t1 4096 1⁄ 8192 1⁄ 4096 64 1⁄ 128 1⁄ 64 1 1⁄ 64 1⁄ 64 1⁄ 60 1⁄ 64 1⁄ 64 [1] n = loaded countdown value. Timer stopped when n = 0. If the MSF or CDTF flag (register Control_2) is cleared before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately when it is serviced, that is, the system does not have to wait for the completion of the pulse before continuing, see Figure 28 and Figure 29. Instructions for clearing bit MSF and bit CDTF can be found in Section 8.11.6. seconds counter 58 59 MSF INT (1) SCL 8th clock instruction CLEAR INSTRUCTION 001aaf908 (1) Indicates normal duration of INT pulse. The timing shown for clearing bit MSF is also valid for the non-pulsed interrupt mode, that is, when TI_TP is logic 0, where the INT pulse may be shortened by setting both bits MI and SI logic 0. Fig 28. Example of shortening the INT pulse by clearing the MSF flag PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 50 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal countdown counter 01 n CDTF INT (1) SCL 8th clock instruction CLEAR INSTRUCTION 001aaf909 (1) Indicates normal duration of INT pulse. The timing shown for clearing CDTF is also valid for the non-pulsed interrupt mode, that TI_TP is logic 0, where the INT pulse may be shortened by setting CDTIE logic 0. is, when Fig 29. Example of shortening the INT pulse by clearing the CDTF flag 8.13.4 Watchdog timer interrupts The generation of interrupts from the watchdog timer is controlled using the WD_CD[1:0] bits (register Watchdg_tim_ctl). The interrupt is generated as an active signal which follows the status of the watchdog timer flag WDTF (register Control_2). No pulse generation is possible for watchdog timer interrupts. The interrupt is cleared when the flag WDTF is reset. WDTF is a read only bit and cannot be cleared by command. Instructions for clearing it can be found in Section 8.11.6. 8.13.5 Alarm interrupts Generation of interrupts from the alarm function is controlled by the bit AIE (register Control_2). If AIE is enabled, the INT pin will follow the status of bit AF (register Control_2). Clearing AF will immediately clear INT. No pulse generation is possible for alarm interrupts. minute counter 44 minute alarm 45 45 AF INT SCL 8th clock instruction CLEAR INSTRUCTION 001aaf910 Example where only the minute alarm is used and no other interrupts are enabled. Fig 30. AF timing diagram PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 51 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.13.6 Timestamp interrupts Interrupt generation from the timestamp function is controlled using the TSIE bit (register Control_2). If TSIE is enabled, the INT pin follows the status of the flags TSFx. Clearing the flags TSFx immediately clears INT. No pulse generation is possible for timestamp interrupts. 8.13.7 Battery switch-over interrupts Generation of interrupts from the battery switch-over is controlled by the BIE bit (register Control_3). If BIE is enabled, the INT pin follows the status of bit BF in register Control_3 (see Table 53). Clearing BF immediately clears INT. No pulse generation is possible for battery switch-over interrupts. 8.13.8 Battery low detection interrupts Generation of interrupts from the battery low detection is controlled by the BLIE bit (register Control_3). If BLIE is enabled, the INT pin will follow the status of bit BLF (register Control_3). The interrupt is cleared when the battery is replaced (BLF is logic 0) or when bit BLIE is disabled (BLIE is logic 0). BLF is read only and therefore cannot be cleared by command. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 52 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.14 External clock test mode A test mode is available which allows on-board testing. In this mode, it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit EXT_TEST logic 1 (register Control_1). Then pin CLKOUT becomes an input. The test mode replaces the internal clock signal (64 Hz) with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT generate an increment of one second. The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a maximum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided down by a 26 divider chain called prescaler (see Table 56). The prescaler can be set into a known state by using bit STOP. When bit STOP is logic 1, the prescaler is reset to 0. STOP must be cleared before the prescaler can operate again. From a stop condition, the first 1 second increment will take place after 32 positive edges on pin CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment. Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assumption as to the state of the prescaler can be made. Operating example: 1. Set EXT_TEST test mode (register Control_1, EXT_TEST is logic 1). 2. Set bit STOP (register Control_1, STOP is logic 1). 3. Set time registers to desired value. 4. Clear STOP (register Control_1, STOP is logic 0). 5. Apply 32 clock pulses to CLKOUT. 6. Read time registers to see the first change. 7. Apply 64 clock pulses to CLKOUT. 8. Read time registers to see the second change. Repeat 7 and 8 for additional increments. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 53 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.15 STOP bit function The function of the STOP bit is to allow for accurate starting of the time circuits. STOP will cause the upper part of the prescaler (F9 to F14) to be held in reset and thus no 1 Hz ticks are generated. The time circuits can then be set and will not increment until the STOP bit is released. STOP will not affect the CLKOUT signal but the output of the prescaler in the range of 32 Hz to 1 Hz (see Figure 31). The lower stages of the prescaler, F0 to F8, are not reset and because the I2C-bus and the SPI-bus are asynchronous to the crystal oscillator, the accuracy of restarting the time circuits is between 0 and one 64 Hz cycle (0.484375 s and 0.500000 s), see Table 56 and Figure 32. Table 56. First increment of time circuits after stop release Bit STOP Prescaler bits[1] F0 to F8 - F9 to F14 1 Hz tick Time hh:mm:ss Comment 12:45:12 prescaler counting normally Clock is running normally 0 010000111-010100 STOP bit is activated by user. F0 to F8 are not reset and values cannot be predicted externally 1 xxxxxxxxx-000000 12:45:12 prescaler is reset; time circuits are frozen 08:00:00 prescaler is reset; time circuits are frozen 08:00:00 prescaler is now running New time is set by user 1 xxxxxxxxx-000000 STOP bit is released by user xxxxxxxxx-000000 0 xxxxxxxxx-100000 0 xxxxxxxxx-100000 0 xxxxxxxxx-110000 : : 0 111111111-111110 0 000000000-000001 08:00:01 0 100000000-000001 08:00:01 : : : 0 111111111-111111 08:00:01 0 000000000-000000 0 100000000-000000 : : : 0 111111111-111110 08:00:01 0 000000000-000001 08:00:02 0.484375 - 0.500000 s 0 08:00:00 08:00:00 08:00:00 : 1s 08:00:00 0 to 1 transition of F14 increments the time circuits 08:00:01 0 to 1 transition of F14 increments the time circuits 001aaj479 [1] F0 is clocked at 32.768 kHz. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 54 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal LOWER PRESCALER 16384 Hz 32768 Hz F0 8192 Hz F1 UPPER PRESCALER 128 Hz 4096 Hz F2 64 Hz F8 F9 F10 F13 F14 RES RES RES RES OSC 1 Hz tick stop 001aaj342 Fig 31. STOP bit functional diagram 64 Hz stop released 0 ms - 15.625 ms 001aaj343 Fig 32. STOP bit release timing PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 55 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 9. Interfaces The PCF2127AT has an I2C-bus or SPI-bus interface using the same pins. The selection is done by using the interface selection pin IFS (see Table 57). Table 57. Interface selection input pin IFS Pin Connection Bus interface Reference IFS VSS SPI-bus Section 9.1 BBS I2C-bus Section 9.2 VDD VDD SCL RPU RPU SDI SDO SCL CE SDA SCL SDI SDO SDA/CE IFS 1 20 2 19 3 18 4 17 5 6 VSS PCF2127AT SCL VDD SDI SDO BBS SDA/CE IFS 16 14 8 13 9 12 10 11 VSS VSS 001aaj679 2 19 3 18 4 17 5 16 PCF2127AT VDD BBS 15 7 14 8 13 9 12 10 11 VSS 001aaj680 To select the I2C-bus interface, pin IFS has to be connected to pin BBS. To select the SPI-bus interface, pin IFS has to be connected to pin VSS. a. SPI-bus interface selection 20 6 15 7 1 b. I2C-bus interface selection Fig 33. Interface selection PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 56 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 9.1 SPI-bus interface Data transfer to and from the device is made by a 3 line SPI-bus (see Table 58). The data lines for input and output are split. The data input and output line can be connected together to facilitate a bidirectional data bus (see Figure 34). The SPI-bus is initialized whenever the chip enable line pin SDA/CE is inactive. SDI SDI SDO SDO two wire mode single wire mode 001aai560 Fig 34. SDI, SDO configurations Table 58. Symbol SDA/CE SCL Serial interface Function Description chip enable input; active LOW [1] when HIGH, the interface is reset; input may be higher than VDD serial clock input when SDA/CE is HIGH, input may float; input may be higher than VDD SDI serial data input when SDA/CE is HIGH, input may float; input may be higher than VDD; input data is sampled on the rising edge of SCL SDO serial data output push-pull output; drives from VSS to VBBS; output data is changed on the falling edge of SCL [1] The chip enable must not be wired permanently LOW. 9.1.1 Data transmission The chip enable signal is used to identify the transmitted data. Each data transfer is a whole byte, with the Most Significant Bit (MSB) sent first. The transmission is controlled by the active LOW chip enable signal SDA/CE. The first byte transmitted is the command byte. Subsequent bytes will be either data to be written or data to be read (see Figure 35). data bus COMMAND DATA DATA DATA SDA/CE 013aaa311 Fig 35. Data transfer overview The command byte defines the address of the first register to be accessed and the read/write mode. The address counter will auto increment after every access and will reset to zero after the last valid register is accessed. The R/W bit defines if the following bytes will be read or write information. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 57 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal Table 59. Command byte definition Bit Symbol 7 R/W 6 to 5 Value Description data read or write selection SA 0 write data 1 read data 01 subaddress; other codes will cause the device to ignore data transfer 4 to 0 R/W b7 0 RA addr 03h SA b6 0 b5 1 00h to 1Dh register address b4 0 b3 0 b2 0 seconds data 45BCD b1 1 b0 1 b7 0 b6 1 b5 0 b4 0 b3 0 b2 1 minutes data 10BCD b1 0 b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 0 SCL SDI SDA/CE address counter xx 03 04 05 001aaj348 In this example, the Seconds register is set to 45 seconds and the Minutes register to 10 minutes. Fig 36. SPI-bus write example R/W b7 1 addr 08h SA b6 0 b5 1 b4 0 b3 1 b2 0 months data 11BCD b1 0 b0 0 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 years data 06BCD b1 0 b0 1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 1 b1 1 b0 0 SCL SDI SDO SDA/CE address counter xx 08 09 0A 001aaj349 In this example, the registers Months and Years are read. The pins SDI and SDO are not connected together. For this configuration, it is important that pin SDI is never left floating. It must always be driven either HIGH or LOW. If pin SDI is left open, high IDD currents may result. Fig 37. SPI-bus read example PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 58 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 9.2 I2C-bus interface The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines are connected to a positive supply by a pull-up resistor. Data transfer is initiated only when the bus is not busy. 9.2.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line remains stable during the HIGH period of the clock pulse as changes in the data line at this time are interpreted as control signals (see Figure 38). SDA SCL data line stable; data valid change of data allowed mbc621 Fig 38. Bit transfer 9.2.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as the START condition S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition P (see Figure 39). SDA SDA SCL SCL S P START condition STOP condition mbc622 Fig 39. Definition of START and STOP conditions Remark: For the PCF2127AT, a repeated START is not allowed. Therefore a STOP has to be released before the next START. 9.2.3 System configuration A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master; and the devices which are controlled by the master are the slaves. The PCF2127AT can act as a slave transmitter and a slave receiver. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 59 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal SDA SCL MASTER TRANSMITTER RECEIVER SLAVE TRANSMITTER RECEIVER SLAVE RECEIVER MASTER TRANSMITTER RECEIVER MASTER TRANSMITTER mba605 Fig 40. System configuration 9.2.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver which is addressed must generate an acknowledge after the reception of each byte. • Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be considered). • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Figure 41. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 8 9 S START condition clock pulse for acknowledgement mbc602 Fig 41. Acknowledgement on the I2C-bus PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 60 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 9.2.5 I2C-bus protocol After a start condition, a valid hardware address has to be sent to a PCF2127AT device. The appropriate I2C-bus slave address is 1010001. The entire I2C-bus slave address byte is shown in Table 60. I2C slave address byte Table 60. Slave address Bit 7 6 5 4 3 2 1 MSB 0 LSB 1 0 1 0 0 0 1 R/W The R/W bit defines the direction of the following single or multiple byte data transfer (read is logic 1, write is logic 0). For the format and the timing of the START condition (S), the STOP condition (P), and the acknowledge bit (A) refer to the I2C-bus specification Ref. 11 “UM10204” and the characteristics table (Table 65). In the write mode, a data transfer is terminated by sending either a STOP condition or the START condition of the next data transfer. acknowledge from PCF2127AT S 1 0 1 0 0 0 1 slave address 0 acknowledge from PCF2127AT acknowledge from PCF2127AT A A A register address 00h to 1Dh write bit 0 to n data bytes P/S START/ STOP 001aaj719 Fig 42. Bus protocol, writing to registers acknowledge from PCF2127AT S 1 0 1 0 0 0 1 slave address 0 acknowledge from PCF2127AT A A register address 00h to 1Dh write bit acknowledge from PCF2127AT S 1 0 1 0 0 slave address 0 1 1 A read bit DATA BYTE set register address P STOP acknowledge from master no acknowledge A A LAST DATA BYTE 0 to n data bytes P read register data 001aaj721 Fig 43. Bus protocol, reading from registers PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 61 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal acknowledge from PCF2127AT acknowledge from PCF2127AT S 1 0 1 0 0 0 1 slave address 0 A register address 1Ah write bit acknowledge from PCF2127AT acknowledge from PCF2127AT data byte 1Ah A data byte 1Bh 1 0 1 0 0 0 1 slave address 0 A set RAM address A acknowledge from PCF2127AT acknowledge from PCF2127AT P/S A register address 1Ch A RAM write command write bit acknowledge from PCF2127AT data byte (RAM address) A P 0 to n data bytes write data to RAM 001aaj720 Fig 44. Bus protocol, writing to RAM PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 62 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal acknowledge from PCF2127AT acknowledge from PCF2127AT S 1 0 1 0 0 0 1 slave address 0 A register address 1Ah write bit acknowledge from PCF2127AT acknowledge from PCF2127AT data byte 1Ah A data byte 1Bh 1 0 1 0 0 0 1 slave address 0 A register address 1Dh 1 0 1 0 0 0 slave address RAM read command A write bit acknowledge from master acknowledge from PCF2127AT P/S set RAM address A acknowledge from PCF2127AT acknowledge from PCF2127AT P/S A 1 1 A data byte 0 to n data bytes read bit A read data from RAM no acknowledge last data byte A P 001aaj722 Fig 45. Bus protocol, reading from RAM PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 63 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 10. Internal circuitry VDD SCL VBAT BBS SDI SDO INT SDA/CE RST IFS PFI TS CLKOUT PFO TEST VSS PCF2127AT 001aaj677 Fig 46. Device diode protection diagram of PCF2127AT 11. Safety notes CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices. Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or equivalent standards. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 64 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 12. Limiting values Table 61. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD Conditions Min Max Unit supply voltage 0.5 +6.5 V IDD supply current 50 +50 mA Vi input voltage 0.5 +6.5 V II input current 10 +10 mA VO output voltage 0.5 +6.5 V IO output current 10 +10 mA 10 +20 mA 0.5 +6.5 V at pin SDA/CE VBAT battery supply voltage Ptot total power dissipation - 300 mW HBM [1] - 3500 V CDM [2] - 1250 V latch-up current [3] - 200 mA Tstg storage temperature [4] 55 +85 C Tamb ambient temperature 40 +85 C VESD Ilu PCF2127AT Product data sheet electrostatic discharge voltage operating device [1] Pass level; Human Body Model (HBM) according to Ref. 7 “JESD22-A114”. [2] Pass level; Charged-Device Model (CDM), according to Ref. 8 “JESD22-C101”. [3] Pass level; latch-up testing according to Ref. 9 “JESD78” at maximum ambient temperature (Tamb(max)). [4] According to the store and transport requirements (see Ref. 12 “UM10569”) the devices have to be stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 65 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 13. Static characteristics Table 62. Static characteristics VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies [1] VDD supply voltage 1.8 - 4.2 V VBAT battery supply voltage 1.8 - 4.2 V VDD(cal) calibration supply voltage - 3.3 - V Vlow low voltage - 1.2 - V IDD supply current SPI-bus (fSCL = 6.5 MHz) - - 800 A I2C-bus - - 200 A interface active; supplied by VDD (fSCL = 400 kHz) Hz)[2]; interface inactive (fSCL = 0 TCR[1:0] = 00 (see Table 9 on page 13) PWRMNG[2:0] = 111 (see Table 18 on page 18); TSOFF = 1 (see Table 46 on page 44); COF[2:0] = 111 (see Table 11 on page 14) VDD = 2.0 V - 500 - nA VDD = 3.3 V - 700 1500 nA VDD = 4.2 V - 800 - nA PWRMNG[2:0] = 111 (see Table 18 on page 18); TSOFF = 1 (see Table 46 on page 44); COF[2:0] = 000 (see Table 11 on page 14) VDD = 2.0 V - 600 - nA VDD = 3.3 V - 850 - nA VDD = 4.2 V - 1050 - nA PWRMNG[2:0] = 000 (see Table 18 on page 18); TSOFF = 0 (see Table 46 on page 44); COF[2:0] = 111 (see Table 11 on page 14) VDD or VBAT = 2.0 V [3] - 1800 - nA VDD or VBAT = 3.3 V [3] - 2150 - nA VDD or VBAT = 4.2 V [3] - 2350 3500 nA PWRMNG[2:0] = 000 (see Table 18 on page 18); TSOFF = 0 (see Table 46 on page 44); COF[2:0] = 000 (see Table 11 on page 14) IL(bat) battery leakage current PCF2127AT Product data sheet VDD or VBAT = 2.0 V [3] - 1900 - nA VDD or VBAT = 3.3 V [3] - 2300 - nA VDD or VBAT = 4.2 V [3] - 2600 - nA - 50 100 nA VDD is active supply; VBAT = 3.0 V All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 66 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal Table 62. Static characteristics …continued VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Power management Vth(sw)bat battery switch threshold voltage - 2.5 - V Vth(bat)low low battery threshold voltage - 2.5 - V Vth(PFI) threshold voltage on pin PFI - 1.25 - V VI input voltage 0.5 - VDD + 0.5 V VIL LOW-level input voltage - - 0.25VDD V Tamb = 20 C to +85 C; VDD > 2.0 V - - 0.3VDD V 0.7VDD - - V VI = VDD or VSS - 0 - A 1 - +1 A - - 7 pF on pins CLKOUT, INT, RST, PFO, referring to external pull-up 0.5 - 5.5 V on pin SDO 0.5 - VBBS + 0.5 V 3 17 - mA 1.0 - - mA Inputs[4] VIH HIGH-level input voltage ILI input leakage current post ESD event [5] input capacitance Ci Outputs output voltage VO LOW-level output current IOL output sink current; VOL = 0.4 V on pin SDA/CE on all other outputs [6] IOH HIGH-level output current output source current; on pin SDO; VOH = 3.8 V; VDD = 4.2 V 1.0 - - mA ILO output leakage current VO = VDD or VSS - 0 - A 1 - +1 A post ESD event [1] For reliable oscillator start-up at power-on: VDD(po)min = VDD(min) + 0.3 V. [2] Timer source clock = 1⁄60 Hz, level of pins SDA/CE, SDI, and SCL is VDD or VSS. [3] When the device is supplied by the VBAT pin instead of the VDD pin, the current values for IBAT will be as specified for IDD under the same conditions. [4] The I2C-bus and the SPI-bus interface of PCF2127AT are 5 V tolerant. [5] Tested on sample basis. [6] For further information, see Figure 47. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 67 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 13.1 Current consumption characteristics, typical 001aal763 22 IOL (mA) 18 14 10 6 1.5 2.5 3.5 4.5 VDD (V) Typical value; VOL = 0.4 V. Fig 47. IOL on pin SDA/CE 001aaj432 2.0 IDD (μA) 1.6 1.2 VDD = 3 V VDD = 2 V 0.8 0.4 0 −40 −20 0 20 40 60 80 100 Temperature (°C) CLKOUT disabled; PWRMNG[2:0] = 111; TSOFF = 1; TS input floating. Fig 48. IDD as a function of temperature PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 68 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 001aaj433 2.0 IDD (μA) 1.6 1.2 CLKOUT enabled at 32 kHz 0.8 CLKOUT OFF 0.4 0 1.8 2.2 2.6 3.0 3.4 3.8 4.2 VDD (V) a. PWRMNG[2:0] = 111; TSOFF = 1; Tamb = 25 C; TS input floating 001aaj434 4.0 IDD (μA) 3.2 CLKOUT enabled at 32 kHz 2.4 CLKOUT OFF 1.6 0.8 0 1.8 2.2 2.6 3.0 3.4 3.8 4.2 VDD (V) b. PWRMNG[2:0] = 000; TSOFF = 0; Tamb = 25 C; TS input floating Fig 49. IDD as a function of VDD PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 69 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 13.2 Frequency characteristics Table 63. Frequency characteristics VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = +25 C, unless otherwise specified. Symbol Parameter Conditions Min Typ fo output frequency on pin CLKOUT; VDD or VBAT = 3.3 V; COF[2:0] = 000; AO[3:0] = 1000 - 32.768 - f/f frequency stability VDD or VBAT = 3.3 V [1] frequency variation with voltage Unit kHz Tamb = 15 C to +60 C [1][2] - 3 5 ppm Tamb = 25 C to 15 C and Tamb = +60 C to +65 C [1][2] - 5 10 ppm [3] - - 3 ppm - 1 - ppm/V fxtal/fxtal relative crystal frequency variation crystal aging, first year; VDD or VBAT = 3.3 V f/V Max on pin CLKOUT 1 ppm corresponds to a time deviation of 0.0864 seconds per day. [2] Only valid if CLKOUT frequencies are not equal to 32.768 kHz or if CLKOUT is disabled. [3] Not production tested. Effects of reflow soldering are not included (see Ref. 3 “AN10857”). 013aaa593 40 Frequency stability (ppm) ± 5 ppm ± 3 ppm ± 5 ppm 0 (1) -40 (2) -80 -40 -20 0 20 40 60 80 100 Temperature (°C) (1) Typical temperature compensated frequency response. (2) Uncompensated typical tuning-fork crystal frequency. Fig 50. Typical characteristic of frequency with respect to temperature PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 70 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 14. Dynamic characteristics 14.1 SPI-bus timing characteristics Table 64. SPI-bus characteristics VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = 40 C to +85 C, unless otherwise specified. All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD. Symbol Parameter Conditions VDD = 1.8 V VDD = 4.2 V Min Max Min Max - 2.0 - 6.5 Unit Pin SCL fclk(SCL) SCL clock frequency SCL time tSCL tclk(H) tclk(L) clock HIGH time clock LOW time register read/write access MHz RAM write access - 2.0 - 6.5 MHz RAM read access - 1.11 - 6.25 MHz register read/write access 800 - 140 - ns RAM write access 800 - 140 - ns RAM read access 900 - 160 - ns register read/write access 100 - 70 - ns RAM write access 100 - 70 - ns RAM read access 450 - 80 - ns register read/write access 400 - 70 - ns RAM write access 400 - 70 - ns RAM read access 450 - 80 - ns tr rise time for SCL signal - 100 - 100 ns tf fall time for SCL signal - 100 - 100 ns Pin SDA/CE tsu(CE_N) CE_N set-up time 60 - 30 - ns th(CE_N) CE_N hold time 40 - 25 - ns trec(CE_N) CE_N recovery time 100 - 30 - ns tw(CE_N) CE_N pulse width - 0.99 - 0.99 s Pin SDI tsu set-up time set-up time for SDI data 70 - 20 - ns th hold time hold time for SDI data 70 - 20 - ns SDO read delay time CL = 50 pF register read access - 225 - 55 ns RAM read access Pin SDO td(R)SDO - 410 - 55 ns tdis(SDO) SDO disable time [1] - 90 - 25 ns tt(SDI-SDO) transition time from SDI to SDO to avoid bus conflict 0 - 0 - ns [1] No load value; bus will be held up by bus capacitance; use RC time constant with application values. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 71 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal tw(CE_N) CE tsu(CE_N) trec(CE_N) tr tf tclk(SCL) th(CE_N) 80% SCL 20% tclk(L) tclk(H) WRITE tsu th SDI SDO R/W SA2 RA0 b6 b0 b7 b6 b0 high-Z READ SDI b7 tt(SDI-SDO) td(R)SDO SDO high-Z b7 tdis(SDO) b6 b0 013aaa152 Fig 51. SPI-bus timing PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 72 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 14.2 I2C interface timing characteristics Table 65. I2C-bus characteristics All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to 30 % and 70 % with an input voltage swing of VSS to VDD (see Figure 52). Symbol Parameter Standard mode Fast-mode (Fm) Unit Min Max Min Max 0 100 0 400 kHz Pin SCL [1] fSCL SCL clock frequency tLOW LOW period of the SCL clock 4.7 - 1.3 - s tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s Pin SDA/CE tSU;DAT data set-up time 250 - 100 - ns tHD;DAT data hold time 0 - 0 - ns Pins SCL and SDA/CE tBUF bus free time between a STOP and START condition 4.7 - 1.3 - s tSU;STO set-up time for STOP condition 4.0 - 0.6 - s tHD;STA hold time (repeated) START condition 4.0 - 0.6 - s tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - s tr rise time of both SDA and SCL signals [2][3][4] - 1000 20 + 0.1Cb 300 ns tf fall time of both SDA and SCL signals [2][3][4] - 300 20 + 0.1Cb 300 ns tVD;ACK data valid acknowledge time [5] 0.1 3.45 0.1 0.9 s tVD;DAT data valid time [6] 300 - 75 - ns pulse width of spikes that must be suppressed by the input filter [7] - 50 - 50 ns tSP PCF2127AT Product data sheet [1] The minimum SCL clock frequency is limited by the bus time-out feature which resets the serial bus interface if either the SDA or SCL is held LOW for a minimum of 25 ms. The bus time-out feature must be disabled for DC operation. [2] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. [3] Cb is the total capacitance of one bus line in pF. [4] The maximum tf for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, tf is 250 ns. This allows series protection resistors to be connected between the SDA/CE pin, the SCL pin, and the SDA/SCL bus lines without exceeding the maximum tf. [5] tVD;ACK is the time of the acknowledgement signal from SCL LOW to SDA (out) LOW. [6] tVD;DAT is the minimum time for valid SDA (out) data following SCL LOW. [7] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns. All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 73 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal PROTOCOL tSU;STA BIT 6 (A6) BIT 7 MSB (A7) START CONDITION (S) tLOW tHIGH BIT 0 LSB (R/W) ACKNOWLEDGE (A) STOP CONDITION (P) 1 / fSCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tSU;STO mbd820 Fig 52. I2C-bus timing diagram; rise and fall times refer to 30 % and 70 % 15. Application information For information about application configuration, see Ref. 3 “AN10857”. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 74 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 16. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 53. Package outline SOT163-1 (SO20) PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 75 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 17. Packing information 17.1 Carrier tape information TOP VIEW Ø D0 P0 W B0 P1 A0 K0 Ø D1 direction of feed Original dimensions are in mm. Figure not drawn to scale. 013aaa699 Fig 54. Tape and reel details for PCF2127AT Table 66. Carrier tape dimensions of PCF2127AT Symbol Description Value Unit A0 pocket width in x direction 10.8 to 10.9 mm B0 pocket width in y direction 13.3 to 13.4 mm K0 pocket depth 2.70 to 2.85 mm P1 pocket hole pitch 12.0 mm D1 pocket hole diameter 1.5 to 2.05 mm Compartments Overall dimensions W tape width 24.0 mm D0 sprocket hole diameter 1.5 to 1.55 mm P0 sprocket hole pitch 4.0 mm 18. Soldering For information about soldering, see Ref. 3 “AN10857”. PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 76 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 19. Footprint information 13.40 0.60 (20×) 1.50 8.00 11.00 11.40 1.27 (18×) solder lands occupied area placement accuracy ± 0.25 Dimensions in mm sot163-1_fr Fig 55. Footprint information for reflow soldering of SO20 package PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 77 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 20. Abbreviations Table 67. PCF2127AT Product data sheet Abbreviations Acronym Description AM Ante Meridiem BCD Binary Coded Decimal CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DC Direct Current GPS Global Positioning System HBM Human Body Model I2C Inter-Integrated Circuit IC Integrated Circuit LSB Least Significant Bit MCU Microcontroller Unit MSB Most Significant Bit PM Post Meridiem POR Power-On Reset PORO Power-On Reset Override PPM Parts Per Million RAM Random Access Memory RC Resistance-Capacitance RTC Real Time Clock SCL Serial CLock line SDA Serial DAta line SPI Serial Peripheral Interface SRAM Static Random Access Memory TCXO Temperature Compensated Xtal Oscillator Xtal crystal All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 78 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 21. References [1] AN10365 — Surface mount reflow soldering description [2] AN10853 — Handling precautions of ESD sensitive devices [3] AN10857 — Application and soldering information for PCF2127A and PCF2129A TCXO RTC [4] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [6] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [7] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [8] JESD22-C101 — Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components [9] JESD78 — IC Latch-Up Test [10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [11] UM10204 — I2C-bus specification and user manual [12] UM10569 — Store and transport requirements PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 79 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 22. Revision history Table 68. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF2127AT v.6 20130711 Product data sheet - PCF2127AT v.5 Modifications: • Adjusted rise and fall time values of the SPI-bus in Table 64 PCF2127AT v.5 20130128 Product data sheet - PCF2127AT v.4 PCF2127AT v.4 20121207 Product data sheet - PCF2127AT v.3 PCF2127AT v.3 20121004 Product data sheet - PCF2127A v.2 PCF2127A v.2 20100507 Product data sheet - PCF2127A v.1 PCF2127A v.1 20100121 Product data sheet - - PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 80 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 23. Legal information 23.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 23.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 23.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PCF2127AT Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 81 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 23.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 24. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 82 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 25. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2 Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin description of SO20 (PCF2127AT) . . . . . . .4 Register overview . . . . . . . . . . . . . . . . . . . . . . .8 Control_1 - control and status register 1 (address 00h) bit description . . . . . . . . . . . . . .10 Control_2 - control and status register 2 (address 01h) bit description . . . . . . . . . . . . . . 11 Control_3 - control and status register 3 (address 02h) bit description . . . . . . . . . . . . . .12 CLKOUT_ctl - CLKOUT control register (address 0Fh) bit description . . . . . . . . . . . . . .13 Temperature measurement period . . . . . . . . . .13 CLKOUT frequency selection . . . . . . . . . . . . . .14 Aging_offset - crystal aging offset register (address 19h) bit description . . . . . . . . . . . . . .15 Frequency correction at 25 °C, typical . . . . . . .15 RAM_addr_MSB - RAM address MSB register (address 1Ah) bit description . . . . . . . . . . . . . .16 RAM_addr_LSB - RAM address LSB register (address 1Bh) bit description . . . . . . . . . . . . . .16 RAM_wrt_cmd - RAM write command register (address 1Ch) bit description . . . . . . . . . . . . . .16 RAM_rd_cmd - RAM read command register (address 1Dh) bit description . . . . . . . . . . . . . .16 Power management control bit description . . .18 Output pin BBS. . . . . . . . . . . . . . . . . . . . . . . . .22 Seconds - seconds and clock integrity register (address 03h) bit description . . . . . . . .30 Seconds coded in BCD format . . . . . . . . . . . .30 Minutes - minutes register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Hours - hours register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Days - days register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Weekdays - weekdays register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . .31 Weekday assignments . . . . . . . . . . . . . . . . . . .31 Months - months register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Month assignments in BCD format . . . . . . . . . .32 Years - years register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Second_alarm - second alarm register (address 0Ah) bit description . . . . . . . . . . . . . .34 Minute_alarm - minute alarm register (address 0Bh) bit description . . . . . . . . . . . . . .35 Hour_alarm - hour alarm register (address 0Ch) bit description . . . . . . . . . . . . . .35 Day_alarm - day alarm register (address 0Dh) bit description . . . . . . . . . . . . . .35 Weekday_alarm - weekday alarm register (address 0Eh) bit description . . . . . . . . . . . . . .36 Watchdg_tim_ctl - watchdog timer control PCF2127AT Product data sheet register (address 10h) bit description . . . . . . . 37 Table 36. Watchdg_tim_val - watchdog timer value register (address 11h) bit description . . . . . . . . 38 Table 37. Programmable watchdog or countdown timer . 38 Table 38. Specification of tw(rst) . . . . . . . . . . . . . . . . . . . . 40 Table 39. First period delay for timer counter . . . . . . . . . 41 Table 40. Flag location in register Control_2 . . . . . . . . . . 41 Table 41. Example values in register Control_2 . . . . . . . 42 Table 42. Example to clear only CDTF (bit 3) . . . . . . . . . 42 Table 43. Example to clear only AF (bit 4). . . . . . . . . . . . 42 Table 44. Example to clear only MSF (bit 7) . . . . . . . . . . 42 Table 45. Example to clear both CDTF and MSF . . . . . . 42 Table 46. Timestp_ctl - timestamp control register (address 12h) bit description . . . . . . . . . . . . . . 44 Table 47. Sec_timestp - second timestamp register (address 13h) bit description . . . . . . . . . . . . . . 44 Table 48. Min_timestp - minute timestamp register (address 14h) bit description . . . . . . . . . . . . . . 44 Table 49. Hour_timestp - hour timestamp register (address 15h) bit description . . . . . . . . . . . . . . 45 Table 50. Day_timestp - day timestamp register (address 16h) bit description . . . . . . . . . . . . . . 45 Table 51. Mon_timestp - month timestamp register (address 17h) bit description . . . . . . . . . . . . . . 45 Table 52. Year_timestp - year timestamp register (address 18h) bit description . . . . . . . . . . . . . . 45 Table 53. Battery switch-over and timestamp . . . . . . . . . 46 Table 54. Effect of bits MI and SI on pin INT and bit MSF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 55. INT operation (bit TI_TP = 1) . . . . . . . . . . . . . . 50 Table 56. First increment of time circuits after stop release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 57. Interface selection input pin IFS. . . . . . . . . . . . 56 Table 58. Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 59. Command byte definition . . . . . . . . . . . . . . . . . 58 Table 60. I2C slave address byte . . . . . . . . . . . . . . . . . . . 61 Table 61. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 62. Static characteristics . . . . . . . . . . . . . . . . . . . . 66 Table 63. Frequency characteristics . . . . . . . . . . . . . . . . 70 Table 64. SPI-bus characteristics . . . . . . . . . . . . . . . . . . 71 Table 65. I2C-bus characteristics . . . . . . . . . . . . . . . . . . . 73 Table 66. Carrier tape dimensions of PCF2127AT . . . . . 76 Table 67. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 68. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 80 All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 83 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 26. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. Fig 29. Fig 30. Fig 31. Fig 32. Fig 33. Fig 34. Fig 35. Fig 36. Block diagram of PCF2127AT . . . . . . . . . . . . . . . .3 Pin configuration for SO20 (PCF2127AT) . . . . . . .4 Handling address registers . . . . . . . . . . . . . . . . . .6 Battery switch-over behavior in standard mode with bit BIE set logic 1 (enabled) . . . . . . . . . . . . .20 Battery switch-over behavior in direct switching mode with bit BIE set logic 1 (enabled) . . . . . . . .21 Battery switch-over circuit, simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Typical driving capability of VBBS: (VBBS - VDD) with respect to the output load current IBBS . . . . .23 Battery low detection behavior with bit BLIE set logic 1 (enabled) . . . . . . . . . . . . . . . . . . . . . . . . .24 Typical application of the extra power fail detection function. . . . . . . . . . . . . . . . . . . . . . . . .24 PFO signal behavior when battery switch-over is enabled in standard mode and Vth(uvp) > (VBAT, Vth(sw)bat) . . . . . . . . . . . . . . . . . . .25 PFO signal behavior when battery switch-over is enabled in direct switching mode and Vth(uvp) < VBAT. . . . . . . . . . . . . . . . . . . . . . . . . . . .26 PFO signal behavior when battery switch-over is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Power failure event due to battery discharge: reset occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Dependency between POR and oscillator . . . . . .28 Power-On Reset (POR) system. . . . . . . . . . . . . .29 Power-On Reset Override (PORO) sequence, valid for both I2C-bus and SPI-bus . . . . . . . . . . .29 Data flow of the time function. . . . . . . . . . . . . . . .33 Access time for read/write operations . . . . . . . . .33 Alarm function block diagram. . . . . . . . . . . . . . . .34 Alarm flag timing diagram . . . . . . . . . . . . . . . . . .36 WD_CD[1:0] = 10: watchdog activates an interrupt when timed out . . . . . . . . . . . . . . . . . . .39 WD_CD[1:0] = 11: watchdog activates a reset pulse when timed out . . . . . . . . . . . . . . . . . . . . . .39 General countdown timer behavior . . . . . . . . . . .40 Timestamp detection with two push-buttons on the TS pin (for example, for tamper detection)43 Interrupt block diagram . . . . . . . . . . . . . . . . . . . .47 INT example for SI and MI when TI_TP is logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 INT example for SI and MI when TI_TP is logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Example of shortening the INT pulse by clearing the MSF flag . . . . . . . . . . . . . . . . . . . . . .50 Example of shortening the INT pulse by clearing the CDTF flag . . . . . . . . . . . . . . . . . . . . .51 AF timing diagram . . . . . . . . . . . . . . . . . . . . . . . .51 STOP bit functional diagram . . . . . . . . . . . . . . . .55 STOP bit release timing . . . . . . . . . . . . . . . . . . . .55 Interface selection . . . . . . . . . . . . . . . . . . . . . . . .56 SDI, SDO configurations . . . . . . . . . . . . . . . . . . .57 Data transfer overview . . . . . . . . . . . . . . . . . . . . .57 SPI-bus write example . . . . . . . . . . . . . . . . . . . . .58 PCF2127AT Product data sheet Fig 37. Fig 38. Fig 39. Fig 40. Fig 41. Fig 42. Fig 43. Fig 44. Fig 45. Fig 46. Fig 47. Fig 48. Fig 49. Fig 50. Fig 51. Fig 52. Fig 53. Fig 54. Fig 55. SPI-bus read example. . . . . . . . . . . . . . . . . . . . . 58 Bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Definition of START and STOP conditions . . . . . 59 System configuration. . . . . . . . . . . . . . . . . . . . . . 60 Acknowledgement on the I2C-bus. . . . . . . . . . . . 60 Bus protocol, writing to registers . . . . . . . . . . . . . 61 Bus protocol, reading from registers . . . . . . . . . . 61 Bus protocol, writing to RAM. . . . . . . . . . . . . . . . 62 Bus protocol, reading from RAM . . . . . . . . . . . . . 63 Device diode protection diagram of PCF2127AT 64 IOL on pin SDA/CE . . . . . . . . . . . . . . . . . . . . . . . 68 IDD as a function of temperature . . . . . . . . . . . . . 68 IDD as a function of VDD . . . . . . . . . . . . . . . . . . . . 69 Typical characteristic of frequency with respect to temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SPI-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 72 I2C-bus timing diagram; rise and fall times refer to 30 % and 70 % . . . . . . . . . . . . . . . . . . . . . . . . 74 Package outline SOT163-1 (SO20) . . . . . . . . . . 75 Tape and reel details for PCF2127AT . . . . . . . . . 76 Footprint information for reflow soldering of SO20 package . . . . . . . . . . . . . . . . . . . . . . . . . . 77 All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 84 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 27. Contents 1 2 3 4 4.1 5 6 7 7.1 7.2 8 8.1 8.2 8.2.1 8.2.2 8.2.3 8.3 8.3.1 8.3.1.1 8.3.2 8.4 8.4.1 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.5.1 8.5.5.2 8.6 8.6.1 8.6.1.1 8.6.1.2 8.6.1.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 6 Register overview . . . . . . . . . . . . . . . . . . . . . . . 6 Control registers . . . . . . . . . . . . . . . . . . . . . . . 10 Register Control_1 . . . . . . . . . . . . . . . . . . . . . 10 Register Control_2 . . . . . . . . . . . . . . . . . . . . . 11 Register Control_3 . . . . . . . . . . . . . . . . . . . . . 12 Register CLKOUT_ctl . . . . . . . . . . . . . . . . . . . 13 Temperature compensated crystal oscillator . 13 Temperature measurement . . . . . . . . . . . . . . 13 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Register Aging_offset . . . . . . . . . . . . . . . . . . . 15 Crystal aging correction . . . . . . . . . . . . . . . . . 15 General purpose 512 bytes static RAM . . . . . 16 Register RAM_addr_MSB . . . . . . . . . . . . . . . 16 Register RAM_addr_LSB . . . . . . . . . . . . . . . . 16 Register RAM_wrt_cmd . . . . . . . . . . . . . . . . . 16 Register RAM_rd_cmd . . . . . . . . . . . . . . . . . . 16 Operation examples . . . . . . . . . . . . . . . . . . . . 17 Writing to the RAM . . . . . . . . . . . . . . . . . . . . . 17 Reading from the RAM . . . . . . . . . . . . . . . . . . 17 Power management functions . . . . . . . . . . . . 18 Battery switch-over function . . . . . . . . . . . . . . 19 Standard mode . . . . . . . . . . . . . . . . . . . . . . . . 20 Direct switching mode . . . . . . . . . . . . . . . . . . 21 Battery switch-over disabled: only one power supply (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.6.1.4 Battery switch-over architecture . . . . . . . . . . . 22 8.6.2 Battery backup supply . . . . . . . . . . . . . . . . . . 22 8.6.3 Battery low detection function. . . . . . . . . . . . . 23 8.6.4 Extra power fail detection function . . . . . . . . . 24 8.6.4.1 Extra power fail detection when the battery switch over function is enabled. . . . . . . . . . . . 25 8.6.4.2 Extra power fail detection when the battery switch-over function is disabled . . . . . . . . . . . 26 8.7 Oscillator stop detection function . . . . . . . . . . 27 8.8 Reset function . . . . . . . . . . . . . . . . . . . . . . . . 28 8.8.1 8.8.2 8.9 8.9.1 8.9.2 8.9.3 8.9.4 8.9.5 8.9.6 8.9.7 8.9.8 8.10 8.10.1 8.10.2 8.10.3 8.10.4 8.10.5 8.10.6 8.11 8.11.1 8.11.2 8.11.3 8.11.4 8.11.5 8.11.6 8.12 8.12.1 8.12.2 8.12.3 8.12.3.1 8.12.3.2 8.12.3.3 8.12.3.4 8.12.3.5 8.12.3.6 8.12.3.7 8.12.4 8.13 8.13.1 8.13.2 8.13.3 8.13.4 8.13.5 8.13.6 8.13.7 8.13.8 Power-On Reset (POR) . . . . . . . . . . . . . . . . . Power-On Reset Override (PORO) . . . . . . . . Time and date function. . . . . . . . . . . . . . . . . . Register Seconds. . . . . . . . . . . . . . . . . . . . . . Register Minutes . . . . . . . . . . . . . . . . . . . . . . Register Hours . . . . . . . . . . . . . . . . . . . . . . . . Register Days . . . . . . . . . . . . . . . . . . . . . . . . Register Weekdays . . . . . . . . . . . . . . . . . . . . Register Months. . . . . . . . . . . . . . . . . . . . . . . Register Years . . . . . . . . . . . . . . . . . . . . . . . . Setting and reading the time . . . . . . . . . . . . . Alarm function . . . . . . . . . . . . . . . . . . . . . . . . Register Second_alarm . . . . . . . . . . . . . . . . . Register Minute_alarm. . . . . . . . . . . . . . . . . . Register Hour_alarm . . . . . . . . . . . . . . . . . . . Register Day_alarm . . . . . . . . . . . . . . . . . . . . Register Weekday_alarm. . . . . . . . . . . . . . . . Alarm flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer functions. . . . . . . . . . . . . . . . . . . . . . . . Register Watchdg_tim_ctl . . . . . . . . . . . . . . . Register Watchdg_tim_val . . . . . . . . . . . . . . . Watchdog timer function . . . . . . . . . . . . . . . . Countdown timer function . . . . . . . . . . . . . . . Pre-defined timers: second and minute interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clearing flags . . . . . . . . . . . . . . . . . . . . . . . . . Timestamp function . . . . . . . . . . . . . . . . . . . . Timestamp flag. . . . . . . . . . . . . . . . . . . . . . . . Timestamp mode . . . . . . . . . . . . . . . . . . . . . . Timestamp registers. . . . . . . . . . . . . . . . . . . . Register Timestp_ctl . . . . . . . . . . . . . . . . . . . Register Sec_timestp. . . . . . . . . . . . . . . . . . . Register Min_timestp . . . . . . . . . . . . . . . . . . . Register Hour_timestp . . . . . . . . . . . . . . . . . . Register Day_timestp. . . . . . . . . . . . . . . . . . . Register Mon_timestp . . . . . . . . . . . . . . . . . . Register Year_timestp . . . . . . . . . . . . . . . . . . Dependency between Battery switch-over and timestamp . . . . . . . . . . . . . . . . . . . . . . . . Interrupt output, INT. . . . . . . . . . . . . . . . . . . . Minute and second interrupts. . . . . . . . . . . . . Countdown timer interrupts . . . . . . . . . . . . . . INT pulse shortening . . . . . . . . . . . . . . . . . . . Watchdog timer interrupts . . . . . . . . . . . . . . . Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . Timestamp interrupts . . . . . . . . . . . . . . . . . . . Battery switch-over interrupts . . . . . . . . . . . . Battery low detection interrupts . . . . . . . . . . . 28 28 30 30 30 31 31 31 32 32 32 34 34 35 35 35 36 36 37 37 38 38 40 41 41 43 43 44 44 44 44 44 45 45 45 45 46 47 48 49 49 51 51 52 52 52 continued >> PCF2127AT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 11 July 2013 © NXP B.V. 2013. All rights reserved. 85 of 86 PCF2127AT NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.14 8.15 9 9.1 9.1.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 10 11 12 13 13.1 13.2 14 14.1 14.2 15 16 17 17.1 18 19 20 21 22 23 23.1 23.2 23.3 23.4 24 25 26 27 External clock test mode . . . . . . . . . . . . . . . . STOP bit function . . . . . . . . . . . . . . . . . . . . . . Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI-bus interface . . . . . . . . . . . . . . . . . . . . . . Data transmission . . . . . . . . . . . . . . . . . . . . . . I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . START and STOP conditions . . . . . . . . . . . . . System configuration . . . . . . . . . . . . . . . . . . . Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . Safety notes . . . . . . . . . . . . . . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics. . . . . . . . . . . . . . . . . . . . Current consumption characteristics, typical . Frequency characteristics. . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . SPI-bus timing characteristics . . . . . . . . . . . . I2C interface timing characteristics . . . . . . . . . Application information. . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Carrier tape information . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Footprint information . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 54 56 57 57 59 59 59 59 60 61 64 64 65 66 68 70 71 71 73 74 75 76 76 76 77 78 79 80 81 81 81 81 82 82 83 84 85 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 July 2013 Document identifier: PCF2127AT