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PCF2127AT/2

PCF2127AT/2

  • 厂商:

    NXP(恩智浦)

  • 封装:

    -

  • 描述:

    PCF2127AT/2

  • 数据手册
  • 价格&库存
PCF2127AT/2 数据手册
PCF2127 Accurate RTC with integrated quartz crystal for industrial applications Rev. 8 — 19 December 2014 Product data sheet 1. General description The PCF2127 is a CMOS1 Real Time Clock (RTC) and calendar with an integrated Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal optimized for very high accuracy and very low power consumption. The PCF2127 has 512 bytes of general-purpose static RAM, a selectable I2C-bus or SPI-bus, a backup battery switch-over circuit, a programmable watchdog function, a timestamp function, and many other features. For a selection of NXP Real-Time Clocks, see Table 94 on page 89 2. Features and benefits                  1. UL Recognized Component Operating temperature range from 40 C to +85 C Temperature Compensated Crystal Oscillator (TCXO) with integrated capacitors Typical accuracy:  PCF2127AT: 3 ppm from 15 C to +60 C  PCF2127T: 3 ppm from 30 C to +80 C Integration of a 32.768 kHz quartz crystal and oscillator in the same package Provides year, month, day, weekday, hours, minutes, seconds, and leap year correction 512 bytes of general-purpose static RAM Timestamp function  with interrupt capability  detection of two different events on one multilevel input pin (for example, for tamper detection) Two line bidirectional 400 kHz Fast-mode I2C-bus interface 3 line SPI-bus with separate data input and output (maximum speed 6.5 Mbit/s) Battery backup input pin and switch-over circuitry Battery backed output voltage Battery low detection function Extra power fail detection function with input and output pins Power-On Reset Override (PORO) Oscillator stop detection function Interrupt output (open-drain) The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21. PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications        Programmable 1 second or 1 minute interrupt Programmable watchdog timer with interrupt Programmable alarm function with interrupt capability Programmable square wave output pin Programmable countdown timer with interrupt Clock operating voltage: 1.8 V to 4.2 V Low supply current: typical 0.70 A at VDD = 3.3 V 3. Applications       Electronic metering for electricity, water, and gas Precision timekeeping Access to accurate time of the day GPS equipment to reduce time to first fix Applications that require an accurate process timing Products with long automated unattended operation time 4. Ordering information Table 1. Ordering information Type number Package Name Description Version PCF2127AT SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 PCF2127T SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 4.1 Ordering options Table 2. Ordering options Product type number Orderable part number Sales item (12NC) Delivery form IC revision PCF2127AT/2 PCF2127AT/2Y 935299867518 tape and reel, 13 inch, dry pack 2 PCF2127T/2 PCF2127T/2Y 935299866518 tape and reel, 13 inch, dry pack 2 5. Marking Table 3. PCF2127 Product data sheet Marking codes Product type number Marking code PCF2127AT/2 PCF2127AT PCF2127T/2 PCF2127T All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 2 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 6. Block diagram ,17 7&;2 26&, &/.287 ',9,'(5 $1' 7,0(5 N+] 26&2 3), 3)2 9 LQWHUQDO 9'' 9%$7 966 %$77(5 Vth(sw)bat: Voper(int) is at VDD potential. If VDD < VBAT AND VDD < Vth(sw)bat: Voper(int) is at VBAT potential. EDFNXSEDWWHU\RSHUDWLRQ 9'' 9RSHU LQW 9%$7 9RSHU LQW LQWHUQDORSHUDWLQJYROWDJH 9RSHU LQW 9WK VZ EDW 9 9'' 9 %) ,17 FOHDUHGYLDLQWHUIDFH DDM Vth(sw)bat is the battery switch threshold voltage. Typical value is 2.5 V. In standard mode, the battery switch-over works only for VDD > 2.5 V. VDD may be lower than VBAT (for example VDD = 3 V, VBAT = 4.1 V). Fig 6. PCF2127 Product data sheet Battery switch-over behavior in standard mode with bit BIE set logic 1 (enabled) All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 20 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 8.6.1.2 Direct switching mode If VDD > VBAT: Voper(int) is at VDD potential. If VDD < VBAT: Voper(int) is at VBAT potential. The direct switching mode is useful in systems where VDD is always higher than VBAT. This mode is not recommended if the VDD and VBAT values are similar (for example, VDD = 3.3 V, VBAT  3.0 V). In direct switching mode, the power consumption is reduced compared to the standard mode because the monitoring of VDD and Vth(sw)bat is not performed. EDFNXSEDWWHU\RSHUDWLRQ 9'' 9RSHU LQW 9%$7 9RSHU LQW LQWHUQDORSHUDWLQJYROWDJH 9RSHU LQW 9WK VZ EDW 9 9'' 9 %) ,17 FOHDUHGYLDLQWHUIDFH DDM Fig 7. 8.6.1.3 Battery switch-over behavior in direct switching mode with bit BIE set logic 1 (enabled) Battery switch-over disabled: only one power supply (VDD) When the battery switch-over function is disabled: • • • • PCF2127 Product data sheet The power supply is applied on the VDD pin The VBAT pin must be connected to ground Voper(int) is at VDD potential The battery flag (BF) is always logic 0 All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 21 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 8.6.1.4 Battery switch-over architecture The architecture of the battery switch-over circuit is shown in Figure 8. FRPSDUDWRUV ORJLF VZLWFKHV 9'' 9WK VZ EDW 9'' 9RSHU LQW /2*,& 9WK VZ EDW 9%$7 9%$7 DDJ Fig 8. Battery switch-over circuit, simplified block diagram Voper(int) is at VDD or VBAT potential. Remark: It has to be assured that there are decoupling capacitors on the pins VDD, VBAT, and BBS. 8.6.2 Battery low detection function The PCF2127 has a battery low detection circuit which monitors the status of the battery VBAT. When VBAT drops below the threshold value Vth(bat)low (typically 2.5 V), the BLF flag (register Control_3) is set to indicate that the battery is low and that it must be replaced. Monitoring of the battery voltage also occurs during battery operation. An unreliable battery cannot prevent that the supply voltage drops below Vlow (typical 1.2 V) and with that the data integrity gets lost. (For further information about Vlow see Section 8.7.) When VBAT drops below the threshold value Vth(bat)low, the following sequence occurs (see Figure 9): 1. The battery low flag BLF is set logic 1. 2. An interrupt is generated if the control bit BLIE (register Control_3) is enabled (see Section 8.13.8). 3. The flag BLF remains logic 1 until the battery is replaced. BLF cannot be cleared by command. It is automatically cleared by the battery low detection circuit when the battery is replaced or when the voltage rises again above the threshold value. This could happen if a super capacitor is used as a backup source and the main power is applied again. PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 22 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 9'' 9RSHU LQW LQWHUQDORSHUDWLQJYROWDJH 9RSHU LQW 9%$7 9WK EDW ORZ 9 9%$7 %/) ,17 DDM Fig 9. Battery low detection behavior with bit BLIE set logic 1 (enabled) 8.6.3 Extra power fail detection function The PCF2127 has an extra power fail detection circuit which compares the voltage at the power fail input pin PFI to an internal reference voltage equal to 1.25 V. If VPFI < 1.25 V, the power fail output PFO is driven LOW. PFO is an open-drain, active LOW output which requires an external pull-up resistor in any application. The extra power fail detection function is typically used as a low voltage detection for the main power supply VDD (see Figure 10). 9'' 5 3&) 538 9 LQWHUQDO 3), %DWWHU\ VZLWFK FRQWURO  3)2 WR0&8 5 966 & DDD Fig 10. Typical application of the extra power fail detection function PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 23 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Usually R1 and R2 should be chosen such that the voltage at pin PFI • is higher than 1.25 V at start-up • falls below 1.25 V when VDD falls below a desired threshold voltage, Vth(uvp), defined by Equation 1: R V th  uvp  =  -----1- + 1  1.25V R  2 (1) Vth(uvp) value is usually set to a value that there are several milliseconds before VDD falls below the minimum operating voltage of the system, in order to allow the microcontroller to perform early backup operations, like terminating the communication with the PCF2127. The value of C is determined from Equation 2: 0.02 As C = --------------------- ----- R 1 //R 2  V (2) If the extra power fail detection function is not used, pin PFI must be connected to VSS and pin PFO must be left open circuit. 8.6.3.1 Extra power fail detection when the battery switch-over function is enabled • When the power switches to the backup battery supply VBAT, the power fail comparator is switched off and the power fail output at pin PFO goes (or remains) LOW • When the power switches back to the main VDD, the pin PFO is not driven LOW anymore. It is pulled HIGH through the external pull-up resistance for a certain time (trec = 15.63 ms to 31.25 ms). Then the power fail comparator is enabled again For illustration, see Figure 11 and Figure 12. PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 24 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 9'' 9WK XYS 9%$7 LQWHUQDORSHUDWLQJYROWDJH 9RSHU LQW 9RSHU LQW 9RSHU LQW 9WK VZ EDW 9 9'' 9 FRPSDUDWRU HQDEOHG FRPSDUDWRU GLVDEOHG FRPSDUDWRU HQDEOHG 3) WUHF >@PV DDM Fig 11. PFO signal behavior when battery switch-over is enabled in standard mode and Vth(uvp) > (VBAT, Vth(sw)bat) 9'' 9RSHU LQW 9%$7 LQWHUQDORSHUDWLQJYROWDJH 9RSHU LQW 9RSHU LQW 9WK XYS 9WK VZ EDW 9 9'' 9 FRPSDUDWRU HQDEOHG FRPSDUDWRU GLVDEOHG FRPSDUDWRU HQDEOHG 3) WUHF DDM Fig 12. PFO signal behavior when battery switch-over is enabled in direct switching mode and Vth(uvp) < VBAT PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 25 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 8.6.3.2 Extra power fail detection when the battery switch-over function is disabled If the battery switch-over function is disabled and the power fail comparator is enabled, the power fail output at pin PFO depends only on the result of the comparison between VPFI and 1.25 V: • If VPFI > 1.25 V, PFO = HIGH (through the external pull-up resistor) • If VPFI < 1.25 V, PFO = LOW 9'' 9WK XYS  9WK VZ EDW 9 FRPSDUDWRUDOZD\VHQDEOHG 3) DDM Fig 13. PFO signal behavior when battery switch-over is disabled 8.6.4 Battery backup supply The VBBS voltage on the output pin BBS is at the same potential as the internal operating voltage Voper(int), depending on the selected battery switch-over function mode: Table 26. Output pin BBS Battery switch-over function mode Conditions Potential of Voper(int) and VBBS standard VDD > VBAT OR VDD > Vth(sw)bat VDD VDD < VBAT AND VDD < Vth(sw)bat VBAT direct switching VDD > VBAT VDD VDD < VBAT VBAT disabled only VDD available, VBAT must be put to ground VDD The output pin BBS can be used as a supply for external devices with battery backup needs, such as SRAM (see Ref. 3 “AN11266”). For this case, Figure 14 shows the typical driving capability when VBBS is driven from VDD. PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 26 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications DDM  9%%6 9'' P9   9'' 9   9'' 9 9'' 9          ,%%6 P$ Fig 14. Typical driving capability of VBBS: (VBBS  VDD) with respect to the output load current IBBS 8.7 Oscillator stop detection function The PCF2127 has an on-chip oscillator detection circuit which monitors the status of the oscillation: whenever the oscillation stops, a reset occurs and the oscillator stop flag OSF (in register Seconds) is set logic 1. • Power-on: a. The oscillator is not running, the chip is in reset (OSF is logic 1). b. When the oscillator starts running and is stable after power-on, the chip exits from reset. c. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) by command. • Power supply failure: a. When the power supply of the chip drops below a certain value (Vlow), typically 1.2 V, the oscillator stops running and a reset occurs. b. When the power supply returns to normal operation, the oscillator starts running again, the chip exits from reset. c. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) by command. PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 27 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 9'' 9RSHU LQW 9'' 9RSHU LQW 9%$7 9%$7 9WK VZ EDW 9 9'' 9'' EDWWHU\GLVFKDUJH 9ORZ 9 9RSHU LQW 9%$7 966 966   26) DDM (1) Theoretical state of the signals since there is no power. (2) The oscillator stop flag (OSF), set logic 1, indicates that the oscillation has stopped and a reset has occurred since the flag was last cleared (OSF set logic 0). In this case, the integrity of the clock information is not guaranteed. The OSF flag is cleared by command. Fig 15. Power failure event due to battery discharge: reset occurs 8.8 Reset function The PCF2127 has a Power-On Reset (POR) and a Power-On Reset Override (PORO) function implemented. 8.8.1 Power-On Reset (POR) The POR is active whenever the oscillator is stopped. The oscillator is considered to be stopped during the time between power-on and stable crystal resonance (see Figure 16). This time may be in the range of 200 ms to 2 s depending on temperature and supply voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF set logic 1). The OTP refresh (see Section 8.3.2 on page 13) should ideally be executed as the first instruction after start-up and also after a reset due to an oscillator stop. PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 28 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications FKLSLQUHVHW FKLSQRWLQUHVHW FKLSIXOO\RSHUDWLYH &/.287 DYDLODEOH 9'' RVFLOODWLRQ 567 2735 W DDD Fig 16. Dependency between POR and oscillator After POR, the following mode is entered: • • • • • • 32.768 kHz CLKOUT active Power-On Reset Override (PORO) available to be set 24-hour mode is selected Battery switch-over is enabled Battery low detection is enabled Extra power fail detection is enabled The register values after power-on are shown in Table 5 on page 8. 8.8.2 Power-On Reset Override (PORO) The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and therefore speed up the on-board test of the device. 26&,//$725 6&/ 6'$&( 5(6(7 29(55,'( RVFVWRSSHG  VWRSSHG UXQQLQJ UHVHW  RYHUULGHLQDFWLYH  RYHUULGHDFWLYH &/($5 325B295'  FOHDURYHUULGHPRGH  RYHUULGHSRVVLEOH DDM Fig 17. Power-On Reset (POR) system The setting of the PORO mode requires that POR_OVRD in register Control_1 is set logic 1 and that the signals at the interface pins SDA/CE and SCL are toggled as illustrated in Figure 18. All timings shown are required minimum. PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 29 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications SRZHUXS PV PLQLPXPQV PLQLPXPQV 6'$&( 6&/ UHVHWRYHUULGH DDM Fig 18. Power-On Reset Override (PORO) sequence, valid for both I2C-bus and SPI-bus Once the override mode is entered, the device is immediately released from the reset state and the set-up operation can commence. The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0 during normal operation has no effect except to prevent accidental entry into the PORO mode. 8.9 Time and date function Most of these registers are coded in the Binary Coded Decimal (BCD) format. 8.9.1 Register Seconds Table 27. Seconds - seconds and clock integrity register (address 03h) bit allocation Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 Symbol 6 5 4 OSF Reset value 1 3 2 1 0 X X X SECONDS (0 to 59) X X X X Table 28. Seconds - seconds and clock integrity register (address 03h) bit description Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol 7 OSF Value Place value Description 0 - clock integrity is guaranteed 1 - clock integrity is not guaranteed: oscillator has stopped and chip reset has occurred since flag was last cleared 6 to 4 SECONDS 3 to 0 PCF2127 Product data sheet 0 to 5 ten’s place 0 to 9 unit place actual seconds coded in BCD format All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 30 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 29. Seconds coded in BCD format Seconds value in decimal Upper-digit (ten’s place) Digit (unit place) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0 0 0 0 0 0 0 01 0 0 0 0 0 0 1 02 0 0 0 0 0 1 0 : : : : : : : : 09 0 0 0 1 0 0 1 10 0 0 1 0 0 0 0 : : : : : : : : 58 1 0 1 1 0 0 0 59 1 0 1 1 0 0 1 8.9.2 Register Minutes Table 30. Minutes - minutes register (address 04h) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 Symbol - Reset value - 6 5 4 3 2 1 0 X X X MINUTES (0 to 59) X X X X Table 31. Minutes - minutes register (address 04h) bit description Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Place value Description 7 - - - unused 6 to 4 MINUTES 0 to 5 ten’s place actual minutes coded in BCD format 0 to 9 unit place 3 to 0 PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 31 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 8.9.3 Register Hours Table 32. Hours - hours register (address 05h) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 6 5 Symbol - - AMPM 4 3 2 1 0 HOURS (1 to 12) in 12-hour mode HOURS (0 to 23) in 24-hour mode Reset value - - X X X X X X Table 33. Hours - hours register (address 05h) bit description Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Place value Description 7 to 6 - - - unused - indicates AM 12-hour mode[1] 5 AMPM 0 1 - indicates PM 4 HOURS 0 to 1 ten’s place 0 to 9 unit place actual hours coded in BCD format when in 12-hour mode 0 to 2 ten’s place 0 to 9 unit place 3 to 0 24-hour mode[1] 5 to 4 HOURS 3 to 0 [1] actual hours coded in BCD format when in 24-hour mode Hour mode is set by the bit 12_24 in register Control_1 (see Table 7). 8.9.4 Register Days Table 34. Days - days register (address 06h) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 6 Symbol - - Reset value - - Table 35. 5 4 3 2 X X X X 0 X X Days - days register (address 06h) bit description Bit Symbol Value Place value Description 7 to 6 - - - unused 5 to 4 DAYS[1] 0 to 3 ten’s place actual day coded in BCD format 0 to 9 unit place 3 to 0 [1] 1 DAYS (1 to 31) If the year counter contains a value which is exactly divisible by 4, including the year 00, the RTC compensates for leap years by adding a 29th day to February. PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 32 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 8.9.5 Register Weekdays Table 36. Weekdays - weekdays register (address 07h) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 6 5 4 3 Symbol - - - - - Reset value - - - - - 2 1 0 WEEKDAYS (0 to 6) X X X Table 37. Weekdays - weekdays register (address 07h) bit description Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Description 7 to 3 - - unused 2 to 0 WEEKDAYS 0 to 6 actual weekday value, see Table 38 Although the association of the weekdays counter to the actual weekday is arbitrary, the PCF2127 assumes that Sunday is 000 and Monday is 001 for the purpose of determining the increment for calendar weeks. Table 38. Weekday assignments Day[1] 2 1 0 Sunday 0 0 0 Monday 0 0 1 Tuesday 0 1 0 Wednesday 0 1 1 Thursday 1 0 0 Friday 1 0 1 Saturday 1 1 0 [1] PCF2127 Product data sheet Bit Definition may be reassigned by the user. All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 33 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 8.9.6 Register Months Table 39. Months - months register (address 08h) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 6 5 Symbol - - - Reset value - - - 4 3 2 1 0 X X MONTHS (1 to 12) X X X Table 40. Months - months register (address 08h) bit description Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Place value Description 7 to 5 - - - unused 4 MONTHS 0 to 1 ten’s place actual month coded in BCD format, see Table 41 0 to 9 unit place 3 to 0 Table 41. Month PCF2127 Product data sheet Month assignments in BCD format Upper-digit (ten’s place) Digit (unit place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 January 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April 0 0 1 0 0 May 0 0 1 0 1 June 0 0 1 1 0 July 0 0 1 1 1 August 0 1 0 0 0 September 0 1 0 0 1 October 1 0 0 0 0 November 1 0 0 0 1 December 1 0 0 1 0 All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 34 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 8.9.7 Register Years Table 42. Years - years register (address 09h) bit allocation Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 6 5 X X X Symbol 4 3 2 1 0 X X X YEARS (0 to 99) Reset value X X Table 43. Years - years register (address 09h) bit description Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Place value Description 7 to 4 YEARS 0 to 9 ten’s place 0 to 9 unit place 3 to 0 actual year coded in BCD format 8.9.8 Setting and reading the time Figure 19 shows the data flow and data dependencies starting from the 1 Hz clock tick. During read/write operations, the time counting circuits (memory locations 03h through 09h) are blocked. This prevents • Faulty reading of the clock and calendar during a carry condition • Incrementing the time registers during the read cycle +]WLFN 6(&21'6 0,187(6 BKRXUPRGH +2856 /($31 4096 1⁄ 8192 1⁄ 4096 64 1⁄ 128 1⁄ 64 1 1⁄ 64 1⁄ 64 1⁄ 60 1⁄ 64 1⁄ 64 [1] n = loaded countdown value. Timer stopped when n = 0. If the MSF or CDTF flag (register Control_2) is cleared before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately when it is serviced, that is, the system does not have to wait for the completion of the pulse before continuing, see Figure 30 and Figure 31. Instructions for clearing bit MSF and bit CDTF can be found in Section 8.11.6. VHFRQGVFRXQWHU   06) ,17  6&/ WKFORFN LQVWUXFWLRQ &/($5,16758&7,21 DDI (1) Indicates normal duration of INT pulse. The timing shown for clearing bit MSF is also valid for the non-pulsed interrupt mode. That is, when TI_TP is logic 0, where the INT pulse may be shortened by setting both bits MI and SI logic 0. Fig 30. Example of shortening the INT pulse by clearing the MSF flag FRXQWGRZQFRXQWHU  Q &'7) ,17  6&/ WKFORFN LQVWUXFWLRQ &/($5,16758&7,21 DDI (1) Indicates normal duration of INT pulse. The timing shown for clearing CDTF is also valid for the non-pulsed interrupt mode. That is, when TI_TP is logic 0, where the INT pulse may be shortened by setting CDTIE logic 0. Fig 31. Example of shortening the INT pulse by clearing the CDTF flag PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 57 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 8.13.4 Watchdog timer interrupts The generation of interrupts from the watchdog timer is controlled using the WD_CD[1:0] bits (register Watchdg_tim_ctl). The interrupt is generated as an active signal which follows the status of the watchdog timer flag WDTF (register Control_2). No pulse generation is possible for watchdog timer interrupts. The interrupt is cleared when the flag WDTF is reset. WDTF is a read-only bit and cannot be cleared by command. Instructions for clearing it can be found in Section 8.11.6. 8.13.5 Alarm interrupts Generation of interrupts from the alarm function is controlled by the bit AIE (register Control_2). If AIE is enabled, the INT pin follows the status of bit AF (register Control_2). Clearing AF immediately clears INT. No pulse generation is possible for alarm interrupts. PLQXWHFRXQWHU  PLQXWHDODUP   $) ,17 6&/ WKFORFN LQVWUXFWLRQ &/($5,16758&7,21 DDI Example where only the minute alarm is used and no other interrupts are enabled. Fig 32. AF timing diagram 8.13.6 Timestamp interrupts Interrupt generation from the timestamp function is controlled using the TSIE bit (register Control_2). If TSIE is enabled, the INT pin follows the status of the flags TSFx. Clearing the flags TSFx immediately clears INT. No pulse generation is possible for timestamp interrupts. 8.13.7 Battery switch-over interrupts Generation of interrupts from the battery switch-over is controlled by the BIE bit (register Control_3). If BIE is enabled, the INT pin follows the status of bit BF in register Control_3 (see Table 81). Clearing BF immediately clears INT. No pulse generation is possible for battery switch-over interrupts. 8.13.8 Battery low detection interrupts Generation of interrupts from the battery low detection is controlled by the BLIE bit (register Control_3). If BLIE is enabled, the INT pin follows the status of bit BLF (register Control_3). The interrupt is cleared when the battery is replaced (BLF is logic 0) or when bit BLIE is disabled (BLIE is logic 0). BLF is read only and therefore cannot be cleared by command. PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 58 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 8.14 External clock test mode A test mode is available which allows on-board testing. In this mode, it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit EXT_TEST logic 1 (register Control_1). Then pin CLKOUT becomes an input. The test mode replaces the internal clock signal (64 Hz) with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT generate an increment of one second. The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a maximum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided down by a 26 divider chain called prescaler (see Table 84). The prescaler can be set into a known state by using bit STOP. When bit STOP is logic 1, the prescaler is reset to 0. STOP must be cleared before the prescaler can operate again. From a stop condition, the first 1 second increment will take place after 32 positive edges on pin CLKOUT. Thereafter, every 64 positive edges cause a 1 second increment. Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assumption as to the state of the prescaler can be made. Operating example: 1. Set EXT_TEST test mode (register Control_1, EXT_TEST is logic 1). 2. Set bit STOP (register Control_1, STOP is logic 1). 3. Set time registers to desired value. 4. Clear STOP (register Control_1, STOP is logic 0). 5. Apply 32 clock pulses to CLKOUT. 6. Read time registers to see the first change. 7. Apply 64 clock pulses to CLKOUT. 8. Read time registers to see the second change. Repeat 7 and 8 for additional increments. 8.15 STOP bit function The function of the STOP bit is to allow for accurate starting of the time circuits. STOP causes the upper part of the prescaler (F9 to F14) to be held in reset and thus no 1 Hz ticks are generated. The time circuits can then be set and will not increment until the STOP bit is released. STOP doesn't affect the CLKOUT signal but the output of the prescaler in the range of 32 Hz to 1 Hz (see Figure 33). PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 59 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications /2:(535(6&$/(5 +] +] ) 26& +] ) 833(535(6&$/(5 +] +] ) +] ) ) ) ) ) 5(6 5(6 5(6 5(6 +]WLFN VWRS DDM Fig 33. STOP bit functional diagram The lower stages of the prescaler, F0 to F8, are not reset and because the I2C-bus and the SPI-bus are asynchronous to the crystal oscillator, the accuracy of restarting the time circuits is between 0 and one 64 Hz cycle (0.484375 s and 0.500000 s), see Table 84 and Figure 34. Table 84. First increment of time circuits after stop release Bit STOP Prescaler bits[1] F0 to F8 - F9 to F14 1 Hz tick Time hh:mm:ss Comment 12:45:12 prescaler counting normally Clock is running normally 0 010000111-010100 STOP bit is activated by user. F0 to F8 are not reset and values cannot be predicted externally 1 xxxxxxxxx-000000 12:45:12 prescaler is reset; time circuits are frozen 08:00:00 prescaler is reset; time circuits are frozen 08:00:00 prescaler is now running New time is set by user 1 xxxxxxxxx-000000 STOP bit is released by user xxxxxxxxx-000000 0 xxxxxxxxx-100000 0 xxxxxxxxx-100000 0 xxxxxxxxx-110000 : : 0 111111111-111110 0 000000000-000001 08:00:01 0 100000000-000001 08:00:01 : : : 0 111111111-111111 08:00:01 0 000000000-000000 V 0 08:00:00 08:00:00 08:00:00 : V 08:00:00 0 to 1 transition of F14 increments the time circuits 08:00:01 0 100000000-000000 : : : 0 111111111-111110 08:00:01 0 000000000-000001 08:00:02 0 to 1 transition of F14 increments the time circuits DDM [1] F0 is clocked at 32.768 kHz. PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 60 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications +] VWRSUHOHDVHG PVPV DDM Fig 34. STOP bit release timing PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 61 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 9. Interfaces The PCF2127 has an I2C-bus or SPI-bus interface using the same pins. The selection is done using the interface selection pin IFS (see Table 85). Table 85. Interface selection input pin IFS Pin Connection Bus interface Reference IFS VSS SPI-bus Section 9.1 BBS I2C-bus Section 9.2 9'' 9'' 538 6&/ 6', 6&/ 6'2 6'$ &( 538 9'' 6&/ 6', 9'' 6&/ 6'2 6', ,)6 6'$&( ,)6 %%6 6'$&( %%6 6'2 3&) 3&) 966 966 966 966 DDD DDD To select the I2C-bus interface, pin IFS has to be connected to pin BBS. To select the SPI-bus interface, pin IFS has to be connected to pin VSS. b. I2C-bus interface selection a. SPI-bus interface selection Fig 35. Interface selection 9.1 SPI-bus interface Data transfer to and from the device is made by a 3 line SPI-bus (see Table 86). The data lines for input and output are split. The data input and output line can be connected together to facilitate a bidirectional data bus (see Figure 36). The SPI-bus is initialized whenever the chip enable line pin SDA/CE is inactive. 6', 6', 6'2 6'2 WZRZLUHPRGH VLQJOHZLUHPRGH DDL Fig 36. SDI, SDO configurations PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 62 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 86. Serial interface Symbol Function SDA/CE Description [1] chip enable input; active LOW when HIGH, the interface is reset; input may be higher than VDD SCL serial clock input when SDA/CE is HIGH, input may float; SDI serial data input when SDA/CE is HIGH, input may float; input may be higher than VDD input may be higher than VDD; input data is sampled on the rising edge of SCL SDO serial data output push-pull output; drives from VSS to Voper(int) (VBBS); output data is changed on the falling edge of SCL [1] The chip enable must not be wired permanently LOW. 9.1.1 Data transmission The chip enable signal is used to identify the transmitted data. Each data transfer is a whole byte, with the Most Significant Bit (MSB) sent first. The transmission is controlled by the active LOW chip enable signal SDA/CE. The first byte transmitted is the command byte. Subsequent bytes are either data to be written or data to be read (see Figure 37). GDWDEXV &200$1' '$7$ '$7$ '$7$ 6'$&( DDD Fig 37. Data transfer overview The command byte defines the address of the first register to be accessed and the read/write mode. The address counter will auto increment after every access and will reset to zero after the last valid register is accessed. The R/W bit defines if the following bytes are read or write information. Table 87. Command byte definition Bit Symbol 7 R/W 6 to 5 SA Value Description data read or write selection 0 write data 1 read data 01 subaddress; other codes will cause the device to ignore data transfer 4 to 0 PCF2127 Product data sheet RA 00h to 1Dh register address All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 63 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 5: 6$ DGGUK VHFRQGVGDWD%&' PLQXWHVGDWD%&' E E E E E E E E E E E E E E E E E E E E E E E E                         6&/ 6', 6'$&( DGGUHVV [[ FRXQWHU    DDM In this example, the Seconds register is set to 45 seconds and the Minutes register to 10 minutes. a. Writing seconds and minutes 5: E  6$ E  E  UHJLVWHUDGGUHVV$K E  E  E  E  E  GDWDK E  E  E  E  E  GDWDK E  E  E  E  E  E  E  E  E  E  E  E ; E ; E ; E ; E ; E ; 6&/ 6', 6'2 6'$&( 5: E  6$ E  E  DGGU&K E  E  E  E  WRQGDWDE\WHV E  E ; E ; E ; E ; E ; E ; E ; E ; E ; E ; 6&/ 6', 6'2 6'$&( DDD b. Writing to RAM address 02h Fig 38. SPI-bus write examples PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 64 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 5: 6$ DGGUK PRQWKVGDWD%&' \HDUVGDWD%&' E E E E E E E E E E E E E E E E E E E E E E E E                         6&/ 6', 6'2 6'$&( DGGUHVV [[ FRXQWHU   $ DDM In this example, the registers Months and Years are read. The pins SDI and SDO are not connected together. For this configuration, it is important that pin SDI is never left floating. It must always be driven either HIGH or LOW. If pin SDI is left open, high IDD currents may result. a. Reading month and year 5: E  6$ E  E  UHJLVWHUDGGUHVV$K E  E  E  E  E  GDWDK E  E  E  E  E  GDWDK E  E  E  E  E  E  E  E  E  E  E  E ; E ; E ; E ; E ; E ; 6&/ 6', 6'2 6'$&( 5: E  6$ E  E  DGGU'K E  E  E  E  WRQGDWDE\WHV E  E ; E ; E ; E ; E ; E ; E ; E ; E ; E ; 6&/ 6', 6'2 6'$&( DDD b. Reading from RAM address 12h Fig 39. SPI-bus read examples PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 65 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 9.2 I2C-bus interface The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines are connected to a positive supply by a pull-up resistor. Data transfer is initiated only when the bus is not busy. 9.2.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line remains stable during the HIGH period of the clock pulse as changes in the data line at this time are interpreted as control signals (see Figure 40). 6'$ 6&/ GDWDOLQH VWDEOH GDWDYDOLG FKDQJH RIGDWD DOORZHG PEF Fig 40. Bit transfer 9.2.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as the START condition S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition P (see Figure 41). 6'$ 6'$ 6&/ 6&/ 6 3 67$57FRQGLWLRQ 6723FRQGLWLRQ PEF Fig 41. Definition of START and STOP conditions Remark: For the PCF2127, a repeated START is not allowed. Therefore a STOP has to be released before the next START. 9.2.3 System configuration A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master; and the devices which are controlled by the master are the slaves. The PCF2127 can act as a slave transmitter and a slave receiver. PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 66 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 6'$ 6&/ 0$67(5 75$160,77(5 5(&(,9(5 6/$9( 75$160,77(5 5(&(,9(5 6/$9( 5(&(,9(5 0$67(5 75$160,77(5 5(&(,9(5 0$67(5 75$160,77(5 PED Fig 42. System configuration 9.2.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver which is addressed must generate an acknowledge after the reception of each byte. • Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be considered). • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Figure 43. GDWDRXWSXW E\WUDQVPLWWHU QRWDFNQRZOHGJH GDWDRXWSXW E\UHFHLYHU DFNQRZOHGJH 6&/IURP PDVWHU     6 67$57 FRQGLWLRQ FORFNSXOVHIRU DFNQRZOHGJHPHQW PEF Fig 43. Acknowledgement on the I2C-bus 9.2.5 I2C-bus protocol After a start condition, a valid hardware address has to be sent to a PCF2127 device. The appropriate I2C-bus slave address is 1010001. The entire I2C-bus slave address byte is shown in Table 88. PCF2127 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 67 of 100 PCF2127 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications I2C slave address byte Table 88. Slave address Bit 7 6 5 4 3 2 1 0 0 1 0 0 0 1 R/W MSB LSB 1 The R/W bit defines the direction of the following single or multiple byte data transfer (read is logic 1, write is logic 0). For the format and the timing of the START condition (S), the STOP condition (P), and the acknowledge (A) refer to the I2C-bus specification Ref. 13 “UM10204” and the characteristics table (Table 93). In the write mode, a data transfer is terminated by sending a STOP condition. A repeated START (Sr) condition is not applicable. DFNQRZOHGJH IURP3&) 6        VODYHDGGUHVV  DFNQRZOHGJH IURP3&) DFNQRZOHGJH IURP3&) $ $ $ ZULWHELW WRQ GDWDE\WHV SOXV$&. UHJLVWHUDGGUHVV KWR'K 3 6 6723 67$57 DDD Fig 44. Bus protocol, writing to registers DFNQRZOHGJH IURP3&) 6        VODYHDGGUHVV  DFNQRZOHGJH IURP3&) $ $ UHJLVWHUDGGUHVV KWR'K ZULWHELW DFNQRZOHGJH IURP3&) 6      VODYHDGGUHVV    $ VHWUHJLVWHU DGGUHVV 3 6723 DFNQRZOHGJH IURPPDVWHU QRDFNQRZOHGJH $ $ '$7$%
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