PCF2129AT/1,518

PCF2129 Accurate RTC with integrated quartz crystal for industrial applications Rev. 8.0 — 18 July 2022 1 Product data sheet General description 1 The PCF2129 is a CMOS Real Time Clock (RTC) and calendar with an integrated Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal optimized for very high accuracy and very low power consumption. The 2 PCF2129 has a selectable I C-bus or SPI-bus, a backup battery switch-over circuit, a programmable watchdog function, a timestamp function, and many other features. For a selection of NXP Real-Time Clocks, see Table 82 2 Features and benefits • • • • • • • • • • • • • • • • • • • • UL Recognized Component (PCF2129AT and PCF2129T) Operating temperature range from -40 °C to +85 °C Temperature Compensated Crystal Oscillator (TCXO) with integrated capacitors Typical accuracy: – PCF2129AT: ±3 ppm from -15 °C to +60 °C – PCF2129T: ±3 ppm from -30 °C to +80 °C Integration of a 32.768 kHz quartz crystal and oscillator in the same package Provides year, month, day, weekday, hours, minutes, seconds, and leap year correction Timestamp function – with interrupt capability – detection of two different events on one multilevel input pin (for example, for tamper detection) 2 Two line bidirectional 400 kHz Fast-mode I C-bus interface Three line SPI-bus with separate data input and output (maximum speed 6.5 Mbit/s) Battery backup input pin and switch-over circuitry Battery backed output voltage Battery low detection function Power-On Reset Override (PORO) Oscillator stop detection function Interrupt output (open-drain) Programmable 1 second or 1 minute interrupt Programmable watchdog timer with interrupt Programmable alarm function with interrupt capability Programmable square output Clock operating voltage: 1.8 V to 4.2 V 1 The definition of the abbreviations and acronyms used in this data sheet can be found in Section 20. PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications • Low supply current: typical 0.70 μA at VDD = 3.3 V 3 Applications • • • • • • 4 Electronic metering for electricity, water, and gas Precision timekeeping Access to accurate time of the day GPS equipment to reduce time to first fix Applications that require an accurate process timing Products with long automated unattended operation time Ordering information Table 1. Ordering information Type number Topside marking Package Name Description Version PCF2129AT PCF2129AT SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 PCF2129T PCF2129T SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 4.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method PCF2129AT PCF2129AT/2,518 SO20 PCF2129T PCF2129T/2,518 SO16 [1] [1] Minimum order quantity Temperature reel 13" Q1 DP 2000 Tamb = -40 °C to +85 °C reel 13" Q1 DP 1000 Tamb = -40 °C to +85 °C Standard packing quantities and other packaging data are available at www.nxp.com/packages/. PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 2 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 5 Block diagram INT TCXO OSCI 32.768 kHz DIVIDER AND TIMER OSCO CLKOUT VDD VBAT VSS TEMP BATTERY BACK UP SWITCH-OVER CIRCUITRY BBS OSCILLATOR MONITOR internal operating voltage Voper(int) SDO SDI SCL IFS LOGIC CONTROL RESET SPI-BUS INTERFACE SDA/CE 1 Hz ADDRESS REGISTER SERIAL BUS INTERFACE SELECTOR I2C-BUS INTERFACE PCF2129 RPU TS TEMP TEMPERATURE SENSOR Control_1 00h Control_2 01h Control_3 02h Seconds 03h Minutes 04h Hours 05h Days 06h Weekdays 07h Months 08h Years 09h Second_alarm 0Ah Minute_alarm 0Bh Hour_alarm 0Ch Day_alarm 0Dh Weekday_alarm 0Eh CLKOUT_ctl 0Fh Watchdg_tim_ctl 10h Watchdg_tim_val 11h Timestp_ctl 12h Sec_timestp 13h Min_timestp 14h Hour_timestp 15h Day_timestp 16h Mon_timestp 17h Year_timestp 18h Aging_offset 19h Internal_reg 1Ah Internal_reg 1Bh aaa-015269 Figure 1. Block diagram of PCF2129 PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 3 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 6 Pinning information 6.1 Pinning SCL 1 20 VDD SDI 2 19 VBAT SDO 3 18 BBS SDA/CE 4 17 INT IFS 5 TS 6 CLKOUT 7 14 n.c. VSS 8 13 n.c. n.c. 9 12 n.c. n.c. 10 11 n.c. PCF2129AT 16 n.c. 15 n.c. 001aaj704 Top view. For mechanical details, see Figure 50. Figure 2. Pin configuration for PCF2129AT (SO20) SCL 1 16 VDD SDI 2 15 VBAT SDO 3 14 BBS SDA/CE 4 IFS 5 TS 6 11 n.c. CLKOUT 7 10 n.c. VSS 8 PCF2129T 13 INT 12 n.c. 9 n.c. 013aaa567 Top view. For mechanical details, see Figure 50. Figure 3. Pin configuration for PCF2129T (SO16) aaa-015271 Figure 4. Position of the stubs from the package assembly process After lead forming and cutting, there remain stubs from the package assembly process. These stubs are present at the edge of the package as illustrated in Figure 4. The stubs are at an electrical potential. To avoid malfunction of the PCF2129, it has to be ensured that they are not shorted with another electrical potential (e.g. by condensation). PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 4 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 6.2 Pin description Table 3. Pin description of PCF2129 Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified. Symbol Pin Description PCF2129AT PCF2129T SCL 1 1 combined serial clock input for both I C-bus and SPI-bus SDI 2 2 serial data input for SPI-bus 2 connect to pin VSS if I C-bus is selected SDO 3 3 serial data output for SPI-bus, push-pull SDA/CE 4 4 combined serial data input and output for the I C-bus and chip enable input (active LOW) for the SPI-bus IFS 5 5 interface selector input connect to pin VSS to select the SPI-bus 2 connect to pin BBS to select the I C-bus TS 6 6 timestamp input (active LOW) with 200 kΩ internal pull-up resistor (RPU) CLKOUT 7 7 clock output (open-drain) VSS 8 8 ground supply voltage n.c. 9 to 16 9 to 12 not connected; do not connect; do not use as feed through INT 17 13 interrupt output (open-drain; active LOW) BBS 18 14 output voltage (battery backed) VBAT 19 15 battery supply voltage (backup) connect to VSS if battery switch over is not used VDD 20 16 supply voltage 7 2 2 Functional description The PCF2129 is a Real Time Clock (RTC) and calendar with an on-chip Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal integrated into the same package (see Section 7.3.3). 2 Address and data are transferred by a selectable 400 kHz Fast-mode I C-bus or a 3 line SPI-bus with separate data input and output (see Section 8). The maximum speed of the SPI-bus is 6.5 Mbit/s. The PCF2129 has a backup battery input pin and backup battery switch-over circuit which monitors the main power supply. The backup battery switch-over circuit automatically switches to the backup battery when a power failure condition is detected (see Section 7.5.1). Accurate timekeeping is maintained even when the main power supply is interrupted. A battery low detection circuit monitors the status of the battery (see Section 7.5.2). When the battery voltage drops below a certain threshold value, a flag is set to indicate that the battery must be replaced soon. This ensures the integrity of the data during periods of battery backup. PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 5 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 7.1 Register overview The PCF2129 contains an auto-incrementing address register: the built-in address register will increment automatically after each read or write of a data byte up to the register 1Bh. After register 1Bh, the auto-incrementing will wrap around to address 00h (see Figure 5). address register 00h 01h 02h auto-increment 03h ... 19h 1Ah 1Bh wrap around 001aaj398 Figure 5. Handling address registers • The first three registers (memory address 00h, 01h, and 02h) are used as control registers (see Section 7.2). • The memory addresses 03h through to 09h are used as counters for the clock function (seconds up to years). The date is automatically adjusted for months with fewer than 31 days, including corrections for leap years. The clock can operate in 12-hour mode with an AM/PM indication or in 24-hour mode (see Section 7.8). • The registers at addresses 0Ah through 0Eh define the alarm function. It can be selected that an interrupt is generated when an alarm event occurs (see Section 7.9). • The register at address 0Fh defines the temperature measurement period and the clock out mode. The temperature measurement can be selected from every 4 minutes (default) down to every 30 seconds (see Table 13). CLKOUT frequencies of 32.768 kHz (default) down to 1 Hz for use as system clock, microcontroller clock, and so on, can be chosen (see Table 14). • The registers at addresses 10h and 11h are used for the watchdog timer functions. The watchdog timer has four selectable source clocks allowing for timer periods from less than 1 ms to greater than 4 hours (see Table 51). An interrupt is generated when the watchdog times out. • The registers at addresses 12h to 18h are used for the timestamp function. When the trigger event happens, the actual time is saved in the timestamp registers (see Section 7.11). • The register at address 19h is used for the correction of the crystal aging effect (see Section 7.4.1). • The registers at addresses 1Ah and 1Bh are for internal use only. • The registers Seconds, Minutes, Hours, Days, Months, and Years are all coded in Binary Coded Decimal (BCD) format to simplify application use. Other registers are either bit-wise or standard binary. When one of the RTC registers is written or read, the content of all counters is temporarily frozen. This prevents a faulty writing or reading of the clock and calendar during a carry condition (see Section 7.8.8). PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 6 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 4. Register overview Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as T must always be written with logic 0. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Address Register name Bit 7 6 5 4 3 2 1 Reset value Reference 0 Control registers 00h Control_1 EXT_ TEST T STOP TSF1 POR_ OVRD 12_24 MI SI 0000 1000 Table 6 01h Control_2 MSF WDTF TSF2 AF T TSIE AIE T 0000 0000 Table 8 02h Control_3 BTSE BF BLF BIE BLIE 0000 0000 Table 10 PWRMNG[2:0] Time and date registers 03h Seconds OSF SECONDS (0 to 59) 1XXX XXXX Table 21 04h Minutes - MINUTES (0 to 59) - XXX XXXX Table 24 05h Hours - - - XX XXXX Table 26 - AMPM 06h Days - - 07h Weekdays - - - 08h Months - - - 09h Years HOURS (1 to 12) in 12-hour mode HOURS (0 to 23) in 24-hour mode - - XX XXXX DAYS (1 to 31) - - XX XXXX Table 28 - - - - - XXX Table 30 - - - X XXXX Table 33 YEARS (0 to 99) XXXX XXXX Table 36 - - WEEKDAYS (0 to 6) MONTHS (1 to 12) Alarm registers 0Ah Second_alarm AE_S SECOND_ALARM (0 to 59) 1XXX XXXX Table 38 0Bh Minute_alarm AE_M MINUTE_ALARM (0 to 59) 1XXX XXXX Table 40 0Ch Hour_alarm AE_H 1 - XX XXXX Table 42 - 0Dh Day_alarm AE_D - 0Eh Weekday_alarm AE_W - AMPM HOUR_ALARM (1 to 12) in 12-hour mode HOUR_ALARM (0 to 23) in 24-hour mode 1 - XX XXXX DAY_ALARM (1 to 31) 1 - XX XXXX Table 44 - - - WEEKDAY_ALARM (0 to 6) 1 - - - - XXX Table 46 OTPR - - COF[2:0] 00X - - 000 Table 12 CLKOUT control register 0Fh CLKOUT_ctl PCF2129 Product data sheet TCR[1:0] All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 7 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 4. Register overview...continued Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as T must always be written with logic 0. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Address Register name Bit 7 6 5 4 3 2 1 Reset value Reference 000 - - - 11 Table 48 XXXX XXXX Table 50 00 - X XXXX Table 57 0 Watchdog registers 10h Watchdg_tim_ctl 11h Watchdg_tim_val WD_CD T TI_TP - - - TF[1:0] WATCHDG_TIM_VAL[7:0] Timestamp registers 12h Timestp_ctl TSM TSOFF 13h Sec_timestp - SECOND_TIMESTP (0 to 59) - XXX XXXX Table 59 14h Min_timestp - MINUTE_TIMESTP (0 to 59) - XXX XXXX Table 61 15h Hour_timestp - - - XX XXXX Table 63 - 16h Day_timestp - - 17h Mon_timestp - - 18h Year_timestp - 1_O_16_TIMESTP[4:0] AMPM HOUR_TIMESTP (1 to 12) in 12-hour mode HOUR_TIMESTP (0 to 23) in 24-hour mode - - XX XXXX DAY_TIMESTP (1 to 31) - - XX XXXX Table 65 - - - X XXXX Table 67 XXXX XXXX Table 69 - - - - 1000 Table 16 - MONTH_TIMESTP (1 to 12) YEAR_TIMESTP (0 to 99) Aging offset register 19h Aging_offset - - - - AO[3:0] Internal registers 1Ah Internal_reg - - - - - - - - -------- - 1Bh Internal_reg - - - - - - - - -------- - PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 8 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 7.2 Control registers The first 3 registers of the PCF2129, with the addresses 00h, 01h, and 02h, are used as control registers. 7.2.1 Register Control_1 Table 5. Control_1 - control and status register 1 (address 00h) bit allocation Bits labeled as T must always be written with logic 0. Bit Symbol 7 6 5 4 3 2 1 0 EXT_ TEST T STOP TSF1 POR_ OVRD 12_24 MI SI 0 0 0 0 1 0 0 0 Reset value Table 6. Control_1 - control and status register 1 (address 00h) bit description Bits labeled as T must always be written with logic 0. Bit Symbol Value Description Reference 7 EXT_TEST 0 normal mode Section 7.13 1 external clock test mode 6 T 0 unused - 5 STOP 0 RTC source clock runs Section 7.14 1 RTC clock is stopped; RTC divider chain flip-flops are asynchronously set logic 0; CLKOUT at 32.768 kHz, 16.384 kHz, or 8.192 kHz is still available 0 no timestamp interrupt generated 1 flag set when TS input is driven to an intermediate level between power supply and ground; flag must be cleared to clear interrupt 0 Power-On Reset Override (PORO) facility disabled; Section 7.7.2 set logic 0 for normal operation 1 Power-On Reset Override (PORO) sequence reception enabled 0 24-hour mode selected 1 12-hour mode selected Table 26, Table 42, Table 43, Table 63 0 minute interrupt disabled Section 7.12.1 1 minute interrupt enabled 0 second interrupt disabled 1 second interrupt enabled 4 3 2 1 0 TSF1 POR_OVRD 12_24 MI SI PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 Section 7.11.1 © 2022 NXP B.V. All rights reserved. 9 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 7.2.2 Register Control_2 Table 7. Control_2 - control and status register 2 (address 01h) bit allocation Bits labeled as T must always be written with logic 0. Bit Symbol 7 6 5 4 3 2 1 0 MSF WDTF TSF2 AF T TSIE AIE T 0 0 0 0 0 0 0 0 Reset value Table 8. Control_2 - control and status register 2 (address 01h) bit description Bits labeled as T must always be written with logic 0. Bit Symbol Value Description Reference 7 MSF 0 no minute or second interrupt generated Section 7.12 1 flag set when minute or second interrupt generated; flag must be cleared to clear interrupt 0 no watchdog timer interrupt or reset generated 1 flag set when watchdog timer interrupt or reset generated; flag cannot be cleared by command (read-only) 0 no timestamp interrupt generated 1 flag set when TS input is driven to ground; flag must be cleared to clear interrupt 0 no alarm interrupt generated 1 flag set when alarm triggered; flag must be cleared to clear interrupt 6 5 4 WDTF TSF2 AF Section 7.12.3 Section 7.11.1 Section 7.9.6 3 T 0 unused - 2 TSIE 0 no interrupt generated from timestamp flag Section 7.12.5 1 interrupt generated when timestamp flag set 0 no interrupt generated from the alarm flag 1 interrupt generated when alarm flag set 0 unused 1 0 AIE T Section 7.12.4 - 7.2.3 Register Control_3 Table 9. Control_3 - control and status register 3 (address 02h) bit allocation Bit 7 Symbol Reset value PCF2129 Product data sheet 6 5 PWRMNG[2:0] 0 0 0 4 3 2 1 0 BTSE BF BLF BIE BLIE 0 0 0 0 0 All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 10 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 10. Control_3 - control and status register 3 (address 02h) bit description Bit Symbol Value Description Reference 7 to 5 PWRMNG[2:0] see Table 18 control of the battery switch-over, battery low detection, and extra power fail detection functions Section 7.5 4 BTSE 0 no timestamp when battery switch-over occurs Section 7.11.4 1 time-stamped when battery switch-over occurs 0 no battery switch-over interrupt generated 1 flag set when battery switch-over occurs; flag must be cleared to clear interrupt 0 battery status ok; no battery low interrupt generated 1 battery status low; flag cannot be cleared by command 0 no interrupt generated from the battery flag (BF) 1 interrupt generated when BF is set 0 no interrupt generated from battery low flag (BLF) 1 interrupt generated when BLF is set 3 2 1 0 BF BLF BIE BLIE Section 7.5.1 and Section 7.11.4 Section 7.5.2 Section 7.12.6 Section 7.12.7 7.3 Register CLKOUT_ctl Table 11. CLKOUT_ctl - CLKOUT control register (address 0Fh) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 Symbol 6 TCR[1:0] Reset value 0 0 5 4 3 OTPR - - X - - 2 1 0 COF[2:0] 0 0 0 Table 12. CLKOUT_ctl - CLKOUT control register (address 0Fh) bit description Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Description 7 to 6 TCR[1:0] see Table 13 temperature measurement period 5 OTPR 0 no OTP refresh 1 OTP refresh performed 4 to 3 - - unused 2 to 0 COF[2:0] see Table 14 CLKOUT frequency selection 7.3.1 Temperature compensated crystal oscillator The frequency of tuning fork quartz crystal oscillators is temperature-dependent. In the PCF2129, the frequency deviation caused by temperature variation is corrected by adjusting the load capacitance of the crystal oscillator. PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 11 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications The load capacitance is changed by switching between two load capacitance values using a modulation signal with a programmable duty cycle. In order to compensate the spread of the quartz parameters every chip is factory calibrated. The frequency accuracy can be evaluated by measuring the frequency of the square wave signal available at the output pin CLKOUT. However, the selection of fCLKOUT = 32.768 kHz (default value) leads to inaccurate measurements. Accurate frequency measurement occurs when fCLKOUT = 16.384 kHz or lower is selected (see Table 14). 7.3.1.1 Temperature measurement The PCF2129 has a temperature sensor circuit used to perform the temperature compensation of the frequency. The temperature is measured immediately after poweron and then periodically with a period set by the temperature conversion rate TCR[1:0] in the register CLKOUT_ctl. Table 13. Temperature measurement period TCR[1:0] Temperature measurement period [1] 00 4 min 01 2 min 10 1 min 11 30 seconds [1] Default value. 7.3.2 OTP refresh Each IC is calibrated during production and testing of the device. The calibration parameters are stored on EPROM cells called One Time Programmable (OTP) cells. It is recommended to process an OTP refresh once after the power is up and the oscillator is operating stable. The OTP refresh takes less than 100 ms to complete. To perform an OTP refresh, bit OTPR has to be cleared (set to logic 0) and then set to logic 1 again. 7.3.3 Clock output A programmable square wave is available at pin CLKOUT. Operation is controlled by the COF[2:0] control bits in register CLKOUT_ctl. Frequencies of 32.768 kHz (default) down to 1 Hz can be generated for use as system clock, microcontroller clock, charge pump input, or for calibrating the oscillator. CLKOUT is an open-drain output and enabled at power-on. When disabled, the output is high-impedance. Table 14. CLKOUT frequency selection COF[2:0] CLKOUT frequency (Hz) Typical duty cycle 32 768 60 : 40 to 40 : 60 001 16 384 50 : 50 010 8 192 50 : 50 011 4 096 50 : 50 100 2 048 50 : 50 000 PCF2129 Product data sheet [2][3] All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 [1] © 2022 NXP B.V. All rights reserved. 12 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 14. CLKOUT frequency selection...continued COF[2:0] CLKOUT frequency (Hz) Typical duty cycle 101 1 024 50 : 50 110 1 50 : 50 111 CLKOUT = high-Z - [1] [2] [3] [1] Duty cycle definition: % HIGH-level time : % LOW-level time. Default value. The specified accuracy of the RTC can be only achieved with CLKOUT frequencies not equal to 32.768 kHz or if CLKOUT is disabled. The duty cycle of the selected clock is not controlled, however, due to the nature of the clock generation all but the 32.768 kHz frequencies are 50 : 50. 7.4 Register Aging_offset Table 15. Aging_offset - crystal aging offset register (address 19h) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bit 7 6 5 4 Symbol - - - - Reset value - - - - 3 2 1 0 0 0 AO[3:0] 1 0 Table 16. Aging_offset - crystal aging offset register (address 19h) bit description Bit positions labeled as - are not implemented and return 0 when read. Bit Symbol Value Description 7 to 4 - - unused 3 to 0 AO[3:0] see Table 17 aging offset value 7.4.1 Crystal aging correction 2 The PCF2129 has an offset register Aging_offset to correct the crystal aging effects . The accuracy of the frequency of a quartz crystal depends on its aging. The aging offset adds an adjustment, positive or negative, in the temperature compensation circuit which allows correcting the aging effect. At 25 °C, the aging offset bits allow a frequency correction of typically 1 ppm per AO[3:0] value, from -7 ppm to +8 ppm. Table 17. Frequency correction at 25 °C, typical AO[3:0] ppm Decimal Binary 0 0000 +8 1 0001 +7 2 0010 +6 2 For further information, refer to the application note [1]. PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 13 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 17. Frequency correction at 25 °C, typical...continued AO[3:0] ppm Decimal Binary 3 0011 +5 4 0100 +4 5 0101 +3 6 0110 +2 7 0111 +1 [1] 8 1000 9 1001 -1 10 1010 -2 11 1011 -3 12 1100 -4 13 1101 -5 14 1110 -6 15 1111 -7 [1] 0 Default value. 7.5 Power management functions The PCF2129 has two power supplies: VDD the main power supply VBAT the battery backup supply Internally, the PCF2129 is operating with the internal operating voltage Voper(int) which is also available as VBBS on the battery backed output voltage pin, BBS. Depending on the condition of the main power supply and the selected power management function, Voper(int) is either on the potential of VDD or VBAT (see Section 7.5.3). Two power management functions are implemented: Battery switch-over function monitoring the main power supply VDD and switching to VBAT in case a power fail condition is detected (see Section 7.5.1). Battery low detection function monitoring the status of the battery, VBAT (see Section 7.5.2). The power management functions are controlled by the control bits PWRMNG[2:0] (see Table 18) in register Control_3 (see Table 10): PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 14 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 18. Power management control bit description PWRMNG[2:0] Function [1] 000 battery switch-over function is enabled in standard mode; battery low detection function is enabled 001 battery switch-over function is enabled in standard mode; battery low detection function is disabled 010 battery switch-over function is enabled in standard mode; battery low detection function is disabled 011 battery switch-over function is enabled in direct switching mode; battery low detection function is enabled 100 battery switch-over function is enabled in direct switching mode; battery low detection function is disabled 101 battery switch-over function is enabled in direct switching mode; battery low detection function is disabled [2] 111 [1] [2] battery switch-over function is disabled, only one power supply (VDD); battery low detection function is disabled Default value. When the battery switch-over function is disabled, the PCF2129 works only with the power supply VDD. VBAT must be put to ground and the battery low detection function is disabled. 7.5.1 Battery switch-over function The PCF2129 has a backup battery switch-over circuit which monitors the main power supply VDD. When a power failure condition is detected, it automatically switches to the backup battery. One of two operation modes can be selected: Standard mode the power failure condition happens when: VDD < VBAT AND VDD < Vth(sw)bat Vth(sw)bat is the battery switch threshold voltage. Typical value is 2.5 V. The battery switch-over in standard mode works only for VDD > 2.5 V Direct switching mode the power failure condition happens when VDD < VBAT. Direct switching from VDD to VBAT without requiring VDD to drop below Vth(sw)bat When a power failure condition occurs and the power supply switches to the battery, the following sequence occurs: 1. The battery switch flag BF (register Control_3) is set logic 1. 2. An interrupt is generated if the control bit BIE (register Control_3) is enabled (see Section 7.12.6). 3. If the control bit BTSE (register Control_3) is logic 1, the timestamp registers store the time and date when the battery switch occurred (see Section 7.11.4). 4. The battery switch flag BF is cleared by command; it must be cleared to clear the interrupt. PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 15 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications The interface is disabled in battery backup operation: • Interface inputs are not recognized, preventing extraneous data being written to the device • Interface outputs are high-impedance 2 For further information about I C-bus communication and battery backup operation, see Section 8.3. 7.5.1.1 Standard mode If VDD > VBAT OR VDD > Vth(sw)bat: Voper(int) is at VDD potential. If VDD < VBAT AND VDD < Vth(sw)bat: Voper(int) is at VBAT potential. backup battery operation VDD Voper(int) VBAT Voper(int) internal operating voltage (Voper(int)) Vth(sw)bat (= 2.5 V) VDD (= 0 V) BF INT cleared via interface 001aaj311 Vth(sw)bat is the battery switch threshold voltage. Typical value is 2.5 V. In standard mode, the battery switch-over works only for VDD > 2.5 V. VDD may be lower than VBAT (for example VDD = 3 V, VBAT = 4.1 V). Figure 6. Battery switch-over behavior in standard mode with bit BIE set logic 1 (enabled) 7.5.1.2 Direct switching mode If VDD > VBAT: Voper(int) is at VDD potential. If VDD < VBAT: Voper(int) is at VBAT potential. The direct switching mode is useful in systems where VDD is always higher than VBAT. This mode is not recommended if the VDD and VBAT values are similar (for example, VDD = 3.3 V, VBAT ≥ 3.0 V). In direct switching mode, the power consumption is reduced compared to the standard mode because the monitoring of VDD and Vth(sw)bat is not performed. PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 16 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications backup battery operation VDD Voper(int) VBAT Voper(int) internal operating voltage (Voper(int)) Vth(sw)bat (= 2.5 V) VDD (= 0 V) BF INT cleared via interface 001aaj312 Figure 7. Battery switch-over behavior in direct switching mode with bit BIE set logic 1 (enabled) 7.5.1.3 Battery switch-over disabled: only one power supply (VDD) When the battery switch-over function is disabled: • • • • The power supply is applied on the VDD pin The VBAT pin must be connected to ground Voper(int) is at VDD potential The battery flag (BF) is always logic 0 7.5.1.4 Battery switch-over architecture The architecture of the battery switch-over circuit is shown in Figure 8. comparators logic switches VDD Vth(sw)bat VDD Voper(int) LOGIC Vth(sw)bat VBAT VBAT 001aag061 Figure 8. Battery switch-over circuit, simplified block diagram Voper(int) is at VDD or VBAT potential. Remark: It has to be assured that there are decoupling capacitors on the pins VDD, VBAT, and BBS. 7.5.2 Battery low detection function The PCF2129 has a battery low detection circuit which monitors the status of the battery VBAT. PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 17 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications When VBAT drops below the threshold value Vth(bat)low (typically 2.5 V), the BLF flag (register Control_3) is set to indicate that the battery is low and that it must be replaced. Monitoring of the battery voltage also occurs during battery operation. An unreliable battery cannot prevent that the supply voltage drops below Vlow (typical 1.2 V) and with that the data integrity gets lost. (For further information about Vlow see Section 7.6.) When VBAT drops below the threshold value Vth(bat)low, the following sequence occurs (see Figure 9): 1. The battery low flag BLF is set logic 1. 2. An interrupt is generated if the control bit BLIE (register Control_3) is enabled (see Section 7.12.7). 3. The flag BLF remains logic 1 until the battery is replaced. BLF cannot be cleared by command. It is automatically cleared by the battery low detection circuit when the battery is replaced or when the voltage rises again above the threshold value. This could happen if a super capacitor is used as a backup source and the main power is applied again. VDD = Voper(int) internal operating voltage (Voper(int)) VBAT Vth(bat)low (= 2.5 V) VBAT BLF INT 001aaj322 Figure 9. Battery low detection behavior with bit BLIE set logic 1 (enabled) 7.5.3 Battery backup supply The VBBS voltage on the output pin BBS is at the same potential as the internal operating voltage Voper(int), depending on the selected battery switch-over function mode: Table 19. Output pin BBS Battery switch-over function mode Conditions Potential of Voper(int) and VBBS standard VDD > VBAT OR VDD > Vth(sw)bat VDD VDD < VBAT AND VDD < Vth(sw)bat VBAT VDD > VBAT VDD direct switching PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 18 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 19. Output pin BBS...continued Battery switch-over function mode disabled Conditions Potential of Voper(int) and VBBS VDD < VBAT VBAT only VDD available, VBAT must be put to ground VDD The output pin BBS can be used as a supply for external devices with battery backup needs, such as SRAM (see [1]). For this case, Figure 10 shows the typical driving capability when VBBS is driven from VDD. 001aaj327 0 VBBS - VDD (mV) - 200 VDD = 4.2 V - 400 VDD = 3 V VDD = 2 V - 600 - 800 0 2 4 6 IBBS (mA) 8 Figure 10. Typical driving capability of VBBS: (VBBS - VDD) with respect to the output load current IBBS 7.6 Oscillator stop detection function The PCF2129 has an on-chip oscillator detection circuit which monitors the status of the oscillation: whenever the oscillation stops, a reset occurs and the oscillator stop flag OSF (in register Seconds) is set logic 1. • Power-on: 1. The oscillator is not running, the chip is in reset (OSF is logic 1). 2. When the oscillator starts running and is stable after power-on, the chip exits from reset. 3. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) by command. • Power supply failure: 1. When the power supply of the chip drops below a certain value (Vlow), typically 1.2 V, the oscillator stops running and a reset occurs. 2. When the power supply returns to normal operation, the oscillator starts running again, the chip exits from reset. 3. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) by command. PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 19 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications VDD Voper(int) VDD Voper(int) VBAT VBAT Vth(sw)bat (= 2.5 V) Vlow (= 1.2 V) VDD VDD battery discharge Voper(int) VBAT VSS VSS (1) (2) OSF 001aaj409 1. Theoretical state of the signals since there is no power. 2. The oscillator stop flag (OSF), set logic 1, indicates that the oscillation has stopped and a reset has occurred since the flag was last cleared (OSF set logic 0). In this case, the integrity of the clock information is not guaranteed. The OSF flag is cleared by command. Figure 11. Power failure event due to battery discharge: reset occurs 7.7 Reset function The PCF2129 has a Power-On Reset (POR) and a Power-On Reset Override (PORO) function implemented. 7.7.1 Power-On Reset (POR) The POR is active whenever the oscillator is stopped. The oscillator is considered to be stopped during the time between power-on and stable crystal resonance (see Figure 12). This time may be in the range of 200 ms to 2 s depending on temperature and supply voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF set logic 1). The OTP refresh (see Section 7.3.2) should ideally be executed as the first instruction after start-up and also after a reset due to an oscillator stop. PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 20 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications chip in reset chip not in reset chip fully operative CLKOUT available VDD oscillation internal reset OTPR t aaa-015298 Figure 12. Dependency between POR and oscillator After POR, the following mode is entered: • • • • • 32.768 kHz CLKOUT active Power-On Reset Override (PORO) available to be set 24-hour mode is selected Battery switch-over is enabled Battery low detection is enabled The register values after power-on are shown in Table 4. 7.7.2 Power-On Reset Override (PORO) The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and therefore speed up the on-board test of the device. OSCILLATOR SCL SDA/CE RESET OVERRIDE osc stopped 0 = stopped, 1 = running reset 0 = override inactive 1 = override active CLEAR POR_OVRD 0 = clear override mode 1 = override possible 001aaj324 Figure 13. Power-On Reset (POR) system The setting of the PORO mode requires that POR_OVRD in register Control_1 is set logic 1 and that the signals at the interface pins SDA/CE and SCL are toggled as illustrated in Figure 14. All timings shown are required minimum. PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 21 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications power up 8 ms minimum 500 ns minimum 2000 ns SDA/CE SCL reset override 001aaj326 2 Figure 14. Power-On Reset Override (PORO) sequence, valid for both I C-bus and SPI-bus Once the override mode is entered, the device is immediately released from the reset state and the set-up operation can commence. The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0 during normal operation has no effect except to prevent accidental entry into the PORO mode. 7.8 Time and date function Most of these registers are coded in the Binary Coded Decimal (BCD) format. 7.8.1 Register Seconds Table 20. Seconds - seconds and clock integrity register (address 03h) bit allocation Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 Symbol 6 5 4 3 OSF Reset value 2 1 0 X X X SECONDS (0 to 59) 1 X X X X Table 21. Seconds - seconds and clock integrity register (address 03h) bit description Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Place value Description 7 OSF 0 - clock integrity is guaranteed 1 - clock integrity is not guaranteed: oscillator has stopped and chip reset has occurred since flag was last cleared 0 to 5 ten’s place actual seconds coded in BCD format 0 to 9 unit place 6 to 4 SECONDS 3 to 0 Table 22. Seconds coded in BCD format PCF2129 Product data sheet Seconds value in decimal Upper-digit (ten’s place) Digit (unit place) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0 0 0 0 0 0 0 All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 22 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 22. Seconds coded in BCD format...continued Seconds value in decimal Upper-digit (ten’s place) Digit (unit place) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 01 0 0 0 0 0 0 1 02 0 0 0 0 0 1 0 : : : : : : : : 09 0 0 0 1 0 0 1 10 0 0 1 0 0 0 0 : : : : : : : : 58 1 0 1 1 0 0 0 59 1 0 1 1 0 0 1 7.8.2 Register Minutes Table 23. Minutes - minutes register (address 04h) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 Symbol - Reset value - 6 5 4 3 2 1 0 X X X MINUTES (0 to 59) X X X X Table 24. Minutes - minutes register (address 04h) bit description Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Place value Description 7 - - - unused 6 to 4 MINUTES 0 to 5 ten’s place actual minutes coded in BCD format 0 to 9 unit place 3 to 0 7.8.3 Register Hours Table 25. Hours - hours register (address 05h) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 6 5 4 Symbol - - AMPM 3 2 1 0 HOURS (1 to 12) in 12-hour mode HOURS (0 to 23) in 24-hour mode Reset value PCF2129 Product data sheet - - X X X All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 X X X © 2022 NXP B.V. All rights reserved. 23 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 26. Hours - hours register (address 05h) bit description Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Place value Description 7 to 6 - - - unused 0 - indicates AM 1 - indicates PM 0 to 1 ten’s place 0 to 9 unit place actual hours coded in BCD format when in 12-hour mode 0 to 2 ten’s place 0 to 9 unit place [1] 12-hour mode 5 AMPM 4 HOURS 3 to 0 [1] 24-hour mode 5 to 4 HOURS 3 to 0 [1] actual hours coded in BCD format when in 24-hour mode Hour mode is set by the bit 12_24 in register Control_1 (see Table 6). 7.8.4 Register Days Table 27. Days - days register (address 06h) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 6 Symbol - - Reset value - - 5 4 3 2 1 0 X X DAYS (1 to 31) X X X X Table 28. Days - days register (address 06h) bit description Bit Symbol Value Place value Description 7 to 6 - - - unused 0 to 3 ten’s place actual day coded in BCD format 0 to 9 unit place 5 to 4 [1] DAYS 3 to 0 [1] th If the year counter contains a value which is exactly divisible by 4, including the year 00, the RTC compensates for leap years by adding a 29 day to February. 7.8.5 Register Weekdays Table 29. Weekdays - weekdays register (address 07h) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 6 5 4 3 Symbol - - - - - Reset value - - - - - PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 2 1 0 WEEKDAYS (0 to 6) X X X © 2022 NXP B.V. All rights reserved. 24 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 30. Weekdays - weekdays register (address 07h) bit description Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Description 7 to 3 - - unused 2 to 0 WEEKDAYS 0 to 6 actual weekday value, see Table 31 Although the association of the weekdays counter to the actual weekday is arbitrary, the PCF2129 assumes that Sunday is 000 and Monday is 001 for the purpose of determining the increment for calendar weeks. Table 31. Weekday assignments Day [1] Bit 2 1 0 Sunday 0 0 0 Monday 0 0 1 Tuesday 0 1 0 Wednesday 0 1 1 Thursday 1 0 0 Friday 1 0 1 Saturday 1 1 0 [1] Definition may be reassigned by the user. 7.8.6 Register Months Table 32. Months - months register (address 08h) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 6 5 Symbol - - - Reset value - - - 4 3 2 1 0 X X MONTHS (1 to 12) X X X Table 33. Months - months register (address 08h) bit description Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Place value Description 7 to 5 - - - unused 4 MONTHS 0 to 1 ten’s place actual month coded in BCD format, see Table 34 0 to 9 unit place 3 to 0 PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 25 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 34. Month assignments in BCD format Upper-digit (ten’s place) Digit (unit place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 January 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April 0 0 1 0 0 May 0 0 1 0 1 June 0 0 1 1 0 July 0 0 1 1 1 August 0 1 0 0 0 September 0 1 0 0 1 October 1 0 0 0 0 November 1 0 0 0 1 December 1 0 0 1 0 Month 7.8.7 Register Years Table 35. Years - years register (address 09h) bit allocation Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 6 5 Symbol 4 3 2 1 0 X X X YEARS (0 to 99) Reset value X X X X X Table 36. Years - years register (address 09h) bit description Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Place value Description 7 to 4 YEARS 0 to 9 ten’s place 0 to 9 unit place 3 to 0 actual year coded in BCD format 7.8.8 Setting and reading the time Figure 15 shows the data flow and data dependencies starting from the 1 Hz clock tick. During read/write operations, the time counting circuits (memory locations 03h through 09h) are blocked. This prevents • Faulty reading of the clock and calendar during a carry condition • Incrementing the time registers during the read cycle PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 26 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 1 Hz tick SECONDS MINUTES 12_24 hour mode HOURS LEAP YEAR CALCULATION DAYS WEEKDAY MONTHS YEARS 001aaf901 Figure 15. Data flow of the time function After this read/write access is completed, the time circuit is released again. Any pending request to increment the time counters that occurred during the read/write access is serviced. A maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see Figure 16). t 2.0 V VIH HIGH-level input voltage ILI input leakage current VI = VDD or VSS post ESD event Ci [5] input capacitance Outputs VO output voltage VOH HIGH output voltage on pin SDO 0.8VDD - VDD V VOL LOW output voltage on pins CLKOUT, INT, and SDO VSS - 0.2VDD V IOL LOW-level output current output sink current; VOL = 0.4 V 3 17 - mA 1.0 - - mA on pin SDA/CE on all other outputs PCF2129 Product data sheet [6] All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 55 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 78. Static characteristics...continued VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = -40 °C to +85 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IOH HIGH-level output current output source current; on pin SDO; VOH = 3.8 V; VDD = 4.2 V 1.0 - - mA ILO output leakage current VO = VDD or VSS - 0 - μA -1 - +1 μA post ESD event [1] [2] [3] [4] [5] [6] For reliable oscillator start-up at power-on: VDD(po)min = VDD(min) + 0.3 V. 1 Timer source clock = ⁄60 Hz, level of pins SDA/CE, SDI, and SCL is VDD or VSS. When the device is supplied by the VBAT pin instead of the VDD pin, the current values for IBAT are as specified for IDD under the same conditions. 2 The I C-bus and SPI-bus interfaces of PCF2129 are 5 V tolerant. Tested on sample basis. For further information, see Figure 40. 12.1 Current consumption characteristics, typical 001aal763 22 IOL (mA) 18 14 10 6 1.5 2.5 3.5 VDD (V) 4.5 Typical value; VOL = 0.4 V. Figure 40. IOL on pin SDA/CE PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 56 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 001aaj432 2.0 IDD (µA) 1.6 1.2 VDD = 3 V VDD = 2 V 0.8 0.4 0 - 40 - 20 0 20 40 60 80 100 Temperature (°C) CLKOUT disabled; PWRMNG[2:0] = 111; TSOFF = 1; TS input floating. Figure 41. IDD as a function of temperature PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 57 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 001aaj433 2.0 IDD (µA) 1.6 1.2 CLKOUT enabled at 32 kHz 0.8 CLKOUT OFF 0.4 0 1.8 2.2 2.6 3.0 3.4 3.8 VDD (V) 4.2 a. PWRMNG[2:0] = 111; TSOFF = 1; Tamb = 25 °C; TS input floating 001aaj434 4.0 IDD (µA) 3.2 CLKOUT enabled at 32 kHz 2.4 CLKOUT OFF 1.6 0.8 0 1.8 2.2 2.6 3.0 3.4 3.8 VDD (V) 4.2 b. PWRMNG[2:0] = 000; TSOFF = 0; Tamb = 25 °C; TS input floating Figure 42. IDD as a function of VDD PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 58 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 3 IDD (µA) (6) (3) 2.5 (2) 2 (5) (5) (5) (1) (6) 1.5 (4) (5) (3) 1 (4) (5) (5) (4) (4) (4) (6) (6) (6) (6) (2) (4) (1) 0.5 0 111 110 101 100 011 010 001 PWRMG[2:0] 000 aaa-013877 Interface inactive; Tamb = 25 °C; VBAT = 0 V; default configuration. Description of the PWRMNG[2:0] settings, see Table 18. 1. VDD = 1.8 V. 2. VDD = 3.3 V. 3. VDD = 4.2 V. 4. VDD or VBAT = 1.8 V. 5. VDD or VBAT = 3.3 V. 6. VDD or VBAT = 4.2 V. Figure 43. Typical IDD as a function of the power management settings 12.2 Frequency characteristics Table 79. Frequency characteristics VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = +25 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit fo output frequency on pin CLKOUT; VDD or VBAT = 3.3 V; COF[2:0] = 000; AO[3:0] = 1000 - 32.768 - kHz Δf/f frequency stability VDD or VBAT = 3.3 V PCF2129AT Tamb = -15 °C to +60 °C [1][2] - ±3 ±5 ppm Tamb = -25 °C to -15 °C and Tamb = +60 °C to +65 °C [1][2] - ±5 ±10 ppm Tamb = -30 °C to +80 °C [1][2] - ±3 ±8 ppm Tamb = -40 °C to -30 °C and Tamb = +80 °C to +85 °C [1][2] - ±5 ±15 ppm PCF2129T PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 59 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 79. Frequency characteristics...continued VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = +25 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Δfxtal/fxtal relative crystal frequency variation crystal aging [3] - - ±3 ppm [3] - - ±3 ppm ten years - - ±8 ppm on pin CLKOUT - ±1 - ppm/V PCF2129AT first year; VDD or VBAT = 3.3 V PCF2129T first year Δf/ΔV [1] [2] [3] frequency variation with voltage ±1 ppm corresponds to a time deviation of ±0.0864 seconds per day. Only valid if CLKOUT frequencies are not equal to 32.768 kHz or if CLKOUT is disabled. Not production tested. Effects of reflow soldering are included (see [1]). 013aaa593 40 Frequency stability (ppm) ± 5 ppm ± 3 ppm ± 5 ppm 0 (1) -40 (2) -80 -40 -20 0 20 40 60 80 100 Temperature (°C) 1. Typical temperature compensated frequency response. 2. Uncompensated typical tuning-fork crystal frequency. Figure 44. Typical characteristic of frequency with respect to temperature of PCF2129AT PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 60 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 013aaa345 40 Frequency stability (ppm) ± 5 ppm ± 3 ppm ± 5 ppm 0 (1) -40 (2) -80 -40 -20 0 20 40 60 80 100 Temperature (°C) 1. Typical temperature compensated frequency response. 2. Uncompensated typical tuning-fork crystal frequency. Figure 45. Typical characteristic of frequency with respect to temperature of PCF2129T 13 Dynamic characteristics 13.1 SPI-bus timing characteristics Table 80. SPI-bus characteristics VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = -40 °C to +85 °C, unless otherwise specified. All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD (see Figure 46). Symbol Parameter Conditions VDD = 1.8 V VDD = 4.2 V Min Max Min Max Unit Pin SCL fclk(SCL) SCL clock frequency - 2.0 - 6.5 MHz tSCL SCL time 800 - 140 - ns tclk(H) clock HIGH time 100 - 70 - ns tclk(L) clock LOW time 400 - 70 - ns tr rise time for SCL signal - 100 - 100 ns tf fall time for SCL signal - 100 - 100 ns Pin SDA/CE tsu(CE_N) CE_N set-up time 60 - 30 - ns th(CE_N) CE_N hold time 40 - 25 - ns trec(CE_N) CE_N recovery time 100 - 30 - ns tw(CE_N) CE_N pulse width - 0.99 - 0.99 s 70 - 20 - ns Pin SDI tsu set-up time PCF2129 Product data sheet set-up time for SDI data All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 61 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 80. SPI-bus characteristics...continued VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = -40 °C to +85 °C, unless otherwise specified. All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD (see Figure 46). Symbol th Parameter Conditions hold time hold time for SDI data SDO read delay time CL = 50 pF VDD = 1.8 V VDD = 4.2 V Unit Min Max Min Max 70 - 20 - ns - 225 - 55 ns - 90 - 25 ns 0 - 0 - ns Pin SDO td(R)SDO [1] tdis(SDO) SDO disable time tt(SDI-SDO) transition time from SDI to SDO [1] to avoid bus conflict No load value; bus is held up by bus capacitance; use RC time constant with application values. tw(CE_N) CE tsu(CE_N) tr tf tclk(SCL) th(CE_N) trec(CE_N) 80% SCL 20% tclk(H) WRITE SDI SDO tsu tclk(L) th R/W SA2 RA0 b6 b0 b7 b6 b0 high-Z READ SDI b7 tt(SDI-SDO) SDO high-Z td(R)SDO b7 tdis(SDO) b6 b0 013aaa152 Figure 46. SPI-bus timing PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 62 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 2 13.2 I C-bus timing characteristics 2 Table 81. I C-bus characteristics All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to 30 % and 70 % with an input voltage swing of VSS to VDD (see Figure 47). Symbol Parameter Standard mode Fast-mode (Fm) Unit Min Max Min Max 0 100 0 400 kHz Pin SCL [1] fSCL SCL clock frequency tLOW LOW period of the SCL clock 4.7 - 1.3 - μs tHIGH HIGH period of the SCL clock 4.0 - 0.6 - μs Pin SDA/CE tSU;DAT data set-up time 250 - 100 - ns tHD;DAT data hold time 0 - 0 - ns Pins SCL and SDA/CE tBUF bus free time between a STOP and START condition 4.7 - 1.3 - μs tSU;STO set-up time for STOP condition 4.0 - 0.6 - μs tHD;STA hold time (repeated) START condition 4.0 - 0.6 - μs tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - μs tr rise time of both SDA and SCL signals [2][3][4] - 1 000 20 + 0.1Cb 300 ns tf fall time of both SDA and SCL signals [2][3][4] - 300 20 + 0.1Cb 300 ns tVD;ACK data valid acknowledge time [5] 0.1 3.45 0.1 0.9 μs data valid time [6] 300 - 75 - ns pulse width of spikes that must be suppressed by the input filter [7] - 50 - 50 ns tVD;DAT tSP [1] [2] [3] [4] [5] [6] [7] The minimum SCL clock frequency is limited by the bus time-out feature which resets the serial bus interface if either the SDA or SCL is held LOW for a minimum of 25 ms. The bus time-out feature must be disabled for DC operation. A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. Cb is the total capacitance of one bus line in pF. The maximum tf for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, tf is 250 ns. This allows series protection resistors to be connected between the SDA/CE pin, the SCL pin, and the SDA/SCL bus lines without exceeding the maximum tf. tVD;ACK is the time of the acknowledgement signal from SCL LOW to SDA (out) LOW. tVD;DAT is the minimum time for valid SDA (out) data following SCL LOW. Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns. PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 63 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications START CONDITION (S) PROTOCOL tSU;STA BIT 7 MSB (A7) tLOW BIT 6 (A6) tHIGH BIT 0 LSB (R/W) ACKNOWLEDGE (A) STOP CONDITION (P) 1 / fSCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tSU;STO mbd820 2 Figure 47. I C-bus timing diagram; rise and fall times refer to 30 % and 70 % 14 Application information 100 nF VDD SCL SDI Interface 330 Ω SDO I2C SPI VDD 100 nF VBAT SDA/CE BBS 6.8 µF BBS IFS 1 to 100 nF BBS PCF2129 TS INT INT RPU VDD 220 kΩ Ci VSS CLKOUT CLKOUT RPU VDD aaa-015370 Ci: In case mechanical switches are used, a capacitor of 1 nF is recommended. RPU: For example, 10 kΩ. Figure 48. General application diagram For information about application configuration, see [1]. PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 64 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 15 Test information 15.1 Quality information UL Component Recognition This (component or material) is Recognized by UL. Representative samples of this component have been evaluated by UL and meet applicable UL requirements. PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 65 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 16 Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE v M A Z 20 11 Q A2 A (A 3 ) A1 pin 1 index θ Lp L 1 10 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.1 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Figure 49. Package outline SOT163-1 (SO20) of PCF2129AT PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 66 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 D E A X c HE y v M A Z 16 9 Q A2 A (A 3 ) A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 10.5 10.1 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.1 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.41 0.40 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT162-1 075E03 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Figure 50. Package outline SOT162-1 (SO16) of PCF2129T PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 67 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 17 Packing information 17.1 Tape and reel information For tape and reel packing information, see • [5] for the PCF2129T. • [6] for the PCF2129AT. 18 Soldering For information about soldering, see [1]. 18.1 Footprint information 13.40 0.60 (20×) 1.50 8.00 11.00 11.40 1.27 (18×) solder lands occupied area placement accuracy ± 0.25 Dimensions in mm sot163-1_fr Figure 51. Footprint information for reflow soldering of SOT163-1 (SO20) of PCF2129AT PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 68 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Footprint information for reflow soldering of SO16 package SOT162-1 Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 1.270 P2 Ay 1.320 11.200 By C D1 6.400 2.400 0.700 D2 Gx 0.800 10.040 Gy Hx Hy 8.600 11.900 11.450 sot162-1_fr Figure 52. Footprint information for reflow soldering of SOT162-1 (SO16) of PCF2129T 19 Appendix PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 69 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 19.1 Real-Time Clock selection PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 70 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 82. Selection of Real-Time Clocks Type name Alarm, Timer, Watchdog Interrupt output Interface IDD, typical (nA) Battery backup Timestamp, tamper input AEC-Q100 compliant Special features Packages PCF8563 X 1 I C 2 250 - - - - SO8, TSSOP8, HVSON10 PCF8564A X 1 I C 2 250 - - - integrated oscillator caps WLCSP 2 PCA8565 X 1 I C 600 - - grade 1 high robustness, Tamb= -40 °C to 125 °C TSSOP8, HVSON10 PCA8565A X 1 I C 2 600 - - - integrated oscillator caps, Tamb= -40 °C to 125 °C WLCSP PCF85063 - 1 I C 2 220 - - - basic functions only, no alarm HXSON8 2 PCF85063A X 1 I C 220 - - - tiny package SO8, DFN2626-10 PCF85063B X 1 SPI 220 - - - tiny package DFN2626-10 PCF85263A X 2 I C 230 X X - time stamp, battery backup, 1 stopwatch ⁄100 s SO8, TSSOP10, TSSOP8, DFN2626-10 PCF85263B X 2 SPI 230 X X - time stamp, battery backup, 1 stopwatch ⁄100s TSSOP10, DFN2626-10 PCF85363A X 2 I C 230 X X - time stamp, battery backup, 1 stopwatch ⁄100s, 64 Byte RAM TSSOP10, DFN2626-10 PCF85363B X 2 SPI 230 X X - time stamp, battery backup, 1 stopwatch ⁄100s, 64 Byte RAM TSSOP10, DFN2626-10 PCF8523 X 2 I C 150 X - - lowest power 150 nA in operation, FM+ 1 MHz SO8, HVSON8, TSSOP14, WLCSP PCF2123 X 1 SPI 100 - - - lowest power 100 nA in operation TSSOP14, HVQFN16 PCF2127 X 1 I C and SPI 2 500 X X - temperature compensated, SO16 quartz built in, calibrated, 512 Byte RAM PCF2127A X 1 I C and SPI 2 500 X X - temperature compensated, SO20 quartz built in, calibrated, 512 Byte RAM PCF2129 Product data sheet 2 2 2 All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 71 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Table 82. Selection of Real-Time Clocks...continued Type name Alarm, Timer, Watchdog Interrupt output Interface PCF2129 X 1 I C and SPI PCF2129A X 1 I C and SPI PCA2129 X 1 PCA21125 X 1 PCF2129 Product data sheet IDD, typical (nA) Battery backup Timestamp, tamper input AEC-Q100 compliant Special features Packages 2 500 X X - temperature compensated, quartz built in, calibrated SO16 2 500 X X - temperature compensated, quartz built in, calibrated SO20 I C and SPI 2 500 X X grade 3 temperature compensated, quartz built in, calibrated SO16 SPI 820 - - grade 1 high robustness, Tamb= -40 °C to 125 °C TSSOP14 All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 72 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 20 Abbreviations Table 83. Abbreviations Acronym Description AM Ante Meridiem BCD Binary Coded Decimal CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DC Direct Current GPS Global Positioning System HBM Human Body Model 2 I C Inter-Integrated Circuit IC Integrated Circuit LSB Least Significant Bit MCU Microcontroller Unit MM Machine Model MSB Most Significant Bit PM Post Meridiem POR Power-On Reset PORO Power-On Reset Override PPM Parts Per Million RC Resistance-Capacitance RTC Real-Time Clock SCL Serial CLock line SDA Serial DAta line SPI Serial Peripheral Interface SRAM Static Random Access Memory TCXO Temperature Compensated Xtal Oscillator Xtal crystal 21 References [1] [2] [3] [4] [5] PCF2129 Product data sheet AN11186 Application and soldering information for the PCA2129 and PCF2129 TCXO RTC JESD22-A114 Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) JESD22-C101 Field-Induced Charged-Device Model Test Method for ElectrostaticDischarge-Withstand Thresholds of Microelectronic Components JESD78 IC Latch-Up Test SOT162-1_518 SO16; Reel pack; SMD, 13", packing information All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 73 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications [6] [7] [8] SOT163-1_518 SO20; Reel pack; SMD, 13", packing information 2 UM10204 I C-bus specification and user manual UM10569 Store and transport requirements 22 Revision history Table 84. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF2129 v.8 20220718 Product data sheet - PCF2129 v.7 Modifications: • Added UL certification information • Updated layout of Section 4 PCF2129 v.7 20141219 Product data sheet - PCF2129AT v.6 PCF2129T v.4 PCF2127AT v.6 20130711 Product data sheet - PCF2127AT v.5 PCF2129AT v.5 20130212 Product data sheet - PCF2129AT v.4 PCF2129AT v.4 20121107 Product data sheet - PCF2129AT v.3 PCF2129AT v.3 20121004 Product data sheet - PCF2129AT v.2 PCF2129AT v.2 20100507 Product data sheet - PCF2129AT v.1 PCF2129AT v.1 20100113 Product data sheet - - PCF2129T v.4 20130711 Product data sheet - PCF2129T v.3 PCF2129T v.3 20130212 Product data sheet - PCF2129T v.2 PCF2129T v.2 20121025 Product data sheet - PCF2129T v.1 PCF2129T v.1 20120618 Product data sheet - - PCF2129AT PCF2129T PCF2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 74 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 23 Legal information 23.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 23.2 Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 75 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. 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Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. 23.4 Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 76 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Tab. 6. Tab. 7. Tab. 8. Tab. 9. Tab. 10. Tab. 11. Tab. 12. Tab. 13. Tab. 14. Tab. 15. Tab. 16. Tab. 17. Tab. 18. Tab. 19. Tab. 20. Tab. 21. Tab. 22. Tab. 23. Tab. 24. Tab. 25. Tab. 26. Tab. 27. Tab. 28. Tab. 29. Tab. 30. Tab. 31. Tab. 32. Tab. 33. Tab. 34. Ordering information ..........................................2 Ordering options ................................................2 Pin description of PCF2129 .............................. 5 Register overview ..............................................7 Control_1 - control and status register 1 (address 00h) bit allocation ...............................9 Control_1 - control and status register 1 (address 00h) bit description .............................9 Control_2 - control and status register 2 (address 01h) bit allocation ............................. 10 Control_2 - control and status register 2 (address 01h) bit description ...........................10 Control_3 - control and status register 3 (address 02h) bit allocation ............................. 10 Control_3 - control and status register 3 (address 02h) bit description ...........................11 CLKOUT_ctl - CLKOUT control register (address 0Fh) bit allocation .............................11 CLKOUT_ctl - CLKOUT control register (address 0Fh) bit description ...........................11 Temperature measurement period .................. 12 CLKOUT frequency selection ..........................12 Aging_offset - crystal aging offset register (address 19h) bit allocation ............................. 13 Aging_offset - crystal aging offset register (address 19h) bit description ...........................13 Frequency correction at 25 °C, typical ............ 13 Power management control bit description ......15 Output pin BBS ............................................... 18 Seconds - seconds and clock integrity register (address 03h) bit allocation ................ 22 Seconds - seconds and clock integrity register (address 03h) bit description .............. 22 Seconds coded in BCD format ........................22 Minutes - minutes register (address 04h) bit allocation ......................................................... 23 Minutes - minutes register (address 04h) bit description ....................................................... 23 Hours - hours register (address 05h) bit allocation ......................................................... 23 Hours - hours register (address 05h) bit description ....................................................... 24 Days - days register (address 06h) bit allocation ......................................................... 24 Days - days register (address 06h) bit description ....................................................... 24 Weekdays - weekdays register (address 07h) bit allocation ............................................24 Weekdays - weekdays register (address 07h) bit description ..........................................25 Weekday assignments .................................... 25 Months - months register (address 08h) bit allocation ......................................................... 25 Months - months register (address 08h) bit description ....................................................... 25 Month assignments in BCD format ..................26 PCF2129 Product data sheet Tab. 35. Tab. 36. Tab. 37. Tab. 38. Tab. 39. Tab. 40. Tab. 41. Tab. 42. Tab. 43. Tab. 44. Tab. 45. Tab. 46. Tab. 47. Tab. 48. Tab. 49. Tab. 50. Tab. 51. Tab. 52. Tab. 53. Tab. 54. Tab. 55. Tab. 56. Tab. 57. Tab. 58. Tab. 59. Tab. 60. Tab. 61. Tab. 62. Tab. 63. Tab. 64. Years - years register (address 09h) bit allocation ......................................................... 26 Years - years register (address 09h) bit description ....................................................... 26 Second_alarm - second alarm register (address 0Ah) bit allocation .............................28 Second_alarm - second alarm register (address 0Ah) bit description .......................... 28 Minute_alarm - minute alarm register (address 0Bh) bit allocation .............................29 Minute_alarm - minute alarm register (address 0Bh) bit description .......................... 29 Hour_alarm - hour alarm register (address 0Ch) bit allocation ........................................... 29 Hour_alarm - hour alarm register (address 0Ch) bit description ......................................... 29 Day_alarm - day alarm register (address 0Dh) bit allocation ........................................... 30 Day_alarm - day alarm register (address 0Dh) bit description ......................................... 30 Weekday_alarm - weekday alarm register (address 0Eh) bit allocation .............................30 Weekday_alarm - weekday alarm register (address 0Eh) bit description .......................... 31 Watchdg_tim_ctl - watchdog timer control register (address 10h) bit allocation ................ 31 Watchdg_tim_ctl - watchdog timer control register (address 10h) bit description .............. 32 Watchdg_tim_val - watchdog timer value register (address 11h) bit allocation ................ 32 Watchdg_tim_val - watchdog timer value register (address 11h) bit description .............. 32 Programmable watchdog timer ....................... 32 Flag location in register Control_2 .................. 34 Example values in register Control_2 ..............34 Example to clear only AF (bit 4) ......................34 Example to clear only MSF (bit 7) ................... 35 Timestp_ctl - timestamp control register (address 12h) bit allocation ............................. 36 Timestp_ctl - timestamp control register (address 12h) bit description ...........................36 Sec_timestp - second timestamp register (address 13h) bit allocation ............................. 37 Sec_timestp - second timestamp register (address 13h) bit description ...........................37 Min_timestp - minute timestamp register (address 14h) bit allocation ............................. 37 Min_timestp - minute timestamp register (address 14h) bit description ...........................37 Hour_timestp - hour timestamp register (address 15h) bit allocation ............................. 37 Hour_timestp - hour timestamp register (address 15h) bit description ...........................38 Day_timestp - day timestamp register (address 16h) bit allocation ............................. 38 All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 77 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Tab. 65. Tab. 66. Tab. 67. Tab. 68. Tab. 69. Tab. 70. Tab. 71. Day_timestp - day timestamp register (address 16h) bit description ...........................38 Mon_timestp - month timestamp register (address 17h) bit allocation ............................. 39 Mon_timestp - month timestamp register (address 17h) bit description ...........................39 Year_timestp - year timestamp register (address 18h) bit allocation ............................. 39 Year_timestp - year timestamp register (address 18h) bit description ...........................39 Battery switch-over and timestamp ................. 39 Effect of bits MI and SI on pin INT and bit MSF ................................................................. 41 Tab. 72. Tab. 73. Tab. 74. Tab. 75. Tab. 76. Tab. 77. Tab. 78. Tab. 79. Tab. 80. Tab. 81. Tab. 82. Tab. 83. Tab. 84. First increment of time circuits after stop release .............................................................45 Interface selection input pin IFS ......................46 Serial interface ................................................ 47 Command byte definition ................................ 48 I2C slave address byte ................................... 51 Limiting values ................................................ 53 Static characteristics ....................................... 54 Frequency characteristics ............................... 59 SPI-bus characteristics ....................................61 I2C-bus characteristics ....................................63 Selection of Real-Time Clocks ........................ 71 Abbreviations ...................................................73 Revision history ...............................................74 Figures Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. Fig. 6. Fig. 7. Fig. 8. Fig. 9. Fig. 10. Fig. 11. Fig. 12. Fig. 13. Fig. 14. Fig. 15. Fig. 16. Fig. 17. Fig. 18. Fig. 19. Fig. 20. Fig. 21. Fig. 22. Fig. 23. Block diagram of PCF2129 ............................... 3 Pin configuration for PCF2129AT (SO20) ......... 4 Pin configuration for PCF2129T (SO16) ............4 Position of the stubs from the package assembly process ............................................. 4 Handling address registers ............................... 6 Battery switch-over behavior in standard mode with bit BIE set logic 1 (enabled) ........... 16 Battery switch-over behavior in direct switching mode with bit BIE set logic 1 (enabled) ......................................................... 17 Battery switch-over circuit, simplified block diagram ............................................................17 Battery low detection behavior with bit BLIE set logic 1 (enabled) ....................................... 18 Typical driving capability of VBBS: (VBBS - VDD) with respect to the output load current IBBS ....................................................19 Power failure event due to battery discharge: reset occurs ................................... 20 Dependency between POR and oscillator ....... 21 Power-On Reset (POR) system ...................... 21 Power-On Reset Override (PORO) sequence, valid for both I2C-bus and SPIbus ...................................................................22 Data flow of the time function ......................... 27 Access time for read/write operations ............. 27 Alarm function block diagram ..........................28 Alarm flag timing diagram ............................... 31 WD_CD set logic 1: watchdog activates an interrupt when timed out ................................. 33 Timestamp detection with two push-buttons on the TS pin (for example, for tamper detection) .........................................................35 Interrupt block diagram ................................... 41 INT example for SI and MI when TI_TP is logic 1 ..............................................................42 INT example for SI and MI when TI_TP is logic 0 ..............................................................42 PCF2129 Product data sheet Fig. 24. Fig. 25. Fig. 26. Fig. 27. Fig. 28. Fig. 29. Fig. 30. Fig. 31. Fig. 32. Fig. 33. Fig. 34. Fig. 35. Fig. 36. Fig. 37. Fig. 38. Fig. 39. Fig. 40. Fig. 41. Fig. 42. Fig. 43. Fig. 44. Fig. 45. Fig. 46. Fig. 47. Fig. 48. Fig. 49. Fig. 50. Fig. 51. Fig. 52. Example of shortening the INT pulse by clearing the MSF flag ......................................43 AF timing diagram ...........................................44 STOP bit functional diagram ........................... 45 STOP bit release timing .................................. 46 Interface selection ........................................... 47 SDI, SDO configurations ................................. 47 Data transfer overview .................................... 48 SPI-bus write example .................................... 49 SPI-bus read example .....................................49 Bit transfer .......................................................50 Definition of START and STOP conditions ...... 50 System configuration .......................................50 Acknowledgement on the I2C-bus .................. 51 Bus protocol, writing to registers ..................... 52 Bus protocol, reading from registers ............... 52 Device diode protection diagram of PCF2129 ......................................................... 53 IOL on pin SDA/CE .........................................56 IDD as a function of temperature .................... 57 IDD as a function of VDD ............................... 58 Typical IDD as a function of the power management settings ...................................... 59 Typical characteristic of frequency with respect to temperature of PCF2129AT ............60 Typical characteristic of frequency with respect to temperature of PCF2129T .............. 61 SPI-bus timing .................................................62 I2C-bus timing diagram; rise and fall times refer to 30 % and 70 % .................................. 64 General application diagram ........................... 64 Package outline SOT163-1 (SO20) of PCF2129AT ..................................................... 66 Package outline SOT162-1 (SO16) of PCF2129T ....................................................... 67 Footprint information for reflow soldering of SOT163-1 (SO20) of PCF2129AT ...................68 Footprint information for reflow soldering of SOT162-1 (SO16) of PCF2129T .....................69 All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 78 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.3 7.3.1 7.3.1.1 7.3.2 7.3.3 7.4 7.4.1 7.5 7.5.1 7.5.1.1 7.5.1.2 7.5.1.3 7.5.1.4 7.5.2 7.5.3 7.6 7.7 7.7.1 7.7.2 7.8 7.8.1 7.8.2 7.8.3 7.8.4 7.8.5 7.8.6 7.8.7 7.8.8 7.9 7.9.1 7.9.2 7.9.3 7.9.4 7.9.5 7.9.6 7.10 7.10.1 7.10.2 7.10.3 General description ............................................ 1 Features and benefits .........................................1 Applications .........................................................2 Ordering information .......................................... 2 Ordering options ................................................ 2 Block diagram ..................................................... 3 Pinning information ............................................ 4 Pinning ............................................................... 4 Pin description ................................................... 5 Functional description ........................................5 Register overview .............................................. 6 Control registers ................................................ 9 Register Control_1 .............................................9 Register Control_2 ...........................................10 Register Control_3 ...........................................10 Register CLKOUT_ctl ...................................... 11 Temperature compensated crystal oscillator ....11 Temperature measurement ..............................12 OTP refresh ..................................................... 12 Clock output .....................................................12 Register Aging_offset ...................................... 13 Crystal aging correction ...................................13 Power management functions ......................... 14 Battery switch-over function .............................15 Standard mode ................................................ 16 Direct switching mode ..................................... 16 Battery switch-over disabled: only one power supply (VDD) ........................................ 17 Battery switch-over architecture ...................... 17 Battery low detection function ..........................17 Battery backup supply ..................................... 18 Oscillator stop detection function .....................19 Reset function ..................................................20 Power-On Reset (POR) ...................................20 Power-On Reset Override (PORO) ................. 21 Time and date function .................................... 22 Register Seconds ............................................ 22 Register Minutes ..............................................23 Register Hours .................................................23 Register Days .................................................. 24 Register Weekdays ..........................................24 Register Months .............................................. 25 Register Years ................................................. 26 Setting and reading the time ........................... 26 Alarm function ..................................................27 Register Second_alarm ................................... 28 Register Minute_alarm .....................................29 Register Hour_alarm ........................................29 Register Day_alarm ......................................... 30 Register Weekday_alarm .................................30 Alarm flag ........................................................ 31 Timer functions ................................................ 31 Register Watchdg_tim_ctl ................................ 31 Register Watchdg_tim_val ............................... 32 Watchdog timer function .................................. 33 PCF2129 Product data sheet 7.10.4 Pre-defined timers: second and minute interrupt ............................................................34 7.10.5 Clearing flags ...................................................34 7.11 Timestamp function ......................................... 35 7.11.1 Timestamp flag ................................................ 35 7.11.2 Timestamp mode ............................................. 36 7.11.3 Timestamp registers ........................................ 36 7.11.3.1 Register Timestp_ctl ........................................ 36 7.11.3.2 Register Sec_timestp .......................................37 7.11.3.3 Register Min_timestp ....................................... 37 7.11.3.4 Register Hour_timestp ..................................... 37 7.11.3.5 Register Day_timestp ...................................... 38 7.11.3.6 Register Mon_timestp ......................................39 7.11.3.7 Register Year_timestp ......................................39 7.11.4 Dependency between Battery switch-over and timestamp ................................................. 39 7.12 Interrupt output, INT ........................................ 40 7.12.1 Minute and second interrupts .......................... 41 7.12.2 INT pulse shortening ....................................... 43 7.12.3 Watchdog timer interrupts ................................43 7.12.4 Alarm interrupts ............................................... 43 7.12.5 Timestamp interrupts ....................................... 44 7.12.6 Battery switch-over interrupts .......................... 44 7.12.7 Battery low detection interrupts ....................... 44 7.13 External clock test mode ................................. 44 7.14 STOP bit function ............................................ 45 8 Interfaces ........................................................... 46 8.1 SPI-bus interface ............................................. 47 8.1.1 Data transmission ............................................ 48 8.2 I2C-bus interface ............................................. 49 8.2.1 Bit transfer ....................................................... 49 8.2.2 START and STOP conditions .......................... 50 8.2.3 System configuration ....................................... 50 8.2.4 Acknowledge ....................................................50 8.2.5 I2C-bus protocol .............................................. 51 8.3 Bus communication and battery backup operation .......................................................... 52 9 Internal circuitry ................................................ 53 10 Safety notes .......................................................53 11 Limiting values .................................................. 53 12 Static characteristics ........................................ 54 12.1 Current consumption characteristics, typical ....56 12.2 Frequency characteristics ................................ 59 13 Dynamic characteristics ...................................61 13.1 SPI-bus timing characteristics ......................... 61 13.2 I2C-bus timing characteristics ..........................63 14 Application information .................................... 64 15 Test information ................................................ 65 15.1 Quality information ...........................................65 16 Package outline .................................................66 17 Packing information ..........................................68 17.1 Tape and reel information ................................68 18 Soldering ............................................................68 18.1 Footprint information ........................................68 19 Appendix ............................................................ 69 19.1 Real-Time Clock selection ............................... 70 All information provided in this document is subject to legal disclaimers. Rev. 8.0 — 18 July 2022 © 2022 NXP B.V. All rights reserved. 79 / 80 PCF2129 NXP Semiconductors Accurate RTC with integrated quartz crystal for industrial applications 20 21 22 23 Abbreviations .................................................... 73 References ......................................................... 73 Revision history ................................................ 74 Legal information .............................................. 75 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2022 NXP B.V. All rights reserved. For more information, please visit: http://www.nxp.com Date of release: 18 July 2022 Document identifier: PCF2129