PCF8523TS/1,112

PCF8523 Real-Time Clock (RTC) and calendar Rev. 7 — 28 April 2015 Product data sheet 1. General description The PCF8523 is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low power consumption. Data is transferred serially via the I2C-bus with a maximum data rate of 1000 kbit/s. Alarm and timer functions are available with the possibility to generate a wake-up signal on an interrupt pin. An offset register allows fine-tuning of the clock. The PCF8523 has a backup battery switch-over circuit, which detects power failures and automatically switches to the battery supply when a power failure occurs. For a selection of NXP Real-Time Clocks, see Table 56 on page 68 2. Features and benefits  Provides year, month, day, weekday, hours, minutes, and seconds based on a 32.768 kHz quartz crystal  Resolution: seconds to years  Clock operating voltage: 1.0 V to 5.5 V  Low backup current: typical 150 nA at VDD = 3.0 V and Tamb = 25 C  2 line bidirectional 1 MHz Fast-mode Plus (Fm+) I2C interface, read D1h, write D0h2  Battery backup input pin and switch-over circuit  Freely programmable timer and alarm with interrupt capability  Selectable integrated oscillator load capacitors for CL = 7 pF or CL = 12.5 pF  Oscillator stop detection function  Internal Power-On Reset (POR)  Open-drain interrupt or clock output pins  Programmable offset register for frequency adjustment 3. Applications  Time keeping application  Battery powered devices  Metering 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 22. 2. Devices with other I2C-bus slave addresses can be produced on request. PCF8523 NXP Semiconductors Real-Time Clock (RTC) and calendar 4. Ordering information Table 1. Ordering information Type number Package Name Description Version PCF8523T SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 PCF8523TK HVSON8 plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 4  4  0.85 mm SOT909-1 PCF8523TS TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm PCF8523U bare die 12 bumps (6-6) PCF8523U 4.1 Ordering options Table 2. Ordering options Product type number Sales item (12NC) Orderable part number IC revision Delivery form PCF8523T/1 935293581118 PCF8523T/1,118 1 tape and reel, 13 inch PCF8523TK/1 935293573118 PCF8523TK/1,118 1 tape and reel, 13 inch PCF8523TS/1 PCF8523U/12AA/1 [1] 935291196112 PCF8523TS/1,112 1 tube 935291196118 PCF8523TS/1,118 1 tape and reel, 13 inch 935293887005 PCF8523U/12AA/1,00 1 chips with bumps[1], sawn wafer on Film Frame Carrier (FFC) Bump hardness see Table 53. Table 3. PCF8523U wafer information Type number Wafer thickness Wafer diameter FFC for wafer size Marking of bad die PCF8523U/12AA/1 200 m 6 inch 8 inch wafer mapping 5. Marking Table 4. PCF8523 Product data sheet Marking codes Type number Marking code PCF8523T/1 8523T PCF8523TK/1 8523 PCF8523TS/1 8523TS PCF8523U/12AA/1 PC8523-1 All information provided in this document is subject to legal disclaimers. Rev. 7 — 28 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 2 of 78 PCF8523 NXP Semiconductors Real-Time Clock (RTC) and calendar 6. Block diagram 26&, &/.287 &26&, 26&,//$725 N+] ',9,'(5 &/2&.287 26&2 &26&2 9'' 9%$7 966 %$77(5 Vth(sw)bat, the internal power supply is VDD. If VDD < VBAT AND VDD < Vth(sw)bat, the internal power supply is VBAT. EDFNXSEDWWHU\RSHUDWLRQ 9'' 9%%6 9%$7 9%%6 LQWHUQDOSRZHUVXSSO\ 9%%6 9WKVZEDW  9 9'' 9 %6) ,17 FOHDUHGYLDLQWHUIDFH DDD Fig 9. PCF8523 Product data sheet Battery switch-over behavior in standard mode and with bit BSIE set logic 1 (enabled) All information provided in this document is subject to legal disclaimers. Rev. 7 — 28 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 17 of 78 PCF8523 NXP Semiconductors Real-Time Clock (RTC) and calendar 8.5.2.2 Direct switching mode If VDD > VBAT the internal power supply is VDD. If VDD < VBAT the internal power supply is VBAT. The direct switching mode is useful in systems where VDD is higher than VBAT at all times (for example, VDD = 5 V, VBAT = 3.5 V). If the VDD and VBAT values are similar (for example, VDD = 3.3 V, VBAT  3.0 V), the direct switching mode is not recommended. In direct switching mode, the power consumption is reduced compared to the standard mode because the monitoring of VDD and Vth(sw)bat is not performed. EDFNXSEDWWHU\RSHUDWLRQ 9'' 9%%6 9%%6 9%$7 LQWHUQDOSRZHUVXSSO\ 9%%6 9WKVZEDW  9 9'' 9 %6) ,17 FOHDUHGYLDLQWHUIDFH DDD Fig 10. Battery switch-over behavior in direct switching mode and with bit BSIE set logic 1 (enabled) 8.5.2.3 Battery switch-over disabled, only one power supply (VDD) When the battery switch-over function is disabled: • The power supply is applied on the VDD pin • The VBAT pin must be connected to VDD • The battery flag (BSF) is always logic 0 8.5.3 Battery low detection function The PCF8523 has a battery low detection circuit, which monitors the status of the battery VBAT. Generation of interrupts from the battery low detection is controlled via bit BLIE (register Control_3). If BLIE is enabled, the INT1 follows the status of bit BLF (register Control_3). When VBAT drops below the threshold value Vth(bat)low (typically 2.5 V), the BLF flag (register Control_3) is set to indicate that the battery is low and that it must be replaced. Monitoring of the battery voltage also occurs during battery operation. PCF8523 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 28 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 18 of 78 PCF8523 NXP Semiconductors Real-Time Clock (RTC) and calendar An unreliable battery does not ensure data integrity during periods of backup battery operation. When VBAT drops below the threshold value Vth(bat)low, the following sequence occurs (see Figure 11): 1. The battery low flag BLF is set logic 1 2. An interrupt is generated if the control bit BLIE (register Control_3) is enabled. The interrupt remains active until the battery is replaced (BLF set logic 0) or when bit BLIE is disabled (BLIE set logic 0) 3. The flag BLF (register Control_3) remains logic 1 until the battery is replaced. BLF cannot be cleared using the interface. It is cleared automatically by the battery low detection circuit when the battery is replaced 9'' 9%%6 LQWHUQDOSRZHUVXSSO\ 9%%6 9%$7 9WKEDWORZ  9 9%$7 %/) ,17 DDD Fig 11. Battery low detection behavior with bit BLIE set logic 1 (enabled) 8.6 Time and date registers Most of these registers are coded in the Binary Coded Decimal (BCD) format. BCD is used to simplify application use. An example is shown for the array SECONDS in Table 13. PCF8523 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 28 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 19 of 78 PCF8523 NXP Semiconductors Real-Time Clock (RTC) and calendar 8.6.1 Register Seconds Table 12. Seconds - seconds and clock integrity status register (address 03h) bit description Bit Symbol Value Place value Description 7 OS 0 - clock integrity is guaranteed 1[1] - clock integrity is not guaranteed; oscillator has stopped or been interrupted 0 to 5 ten’s place 0 to 9 unit place actual seconds coded in BCD format 6 to 4 SECONDS 3 to 0 [1] Start-up value. Table 13. SECONDS coded in BCD format Seconds value in decimal 8.6.1.1 Upper-digit (ten’s place) Digit (unit place) Bit Bit 6 5 4 3 2 1 0 00 0 0 0 0 0 0 0 01 0 0 0 0 0 0 1 02 0 0 0 0 0 1 0 : : : : : : : : 09 0 0 0 1 0 0 1 10 0 0 1 0 0 0 0 : : : : : : : : 58 1 0 1 1 0 0 0 59 1 0 1 1 0 0 1 Oscillator STOP flag The OS flag is set whenever the oscillator is stopped (see Figure 12). The flag remains set until cleared by using the interface. When the oscillator is not running, then the OS flag cannot be cleared. This method can be used to monitor the oscillator. The oscillator may be stopped, for example, by grounding one of the oscillator pins, OSCI or OSCO. The oscillator is also considered to be stopped during the time between power-on and stable crystal resonance. This time may be in a range of 200 ms to 2 s, depending on crystal type, temperature, and supply voltage. At power-on, the OS flag is always set. PCF8523 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 28 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 20 of 78 PCF8523 NXP Semiconductors Real-Time Clock (RTC) and calendar 26 DQGIODJFDQQRWEHFOHDUHG 26 DQGIODJFDQEHFOHDUHG 9'' RVFLOODWLRQ 26IODJ 26IODJFOHDUHG E\VRIWZDUH 26IODJVHWZKHQ RVFLOODWLRQVWRSV  W RVFLOODWLRQQRZVWDEOH DDD Fig 12. OS flag 8.6.2 Register Minutes Table 14. Minutes - minutes register (address 04h) bit description Bit Symbol Value Place value Description 7 - - - unused 6 to 4 MINUTES 0 to 5 ten’s place 0 to 9 unit place actual minutes coded in BCD format 3 to 0 8.6.3 Register Hours Table 15. Hours - hours register (address 05h) bit description Bit Symbol Value Place value Description 7 to 6 - - - unused 0 - indicates AM 1 - indicates PM 0 to 1 ten’s place 0 to 9 unit place actual hours in 12 hour mode coded in BCD format 0 to 2 ten’s place 0 to 9 unit place 12 hour mode[1] 5 AMPM 4 HOURS 3 to 0 24 hour mode[1] 5 to 4 HOURS 3 to 0 [1] actual hours in 24 hour mode coded in BCD format Hour mode is set by bit 12_24 in register Control_1 (see Table 7). 8.6.4 Register Days Table 16. Bit Symbol Value Place value Description 7 to 6 - - - unused 5 to 4 DAYS[1] 0 to 3 ten’s place actual day coded in BCD format 0 to 9 unit place 3 to 0 [1] PCF8523 Product data sheet Days - days register (address 06h) bit description If the year counter contains a value, which is exactly divisible by 4 (including the year 00), the PCF8523 compensates for leap years by adding a 29th day to February. All information provided in this document is subject to legal disclaimers. Rev. 7 — 28 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 21 of 78 PCF8523 NXP Semiconductors Real-Time Clock (RTC) and calendar 8.6.5 Register Weekdays Table 17. Weekdays - weekdays register (address 07h) bit description Bit Symbol Value Description 7 to 3 - - unused 2 to 0 WEEKDAYS 0 to 6 actual weekday, values see Table 18 Table 18. Weekday assignments Day[1] Bit 2 1 0 Sunday 0 0 0 Monday 0 0 1 Tuesday 0 1 0 Wednesday 0 1 1 Thursday 1 0 0 Friday 1 0 1 Saturday 1 1 0 [1] Definition may be reassigned by the user. 8.6.6 Register Months Table 19. Months - months register (address 08h) bit description Bit Symbol Value Place value Description 7 to 5 - - - unused 4 MONTHS 0 to 1 ten’s place 0 to 9 unit place actual month coded in BCD format; assignments see Table 20 3 to 0 Table 20. Month PCF8523 Product data sheet Month assignments in BCD format Upper-digit (ten’s place) Digit (unit place) Bit Bit 4 3 2 1 0 January 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April 0 0 1 0 0 May 0 0 1 0 1 June 0 0 1 1 0 July 0 0 1 1 1 August 0 1 0 0 0 September 0 1 0 0 1 October 1 0 0 0 0 November 1 0 0 0 1 December 1 0 0 1 0 All information provided in this document is subject to legal disclaimers. Rev. 7 — 28 April 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 22 of 78 PCF8523 NXP Semiconductors Real-Time Clock (RTC) and calendar 8.6.7 Register Years Table 21. Years - years register (09h) bit description Bit Symbol Value Place value Description 7 to 4 YEARS 0 to 9 ten’s place 0 to 9 unit place 3 to 0 actual year coded in BCD format 8.6.8 Data flow of the time function Figure 13 shows the data flow and data dependencies starting from the 1 Hz clock tick. +]WLFN 6(&21'6 0,187(6 KRXUPRGH +2856 /($3