PCF8532
Universal LCD driver for low multiplex rates
Rev. 4 — 11 July 2013
Product data sheet
1. General description
The PCF8532 is a peripheral device which interfaces to almost any Liquid Crystal Display
(LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed
LCD containing up to four backplanes and up to 160 segments. It can easily be cascaded
for larger LCD applications. The PCF8532 is compatible with most microcontrollers and
communicates via the two-line bidirectional I2C-bus. Communication overheads are
minimized by a display RAM with auto-incremental addressing, by hardware
subaddressing, and by display memory switching (static and duplex drive modes).
Not to be used for new designs. Replacement part is PCF85132U/2DA/1 for industrial and
PCA85132U/2DA/Q1 for automotive applications.
2. Features and benefits
Single-chip LCD controller and driver for up to 640 elements
Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
160 segment drives:
Up to 80 7-segment numeric characters
Up to 40 14-segment alphanumeric characters
Any graphics of up to 640 elements
May be cascaded for large LCD applications (up to 5120 elements possible)
160 4-bit RAM for display data storage
Software programmable frame frequency in steps of 5 Hz in the range of 60 Hz to
90 Hz
Wide LCD supply range: from 1.8 V for low threshold LCDs and up to 8.0 V for
guest-host LCDs and high threshold (automobile) twisted nematic LCDs
Internal LCD bias generation with voltage-follower buffers
Selectable display bias configuration: static, 1⁄2, or 1⁄3
Wide power supply range: from 1.8 V to 5.5 V
LCD and logic supplies may be separated
Low power consumption, typical: IDD = 4 A, IDD(LCD) = 30 A
400 kHz I2C-bus interface
Auto-incremental display data loading across device subaddress boundaries
Versatile blinking modes
Compatible with Chip-On-Glass (COG) technology
Two sets of backplane outputs for optimal COG configurations of the application
Display memory bank switching in static and duplex drive modes
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 17.
PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
No external components required
Manufactured in silicon gate CMOS process
3. Ordering information
Table 1.
Ordering information
Type number
Package
PCF8532U
Name
Description
Version
bare die
197 bumps; 6.5 1.16 0.38 mm
PCF8532U
3.1 Ordering options
Table 2.
Ordering options
Product type number
IC
revision
Sales item (12NC)
Delivery form
PCF8532U/2DA/1
1
935288613026
chip with bumps in tray
4. Marking
Table 3.
PCF8532
Product data sheet
Marking codes
Product type number
Marking code
PCF8532U/2DA/1
PC8532-1
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
5. Block diagram
S0 to S159
BP0 BP1 BP2 BP3
160
VLCD
BACKPLANE
OUTPUTS
LCD
VOLTAGE
SELECTOR
DISPLAY SEGMENT OUTPUTS
DISPLAY REGISTER
OUTPUT BANK SELECT
AND BLINK CONTROL
DISPLAY
CONTROL
LCD BIAS
GENERATOR
VSS
PCF8532
CLK
SYNC
CLOCK SELECT
AND TIMING
BLINKER
TIMEBASE
OSC
OSCILLATOR
POWER-ON
RESET
SCL
INPUT
FILTERS
SDA
COMMAND
DECODE
WRITE DATA
CONTROL
I2C-BUS
CONTROLLER
SA0
Fig 1.
DISPLAY
RAM
SDAACK
DATA POINTER AND
AUTO INCREMENT
SUBADDRESS
COUNTER
T1
T2
T3
VDD
A0
A1
001aah851
Block diagram of PCF8532
PCF8532
Product data sheet
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NXP Semiconductors
PCF8532
S29
D3
61
112
S80
D4
S130
166
+y
Pinning diagram of PCF8532
30
BP2
BP0
S0
VLCD
VSS
A0
A1
SA0
T3
T2
OSC
T1
SYNC
VDD
CLK
SCL
SDA
60
001aah892
PCF8532
4 of 62
© NXP B.V. 2013. All rights reserved.
Viewed from active side. For mechanical details, see Figure 34 on page 48.
Fig 2.
+x
0
1
197
S159
BP3
BP1
SDAACK
167
0
S28
D2
PCF8532
Universal LCD driver for low multiplex rates
Rev. 4 — 11 July 2013
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BP3
BP1
BP2
BP0
S79
6.1 Pinning
D1
S131
Product data sheet
6. Pinning information
PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
6.2 Pin description
Table 4.
PCF8532
Product data sheet
Pin description
Symbol
Pin
Description
SDAACK[1]
1 to 3
I2C-bus acknowledge output
SDA[1]
4 to 6
I2C-bus serial data input
SCL
7 to 9
I2C-bus serial clock input
CLK
10
clock input and output
VDD
11 to 13
supply voltage
SYNC
14
cascade synchronization input and output
OSC
15
selection of internal or external clock
T1, T2, and T3
16, 17, and 18 to 20
dedicated testing pins; to be tied to VSS in
application mode
A0 and A1
21, 22
subaddress inputs
SA0
23
I2C-bus slave address input
VSS[2]
24 to 26
logic ground
VLCD
27 to 29
LCD supply voltage
BP2 and BP0
30, 31
LCD backplane outputs
S0 to S79
32 to 111
LCD segment outputs
BP0, BP2, BP1, and BP3
112 to 115
LCD backplane outputs
S80 to S159
116 to 195
LCD segment outputs
BP3 and BP1
196, 197
LCD backplane outputs
[1]
For most applications SDA and SDAACK are shorted together (see Section 14.3 on page 43).
[2]
The substrate (rear side of the die) is connected to VSS and should be electrically isolated.
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
7. Functional description
The PCF8532 is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot matrix displays. It can directly
drive any static or multiplexed LCD containing up to four backplanes and up to
160 segments.
7.1 Commands of PCF8532
The commands available to the PCF8532 are defined in Table 5.
Table 5.
Definition of PCF8532 commands
Command
Operation code
Reference
Bit
7
6
5
4
3
2
1
B
M[1:0]
0
mode-set
1
1
0
0
E
load-data-pointer-MSB
0
0
0
0
P[7:4]
Table 7
load-data-pointer-LSB
0
1
0
0
P[3:0]
Table 8
device-select
1
1
1
0
0
0
Table 6
A[1:0]
Table 9
bank-select
1
1
1
1
1
0
I
blink-select
1
1
1
1
0
AB
BF[1:0]
O
frequency-ctrl
1
1
1
0
1
F[2:0]
Table 10
Table 11
Table 12
7.1.1 Command: mode-set
The mode-set command allows configuring the multiplex mode, the bias levels and
enabling or disabling the display.
Table 6.
Mode-set - command bit description
Bit
Symbol
Value
Description
7 to 4
-
1100
fixed value
3
E
2
display status[1]
0[2]
disabled (blank)[3]
1
enabled
LCD bias configuration[4]
B
1 to 0
0[2]
1⁄ bias
3
1
1⁄
2
M[1:0]
LCD drive mode selection
01
PCF8532
Product data sheet
bias
static; BP0
10
1:2 multiplex; BP0, BP1
11
1:3 multiplex; BP0, BP1, BP2
00[2]
1:4 multiplex; BP0, BP1, BP2, BP3
[1]
The possibility to disable the display allows implementation of blinking under external control. The enable
bit determines also whether the internal clock signal is available at the CLK pin (see Section 7.1.6.2 on
page 9).
[2]
Default value.
[3]
The display is disabled by setting all backplane and segment outputs to VLCD.
[4]
Not applicable for static drive mode.
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.1.2 Command: load-data-pointer
The load-data-pointer command defines the display RAM address where the following
display data will be sent to.
Table 7.
Load-data-pointer-MSB - command bit description
See Section 7.5.4 on page 25.
Bit
Symbol
Value
Description
7 to 4
-
0000
fixed value
P[7:4]
0000[1]
3 to 0
to
1001
[1]
defines the first 4 (most significant) bits of the
data-pointer
the data-pointer indicates one of the 160 display RAM
addresses
Default value.
Table 8.
Load-data-pointer-LSB - command bit description
See Section 7.5.1 on page 24.
Bit
Symbol
Value
Description
7 to 4
-
0100
fixed value
P[3:0]
0000[1]
3 to 0
to
1111
[1]
defines the last 4 (least significant) bits of the
data-pointer
the data-pointer indicates one of the 160 display RAM
addresses
Default value.
7.1.3 Command: device-select
The device-select command allows defining the subaddress counter value.
Table 9.
Device-select - command bit description
See Section 7.5.2 on page 24.
Bit
Symbol
Value
Description
7 to 2
-
111000
fixed value
1 to 0
A[1:0]
00[1] to 11
defines one of four hardware subaddresses
(see Table 23 on page 43)
[1]
PCF8532
Product data sheet
Default value.
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.1.4 Command: bank-select
The bank-select command controls where data is written to RAM and where it is displayed
from.
Table 10. Bank-select - command bit description
See Section 7.5.4.1 on page 25 and Section 7.5.4.2 on page 26.
Bit
Symbol
Value
Description
Static
7 to 2
-
1
I
0
111110
1:2 multiplex[1]
fixed value
input bank selection; storage of arriving display data
0[2]
RAM row 0
RAM rows 0 and 1
1
RAM row 2
RAM rows 2 and 3
O
output bank selection; retrieval of LCD display data
0[2]
RAM row 0
RAM rows 0 and 1
1
RAM row 2
RAM rows 2 and 3
[1]
The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
[2]
Default value.
7.1.5 Command: blink-select
The blink-select command allows configuring the blink mode and the blink frequency.
Table 11. Blink-select - command bit description
See Section 7.1.6.6 on page 10.
Bit
Symbol
Value
Description
7 to 3
-
11110
fixed value
2
AB
1 to 0
blink mode selection
0[1]
normal blinking[2]
1
alternate RAM bank blinking[3]
BF[1:0]
blink frequency selection
00[1]
off
01
1
10
2
11
3
[1]
Default value.
[2]
Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[3]
Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
7.1.6 Clock frequency and timing
The timing of the PCF8532 organizes the internal data flow of the device. The timing
includes the transfer of display data from the display RAM to the display segment outputs
and therefore the frame frequency.
PCF8532
Product data sheet
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.1.6.1
Clock source selection
The PCF8532 can be configured to use either the built-in oscillator or an external clock as
clock source:
Internal clock — To enable the internal oscillator, pin OSC has to be connected to VSS.
Pin CLK then becomes an output. For further information on the internal clock, see
Section 7.1.6.2.
External clock — To enable the use of an external clock, pin OSC has to be connected to
VDD. Pin CLK then becomes an input for the external clock frequency fclk(ext). For further
information on the external clock, see Section 7.1.6.3.
Figure 3 illustrates the frequency generation of the PCF8532.
&/.
IFON H[W
9''
IFON
IRVF
)5(48(1& 3Vth(off).
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
1
Bias is calculated by ------------- , where the values for a are
1+a
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 2:
V on RMS =
V LCD
a 2 + 2a + n
-----------------------------2
n 1 + a
(2)
where the values for n are
n = 1 for static drive mode
n = 2 for 1:2 multiplex drive mode
PCF8532
Product data sheet
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
n = 3 for 1:3 multiplex drive mode
n = 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 3:
V off RMS =
V LCD
a 2 – 2a + n
-----------------------------2
n 1 + a
(3)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 4:
V on RMS
D = ----------------------- =
V off RMS
2
a + 2a + n
--------------------------2
a – 2a + n
(4)
Using Equation 4, the discrimination for an LCD drive mode of 1:3 multiplex with
1⁄
2
bias is
1⁄
2
21
bias is ---------- = 1.528 .
3
3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
• 1:3 multiplex (1⁄2 bias): V LCD =
6 V off RMS = 2.449V off RMS
4 3
- = 2.309V off RMS
• 1:4 multiplex (1⁄2 bias): V LCD = --------------------3
These compare with V LCD = 3V off RMS when 1⁄3 bias is used.
VLCD is sometimes referred as the LCD operating voltage.
7.3.3.1
Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltages, at which a pixel is switched on or off, determine the transmissibility of the
pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 6. For a good contrast performance, the following rules should be followed:
V on RMS V th on
(5)
V off RMS V th off
(6)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a (see Equation 2), n (see Equation 4), and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
PCF8532
Product data sheet
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
100 %
Relative Transmission
90 %
10 %
Vth(off)
OFF
SEGMENT
Vth(on)
GREY
SEGMENT
VRMS [V]
ON
SEGMENT
013aaa494
Fig 6.
PCF8532
Product data sheet
Electro-optical characteristic: relative transmission curve of the liquid
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.3.4 LCD drive mode waveforms
7.3.4.1
Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
Backplane and segment drive waveforms for this mode are shown in Figure 7.
Tfr
LCD segments
VLCD
BP0
VSS
state 1
(on)
VLCD
state 2
(off)
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
state 1
0V
−VLCD
VLCD
state 2
0V
−VLCD
(b) Resultant waveforms
at LCD segment.
013aaa207
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = VLCD.
Vstate2(t) = V(Sn+1)(t) VBP0(t).
Voff(RMS) = 0 V.
Fig 7.
PCF8532
Product data sheet
Static drive mode waveforms
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.3.4.2
1:2 multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCF8532 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 8 and
Figure 9.
Tfr
VLCD
BP0
LCD segments
VLCD/2
VSS
state 1
VLCD
BP1
state 2
VLCD/2
VSS
VLCD
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
VLCD/2
state 1
0V
−VLCD/2
−VLCD
VLCD
VLCD/2
state 2
0V
−VLCD/2
−VLCD
(b) Resultant waveforms
at LCD segment.
013aaa208
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.791VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.354VLCD.
Fig 8.
PCF8532
Product data sheet
Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
Tfr
BP0
BP1
Sn
Sn+1
VLCD
2VLCD/3
LCD segments
VLCD/3
VSS
state 1
VLCD
2VLCD/3
state 2
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
(a) Waveforms at driver.
VLCD
2VLCD/3
VLCD/3
state 1
0V
−VLCD/3
−2VLCD/3
−VLCD
VLCD
2VLCD/3
VLCD/3
state 2
0V
−VLCD/3
−2VLCD/3
−VLCD
(b) Resultant waveforms
at LCD segment.
013aaa209
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.745VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 9.
PCF8532
Product data sheet
Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.3.4.3
1:3 multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as
shown in Figure 10.
Tfr
BP0
BP1
BP2
Sn
Sn+1
Sn+2
VLCD
2VLCD/3
LCD segments
VLCD/3
VSS
state 1
VLCD
2VLCD/3
state 2
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
(a) Waveforms at driver.
VLCD
2VLCD/3
VLCD/3
state 1
0V
−VLCD/3
−2VLCD/3
−VLCD
VLCD
2VLCD/3
VLCD/3
state 2
0V
−VLCD/3
−2VLCD/3
−VLCD
(b) Resultant waveforms
at LCD segment.
013aaa210
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.638VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 10. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
PCF8532
Product data sheet
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.3.4.4
1:4 multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as
shown in Figure 11.
Tfr
BP0
VLCD
2VLCD/3
VLCD/3
VSS
BP1
VLCD
2VLCD/3
VLCD/3
VSS
BP2
VLCD
2VLCD/3
VLCD/3
VSS
BP3
VLCD
2VLCD/3
VLCD/3
VSS
Sn
VLCD
2VLCD/3
VLCD/3
VSS
Sn+1
VLCD
2VLCD/3
VLCD/3
VSS
Sn+2
VLCD
2VLCD/3
VLCD/3
VSS
Sn+3
VLCD
2VLCD/3
VLCD/3
VSS
state 1
VLCD
2VLCD/3
VLCD/3
0V
-VLCD/3
-2VLCD/3
-VLCD
state 2
VLCD
2VLCD/3
VLCD/3
0V
-VLCD/3
-2VLCD/3
-VLCD
LCD segments
state 1
state 2
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
013aaa211
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.577VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 11. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias
PCF8532
Product data sheet
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PCF8532
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Universal LCD driver for low multiplex rates
7.4 Backplane and segment outputs
7.4.1 Backplane outputs
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated in accordance with the selected LCD drive mode.
• In the 1:4 multiplex drive mode BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required, the unused outputs can be left
open-circuit.
• In 1:3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
• In 1:2 multiplex drive mode BP0 and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive capabilities.
• In static drive mode, the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
The pins for the four backplanes BP0 to BP3 are available on both pin bars of the chip. In
applications, it is possible to use either the pins for the backplanes
• on the top pin bar
• on the bottom pin bar
• or both of them to increase the driving strength of the device.
When using all backplanes available they may be connected to the respective sibling
(BP0 on the top pin bar with BP0 on the bottom pin bar, and so on).
7.4.2 Segment outputs
The LCD drive section includes 160 segment outputs (S0 to S159) which must be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data resident in the display register.
When less than 160 segment outputs are required, the unused segment outputs must be
left open-circuit.
7.5 Display RAM
The display RAM is a static 160 4 bit RAM which stores LCD data. There is a one-to-one
correspondence between
• the bits in the RAM bitmap and the LCD elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
PCF8532
Product data sheet
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PCF8532
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Universal LCD driver for low multiplex rates
The display RAM bitmap, Figure 12, shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 159 which correspond with the
segment outputs S0 to S159. In multiplexed LCD applications the segment data of the
first, second, third, and fourth row of the display RAM are time-multiplexed with BP0,
BP1, BP2, and BP3 respectively.
columns
display RAM addresses/segment outputs (S)
0
rows
1
2
3
4
155 156 157 158 159
0
display RAM rows/
backplane outputs 1
(BP)
2
3
013aaa220
The display RAM bitmap shows the direct relationship between the display RAM addresses and
the segment outputs; and between the bits in a RAM word and the backplane outputs.
Fig 12. Display RAM bitmap
When display data is transmitted to the PCF8532, the received display bytes are stored in
the display RAM in accordance with the selected LCD drive mode. The data is stored as it
arrives and does not wait for the acknowledge cycle as with the commands. Depending on
the current multiplex drive mode, data is stored singularly, in pairs, triples, or quadruples.
To illustrate the filling order, an example of a 7-segment numeric display showing all drive
modes is given in Figure 13. The RAM filling organization depicted applies equally to
other LCD types.
The following applies to Figure 13:
• In static drive mode the eight transmitted data bits are placed in row 0 as 1 byte.
• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 as 2 successive 4-bit RAM words.
• In 1:3 multiplex drive mode the 8 bits are placed in triples into row 0, 1, and 2 as 3
successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is not
recommended to use this bit in a display because of the difficult addressing. This last
bit may, if necessary, be controlled by an additional transfer to this address but care
should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see Section 7.5.3 on page 25).
• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as 2 successive 4-bit RAM words.
PCF8532
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Sn+2
Sn+3
static
display RAM filling order
b
f
Sn+1
BP0
rows
display RAM 0
rows/backplane
1
outputs (BP)
2
3
g
e
Sn+6
Sn
Sn+7
c
DP
d
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
c
x
x
x
b
x
x
x
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
x
Sn
a
b
f
g
multiplex
Sn+2
BP1
e
Sn+3
c
Sn+1
1:3
Sn+2
DP
d
a
b
Sn
multiplex
BP1
c
b
f
BP0
g
multiplex
e
BP1
c
d
g e d DP
n
n+1
n+2
n+3
a
b
x
x
f
g
x
x
e
c
x
x
d
DP
x
x
MSB
a b
LSB
f
g e c d DP
n
rows
display RAM 0 b
rows/backplane
1 DP
outputs (BP)
2 c
3 x
n+1
n+2
a
d
g
x
f
e
x
x
MSB
LSB
b DP c a d g
f
e
DP
BP2
n
rows
display RAM 0 a
rows/backplane
1 c
BP3 outputs (BP) 2 b
3 DP
n+1
f
e
g
d
MSB
a c b DP f
LSB
e g d
001aaj646
x = data bit unchanged
Fig 13. Relationships between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus
PCF8532
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Sn+1
f
columns
display RAM address/segment outputs (s)
byte1
byte2
byte3
byte4
byte5
a
Sn
1:4
BP2
DP
d
c b a
columns
display RAM address/segment outputs (s)
byte1
byte2
byte3
g
e
rows
display RAM 0
rows/backplane
1
outputs (BP)
2
3
BP0
f
LSB
Universal LCD driver for low multiplex rates
Rev. 4 — 11 July 2013
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Sn+1
MSB
columns
display RAM address/segment outputs (s)
byte1
byte2
BP0
1:2
transmitted display byte
columns
display RAM address/segment outputs (s)
byte1
a
Sn+4
Sn+5
LCD backplanes
NXP Semiconductors
PCF8532
Product data sheet
LCD segments
drive mode
PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.5.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 7 on page 7 and Table 8 on
page 7). Following this command, an arriving data byte is stored at the display RAM
address indicated by the data pointer. The filling order is shown in Figure 13.
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
•
•
•
•
In static drive mode by eight
In 1:2 multiplex drive mode by four
In 1:3 multiplex drive mode by three
In 1:4 multiplex drive mode by two
If an I2C-bus data access is terminated early, then the state of the data pointer is
unknown. The data pointer should be re-written before further RAM accesses.
7.5.2 Subaddress counter
The storage of display data is conditioned by the content of the subaddress counter.
Storage is allowed only when the content of the subaddress counter matches with the
hardware subaddress applied to A0 and A1. The subaddress counter value is defined by
the device-select command (see Table 9 on page 7). If the content of the subaddress
counter and the hardware subaddress do not match then data storage is inhibited but the
data pointer is incremented as if data storage had taken place. The subaddress counter is
also incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF8532 occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character.
The hardware subaddress must not be changed while the device is being accessed on the
I2C-bus interface.
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PCF8532
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Universal LCD driver for low multiplex rates
7.5.3 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 16 (see Figure 13 as
well).
Table 16. Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
0
a7
a4
a1
b7
b4
b1
c7
c4
c1
d7
:
1
a6
a3
a0
b6
b3
b0
c6
c3
c0
d6
:
2
a5
a2
-
b5
b2
-
c5
c2
-
d5
:
3
-
-
-
-
-
-
-
-
-
-
:
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 17.
Table 17. Entire RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
0
a7
a4
a1/b7 b4
b1/c7 c4
c1/d7 d4
d1/e7 e4
:
1
a6
a3
a0/b6 b3
b0/c6 c3
c0/d6 d3
d0/e6 e3
:
2
a5
a2
b5
b2
c5
c2
d5
d2
e5
e2
:
3
-
-
-
-
-
-
-
-
-
-
:
3
4
5
6
7
8
9
:
In the case described in Table 17 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8, and so on, have to be connected to elements on the display. This can be
achieved by a combination of writing and rewriting the RAM like follows:
• In the first write to the RAM, bits a7 to a0 are written
• The data-pointer (see Section 7.1.2 on page 7) has to be set to the address of bit a1
• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6
• The data-pointer has to be set to the address of bit b1
• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used, but it has to be considered in the module
layout process as well as in the driver software design.
7.5.4 Bank selection
7.5.4.1
Output bank selector
The output bank selector (see Table 10 on page 8) selects one of the four rows per display
RAM address for transfer to the display register. The actual row selected depends on the
particular LCD drive mode in operation and on the instant in the multiplex sequence.
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PCF8532
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Universal LCD driver for low multiplex rates
• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, followed by the
contents of row 1, row 2, and then row 3
• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
• In 1:2 multiplex mode, rows 0 and 1 are selected
• In static mode, row 0 is selected
7.5.4.2
Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded by using the bank-select
command (see Table 10). The input bank selector functions independently to the output
bank selector.
7.5.4.3
RAM bank switching
The PCF8532 includes a RAM bank switching feature in the static and 1:2 multiplex drive
modes. A bank can be thought of as one RAM row or a collection of RAM rows (see
Figure 14). The RAM bank switching gives the provision for preparing display information
in an alternative bank and to be able to switch to it once it is complete.
GLVSOD\5$0DGGUHVVHV FROXPQV VHJPHQWRXWSXWV 6
VWDWLFGULYHPRGH
GLVSOD\5$0ELWV URZV EDFNSODQHRXWSXWV %3
EDQN
EDQN
PXOWLSOH[GULYHPRGH
EDQN
EDQN
DDD
Fig 14. RAM banks in static and multiplex driving mode 1:2
There are two banks; bank 0 and bank 1. Figure 14 shows the location of these banks
relative to the RAM map. Input and output banks can be set independently from one
another with the Bank-select command (see Table 10 on page 8). Figure 15 shows the
concept.
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
LQSXWEDQNVHOHFWLRQ
FRQWUROVWKHLQSXW
GDWDSDWK
RXWSXWEDQNVHOHFWLRQ
FRQWUROVWKHRXWSXW
GDWDSDWK
%$1.
0,&52&21752//(5
',63/$<
5$0
%$1.
DDD
Fig 15. Bank selection
In the static drive mode, the bank-select command may request the contents of row 2 to
be selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the
contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the
provision for preparing display information in an alternative bank and to be able to switch
to it once it is assembled.
In Figure 16 an example is shown for 1:2 multiplex drive mode where the displayed data is
read from the first two rows of the memory (bank 0), while the transmitted data is stored in
the second two rows of the memory (bank 1).
FROXPQV
GLVSOD\5$0FROXPQVVHJPHQWRXWSXWV 6
URZV
RXWSXW5$0EDQN
WRWKH/&'
GLVSOD\5$0URZV
EDFNSODQHRXWSXWV
%3
WRWKH5$0
LQSXW5$0EDQN
DDD
Fig 16. Example of the Bank-select command with multiplex drive mode 1:2
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
8. Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
By connecting pin SDAACK to pin SDA on the PCF8532, the SDA line becomes fully
I2C-bus compatible. In COG applications where the track resistance from the SDAACK
pin to the system SDA line can be significant, possibly a voltage divider is generated by
the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As a
consequence, it may be possible that the acknowledge generated by the PCF8532 cannot
be interpreted as logic 0 by the master. In COG applications where the acknowledge cycle
is required, it is therefore necessary to minimize the track resistance from the SDAACK
pin to the system SDA line to guarantee a valid LOW level (see Section 14.2 on page 41).
By separating the acknowledge output from the serial data line (having the SDAACK open
circuit) design efforts to generate a valid acknowledge level can be avoided. However, in
that case the I2C-bus master has to be set up in such a way that it ignores the
acknowledge cycle.2
The following definition assumes that SDA and SDAACK are connected and refers to the
pair as SDA.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as a control signal (see Figure 17).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 17. Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change
of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP
condition (P). The START and STOP conditions are shown in Figure 18.
2.
For further information, please consider the NXP application note: Ref. 1 “AN10170”.
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
mbc622
Fig 18. Definition of START and STOP conditions
8.2 System configuration
A device generating a message is a transmitter; a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 19.
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
mga807
Fig 19. System configuration
8.3 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 20.
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
Fig 20. Acknowledgement on the I2C-bus
8.4 I2C-bus controller
The PCF8532 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF8532 is the
acknowledge signal. Device selection depends on the I2C-bus slave address, on the
transferred command data, and on the hardware subaddress.
In single device applications, the hardware subaddress inputs A0 and A1 are normally tied
to VSS which defines the hardware subaddress 0. In multiple device applications
A0 and A1 are tied to VSS or VDD in accordance with a binary coding scheme. No two
devices with a common I2C-bus slave address must have the same hardware
subaddress.
8.5 Input filters
To enhance noise immunity in electrical adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.6 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8532.
The entire I2C-bus slave address byte is shown in Table 18.
Table 18.
I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
MSB
0
0
LSB
1
1
1
0
0
SA0
R/W
The PCF8532 is a write-only device and does not respond to a read access, therefore
bit 0 should always be logic 0. Bit 1 of the slave address byte, that a PCF8532 responds
to, is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).
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PCF8532
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Universal LCD driver for low multiplex rates
Having two reserved slave addresses allows the following on the same I2C-bus:
• Up to 8 PCF8532 on the same I2C-bus for very large LCD applications
• The use of two types of LCD multiplex drive modes on the same I2C-bus
The I2C-bus protocol is shown in Figure 21. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of two possible PCF8532
slave addresses available. All PCF8532 with the corresponding SA0 level acknowledge in
parallel to the slave address, but all PCF8532 with the alternative SA0 level ignore the
whole I2C-bus transfer.
R/W = 0
slave address
control byte
RAM/command byte
S
C R
S 0 1 1 1 0 0 A 0 A
O S
0
M
A S
B
L
S P
B
EXAMPLES
a) transmit two bytes of RAM data
S
S 0 1 1 1 0 0 A 0 A 0 1
0
RAM DATA
A
RAM DATA
A
A
COMMAND
A 0 0
A
COMMAND
A P
A
COMMAND
A 0 1
A
RAM DATA
A
A P
b) transmit two command bytes
S
S 0 1 1 1 0 0 A 0 A 1 0
0
c) transmit one command byte and two RAM date bytes
S
S 0 1 1 1 0 0 A 0 A 1 0
0
RAM DATA
A P
mgl752
Fig 21. I2C-bus protocol
After acknowledgement, a control byte follows which defines if the next byte is RAM or
command information.
Table 19.
Control byte description
Bit
Symbol
7
CO
6
5 to 0
PCF8532
Product data sheet
Value
continue bit
0
last control byte
1
control bytes continue
RS
-
Description
register selection
0
command register
1
data register
-
not relevant
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
MSB
7
6
5
CO RS
4
3
2
1
LSB
0
not relevant
mgl753
Fig 22. Control byte format
In this way, it is possible to configure the device and then fill the display RAM with little
overhead.
The command bytes and control bytes are also acknowledged by all addressed PCF8532
connected to the bus.
The display bytes are stored in the display RAM at the address specified by the data
pointer and the subaddress counter; see Section 7.5.1 and Section 7.5.2.
The acknowledgement after each byte is made only by the (A0 and A1) addressed
PCF8532. After the last (display) byte, the I2C-bus master issues a STOP condition (P).
Alternatively a repeated START may be asserted to restart an I2C-bus access.
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PCF8532
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Universal LCD driver for low multiplex rates
9. Internal circuitry
VDD
VDD
VSS
VSS
SA0
VDD
CLK
SCL
VSS
VDD
VSS
OSC
VSS
VDD
SDA
SYNC
VSS
VSS
VDD
A0, A1
SDAACK
VSS
VLCD
VSS
BP0 to BP3
VSS
VLCD
VLCD
S0 to S159
VSS
VSS
VDD
T3
T1, T2
VSS
VSS
001aah856
Fig 23. Device protection diagram
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Product data sheet
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PCF8532
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Universal LCD driver for low multiplex rates
10. Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
CAUTION
Semiconductors are light sensitive. Exposure to light sources can cause the IC to
malfunction. The IC must be protected against light. The protection must be applied to all
sides of the IC.
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
11. Limiting values
Table 20. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter
Max
Unit
+6.5
V
supply voltage
0.5
IDD
supply current
50
+50
mA
VLCD
LCD supply voltage
0.5
+9.0
V
IDD(LCD) LCD supply current
50
+50
mA
0.5
+6.5
V
10
+10
mA
on pins S0 to S159 and
BP0 to BP3
0.5
+7.5
V
on pins SDAACK,
CLK, SYNC
0.5
+6.5
V
10
+10
mA
Vi
input voltage
II
input current
VO
output voltage
on pins CLK, SYNC,
SA0, OSC, SDA, SCL,
A0, A1, T1, T2, and T3
IO
output current
ISS
ground supply current
50
+50
mA
Ptot
total power dissipation
-
400
mW
P/out
power dissipation per output
electrostatic discharge
voltage
-
100
mW
HBM
[2]
-
4500
V
MM
[3]
-
250
V
Ilu
latch-up current
[4]
-
200
mA
Tstg
storage temperature
[5]
65
+150
C
Tamb
ambient temperature
40
+85
C
[1]
Product data sheet
Min
VDD
VESD
PCF8532
Conditions
operating device
Stresses above these values listed may cause permanent damage to the device.
[2]
Pass level; Human Body Model (HBM) according to Ref. 6 “JESD22-A114”.
[3]
Pass level; Machine Model (MM), according to Ref. 7 “JESD22-A115”.
[4]
Pass level; latch-up testing, according to Ref. 8 “JESD78” at maximum ambient temperature (Tamb(max)).
[5]
According to the store and transport requirements (see Ref. 11 “UM10569”) the devices have to be stored
at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
12. Static characteristics
Table 21. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 8.0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
1.8
-
5.5
V
VLCD
LCD supply voltage
1.8
-
8.0
V
[1][2]
-
4
20
A
[1]
-
18
60
A
[1][2]
-
30
70
A
[1]
-
30
70
A
-
+5.5
V
IDD
supply current
fclk(ext) = 1.800 kHz
with internal oscillator running
IDD(LCD)
LCD supply current
fclk(ext) = 1.800 kHz
with internal oscillator running
Logic[3]
VI
input voltage
on pins SDA and SCL
0.5
all other input pins
0.5
-
VDD + 0.5
V
VIH
HIGH-level input voltage
on pins CLK, SYNC, OSC, A0,
A1, SA0, SCL, and SDA
0.7VDD
-
-
V
VIL
LOW-level input voltage
on pins CLK, SYNC, OSC, A0,
A1, SA0, SCL, and SDA
-
-
0.3VDD
V
VO
output voltage
on pins SCL and SYNC
0.5
-
VDD + 0.5
V
on pin SDAACK
0.5
-
+5.5
V
1.5
-
-
mA
1.5
-
-
mA
VDD 2 V;
VOL = 0.2VDD
3
-
-
mA
2 V < VDD < 3 V;
VOL = 0.4 V
3
-
-
mA
VDD 3 V;
VOL = 0.4 V
6
-
-
mA
1.0
1.3
1.6
V
1
-
+1
A
IOH
HIGH-level output current output source current;
VOH = 4.6 V;
VDD = 5 V;
on pin CLK
IOL
LOW-level output current output sink current;
on pins CLK and SYNC
VOL = 0.4 V;
VDD = 5 V
on pin SDAACK
VPOR
power-on reset voltage
IL
leakage current
PCF8532
Product data sheet
VI = VDD or VSS;
on pin OSC, CLK, A0, A1, SA0,
SDA, SDAACK, and SCL
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 21. Static characteristics …continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 8.0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
30
-
+30
mV
on pins BP0 to BP3
-
1.5
5
k
on pins S0 to S159
-
2.0
5
k
LCD outputs
VO
output voltage variation
on pins BP0 to BP3 and S0 to
S159
RO
output resistance
VLCD = 5 V
[4][5]
[1]
LCD outputs are open-circuit; inputs at VSS or VDD; I2C-bus inactive; VLCD = 8.0 V, VDD = 5.0 V and RAM written with all logic 1.
[2]
External clock with 50 % duty factor.
[3]
The I2C-bus interface of PCF8532 is 5 V tolerant.
[4]
Variation between any 2 backplanes on a given voltage level; static measured.
[5]
Variation between any 2 segments on a given voltage level; static measured.
001aaj497
40
IDD(LCD)
(μA)
30
20
10
0
1
3
5
7
9
VLCD (V)
Tamb = 25 C; MUX 1:4; all RAM written with logic 1; no display connected; external clock with
fclk(ext) = 1.800 kHz.
Fig 24. IDD(LCD) (typical) with respect to VLCD
PCF8532
Product data sheet
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
13. Dynamic characteristics
Table 22. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 8.0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
fclk(int)
Parameter
Conditions
internal clock frequency
on pin CLK; see Table 12
[1]
[2]
Min
Typ
Max
Unit
900
1800
3000
Hz
fclk(ext)
external clock frequency
700
-
5000
Hz
tclk(H)
HIGH-level clock time
external clock source used
100
-
-
s
tclk(L)
LOW-level clock time
external clock source used
100
-
-
s
tPD(SYNC_N)
SYNC propagation delay
-
30
-
ns
tSYNC_NL
SYNC LOW time
100
-
-
s
tPD(drv)
driver propagation delay
-
10
-
s
VLCD = 5 V
Timing characteristics: I2C-bus
[3]
fSCL
SCL clock frequency
-
-
400
kHz
tBUF
bus free time between a
STOP and START condition
1.3
-
-
s
tHD;STA
hold time (repeated) START
condition
0.6
-
-
s
tSU;STA
set-up time for a repeated
START condition
0.6
-
-
s
tVD;ACK
data valid acknowledge time
-
-
1.2
s
tHIGH
HIGH period of the SCL clock
0.6
-
-
s
tLOW
LOW period of the SCL clock
1.3
-
-
s
tf
fall time
of both SDA and SCL signals
-
-
0.3
s
tr
rise time
of both SDA and SCL signals
-
-
0.3
s
Cb
capacitive load for each bus
line
-
-
400
pF
tSU;DAT
data set-up time
200
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
tSU;STO
set-up time for STOP
condition
0.6
-
-
s
tw(spike)
spike pulse width
-
-
50
ns
[1]
Typical output duty factor: 50 % measured at the CLK output pin.
[2]
For fclk(ext) > 4 kHz, it is recommended to use an external pull-up resistor between pin SYNC and pin VDD. The value of the resistor
should be between 100 k and 1 M. This resistor should be present even when no cascading configuration is used!
[3]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
PCF8532
Product data sheet
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
1 / fCLK
tclk(L)
tclk(H)
0.7 VDD
CLK
0.3 VDD
0.7 VDD
SYNC
0.3 VDD
tPD(SYNC_N)
tSYNC_NL
0.5 V
BP0 to BP3,
and S0 to S159
(VDD = 5 V)
0.5 V
tPD(drv)
001aah848
Fig 25. Driver timing waveforms
tVD;ACK
SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA
tSU;STO
001aah850
Fig 26. I2C-bus timing waveforms
PCF8532
Product data sheet
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
14. Application information
14.1 Pull-up resistor sizing on I2C-bus
14.1.1 Max value of pull-up resistor
The bus capacitance (Cb) is the total capacitance of wire, connections, and pins. This
capacitance on pin SDA limits the maximum value of the pull-up resistor (RPU) due to the
specified rise time.
According to the I2C-bus specification the rise time (tr) is defined between the VDD-related
input threshold of VIL = 0.3VDD and VIH = 0.7VDD. The value for tr(max) is 300 ns.
tr is calculated with Equation 7:
(7)
t r = t2 – t1
whereas t1 and t2 are the time since the charging started. The values for t1 and t2 are
derivatives of the functions V(t1) and V(t2):
V t1 = 0.3V DD = V DD 1 – e
V t2 = 0.7V DD = V DD 1 – e
-t1 R PU C b
-t2 R PU C b
(8)
(9)
with the results of
t1 = – R PU C b ln(0.7)
(10)
t2 = – R PU C b ln(0.3)
(11)
t r = – R PU C b ln(0.3) + R PU C b ln(0.7)
(12)
RPU(max) is a function of the rise time (tr) and the bus capacitance (Cb) and is calculated
with Equation 13:
tr
300 10 –9
R PU max = ----------------------- = -------------------------0.8473C b 0.8473C b
(13)
14.1.2 Min value of pull-up resistor
The supply voltage limits the minimum value of resistor RPU due to the specified minimum
sink current (see value of IOL on pin SDAACK in Table 21 on page 36). RPU(min) as a
function of VDD is calculated with Equation 14:
V DD – V OL
R PU min = -------------------------I OL
(14)
The designer now has the minimum and maximum value of RPU. The values for RPU(max)
and RPU(min) are shown in Figure 27 and Figure 28.
PCF8532
Product data sheet
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
001aak441
6
RPU(max)
(kΩ)
5
4
3
2
1
0
20
60
100
140
180
220
260
300
340
380
420
460
500
Cb (pF)
Fig 27. Values for RPU(max)
001aak440
6
RPU(min)
(kΩ)
5
4
3
2
1
0
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
Fig 28. Values for RPU(min)
14.2 ITO track resistance
If an application requires to have a low VDD supply voltage compared to the VLCD supply
voltage, it is recommended to increase the ITO resistance on the VLCD supply track in
order to reduce the noise induced on the VSS line when display is enabled. A low VDD
voltage supply and noise peaks on VSS induced by display activities may introduce
disturbances into the I2C communication with the microcontroller.
Figure 29 shows that, when the ITO resistance of the VSS pin has a certain value, it is
indicated to have a higher ITO resistance on the VLCD track, especially if VLCD (for
example, 9 V) is sharply higher than VDD (for example, 1.8 V). With a higher ITO
resistance on the VLCD track, the noise spikes induced to the VSS of the PCF8532 are
getting smaller and the functionality is less affected.
PCF8532
Product data sheet
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
DDD
9/&'
9
RSHUDWLQJUDQJHRI
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9'' 9
Tamb = 25 C; RITO(VSS) = 25 ; RITO(VDD) = 50 .
(1) RITO(VLCD) = 50 .
(2) RITO(VLCD) = 100 .
(3) RITO(VLCD) = 150 .
a. Operating range of the PCF8532 with RITO(VSS) = 25
9/&'
9
DDD
RSHUDWLQJUDQJHRI
3&)
9'' 9
Tamb = 25 C; RITO(VSS) = 50 ; RITO(VDD) = 50 .
(1) RITO(VLCD) = 50 .
(2) RITO(VLCD) = 75 .
(3) RITO(VLCD) = 100 .
(4) RITO(VLCD) = 150 .
(5) RITO(VLCD) = 200 .
(6) RITO(VLCD) = 300 .
b. Operating range of the PCF8532 with RITO(VSS) = 50
Fig 29. Operating range of the PCF8532 with respect to the ITO track resistance
PCF8532
Product data sheet
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
14.3 SDA and SDAACK configuration
The Serial DAta Line (SDA) and the I2C-bus acknowledge line (SDAACK) are split. Both
lines can be connected together to facilitate a single-line SDA.
SDA
SDA
SDAACK
SDAACK
two wire mode
single wire mode
013aaa111
Fig 30. SDA, SDAACK configurations
14.4 Cascaded operation
In large display configurations, up to 8 PCF8532 can be distinguished on the same
I2C-bus by using the 2-bit hardware subaddress (A0 and A1) and the programmable
I2C-bus slave address (SA0).
Table 23.
Addressing cascaded PCF8532
Cluster
Bit SA0
Pin A1
Pin A0
Device
1
0
0
0
0
0
1
1
1
0
2
1
1
3
0
0
4
0
1
5
1
0
6
1
1
7
2
1
When cascaded PCF8532 are synchronized, they can share the backplane signals from
one of the devices in the cascade. Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one device need to be through-plated to
the backplane electrodes of the display. The other PCF8532 of the cascade contribute
additional segment outputs but their backplane outputs are left open-circuit (see Figure 31
on page 45).
For display sizes that are not multiple of 640 elements, a mixed cascaded system can be
considered containing only devices like PCF8532 and PCA85133. Depending on the
application, one must take care of the software commands compatibility and pin
connection compatibility.
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF8532. This synchronization is guaranteed after the Power-On Reset (POR). The only
time that SYNC is likely to be needed is if synchronization is accidentally lost (for
example, by noise in adverse electrical environments, or by the definition of a multiplex
mode when PCF8532 with different SA0 levels are cascaded). SYNC is organized as an
input/output pin; the output selection being realized as an open-drain driver with an
internal pull-up resistor. A PCF8532 asserts the SYNC line at the onset of its last active
backplane signal and monitors the SYNC line at all other times. Should synchronization in
PCF8532
Product data sheet
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
the cascade be lost, it is restored by the first PCF8532 to assert SYNC. The timing
relationship between the backplane waveforms and the SYNC signal for the various drive
modes of the PCF8532 are shown in Figure 33 on page 47.
When using an external clock signal with high frequencies (fclk(ext) > 4 kHz), it is
recommended to have an external pull-up resistor between pin SYNC and pin VDD (see
Table 22 on page 38). This resistor should be present even when no cascading
configuration is used! When using it in a cascaded configuration, care must be taken not
to route the SYNC signal to close to noisy signals.
The contact resistance between the SYNC pads of cascaded devices must be controlled.
If the resistance is too high, the device is not able to synchronize properly. This is
particularly applicable to COG applications. Table 24 shows the limiting values for contact
resistance.
Table 24.
SYNC contact resistance
Number of devices
Maximum contact resistance
2
6000
3 to 5
2200
6 to 8
1200
In the cascaded applications, the OSC pin of the PCF8532 with subaddress 0 is
connected to VSS so that this device uses its internal clock to generate a clock signal at
the CLK pin. The other PCF8532 devices are having the OSC pin connected to VDD,
meaning that these devices are ready to receive external clock, the signal being provided
by the device with subaddress 0.
If the master is providing the clock signal to the slave devices, care must be taken that the
sending of display enable or disable is received by both, the master and the slaves at the
same time. When the display is disabled, the output from pin CLK is disabled too. The
disconnection of the clock may result in a DC component for the display.
Alternatively, the schematic can be also constructed such that all the devices have OSC
pin connected to VDD and thus an external CLK being provided for the system (all devices
connected to the same external CLK).
A configuration where SYNC is connected but all PCF8532 are using their internal clock
(OSC pin tied to VSS) should not be used and may lead to display artifacts!
PCF8532
Product data sheet
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PCF8532
NXP Semiconductors
Universal LCD driver for low multiplex rates
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