PCF8536
Universal LCD driver for low multiplex rates including a 6
channel PWM generator
Rev. 3 — 2 November 2021
1
Product data sheet
General description
The PCF8536 is a peripheral device which interfaces to almost any Liquid Crystal Display
1
(LCD) with low multiplex rates. It generates the drive signals for any multiplexed LCD
containing up to eight backplanes, up to 44 segments, and up to 320 elements. The
PCF8536 is compatible with most microcontrollers and communicates via the two-line
2
bidirectional I C-bus (PCF8536AT) or a three line unidirectional SPI-bus (PCF8536BT).
Communication overheads are minimized using a display RAM with auto-incremented
addressing.
The PCF8536 features an on-chip PWM controller for LED illumination. Up to six
independent channels can be configured. Each channel has 128 levels allowing the
possibility for two RGB controllers. Each of them provides over 2 million colors. Each
channel can also be used for static drive.
2
Features and benefits
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single-chip 320 segment LCD controller and driver with 6 channel PWM generator
6 channel PWM generator for backlight LED illumination
Selectable display bias configuration
Wide range for digital power supply: from 1.8 V to 5.5 V
Wide LCD supply range: from 2.5 V for low threshold LCDs and up to 9.0 V for high
threshold twisted nematic LCDs
Low power consumption
Selectable backplane drive configuration: 4, 6, or 8 backplane multiplexing
LCD and logic supplies may be separated
320-bit RAM for display data storage
6 PWM outputs with a 7-bit resolution (128 steps) and drivers for external transistors
Programmable PWM frame frequency to avoid LCD backlight flickering
2
400 kHz I C-bus interface (PCF8536AT)
5 MHz SPI-bus interface (PCF8536BT)
Programmable frame frequency in the range of 60 Hz to 300 Hz in steps of 10 Hz;
factory calibrated
320 segments driven allowing:
– up to 40 7-segment alphanumeric characters
– up to 20 14-segment alphanumeric characters
– any graphics of up to 320 elements
Manufactured in silicon gate CMOS process
1 The definition of the abbreviations and acronyms used in this data sheet can be found in Section 18.
PCF8536
NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
3
Applications
• White goods and consumer products
4
Ordering information
Table 1. Ordering information
Type number
Interface
Topside
type
mark
PCF8536AT/1
I C-bus
Package
Name
PCF8536AT TSSOP56
PCF8536BT/1
SPI-bus
PCF8536BT TSSOP56
2
Description
plastic thin shrink small outline package; 56
leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2
mm body
plastic thin shrink small outline package; 56
leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2
mm body
Version
SOT364-1
SOT364-1
4.1 Ordering options
Table 2. Ordering options
Type number
Orderable part number
PCF8536AT/1
PCF8536AT/1,118
[2]
PCF8536AT/1Y
PCF8536BT/1
PCF8536BT/1,118
PCF8536BT/1Y
[1]
[2]
[3]
Packing method
TSSOP56
reel 13 inch q1 non
dry pack
reel 13 inch q1 dry
pack
reel 13 inch q1 non
dry pack
reel 13 inch q1 dry
pack
TSSOP56
[3]
[1]
Package
TSSOP56
TSSOP56
Minimum
order
quantity
2000
Temperature
2000
Tamb = -40 °C to +85 °C
2000
Tamb = -40 °C to +85 °C
2000
Tamb = -40 °C to +85 °C
Tamb = -40 °C to +85 °C
Standard packing quantities and other packaging data are available at www.nxp.com/packages/.
Discontinuation Notice 202107021DN - drop in replacement is PCF8536AT/1Y - this is documented in PCN202102010F01.
Discontinuation Notice 202107021DN - drop in replacement is PCF8536BT/1Y - this is documented in PCN202102010F01.
PCF8536
Product data sheet
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PCF8536
NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
5
Block diagram
VDD
BP4 to BP7/
S40 to S43
BP0 to BP3
S6 to S39
S0/GP0 to
S5/GP5
VLCD
BACKPLANE
OUTPUTS
LCD
VOLTAGE
SELECTOR
DISPLAY SEGMENT
OUTPUTS
GPO/PWM
GENERATOR
DISPLAY REGISTER
VSS
OSCCLK
LCD BIAS
GENERATOR
OSCILLATOR
AND CLOCK
SELECTION
POWER-ON
RESET
RESET
SCL
SDA
PRESCALER
AND TIMING
INPUT
FILTERS
DISPLAY RAM
AND
PWM REGISTERS
PCF8536AT
COMMAND
DECODER
WRITE DATA
CONTROL
DATA POINTER,
AUTO INCREMENT
I2C-BUS
CONTROLLER
013aaa419
A0
Figure 1. Block diagram of PCF8536AT
PCF8536
Product data sheet
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PCF8536
NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
VDD
BP4 to BP7/
S40 to S43
BP0 to BP3
S6 to S39
S0/GP0 to
S5/GP5
VLCD
BACKPLANE
OUTPUTS
LCD
VOLTAGE
SELECTOR
DISPLAY SEGMENT
OUTPUTS
GPO/PWM
GENERATOR
DISPLAY REGISTER
VSS
OSCCLK
LCD BIAS
GENERATOR
OSCILLATOR
AND CLOCK
SELECTION
PRESCALER
AND TIMING
POWER-ON
RESET
RESET
SCL
DISPLAY RAM
AND
PWM REGISTERS
PCF8536BT
COMMAND
DECODER
WRITE DATA
CONTROL
DATA POINTER,
AUTO INCREMENT
SPI-BUS
CONTROLLER
SDI
013aaa429
CE
Figure 2. Block diagram of PCF8536BT
6
Pinning information
6.1 Pinning
PCF8536
Product data sheet
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PCF8536
NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
S9
1
56 S8
S9
1
56 S8
S10
2
55 S7
S10
2
55 S7
S11
3
54 S6
S11
3
54 S6
S12
4
53 S5/GP5
S12
4
53 S5/GP5
S13
5
52 S4/GP4
S13
5
52 S4/GP4
S14
6
51 S3/GP3
S14
6
51 S3/GP3
S15
7
50 S2/GP2
S15
7
50 S2/GP2
S16
8
49 S1/GP1
S16
8
49 S1/GP1
S17
9
48 S0/GP0
S17
9
48 S0/GP0
S18 10
47 VLCD
S18 10
47 VLCD
S19 11
46 OSCCLK
S19 11
46 OSCCLK
BP0/S32 12
45 VDD
BP0/S32 12
45 VDD
BP1/S33 13
44 VSS
BP1/S33 13
44 VSS
BP2/S34 14
43 RESET
BP2/S34 14
42 SDA
BP3/S35 15
BP4/S43/S36 16
41 SCL
BP4/S43/S36 16
41 SCL
BP5/S42/S37 17
40 A0
BP5/S42/S37 17
40 CE
BP6/S41/S38 18
39 S39/BP0
BP6/S41/S38 18
39 S39/BP0
BP7/S40/S39 19
38 S38/BP1
BP7/S40/S39 19
38 S38/BP1
S20 20
37 S37/BP2
S20 20
37 S37/BP2
S21 21
36 S36/BP3
S21 21
36 S36/BP3
S22 22
35 S35/BP4/S43
S22 22
35 S35/BP4/S43
S23 23
34 S34/BP5/S42
S23 23
34 S34/BP5/S42
S24 24
33 S33/BP6/S41
S24 24
33 S33/BP6/S41
S25 25
32 S32/BP7/S40
S25 25
32 S32/BP7/S40
S26 26
31 S31
S26 26
31 S31
S27 27
30 S30
S27 27
30 S30
S28 28
29 S29
S28 28
29 S29
BP3/S35 15
PCF8536AT
43 RESET
PCF8536BT
013aaa430
42 SDI
013aaa431
Top view. For mechanical details, see Figure 51.
Top view. For mechanical details, see Figure 51.
Figure 3. Pin configuration for TSSOP56 (PCF8536AT)
Figure 4. Pin configuration for TSSOP56 (PCF8536BT)
PCF8536
Product data sheet
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PCF8536
NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
6.2 Pin description
Table 3. Pin description of PCF8536AT and PCF8536BT
Pin
Symbol
Type
Description
1 to 11
S9 to S19
output
LCD segment
20 to 31
S20 to S31
output
LCD segment
43
RESET
input
active LOW reset input
44
VSS
supply
ground supply voltage
45
VDD
supply
supply voltage
46
OSCCLK
input/output external clock input/internal oscillator
output
47
VLCD
supply
LCD supply voltage
48 to 53
S0/GP0 to S5/GP5
output
LCD segment/GPO (PWM) output
54 to 56
S6 to S8
output
LCD segment
[1]
[2]
Pin layout depending on backplane swap configuration
[3]
BPS = 0
BPS = 1
12
BP0
S32
13
BP1
S33
14
BP2
S34
15
BP3
S35
16
BP4/S43
S36
17
BP5/S42
S37
18
BP6/S41
S38
19
BP7/S40
S39
32
S32
BP7/S40
33
S33
BP6/S41
34
S34
BP5/S42
35
S35
BP4/S43
36
S36
BP3
37
S37
BP2
38
S38
BP1
39
S39
BP0
output
LCD backplane/LCD segment
Pin layout depending on product and bus type
PCF8536AT
40
PCF8536BT
A0
CE
41
SCL
SCL
PCF8536
Product data sheet
2
input
I C-bus target address selection
input
SPI-bus chip enable - active LOW
input
I C-bus serial clock
input
SPI-bus serial clock
2
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PCF8536
NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Table 3. Pin description of PCF8536AT and PCF8536BT...continued
Pin
Symbol
Type
42
SDA
input/output I C-bus serial data
2
SDI
[1]
[2]
[3]
7
Description
input
SPI-bus data input
VLCD must be equal to or greater than VDD.
Effect of backplane swapping is illustrated in Figure 5.
Bit BPS is explained in Section 7.1.4.
Functional description
The PCF8536 is a versatile peripheral device designed to interface any microcontroller
to a wide variety of LCDs and 6 backlight LEDs. It can directly drive any multiplexed LCD
containing up to eight backplanes and up to 44 segments.
7.1 Commands of PCF8536
The PCF8536 is controlled by 15 commands, which are defined in Table 4. Any other
combinations of operation code bits that are not mentioned in this document may lead to
undesired operation modes of PCF8536.
Table 4. Commands of PCF8536
Command name
Register
selection
[1]
RS[1:0]
Bits
7
6
5
4
3
2
1
0
initialize
0
0
0
0
0
1
0
1
1
0
Section 7.1.1
OTP-refresh
0
0
1
1
1
1
0
0
0
0
Section 7.1.2
PWM-inversion
0
0
0
0
0
1
0
1
0
PWMI Section 7.1.3
mode-settings
0
0
0
1
0
1
BPS
INV
PD
E
Section 7.1.4
oscillator-control
0
0
0
0
0
1
1
EFR
COE
OSC
Section 7.1.5
GPO-output-config
0
0
1
1
0
0
GPM1[1:0]
GPM0[1:0]
0
0
1
1
0
1
GPM3[1:0]
GPM2[1:0]
0
0
1
1
1
0
GPM5[1:0]
GPM4[1:0]
set-MUX-mode
0
0
0
0
0
0
0
0
M[1:0]
Section 7.1.7
set-bias-mode
0
0
0
0
0
0
0
1
B[1:0]
Section 7.1.8
frame-frequency-LCD
0
0
0
0
1
FD[4:0]
frame-frequency-PWM
0
0
0
1
0
0
FP[3:0]
GPO-static-data
0
0
0
1
1
0
0
GPO2 GPO1 GPO0 Section 7.1.11
0
0
0
1
1
0
1
GPO5 GPO4 GPO3
load-data-pointer-LCD
0
0
1
0
DP[5:0]
load-data-pointer-PWM
0
0
0
1
1
write-RAM-data
0
1
D[7:0]
write-PWM-data
1
0
0
[1]
Reference
Section 7.1.6
Section 7.1.9
Section 7.1.10
Section 7.1.12
1
0
PP[2:0]
Section 7.1.13
Section 7.1.14
P[6:0]
Section 7.1.15
Information about control byte and register selection see Section 8.1.
PCF8536
Product data sheet
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PCF8536
NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
7.1.1 Command: initialize
This command generates a chip-wide reset. It has the same function as the RESET pin.
Reset takes 1 ms to complete.
Table 5. Initialize - initialize command bit description
Bit
Symbol
Value
Description
7 to 0
-
0001 0110
fixed value
7.1.2 Command: OTP-refresh
During production and testing of the device, each IC is calibrated to achieve the specified
accuracy of the frame frequency. This calibration is performed on EPROM cells called
One Time Programmable (OTP) cells. The device reads these cells every time the OTPrefresh command is sent. This instruction has to be sent after a reset has been made and
before the display is enabled.
This command will be completed after a maximum of 30 ms and requires either the
internal or external clock to run. If the internal oscillator is not used, then a clock must
be supplied to the OSCCLK pin. If the OTP-refresh instruction is sent and no clock is
present, then the request is stored until a clock is available.
Remark: It is recommended not to enter power-down mode during the OTP refresh
cycle.
Table 6. OTP-refresh - OTP-refresh command bit description
Bit
Symbol
Value
Description
7 to 0
-
1111 0000
fixed value
7.1.3 Command: PWM-inversion
It is possible to invert the output of the PWM generators. This function may be
useful for counteracting EMC issues. The description of this mode can be found in
Section 7.11.2page 45.
Table 7. PWM-inversion - PWM inversion command bit description
Bit
Symbol
Value
Description
7 to 1
-
0001 010
fixed value
0
PWMI
PWM inversion mode
1
0
[1]
PWM inversion mode on
[1]
PWM inversion mode off
Default value.
7.1.4 Command: mode-settings
Table 8. Mode-settings - mode settings command bit description
PCF8536
Product data sheet
Bit
Symbol
Value
Description
7 to 4
-
0101
fixed value
3
BPS
backplane swapping
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PCF8536
NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Table 8. Mode-settings - mode settings command bit description...continued
Bit
Symbol
Value
0
[1]
1
2
set inversion mode
[1][2]
1
set power mode
PD
power-down mode; backplane and segment
outputs are connected to VSS and the
internal oscillator is switched off
0
[1]
0
[1]
power-up mode
display switch
E
1
[1]
[2]
Driving scheme A: LCD line inversion mode
Driving scheme B: LCD frame inversion
mode
1
0
backplane configuration 0
backplane configuration 1
INV
0
1
Description
display disabled; backplane and segment
outputs are connected to VSS
display enabled
Default value.
See Section 7.1.4.2.
7.1.4.1 Backplane swapping
Backplane swapping can be configured with the BPS bit (see Table 8). It moves the
location of the backplane and the associated segment outputs from one side of the
PCF8536 to the other. Backplane swapping is sometimes desirable to aid with the routing
of PCBs that do not use multiple layers.
The BPS bit has to be set to the required value before enabling the display. Failure to do
so does not damage the PCF8536 or the display, however unexpected display content
may appear.
PCF8536
Product data sheet
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PCF8536
NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
BP0 12
S32 12
BP1 13
S33 13
BP2 14
S34 14
BP3 15
S35 15
BP4/S43 16
S36 16
BP5/S42 17
S37 17
BP6/S41 18
39 S39
S38 18
39 BP0
BP7/S40 19
38 S38
S39 19
38 BP1
S20 20
37 S37
S20 20
37 BP2
S21 21
36 S36
S21 21
36 BP3
S22 22
35 S35
S22 22
35 BP4/S43
S23 23
34 S34
S23 23
34 BP5/S42
S24 24
33 S33
S24 24
33 BP6/S41
S25 25
32 S32
S25 25
32 BP7/S40
S26 26
31 S31
S26 26
31 S31
S27 27
30 S30
S27 27
30 S30
S28 28
29 S29
S28 28
29 S29
BPS = 1
BPS = 0
013aaa432
Figure 5. Effect of backplane swapping
7.1.4.2 Line inversion (driving scheme A) and frame inversion (driving scheme B)
The DC offset of the voltage across the LCD is compensated over a certain period: linewise in line inversion mode (driving scheme A) or frame-wise in frame inversion mode
(driving scheme B). With the INV bit (see Table 8), the compensation mode can be
switched.
In frame inversion mode, the DC value is compensated across two frames and not
within one frame. Changing the inversion mode to frame inversion reduces the power
consumption; therefore it is useful when power consumption is a key point in the
application.
Frame inversion may not be suitable for all applications. The RMS voltage across a
segment is better defined; however, since the switching frequency is reduced, there is
possibility for flicker to occur.
The waveforms of Figure 15 to Figure 18 are showing line inversion mode. Figure 19
shows an example of frame inversion.
7.1.4.3 Power-down mode
The power-down bit (PD) allows the PCF8536 to be put in a minimum power
configuration. In order to avoid display artefacts, it is recommended to enter power-down
only after the display has been switched off by setting bit E to logic 0.
During power-down, the internal oscillator is switched off and any selected PWM output
is revert to the static value stored in bits GPO0 to GPO5. These bits may be programmed
to give a static logic 0 or static logic 1 on selected GP0 to GP5 pins.
PCF8536
Product data sheet
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PCF8536
NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Table 9. Effect of the power-down bit (PD)
Effect on function
Mode settings
Effect of setting PD
0
1
backplane output
E=1
normal function
VSS
segment output
E=1
normal function
VSS
internal oscillator
OSC = 0, COE = 1
on
off
OSCCLK pin
OSC = 0, COE = 1
output of internal
oscillator frequency
VDD
OSCCLK pin
OSC = 1
input clock
clock input, can be
logic 0, logic 1, or left
floating
GPO
static drive
static drive
static drive
GPO
PWM drive
PWM drive
static drive
With the following sequence, the PCF8536 can be set to a state of minimum power
consumption, called power-down mode.
START
Disable display
by setting bit E
logic 0
External clock
can be
removed now
Enable powerdown mode
with PD = 1
STOP
013aaa447
Figure 6. Recommended power-down sequence
Remarks:
• It is necessary to run the power-down sequence before removing the supplies.
Depending on the application, care must be taken that no other signals are present at
the chip input or output pins when removing the supplies (see Section 9). Otherwise
it may cause unwanted display artifacts. In case of an uncontrolled removal of supply
voltages, the PCF8536 will not be damaged.
• Static voltages across the liquid crystal display can build up when the external LCD
supply voltage (VLCD) is on while the IC supply voltage is off, or vice versa. This may
cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be
applied or removed together.
PCF8536
Product data sheet
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PCF8536
NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
• A clock signal must always be supplied to the device when the display is active.
Removing the clock may freeze the LCD in a DC state, which is not suitable for the
liquid crystal. It is recommended to disable the display first and afterwards to remove
the clock signal.
7.1.4.4 Display enable
The display enable bit (E) is used to enable and disable the display. When the display
is disabled, all LCD outputs go to VSS. This function is implemented to ensure that no
voltage can be induced on the LCD outputs as it may lead to unwanted displays of
segments.
Recommended start-up sequences are found in Section 7.2.3
Remarks:
• The state of display enable has no effect on the GPO outputs.
• Display enable is not synchronized to an LCD frame boundary. Therefore using this
function to flash a display for prolonged periods is not recommended due to the
possible build-up of DC voltages on the display.
7.1.5 Command: oscillator-control
The oscillator-control command switches between internal and external oscillator
and enables or disables the pin OSCCLK. It is also used to define what the external
frequency will be.
Table 10. Oscillator-control - oscillator control command bit description
Bit
Symbol
Value
Description
7 to 3
-
0001 1
fixed value
2
EFR
external clock frequency applied on pin
OSCCLK
0
[1]
1
1
230 kHz
clock output enable for pin OSCCLK
COE
0
[1]
1
0
clock signal not available on pin OSCCLK;
pin OSCCLK is in 3-state
clock signal available on pin OSCCLK
oscillator source
OSC
0
[1]
1
[1]
9.6 kHz
internal oscillator running
external oscillator used;
pin OSCCLK becomes an input;
used in combination with EFR to determine
input frequency
Default value.
The bits OSC, COE, and EFR control the source and frequency of the clock used to
generate the LCD and PWM signals (see Figure 7). Valid combinations are shown in
Table 11.
PCF8536
Product data sheet
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PCF8536
NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
COE (1)
EFR (2)
OSCCLK
pin
0
1
Internal oscillator
230 kHz
Programmable
divider
0
OSC
LCD frame frequency
selection, q
0
1.
2.
3.
4.
9.6 kHz (3)
Programmable
divider
1
(4)
1
LCD waveform
generator
PWM waveform
generator
PWM frame frequency
selection, p
013aaa448
Can only be used with the internal oscillator (OSC = 0).
Can only be used with an external oscillator (OSC = 1).
Nominal value for divide factor q is 24; source clock is 230 kHz (see Section 7.1.9).
PWM requires an external or internal 230 kHz clock.
Figure 7. Oscillator selection
Table 11. Valid combinations of bits OSC, EFR, and COE
OSC
COE
EFR
OSCCLK pin
Clock source
0
0
not used
inactive;
may be left floating
internal oscillator used
0
1
not used
output of internal oscillator
frequency (prescaler)
internal oscillator used
1
not used
0
9.6 kHz input
OSCCLK pin
1
not used
1
230 kHz input
OSCCLK pin
Table 12. Typical use of bits OSC, EFR, and COE
Usage
OSC
CDE
EFR
LCD and/or PWM with internal oscillator
0
0
not used
LCD and PWM with external oscillator
1
not used
1
LCD with external oscillator
1
not used
0
7.1.5.1 Oscillator
The internal logic and LCD drive signals of the PCF8536 are timed either by the built-in
oscillator or from an external clock.
Internal clock
When the internal oscillator is used, all LCD and PWM signals are generated from it. The
oscillator runs at nominal 230 kHz. The relationship between this frequency and the LCD
frame frequency is detailed in Section 7.1.9. The relationship between this frequency and
the PWM frame frequency is detailed in Section 7.1.10.
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Control over the internal oscillator is made with the OSC bit (see Section 7.1.5). The
internal oscillator is also switched on or off under certain combinations of modes which
are described in Table 13.
Table 13. Internal oscillator on/off table
PD
OSC
PWM
EFR
Internal
[1]
oscillator state
power-down
n.a.
n.a.
n.a.
off
power-up
internal oscillator
n.a.
n.a.
on
external oscillator
off
n.a.
off
on
9.6 kHz
on
on
230 kHz
off
[1]
[2]
[2]
When RESET is active, the internal oscillator is off.
Special case. The PWM generator needs 230 kHz and must be enabled when PWM is enabled.
It is possible to make the internal oscillator signal available on pin OSCCLK by using the
oscillator-control command (see Table 10) and configuring the clock output enable (COE)
bit. If not required, the pin OSCCLK should be left open or connected to VSS. At power-on
the signal at pin OSCCLK is disabled and pin OSCCLK is in 3-state.
Clock output is only valid when using the internal oscillator. The signal will appear on the
OSCCLK pin.
An intermediate clock frequency is available at the OSCCLK pin. The duty cycle of this
clock varies with the chosen divide ratio.
Table 14. OSCCLK table
[1]
PD
OSC
COE
EFR
OSCCLK pin
power-down
n.a.
off
n.a.
3-state
power-down
n.a.
on
n.a.
VDD
power-up
internal oscillator
off
n.a.
3-state
on
n.a.
9.6 kHz output
n.a.
9.6 kHz
9.6 kHz input
230 kHz
230 kHz input
external oscillator
[1]
[2]
[3]
[2]
[3]
When RESET is active, the internal oscillator is off.
In this state, an external clock may be applied, but it is not a requirement.
9.6 kHz is the nominal frequency with q = 24, see Table 15.
1. When RESET is active, the pin OSCCLK is in 3-state.
External clock
In applications where an external clock must be applied to the PCF8536, bit OSC (see
Table 10) has to be set logic 1. In this case pin OSCCLK becomes an input.
The OSCCLK signal must switch between the VSS and the VDD voltage supplied to the
chip.
The system is designed for a 230 kHz clock or alternatively for using a 9.6 kHz clock.
The EFR bit determines the external clock frequency. The clock frequency (fclk(ext)) in turn
determines the LCD frame frequency, see Table 15.
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The PWM generator requires a 230 kHz clock to operate. If PWM is enabled and an
external clock of 9.6 kHz is selected, then the internal oscillator will automatically start
and be used for the PWM signal generation.
Remark: If an external clock is used, then this clock signal must always be supplied to
the device when the display is on. Removing the clock may freeze the LCD in a DC state
which will damage the LCD material.
7.1.5.2 Timing and frame frequency
The timing of the PCF8536 organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. The
timing also generates the LCD frame frequency which it derives as an integer division of
the clock frequency (see Table 15). The frame frequency is a fixed division of the internal
clock or of the frequency applied to pin OSCCLK when an external clock is used.
Table 15. LCD frame frequencies
Frame frequency
[1]
[1]
Typical external Nominal frame
frequency (Hz)
frequency (Hz)
EFR bit
Value of q
9 600
200
0
-
230 000
200
1
24
Other values of the frame frequency prescaler see Table 21.
When the internal clock is used, or an external clock with EFR = 1, the LCD frame
frequency can be programmed by software in steps of approximately 10 Hz in the
range of 60 Hz to 300 Hz (see Table 21). Furthermore the internal oscillator is factory
calibrated, see Table 44.
7.1.6 Command: GPO-output-config
The behavior of the combined LCD and GPO outputs S5/GP5 to S0/GP0 is configured
with the bits described in Table 16.
Table 16. GPO-output-config - output mode config command for S5/GP5 to S0/GP0
Bit
Symbol
Value
Description
GPM0 and GPM1
7 to 4
-
1100
fixed value
3 to 2
GPM1[1:0]
see Table 17
output mode for S1/GP1
1 to 0
GPM0[1:0]
see Table 17
output mode for S0/GP0
GPM2 and GPM3
7 to 4
-
1101
fixed value
3 to 2
GPM3[1:0]
see Table 17
output mode for S3/GP3
1 to 0
GPM2[1:0]
see Table 17
output mode for S2/GP2
GPM4 and GPM5
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Product data sheet
7 to 4
-
1110
fixed value
3 to 2
GPM5[1:0]
see Table 17
output mode for S5/GP5
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Table 16. GPO-output-config - output mode config command for S5/GP5 to S0/GP0...continued
Bit
Symbol
Value
Description
1 to 0
GPM4[1:0]
see Table 17
output mode for S4/GP4
Each output can be individually configured to be either an LCD segment output, a PWM
output or a static general-purpose output (GPO), see Table 17.
Remark: Even if using GPO only, VLCD must still be applied to the device.
Table 17. GPMO mode definition
GPM0[1:0] to GPM5[1:0]
Mode
Description
00 , 01
LCD
output is an LCD segment
10
static
output is static GPO
11
PWM
output is PWM GPO
[1]
[1]
Default value.
7.1.7 Command: set-MUX-mode
The multiplex drive mode is configured with the bits described in Table 18.
Table 18. Set-MUX-mode - set multiplex drive mode command bit description
Bit
Symbol
Value
Description
7 to 2
-
0000 00
fixed value
1 to 0
[1]
[1]
M[1:0]
00 , 01
1:8 multiplex drive mode; eight backplanes
10
1:6 multiplex drive mode; 6 backplanes
11
1:4 multiplex drive mode; 4 backplanes
Default value.
7.1.8 Command: set-bias-mode
The set-bias-mode command allows setting the bias level.
Table 19. Set-bias-mode - set bias mode command bit description
Bit
Symbol
Value
Description
7 to 2
-
0000 01
fixed value
1 to 0
[1]
B[1:0]
[1]
00 . 01
1
11
1
10
1
⁄4 bias
⁄3 bias
⁄2 bias
Default value.
7.1.9 Command: frame-frequency-LCD
With the frame-frequency-LCD command, the frame frequency for the display can be
configured. The clock frequency determines the frame frequency.
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Table 20. Frame-frequency-LCD - frame frequency and output clock frequency command bit
description
Bit
Symbol
Value
Description
7 to 5
-
001
fixed value
4 to 0
FD[4:0]
see Table 21
frequency prescaler
The system is designed for a 230 kHz clock. It is either internally generated or externally
provided. Alternatively a 9.6 kHz clock signal can be provided as well. The EFR bit (see
Table 10) has to be set according to the external clock frequency.
When EFR is set to 9.6 kHz, then the LCD frame frequency is calculated with Equation 1:
(1)
When EFR is set to 230 kHz, then the LCD frame frequency is calculated with Equation
2:
(2)
where q is the frequency divide factor (see Table 21).
Remark: fclk(ext) is the external input clock frequency to pin OSCCLK.
When the internal oscillator is used, the intermediate frequency may be output on the
OSCCLK pin. Its frequency is given in Table 21.
Table 21. Frame frequency prescaler values for 230 kHz clock operation
FD[4:0]
Nominal LCD frame
[1]
frequency (Hz)
Divide factor, q
Intermediate clock
frequency (Hz)
0 0000
59.9
80
2 875
0 0001
70.5
68
3 382
0 0010
79.9
60
3 833
0 0011
90.4
53
4 340
0 0100
99.8
48
4 792
0 0101
108.9
44
5 227
0 0110
119.8
40
5 750
0 0111
129.5
37
6 216
0 1000
140.9
34
6 765
0 1001
149.7
32
7 188
0 1010
159.7
30
7 667
0 1011
171.1
28
8 214
0 1100
177.5
27
8 519
0 1101
191.7
25
9 200
199.7
24
9 583
0 1111
208.3
23
10 000
1 0000
217.8
22
10 455
0 1110
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Table 21. Frame frequency prescaler values for 230 kHz clock operation...continued
FD[4:0]
Nominal LCD frame
[1]
frequency (Hz)
Divide factor, q
Intermediate clock
frequency (Hz)
1 0001
228.3
21
10 952
1 0010
239.6
20
11 500
1 0011
252.2
19
12 105
1 0100
266.2
18
12 778
1 0101
281.9
17
13 529
1 0110
299.5
16
14 375
1 0111 to 1 1111
not used
[1]
[2]
Nominal frame frequency calculated for the default clock frequency of 230 kHz.
Default value.
7.1.10 Command: frame-frequency-PWM
With the frame-frequency-PWM command, the frame frequency for the PWM signal can
be set.
The PWM system requires a clock of 230 kHz either internally generated or externally
supplied. Using a slower clock may result in visible flickering of LEDs driven with the
PWM signal.
When EFR is set to 230 kHz, then the PWM frame frequency will be calculated with
Equation 3:
(3)
where p is the frequency divide factor (see Table 23).
Table 22. Frame-frequency-PWM - PWM frame frequency command bit description
Bit
Symbol
Value
Description
7 to 4
-
0100
fixed value
3 to 0
FP[3:0]
see Table 23
frequency prescaler
Table 23. PWM frame frequency prescaler values for 230 kHz clock operation
Nominal PWM frame frequency (Hz)
Divide factor, p
0000
59.9
30
0001
69.1
26
0010
81.7
22
0011
89.8
20
0100
99.8
18
0101
112.3
16
0110
119.8
15
128.3
14
0111
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FP[3:0]
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Table 23. PWM frame frequency prescaler values for 230 kHz clock operation...continued
[1]
FP[3:0]
Nominal PWM frame frequency (Hz)
Divide factor, p
1000
138.2
13
1001
149.7
12
1010
163.4
11
1011
179.7
10
1100
199.7
9
1101
224.6
8
1110
256.7
7
1111
299.5
6
[1]
[2]
Nominal frame frequency calculated for the default clock frequency of 230 kHz.
Default value.
In order to avoid flickering caused by the interaction of the backlight LED and the LCD
frame frequency, the PWM frame frequency should be programmed to be more than 50
Hz different from LCD frame frequency or multiples of the LCD frame frequency (see
Figure 8 and Table 49 on page 68).
Intensity of
visible flickering
Flickering is most
visible when fPWM
and ffr(LCD) are within
10 Hz of each other
In general, the higher the PWM frame
frequency, the less flickering will be visible
Flickering is also visible at multiples
of the fundamental frequency;
however, the visibility is lower
Flickering will not be
visible when fPWM
and ffr(LCD) are more
than 50 Hz apart
f1
2f1
This will repeat for 3f1, 4f1, etc.
f0
013aaa449
Where f0 = fPWM and f1 = ffr(LCD) or f1 = fPWM and f0 = ffr(LCD).
Figure 8. Flicker avoidance for LED backlighting
7.1.11 Command: GPO-static-data
When static GPOs are selected instead of PWM, then the value for the output is taken
from these register bits. The output is a static level.
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Table 24. GPO-static-data - write GPO data for GP0 to GP5 command bit
description
Bit
Symbol
Value
Description
0110 0
fixed value
GPO0 to GPO2
7 to 3
2
-
0
GPO2
[1]
0 level output on pin GP2
1
1
0
GPO1
1 level output on pin GP2
[1]
0 level output on pin GP1
1
0
0
GPO0
1 level output on pin GP1
[1]
0 level output on pin GP0
1
1 level output on pin GP0
GPO3 to GPO5
7 to 3
2
-
0110 1
0
GPO5
fixed value
[1]
0 level output on pin GP5
1
1
0
GPO4
1 level output on pin GP5
[1]
0 level output on pin GP4
1
0
0
GPO3
1 level output on pin GP4
[1]
0 level output on pin GP3
1
[1]
1 level output on pin GP3
Default value.
7.1.12 Command: load-data-pointer-LCD
The load-data-pointer-LCD command defines the start address of the display RAM. The
data pointer is auto incremented after each RAM write. The size of the display RAM is
dependent on the current multiplex drive mode setting, see Table 25.
Table 25. Load-data-pointer-LCD - load data pointer command bit description
Bit
Symbol
Value
Description
7 to 6
-
10
fixed value
Multiplex drive mode 1:8
5 to 0
DP[5:0]
00 0000
10 0111
[1]
to
6-bit binary value of 0 to 39
00 0000
10 1001
[1]
to
6-bit binary value of 0 to 41
00 0000
10 1011
[1]
to
6-bit binary value of 0 to 43
Multiplex drive mode 1:6
5 to 0
DP[5:0]
Multiplex drive mode 1:4
5 to 0
[1]
DP[5:0]
Default value.
Remark: Data pointer values outside of the valid range will be ignored and no RAM
content will be transferred until a valid data pointer value is set.
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Filling of the display RAM is described in Section 7.9.
7.1.13 Command: load-data-pointer-PWM
The load-data-pointer-PWM command defines one of the 6 PWM addresses.
Table 26. Load-data-pointer-PWM - load data pointer command bit description
Bit
Symbol
Value
Description
7 to 3
-
0111 0
fixed value
2 to 0
[1]
[1]
PP[2:0]
000
to 101
3-bit binary value of 0 to 5
Default value.
Remark: Data pointer values outside of the valid range will be ignored and no PWM
content will be transferred until a valid data pointer value is set.
7.1.14 Command: write-RAM-data
This command will initiate the transfer of data to the display RAM. Data will be written
into the address defined by the load-data-pointer-LCD command. RAM filling is described
in Section 7.9.
[1]
Table 27. Write-RAM-data - write RAM data command bit description
Bit
Symbol
Value
Description
7 to 0
D[7:0]
0000 0000 to
[2]
1111 1111
writing data byte-wise to RAM
[1]
[2]
For this command to be effective bit RS[1:0] of the control byte has to be set logic 01, see Table 36page 46.
After Power-On Reset (POR), the RAM content is random and should be brought to a defined status by writing meaningful
content otherwise unexpected display content may appear.
7.1.15 Command: write-PWM-data
This command will initiate the transfer of data to the PWM registers. Data will be written
into the address defined by the load-data-pointer-PWM command. PWM register filling is
described in Section 7.10
[1]
Table 28. Write-PWM-data - write PWM data command bit description
Bit
Symbol
Value
7
-
0
6 to 0
[1]
[2]
Description
fixed value
[2]
P[6:0]
000 0000
111 1111
to
writing data byte-wise to PWM registers
For this command to be effective bit RS[1:0] of the control byte has to be set logic 10, see Table 36page 46.
Default value. After Power-On Reset (POR) the PWM content is set to 0.
7.2 Start-up and shut-down
7.2.1 Reset and Power-On Reset (POR)
After a reset and at power-on the PCF8536 resets to starting conditions as follows:
1. The display is disabled.
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2.
3.
4.
5.
6.
7.
8.
9.
All backplane outputs are set to VSS.
All segment outputs are set to VSS.
All GPO outputs are disabled.
1
Selected drive mode is: 1:8 with ⁄4 bias.
The data pointers are cleared (set logic 0).
PWM values are all reset to zero.
RAM data is not initialized. Its content can be considered to be random.
The internal oscillator is running; no clock signal is available on pin OSCCLK; pin
OSCCLK is in 3-state.
The reset state is as shown in Table 29.
Table 29. Reset state
Reset state of configurable bits shown in the command table format for clarity.
Associated command
Bits
7
6
5
4
3
2
1
0
PWM-inversion
PWMI = 0
mode-settings
-
-
-
-
BPS = 0
INV = 0
PD = 0
E=0
oscillator-control
-
-
-
-
-
EFR = 0
COE = 0
OSC = 0
GPO-output-config
-
-
-
-
GPM1[1:0] = 00
GPM0[1:0] = 00
-
-
-
-
GPM3[1:0] = 00
GPM2[1:0] = 00
-
-
-
-
GPM5[1:0] = 00
GPM4[1:0] = 00
set-MUX-mode
-
-
-
-
-
-
M[1:0] = 00
set-bias-mode
-
-
-
-
-
-
B[1:0] = 00
frame-frequency-LCD
-
-
-
FD[4:0] = 0 1110
frame-frequency-PWM
-
-
-
-
FP[3:0] = 0111
GPO-static-data
-
-
-
-
-
GPO2 = 0
GPO1 = 0
GPO0 = 0
-
-
-
-
-
GPO5 = 0
GPO4 = 0
GPO3 = 0
load-data-pointer-LCD
-
-
DP[5:0] = 00 0000
load-data-pointer-PWM
-
-
-
-
PP[2:0] = 000
-
The first command sent to the device after the power-on event must be the initialize
command (see Section 7.1.1).
After Power-On Reset (POR) and before enabling the display, the RAM content should
be brought to a defined state by writing meaningful content (e.g. a graphic) otherwise
unwanted display artifacts may appear on the display.
7.2.2 RESET pin function
The RESET pin of the PCF8536 will reset all the registers to their default state. The reset
state is given in Table 29. The RAM contents will remain unchanged. After the reset
signal is removed, the PCF8536 will behave in the same manner as after Power-On
Reset (POR). See Section 7.2.1 for details.
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7.2.3 Recommended start-up sequences
This chapter describes how to proceed with the initialization of the chip in different
application modes.
In general, the sequence should always be:
1.
2.
3.
4.
Power-on the device,
set the display and functional modes,
fill the display memory and then
turn on the display.
START
Power-on VDD
and VLCD
together
Toggle RESET
pin
(1)
Wait minimum
1 ms
Send
OTP-refresh
Set:
- mode settings: BPS and INV
- LCD/GPO output mode
- multiplex driver mode
- bias mode
- LCD frame frequency
If using GPO outputs, set
- GPO data
- PWM data
- PWM frame frequency
Send display
content
Enable
the display
STOP
013aaa452
1. Alternatively, it is possible to send the initialize command.
Figure 9. Recommended start-up sequence when using the internal oscillator
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START
Power-on VDD
and VLCD
together
Toggle RESET
pin
(1)
Wait minimum
1 ms
External clock
can be applied
now
Send
OTP-refresh
Set:
- Mode settings: BPS and INV
- Select external clock
- GPO output mode
- Multiplex driver mode
- Bias mode
- LCD frame frequency
If using GPO outputs, set
- GPO data
- PWM data
- PWM frame frequency
Send display
content
External clock
must be
applied by now
Enable
the display
STOP
013aaa453
1. Alternatively, it is possible to send the initialize command.
Figure 10. Recommended start-up sequence when using an external clock signal
7.3 Possible display configurations
The PCF8536 is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 11). It
can drive multiplexed LCD with 4, 6, or 8 backplanes and up to 44 segments.
The display configurations possible with the PCF8536 depend on the number of active
backplane outputs required. A selection of possible display configurations is given in
Table 30.
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dot matrix
7-segment with dot
14-segment with dot and accent
013aaa312
Figure 11. Example of displays suitable for PCF8536
Table 30. Selection of display configurations
Number of
Backplanes
Digits/Characters
Segments
[1]
Icons
7 segment
14 segment
[2]
Dot matrix/
Elements
No GPO or PWM outputs enabled
8
40
320
40
20
320
6
42
252
31
15
252
4
44
176
22
11
176
With 6 GPO or PWM outputs enabled
8
34
272
34
17
272
6
36
216
27
13
216
4
38
152
19
9
152
[1]
[2]
7 segment display has 8 elements including the decimal point.
14 segment display has 16 elements including decimal point and accent dot.
All of the display configurations in Table 30 can be implemented in the typical systems
shown in Figure 12 and Figure 13.
VDD
R=
tr
2Cb
HOST
PROCESSOR/
MICROCONTROLLER
SDA
SCL
40 to 44 segment
drives
VDD
PCF8536AT
A0
4 to 8 backplanes
VSS
LCD PANEL
(up to 320
elements)
013aaa450
VSS
2
Figure 12. Typical system configuration for the I C-bus
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PCF8536
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
VDD
SDI
HOST
PROCESSOR/
MICROCONTROLLER
40 to 44 segment
drives
VDD
SCL
PCF8536BT
CE
LCD PANEL
(up to 320
elements)
4 to 8 backplanes
VSS
013aaa451
VSS
Figure 13. Typical system configuration for the SPI-bus
2
The host microcontroller maintains the two line I C-bus or a three line SPI-bus
communication channel with the PCF8536. The appropriate biasing voltages for the
multiplexed LCD waveforms are generated internally. The only other connections
required to complete the system are the power supplies (VDD, VSS, VLCD) and the LCD
panel selected for the application.
The minimum recommended values for external capacitors on VDD and VLCD are 100
nF respectively. Decoupling of VLCD will help to reduce display artifacts. The decoupling
capacitors should be placed close to the IC with short connections to the respective
supply pin and VSS.
7.4 LCD voltage selector
The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with
the selected LCD drive configuration. The operation of the voltage selector is controlled
by the set-bias-mode command (see Table 19) and the set-MUX-mode command (see
Table 18).
Fractional LCD biasing voltages are obtained from an internal voltage divider. The
biasing configurations that apply to the preferred modes of operation, together with the
biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are
given in Table 31.
Discrimination is a term which is defined as the ratio of the on and off RMS voltage
across a segment. It can be thought of as a measurement of contrast.
Table 31. Preferred LCD drive modes: summary of characteristics
LCD multiplex
drive mode
1:4
[3]
1:4
Number of:
LCD bias
configuration
[1]
[2]
VLCD
Backplanes
Levels
4
3
1
0.433
0.661
1.527
2.309Voff(RMS)
4
1
0.333
0.577
1.732
3.0Voff(RMS)
0.331
0.545
1.646
3.024Voff(RMS)
4
⁄2
⁄3
1:4
[3]
4
5
1
1:6
[3]
6
3
1
0.456
0.612
1.341
2.191Voff(RMS)
4
1
0.333
0.509
1.527
3.0Voff(RMS)
5
1
0.306
0.467
1.527
3.266Voff(RMS)
3
1
0.467
0.586
1.254
2.138Voff(RMS)
4
1
0.333
0.471
1.414
3.0Voff(RMS)
1:6
6
1:6
6
1:8
[3]
1:8
[3]
PCF8536
Product data sheet
8
8
⁄4
⁄2
⁄3
⁄4
⁄2
⁄3
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Table 31. Preferred LCD drive modes: summary of characteristics...continued
LCD multiplex
drive mode
Number of:
Backplanes
Levels
1:8
8
5
[1]
[2]
[3]
LCD bias
configuration
1
⁄4
[1]
0.293
0.424
1.447
[2]
VLCD
3.411Voff(RMS)
Determined from Equation 6.
Determined from Equation 5.
In these examples, the discrimination factor and hence the contrast ratios are smaller. The advantage of these LCD drive modes is a reduction of the LCD
voltage VLCD.
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast.
Bias is calculated by
, where the values for a are
1
a = 1 for ⁄2 bias
1
a = 2 for ⁄3 bias
1
a = 3 for ⁄4 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 4
(4)
where VLCD is the resultant voltage at the LCD segment and where the values for n are
n = 4 for 1:4 multiplex drive
n = 6 for 1:6 multiplex drive
n = 8 for 1:8 multiplex drive
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 5:
(5)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 6:
(6)
It should be noted that VLCD is sometimes referred to as the LCD operating voltage.
7.4.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 14. For a good contrast performance, the following rules should be followed:
(7)
(8)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the
selection of a, n (see Equation 4 to Equation 6) and the VLCD voltage.
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes just named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
100 %
Relative Transmission
90 %
10 %
Vth(off)
OFF
SEGMENT
Vth(on)
GREY
SEGMENT
VRMS [V]
ON
SEGMENT
013aaa494
Figure 14. Electro-optical characteristic: relative transmission curve of the liquid
7.5 LCD drive mode waveforms
7.5.1 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies,
as shown in Figure 15. This drawing is also showing the case of line inversion (see
Section 7.1.4.2).
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
BP0
VLCD
2VLCD/3
VLCD/3
VSS
BP1
VLCD
2VLCD/3
VLCD/3
VSS
BP2
VLCD
2VLCD/3
VLCD/3
VSS
BP3
VLCD
2VLCD/3
VLCD/3
VSS
Sn
VLCD
2VLCD/3
VLCD/3
VSS
Sn+1
VLCD
2VLCD/3
VLCD/3
VSS
Sn+2
VLCD
2VLCD/3
VLCD/3
VSS
Sn+3
VLCD
2VLCD/3
VLCD/3
VSS
state 1
VLCD
2VLCD/3
VLCD/3
0V
-VLCD/3
-2VLCD/3
-VLCD
state 2
VLCD
2VLCD/3
VLCD/3
0V
-VLCD/3
-2VLCD/3
-VLCD
Tfr
LCD segments
state 1
state 2
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
Vstate1(t) = VSn(t) - VBP0(t). Vstate2(t) = VSn(t) - VBP1(t).
Von(RMS)(t) = 0.577VLCD. Voff(RMS)(t) = 0.333VLCD.
013aaa211
1
Figure 15. Waveforms for the 1:4 multiplex drive mode with ⁄3 bias and line inversion
7.5.2 1:6 Multiplex drive mode
When six backplanes are provided in the LCD, the 1:6 multiplex drive mode applies.
1
1
The PCF8536 allows use of ⁄3 bias or ⁄4 bias in this mode as shown in Figure 16
and Figure 17. These waveforms are drawn for the case of line inversion (see
Section 7.1.4.2).
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Tfr
BP0
VLCD
2VLCD / 3
VLCD / 3
VSS
BP1
VLCD
2VLCD / 3
VLCD / 3
VSS
BP2
VLCD
2VLCD / 3
VLCD / 3
VSS
BP3
VLCD
2VLCD / 3
VLCD / 3
VSS
BP4
VLCD
2VLCD / 3
VLCD / 3
VSS
BP5
VLCD
2VLCD / 3
VLCD / 3
VSS
Sn
VLCD
2VLCD / 3
VLCD / 3
VSS
Sn + 1
VLCD
2VLCD / 3
VLCD / 3
VSS
LCD segments
state 1
state 2
(a) Waveforms at driver
VLCD
2VLCD / 3
state 1
VLCD / 3
VSS
-VLCD / 3
-2VLCD / 3
-VLCD
VLCD
2VLCD / 3
state 2
VLCD / 3
VSS
-VLCD / 3
-2VLCD / 3
-VLCD
(b) Resultant waveforms at LCD segment
001aal399
Vstate1(t) = VSn(t) - VBP0(t). Vstate2(t) = VSn +1 (t) - VBP0(t). Von(RMS)(t) = 0.509VLCD. Voff(RMS)(t) = 0.333VLCD.
1
Figure 16. Waveforms for 1:6 multiplex drive mode with bias ⁄3 and line inversion
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Tfr
BP0
BP1
BP2
BP3
BP4
BP5
LCD segments
VLCD
3VLCD / 4
state 1
state 2
VLCD / 4
VSS
VLCD
3VLCD / 4
VLCD / 4
VSS
VLCD
3VLCD / 4
VLCD / 4
VSS
VLCD
3VLCD / 4
VLCD / 4
VSS
VLCD
3VLCD / 4
VLCD / 4
VSS
VLCD
3VLCD / 4
VLCD / 4
VSS
VLCD
Sn
VLCD / 2
VSS
VLCD
Sn + 1
VLCD / 2
VSS
VLCD
3VLCD / 4
state 1
(a) Waveforms at driver
VLCD / 4
VSS
-VLCD / 4
-3VLCD / 4
-VLCD
VLCD
3VLCD / 4
VLCD / 2
VLCD / 4
state 2
VSS
-VLCD / 4
-VLCD / 2
-3VLCD / 4
-VLCD
(b) Resultant waveforms at LCD segment
Vstate1(t) = VSn(t) - VBP0(t). Vstate2(t) = VSn + 1(t) - VBP0(t).
Von(RMS)(t) = 0.467VLCD. Voff(RMS)(t) = 0.306VLCD.
001aal400
1
Figure 17. Waveforms for 1:6 multiplex drive mode with bias ⁄4 and line inversion
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
7.5.3 1:8 Multiplex drive mode
BP0
BP1
BP2
BP3
BP4
BP5
BP6
BP7
VLCD
3VLCD / 4
Tfr
LCD segments
state 1
state 2
VLCD / 4
VSS
VLCD
3VLCD / 4
VLCD / 4
VSS
VLCD
3VLCD / 4
VLCD / 4
VSS
VLCD
3VLCD / 4
VLCD / 4
VSS
VLCD
3VLCD / 4
3LCD / 4
VSS
VLCD
3VLCD / 4
VLCD / 4
VSS
VLCD
3VLCD / 4
VLCD / 4
VSS
VLCD
3VLCD / 4
VLCD / 4
VSS
VLCD
Sn
VLCD / 2
VSS
VLCD
Sn + 1
VLCD / 2
VSS
VLCD
3VLCD / 4
state 1
(a) Waveforms at driver
VLCD / 4
VSS
-VLCD / 4
-3VLCD / 4
-VLCD
state 2
VLCD
3VLCD / 4
VLCD / 2
VLCD / 4
VSS
-VLCD / 4
-VLCD / 2
-3VLCD / 4
-VLCD
(b) Resultant waveforms at LCD segment
001aal398
Vstate1(t) = VSn(t) - VBP0(t). Vstate2(t) = VSn + 1(t) - VBP0(t). Von(RMS)(t) = 0.424VLCD. Voff(RMS)(t) = 0.293VLCD.
1
Figure 18. Waveforms for 1:8 multiplex drive mode with bias ⁄4 and line inversion
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PCF8536
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
BP0
BP1
BP2
BP3
BP4
BP5
BP6
BP7
VLCD
3/4 VLCD
Tfr
frame n
Tfr
frame n+1
LCD segments
state 1
state 2
1/4 VLCD
VSS
VLCD
3/4 VLCD
1/4 VLCD
VSS
VLCD
3/4 VLCD
1/4 VLCD
VSS
VLCD
3/4 VLCD
1/4 VLCD
VSS
VLCD
3/4 VLCD
1/4 VLCD
VSS
VLCD
3/4 VLCD
1/4 VLCD
VSS
VLCD
3/4 VLCD
1/4 VLCD
VSS
VLCD
3/4 VLCD
1/4 VLCD
VSS
VLCD
Sn
1/2 VLCD
VSS
VLCD
Sn + 1
1/2 VLCD
VSS
(a) Waveforms at driver
state 1
VLCD
3/4 VLCD
1/2 VLCD
1/4 VLCD
VSS
1/4 VLCD
1/2 VLCD
3/4 VLCD
VLCD
state 2
VLCD
3/4 VLCD
1/2 VLCD
1/4 VLCD
VSS
1/4 VLCD
1/2 VLCD
3/4 VLCD
VLCD
(b) Resultant waveforms at LCD segment
001aam359
Vstate1(t) = VSn(t) - VBP0(t). Vstate2(t) = VSn + 1(t) - VBP0(t). Von(RMS)(t) = 0.424VLCD. Voff(RMS)(t) = 0.293VLCD.
1
Figure 19. Waveforms for 1:8 multiplex drive mode with bias ⁄4 and frame inversion
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
7.6 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
7.7 Backplane outputs
The LCD drive section includes eight backplane outputs: BP0 to BP7. The backplane
output signals are generated based on the selected LCD multiplex drive mode.
• In 1:8 multiplex drive mode: BP0 to BP7 must be connected directly to the LCD.
• In 1:6 multiplex drive mode: BP0 to BP5 must be connected directly to the LCD.
• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
7.8 Segment outputs
The LCD drive section includes up to 44 segment outputs (S0 to S43) which must be
connected directly to the LCD. The segment output signals are generated based on the
multiplexed backplane signals and with data resident in the display register. When less
segment outputs are required, the unused segment outputs must be left open-circuit.
The number of available segments depends on the multiplex drive mode selected and
the number of GPOs used. The table shows consecutive GPOs selected, but this is just
for simplicity of explanation. Any combination of GPOs may be used.
Table 32. Backplane and active segment combinations
Basic examples. GPO pins may be configured in any combination. Other LCD segment and GPO combinations are possible.
Multiplex
Active BPs Active GPOs
drive mode
None
GP0 only
GP0 to GP1 GP0 to GP2 GP0 to GP3 GP0 to GP4 GP0 to GP5
1:8
BP0 to BP7 S0 to S39
S1 to S39
S2 to S39
S3 to S39
S4 to S39
S5 to S39
S6 to S39
1:6
BP0 to BP5 S0 to S41
S1 to S41
S2 to S41
S3 to S41
S4 to S41
S5 to S41
S6 to S41
1:4
BP0 to BP3 S0 to S43
S1 to S43
S2 to S43
S3 to S43
S4 to S43
S5 to S43
S6 to S43
7.9 Display RAM
The display RAM stores the LCD data. Depending on the multiplex drive mode, the
arrangement of the RAM is changed.
• multiplex drive 1:8: RAM is 40 × 8 bit
• multiplex drive 1:6: RAM is 42 × 6 bit
• multiplex drive 1:4: RAM is 44 × 4 bit
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Display RAM addresses (columns)/segment outputs (S)
Multiplex 1:8 drive mode
S0 S1 S2 S3 S4
S35 S36 S37 S38 S39
S0 S1 S2 S3 S4
S35 S36 S37 S38 S39 S40 S41
S0 S1 S2 S3 S4
S35 S36 S37 S38 S39 S40 S41 S42 S43
BP0
BP1
BP2
BP3
BP4
Display RAM bits (rows)/backplane outputs (BP)
BP5
BP6
BP7
Multiplex 1:6 drive mode
BP0
BP1
BP2
BP3
BP4
BP5
Multiplex 1:4 drive mode
BP0
BP1
BP2
BP3
013aaa454
The display RAM bitmap shows the direct relationship between the display RAM column and the
segment outputs and between the bits in a RAM row and the backplane outputs.
Figure 20. Display RAM bitmap
Logic 1 in the RAM bit map indicates the on-state (Von(RMS)) of the corresponding LCD
element; similarly, logic 0 indicates the off-state (Voff(RMS)). For more information on
Von(RMS) and Voff(RMS), see Section 7.4.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD elements,
• the RAM columns and the segment outputs,
• the RAM rows and the backplane outputs.
The display RAM bit map, Figure 20, shows row 0 to row 7 which correspond with the
backplane outputs BP0 to BP7, and column 0 to column 43 which correspond with the
segment outputs S0 to S43. In multiplexed LCD applications, the data of each row of the
display RAM is time-multiplexed with the corresponding backplane (row 0 with BP0, row
1 with BP1, and so on).
When display data is transmitted to the PCF8536, the display bytes received are stored
in the display RAM in accordance with the selected LCD multiplex drive mode. The data
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
is stored as it arrives and depending on the current multiplex drive mode, data is stored
in quadruples, sextuples or bytes.
7.9.1 Data pointer (LCD part)
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer-LCD command (see Table 25).
Following this command, an arriving data byte is stored starting at the display RAM
address indicated by the data pointer.
The data pointer is automatically incremented in accordance with the chosen LCD
multiplex drive mode configuration. That is, after each byte is stored, the contents of the
data pointer are incremented
• by two (1:4 multiplex drive mode),
• by one or two (1:6 multiplex drive mode),
• by one (1:8 multiplex drive mode).
Multiplex drive 1:6 is a special case and is described later on.
When the address counter reaches the end of the RAM, it stops incrementing after the
last byte is transmitted. Redundant bits of the last byte and subsequent bytes transmitted
are discarded until the pointer is reset. To send new RAM data, the data pointer must be
reset.
2
If an I C-bus or SPI-bus data access is terminated early then the state of the data pointer
is unknown. The data pointer must then be re-written prior to further RAM accesses.
7.9.2 RAM filling in 1:4 multiplex drive mode
In the 1:4 multiplex drive mode the RAM is organized in four rows and 44 columns. The
eight transmitted data bits are placed in two successive display RAM columns of four
rows (see Figure 21). In order to fill the whole four RAM rows, 22 bytes need to be sent
to the PCF8536. After the last byte sent, the data pointer must be reset before the next
RAM content update. Additional data bytes sent and any data bits that spill over the RAM
will be discarded.
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Columns
Display RAM addresses (columns)/segment outputs (S)
0 1 2
0 b7 b3
1 b6 b2
Rows
Display RAM
bits (rows)/
backplane outputs
(BP)
3
4
5
6
7
39 40 41 42 43
2 b5 b1
3 b4 b0
b7 b6 b5 b4 b3 b2 b1 b0
MSB
LSB
Transmitted data byte
013aaa455
Figure 21. Display RAM filling order in 1:4 multiplex drive mode
Depending on the start address of the data pointer, there is the possibility for a boundary
condition. This will occur when more data bits are sent than fit into the remaining RAM.
The additional data bits are discarded. See Figure 22.
Columns
Display RAM addresses (columns)/segment outputs (S)
Rows
Display RAM
bits (rows)/
backplane outputs
(BP)
0
1
0
1
2
3
4
5
6
7
39 40 41 42 43
b7
b6
2
b5
3
b4
Discarded
b7 b6 b5 b4 b3 b2 b1 b0
MSB
LSB
Transmitted data byte
013aaa456
Figure 22. Boundary condition in 1:4 multiplex drive mode
7.9.3 RAM filling in 1:6 multiplex drive mode
In the 1:6 multiplex drive mode the RAM is organized in six rows and 42 columns. The
eight transmitted data bits are placed in such a way, that a column is filled up (see
Figure 23).
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Columns
Display RAM addresses (columns)/segment outputs (S)
0
1
2
3
4
5
6
7
37 38 39 40 41
0 a7 a1 b3 c5
Rows
Display RAM
bits (rows)/
backplane outputs
(BP)
1 a6 a0 b2 c4
2 a5 b7 b1 c3
3 a4 b6 b0 c2
4 a3 b5 c7 c1
5 a2 b4 c6 c0
MSB
LSB
a7 a6 a5 a4 a3 a2 a1 a0
b7 b6 b5 b4 b3 b2 b1 b0
c7 c6 c5 c4 c3 c2 c1 c0
Transmitted data bytes
013aaa457
Figure 23. Display RAM filling order in 1:6 multiplex drive mode
The remaining bits are wrapped over into the next column. In order to fill the whole
RAM, 31 and a half bytes need to be sent to the PCF8536. After the last byte sent, the
data pointer must be reset before the next RAM content update. Additional data bytes
sent and any data bits that spill over the RAM will be discarded. Depending on the start
address of the data pointer, there are three possible boundary conditions. See Figure 24.
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Columns
Display RAM addresses (columns)/segment outputs (S)
0
1
2
3
4
5
6
7
37 38 39 40 41
0
1
b7
b6
2
b5
3
b4
4
b3
5
b2
Rows
Display RAM bits (rows)/backplane outputs (BP)
Discarded
b7 b6 b5 b4 b3 b2 b1 b0
MSB
0
1
2
3
4
5
6
7
LSB
Transmitted data byte
37 38 39 40 41
0
1
2
b7
3
b6
4
b5
5
b4
Discarded
b7 b6 b5 b4 b3 b2 b1 b0
MSB
0
1
2
3
4
5
6
7
LSB
Transmitted data byte
37 38 39 40 41
0
1
2
3
4
b7
b6
5
Discarded
b7 b6 b5 b4 b3 b2 b1 b0
MSB
LSB
Transmitted data byte
013aaa458
Figure 24. Boundary condition in 1:6 multiplex drive mode
7.9.4 RAM filling in 1:8 multiplex drive mode
In the 1:8 multiplex drive mode the RAM is organized in eight rows and 40 columns. The
eight transmitted data bits are placed into eight rows of one display RAM column (see
Figure 25). In order to fill the whole RAM, 40 bytes need to be sent to the PCF8536. After
the last byte sent, the data pointer must be reset before the next RAM content update.
Additional data bytes sent will be discarded.
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PCF8536
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Columns
Display RAM columns/segment outputs (S)
0
1
2
3
4
5
6
7
35 36 37 38 39
0 b7
1 b6
Rows
Display RAM rows/
backplane outputs
(BP)
2 b5
3 b4
4 b3
5 b2
6 b1
7 b0
b7 b6 b5 b4 b3 b2 b1 b0
MSB
Transmitted data byte
LSB
013aaa459
Figure 25. Display RAM filling order in 1:8 multiplex drive mode
There are no boundary conditions in 1:8 multiplex drive mode.
7.10 PWM registers and data pointer (PWM part)
There are six PWM generators which can be independently configured. The values used
to define the PWM output are stored here.
The addressing mechanism for the PWM register is realized using the PWM data pointer.
This allows the loading of an individual PWM data byte, or a series of data bytes, into any
location of the PWM registers. The sequence commences with the initialization of the
data pointer by the load-data-pointer-PWM command (see Table 26).
Following this command, an arriving data byte is stored starting at the PWM register
address indicated by the PWM data pointer. The data pointer is automatically
incremented. That is, after each byte is stored, the contents of the data pointer are
incremented. The data pointer will wrap around continuously as long as data is
transmitted.
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PCF8536
NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Columns
Display RAM columns/segment outputs (S)
0
1
2
3
4
5
6
7
35 36 37 38 39
0 b7
1 b6
Rows
2 b5
Display RAM rows/
backplane outputs
(BP)
3 b4
4 b3
5 b2
6 b1
7 b0
b7 b6 b5 b4 b3 b2 b1 b0
MSB
Transmitted data byte
LSB
013aaa460
Figure 26. PWM register filling
7.11 GPO output
The PCF8536 contains six independently configured GPO pins (GP0 to GP5). These
outputs, when enabled, will replace the function of the corresponding LCD segment
outputs.
Each GPO output can supply either a logic 1, a logic 0, or a PWM signal. The PWM
signal can be used to control the brightness of an LED.
The PWM generator has 128 possible levels allowing for an output with a variable duty
cycle between 0 % and 99.7 %. 100 % can only be achieved by a static 1 output.
The period of the PWM frame frequency described in Section 7.1.10 is divided into 128
time slots. The value in the PWM register determines for how many of these time slots
the PWM output is at logic 1.
Table 33. PWM generator
PWM register value
Percentage of ON
time (%)
Time slots at 1
Time slots at 0
0
0
0
128
1
0.78
1
127
2
1.56
2
126
:
:
:
:
126
98.4
126
2
127
99.2
127
1
PWM duty cycle may be calculated by:
(9)
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
PWMI
230 kHz
PWM generator
channel 0
PWM value 0
0
1
GP0
segment 0
LCD data
1
1
0
0
0
1
1
0
S0/GP0
GP0M[1:0]
230 kHz
PWM generator
channel 1
PWM value 1
0
1
GP1
segment 1
LCD data
1
1
0
0
0
1
1
0
S1/GP1
GP1M[1:0]
230 kHz
PWM generator
channel 2
PWM value 2
0
1
GP2
segment 2
LCD data
1
1
0
0
0
1
1
0
S2/GP2
GP2M[1:0]
230 kHz
PWM generator
channel 3
PWM value 3
0
1
GP3
segment 3
LCD data
1
1
0
0
0
1
1
0
S3/GP3
GP3M[1:0]
230 kHz
PWM generator
channel 4
0
1
PWM value 4
GP4
segment 4
LCD data
1
1
0
0
0
1
1
0
S4/GP4
GP4M[1:0]
230 kHz
PWM generator
channel 5
PWM value 5
0
1
GP5
segment 5
LCD data
1
1
0
0
0
1
1
0
GP5M[1:0]
S5/GP5
001aan567
There are six independently configured GPO outputs.
Figure 27. General-purpose output block diagram
An example of the PWM waveforms is given in Figure 28.
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
fPWM
PWM register 0 = 0
0.00 %
PWM register 1 = 1
0.78 %
PWM register 2 = 32
24.96 %
PWM register 3 = 64
49.92 %
PWM register 4 = 96
74.88 %
PWM register 5 = 127
99.20 %
1
t=
128 x fPWM
001aan569
Figure 28. PWM example waveforms for PWMI = 0
7.11.1 RGB color driving
There are six PWM channels that can be arranged as two RGB channels. There are no
explicit settings for this feature, only ways of utilizing the PWM channels.
Table 34 gives an example of how two RGB clusters can be configured.
Table 34. Combining PWM channels for RGB
RGB cluster
PWM channel
Component color
0
0
red
1
green
2
blue
3
red
4
green
5
blue
1
Figure 29 gives an example of how two RGB clusters can be connected.
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
LED supply voltage
R
G
B
R
G
cluster 0
B
cluster 1
S0/GP0
S1/GP1
S2/GP2
S3/GP3
S4/GP4
S5/GP5
001aan568
There are six independently configured GPO outputs.
Figure 29. Configuration for two RGB clusters
Table 35 gives some examples of programming values for the PWM channels in order to
achieve the given colors. By using three PWM channels for one RGB cluster it is possible
to generate two million colors.
Table 35. Example PWM values
PCF8536
Product data sheet
PWM channel
Component
color
PWM channel
value
Resultant color
0
red
127
yellow
1
green
127
2
blue
0
3
red
127
4
green
82
5
blue
0
0
red
0
1
green
127
2
blue
127
3
red
127
4
green
108
5
blue
0
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aqua
gold
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NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
7.11.2 PWM inversion mode
The PWM inversion mode can be enabled by setting the PWMI bit to logic 1 (see
Table 7on page 8). The PWMI mode will invert the PWM waveform.
By default, all PWM outputs will switch HIGH at the same time. If the PWM output is used
to drive external LEDs then this could cause a voltage dip on the power supply of the
LEDs. With the PWMI mode, it is possible to prevent multiple outputs switching HIGH at
the same time by ensuring that the PWM values are not identical.
In the example in Figure 30, none of the six PWM outputs switch HIGH together. All
PWM channels instead switch off together; however this will not cause any power supply
disturbances.
fPWM
PWM register 0 = 0
100.00 %
PWM register 1 = 1
99.20 %
PWM register 2 = 32
75.00 %
PWM register 3 = 64
50.00 %
PWM register 4 = 96
25.00 %
PWM register 5 = 127
0.78 %
t=
1
128 x fPWM
001aan570
Figure 30. PWM example waveforms for PWMI = 1
When PWM inversion mode is used, the PWM duty cycle can be calculated with:
(10)
8
Bus interfaces
8.1 Control byte and register selection
2
After initiating the communication over the bus and sending the target address (I C-bus,
see Section 8.2) or subaddress (SPI-bus, see Section 8.3), a control byte follows. The
purpose of this byte is to indicate both, the content for the following data bytes (RAM,
command, or PWM data) and to indicate that more control bytes will follow.
Typical sequences could be:
• target address/subaddress - control byte - command byte - command byte - command
byte - end
• target address/subaddress - control byte - RAM byte - RAM byte - RAM byte - end
• target address/subaddress - control byte - command byte - control byte - RAM byte end
In this way, it is possible to send a mixture of RAM, PWM and command data in one
access or alternatively, to send just one type of data in one access.
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Table 36. Control byte description
Bit
Symbol
7
CO
6 to 5
4 to 0
Value
Description
continue bit
0
last control byte
1
control bytes continue
register selection
RS[1:0]
-
00
command register
01
RAM data
10
PWM data
11
unused
-
MSB
7
CO
unused
6
5
4
RS[1:0]
3
2
1
LSB
0
not relevant
013aaa461
Figure 31. Control byte format
2
8.2 I C-bus interface
2
The I C-bus is for bidirectional, two-line communication between different ICs or
modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both
lines must be connected to a positive supply via a pull-up resistor when connected to the
output stages of a device. Data transfer may be initiated only when the bus is not busy.
8.2.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at
this time will be interpreted as a control signal (see Figure 32).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Figure 32. Bit transfer
8.2.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the
START condition (S).
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PCF8536
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP
condition (P).
The START and STOP conditions are shown in Figure 33.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
mbc 622
Figure 33. Definition of START and STOP conditions
8.2.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the controller and the devices which
are controlled by the controller are the targets. The system configuration is shown in
Figure 34.
CONTROLLER
TRANSMITTER/
RECEIVER
TARGET
RECEIVER
TARGET
TRANSMITTER/
RECEIVER
CONTROLLER
TRANSMITTER
CONTROLLER
TRANSMITTER/
RECEIVER
SDA
SCL
mga807
Figure 34. System configuration
8.2.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A target receiver which is addressed must generate an acknowledge after the reception
of each byte.
• Also a controller receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the target transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
• A controller receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the target. In this event, the
transmitter must leave the data line HIGH to enable the controller to generate a STOP
condition.
2
Acknowledgement on the I C-bus is shown in Figure 35.
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PCF8536
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL
from controller
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
2
Figure 35. Acknowledgement on the I C-bus
2
8.2.5 I C-bus controller
2
2
The PCF8536 acts as an I C-bus target receiver. It does not initiate I C-bus transfers or
2
2
transmit data to an I C-bus controller receiver. Device selection depends on the I C-bus
target address.
8.2.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
2
8.2.7 I C-bus target address
2
2
Device selection depends on the I C-bus target address. Two different I C-bus target
addresses can be used to address the PCF8536 (see Table 37).
2
Table 37. I C target address
target address
7
Bit
6
5
4
3
2
1
MSB
0
0
LSB
1
1
1
0
0
A0
R/W
The least significant bit of the target address byte is bit R/W. Bit 1 of the target address is
defined by connecting the input A0 to either VSS (logic 0) or VDD (logic 1). Therefore, two
2
instances of PCF8536 can be distinguished on the same I C-bus.
2
8.2.8 I C-bus protocol
2
The I C-bus protocol is shown in Figure 36. The sequence is initiated with a START
2
condition (S) from the I C-bus controller which is followed by one of the two PCF8536
target addresses available. All PCF8536 with the corresponding A0 level acknowledge in
parallel to the target address, but any PCF8536 with the alternative A0 level ignore the
2
whole I C-bus transfer.
After acknowledgement, a control byte follows (see Section 8.1).
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
The display bytes are stored in the display RAM at the address specified by the RAM
data pointer and PWM data is stored at the address pointed to by the PWM data pointer.
The acknowledgement after each byte is made only by the addressed PCF8536. After
2
the last data byte, the I C-bus controller issues a STOP condition (P). Alternatively a
2
START may be issued to RESTART an I C-bus access.
R/W = 0
target address
control byte
R R
S 0 1 1 1 0 0 A 0 AC S S
0
O1 0
RAM/command byte
M
L
S P
A S
B
B
EXAMPLES
a) transmit two byte of RAM data
S 0 1 1 1 0 0 A 0 A 0 0 1
0
A
RAM DATA
A
RAM DATA
A P
A
COMMAND
A 0 0 0
A
COMMAND
A P
A 0 0 1
A
RAM DATA
A
b) transmit two command bytes
S 0 1 1 1 0 0 A 0 A 1 0 0
0
c) transmit one command byte and two RAM date bytes
A
S 0 1 1 1 0 A
1 0 0 A 1 0 0
A
COMMAND
RAM DATA
A P
013aaa462
2
Figure 36. I C-bus protocol write mode
8.2.8.1 Status read out
2
Status read out for I C-bus operation only. This command will initiate the read out of a
fixed value plus the target address bit A0 from the PCF8536. This read out function will
2
2
allow the I C controller to confirm the existence of the device on the I C-bus.
Table 38. Status read out value
Bit
Symbol
Value
Description
7 to 1
-
0101 010
fixed value
0
A0
0
read back value is 0101 0100
1
read back value is 0101 0101
If a readout is made, the R/W bit must be logic 1 and then the next data byte following is
provided by the PCF8536 as shown in Figure 37.
target address
R/W = 1
readout byte
S 0 1 1 1 0 0 A 1 A 0 1 0 1 0 1 0 A A P
0
0
acknowledge (1)
acknowledge
from controller
013aaa463
1. From PCF8536.
2
Figure 37. I C-bus protocol read mode
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PCF8536
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
In the unlikely case that the chip has entered the internal test mode, detection of this
state is possible by using the modified status read out detailed in Table 39. The read out
value is modified to indicate that the chip has entered an internal test mode.
Table 39. Modified status read out value
Bit
Symbol
Value
Description
7 to 1
-
1111 000
fixed value
0
A0
0
read back value is 1111 0000
1
read back value is 1111 0001
EMC detection
The PCF8536 is ruggedized against EMC susceptibility; however it is not possible to
cover all cases. To detect if a severe EMC event has occurred, it is possible to check the
responsiveness of the device by reading its register.
8.3 SPI-bus interface
Data transfer to the device is made via a 3 line SPI-bus (see Table 40). There is no
output data line. The SPI-bus is initialized whenever the chip enable line pin CE is
inactive.
Table 40. Serial interface
Symbol
Function
Description
[1]
CE
chip enable input ; active LOW
when HIGH, the interface is reset
SCL
serial clock input
input may be higher than VDD
SDI
serial data input
input may be higher than VDD; input data is
sampled on the rising edge of SCL
[1]
The chip enable must not be wired permanently LOW.
8.3.1 Data transmission
The chip enable signal is used to identify the transmitted data. Each data transfer is a
byte with the Most Significant Bit (MSB) sent first.
The transmission is controlled by the active LOW chip enable signal CE. The first byte
transmitted is the subaddress byte.
data bus
SUBADDRESS
DATA
DATA
DATA
CE
013aaa464
Figure 38. Data transfer overview
The subaddress byte opens the communication with a read/write bit and a subaddress.
The subaddress is used to identify multiple devices on one SPI-BUS.
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Table 41. Subaddress byte definition
Bit
Symbol
7
R/W
6 to 5
SA
4 to 0
-
Value
Description
data read or write selection
0
write data
1
read data
subaddress; other codes will cause the device
to ignore data transfer
01
unused
After the subaddress byte, a control byte follows (see Section 8.1).
R/W = 0
subaddress
control byte
R R
C S S
O1 0
0 0 1
RAM/command byte
M
L
S
S
B
B
EXAMPLES
a) transmit two bytes of display RAM data
0 0 1
0 0 1
RAM DATA
RAM DATA
b) transmit two command bytes
0 0 1
1 0 0
COMMAND
0 0 0
COMMAND
c) transmit one command byte and two display RAM date bytes
0 0 1
1 0 0
COMMAND
0 0 1
RAM DATA
RAM DATA
013aaa465
Data transfers are terminated by de-asserting CE (set CE to logic 1).
Figure 39. SPI-bus write example
R/W
b7
1
SA
b6
0
b5
1
unused
b4
0
b3
0
b2
0
command byte
b1
0
b0
0
b7
0
b6
0
b5
0
b4
0
b3
0
b2
0
Bias sytem = 1/3 B[1:0] = 11
b1
0
b0
0
b7
0
b6
0
b5
0
b4
0
b3
0
b2
1
b1
1
b0
1
SCL
SDI
CE
013aaa466
1
In this example, the bias system is set to ⁄3. The transfer is terminated by CE returning to logic 1. After the last bit is
transmitted, the state of the SDI line is not important.
Figure 40. SPI-bus example
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
9
Internal circuitry
VDD
A0, RESET,
OSCCLK
VLCD, VDD,
SCL, SDA
VSS
VLCD
VSS
BP0 to BP7,
S0/GP0 to S5/GP5
S6 to S39
VSS
013aaa472
Figure 41. Device protection diagram for PCF8536AT
VDD
CE, RESET,
OSCCLK
SDI, SCL
VLCD,VDD
VSS
VLCD
VSS
BP0 to BP7,
S0/GP0 to S5/GP5
S6 to S39
VSS
013aaa473
Figure 42. Device protection diagram for PCF8536BT
10 Limiting values
CAUTION
Static voltages across the liquid crystal display can build up when the LCD
supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice
versa. This may cause unwanted display artifacts. To avoid such artifacts,
VLCD and VDD must be applied or removed together.
Table 42. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Min
Max
Unit
VDD
supply voltage
-0.5
+6.5
V
IDD
supply current
-50
+50
mA
VLCD
LCD supply voltage
-0.5
+10
V
IDD(LCD)
LCD supply current
-50
+50
mA
VI
input voltage
PCF8536
Product data sheet
Conditions
PCF8536AT
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PCF8536
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Table 42. Limiting values...continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Min
Max
Unit
-0.5
+6.5
V
-0.5
+6.5
V
-10
+10
mA
on pins S0/GP0 to S5/
GP5, S6 to S39, BP0
to BP7
-0.5
+10
V
on pin SDA
-0.5
+6.5
V
Conditions
on pins SDA,
OSCCLK, SCL,
A0, RESET
PCF8536BT
on pins CE,
OSCCLK, SCL,
SDI, RESET
II
input current
VO
output voltage
IO
output current
-10
+10
mA
ISS
ground supply current
-50
+50
mA
Ptot
total power dissipation
-
400
mW
P/out
power dissipation per output
-
100
mW
HBM
[1]
-
±3 500
V
CDM
[2]
-
±1 250
V
latch-up current
[3]
-
200
mA
Tstg
storage temperature
[4]
-65
+150
°C
Tamb
ambient temperature
-40
+85
°C
VESD
Ilu
[1]
[2]
[3]
[4]
electrostatic discharge voltage
operating device
Pass level; Human Body Model (HBM), according to [1].
Pass level; Charge Device Model (CDM), according to [2].
Pass level; latch-up testing according to [3] at maximum ambient temperature (Tamb(max)).
According to the NXP store and transport requirements (see [4]) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 %
to 75 %. For long-term storage products deviant conditions are described in that document.
11 Static characteristics
Table 43. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = -40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.8
-
5.5
V
Supplies
VDD
supply voltage
VLCD
LCD supply voltage
VLCD ≥ VDD
IDD(pd)
power-down mode supply current
IDD
supply current
PCF8536
Product data sheet
2.5
-
9.0
V
[1]
-
0.5
2
μA
external 9.6 kHz clock
[2]
-
10
25
μA
external 230 kHz
clock with PWM
[3]
-
20
40
μA
internal oscillator
[2]
-
30
60
μA
see Figure 43
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PCF8536
NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Table 43. Static characteristics...continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = -40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[3]
-
60
130
μA
[1][4]
-
7
15
μA
[5]
-
55
140
μA
VSS - 0.5
-
VDD + 0.5
V
internal oscillator with
PWM
IDD(LCD)
LCD supply current
power-down, see
Figure 44
display active, see
Figure 45
Logic
VI
input voltage
VIL
LOW-level input voltage
on pins OSCCLK,
A0 and RESET
-
-
0.3VDD
V
VIH
HIGH-level input voltage
on pins OSCCLK,
A0 and RESET
0.7VDD
-
-
V
VO
output voltage
-0.5
-
VDD + 0.5
V
VOH
HIGH-level output voltage
driving load of 50 μA
on pins OSCCLK and
GP0 to GP5
0.8VDD
-
-
V
VOL
LOW-level output voltage
driving load of 50 μA
on pins OSCCLK and
GP0 to GP5
-
-
0.2VDD
V
IOH
HIGH-level output current
output source current;
VOH = VDD - 0.4 V
VDD = 1.8 V
0.7
1.6
-
mA
VDD ≥ 3.3 V
1.5
4.0
-
mA
VDD = 1.8 V;
VLCD = 2.5 V
0.7
1.1
-
mA
VDD = 3.3 V;
VLCD ≥ 5.5 V
1.5
2.8
-
mA
VDD = 1.8 V
3
4
-
mA
VDD ≥ 3.3 V
5
10
-
mA
0.7
1.1
-
mA
on pin OSCCLK
on pins GP0 to
GP5
IOL
LOW-level output current
output sink current;
VOL = 0.4 V
on pin OSCCLK
on pins GP0 to
GP5
VDD = 1.8 V;
VLCD = 2.5 V
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Table 43. Static characteristics...continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = -40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
VDD = 3.3 V;
VLCD ≥ 5.5 V
IL
leakage current
2
Vi = VDD or VSS; on
pin OSCCLK and GP0
to GP5
Min
Typ
Max
Unit
1.5
2.4
-
mA
-1
-
+1
μA
[6]
I C-bus
On pins SCL and SDA
VI
input voltage
VSS - 0.5
-
5.5
V
VIL
LOW-level input voltage
-
-
0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
-
V
VO
output voltage
-0.5
-
+5.5
V
IL
leakage current
VI = VDD or VSS
-1
-
+1
μA
LOW-level output current
output sink current
VDD = 1.8 V
3
5.5
-
mA
VDD = 3.3 V
5
9
-
mA
on pin SCL
VSS - 0.5
-
5.5
V
on pins CE and SDI
VSS - 0.5
-
VDD + 0.5
V
On pin SDA
IOL
SPI-bus
VI
input voltage
On pins SCL, CE and SDI
VIL
LOW-level input voltage
-
-
0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
-
V
IL
leakage current
-1
-
+1
μA
VI = VDD or VSS
LCD outputs
ΔVO
RO
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
output voltage variation
output resistance
on pins BP0 to BP7
[7]
-
2.5
+10
mV
on pins S0 to S43
[8]
-
2.5
+10
mV
VLCD = 7 V;
on pins BP0 to BP7
[9]
-
0.9
5.0
kΩ
VLCD = 7 V;
on pins S0 to S43
[9]
-
1.5
6.0
kΩ
2
Power-down mode is enabled; I C-bus or SPI-bus inactive.
1
1:8 multiplex drive mode; ⁄4 bias; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; default display
2
prescale factor; I C-bus or SPI-bus inactive.
1
1:8 multiplex drive mode; ⁄4 bias; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; default display
2
prescale factor; I C-bus or SPI-bus inactive; six PWM channels active at 50 % duty.
Strongly linked to VLCD voltage. See Figure 44.
1
1:8 multiplex drive mode; ⁄4 bias; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; default display prescale factor.
2
The I C-bus interface of PCF8536 is 5 V tolerant.
Variation between any two backplanes on a given voltage level; static measured.
Variation between any two segments on a given voltage level; static measured.
Outputs measured one at a time.
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NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
013aaa503
60
IDD
(µA)
40
20
0
-45
-10
25
60
Tamb (ºC)
95
1
1:8 multiplex drive mode; ⁄4 bias; internal oscillator; display enabled; LCD outputs are open
2
circuit; RAM is all written with logic 1; inputs at VSS or VDD; default display prescale factor; I Cbus or SPI-bus inactive. Typical is defined at VDD = 3.3 V, 25 °C.
Figure 43. Typical IDD with respect to temperature
013aaa505
15
IDD(LCD)
(µA)
VLCD = 9.0 V
10
VLCD = 5.5 V
5
0
-45
-10
25
60
Tamb (ºC)
95
2
Power-down mode is enabled; I C-bus or SPI-bus inactive. Typical is defined at 25 °C.
Figure 44. Typical IDD(LCD) in power-down mode with respect to temperature
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NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
013aaa507
120
IDD(LCD)
(µA)
VLCD = 9.0 V
80
40
VLCD = 5.5 V
0
-45
-10
25
60
Tamb (ºC)
95
1
1:8 multiplex drive mode; ⁄4 bias; display enabled; LCD outputs are open circuit; RAM is all
written with logic 1; default display prescale factor. Typical is defined at 25 °C.
Figure 45. Typical IDD(LCD) when display is active with respect to temperature
12 Dynamic characteristics
Table 44. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = -40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
[1]
Min
Typ
Max
Unit
7 800
9 600
11 040
Hz
fclk
clock frequency
output on pin
OSCCLK; VDD = 3.3 V
fclk(ext)
external clock frequency
EFR = 0
-
-
250 000
Hz
t(RESET_N)
RESET_N pulse width
LOW time
400
-
-
ns
External clock source used on pin OSCCLK
tclk(H)
clock HIGH time
33
-
-
μs
tclk(L)
clock LOW time
33
-
-
μs
[1]
Frequency present on OSCCLK with default display frequency division factor.
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NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
013aaa501
15
fclk
(kHz)
(3)
(2)
10
(1)
5
0
1
3
5
7
VDD (V)
1. -40 °C.
2. 25 °C.
3. 85 °C.
Figure 46. Typical clock frequency with respect to VDD and temperature
tclk(H)
1/fclk(ext)
tclk(L)
0.7VDD
OSCCLK
0.3VDD
013aaa474
External clock source used on pin OSCCLK.
Figure 47. Driver timing waveforms
tRESET(L)
RESET
0.3VDD
013aaa475
Figure 48. RESET timing
2
Table 45. Timing characteristics: I C-bus
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = -40 °C to +85 °C; unless otherwise specified. All timing values
are valid within the operating supply voltage and temperature range and referenced to VIL and VIH with an input voltage
swing of VSS to VDD. Timing waveforms see Figure 49.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
-
400
kHz
Pin SCL
fSCL
[1]
SCL clock frequency
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
2
Table 45. Timing characteristics: I C-bus...continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = -40 °C to +85 °C; unless otherwise specified. All timing values
are valid within the operating supply voltage and temperature range and referenced to VIL and VIH with an input voltage
swing of VSS to VDD. Timing waveforms see Figure 49.
Symbol
Parameter
tLOW
tHIGH
Conditions
Min
Typ
Max
Unit
LOW period of the SCL clock
1.3
-
-
μs
HIGH period of the SCL clock
0.6
-
-
μs
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
Pin SDA
Pins SCL and SDA
tBUF
bus free time between a STOP
and START condition
1.3
-
-
μs
tSU;STO
set-up time for STOP condition
0.6
-
-
μs
tHD;STA
hold time (repeated) START
condition
0.6
-
-
μs
tSU;STA
set-up time for a repeated START
condition
0.6
-
-
μs
tr
rise time of both SDA and SCL
signals
fSCL = 400 kHz
-
-
0.3
μs
fSCL = 100 kHz
-
-
1.0
μs
-
-
0.3
μs
tf
fall time of both SDA and SCL
signals
tVD;ACK
data valid acknowledge time
[2]
0.6
-
-
μs
tVD;DAT
data valid time
[3]
0.6
-
-
μs
Cb
capacitive load for each bus line
-
-
400
pF
-
-
50
ns
tSP
[1]
[2]
[3]
[4]
[4]
pulse width of spikes that must
be suppressed by the input filter
The minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either the SDA or SCL is held LOW for a
minimum of 25 ms. The bus time-out feature must be disabled for DC operation.
tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW.
tVD;DAT = minimum time for valid SDA output following SCL LOW.
Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
START
condition
(S)
protocol
bit 7
MSB
(A7)
tSU;STA
tLOW
bit 6
(A6)
tHIGH
1/f
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
SCL
SCL
tBUF
tr
tf
SDA
tHD;STA
tSU;DAT
tVD;DAT
tHD;DAT
tVD;ACK
tSU;STO
013aaa417
2
Figure 49. I C-bus timing waveforms
Table 46. Timing characteristics: SPI-bus
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C. All timing values are valid within the operating supply voltage
and temperature range and referenced to VIL and VIH with an input voltage swing of VSS to VDD. Timing waveforms see
Figure 50.
Symbol
Parameter
Conditions
VDD < 2.7 V
VDD ≥ 2.7 V
Min
Max
Min
Max
Unit
fclk(SCL)
SCL clock frequency
-
2
-
5
MHz
tSCL
SCL time
500
-
200
-
ns
tclk(H)
clock HIGH time
200
-
80
-
ns
tclk(L)
clock LOW time
200
-
80
-
ns
tr
rise time
for SCL signal
-
100
-
100
ns
tf
fall time
for SCL signal
-
100
-
100
ns
tsu(CE_N)
CE_N set-up time
150
-
80
-
ns
th(CE_N)
CE_N hold time
0
-
0
-
ns
trec(CE_N)
CE_N recovery time
100
-
100
-
ns
tsu
set-up time
set-up time for
SDI data
10
-
5
-
ns
th
hold time
hold time for SDI
data
25
-
10
-
ns
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
CE
tsu(CE_N)
tr
tSCL
tclk(H)
tf
th(CE_N)
trec(CE_N)
70%
SCL
30%
tsu
tclk(L)
th
SDI
b7
b6
b0
013aaa476
Figure 50. SPI-bus timing
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
13 Package outline
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
HE
y
v M A
Z
56
29
Q
A2
(A 3 )
A1
pin 1 index
A
θ
Lp
L
1
28
w M
bp
e
detail X
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
0.5
8.3
7.9
1
0.8
0.4
0.50
0.35
0.25
0.08
0.1
0.5
0.1
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT364-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Figure 51. Package outline SOT364-1 (TSSOP56)
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14 Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
15 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 52) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 47 and Table 48
Table 47. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 48. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 52.
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 52. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
16 Footprint information for reflow soldering
Footprint information for reflow soldering of TSSOP56 package
SOT364-1
Hx
Gx
P2
(0.125)
Hy
Gy
(0.125)
By
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ay
By
C
D1
0.500
0.560
8.900
6.100
1.400
0.280
D2
Gx
0.400 14.270
Gy
Hx
Hy
7.000 16.600 9.150
sot364-1_fr
Figure 53. Footprint information for reflow soldering of SOT364-1 (TSSOP56) package
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17 Appendix: possible PWM and LCD frame frequency combinations to
avoid flicker
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[1]
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Table 49. LCD and PWM frame frequency combinations to avoid flicker
Experiments have shown that likely no flicker occurs when PWM frame frequency and LCD frame frequency are between 40 Hz and 50 Hz apart and no flicker occurs if they are
more than 50 Hz apart.
frame frequencies
PWM (fPWM)
LCD (ffr(LCD))
59.9
69.1
81.7
89.8
99.8
112.3
119.8
128.3
138.2
149.7
163.4
179.7
199.7
224.6
256.7
299.5
59.9
0.0
9.2
21.8
29.9
20.0
7.5
0.0
8.6
18.4
29.9
16.3
0.0
20.0
15.0
17.1
0.0
70.5
10.6
1.4
11.2
19.4
29.4
28.6
21.1
12.6
2.7
8.8
22.4
31.7
11.7
13.2
25.2
17.6
79.9
20.0
10.8
1.8
10.0
20.0
32.4
39.9
31.4
21.5
10.0
3.6
20.0
39.9
15.0
17.1
20.0
90.4
29.4
21.3
8.7
0.6
9.4
21.9
29.4
37.9
42.6
31.1
17.5
1.1
18.8
43.8
14.5
28.3
99.8
20.0
30.7
18.2
10.0
0.0
12.5
20.0
28.5
38.4
49.9
36.3
20.0
0.0
25.0
42.8
0.0
108.9
10.9
29.3
27.2
19.1
9.1
3.4
10.9
19.4
29.3
40.8
54.5
38.1
18.2
6.8
38.9
27.2
119.8
0.0
18.4
38.1
29.9
20.0
7.5
0.0
8.6
18.4
29.9
43.6
59.9
39.9
15.0
17.1
59.9
129.5
9.7
8.7
33.8
39.7
29.7
17.2
9.7
1.2
8.7
20.2
33.8
50.2
59.4
34.4
2.3
40.5
140.9
21.1
2.7
22.4
38.8
41.1
28.6
21.1
12.6
2.7
8.8
22.4
38.8
58.7
57.3
25.2
17.6
149.7
29.9
11.5
13.6
29.9
49.9
37.4
29.9
21.4
11.5
0.0
13.6
29.9
49.9
74.9
42.8
0.0
159.7
20.0
21.5
3.6
20.0
39.9
47.4
39.9
31.4
21.5
10.0
3.6
20.0
39.9
64.9
62.7
20.0
171.1
8.6
32.9
7.8
8.6
28.5
53.5
51.3
42.8
32.9
21.4
7.8
8.6
28.5
53.5
85.6
42.8
177.5
2.2
29.9
14.1
2.2
22.2
47.1
57.7
49.1
39.2
27.7
14.1
2.2
22.2
47.1
79.2
55.5
184.3
4.6
23.0
20.9
4.6
15.4
40.3
55.3
55.9
46.1
34.6
20.9
4.6
15.4
40.3
72.4
69.1
191.7
12.0
15.7
28.3
12.0
8.0
32.9
47.9
63.3
53.4
41.9
28.3
12.0
8.0
32.9
65.0
83.9
199.7
20.0
7.7
36.3
20.0
0.0
25.0
39.9
57.0
61.4
49.9
36.3
20.0
0.0
25.0
57.0
99.8
208.3
28.6
1.0
36.7
28.6
8.7
16.3
31.3
48.4
68.1
58.6
45.0
28.6
8.7
16.3
48.4
91.1
217.8
21.8
10.5
27.2
38.1
18.2
6.8
21.8
38.9
58.6
68.1
54.5
38.1
18.2
6.8
38.9
81.7
228.2
11.4
20.8
16.9
41.4
28.5
3.6
11.4
28.5
48.3
71.3
64.8
48.5
28.5
3.6
28.5
71.3
239.6
0.0
32.3
5.4
29.9
39.9
15.0
0.0
17.1
36.9
59.9
76.2
59.9
39.9
15.0
17.1
59.9
252.2
12.6
24.2
7.2
17.3
47.3
27.6
12.6
4.5
24.2
47.3
74.5
72.5
52.5
27.6
4.5
47.3
266.2
26.6
10.2
21.2
3.3
33.3
41.6
26.6
9.5
10.2
33.3
60.5
86.5
66.6
41.6
9.5
33.3
281.9
17.6
5.4
36.8
12.3
17.6
55.1
42.3
25.2
5.4
17.6
44.8
77.5
82.2
57.3
25.2
17.6
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PCF8536
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[1]
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Table 49. LCD and PWM frame frequency combinations to avoid flicker ...continued
Experiments have shown that likely no flicker occurs when PWM frame frequency and LCD frame frequency are between 40 Hz and 50 Hz apart and no flicker occurs if they are
more than 50 Hz apart.
frame frequencies
PWM (fPWM)
LCD (ffr(LCD))
59.9
69.1
81.7
89.8
99.8
112.3
119.8
128.3
138.2
149.7
163.4
179.7
199.7
224.6
256.7
299.5
299.5
0.0
23.0
27.2
29.9
0.0
37.4
59.9
42.8
23.0
0.0
27.2
59.9
99.8
74.9
42.8
0.0
[1]
The table shows the smallest distance (Δf) from one frequency to the next or multiples of the next. Δf = MIN(f1 - n × f2); the values for n are 1 to 6; f1 and f2 can be either fPWM or ffr(LCD); both relationships have to be considered.
A PWM frame frequency (fPWM) of less than 60 Hz may show flicker purely from the LCD.
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PCF8536
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
18 Abbreviations
Table 50. Abbreviations
Acronym
Description
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DC
Direct Current
EMC
ElectroMagnetic Compatibility
EPROM
Erasable Programmable Read-Only Memory
ESD
ElectroStatic Discharge
HBM
Human Body Model
2
I C
Inter-Integrated Circuit bus
IC
Integrated Circuit
LCD
Liquid Crystal Display
LED
Light-Emitting Diode
LSB
Least Significant Bit
MSB
Most Significant Bit
MSL
Moisture Sensitivity Level
MUX
Multiplexer
OTP
One Time Programmable
PCB
Printed-Circuit Board
POR
Power-On Reset
PWM
Pulse-Width Modulation
RC
Resistance-Capacitance
RAM
Random Access Memory
RGB
Red Green Blue
RMS
Root Mean Square
SCL
Serial CLock line
SDA
Serial DAta line
SPI
Serial Peripheral Interface
19 References
[1]
[2]
[3]
[4]
PCF8536
Product data sheet
JESD22-A114 Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model
(HBM)
JESD22-C101 Field-Induced Charged-Device Model Test Method for ElectrostaticDischarge-Withstand Thresholds of Microelectronic Components
JESD78 IC Latch-Up Test
NX3-00092 NXP store and transport requirements
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
20 Revision history
Table 51. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCF8536 v.3
20211102
Product data sheet
PCN202102010F01
PCF8536 v.2
Modifications:
• Updated Ordering information and added Ordering options.
• Removed Marking section (formerly Section 5).
• The terms master and slave changed to controller and target to comply with NXP inclusive
language policy.
PCF8536 v.2
20120221
Modifications:
• Fixed typos
PCF8536 v.1
20111006
PCF8536
Product data sheet
Product data sheet
-
PCF8536 v.1
Product data sheet
-
-
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
21 Legal information
21.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
21.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
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legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
PCF8536
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
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No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
PCF8536
Product data sheet
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
21.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
2
I C-bus — logo is a trademark of NXP B.V.
NXP — wordmark and logo are trademarks of NXP B.V.
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PCF8536
NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.
Tab. 11.
Tab. 12.
Tab. 13.
Tab. 14.
Tab. 15.
Tab. 16.
Tab. 17.
Tab. 18.
Tab. 19.
Tab. 20.
Tab. 21.
Tab. 22.
Tab. 23.
Ordering information ..........................................2
Ordering options ................................................2
Pin description of PCF8536AT and
PCF8536BT .......................................................6
Commands of PCF8536 ....................................7
Initialize - initialize command bit description ......8
OTP-refresh - OTP-refresh command bit
description ......................................................... 8
PWM-inversion - PWM inversion command
bit description .................................................... 8
Mode-settings - mode settings command
bit description .................................................... 8
Effect of the power-down bit (PD) ................... 11
Oscillator-control - oscillator control
command bit description ................................. 12
Valid combinations of bits OSC, EFR, and
COE .................................................................13
Typical use of bits OSC, EFR, and COE ......... 13
Internal oscillator on/off table .......................... 14
OSCCLK table .................................................14
LCD frame frequencies ................................... 15
GPO-output-config - output mode config
command for S5/GP5 to S0/GP0 .................... 15
GPMO mode definition ....................................16
Set-MUX-mode - set multiplex drive mode
command bit description ................................. 16
Set-bias-mode - set bias mode command
bit description .................................................. 16
Frame-frequency-LCD - frame frequency
and output clock frequency command bit
description ....................................................... 17
Frame frequency prescaler values for 230
kHz clock operation .........................................17
Frame-frequency-PWM - PWM frame
frequency command bit description .................18
PWM frame frequency prescaler values for
230 kHz clock operation ..................................18
Tab. 24.
Tab. 25.
Tab. 26.
Tab. 27.
Tab. 28.
Tab. 29.
Tab. 30.
Tab. 31.
Tab. 32.
Tab. 33.
Tab. 34.
Tab. 35.
Tab. 36.
Tab. 37.
Tab. 38.
Tab. 39.
Tab. 40.
Tab. 41.
Tab. 42.
Tab. 43.
Tab. 44.
Tab. 45.
Tab. 46.
Tab. 47.
Tab. 48.
Tab. 49.
Tab. 50.
Tab. 51.
GPO-static-data - write GPO data for GP0
to GP5 command bit description ..................... 20
Load-data-pointer-LCD - load data pointer
command bit description ................................. 20
Load-data-pointer-PWM - load data pointer
command bit description ................................. 21
Write-RAM-data - write RAM data
command bit description ................................. 21
Write-PWM-data - write PWM data
command bit description ................................. 21
Reset state ...................................................... 22
Selection of display configurations .................. 25
Preferred LCD drive modes: summary of
characteristics ..................................................26
Backplane and active segment
combinations ................................................... 34
PWM generator ............................................... 41
Combining PWM channels for RGB ................ 43
Example PWM values ..................................... 44
Control byte description .................................. 46
I2C target address .......................................... 48
Status read out value ......................................49
Modified status read out value ........................ 50
Serial interface ................................................ 50
Subaddress byte definition .............................. 51
Limiting values ................................................ 52
Static characteristics ....................................... 53
Dynamic characteristics .................................. 57
Timing characteristics: I2C-bus ....................... 58
Timing characteristics: SPI-bus ....................... 60
SnPb eutectic process (from J-STD-020D) ..... 64
Lead-free process (from J-STD-020D) ............ 64
LCD and PWM frame frequency
combinations to avoid flicker ........................... 68
Abbreviations ...................................................70
Revision history ...............................................71
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Block diagram of PCF8536AT ...........................3
Block diagram of PCF8536BT ...........................4
Pin configuration for TSSOP56
(PCF8536AT) .....................................................5
Pin configuration for TSSOP56
(PCF8536BT) .................................................... 5
Effect of backplane swapping ......................... 10
Recommended power-down sequence ........... 11
Oscillator selection .......................................... 13
Flicker avoidance for LED backlighting ........... 19
Recommended start-up sequence when
using the internal oscillator ............................. 23
Recommended start-up sequence when
using an external clock signal ......................... 24
Example of displays suitable for PCF8536 ...... 25
PCF8536
Product data sheet
Fig. 12.
Fig. 13.
Fig. 14.
Fig. 15.
Fig. 16.
Fig. 17.
Fig. 18.
Typical system configuration for the I2Cbus ...................................................................25
Typical system configuration for the SPIbus ...................................................................26
Electro-optical characteristic: relative
transmission curve of the liquid .......................28
Waveforms for the 1:4 multiplex drive mode
with 1⁄3 bias and line inversion ....................... 29
Waveforms for 1:6 multiplex drive mode
with bias 1⁄3 and line inversion ....................... 30
Waveforms for 1:6 multiplex drive mode
with bias 1⁄4 and line inversion ....................... 31
Waveforms for 1:8 multiplex drive mode
with bias 1⁄4 and line inversion ....................... 32
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PCF8536
NXP Semiconductors
Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.
Fig. 24.
Fig. 25.
Fig. 26.
Fig. 27.
Fig. 28.
Fig. 29.
Fig. 30.
Fig. 31.
Fig. 32.
Fig. 33.
Fig. 34.
Fig. 35.
Waveforms for 1:8 multiplex drive mode
with bias 1⁄4 and frame inversion .................... 33
Display RAM bitmap ....................................... 35
Display RAM filling order in 1:4 multiplex
drive mode ...................................................... 37
Boundary condition in 1:4 multiplex drive
mode ............................................................... 37
Display RAM filling order in 1:6 multiplex
drive mode ...................................................... 38
Boundary condition in 1:6 multiplex drive
mode ............................................................... 39
Display RAM filling order in 1:8 multiplex
drive mode ...................................................... 40
PWM register filling ......................................... 41
General-purpose output block diagram ........... 42
PWM example waveforms for PWMI = 0 .........43
Configuration for two RGB clusters ................. 44
PWM example waveforms for PWMI = 1 .........45
Control byte format ......................................... 46
Bit transfer .......................................................46
Definition of START and STOP conditions ...... 47
System configuration .......................................47
Acknowledgement on the I2C-bus .................. 48
PCF8536
Product data sheet
Fig. 36.
Fig. 37.
Fig. 38.
Fig. 39.
Fig. 40.
Fig. 41.
Fig. 42.
Fig. 43.
Fig. 44.
Fig. 45.
Fig. 46.
Fig. 47.
Fig. 48.
Fig. 49.
Fig. 50.
Fig. 51.
Fig. 52.
Fig. 53.
I2C-bus protocol write mode ........................... 49
I2C-bus protocol read mode ............................49
Data transfer overview .................................... 50
SPI-bus write example .................................... 51
SPI-bus example ............................................. 51
Device protection diagram for PCF8536AT ..... 52
Device protection diagram for PCF8536BT ..... 52
Typical IDD with respect to temperature ..........56
Typical IDD(LCD) in power-down mode
with respect to temperature .............................56
Typical IDD(LCD) when display is active
with respect to temperature .............................57
Typical clock frequency with respect to
VDD and temperature ..................................... 58
Driver timing waveforms ..................................58
RESET timing ..................................................58
I2C-bus timing waveforms ...............................60
SPI-bus timing .................................................61
Package outline SOT364-1 (TSSOP56) ..........62
Temperature profiles for large and small
components ..................................................... 65
Footprint information for reflow soldering of
SOT364-1 (TSSOP56) package ......................66
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PCF8536
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Universal LCD driver for low multiplex rates including a 6 channel PWM generator
Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.4.1
7.1.4.2
7.1.4.3
7.1.4.4
7.1.5
7.1.5.1
7.1.5.2
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10
7.1.11
7.1.12
7.1.13
7.1.14
7.1.15
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.4.1
7.5
7.5.1
7.5.2
7.5.3
7.6
7.7
7.8
7.9
7.9.1
7.9.2
7.9.3
7.9.4
General description ............................................ 1
Features and benefits .........................................1
Applications .........................................................2
Ordering information .......................................... 2
Ordering options ................................................ 2
Block diagram ..................................................... 3
Pinning information ............................................ 4
Pinning ............................................................... 4
Pin description ................................................... 6
Functional description ........................................7
Commands of PCF8536 .................................... 7
Command: initialize ........................................... 8
Command: OTP-refresh .................................... 8
Command: PWM-inversion ................................ 8
Command: mode-settings ..................................8
Backplane swapping ..........................................9
Line inversion (driving scheme A) and
frame inversion (driving scheme B) ................. 10
Power-down mode ...........................................10
Display enable ................................................. 12
Command: oscillator-control ............................ 12
Oscillator .......................................................... 13
Timing and frame frequency ............................ 15
Command: GPO-output-config ........................ 15
Command: set-MUX-mode .............................. 16
Command: set-bias-mode ............................... 16
Command: frame-frequency-LCD ....................16
Command: frame-frequency-PWM .................. 18
Command: GPO-static-data .............................19
Command: load-data-pointer-LCD ...................20
Command: load-data-pointer-PWM ................. 21
Command: write-RAM-data ............................. 21
Command: write-PWM-data .............................21
Start-up and shut-down ................................... 21
Reset and Power-On Reset (POR) ..................21
RESET pin function ......................................... 22
Recommended start-up sequences ................. 23
Possible display configurations ........................24
LCD voltage selector ....................................... 26
Electro-optical performance ............................. 27
LCD drive mode waveforms ............................ 28
1:4 Multiplex drive mode ................................. 28
1:6 Multiplex drive mode ................................. 29
1:8 Multiplex drive mode ................................. 32
Display register ................................................ 34
Backplane outputs ........................................... 34
Segment outputs ............................................. 34
Display RAM ....................................................34
Data pointer (LCD part) ................................... 36
RAM filling in 1:4 multiplex drive mode ............36
RAM filling in 1:6 multiplex drive mode ............37
RAM filling in 1:8 multiplex drive mode ............39
7.10
PWM registers and data pointer (PWM
part) ..................................................................40
7.11
GPO output ......................................................41
7.11.1
RGB color driving ............................................ 43
7.11.2
PWM inversion mode ...................................... 45
8
Bus interfaces ................................................... 45
8.1
Control byte and register selection .................. 45
8.2
I2C-bus interface ............................................. 46
8.2.1
Bit transfer ....................................................... 46
8.2.2
START and STOP conditions .......................... 46
8.2.3
System configuration ....................................... 47
8.2.4
Acknowledge ....................................................47
8.2.5
I2C-bus controller ............................................ 48
8.2.6
Input filters ....................................................... 48
8.2.7
I2C-bus target address .................................... 48
8.2.8
I2C-bus protocol .............................................. 48
8.2.8.1
Status read out ................................................ 49
8.3
SPI-bus interface ............................................. 50
8.3.1
Data transmission ............................................ 50
9
Internal circuitry ................................................ 52
10
Limiting values .................................................. 52
11
Static characteristics ........................................ 53
12
Dynamic characteristics ...................................57
13
Package outline .................................................62
14
Handling information ........................................ 63
15
Soldering of SMD packages .............................63
15.1
Introduction to soldering .................................. 63
15.2
Wave and reflow soldering .............................. 63
15.3
Wave soldering ................................................ 63
15.4
Reflow soldering .............................................. 64
16
Footprint information for reflow soldering ..... 66
17
Appendix: possible PWM and LCD frame
frequency combinations to avoid flicker .........67
18
Abbreviations .................................................... 70
19
References ......................................................... 70
20
Revision history ................................................ 71
21
Legal information .............................................. 72
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 November 2021
Document identifier: PCF8536
