PCF8551BTT/AJ

PCF8551 Universal 36 × 4 LCD segment driver Rev. 3.1 — 3 May 2021 1 Product data sheet General description PCF8551 is an ultra low-power LCD segment driver with 4 backplane- and 36 segment2 driver outputs, with either an I C- (PCF8551A) or an SPI-bus (PCF8551B) interface. It comprises an internal oscillator, bias generation, instruction decoding, and display controller. For a selection of NXP LCD segment drivers, see Table 23. 2 Features and benefits • • • • • • • • • • • • • 3 Single chip LCD controller and driver with temperature range of -40 °C to 85 °C Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing 1 1 Selectable display bias configuration: static, ⁄2, or ⁄3 Internal LCD bias generation with buffers 36 segment drives: – Up to 18 7-segment numeric characters – Up to 9 14-segment alphanumeric characters – Any graphics of up to 144 segments/elements Auto-incrementing display data and instruction loading Versatile blinking modes Independent supplies of VLCD and VDD Power supply ranges: – 1.8 V to 5.5 V for VLCD – 1.8 V to 5.5 V for VDD Ultra low-power consumption 2 400 kHz I C-bus interface (PCF8551A) 5 MHz SPI-bus interface (PCF8551B) Internally generated or externally supplied clock signal Applications • • • • Metering equipment Consumer healthcare devices Battery operated devices Measuring equipment PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 4 Ordering information Table 1. Ordering Information Product type Number Topside mark Package Name Description Version PCF8551ATT/A PCF8551A TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 PCF8551BTT/A PCF8551B TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 4.1 Ordering options Table 2. Ordering options Product type Number Orderable part number PCF8551ATT/A PCF8551ATT/AJ PCF8551BTT/A [1] [2] Package Packing method Minimum order quantity Temperature [1] TSSOP48 Reel 13” Q1 NDP 2000 Tamb = -40 °C to +85 °C PCF8551ATT/AY [2] TSSOP48 Reel 13” Q1 DP 2000 Tamb = -40 °C to +85 °C PCF8551BTT/AJ [1] TSSOP48 Reel 13” Q1 NDP 2000 Tamb = -40 °C to +85 °C PCF8551BTT/AY [2] TSSOP48 Reel 13” Q1 DP 2000 Tamb = -40 °C to +85 °C Not recommend for new design - will be discontinued in mid 2021 - use new version with improved package. Improved package - refer to PCN 202005038F01 PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 2 / 51 PCF8551 NXP Semiconductors 5 Universal 36 × 4 LCD segment driver Block diagram COM0 to COM3 SEG0 to SEG35 COM0 to COM3 36 VLCD Backplane outputs Segment outputs LCD voltage selection Vlow 36 VLCD Backplane outputs Vhigh CLK PORE LCD bias generator Oscillator Sync Clock select Prescaler Timer Power-On Reset Reset control SDA Figure 1. Block diagram of PCF8551A PCF8551 Product data sheet Blink control LCD bias generator VSS Display register Address decoder Display controller IBIAS/ VREF Oscillator Sync Clock select Prescaler Timer Power-On Reset Reset control CLK PCF8551A Internal Bus Input filters SCL Instruction register PORE aaa-013214 SCL Instruction register Display register Address decoder PCF8551B Internal Bus Input filters I2C-bus controller VDD LCD voltage selection Vlow Display controller IBIAS/ VREF Segment outputs Vhigh Blink control VSS SEG0 to SEG35 CE SDIO SPI-bus controller VDD aaa-013215 Figure 2. Block diagram of PCF8551B All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 3 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 6 Pinning information 6.1 Pinning SEG31 1 48 SEG30 SEG32 2 47 SEG29 SEG33 3 46 SEG28 SEG34 4 45 SEG27 SEG35 5 44 SEG26 COM0 6 43 SEG25 COM1 7 42 SEG24 COM2 8 41 SEG23 COM3 9 40 SEG22 VLCD 10 39 SEG21 VDD 11 38 SEG20 VSS 12 PCF8551ATT T1 13 37 SEG19 36 SEG18 CLK 14 35 SEG17 SCL 15 34 SEG16 SDA 16 33 SEG15 PORE 17 32 SEG14 SEG0 18 31 SEG13 SEG1 19 30 SEG12 SEG2 20 29 SEG11 SEG3 21 28 SEG10 SEG4 22 27 SEG9 SEG5 23 26 SEG8 SEG6 24 25 SEG7 aaa-012401 For mechanical details, see Figure 29. Figure 3. Pin configuration of PCF8551ATT (TSSOP48) PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 4 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver SEG31 1 48 SEG30 SEG32 2 47 SEG29 SEG33 3 46 SEG28 SEG34 4 45 SEG27 SEG35 5 44 SEG26 COM0 6 43 SEG25 COM1 7 42 SEG24 COM2 8 41 SEG23 COM3 9 40 SEG22 VLCD 10 39 SEG21 VDD 11 38 SEG20 VSS 12 PCF8551BTT SDIO 13 37 SEG19 36 SEG18 CLK 14 35 SEG17 SCL 15 34 SEG16 CE 16 33 SEG15 PORE 17 32 SEG14 SEG0 18 31 SEG13 SEG1 19 30 SEG12 SEG2 20 29 SEG11 SEG3 21 28 SEG10 SEG4 22 27 SEG9 SEG5 23 26 SEG8 SEG6 24 25 SEG7 aaa-012402 For mechanical details, see Figure 29. Figure 4. Pin configuration of PCF8551BTT (TSSOP48) 6.2 Pin description Table 3. Pin description Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified. Pin Type Description 1 to 5, SEG0 to SEG35 18 to 48 output LCD segment outputs 6 to 9 COM0 to COM3 output LCD backplane outputs 10 VLCD supply LCD supply voltage 11 VDD supply supply voltage 12 VSS supply ground supply Symbol PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 5 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver Table 3. Pin description...continued Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified. Pin Symbol Type Description 14 CLK input/output internal oscillator output, external oscillator input • must be left open if unused 15 SCL input serial clock input input Power-On Reset (POR) enable • connect to VDD for enabling POR • connect to VSS (or leave open) for disabling POR 17 PORE [2] [1] Pin layout depending on product and bus type 13 16 [1] [2] PCF8551ATT 2 (I C-bus) PCF8551BTT (SPI-bus) T1 - - must be left open or connected to VSS - SDIO input/output serial data input/output SDA - input/output serial data line - CE input chip enable input, active LOW Can be configured by command, see Table 5. A series resistance between VDD and the pin must not exceed 1 kΩ to ensure proper functionality, see Section 15.3. 7 Functional description 7.1 Registers of the PCF8551 The registers of the PCF8551 are arranged in bytes with 8 bit, addressed by an address pointer. Table 4 depicts the layout. Table 4. Registers of the PCF8551 Bits labeled as 0 must always be written with logic 0; bits labeled as - are ignored by the device. Register name Address Bits AP[4:0] 7 Reference 6 5 4 3 2 1 0 Command registers Software_reset 00h SR[7:0] Table 8 Device_ctrl 01h 0 0 0 0 FF[1:0] OSC COE Table 5 Display_ctrl_1 02h 0 0 0 BOOST MUX[1:0] B DE Table 6 Display_ctrl_2 03h 0 0 0 0 0 BL[1:0] INV Table 7 04h SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 Table 9 05h SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 06h SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 07h SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 08h - - - - SEG35 SEG34 SEG33 SEG32 Display data registers COM0 PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 6 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver Table 4. Registers of the PCF8551...continued Bits labeled as 0 must always be written with logic 0; bits labeled as - are ignored by the device. Address Bits Register name COM1 COM2 COM3 Reference AP[4:0] 7 6 5 4 3 2 1 0 09h SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 0Ah SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 0Bh SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 0Ch SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 0Dh - - - - SEG35 SEG34 SEG33 SEG32 0Eh SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 0Fh SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 10h SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 11h SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 12h - - - - SEG35 SEG34 SEG33 SEG32 13h SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 14h SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 15h SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 16h SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 17h - - - - SEG35 SEG34 SEG33 SEG32 For writing to the registers, send the address byte first, then write the data to the register (see Section 10.1.4 and Section 10.2.1). The address byte works as an address pointer. For the succeeding registers, the address pointer is automatically incremented by 1 (see Figure 5) and all following data are written into these register addresses. After register 18h, the auto-incrementing will stop and subsequent data are ignored. address counter 00h 01h 02h auto-increment 03h ... 15h 16h 17h aaa-011661 Figure 5. Address counter incrementing 7.2 Command registers of the PCF8551 7.2.1 Command: Device_ctrl The Device_ctrl command sets the device into a defined state. It should be executed before enabling the display (see bit DE in Table 6). PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 7 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver Table 5. Device_ctrl - device control command register (address 01h) bit description Bit Symbol Value Description 7 to 4 - 0000 default value 3 to 2 FF[1:0] frame frequency selection 00 01 1 ffr = 32 Hz [1] ffr = 64 Hz 10 ffr = 96 Hz 11 ffr = 128 Hz internal oscillator control OSC 0 [1] enabled 1 0 disabled clock output enable COE 0 [1] clock signal not available on pin CLK; pin CLK is in 3-state 1 [1] clock signal available on pin CLK Default value. 7.2.1.1 Internal oscillator and clock output Bit OSC enables or disables the internal oscillator. When the internal oscillator is used, bit COE allows making the clock signal available on pin CLK. If this is not intended, pin CLK should be left open. The design ensures that the duty cycle of the clock output is 50 : 50 (% HIGH-level time : % LOW-level time). In power-down mode (see Section 7.3.1) • if pin CLK is configured as an output, there is no signal on CLK • if pin CLK is configured as an input, the signal on CLK can be removed. In applications where an external clock has to be applied to the PCF8551, bit OSC must be set logic 1 and COE logic 0. In this case pin CLK becomes an input. Remark: A clock signal must always be supplied to the device if the display is enabled (see bit DE in Table 6). Removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. 7.2.2 Command: Display_ctrl_1 The Display_ctrl_1 command allows configuring the basic display set-up. Table 6. Display_ctrl_1 - display control command 1 register (address 02h) bit description Bit Symbol Value Description 7 to 5 - 000 default value 4 BOOST large display mode support 0 PCF8551 Product data sheet [1] standard power drive scheme All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 8 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver Table 6. Display_ctrl_1 - display control command 1 register (address 02h) bit description...continued Bit Symbol Value Description 1 3 to 2 enhanced power drive scheme for higher display loads multiplex drive mode selection MUX[1:0] 00 [1] 01 1:3 multiplex drive mode; COM0 to COM2 (nMUX = 3) 10 1:2 multiplex drive mode; COM0 and COM1 (nMUX = 2) 11 static drive mode; COM0 (nMUX = 1) [2] 1 1:4 multiplex drive mode; COM0 to COM3 (nMUX = 4) bias mode selection B 0 [1] 1 0 ⁄3 bias (abias = 2) 1 ⁄2 bias (abias = 1) display enable DE 0 [1] [3] display disabled; device is in power-down mode 1 [1] [2] [3] 1 display enabled; device is in power-on mode Default value. Not applicable for static drive mode. See Section 7.3.1. 7.2.2.1 Enhanced power drive mode By setting the BOOST bit to logic 1, the driving capability of the display signals is increased to cope with large displays with a higher effective capacitance. Setting this bit increases the current consumption on VLCD. 7.2.2.2 Multiplex drive mode MUX[1:0] sets the multiplex driving scheme and the associated backplane drive signals, which are active. For further details, see Section 8.2. 7.2.3 Command: Display_ctrl_2 Table 7. Display_ctrl_2 - display control command 2 register (address 03h) bit description Bit Symbol Value Description 7 to 3 - 00000 default value 2 to 1 BL[1:0] blink control 00 0 PCF8551 Product data sheet INV [1] blinking off 01 blinking on, fblink = 0.5 Hz 10 blinking on, fblink = 1 Hz 11 blinking on, fblink = 2 Hz inversion mode selection All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 9 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver Table 7. Display_ctrl_2 - display control command 2 register (address 03h) bit description...continued Bit Symbol Value 0 Description [1] line inversion (driving scheme A) 1 [1] frame inversion (driving scheme B) Default value. 7.2.3.1 Blinking The whole display blinks at frequencies selected by the blink control bits BL[1:0], see Table 7. The blink frequencies are derived from the clock frequency. During the blank-out phase of the blinking period, the display is turned off. If an external clock with frequency fclk(ext) is used, the blinking frequency is determined by Equation 1. For notation, see Section 8.2. (1) 7.2.3.2 Line inversion (driving scheme A) and frame inversion (driving scheme B) The waveforms used to drive LCD inherently produce a DC voltage across the display cell. The PCF8551 compensates for the DC voltage by inverting the waveforms on alternate frames or alternate lines. The choice of compensation method is determined with the INV bit. 7.3 Starting and resetting the PCF8551 If the internal Power-On Reset (POR) is enabled by connecting pin PORE to VDD, the chip resets automatically when VDD rises above the minimum supply voltage. No further action is required. If the internal POR is disabled by connecting pin PORE to VSS, the chip must be reset by a software reset (see Section 7.3.3). Following a reset, the register 00h has to be rewritten with 0h by the next command byte or the address pointer AP[4:0] has to be set to the required address after a new START procedure. See also application information in Section 15. 7.3.1 Power-down mode After a reset, the PCF8551 remains in power-down mode. In power-down mode the oscillator is switched off and there is no output on pin CLK. The register settings remain unchanged and the bus remains active. To enable the PCF8551, bit DE (command Display_ctrl_1, see Table 6) must be set to logic 1. 7.3.2 Power-On Reset (POR) If pin PORE is connected to VDD, the PCF8551 comprises an internal POR, which puts the device into the following starting conditions: • All backplane and segment outputs are set to VSS 1 • The selected drive mode is: 1:4 multiplex with ⁄3 bias • Blinking is switched off PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 10 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver • • • • The address pointer is cleared (set to logic 0) The display and the internal oscillator are disabled The display registers are set to logic 0 The bus interface is initialized Remark: The internal POR can be disabled by connecting pin PORE to VSS. In this case, the internal registers are not defined and require a software reset, see Section 7.3.3. Remark: For power-on with a slowly starting power supply, see Section 15.1. 7.3.3 Command: Software_reset The internal registers including the display registers and the address pointer (set to logic 0) of the device are reset by the Software_reset command. Table 8. Software_reset - software reset command register (address 00h) bit description Bit Symbol 7 to 0 SR[7:0] Value Description [1] software reset 0000 0000 [2] no reset 0010 1100 [1] [2] software reset Software_reset only generates a reset pulse, therefore this register always reads back as 00h. Default value. 7.4 Display data register mapping Table 9. Register to segment and backplane mapping [1] Backplanes Segments SEG0 to SEG7 SEG8 to SEG15 SEG16 to SEG23 SEG24 to SEG31 SEG32 to SEG35 LSB LSB LSB LSB LSB MSB MSB MSB MSB MSB 1:4 multiplex drive mode COM0 content of 04h content of 05h content of 06h content of 07h content of 08h COM1 content of 09h content of 0Ah content of 0Bh content of 0Ch content of 0Dh COM2 content of 0Eh content of 0Fh content of 10h content of 11h content of 12h COM3 content of 13h content of 14h content of 15h content of 16h content of 17h 1:3 multiplex drive mode COM0 content of 04h content of 05h content of 06h content of 07h content of 08h COM1 content of 09h content of 0Ah content of 0Bh content of 0Ch content of 0Dh COM2 content of 0Eh content of 0Fh content of 10h content of 11h content of 12h 1:2 multiplex drive mode COM0 content of 04h content of 05h content of 06h content of 07h content of 08h COM1 content of 09h content of 0Ah content of 0Bh content of 0Ch content of 0Dh content of 05h content of 06h content of 07h content of 08h static drive mode COM0 [1] content of 04h See also Section 8.3.1 PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 11 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver The example in Table 9 and Figure 6 illustrates the segment and backplane mapping of the display in relation to the display RAM. For example, in 1:4 multiplex drive mode, the backplanes are served by signals COM0 to COM3 and the segments are driven by signals SEG0 to SEG35. Contents of addresses 04h to 08h are allocated to the first row (COM0) starting with the LSB driving the leftmost element and moving forward to the right with increasing bit position. If a bit is logic 0, the element is off, if it is logic 1 the element is turned on. All register content is LSB to MSB left to right. Addresses 09h to 0Dh serve COM1 signals, addresses 0Eh to 12h serve COM2 signals, and addresses 13h to 17h serve COM3 signals. For displays with fewer segments/elements, the unused bits are ignored. PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 12 / 51 PCF8551 Product data sheet Rev. 3.1 — 3 May 2021 All information provided in this document is subject to legal disclaimers. SEG35 SEG33 SEG31 SEG29 SEG27 SEG25 SEG23 D118 D158 D119 D117 D157 D15 D16 D48 D55 D56 D79 D78 D77 D76 D72 D71 D64 D39 D38 D37 D36 D32 D31 D24 D23 D8 D47 D63 D7 D40 RAM D159 D116 D112 D152 D156 D111 D104 D144 D151 D103 D143 D96 D136 D0 COM1 SEG21 D95 D135 D88 D128 COM0 SEG19 SEG17 SEG15 SEG13 SEG11 SEG9 SEG7 D87 D120 D127 D80 COM3 SEG5 COM2 SEG3 SEG1 SEG34 SEG32 SEG30 SEG28 SEG26 SEG24 SEG22 SEG20 SEG18 SEG16 SEG14 SEG12 SEG10 SEG8 SEG6 SEG4 SEG2 SEG0 NXP Semiconductors Universal 36 × 4 LCD segment driver PCF8551 discarded Display aaa-014858 Figure 6. Display RAM organization bitmap for MUX 1:4 © NXP B.V. 2021. All rights reserved. 13 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 8 Possible display configurations The possible display configurations of the PCF8551 depend on the number of active backplane outputs required. A selection of display configurations is shown in Table 10. All of these configurations can be implemented in the typical systems shown in Figure 8 or Figure 9. dot matrix 7-segment with dot 14-segment with dot and accent 013aaa312 Figure 7. Example of displays suitable for PCF8551 Table 10. Selection of possible display configurations Number of Backplanes Icons Digits/Characters 7-segment Product data sheet [2] 14-segment Dot matrix: segments/ elements 4 144 18 9 144 dots (4 × 36) 3 108 13 6 108 dots (3 × 36) 2 72 9 4 72 dots (2 × 36) 1 36 4 2 36 dots (1 × 36) [1] [2] PCF8551 [1] 7 segment display has 8 segments/elements including the decimal point. 14 segment display has 16 segments/elements including decimal point and accent dot. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 14 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver VDD VLCD tr R≤ 2Cb 100 nF 100 nF VDD VLCD 36 segment drives SDA HOST MICROCONTROLLER LCD PANEL (up to 144 elements) PCF8551A SCL 4 backplanes PORE CLK VSS n.c. VSS aaa-013223 The resistance of the power lines must be kept to a minimum. A decoupling capacitor of at least 100 nF is recommended for the supplies. 2 Figure 8. Typical system configuration using I C-bus, internal power-on reset disabled 2 The host microcontroller manages the 2-line I C-bus communication channel with the PCF8551A. The internal oscillator is used and the internal POR is disabled in the example. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are the power supplies (VDD, VSS, and VLCD) and the LCD panel chosen for the application. VDD VLCD 100 nF PORE 100 nF VDD VLCD 36 segment drives CE HOST MICROCONTROLLER LCD PANEL (up to 144 elements) PCF8551B SDIO SCL 4 backplanes CLK VSS n.c. VSS aaa-013224 The resistance of the power lines must be kept to a minimum. A decoupling capacitor of at least 100 nF is recommended for the supplies. Figure 9. Typical system configuration using SPI-bus, internal power-on reset enabled The host microcontroller manages the 3-line SPI-bus communication channel with the PCF8551B. The internal oscillator is enabled. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are the power supplies (VDD, VSS, and VLCD) and the LCD panel chosen for the application. 8.1 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider of three impedances connected between VLCD and VSS. These intermediate levels are tapped PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 15 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 1 2 1 off at positions of ⁄3 and ⁄3, or ⁄2, depending on the bias mode chosen. To keep current consumption to a minimum, on-chip low-power buffers provide these levels to the display. 8.2 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the Display_ctrl_1 command (see Table 6). The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D) are given in Table 11. Table 11. Biasing characteristics LCD drive mode Number of: static 1 Backplanes Levels 1:2 multiplex 2 1:2 multiplex 2 1:3 multiplex 3 1:4 multiplex 4 LCD bias configuration 2 static 0 1 ∞ 3 1 0.354 0.791 2.236 4 1 0.333 0.745 2.236 4 1 0.333 0.638 1.915 4 1 0.333 0.577 1.732 ⁄2 ⁄3 ⁄3 ⁄3 A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode, a suitable choice is VLCD > 3Vth(off). 1 Multiplex drive modes of 1:3 and 1:4 with ⁄2 bias are possible but the discrimination and hence the contrast ratios are smaller. Bias is calculated with Equation 2 (2) The values for abias are: 1 abias = 1 for ⁄2 bias 1 abias = 2 for ⁄3 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 3: (3) where the values for n are nMUX = 1 for static drive mode nMUX = 2 for 1:2 multiplex drive mode nMUX = 3 for 1:3 multiplex drive mode nMUX = 4 for 1:4 multiplex drive mode The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 4: (4) PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 16 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver Discrimination is a term which is defined as the ratio of the on and off RMS voltages (Von(RMS) to Voff(RMS)) across a segment. It can be thought of as a measurement of contrast. Discrimination is determined from Equation 5: (5) 1 Using Equation 5, the discrimination for an LCD drive mode of 1:3 multiplex with ⁄2 bias 1 is and the discrimination for an LCD drive mode of 1:4 multiplex with ⁄2 bias is . The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows: • 1:3 multiplex (1⁄ bias): 2 • 1 1:4 multiplex ( ⁄2 bias): 1 These compare with when ⁄3 bias is used. VLCD is sometimes referred as the LCD operating voltage. 8.2.1 Electro-optical performance Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The RMS voltage, at which a pixel is switched on or off, determine the transmissibility of the pixel. For any given liquid, there are two threshold values defined. One point is at 10 % relative transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see Figure 10. For a good contrast performance, the following rules should be followed: (6) (7) Von(RMS) (see Equation 3) and Voff(RMS) (see Equation 5) are properties of the display driver and are affected by the selection of abias, nMUX, and the VLCD voltage. Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module manufacturer. Vth(off) is sometimes named Vth. Vth(on) is sometimes named saturation voltage Vsat. It is important to match the module properties to those of the driver in order to achieve optimum performance. PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 17 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 100 % Relative Transmission 90 % 10 % Vth(off) OFF SEGMENT Vth(on) GREY SEGMENT VRMS [V] ON SEGMENT 013aaa494 Figure 10. Electro-optical characteristic: relative transmission curve of the liquid 8.2.2 LCD drive mode waveforms 8.2.2.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (COMn) and segment (SEGn) drive waveforms for this mode are shown in Figure 11. PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 18 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver Tfr LCD segments VLCD COM0 VSS state 1 (on) VLCD state 2 (off) SEGn VSS VLCD SEGn+1 VSS (a) Waveforms at driver. VLCD state 1 0V - VLCD VLCD state 2 0V - VLCD (b) Resultant waveforms at LCD segment. aaa-011867 Vstate1(t) = VSEGn(t) - VCOM0(t). Von(RMS) = VLCD. Vstate2(t) = V(SEGn + 1)(t) - VCOM0(t). Voff(RMS) = 0 V. Figure 11. Static drive mode waveforms 8.2.2.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The 1 1 PCF8551 allows the use of ⁄2 bias or ⁄3 bias in this mode as shown in Figure 12 and Figure 13. PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 19 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver Tfr VLCD COM0 LCD segments VLCD/2 VSS state 1 VLCD COM1 state 2 VLCD/2 VSS VLCD SEGn VSS VLCD SEGn+1 VSS (a) Waveforms at driver. VLCD VLCD/2 state 1 0V - VLCD/2 - VLCD VLCD VLCD/2 state 2 0V - VLCD/2 - VLCD (b) Resultant waveforms at LCD segment. Vstate1(t) = VSEGn(t) - VCOM0(t). Von(RMS) = 0.791VLCD. Vstate2(t) = VSEGn(t) - VCOM1(t). Voff(RMS) = 0.354VLCD. aaa-011868 1 Figure 12. Waveforms for the 1:2 multiplex drive mode with ⁄2 bias PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 20 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver Tfr VLCD COM0 COM1 LCD segments 2VLCD/3 VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD SEGn 2VLCD/3 VLCD/3 VSS VLCD SEGn+1 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 state 1 VLCD/3 0V - VLCD/3 -2V LCD/3 - VLCD VLCD 2VLCD/3 state 2 VLCD/3 0V - VLCD/3 -2V LCD/3 - VLCD (b) Resultant waveforms at LCD segment. aaa-011869 Vstate1(t) = VSEGn(t) - VCOM0(t). Von(RMS) = 0.745VLCD. Vstate2(t) = VSEGn(t) - VCOM1(t). Voff(RMS) = 0.333VLCD. 1 Figure 13. Waveforms for the 1:2 multiplex drive mode with ⁄3 bias 8.2.2.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as shown in Figure 14. PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 21 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver COM0 COM1 COM2 SEGn Tfr VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD SEGn+1 2VLCD/3 VLCD/3 VSS VLCD SEGn+2 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD state 1 2VLCD/3 VLCD/3 0V - VLCD/3 -2V LCD/3 - VLCD VLCD 2VLCD/3 state 2 VLCD/3 0V - VLCD/3 -2V LCD/3 - VLCD (b) Resultant waveforms at LCD segment. Vstate1(t) = VSEGn(t) - VCOM0(t). Von(RMS) = 0.638VLCD. Vstate2(t) = VSEGn(t) - VCOM1(t). Voff(RMS) = 0.333VLCD. aaa-011870 1 Figure 14. Waveforms for the 1:3 multiplex drive mode with ⁄3 bias 8.2.2.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as shown in Figure 15. PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 22 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver COM0 VLCD 2VLCD/3 VLCD/3 VSS COM1 VLCD 2VLCD/3 VLCD/3 VSS COM2 VLCD 2VLCD/3 VLCD/3 VSS COM3 VLCD 2VLCD/3 VLCD/3 VSS SEGn VLCD 2VLCD/3 VLCD/3 VSS SEGn+1 VLCD 2VLCD/3 VLCD/3 VSS SEGn+2 VLCD 2VLCD/3 VLCD/3 VSS SEGn+3 VLCD 2VLCD/3 VLCD/3 VSS Tfr LCD segments state 1 state 2 (a) Waveforms at driver. state 1 VLCD 2VLCD/3 VLCD/3 0V - VLCD/3 -2V LCD/3 - VLCD state 2 VLCD 2VLCD/3 VLCD/3 0V - VLCD/3 -2V LCD/3 - VLCD (b) Resultant waveforms at LCD segment. Vstate1(t) = VSEGn(t) - VCOM0(t). Von(RMS) = 0.577VLCD. Vstate2(t) = VSEGn(t) - VCOM1(t). Voff(RMS) = 0.333VLCD. aaa-011871 1 Figure 15. Waveforms for the 1:4 multiplex drive mode with ⁄3 bias 8.3 Backplane and segment outputs PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 23 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 8.3.1 Backplane outputs The LCD drive section includes four backplane outputs COM0 to COM3, which must be directly connected to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required, the unused outputs can be left open-circuit. • In 1:3 multiplex drive mode, COM3 carries the same signal as COM1, therefore these two outputs can be tied together to give enhanced drive capabilities • In 1:2 multiplex drive mode, COM0 and COM2, respectively, COM1 and COM3 all carry the same signals and may also be paired to increase the drive capabilities • In static drive mode, the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements 8.3.2 Segment outputs The LCD drive section includes 36 segment outputs SEG0 to SEG35, which must be directly connected to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display registers. When less than 36 segment outputs are required, the unused segment outputs must be left open-circuit. 9 Power Sequencing 9.1 Power-on To avoid unwanted artifacts on the display, VLCD must never be asserted before VDD, it is permitted to assert VDD and VLCD at the same time. 9.2 Power-off Before turning the power to the device off, the display must be disabled by setting bit DE to logic 0. To avoid unwanted artifacts on the display, VLCD must never be connected, while VDD is switched off. It is permitted to switch off VDD and VLCD simultaneously. 9.3 Power sequences Figure 16 depicts the recommended power-up and power-off sequence. PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 24 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver POWER-ON POWER-OFF Apply VDD(2) Disable display Apply VLCD(1) Remove VLCD(1) Reset Remove VDD(2) Write display data Set device control register Set display control register(s) aaa-011937 Reset: internal power-on reset if PORE = 1, or software reset. If an external oscillator is used, clock must be available after reset. 1. Can be simultaneous with VDD. 2. Can be simultaneous with VLCD. Figure 16. Recommended power-up and power-off sequence 10 Bus interfaces 2 10.1 I C-bus interface of the PCF8551A 2 The I C-bus is for bidirectional, two-line communication between different ICs. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. Both data and clock lines remain HIGH when the bus is not busy. The PCF8551A acts as a slave receiver when being written to and as a slave transmitter when being read from. Write S slave address + 0 A ACK from slave Read slave address + 1 S A write data ACK from slave A ACK from slave read data A ACK from slave A ACK from master write data read data write data A P ACK from slave A ACK from master read data A P ACK from slave aaa-010487 2 Figure 17. I C read and write protocol PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 25 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver I2C write example SCL SDA bit7 S START condition bit0 ACK 1st byte, slave address with R/W = 0 bit7 bit0 ACK P write 2nd byte ACK of 2nd byte from slave ACK of 1st byte from slave STOP condition I2C read example SCL SDA bit7 S START condition bit0 ACK 1st byte, slave address with R/W = 1 ACK of 1st byte from slave bit7 bit0 ACK read 2nd byte ACK of 2nd byte from slave P STOP condition aaa-010489 2 Figure 18. I C read and write signaling 10.1.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse, as changes in the data line at this time are interpreted as STOP or START conditions. 10.1.2 START and STOP conditions A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition - S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition - P (see Figure 18). 10.1.3 Acknowledge Each byte of 8 bits is followed by an acknowledge cycle. An acknowledge is defined as logic 0. A not-acknowledge is defined as logic 1. When written to, the slave will generate an acknowledge after the reception of each byte. After the acknowledge, another byte may be transmitted. It is also possible to send a STOP or START condition. When read from, the master receiver must generate an acknowledge after the reception of each byte. When the master receiver no longer requires bytes to be transmitted, it must generate a not-acknowledge. After the not-acknowledge, either a STOP or START condition must be sent. Remark: The PCF8551A omits the not-acknowledge. After the last byte read, the end of transmission is indicated by a STOP or START condition from the master. 2 A detailed description of the I C-bus specification is given in [5]. PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 26 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 2 10.1.4 I C interface protocol 2 The PCF8551A uses the I C interface for data transfer. Interpretation of the data is determined by the interface protocol. 10.1.4.1 Write protocol 2 After the I C slave address is transmitted, the PCF8551A requires that the register address pointer is defined. It can take the value 00h to 17h. Values outside of that range will result in the transfer being ignored, however the slave will still respond with acknowledge pulses. After the register address has been transmitted, write data is transmitted. The minimum number of data write bytes is 0 and the maximum number is unlimited. After each write, the address pointer increments by one. After address 17h, the address pointer stops incrementing at 18h. • • • • • • • • 2 I C START condition 2 I C slave address + write start register pointer write data write data : write data 2 2 I C STOP condition; an I C RE-START condition is also possible. 10.1.4.2 Read protocol When reading the PCF8551A, reading starts at the current position of the address pointer. The address pointer for read data should first be defined by a write sequence. • • • • 2 I C START condition 2 I C slave address + write start address pointer 2 2 I C STOP condition; an I C RE-START condition is also possible. 2 After setting the address pointer, a read can be executed. After the I C slave address is transmitted, the PCF8551A will immediately output read data. After each read, the address pointer increments by one. After address 17h, the address pointer stops incrementing at 18h. • • • • • 2 I C START condition 2 I C slave address + read read data (master sends acknowledge bit) read data (master sends acknowledge bit) : 2 10.1.4.3 I C-bus slave address 2 Device selection depends on the I C-bus slave address (see Table 12). PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 27 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 2 Table 12. I C slave address byte Slave address Bit 7 MSB 6 5 4 3 2 1 0 LSB 0 1 1 1 0 0 0 R/W The least significant bit of the slave address byte is bit R/W (see Table 13). Table 13. R/W-bit description R/W Description 0 write data 1 read data 10.2 SPI-bus interface of the PCF8551B Data transfer to the device is made via a 3-line SPI-bus (see Table 14). There is no dedicated output data line. The SPI-bus is initialized whenever the chip enable line pin CE is pulled down. Table 14. Serial interface Symbol Function Description [1] CE chip enable input ; active LOW when HIGH, the interface is reset SCL serial clock input input may be higher than VDD SDIO serial data input/output input data are sampled on the rising edge of SCL, output data are valid after the falling edge of SCL [1] The chip enable must not be wired permanently LOW. 10.2.1 Data transmission The chip enable signal is used to identify the transmitted data. Each data transfer is a byte with the Most Significant Bit (MSB) sent first. The transmission is controlled by the active LOW chip enable signal CE. The first byte transmitted is the register address comprising of the address pointer and the R/W bit. data bus REGISTER ADDRESS DATA DATA DATA CE aaa-011938 Figure 19. Data transfer overview Table 15. Address byte definition PCF8551 Product data sheet Bit Symbol 7 R/W Value Description data read or write selection 0 write data 1 read data All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 28 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver Table 15. Address byte definition...continued Bit Symbol Value Description 6 to 5 - 00 default value 4 to 0 AP[4:0] pointer to register start address 00h to 17h valid range; other addresses are ignored After the register address byte, the register contents follows with the address pointer being auto-incremented after every eighth bit sent (see Section 7.1). 10.2.1.1 Write protocol After the CE is set LOW, the PCF8551B requires that R/W and the register address pointer is defined. It can take the value 00h to 17h. Values outside of that range result in the transfer being ignored. After the register address has been transmitted, write data is transmitted. The minimum number of data write bytes is 0 and the maximum number is unlimited. After each write, the address pointer increments by one. After address 17h, the address pointer stops incrementing at 18h. • • • • • • • CE set LOW R/W = 0 and register address write data write data : write data CE set HIGH R/W default b7 0 b6 0 b5 0 AP[4:0] b4 0 b3 0 b2 0 b1 0 register data b0 0 b7 0 b6 0 b5 0 b4 0 b3 0 register data b2 0 b1 0 b0 0 b7 0 b6 0 b5 0 b4 0 b3 1 b2 1 b1 1 b0 1 SCL SDIO CE aaa-011951 Data transfers are terminated by de-asserting CE (set CE to logic 1). Figure 20. SPI-bus write example: writing two data bytes to registers 00h and 01h 10.2.1.2 Read protocol When reading the PCF8551B, reading starts at the defined position of the address pointer. After setting the address pointer, the read can be executed. After each read, the address pointer increments by one. After address 17h, the address pointer stops incrementing at 18h. • • • • • PCF8551 Product data sheet CE set LOW R/W = 1 and register address read data read data : All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 29 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver • CE set HIGH R/W default b7 1 b6 0 AP[4:0] b5 0 b4 0 b3 0 b2 1 display data b1 0 b0 0 b7 1 b6 1 b5 1 b4 0 b3 0 display data b2 0 b1 0 b0 0 b7 0 b6 0 b5 1 b4 1 b3 0 b2 0 b1 0 b0 0 SCL SDIO CE aaa-011954 Data transfers are terminated by de-asserting CE (set CE to logic 1). Figure 21. SPI-bus read example: reading two data bytes from registers 04h and 05h 10.3 EMC detection The PCF8551 is ruggedized against EMC susceptibility; however it is not possible to cover all cases. To detect if a severe EMC event has occurred, it is possible to check the responsiveness of the device by reading its registers. 11 Internal circuitry VDD SCL, SDA/CE PORE, SDIO, CLK VSS VSS VLCD SEG0 to SEG35 COM0 to COM3 VSS aaa-013225 Figure 22. Device protection diagram 12 Safety notes CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices. Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or equivalent standards. PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 30 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. 13 Limiting values Table 16. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Min Max Unit VDD supply voltage -0.5 +6.5 V VLCD LCD supply voltage -0.5 +6.5 V VI input voltage -0.5 +6.5 V VO output voltage -0.5 +6.5 V II input current -10 +10 mA IO output current -10 +10 mA IDD supply current -50 +50 mA IDD(LCD) LCD supply current -50 +50 mA ISS ground supply current -50 +50 mA Ptot total power dissipation - 100 mW Po output power - 100 mW - ±2 000 V VESD electrostatic discharge voltage Conditions [1] HBM on pins SCL, SDA, CE on all other pins - ±5 000 V [2] - ±500 V latch-up current [3] - 200 mA Tstg storage temperature [4] -55 +150 °C Tamb ambient temperature -40 +85 °C CDM Ilu [1] [2] [3] [4] operating device Pass level; Human Body Model (HBM), according to [1]. Pass level; Charged-Device Model (CDM), according to [2]. Pass level; latch-up testing according to [3] at maximum ambient temperature (Tamb(max)). According to the store and transport requirements (see [6]) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. 14 Characteristics Table 17. Electrical characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 5.5 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage 1.8 - 5.5 V VLCD LCD supply voltage 1.8 - 5.5 V PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 31 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver Table 17. Electrical characteristics...continued VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 5.5 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions IDD supply current ffr = 64 Hz; no bus activity IDD(LCD) LCD supply current Min Typ Max Unit VDD = 3.3 V; Tamb = 25 °C - 0.6 - μA VDD = 5.5 V; Tamb = 85 °C - 1.2 2.7 μA - 3.2 4.5 μA BOOST = 0; no display load - 2.5 - μA BOOST = 0; display enabled; display load CL = 1.4 nF - 4.5 - μA BOOST = 1; display enabled; display load CL = 1.4 nF - 5.5 - μA VSS - 0.3VDD V 0.7VDD - VDD V on pin CLK 2 - - mA on pin SDIO 2 - - mA on pin SDA 3 - - mA ffr = 64 Hz; no bus activity [1] VLCD = 5.5 V; Tamb = 85 °C; BOOST = 0; no display load VLCD = 3.3 V; Tamb = 25 °C VIL LOW-level input voltage VIH HIGH-level input voltage IOL LOW-level output current [2] output sink current; VOL = 0.4 V; VDD = 5 V IOH HIGH-level output current output source current; on pins SDIO, CLK; VOH = 4.6 V; VDD = 5 V 2 - - mA IL leakage current any input pin except for RST - 0 - nA after ESD event -500 - +500 nA - 100 - kΩ -100 - +100 mV - 1.5 3 kΩ Rpu(RST_n) pull-up resistance on pin RST_N LCD outputs (pins SEG0 to SEG17 and COM0 to COM3) ΔVo output voltage variation Ro [1] [2] [3] output resistance VLCD = 5 V VLCD = 5 V [3] For typical values, also see Figure 23 to Figure 25. 2 I C pins SCL and SDA have no diode to VDD and may be driven up to 5.5 V. Outputs measured one at a time. PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 32 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver aaa-012359 103 IDD (nA) 103 IDD(LCD) (nA) (1) (2) 102 102 10 10 1 -50 -30 -10 10 30 50 70 Tamb (°C) 90 1 VDD = 5.5 V, VLCD = 5.5 V; power-down mode. 1. IDD. 2. IDD(LCD). Figure 23. Typical IDD and IDD(LCD) in power-down mode as function of temperature aaa-012153 12 IDD(LCD) (μA) 10 (8) (6) (4) 8 (7) (5) 6 (2) (3) 4 2 0 (1) 0 0.7 1.4 2 2.7 3.4 4.1 4.7 CL (nF) 5.4 Tamb = 25 °C; VLCD = 3.3 V; VDD = 3.3 V; ffr = 64 Hz, BOOST = 0. 1. Static, all segments/elements off. 2. Static, all segments/elements on. 1 3. MUX 1:2, bias level ⁄2, all segments/elements off. 1 4. MUX 1:2, bias level ⁄2, all segments/elements on. 1 5. MUX 1:3, bias level ⁄3, all segments/elements off. 1 6. MUX 1:3, bias level ⁄3, all segments/elements on. 1 7. MUX 1:4, bias level ⁄3, all segments/elements off. 1 8. MUX 1:4, bias level ⁄3, all segments/elements on. Figure 24. Typical IDD(LCD) as function of display load PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 33 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver aaa-012360 8 IDD(LCD) (μA) (8) 6 (6) (7) (4) 4 (5) 2 0 (3) (2) (1) 32 64 96 128 ffr (Hz) 160 Tamb = 25 °C; VLCD = 3.3 V; VDD = 3.3 V; ffr = 64 Hz, BOOST = 0, CL = 1.6 nF. 1. Static, all segments/elements off. 2. Static, all segments/elements on. 1 3. MUX 1:2, bias level ⁄2, all segments/elements off. 1 4. MUX 1:2, bias level ⁄2, all segments/elements on. 1 5. MUX 1:3, bias level ⁄3, all segments/elements off. 1 6. MUX 1:3, bias level ⁄3, all segments/elements on. 1 7. MUX 1:4, bias level ⁄3, all segments/elements off. 1 8. MUX 1:4, bias level ⁄3, all segments/elements on. Figure 25. Typical IDD(LCD) as function of ffr Table 18. Frequency characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 5.5 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit ffr frame frequency FF[1:0] = 00 - 32 - Hz FF[1:0] = 01 42 64 86 Hz FF[1:0] = 10 - 96 - Hz FF[1:0] = 11 fclk(int) internal clock frequency ffr = 64 Hz, nMUX = 4 - 128 - Hz [1] - 1024 - Hz [1] - - 4096 Hz fclk(ext) external clock frequency tclk(H) HIGH-level clock time external clock 60 - - μs tclk(L) LOW-level clock time external clock 60 - - μs tw(rst) reset pulse width on pin RST 10 - - μs [1] PCF8551 Product data sheet or respectively (see Table 5 and Table 6). All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 34 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver aaa-012364 1536 fclk (Hz) 1280 (4) (3) (2) (1) 1024 768 512 256 0 1. 2. 3. 4. 32 64 96 128 ffr (Hz) 160 nMUX = 1. nMUX = 2. nMUX = 3. nMUX = 4. Figure 26. Relation of frame frequency (ffr), clock frequency (fclk) and multiplex-rate (nMUX) 2 Table 19. I C-bus characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; unless otherwise specified; all timing values are valid within the [1] operating supply voltage and Tamb range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. Symbol Parameter Conditions Min Typ Max Unit Pin SCL fSCL SCL clock frequency - - 400 kHz tLOW LOW period of the SCL clock 1.3 - - μs tHIGH HIGH period of the SCL clock 0.6 - - μs tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns Pin SDA Pins SCL and SDA tBUF bus free time between a STOP and START condition 1.3 - - μs tSU;STO set-up time for STOP condition 0.6 - - μs tHD;STA hold time (repeated) START condition 0.6 - - μs tSU;STA set-up time for a repeated START condition 0.6 - - μs PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 35 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 2 Table 19. I C-bus characteristics...continued VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; unless otherwise specified; all timing values are valid within the [1] operating supply voltage and Tamb range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. Symbol Parameter Conditions Min Typ Max Unit tr rise time of both SDA and SCL signals fSCL = 400 kHz - - 0.3 μs tf fall time of both SDA and SCL signals - - 0.3 μs Cb capacitive load for each bus line - - 400 pF tw(spike) spike pulse width - - 50 ns [1] 2 on the I C-bus 2 The I C-bus interface of PCF8551A is 5 V tolerant. SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tSU;DAT tHIGH SDA tSU;STA tSU;STO mga728 2 Figure 27. I C-bus timing waveforms Table 20. SPI-bus characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; unless otherwise specified; all timing values are valid within the operating supply voltage and Tamb range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. Symbol Parameter Conditions Min Typ Max Unit Pin SCL fSCL SCL clock frequency - - 5 MHz tLOW LOW period of the SCL clock 150 - - ns tHIGH HIGH period of the SCL clock 80 - - ns tr rise time - - 100 ns tf fall time - - 100 ns Pin CE PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 36 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver Table 20. SPI-bus characteristics...continued VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; unless otherwise specified; all timing values are valid within the operating supply voltage and Tamb range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. Symbol Parameter tsu(CE_N) Conditions Min Typ Max Unit CE_N set-up time 30 - - ns th(CE_N) CE_N hold time 10 - - ns trec(CE_N) CE_N recovery time 70 - - ns Pin SDIO tsu set-up time write data 5 - - ns th hold time write data 50 - - ns td(R)SDIO SDIO read delay time CL = 50 pF - - 150 ns tdis(SDIO) SDIO disable time no load - - 50 ns tt(SDI-SDO) transition time from SDI to SDO write to read mode 0 - - ns CE tsu(CE_N) tr tf th(CE_N) 80 % SCL 20 % tHIGH WRITE SDIO trec(CE_N) tLOW tsu th R/W SA2 RA0 b7 b6 b0 b7 b6 b0 READ SDI tt(SDI-SDO) SDIO SDO high-Z td(R)SDIO b7 tdis(SDIO) b6 b0 aaa-012166 Figure 28. SPI-bus timing waveforms PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 37 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 15 Application information 15.1 Power-on Reset The built-in POR block acts on the rising edge of the VDD supply voltage. Depending on the VDD rising edge in the application, the POR may not work properly. Therefore to ensure proper device operation it is required to send nine clock pulses immediately after power-on (see also UM10204). 2 15.2 I C acknowledge after power-on If the bus does not show an acknowledge at the first access, the command should be sent a second time. 15.3 Resistors on I/O pins The pin PORE comprises an internal, latching pull-down device, which keeps the input at a low potential when left open. If the input is supposed to be at logic 0 potential, this pin can be either connected to VSS or left open. In case the pin is supposed to be at logic 1 potential, it must be connected to VDD to avoid any cross-current during power-up. A series resistance between VDD and PORE must not exceed 1 kΩ to ensure proper functionality. PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 38 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 16 Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c v HE y A Z 48 25 Q A2 A1 (A3) pin 1 index A θ Lp 1 L 24 bp e detail X w 0 5 mm 2.5 scale Dimensions (mm are the original dimensions) Unit mm max nom min A 1.2 A1 A2 0.15 1.05 0.05 0.85 A3 0.25 bp c D(1) E(2) 0.28 0.2 12.6 6.2 0.17 0.1 12.4 6.0 e HE 0.5 8.3 7.9 L 1 Lp Q 0.8 0.50 0.4 0.35 v w 0.25 0.08 y 0.1 Z θ 0.8 8° 0.4 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. Outline version SOT362-1 References IEC JEDEC JEITA sot362-1_po European projection Issue date 03-02-19 13-08-05 MO-153 Figure 29. Package outline SOT362-1 (TSSOP48) of PCF8551 PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 39 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 17 Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC  61340-5 or equivalent standards. 18 Packing information 18.1 Tape and reel information For tape and reel packing information, see [4]. 19 Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 19.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 19.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • Board specifications, including the board finish, solder masks and vias • Package footprints, including solder thieves and orientation • The moisture sensitivity level of the packages PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 40 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering 19.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 19.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 30) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 21 and Table 22 Table 21. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 22. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 41 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 30. temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Figure 30. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 42 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 20 Footprint information Footprint information for reflow soldering of TSSOP48 package SOT362-1 Hx Gx P2 (0.125) Hy (0.125) Gy By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 0.500 0.560 8.900 6.100 1.400 0.280 D2 Gx 0.400 12.270 Gy Hx Hy 7.000 14.100 9.150 sot362-1_fr Figure 31. Footprint information for reflow soldering of SOT362-1 (TSSOP48) of PCF8551 PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 43 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 21 Appendix 21.1 LCD segment driver selection Table 23. Selection of LCD segment drivers Type name PCA8553DTT PCA8546ATT PCA8546BTT PCA8547AHT PCA8547BHT PCF85134HL PCA85134H PCA8543AHL PCF8545ATT PCF8545BTT PCF8536AT PCF8536BT PCA8536AT PCA8536BT PCF8537AH PCF8537BH PCA8537AH PCA8537BH PCA9620H PCA9620U PCF8576DU PCF8551 Product data sheet Number of elements at MUX 1:1 1:2 1:3 1:4 1:6 1:8 1:9 40 80 120 160 - - - 44 44 60 60 60 44 44 44 44 60 60 40 88 88 120 120 120 88 88 88 88 120 120 80 180 180 120 176 176 176 176 240 240 240 176 176 176 176 176 176 176 176 176 176 240 240 160 252 252 252 252 252 252 276 276 276 276 320 320 - 320 320 320 320 320 320 352 352 352 352 480 480 - - VDD (V) VLCD (V) ffr (Hz) 1.8 to 5.5 1.8 to 5.5 32 to 256 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 2.5 to 5.5 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 2.5 to 5.5 2.5 to 5.5 1.8 to 5.5 2.5 to 9 2.5 to 9 2.5 to 9 2.5 to 9 2.5 to 6.5 2.5 to 8 2.5 to 9 2.5 to 5.5 2.5 to 5.5 2.5 to 9 2.5 to 9 2.5 to 9 2.5 to 9 2.5 to 9 2.5 to 9 2.5 to 9 2.5 to 9 2.5 to 9 2.5 to 9 2.5 to 6.5 [1] VLCD (V) charge pump VLCD (V) temperature compensat. Tamb (°C) Interface Package AECQ100 N N -40 to 105 I C / SPI 2 TSSOP56 Y 2 [1] N N -40 to 95 I C TSSOP56 Y [1] N N -40 to 95 SPI TSSOP56 Y 60 to 300 60 to 300 [1] Y Y -40 to 95 I C TQFP64 Y [1] Y Y -40 to 95 SPI 60 to 300 60 to 300 82 N 82 N [1] 60 to 300 Y N N Y 2 TQFP64 Y -40 to 85 2 I C LQFP80 N -40 to 95 2 I C LQFP80 Y 2 LQFP80 Y 2 -40 to 105 I C [1] N N -40 to 85 I C TSSOP56 N [1] N N -40 to 85 SPI TSSOP56 N 60 to 300 60 to 300 [1] N N -40 to 85 I C TSSOP56 N [1] N N -40 to 85 SPI TSSOP56 N 60 to 300 60 to 300 2 [1] N N -40 to 95 I C TSSOP56 Y [1] N N -40 to 95 SPI TSSOP56 Y 60 to 300 60 to 300 2 [1] Y Y -40 to 85 I C TQFP64 N [1] Y Y -40 to 85 SPI TQFP64 N 60 to 300 60 to 300 2 [1] Y Y -40 to 95 I C TQFP64 Y [1] Y Y -40 to 95 SPI 60 to 300 60 to 300 [1] 60 to 300 [1] 60 to 300 77 Y Y N All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 Y Y N 2 TQFP64 Y -40 to 105 2 I C LQFP80 Y -40 to 105 2 I C Bare die Y 2 Bare die N -40 to 85 I C © NXP B.V. 2021. All rights reserved. 44 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver Table 23. Selection of LCD segment drivers...continued Type name PCF8576EUG PCA8576FUG PCF85133U PCA85133U PCA85233UG PCF85132U PCA8530DUG PCA85132U PCA85232U PCF8538UG PCA8538UG [1] [2] Number of elements at MUX 1:1 1:2 1:3 1:4 1:6 1:8 1:9 40 80 120 160 - - - 40 80 80 80 160 102 160 160 102 102 80 160 160 160 320 204 320 320 204 204 120 240 240 240 480 480 480 - 160 320 320 320 640 408 640 640 408 408 612 612 816 816 918 918 VDD (V) VLCD (V) ffr (Hz) VLCD (V) charge pump VLCD (V) temperature compensat. Tamb (°C) Interface 1.8 to 5.5 2.5 to 6.5 77 N N -40 to 85 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 2.5 to 5.5 1.8 to 5.5 1.8 to 5.5 2.5 to 5.5 2.5 to 5.5 2.5 to 8 2.5 to 6.5 2.5 to 8 2.5 to 8 1.8 to 8 4 to 12 1.8 to 8 1.8 to 8 4 to 12 4 to 12 200 N 82, 110 [2] 82, 110 [2] N N [2] 150, 220 60 to 90 [1] N [1] 45 to 300 60 to 90 N [1] Y N [1] 117 to 176 [1] 45 to 300 [1] 45 to 300 N Y Y N N N N N Y N N Y Y Package AECQ100 I C 2 Bare die N 2 I C Bare die Y -40 to 85 2 I C Bare die N -40 to 95 2 I C Bare die Y 2 I C Bare die Y 2 I C Bare die N 2 Bare die Y -40 to 95 2 I C Bare die Y -40 to 95 2 I C Bare die Y -40 to 85 2 Bare die N 2 Bare die Y -40 to 105 -40 to 105 -40 to 85 -40 to 105 -40 to 105 I C / SPI I C / SPI I C / SPI Software programmable. Hardware selectable. PCF8551 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 45 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 22 Abbreviations Table 24. Abbreviations Acronym Description CDM Charged-Device Model DC Direct Current EMC ElectroMagnetic Compatibility ESD ElectroStatic Discharge HBM Human Body Model 2 I C Inter-Integrated Circuit bus IC Integrated Circuit LCD Liquid Crystal Display LSB Least Significant Bit MSB Most Significant Bit MSL Moisture Sensitivity Level MUX Multiplexer PCB Printed-Circuit Board POR Power-On Reset RC Resistance-Capacitance RMS Root Mean Square SCL Serial CLock line SDA Serial DAta line SMD Surface-Mount Device SPI Serial Peripheral Interface 23 References [1] [2] [3] [4] [5] [6] PCF8551 Product data sheet JESD22-A114 Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) JESD22-C101 Field-Induced Charged-Device Model Test Method for ElectrostaticDischarge-Withstand Thresholds of Microelectronic Components JESD78 IC Latch-Up Test SOT362-1_118 TSSOP48; Reel pack; SMD, 13", packing information 2 UM10204 I C-bus specification and user manual UM10569 Store and transport requirements All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 46 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 24 Revision history Table 25. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF8551 v.3.1 20210503 Product data sheet 202005038F01 PCF8551 v.3 Modifications: • Section 4: Added "Y" parts with improved package PCF8551 v.3 20210421 Modifications: • • • • PCF8551 v.2 20150216 Modifications: • Adjusted IDD and IDD(LCD) values in Table 17 • Switched to Product data sheet PCF8551 v.1 20141205 PCF8551 Product data sheet Product data sheet 202104033I PCF8551 v.2 Updated ordering information to new format Section 7.3: Added "See also application information..." Section 7.3.2: Added "The bus interface is initialized" Updated Section 15.1 Product data sheet Objective data sheet - PCF8551 v.1 - - All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 47 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver 25 Legal information 25.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. notice. This document supersedes and replaces all information supplied prior to the publication hereof. 25.2 Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 25.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without PCF8551 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 48 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP PCF8551 Product data sheet Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 25.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 2 I C-bus — logo is a trademark of NXP B.V. NXP — wordmark and logo are trademarks of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 49 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Tab. 6. Tab. 7. Tab. 8. Tab. 9. Tab. 10. Ordering Information ......................................... 2 Ordering options ................................................2 Pin description ...................................................5 Registers of the PCF8551 .................................6 Device_ctrl - device control command register (address 01h) bit description ................ 8 Display_ctrl_1 - display control command 1 register (address 02h) bit description ................ 8 Display_ctrl_2 - display control command 2 register (address 03h) bit description ................ 9 Software_reset - software reset command register (address 00h) bit description .............. 11 Register to segment and backplane mapping ...........................................................11 Selection of possible display configurations .... 14 Tab. 11. Tab. 12. Tab. 13. Tab. 14. Tab. 15. Tab. 16. Tab. 17. Tab. 18. Tab. 19. Tab. 20. Tab. 21. Tab. 22. Tab. 23. Tab. 24. Tab. 25. Biasing characteristics .....................................16 I2C slave address byte ................................... 28 R/W-bit description .......................................... 28 Serial interface ................................................ 28 Address byte definition ....................................28 Limiting values ................................................ 31 Electrical characteristics ..................................31 Frequency characteristics ............................... 34 I2C-bus characteristics ....................................35 SPI-bus characteristics ....................................36 SnPb eutectic process (from J-STD-020D) ..... 41 Lead-free process (from J-STD-020D) ............ 41 Selection of LCD segment drivers ...................44 Abbreviations ...................................................46 Revision history ...............................................47 Fig. 16. Recommended power-up and power-off sequence ......................................................... 25 I2C read and write protocol .............................25 I2C read and write signaling ........................... 26 Data transfer overview .................................... 28 SPI-bus write example: writing two data bytes to registers 00h and 01h ........................29 SPI-bus read example: reading two data bytes from registers 04h and 05h ....................30 Device protection diagram .............................. 30 Typical IDD and IDD(LCD) in power-down mode as function of temperature .................... 33 Typical IDD(LCD) as function of display load ..................................................................33 Typical IDD(LCD) as function of ffr ..................34 Relation of frame frequency (ffr), clock frequency (fclk) and multiplex-rate (nMUX) ..... 35 I2C-bus timing waveforms ...............................36 SPI-bus timing waveforms .............................. 37 Package outline SOT362-1 (TSSOP48) of PCF8551 ......................................................... 39 Temperature profiles for large and small components ..................................................... 42 Footprint information for reflow soldering of SOT362-1 (TSSOP48) of PCF8551 ................ 43 Figures Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. Fig. 6. Fig. 7. Fig. 8. Fig. 9. Fig. 10. Fig. 11. Fig. 12. Fig. 13. Fig. 14. Fig. 15. Block diagram of PCF8551A .............................3 Block diagram of PCF8551B .............................3 Pin configuration of PCF8551ATT (TSSOP48) ........................................................ 4 Pin configuration of PCF8551BTT (TSSOP48) ........................................................ 5 Address counter incrementing ...........................7 Display RAM organization bitmap for MUX 1:4 ................................................................... 13 Example of displays suitable for PCF8551 ...... 14 Typical system configuration using I2C-bus, internal power-on reset disabled ..................... 15 Typical system configuration using SPIbus, internal power-on reset enabled .............. 15 Electro-optical characteristic: relative transmission curve of the liquid .......................18 Static drive mode waveforms .......................... 19 Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias .................................................... 20 Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias .................................................... 21 Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias .................................................... 22 Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias .................................................... 23 PCF8551 Product data sheet Fig. 17. Fig. 18. Fig. 19. Fig. 20. Fig. 21. Fig. 22. Fig. 23. Fig. 24. Fig. 25. Fig. 26. Fig. 27. Fig. 28. Fig. 29. Fig. 30. Fig. 31. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 3 May 2021 © NXP B.V. 2021. All rights reserved. 50 / 51 PCF8551 NXP Semiconductors Universal 36 × 4 LCD segment driver Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.2.1 7.2.1.1 7.2.2 7.2.2.1 7.2.2.2 7.2.3 7.2.3.1 7.2.3.2 General description ............................................ 1 Features and benefits .........................................1 Applications .........................................................1 Ordering information .......................................... 2 Ordering options ................................................ 2 Block diagram ..................................................... 3 Pinning information ............................................ 4 Pinning ............................................................... 4 Pin description ................................................... 5 Functional description ........................................6 Registers of the PCF8551 ................................. 6 Command registers of the PCF8551 ................. 7 Command: Device_ctrl ...................................... 7 Internal oscillator and clock output .................... 8 Command: Display_ctrl_1 ..................................8 Enhanced power drive mode .............................9 Multiplex drive mode ......................................... 9 Command: Display_ctrl_2 ..................................9 Blinking ............................................................ 10 Line inversion (driving scheme A) and frame inversion (driving scheme B) ................. 10 7.3 Starting and resetting the PCF8551 ................ 10 7.3.1 Power-down mode ...........................................10 7.3.2 Power-On Reset (POR) ...................................10 7.3.3 Command: Software_reset .............................. 11 7.4 Display data register mapping ......................... 11 8 Possible display configurations ...................... 14 8.1 LCD bias generator ......................................... 15 8.2 LCD voltage selector ....................................... 16 8.2.1 Electro-optical performance ............................. 17 8.2.2 LCD drive mode waveforms ............................ 18 8.2.2.1 Static drive mode .............................................18 8.2.2.2 1:2 Multiplex drive mode ................................. 19 8.2.2.3 1:3 Multiplex drive mode ................................. 21 8.2.2.4 1:4 Multiplex drive mode ................................. 22 8.3 Backplane and segment outputs ..................... 23 8.3.1 Backplane outputs ........................................... 24 8.3.2 Segment outputs ............................................. 24 9 Power Sequencing ............................................ 24 9.1 Power-on ..........................................................24 9.2 Power-off ..........................................................24 9.3 Power sequences ............................................ 24 10 Bus interfaces ................................................... 25 10.1 I2C-bus interface of the PCF8551A .................25 10.1.1 Bit transfer ....................................................... 26 10.1.2 START and STOP conditions .......................... 26 10.1.3 Acknowledge ....................................................26 10.1.4 I2C interface protocol ...................................... 27 10.1.4.1 Write protocol ...................................................27 10.1.4.2 Read protocol .................................................. 27 10.1.4.3 I2C-bus slave address .....................................27 10.2 SPI-bus interface of the PCF8551B .................28 10.2.1 Data transmission ............................................ 28 10.2.1.1 Write protocol ...................................................29 10.2.1.2 Read protocol .................................................. 29 10.3 EMC detection ................................................. 30 11 Internal circuitry ................................................ 30 12 Safety notes .......................................................30 13 Limiting values .................................................. 31 14 Characteristics .................................................. 31 15 Application information .................................... 38 15.1 Power-on Reset ............................................... 38 15.2 I2C acknowledge after power-on ..................... 38 15.3 Resistors on I/O pins .......................................38 16 Package outline .................................................39 17 Handling information ........................................ 40 18 Packing information ..........................................40 18.1 Tape and reel information ................................40 19 Soldering of SMD packages .............................40 19.1 Introduction to soldering ............................. 19.2 Wave and reflow soldering ......................... 19.3 Wave soldering ........................................... 19.4 Reflow soldering ......................................... 20 Footprint information ........................................43 21 Appendix ............................................................ 44 21.1 LCD segment driver selection ......................... 44 22 Abbreviations .................................................... 46 23 References ......................................................... 46 24 Revision history ................................................ 47 25 Legal information .............................................. 48 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 May 2021 Document identifier: PCF8551