PCF8563TS/5

PCF8563 Real-time clock/calendar Rev. 10 — 3 April 2012 Product data sheet 1. General description The PCF8563 is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low power consumption. A programmable clock output, interrupt output, and voltage-low detector are also provided. All addresses and data are transferred serially via a two-line bidirectional I2C-bus. Maximum bus speed is 400 kbit/s. The register address is incremented automatically after each written or read data byte. 2. Features and benefits  Provides year, month, day, weekday, hours, minutes, and seconds based on a 32.768 kHz quartz crystal  Century flag  Clock operating voltage: 1.0 V to 5.5 V at room temperature  Low backup current; typical 0.25 A at VDD = 3.0 V and Tamb = 25 C  400 kHz two-wire I2C-bus interface (at VDD = 1.8 V to 5.5 V)  Programmable clock output for peripheral devices (32.768 kHz, 1.024 kHz, 32 Hz, and 1 Hz)  Alarm and timer functions  Integrated oscillator capacitor  Internal Power-On Reset (POR)  I2C-bus slave address: read A3h and write A2h  Open-drain interrupt pin 3. Applications     1. Mobile telephones Portable instruments Electronic metering Battery powered products The definition of the abbreviations and acronyms used in this data sheet can be found in Section 18. PCF8563 NXP Semiconductors Real-time clock/calendar 4. Ordering information Table 1. Ordering information Type number Package Name Description Version PCF8563BS/4 HVSON10 plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 3  3  0.85 mm SOT650-1 PCF8563P/F4 DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 PCF8563T/5 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 PCF8563T/F4[1] SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 PCF8563TS/4[2] TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 PCF8563TS/5 TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 [1] Not to be used for new designs. Replacement part is PCF8563T/5. [2] Not to be used for new designs. Replacement part is PCF8563TS/5. 5. Marking Table 2. Marking codes Type number PCF8563 Product data sheet Marking code PCF8563BS/4 8563S PCF8563P/F4 PCF8563P PCF8563T/5 PCF8563 PCF8563T/F4 8563T PCF8563TS/4 8563 PCF8563TS/5 P8563 All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 2 of 50 PCF8563 NXP Semiconductors Real-time clock/calendar 6. Block diagram OSCI OSCILLATOR 32.768 kHz DIVIDER CLOCK OUT CLKOUT OSCO CONTROL MONITOR (1) 00 CONTROL_STATUS_1 01 CONTROL_STATUS_2 0D CLKOUT_CONTROL 02 VL_SECONDS 03 MINUTES 04 HOURS POWER ON RESET TIME VDD VSS WATCH DOG 05 DAYS 06 WEEKDAYS 07 CENTURY_MONTHS 08 YEARS ALARM FUNCTION SDA SCL 09 MINUTE_ALARM 0A HOUR_ALARM I2C-BUS 0B DAY_ALARM INTERFACE 0C WEEKDAY_ALARM INT INTERRUPT TIMER FUNCTION PCF8563 0E TIMER_CONTROL 0F TIMER 001aah658 (1) COSCO; values see Table 30. Fig 1. Block diagram of PCF8563 PCF8563 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 3 of 50 PCF8563 NXP Semiconductors Real-time clock/calendar 7. Pinning information 7.1 Pinning terminal 1 index area OSCI 1 10 n.c. OSCO 2 9 VDD n.c. 3 8 CLKOUT INT 4 7 SCL VSS 5 6 SDA PCF8563BS OSCI 1 OSCO 2 Pin configuration for HVSON10 (PCF8563BS) OSCI 1 8 VDD OSCO 2 7 CLKOUT 3 6 SCL VSS 4 5 SDA INT 3 6 VSS 4 5 Top view. For mechanical details, see Figure 31. Fig 3. Pin configuration for DIP8 (PCF8563P) OSCI 1 8 VDD OSCO 2 7 CLKOUT SCL INT 3 6 SCL SDA VSS 4 5 SDA PCF8563T Top view. For mechanical details, see Figure 33. Top view. For mechanical details, see Figure 32. Pin configuration for SO8 (PCF8563T) Fig 5. All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 April 2012 PCF8563TS 001aaf976 001aaf975 Product data sheet CLKOUT 001aaf977 For mechanical details, see Figure 30. PCF8563 7 INT Transparent top view Fig 4. VDD PCF8563P 001aaf981 Fig 2. 8 Pin configuration for TSSOP8 (PCF8563TS) © NXP B.V. 2012. All rights reserved. 4 of 50 PCF8563 NXP Semiconductors Real-time clock/calendar 7.2 Pin description Table 3. Pin description Symbol Pin DIP8, SO8, TSSOP8 HVSON10 OSCI 1 1 oscillator input OSCO 2 2 oscillator output INT 3 4 interrupt output (open-drain; active LOW) VSS 4 5[1] ground SDA 5 6 serial data input and output SCL 6 7 serial clock input CLKOUT 7 8 clock output, open-drain VDD 8 9 supply voltage n.c. - 3, 10 not connected; do not connect and do not use as feed through [1] PCF8563 Product data sheet Description The die paddle (exposed pad) is wired to VSS but should not be electrically connected. All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 5 of 50 PCF8563 NXP Semiconductors Real-time clock/calendar 8. Functional description The PCF8563 contains sixteen 8-bit registers with an auto-incrementing register address, an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which provides the source clock for the Real-Time Clock (RTC) and calender, a programmable clock output, a timer, an alarm, a voltage-low detector, and a 400 kHz I2C-bus interface. All 16 registers are designed as addressable 8-bit parallel registers although not all bits are implemented. The first two registers (memory address 00h and 01h) are used as control and/or status registers. The memory addresses 02h through 08h are used as counters for the clock function (seconds up to years counters). Address locations 09h through 0Ch contain alarm registers which define the conditions for an alarm. Address 0Dh controls the CLKOUT output frequency. 0Eh and 0Fh are the Timer_control and Timer registers, respectively. The Seconds, Minutes, Hours, Days, Months, Years as well as the Minute_alarm, Hour_alarm, and Day_alarm registers are all coded in Binary Coded Decimal (BCD) format. When one of the RTC registers is written or read, the contents of all time counters are frozen. Therefore, faulty writing or reading of the clock and calendar during a carry condition is prevented. 8.1 CLKOUT output A programmable square wave is available at the CLKOUT pin. Operation is controlled by the register CLKOUT_control at address 0Dh. Frequencies of 32.768 kHz (default), 1.024 kHz, 32 Hz, and 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain output and enabled at power-on. If disabled it becomes high-impedance. PCF8563 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 6 of 50 PCF8563 NXP Semiconductors Real-time clock/calendar 8.2 Register organization Table 4. Formatted registers overview Bit positions labelled as x are not relevant. Bit positions labelled with N should always be written with logic 0; if read they could be either logic 0 or logic 1. After reset, all registers are set according to Table 27. Address Register name Bit 7 6 5 4 3 2 1 0 Control and status registers 00h Control_status_1 TEST1 N STOP N TESTC N N N 01h Control_status_2 N N N TI_TP AF TF AIE TIE x WEEKDAYS (0 to 6) Time and date registers 02h VL_seconds VL SECONDS (0 to 59) 03h Minutes x MINUTES (0 to 59) 04h Hours x x HOURS (0 to 23) 05h Days x x DAYS (1 to 31) 06h Weekdays x x x x 07h Century_months C x x MONTHS (1 to 12) 08h Years YEARS (0 to 99) Alarm registers 09h Minute_alarm AE_M MINUTE_ALARM (0 to 59) 0Ah Hour_alarm AE_H x HOUR_ALARM (0 to 23) 0Bh Day_alarm AE_D x DAY_ALARM (1 to 31) 0Ch Weekday_alarm AE_W x x x x WEEKDAY_ALARM (0 to 6) FE x x x x x FD[1:0] x x x x x TD[1:0] CLKOUT control register 0Dh CLKOUT_control Timer registers 0Eh Timer_control TE 0Fh Timer TIMER[7:0] PCF8563 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 7 of 50 PCF8563 NXP Semiconductors Real-time clock/calendar 8.3 Control registers 8.3.1 Register Control_status_1 Table 5. Bit 7 Control_status_1 - control and status register 1 (address 00h) bit description Symbol Value Description Reference TEST1 0[1] normal mode Section 8.9 must be set to logic 0 during normal operations 6 5 1 EXT_CLK test mode N 0[2] unused STOP 0[1] RTC source clock runs 1 all RTC divider chain flip-flops are asynchronously set to logic 0; the RTC clock is stopped (CLKOUT at 32.768 kHz is still available) 4 N 0[2] unused 3 TESTC 0 Power-On Reset (POR) override facility is disabled; set to logic 0 for normal operation 1[1] Power-On Reset (POR) override may be enabled 000[2] unused 2 to 0 N [1] Default value. [2] Bits labeled as N should always be written with logic 0. Section 8.10 Section 8.11.1 8.3.2 Register Control_status_2 Table 6. Bit 7 to 5 4 Control_status_2 - control and status register 2 (address 01h) bit description Symbol Value Description N 000[1] Reference unused TI_TP 0[2] INT is active when TF is active (subject to the status of TIE) 1 INT pulses active according to Table 7 (subject to the status of TIE); Remark: note that if AF and AIE are active then INT will be permanently active 3 AF 0[2] read: alarm flag inactive Section 8.3.2.1 and Section 8.8 Section 8.3.2.1 write: alarm flag is cleared 1 read: alarm flag active write: alarm flag remains unchanged 2 TF 0[2] read: timer flag inactive write: timer flag is cleared 1 read: timer flag active write: timer flag remains unchanged 1 AIE 0 TIE 0[2] alarm interrupt disabled 1 alarm interrupt enabled 0[2] timer interrupt disabled 1 timer interrupt enabled [1] Bits labeled as N should always be written with logic 0. [2] Default value. PCF8563 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 8 of 50 PCF8563 NXP Semiconductors Real-time clock/calendar 8.3.2.1 Interrupt output Bits TF and AF: When an alarm occurs, AF is set to logic 1. Similarly, at the end of a timer countdown, TF is set to logic 1. These bits maintain their value until overwritten using the interface. If both timer and alarm interrupts are required in the application, the source of the interrupt can be determined by reading these bits. To prevent one flag being overwritten while clearing another, a logic AND is performed during a write access. TI_TP TE to interface: read TF TF: TIMER COUNTDOWN COUNTER SET TIE e.g. AIE 0 1 0 PULSE GENERATOR 2 TRIGGER CLEAR 1 CLEAR INT from interface: clear TF to interface: read AF AF: ALARM FLAG SET set alarm flag AF AIE CLEAR from interface: clear AF 013aaa087 When bits TIE and AIE are disabled, pin INT will remain high-impedance. Fig 6. Interrupt scheme Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when TF or AF is asserted, respectively. The interrupt is the logical OR of these two conditions when both AIE and TIE are set. Countdown timer interrupts: The pulse generator for the countdown timer interrupt uses an internal clock and is dependent on the selected source clock for the countdown timer and on the countdown value n. As a consequence, the width of the interrupt pulse varies (see Table 7). Table 7. INT operation (bit TI_TP = 1)[1] Source clock (Hz) PCF8563 Product data sheet INT period (s) n = 1[2] n > 1[2] 4096 1⁄ 8192 1⁄ 4096 64 1⁄ 128 1⁄ 64 1 1⁄ 64 1⁄ 64 1⁄ 60 1⁄ 64 1⁄ 64 [1] TF and INT become active simultaneously. [2] n = loaded countdown value. Timer stops when n = 0. All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 9 of 50 PCF8563 NXP Semiconductors Real-time clock/calendar 8.4 Time and date registers The majority of the registers are coded in the BCD format to simplify application use. 8.4.1 Register VL_seconds Table 8. VL_seconds - seconds and clock integrity status register (address 02h) bit description Bit Symbol Value Place value Description 7 VL 0 - clock integrity is guaranteed 1[1] - integrity of the clock information is not guaranteed 6 to 4 SECONDS 0 to 5 ten’s place actual seconds coded in BCD format, see Table 9 3 to 0 unit place [1] Start-up value. Table 9. 8.4.1.1 0 to 9 Seconds coded in BCD format Seconds value (decimal) Upper-digit (ten’s place) Digit (unit place) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0 0 0 0 0 0 0 01 0 0 0 0 0 0 1 02 0 0 0 0 0 1 0 : : : : : : : : 09 0 0 0 1 0 0 1 10 0 0 1 0 0 0 0 : : : : : : : : 58 1 0 1 1 0 0 0 59 1 0 1 1 0 0 1 Voltage-low detector and clock monitor The PCF8563 has an on-chip voltage-low detector (see Figure 7). When VDD drops below Vlow, bit VL in the VL_seconds register is set to indicate that the integrity of the clock information is no longer guaranteed. The VL flag can only be cleared by using the interface. mgr887 VDD normal power operation period of battery operation Vlow VL set Fig 7. PCF8563 Product data sheet t Voltage-low detection All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 10 of 50 PCF8563 NXP Semiconductors Real-time clock/calendar The VL flag is intended to detect the situation when VDD is decreasing slowly, for example under battery operation. Should the oscillator stop or VDD reach Vlow before power is re-asserted, then the VL flag is set. This will indicate that the time may be corrupted. 8.4.2 Register Minutes Table 10. Minutes - minutes register (address 03h) bit description Bit Symbol Value Place value Description 7 - - - unused actual minutes coded in BCD format 6 to 4 MINUTES 0 to 5 ten’s place 3 to 0 0 to 9 unit place 8.4.3 Register Hours Table 11. Bit Hours - hours register (address 04h) bit description Value Place value Description 7 to 6 - Symbol - - unused 5 to 4 HOURS 0 to 2 ten’s place actual hours coded in BCD format 3 to 0 0 to 9 unit place 8.4.4 Register Days Table 12. Bit Days - days register (address 05h) bit description Value Place value Description 7 to 6 - - - unused 5 to 4 DAYS[1] 0 to 3 ten’s place actual day coded in BCD format 3 to 0 0 to 9 unit place [1] Symbol The PCF8563 compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year 00. 8.4.5 Register Weekdays Table 13. Bit PCF8563 Product data sheet Weekdays - weekdays register (address 06h) bit description Symbol Value Description 7 to 3 - - unused 2 to 0 WEEKDAYS 0 to 6 actual weekday values, see Table 14 All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 11 of 50 PCF8563 NXP Semiconductors Real-time clock/calendar Table 14. Weekday assignments Day[1] Bit 2 1 0 Sunday 0 0 0 Monday 0 0 1 Tuesday 0 1 0 Wednesday 0 1 1 Thursday 1 0 0 Friday 1 0 1 Saturday 1 1 0 [1] Definition may be re-assigned by the user. 8.4.6 Register Century_months Table 15. Century_months - century flag and months register (address 07h) bit description Bit Symbol Value Place value Description 7 C[1] 0[2] - indicates the century is x 1 - indicates the century is x + 1 6 to 5 - - - unused 4 0 to 1 ten’s place actual month coded in BCD format, see Table 16 0 to 9 unit place MONTHS 3 to 0 [1] This bit may be re-assigned by the user. [2] This bit is toggled when the register Years overflows from 99 to 00. Table 16. Month PCF8563 Product data sheet Month assignments in BCD format Upper-digit (ten’s place) Digit (unit place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 January 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April 0 0 1 0 0 May 0 0 1 0 1 June 0 0 1 1 0 July 0 0 1 1 1 August 0 1 0 0 0 September 0 1 0 0 1 October 1 0 0 0 0 November 1 0 0 0 1 December 1 0 0 1 0 All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 12 of 50 PCF8563 NXP Semiconductors Real-time clock/calendar 8.4.7 Register Years Table 17. Bit Years - years register (08h) bit description Symbol Value Place value Description 7 to 4 YEARS 0 to 9 ten’s place 3 to 0 0 to 9 unit place [1] actual year coded in BCD format[1] When the register Years overflows from 99 to 00, the century bit C in the register Century_months is toggled. 8.5 Setting and reading the time Figure 8 shows the data flow and data dependencies starting from the 1 Hz clock tick. 1 Hz tick SECONDS MINUTES HOURS LEAP YEAR CALCULATION DAYS WEEKDAY MONTHS YEARS C Fig 8. 013aaa092 Data flow for the time function During read/write operations, the time counting circuits (memory locations 02h through 08h) are blocked. This prevents • Faulty reading of the clock and calendar during a carry condition • Incrementing the time registers, during the read cycle After this read/write access is completed, the time circuit is released again and any pending request to increment the time counters that occurred during the read access is serviced. A maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see Figure 9). PCF8563 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 April 2012 © NXP B.V. 2012. All rights reserved. 13 of 50 PCF8563 NXP Semiconductors Real-time clock/calendar t