PCKEL14D

PCKEL14 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip Rev. 01 — 14 October 2002 Product data 1. Description The PCKEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL, or if positive power supplies are used, PECL input signal. The PCKEL14 is designed to operate in ECL or PECL mode for a voltage supply range of −2.375 V to −3.8 V (or 2.375 V to 3.8 V). The PCKEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor), the SEL pin will select the differential clock input. The common enable (EN) is synchronous, so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled, as can happen with an asynchronous control. The internal flip-flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. The VBB pin (an internally generated voltage supply) is available to this device only. For single-ended conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC-coupled inputs. When used, decouple VBB and VCC via a 0.01 µF capacitor and limit current sourcing or sinking to 0.1 mA. When not used, VBB should be left open. 2. Features s s s s s s s s s s s s 50 ps output-to-output skew at 3.3 V Synchronous enable/disable Multiplexed clock input ESD protection: > 2.5 kV HBM The PCK series contains temperature compensation PECL mode operating range: VCC = 2.375 V to 3.8 V, with VEE = 0 V NECL mode operating range: VCC = 0 V, with VEE = −2.375 V to −3.8 V Internal 75 kΩ pull-down resistors on all inputs, plus a 37.5 kΩ pull-up on CLK Q output will default LOW with inputs open or at VEE Meets or exceeds JEDEC spec EIA/JESD78 IC latch-up test Moisture sensitivity level 1 Flammability rating: UL-94 code V-0 @ 1/8” Philips Semiconductors PCKEL14 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip 3. Pinning information 3.1 Pinning Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 1 2 3 4 20 VCC 19 EN 18 VCC 17 NC Q0 1 Q0 2 Q1 3 20 VCC 19 EN 18 VCC PCKEL14PW Q1 4 Q2 5 Q2 6 Q3 7 Q3 8 Q4 9 Q4 10 17 NC 16 SCLK 15 CLK 14 CLK 13 VBB 12 SEL 11 VEE PCKEL14D 5 6 7 8 9 16 SCLK 15 CLK 14 CLK 13 VBB 12 SEL 11 VEE Q4 10 002aaa217 002aaa353 Fig 1. SO20 pin configuration. Fig 2. TSSOP pin configuration. 3.2 Pin description Table 1: Symbol Q0-Q4 Q0-Q4 VEE SEL VBB CLK CLK SCLK NC EN VCC Pin description Pin 1, 3, 5, 7, 9 2, 4, 6, 8, 10 11 12 13 14 15 16 17 19 18, 20 Description ECL differential clock outputs, non-inverted ECL differential clock outputs, inverted negative supply voltage ECL clock select input reference voltage output ECL differential clock input, inverted ECL differential clock input, non-inverted ECL scan clock input no connect ECL synchronous enable, Active-LOW positive supply voltage 3.2.1 Power supply connection CAUTION All VCC and VEE pins must be connected to an appropriate power supply to guarantee proper operation. MSC895 9397 750 09564 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 14 October 2002 2 of 15 Philips Semiconductors PCKEL14 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip 4. Ordering information Table 2: Ordering information Package Name PCKEL14D PCKEL14PW SO20 TSSOP20 Description plastic small outline package; 20 leads; body width 7.5 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm Version SOT163-1 SOT360-1 Type number 5. Logic diagram 1 2 19 Q0 Q0 EN Q1 Q1 3 4 Q D Q2 Q2 5 6 16 15 1 SCLK CLK Q3 Q3 7 8 0 14 CLK 13 12 VBB SEL Q4 Q4 9 10 002aaa218 Fig 3. Logic diagram. CAUTION All VCC and VEE pins must be connected to an appropriate power supply to guarantee proper operation. MSC895 6. Function table Table 3: Function table X = Don’t care. CLK L H X X X [1] 9397 750 09564 SCLK X X L H X SEL L L H H X EN L L L L H Q L H L H L[1] On next negative transition of CLK or SCLK. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 14 October 2002 3 of 15 Philips Semiconductors PCKEL14 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip 7. Limiting values Table 4: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VEE VI Parameter power supply power supply input voltage Conditions PECL mode; VEE = 0 V NECL mode; VCC = 0 V PECL mode; VEE = 0 V; VI ≤ VCC NECL mode; VCC = 0 V; VI ≥ VEE Io IBB Tamb Tstg Rth(j-a) Rth(j-c) Tsld ESDHBM ESDMM ESCCDM [1] Min 0 0 0 0 −0.1 −40 −65 Max 4.1 −4.1 4.1 −4.1 50 100 +0.1 +85 +150 90 60 35 265 >2.50 >100 >1000 Unit V V V V mA mA mA °C °C °C/W °C/W °C/W °C kV V V output current VBB sink/source ambient temperature storage temperature thermal resistance from junction to ambient thermal resistance from junction to case soldering temperature electrostatic discharge electrostatic discharge electrostatic discharge continuous surge 0 LFPM 500 LFPM std bd < 2 to 3 sec @ 248 °C Human Body Model; 1.5 kΩ; 100 pF Machine Model; 0 kΩ; 200 pF Charge Device Model 30 - Maximum ratings are those values beyond which device damage may occur. 9397 750 09564 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 14 October 2002 4 of 15 Philips Semiconductors PCKEL14 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip 8. Static characteristics Table 5: PECL DC characteristics[1] VCC = 2.5 V; VEE = 0 V [2] Symbol IEE VOH VOL VIH VIL VBB VIHCMR Parameter power supply current HIGH-level output voltage LOW-level output voltage HIGH-level input voltage output voltage reference HIGH-level input voltage, common mode range (differential) HIGH-level input current LOW-level input current CLK CLK [1] [2] [3] [4] [5] [5] [3] Conditions - Tamb = −40 °C Min Typ 28 Max 40 - Tamb = +25 °C Min Typ 30 Max 40 - Tamb = +85 °C Min Typ 31 Max 42 Unit mA 1325 1460 1620 1435 1545 1620 1475 1545 1620 mV 670 805 945 690 795 880 690 795 880 mV [3] single-ended [4] 1310 690 1.07 1.2 - 1620 1335 1025 690 1.25 2.1 1.15 1.2 - 1620 1335 1025 690 1.25 2.1 1.15 1.2 - 1620 mV 1025 mV 1.31 2.1 V V LOW-level input voltage single-ended [4] IIH IIL 0.5 - 150 - 0.5 - 150 - 0.5 - 150 - µA µA µA −300 - −300 - −300 - Devices are designed to meet the DC specifications shown in this table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −1.3 V. All loading with 50 Ω to VCC − 2 V. Do not use VBB at VCC < 3.0 V. VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 9397 750 09564 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 14 October 2002 5 of 15 Philips Semiconductors PCKEL14 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip Table 6: Positive DC characteristics[1] VCC = 3.3 V; VEE = 0 V [2] Symbol IEE VOH VOL VIH VIL VBB VIHCMR Parameter power supply current HIGH-level output voltage LOW-level output voltage HIGH-level input voltage LOW-level input voltage output voltage reference HIGH-level input voltage, common mode range (differential) HIGH-level input current LOW-level input current CLK others Vp-p < 500 mV Vp-p ≥ 500 mV [4] [3] Conditions - Tamb = −40 °C Min Typ 32 Max 40 - Tamb = +25 °C Min Typ 32 Max 40 - Tamb = +85 °C Min Typ 34 Max 42 Unit mA 2125 2260 2420 2235 2345 2420 2275 2345 2420 mV 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV 2110 1490 1.87 1.3 1.5 2420 2135 1825 1490 2.05 2.9 2.9 1.95 1.2 1.4 2420 2135 1825 1490 2.05 2.9 2.9 1.95 1.2 1.4 2420 mV 1825 mV 2.11 2.9 2.9 V V V [3] single-ended single-ended IIH IIL - - 150 - - - 150 - - - 150 - µA µA µA −300 0.5 - −300 0.5 - −300 0.5 - [1] [2] [3] [4] Devices are designed to meet the DC specifications shown in this table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. Outputs are terminated through a 50 Ω resistor to VCC − 2V. VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between Vp-p(min) and 1 V. 9397 750 09564 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 14 October 2002 6 of 15 Philips Semiconductors PCKEL14 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip Table 7: Negative DC characteristics[1] VCC = 0.0 V; VEE = − 3.8 V to −2.375 V[2] Symbol Parameter IEE VOH VOL VIH VIL VBB VIHCMR power supply current HIGH-level output voltage LOW-level output voltage HIGH-level input single-ended voltage LOW-level input voltage output voltage reference HIGH-level input Vp-p < 500 mV voltage, Vp-p ≥ 500 mV common mode range (differential) HIGH-level input current LOW-level input current CLK others [4] [3] Conditions - Tamb = −40 °C Min Typ 32 Max 40 - Tamb = +25 °C Min Typ 32 Max 40 −880 - Tamb = +85 °C Min Typ 34 Max 42 −880 Unit mA mV −1175 −1040 −880 −1065 −955 −1025 −955 [3] −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV −1190 −1810 −1.43 −2.0 −1.8 −880 −1165 −880 −1165 −880 mV single-ended −1475 −1810 −1.25 −1.35 −0.4 −0.4 −2.1 −1.9 - −1475 −1810 −1.25 −1.35 −0.4 −0.4 −2.1 −1.9 - −1475 mV −1.19 V −0.4 −0.4 V V IIH IIL −300 0.5 - 150 - −300 0.5 - 150 - −300 0.5 - 150 - µA µA µA [1] [2] [3] [4] Devices are designed to meet the DC specifications shown in this table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. Outputs are terminated through a 50 Ω resistor to VCC − 2 V. VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between Vp-p(min) and 1 V. 9397 750 09564 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 — 14 October 2002 7 of 15 Philips Semiconductors PCKEL14 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip 9. Dynamic characteristics Table 8: AC characteristics (VCC = 2.375 V to 3.8 V; VEE = 0 V) or (VCC = 0 V; VEE = −2.375 V to −3.8 V) [1] Symbol fmax tPLH Parameter maximum toggle frequency LOW-to-HIGH propagation delay Conditions see Figure 4 CLK to Q (diff); 3.3 V CLK to Q (diff); 2.5 V tPHL tSKEW HIGH-to-LOW propagation delay skew time CLK to Q (SE) SCLK to Q part-to-part within-device; 3.3 V within-device; 2.5 V tJITTER tsu th Vi(p-p) tr/tf cycle-to cycle jitter EN set-up time EN hold time input swing CLK output rise/fall times Q pins (20% - 80%); 3.3 V Q pins (20% - 80%); 2.5 V [1] [2] [3] [3] [2] Tamb = −40 °C Min 400 400 330 330 0 0 150 230 Typ >1 0.2 Max 720 800 770 770 200 50 70 1 680 680 0.2 Max 780 940 830 830 200 50 70 1 0.2 Max 830 970 880 880 200 50 70