PCU9956ATWY

PCU9956A 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver Rev. 2 — 29 June 2015 Product data sheet 1. General description The PCU9956A is an Ultra Fast-mode (UFm) I2C-bus controlled 24-channel constant current LED driver optimized for dimming and blinking 57 mA Red/Green/Blue/Amber (RGBA) LEDs in amusement products. Each LED output has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller that operates at 31.25 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set to a specific brightness value. An additional 8-bit resolution (256 steps) group PWM controller has both a fixed frequency of 122 Hz and an adjustable frequency between 15 Hz to once every 16.8 seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to either dim or blink all LEDs with the same value. Each LED output can be off, on (no PWM control), set at its individual PWM controller value or at both individual and group PWM controller values. The PCU9956A operates with a supply voltage range of 3 V to 5.5 V and the constant current sink LED outputs allow up to 20 V for the LED supply. The output peak current is adjustable with an 8-bit linear DAC from 225 A to 57 mA. A thermal shutdown feature protects the device when internal junction temperature exceeds the limit allowed for the process. The PCU9956A device is the first LED controller device in a new Ultra Fast-mode (UFm) I2C-bus family. UFm I2C-bus devices offer higher frequency (up to 5 MHz). the UFm I2C-bus slave devices operate in receive-only mode. That is, only I2C writes to PCU9956A are supported. As such, there are no status registers in PCU9956A. The PCU9956A allows significantly higher data transfer rate compared to the Fast-mode Plus version (PCA9956A). The active LOW output enable input pin (OE) blinks all the LED outputs and can be used to externally PWM the outputs, which is useful when multiple devices need to be dimmed or blinked together without using software control. Software programmable LED Group and three Sub Call I2C-bus addresses allow all or defined groups of PCU9956A devices to respond to a common I2C-bus address, allowing for example, all red LEDs to be turned on or off at the same time or marquee chasing effect, thus minimizing I2C-bus commands. On power-up, PCU9956A will have a unique Sub Call address to identify it as a 24-channel LED driver. This allows mixing of devices with different channel widths. Three hardware address pins on PCU9956A allow up to 125 devices on the same bus. PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver The Software Reset (SWRST) function allows the master to perform a reset of the PCU9956A through the I2C-bus, identical to the Power-On Reset (POR) that initializes the registers to their default state causing the output current switches to be OFF (LED off). This allows an easy and quick way to reconfigure all device registers to the same condition. 2. Features and benefits  24 LED drivers. Each output programmable at:  Off  On  Programmable LED brightness  Programmable group dimming/blinking mixed with individual LED brightness  Programmable LED output delay to reduce EMI and surge currents  24 constant current output channels can sink up to 57 mA, tolerate up to 20 V when OFF  Output current adjusted through an external resistor (REXT input)  Output current accuracy  4 % between output channels  6 % between PCU9956A devices  Thermal shut-down for overtemperature  5 MHz Ultra Fast-mode I2C-bus interface  256-step (8-bit) linear programmable brightness per LED output varying from fully off (default) to maximum brightness using a 31.25 kHz PWM signal  256-step group brightness control allows general dimming (using a 122 Hz PWM signal) from fully off to maximum brightness (default)  256-step group blinking with frequency programmable from 15 Hz to 16.8 s and duty cycle from 0 % to 99.6 %  Output state change programmable on the Acknowledge (bit 9, this bit is always set to 1 by I2C-bus master) or the STOP Command to update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).  Active LOW Output Enable (OE) input pin allows for hardware blinking and dimming of the LEDs  Three quinary hardware address pins allow 125 PCU9956A devices to be connected to the same I2C-bus and to be individually programmed  4 software programmable I2C-bus addresses (one LED Group Call address and three LED Sub Call addresses) allow groups of devices to be addressed at the same time in any combination (for example, one register used for ‘All Call’ so that all the PCU9956As on the I2C-bus can be addressed at the same time and the second register used for three different addresses so that 1⁄3 of all devices on the bus can be addressed at the same time in a group). Software enable and disable for each programmable I2C-bus address.  Unique power-up default Sub Call address allows mixing of devices with different channel widths  Software Reset feature (SWRST Call) allows the device to be reset through the I2C-bus  8 MHz internal oscillator requires no external components PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 2 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver           Internal power-on reset Noise filter on USDA/USCL inputs No glitch on LED outputs on power-up Low standby current Operating power supply voltage (VDD) range of 3 V to 5.5 V 5.5 V tolerant inputs on non-LED pins 40 C to +85 C operation ESD protection exceeds 3000 V HBM per JESD22-A114 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: HTSSOP38 3. Applications       Amusement products RGB or RGBA LED drivers LED status information LED displays LCD backlights Keypad backlights for cellular phones or handheld devices 4. Ordering information Table 1. Ordering information Type number PCU9956ATW Topside mark PCU9956ATW Package Name Description Version HTSSOP38 plastic thermal enhanced thin shrink small outline package; SOT1331-1 38 leads; body width 4.4 mm; lead pitch 0.5 mm; exposed die pad 4.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method Minimum order quantity Temperature PCU9956ATW PCU9956ATWY HTSSOP38 Reel 13” Q1/T1 *standard mark SMD dry pack 2500 Tamb = 40 C to +85 C PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 3 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 5. Block diagram AD0 AD1 AD2 REXT LED0 LED1 LED22 LED23 I/O REGULATOR PCU9956A DAC0 USCL INPUT FILTER DAC1 USDA I2C-BUS CONTROL individual LED current setting 8-bit DACs DAC 22 DAC 23 POWER-ON RESET VDD OUTPUT DRIVER, DELAY CONTROL AND THERMAL SHUTDOWN 200 kΩ VSS INPUT FILTER RESET LED STATE SELECT REGISTER PWM REGISTER X BRIGHTNESS CONTROL ÷ 256 31.25 kHz 8 MHz OSCILLATOR GRPFREQ REGISTER MUX/ CONTROL GRPPWM REGISTER DIM CLOCK '0' – permanently OFF '1' – permanently ON OE 002aag458 Dim repetition rate = 122 Hz. Blink repetition rate = 15 Hz to every 16.8 seconds. Fig 1. Block diagram of PCU9956A PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 4 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 6. Pinning information 6.1 Pinning REXT 1 38 VDD AD0 2 37 USDA AD1 3 36 USCL AD2 4 35 RESET OE 5 34 VSS LED0 6 33 LED23 LED1 7 32 LED22 LED2 8 31 LED21 LED3 9 30 LED20 PCU9956ATW LED4 10 29 LED19 LED5 11 28 LED18 LED6 12 27 LED17 LED7 13 26 LED16 VSS 14 25 VSS LED8 15 24 LED15 LED9 16 23 LED14 LED10 17 22 LED13 VSS 18 21 VSS LED11 19 20 LED12 (1) Transparant top view 002aag459 (1) Thermal pad; connected to VSS. Fig 2. PCU9956A Product data sheet Pin configuration for HTSSOP38 All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 5 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 6.2 Pin description Table 3. Pin Type Description REXT 1 I current set resistor input; resistor to ground AD0 2 I address input 0 AD1 3 I address input 1 AD2 4 I address input 2 OE 5 I active LOW output enable for LEDs LED0 6 O LED driver 0 LED1 7 O LED driver 1 LED2 8 O LED driver 2 LED3 9 O LED driver 3 LED4 10 O LED driver 4 LED5 11 O LED driver 5 LED6 12 O LED driver 6 LED7 13 O LED driver 7 LED8 15 O LED driver 8 LED9 16 O LED driver 9 LED10 17 O LED driver 10 LED11 19 O LED driver 11 LED12 20 O LED driver 12 LED13 22 O LED driver 13 LED14 23 O LED driver 14 LED15 24 O LED driver 15 LED16 26 O LED driver 16 LED17 27 O LED driver 17 LED18 28 O LED driver 18 LED19 29 O LED driver 19 LED20 30 O LED driver 20 LED21 31 O LED driver 21 LED22 32 O LED driver 22 LED23 33 O LED driver 23 RESET 35 I active LOW reset input USCL 36 I UFm serial clock line USDA 37 I UFm serial data line VSS 14, 18, 21, 25, 34[1] ground supply ground VDD 38 power supply supply voltage [1] PCU9956A Product data sheet Pin description Symbol HTSSOP38 package supply ground is connected to both VSS pins and exposed center pad. VSS pins must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 6 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 7. Functional description Refer to Figure 1 “Block diagram of PCU9956A”. 7.1 Device addresses Following a START condition, the bus master must output the address of the slave it is accessing. For PCU9956A there are a maximum of 125 possible programmable addresses using the three quinary hardware address pins. 7.1.1 Regular I2C-bus slave address The I2C-bus slave address of the PCU9956A is shown in Figure 3. The 7-bit slave address is determined by the quinary input pads AD0, AD1 and AD2. Each pad can have one of five states (GND, pull-up, floating, pull-down, and VDD) based on how the input pad is connected on the board. At power-up or hardware/software reset, the quinary input pads are sampled and set the slave address of the device internally. To conserve power, once the slave address is determined, the quinary input pads are turned off and will not be sampled until the next time the device is power cycled. Table 4 lists the five possible connections for the quinary input pads along with the external resistor values that must be used. Table 4. Quinary input pad connection Pad connection (pins AD2, AD1, AD0)[1] Mnemonic Min. Max. tie to ground GND 0 17.9 resistor pull-down to ground PD 34.8 270 open (floating) FLT 503  resistor pull-up to VDD PU 31.7 340 tie to VDD VDD 0 22.1 [1] External resistor (k) These AD[2:0] inputs must be stable before the supply VDD to chip. Table 5 lists all 125 possible slave addresses of the device based on all combinations of the five states connected to three address input pins AD0, AD1 and AD2. Table 5. Hardware selectable input pins I2C-bus slave address for PCU9956A AD2 Decimal AD0 Hex Binary (A[6:0]) Address (R/W = 0) 02h GND GND GND 1 01 GND GND PD 2 02 0000010[1] 04h 03 0000011[1] 06h 04 0000100[1] 08h 0Ah GND Product data sheet AD1 0000001[1] GND PCU9956A I2C-bus slave address GND GND FLT PU 3 4 GND GND VDD 5 05 0000101[1] GND PD GND 6 06 0000110[1] 0Ch 0Eh GND PD PD 7 07 0000111[1] GND PD FLT 8 08 0001000 10h GND PD PU 9 09 0001001 12h All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 7 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver Table 5. PCU9956A Product data sheet I2C-bus slave address …continued Hardware selectable input pins I2C-bus slave address for PCU9956A AD2 AD1 AD0 Decimal Hex Binary (A[6:0]) Address (R/W = 0) GND PD VDD 10 0A 0001010 14h GND FLT GND 11 0B 0001011 16h GND FLT PD 12 0C 0001100 18h GND FLT FLT 13 0D 0001101 1Ah GND FLT PU 14 0E 0001110 1Ch GND FLT VDD 15 0F 0001111 1Eh GND PU GND 16 10 0010000 20h GND PU PD 17 11 0010001 22h GND PU FLT 18 12 0010010 24h GND PU PU 19 13 0010011 26h GND PU VDD 20 14 0010100 28h GND VDD GND 21 15 0010101 2Ah GND VDD PD 22 16 0010110 2Ch GND VDD FLT 23 17 0010111 2Eh GND VDD PU 24 18 0011000 30h GND VDD VDD 25 19 0011001 32h PD GND GND 26 1A 0011010 34h PD GND PD 27 1B 0011011 36h PD GND FLT 28 1C 0011100 38h PD GND PU 29 1D 0011101 3Ah PD GND VDD 30 1E 0011110 3Ch PD PD GND 31 1F 0011111 3Eh PD PD PD 32 20 0100000 40h PD PD FLT 33 21 0100001 42h PD PD PU 34 22 0100010 44h PD PD VDD 35 23 0100011 46h PD FLT GND 36 24 0100100 48h PD FLT PD 37 25 0100101 4Ah PD FLT FLT 38 26 0100110 4Ch PD FLT PU 39 27 0100111 4Eh PD FLT VDD 40 28 0101000 50h PD PU GND 41 29 0101001 52h PD PU PD 42 2A 0101010 54h PD PU FLT 43 2B 0101011 56h PD PU PU 44 2C 0101100 58h PD PU VDD 45 2D 0101101 5Ah All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 8 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver Table 5. PCU9956A Product data sheet I2C-bus slave address …continued Hardware selectable input pins I2C-bus slave address for PCU9956A AD2 AD1 AD0 Decimal Hex Binary (A[6:0]) Address (R/W = 0) PD VDD GND 46 2E 0101110 5Ch PD VDD PD 47 2F 0101111 5Eh PD VDD FLT 48 30 0110000 60h PD VDD PU 49 31 0110001 62h PD VDD VDD 50 32 0110010 64h FLT GND GND 51 33 0110011 66h FLT GND PD 52 34 0110100 68h FLT GND FLT 53 35 0110101 6Ah FLT GND PU 54 36 0110110 6Ch FLT GND VDD 55 37 0110111 6Eh FLT PD GND 56 38 0111000 70h FLT PD PD 57 39 0111001 72h FLT PD FLT 58 3A 0111010 74h FLT PD PU 59 3B 0111011 76h FLT PD VDD 60 3C 0111100 78h FLT FLT GND 61 3D 0111101 7Ah FLT FLT PD 62 3E 0111110 7Ch FLT FLT FLT 63 3F 0111111 7Eh FLT FLT PU 64 40 1000000 80h FLT FLT VDD 65 41 1000001 82h FLT PU GND 66 42 1000010 84h FLT PU PD 67 43 1000011 86h FLT PU FLT 68 44 1000100 88h FLT PU PU 69 45 1000101 8Ah FLT PU VDD 70 46 1000110 8Ch FLT VDD GND 71 47 1000111 8Eh FLT VDD PD 72 48 1001000 90h FLT VDD FLT 73 49 1001001 92h FLT VDD PU 74 4A 1001010 94h FLT VDD VDD 75 4B 1001011 96h PU GND GND 76 4C 1001100 98h PU GND PD 77 4D 1001101 9Ah PU GND FLT 78 4E 1001110 9Ch PU GND PU 79 4F 1001111 9Eh PU GND VDD 80 50 1010000 A0h All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 9 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver Table 5. PCU9956A Product data sheet I2C-bus slave address …continued Hardware selectable input pins I2C-bus slave address for PCU9956A AD2 AD1 AD0 Decimal Hex Binary (A[6:0]) Address (R/W = 0) PU PD GND 81 51 1010001 A2h PU PD PD 82 52 1010010 A4h PU PD FLT 83 53 1010011 A6h PU PD PU 84 54 1010100 A8h PU PD VDD 85 55 1010101 AAh PU FLT GND 86 56 1010110 ACh PU FLT PD 87 57 1010111 AEh PU FLT FLT 88 58 1011000 B0h PU FLT PU 89 59 1011001 B2h PU FLT VDD 90 5A 1011010 B4h PU PU GND 91 5B 1011011 B6h PU PU PD 92 5C 1011100 B8h PU PU FLT 93 5D 1011101 BAh PU PU PU 94 5E 1011110 BCh PU PU VDD 95 5F 1011111 BEh PU VDD GND 96 60 1100000 C0h PU VDD PD 97 61 1100001 C2h PU VDD FLT 98 62 1100010 C4h PU VDD PU 99 63 1100011 C6h PU VDD VDD 100 64 1100100 C8h VDD GND GND 101 65 1100101 CAh VDD GND PD 102 66 1100110 CCh VDD GND FLT 103 67 1100111 CEh VDD GND PU 104 68 1101000 D0h VDD GND VDD 105 69 1101001 D2h VDD PD GND 106 6A 1101010 D4h VDD PD PD 107 6B 1101011 D6h VDD PD FLT 108 6C 1101100 D8h VDD PD PU 109 6D 1101101 DAh VDD PD VDD 110 6E 1101110 DCh VDD FLT GND 111 6F 1101111 DEh VDD FLT PD 112 70 1110000 E0h VDD FLT FLT 113 71 1110001 E2h VDD FLT PU 114 72 1110010 E4h VDD FLT VDD 115 73 1110011 E6h VDD PU GND 116 74 1110100 E8h VDD PU PD 117 75 1110101 EAh VDD PU FLT 118 76 1110110 ECh VDD PU PU 119 77 1110111 EEh VDD PU VDD 120 78 1111000[1] F0h All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 10 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver Table 5. I2C-bus slave address …continued Hardware selectable input pins I2C-bus slave address for PCU9956A AD2 Decimal AD1 VDD VDD GND VDD VDD AD0 121 PD 122 Hex Binary (A[6:0]) Address (R/W = 0) 79 1111001[1] F2h 7A 1111010[1] F4h F6h VDD VDD FLT 123 7B 1111011[1] VDD VDD PU 124 7C 1111100[1] F8h 7D 1111101[1] FAh VDD VDD [1] VDD 125 See ‘Remark’ below. Remark: Reserved I2C-bus addresses must be used with caution since they can interfere with: • • • • ‘reserved for future use’ I2C-bus addresses (0000 011, 1111 1XX) slave devices that use the 10-bit addressing scheme (1111 0XX) slave devices that are designed to respond to the General Call address (0000 000) High-speed mode (Hs-mode) master code (0000 1XX) slave address(1) A6 A5 A4 A3 A2 write only A1 A0 0 002aag460 (1) This slave address must match one of the 125 internal addresses as shown in Table 5. Fig 3. PCU9956A slave address The last bit of the address byte defines the operation to be performed. Only writes to PCU9956A are supported, therefore the last bit is set to 0. No Read available with UFm I2C-bus. 7.1.2 LED All Call I2C-bus address • Default power-up value (ALLCALLADR register): E0h or 1110 000X • Programmable through I2C-bus (volatile programming) • At power-up, LED All Call I2C-bus address is enabled. See Section 7.3.10 “ALLCALLADR, LED All Call I2C-bus address” for more detail. Remark: The default LED All Call I2C-bus address (E0h or 1110 000X) must not be used as a regular I2C-bus slave address since this address is enabled at power-up. All of the PCU9956As on the I2C-bus will recognize the address if sent by the I2C-bus master. PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 11 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 7.1.3 LED Sub Call I2C-bus addresses • 3 different I2C-bus addresses can be used • Default power-up values: – SUBADR1 register: EEh or 1110 111X – SUBADR2 register: EEh or 1110 111X – SUBADR3 register: EEh or 1110 111X • Programmable through I2C-bus (volatile programming) • At power-up, SUBADR1 is enabled while SUBADR2 and SUBADR3 I2C-bus addresses are disabled. Remark: At power-up SUBADR1 identifies this device as a 24-channel driver. See Section 7.3.9 “LED Sub Call I2C-bus addresses for PCU9956A” for more detail. Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus slave addresses as long as they are disabled. 7.2 Control register Following the slave address, LED All Call address or LED Sub Call address, the bus master will send a byte to the PCU9956A, which will be stored in the Control register. The lowest 7 bits are used as a pointer to determine which register will be accessed (D[6:0]). The highest bit is used as Auto-Increment Flag (AIF). This bit along with the MODE1 register bit 5 and bit 6 provide the Auto-Increment feature. register address AIF D6 D5 D4 D3 D2 Auto-Increment Flag D1 D0 002aad850 reset state = 80h Remark: The Control register does not apply to the Software Reset I2C-bus address. Fig 4. Control register When the Auto-Increment Flag is set (AIF = logic 1), the seven low order bits of the Control register are automatically incremented after a write. This allows the user to program the registers sequentially. Four different types of Auto-Increment are possible, depending on AI1 and AI0 values of MODE1 register. PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 12 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver Table 6. Auto-Increment options AIF AI1[1] AI0[1] Function 0 0 0 no Auto-Increment 1 0 0 Auto-Increment for registers (00h to 3Eh). D[6:0] roll over to 00h after the last register 3Eh is accessed. 1 0 1 Auto-Increment for individual brightness registers only (0Ah to 21h). D[6:0] roll over to 0Ah after the last register (21h) is accessed. 1 1 0 Auto-Increment for MODE1 to IREF23 control registers (00h to 39h). D[6:0] roll over to 00h after the last register (39h) is accessed. 1 1 1 Auto-Increment for global control registers and individual brightness registers (08h to 21h). D[6:0] roll over to 08h after the last register (21h) is accessed. [1] AI1 and AI0 come from MODE1 register. Remark: Other combinations not shown in Table 6 (AIF + AI[1:0] = 001b, 010b and 011b) are reserved and must not be used for proper device operation. AIF + AI[1:0] = 000b is used when the same register must be accessed several times during a single I2C-bus communication, for example, changes the brightness of a single LED. Data is overwritten each time the register is accessed during a write operation. AIF + AI[1:0] = 100b is used when all the registers must be sequentially accessed, for example, power-up programming. AIF + AI[1:0] = 101b is used when the 24 LED drivers must be individually programmed with different values during the same I2C-bus communication, for example, changing color setting to another color setting. AIF + AI[1:0] = 110b is used when MODE1 to IREF23 registers must be programmed with different settings during the same I2C-bus communication. AIF + AI[1:0] = 111b is used when the 24 LED drivers must be individually programmed with different values in addition to global programming. Only the 7 least significant bits D[6:0] are affected by the AIF, AI1 and AI0 bits. When the Control register is written, the register entry point determined by D[6:0] is the first register that will be addressed (write operation), and can be anywhere between 00h and 3Eh (as defined in Table 7). When AIF = 1, the Auto-Increment Flag is set and the rollover value at which the register increment stops and goes to the next one is determined by AIF, AI1 and AI0. See Table 6 for rollover values. For example, if MODE1 register bit AI1 = 0 and AI0 = 1 and if the Control register = 1001 0000, then the register addressing sequence will be (in hex): 10  11  …  21  0A  0B  …  21  0A  0B  … as long as the master keeps sending data. If MODE1 register bit AI1 = 0 and AI0 = 0 and if the Control register = 1010 0010, then the register addressing sequence will be (in hex): 22  23  …  3E  00  01  …  21  0A  0B  … as long as the master keeps sending data. PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 13 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver If MODE1 register bit AI1 = 0 and AI0 = 1 and if the Control register = 1000 0101, then the register addressing sequence will be (in hex): 05  06  …  21  0A  0B  …  21  0A  0B  … as long as the master keeps sending data. Remark: Writing to registers marked ‘not used’ will be ignored. 7.3 Register definitions Table 7. Register summary Register D6 number (hex) D5 D4 D3 D2 D1 D0 Name Type Function 00h 0 0 0 0 0 0 0 MODE1 write only Mode register 1 01h 0 0 0 0 0 0 1 MODE2 write only Mode register 2 02h 0 0 0 0 0 1 0 LEDOUT0 write only LED output state 0 03h 0 0 0 0 0 1 1 LEDOUT1 write only LED output state 1 04h 0 0 0 0 1 0 0 LEDOUT2 write only LED output state 2 05h 0 0 0 0 1 0 1 LEDOUT3 write only LED output state 3 06h 0 0 0 0 1 1 0 LEDOUT4 write only LED output state 4 07h 0 0 0 0 1 1 1 LEDOUT5 write only LED output state 5 08h 0 0 0 1 0 0 0 GRPPWM write only group duty cycle control 09h 0 0 0 1 0 0 1 GRPFREQ write only group frequency 0Ah 0 0 0 1 0 1 0 PWM0 write only brightness control LED0 0Bh 0 0 0 1 0 1 1 PWM1 write only brightness control LED1 0Ch 0 0 0 1 1 0 0 PWM2 write only brightness control LED2 0Dh 0 0 0 1 1 0 1 PWM3 write only brightness control LED3 0Eh 0 0 0 1 1 1 0 PWM4 write only brightness control LED4 0Fh 0 0 0 1 1 1 1 PWM5 write only brightness control LED5 10h 0 0 1 0 0 0 0 PWM6 write only brightness control LED6 11h 0 0 1 0 0 0 1 PWM7 write only brightness control LED7 12h 0 0 1 0 0 1 0 PWM8 write only brightness control LED8 13h 0 0 1 0 0 1 1 PWM9 write only brightness control LED9 14h 0 0 1 0 1 0 0 PWM10 write only brightness control LED10 15h 0 0 1 0 1 0 1 PWM11 write only brightness control LED11 16h 0 0 1 0 1 1 0 PWM12 write only brightness control LED12 17h 0 0 1 0 1 1 1 PWM13 write only brightness control LED13 18h 0 0 1 1 0 0 0 PWM14 write only brightness control LED14 19h 0 0 1 1 0 0 1 PWM15 write only brightness control LED15 1Ah 0 0 1 1 0 1 0 PWM16 write only brightness control LED16 1Bh 0 0 1 1 0 1 1 PWM17 write only brightness control LED17 1Ch 0 0 1 1 1 0 0 PWM18 write only brightness control LED18 1Dh 0 0 1 1 1 0 1 PWM19 write only brightness control LED19 1Eh 0 0 1 1 1 1 0 PWM20 write only brightness control LED20 1Fh 0 0 1 1 1 1 1 PWM21 write only brightness control LED21 PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 14 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver Table 7. Register summary …continued Register D6 number (hex) D5 D4 D3 D2 D1 D0 Name Type Function 20h 0 1 1 0 0 0 0 PWM22 write only brightness control LED22 21h 0 1 1 0 0 0 1 PWM23 write only brightness control LED23 22h 0 1 0 0 0 1 0 IREF0 write only output gain control register 0 23h 0 1 0 0 0 1 1 IREF1 write only output gain control register 1 24h 0 1 0 0 1 0 0 IREF2 write only output gain control register 2 25h 0 1 0 0 1 0 1 IREF3 write only output gain control register 3 26h 0 1 0 0 1 1 0 IREF4 write only output gain control register 4 27h 0 1 0 0 1 1 1 IREF5 write only output gain control register 5 28h 0 1 0 1 0 0 0 IREF6 write only output gain control register 6 29h 0 1 0 1 0 0 1 IREF7 write only output gain control register 7 2Ah 0 1 0 1 0 1 0 IREF8 write only output gain control register 8 2Bh 0 1 0 1 0 1 1 IREF9 write only output gain control register 9 2Ch 0 1 0 1 1 0 0 IREF10 write only output gain control register 10 2Dh 0 1 0 1 1 0 1 IREF11 write only output gain control register 11 2Eh 0 1 0 1 1 1 0 IREF12 write only output gain control register 12 2Fh 0 1 0 1 1 1 1 IREF13 write only output gain control register 13 30h 0 1 1 0 0 0 0 IREF14 write only output gain control register 14 31h 0 1 1 0 0 0 1 IREF15 write only output gain control register 15 32h 0 1 1 0 0 1 0 IREF16 write only output gain control register 16 33h 0 1 1 0 0 1 1 IREF17 write only output gain control register 17 34h 0 1 1 0 1 0 0 IREF18 write only output gain control register 18 35h 0 1 1 0 1 0 1 IREF19 write only output gain control register 19 36h 0 1 1 0 1 1 0 IREF20 write only output gain control register 20 37h 0 1 1 0 1 1 1 IREF21 write only output gain control register 21 38h 0 1 1 1 0 0 0 IREF22 write only output gain control register 22 39h 0 1 1 1 0 0 1 IREF23 write only output gain control register 23 3Ah 0 1 1 1 0 1 0 OFFSET write only Offset/delay on LEDn outputs 3Bh 0 1 1 1 0 1 1 SUBADR1 write only I2C-bus subaddress 1 3Ch 0 1 1 1 1 0 0 SUBADR2 write only I2C-bus subaddress 2 3Dh 0 1 1 1 1 0 1 SUBADR3 write only I2C-bus subaddress 3 3Eh 0 1 1 1 1 1 0 ALLCALLADR write only All Call I2C-bus address 3Fh 0 1 1 1 1 1 1 PWMALL write only brightness control for all LEDn 40h 1 0 0 0 0 0 0 IREFALL write only output gain control for all registers IREF0 to IREF23 41h to 7Fh - - - - - - - reserved write only not used[1] [1] Writing to registers marked ‘not used’ will be ignored. PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 15 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 7.3.1 MODE1 — Mode register 1 Table 8. MODE1 - Mode register 1 (address 00h) bit description Legend: * default value. Bit Symbol Access Value Description 7 AIF write only 0 Register Auto-Increment disabled. 1* Register Auto-Increment enabled (write default logic 1). 0* Auto-Increment bit 1 = 0. Auto-increment range as defined in Table 6. 1 Auto-Increment bit 1 = 1. Auto-increment range as defined in Table 6. 0* Auto-Increment bit 0 = 0. Auto-increment range as defined in Table 6. 1 Auto-Increment bit 0 = 1. Auto-increment range as defined in Table 6. 0* Normal mode[1]. 1 Low power mode. Oscillator off[2][3]. 0 PCU9956A does not respond to I2C-bus subaddress 1. 1* PCU9956A responds to I2C-bus subaddress 1. 0* PCU9956A does not respond to I2C-bus subaddress 2. 1 PCU9956A responds to I2C-bus subaddress 2. 0* PCU9956A does not respond to I2C-bus subaddress 3. 1 PCU9956A responds to I2C-bus subaddress 3. 0 PCU9956A does not respond to LED All Call I2C-bus address. 1* PCU9956A responds to LED All Call I2C-bus address. 6 AI1 5 AI0 4 write only SLEEP 3 SUB1 2 write only SUB3 0 write only write only SUB2 1 [1] write only write only ALLCALL write only It takes 500 s max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 s window. [2] No blinking or dimming is possible when the oscillator is off. [3] The device must be reset if the LED driver output state is set to LDRx=11 after the device is set back to Normal mode. 7.3.2 MODE2 — Mode register 2 Table 9. MODE2 - Mode register 2 (address 01h) bit description Legend: * default value. PCU9956A Product data sheet Bit Symbol Access Value Description 7 - - 0* not used (must write a logic 0) 6 - - 0* not used (must write a logic 0) 5 DMBLNK write only 0* group control = dimming. 1 group control = blinking. 4 - - 0* reserved (must write a logic 0) 3 OCH write only 0* outputs change on STOP command 1 outputs change on ACK; this ninth bit is always set to 1 by UFm I2C-bus master 2 - - 1* reserved (must write a logic 1) 1 - - 0* reserved (must write a logic 0) 0 - - 1* reserved (must write a logic 1) All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 16 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 7.3.3 LEDOUT0 to LEDOUT5, LED driver output state Table 10. LEDOUT0 to LEDOUT5 - LED driver output state registers (address 02h to 07h) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 02h LEDOUT0 7:6 LDR3 write only 10* LED3 output state control 5:4 LDR2 write only 10* LED2 output state control 3:2 LDR1 write only 10* LED1 output state control 1:0 LDR0 write only 10* LED0 output state control 7:6 LDR7 write only 10* LED7 output state control 5:4 LDR6 write only 10* LED6 output state control 3:2 LDR5 write only 10* LED5 output state control 1:0 LDR4 write only 10* LED4 output state control 7:6 LDR11 write only 10* LED11 output state control 5:4 LDR10 write only 10* LED10 output state control 3:2 LDR9 write only 10* LED9 output state control 1:0 LDR8 write only 10* LED8 output state control 7:6 LDR15 write only 10* LED15 output state control 5:4 LDR14 write only 10* LED14 output state control 3:2 LDR13 write only 10* LED13 output state control 1:0 LDR12 write only 10* LED12 output state control 7:6 LDR19 write only 10* LED19 output state control 5:4 LDR18 write only 10* LED18 output state control 3:2 LDR17 write only 10* LED17 output state control 1:0 LDR16 write only 10* LED16 output state control 7:6 LDR23 write only 10* LED23 output state control 5:4 LDR22 write only 10* LED22 output state control 3:2 LDR21 write only 10* LED21 output state control 1:0 LDR20 write only 10* LED20 output state control 03h 04h 05h 06h 07h LEDOUT1 LEDOUT2 LEDOUT3 LEDOUT4 LEDOUT5 LDRx = 00 — LED driver x is off (x = 0 to 23). LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking not controlled). The OE pin can be used as external dimming/blinking control in this state. LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx register (default power-up state). LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be controlled through its PWMx register and the GRPPWM registers. Remark: Setting the device in low power mode while being on group dimming/blinking mode may cause the LED output state to be in an unknown state after the device is set back to normal mode. The device must be reset and all register values reprogrammed. PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 17 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 7.3.4 GRPPWM, group duty cycle control Table 11. GRPPWM - Group brightness control register (address 08h) bit description Legend: * default value Address Register Bit Symbol Access Value Description 08h GRPPWM 7:0 GDC[7:0] write only 1111 1111* GRPPWM register When DMBLNK bit (MODE2 register) is programmed with logic 0, a 122 Hz fixed frequency signal is superimposed with the 31.25 kHz individual brightness control signal. GRPPWM is then used as a global brightness control allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’. General brightness for the 24 outputs is controlled through 256 linear steps from 00h (0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness). Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT5 registers). When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPFREQ contains the blinking period (from 67 ms to 16.8 s) and GRPPWM the duty cycle (ON/OFF ratio in %). GDC  7:0  duty cycle = -------------------------256 (1) 7.3.5 GRPFREQ, group frequency Table 12. GRPFREQ - Group frequency register (address 09h) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 09h GRPFREQ 7:0 GFRQ[7:0] write only 0000 0000* GRPFREQ register GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2 register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0. Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT5 registers). Blinking period is controlled through 256 linear steps from 00h (67 ms, frequency 15 Hz) to FFh (16.8 s). GFRQ  7:0  + 1 global blinking period = ----------------------------------------  s  15.26 PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 (2) © NXP Semiconductors N.V. 2015. All rights reserved. 18 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 7.3.6 PWM0 to PWM23, individual brightness control Table 13. PWM0 to PWM23 - PWM registers 0 to 23 (address 0Ah to 21h) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 0Ah PWM0 7:0 IDC0[7:0] write only 0000 0000* PWM0 Individual Duty Cycle 0Bh PWM1 7:0 IDC1[7:0] write only 0000 0000* PWM1 Individual Duty Cycle 0Ch PWM2 7:0 IDC2[7:0] write only 0000 0000* PWM2 Individual Duty Cycle 0Dh PWM3 7:0 IDC3[7:0] write only 0000 0000* PWM3 Individual Duty Cycle 0Eh PWM4 7:0 IDC4[7:0] write only 0000 0000* PWM4 Individual Duty Cycle 0Fh PWM5 7:0 IDC5[7:0] write only 0000 0000* PWM5 Individual Duty Cycle 10h PWM6 7:0 IDC6[7:0] write only 0000 0000* PWM6 Individual Duty Cycle 11h PWM7 7:0 IDC7[7:0] write only 0000 0000* PWM7 Individual Duty Cycle 12h PWM8 7:0 IDC8[7:0] write only 0000 0000* PWM8 Individual Duty Cycle 13h PWM9 7:0 IDC9[7:0] write only 0000 0000* PWM9 Individual Duty Cycle 14h PWM10 7:0 IDC10[7:0] write only 0000 0000* PWM10 Individual Duty Cycle 15h PWM11 7:0 IDC11[7:0] write only 0000 0000* PWM11 Individual Duty Cycle 16h PWM12 7:0 IDC12[7:0] write only 0000 0000* PWM12 Individual Duty Cycle 17h PWM13 7:0 IDC13[7:0] write only 0000 0000* PWM13 Individual Duty Cycle 18h PWM14 7:0 IDC14[7:0] write only 0000 0000* PWM14 Individual Duty Cycle 19h PWM15 7:0 IDC15[7:0] write only 0000 0000* PWM15 Individual Duty Cycle 1Ah PWM16 7:0 IDC16[7:0] write only 0000 0000* PWM16 Individual Duty Cycle 1Bh PWM17 7:0 IDC17[7:0] write only 0000 0000* PWM17 Individual Duty Cycle 1Ch PWM18 7:0 IDC18[7:0] write only 0000 0000* PWM18 Individual Duty Cycle 1Dh PWM19 7:0 IDC19[7:0] write only 0000 0000* PWM19 Individual Duty Cycle 1Eh PWM20 7:0 IDC20[7:0] write only 0000 0000* PWM20 Individual Duty Cycle 1Fh PWM21 7:0 IDC21[7:0] write only 0000 0000* PWM21 Individual Duty Cycle 20h PWM22 7:0 IDC22[7:0] write only 0000 0000* PWM22 Individual Duty Cycle 21h PWM23 7:0 IDC23[7:0] write only 0000 0000* PWM23 Individual Duty Cycle A 31.25 kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs programmed with LDRx = 10 or 11 (LEDOUT0 to LEDOUT5 registers). IDCx  7:0  duty cycle = --------------------------256 (3) Remark: The first lower end 8 steps of PWM and the last (higher end) steps of PWM will not have effective brightness control of LEDs due to edge rate control of LED output pins. PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 19 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 7.3.7 IREF0 to IREF23, LED output current value registers These registers reflect the gain settings for output current for LED0 to LED23. Table 14. IREF0 to IREF23 - LED output gain control registers (address 22h to 39h) bit description Legend: * default value. PCU9956A Product data sheet Address Register Bit Access Value Description 22h IREF0 7:0 write only 00h* LED0 output current setting 23h IREF1 7:0 write only 00h* LED1 output current setting 24h IREF2 7:0 write only 00h* LED2 output current setting 25h IREF3 7:0 write only 00h* LED3 output current setting 26h IREF4 7:0 write only 00h* LED4 output current setting 27h IREF5 7:0 write only 00h* LED5 output current setting 28h IREF6 7:0 write only 00h* LED6 output current setting 29h IREF7 7:0 write only 00h* LED7 output current setting 2Ah IREF8 7:0 write only 00h* LED8 output current setting 2Bh IREF9 7:0 write only 00h* LED9 output current setting 2Ch IREF10 7:0 write only 00h* LED10 output current setting 2Dh IREF11 7:0 write only 00h* LED11 output current setting 2Eh IREF12 7:0 write only 00h* LED12 output current setting 2Fh IREF13 7:0 write only 00h* LED13 output current setting 30h IREF14 7:0 write only 00h* LED14 output current setting 31h IREF15 7:0 write only 00h* LED15 output current setting 32h IREF16 7:0 write only 00h* LED16 output current setting 33h IREF17 7:0 write only 00h* LED17 output current setting 34h IREF18 7:0 write only 00h* LED18 output current setting 35h IREF19 7:0 write only 00h* LED19 output current setting 36h IREF20 7:0 write only 00h* LED20 output current setting 37h IREF21 7:0 write only 00h* LED21 output current setting 38h IREF22 7:0 write only 00h* LED22 output current setting 39h IREF23 7:0 write only 00h* LED23 output current setting All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 20 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 7.3.8 OFFSET — LEDn output delay offset register Table 15. OFFSET - LEDn output delay offset register (address 3Ah) bit description Legend: * default value. Address Register Bit Access Value Description 3Ah OFFSET 7:4 - 0000* not used (must write a logic 0) 3:0 write only 1000* LEDn output delay offset factor The PCU9956A can be programmed to have turn-on delay between LED outputs. This helps to reduce peak current for the VDD supply and reduces EMI. The order in which the LED outputs are enabled will always be the same (channel 0 will enable first and channel 23 will enable last). OFFSET control register bits [3:0] determine the delay used between the turn-on times as follows: 0000 = no delay between outputs (all on, all off at the same time) 0001 = delay of 1 clock cycle (125 ns) between successive outputs 0010 = delay of 2 clock cycles (250 ns) between successive outputs 0011 = delay of 3 clock cycles (375 ns) between successive outputs : 0111 = delay of 7 clock cycles (875 ns) between successive outputs 1000 = delay of 8 clock cycles (1 s) between successive outputs 1001 = delay of 9 clock cycles (1.125 s) between successive outputs 1010 = delay of 10 clock cycles (1.25 s) between successive outputs 1011 = delay of 11 clock cycles (1.375 s) between successive outputs 1100 to 1111 = reserved and do not use Example: If the value in the OFFSET register is 1000 the corresponding delay = 8  125 ns = 1 s delay between successive outputs. channel 0 turns on at time 0 s channel 1 turns on at time 1 s channel 2 turns on at time 2 s channel 3 turns on at time 3 s channel 4 turns on at time 4 s channel 5 turns on at time 5 s channel 6 turns on at time 6 s channel 7 turns on at time 7 s channel 8 turns on at time 8 s channel 9 turns on at time 9 s channel 10 turns on at time 10 s channel 11 turns on at time 11 s channel 12 turns on at time 12 s channel 13 turns on at time 13 s PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 21 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver channel 14 turns on at time 14 s channel 15 turns on at time 15 s channel 16 turns on at time 16 s channel 17 turns on at time 17 s channel 18 turns on at time 18 s channel 19 turns on at time 19 s channel 20 turns on at time 20 s channel 21 turns on at time 21 s channel 22 turns on at time 22 s channel 23 turns on at time 23 s 7.3.9 LED Sub Call I2C-bus addresses for PCU9956A SUBADR1 to SUBADR3 - I2C-bus subaddress registers 1 to 3 (address 3Bh to 3Dh) bit description Legend: * default value. Table 16. Address Register Bit Symbol Access Value Description 3Bh SUBADR1 7:1 A1[7:1] write only 1110 111* I2C-bus subaddress 1 0 A1[0] write only 0* reserved A2[7:1] write only 1110 111* I2C-bus subaddress 2 3Ch SUBADR2 7:1 0 A2[0] write only 0* reserved 3Dh SUBADR3 7:1 A3[7:1] write only 1110 111* I2C-bus subaddress 3 0 A3[0] write only 0* reserved Default power-up values are EEh, EEh, EEh. At power-up, SUBADR1 is enabled while SUBADR2 and SUBADR3 are disabled. The power-up default bit subaddress of EEh indicates that this device is a 24-channel LED driver. All three subaddresses are programmable. Once subaddresses have been programmed to their right values, SUBx bits need to be set to logic 1 in order to have the device respond to these addresses (MODE1 register) (0). When SUBx is set to logic 1, the corresponding I2C-bus subaddress can be used during a UFm I2C-bus write sequence. 7.3.10 ALLCALLADR, LED All Call I2C-bus address ALLCALLADR - LED All Call I2C-bus address register (address 3Eh) bit description Legend: * default value. Table 17. Address Register Bit Symbol Access Value Description 3Eh ALLCALLADR 7:1 AC[7:1] write only 1110 000* ALLCALL I2C-bus address register 0 AC[0] write only 0* reserved The LED All Call I2C-bus address allows all the PCU9956As on the bus to be programmed at the same time (ALLCALL bit in register MODE1 must be equal to logic 1 [power-up default state]). This address is programmable through the I2C-bus and can be used during an I2C-bus write sequence. The register address can also be programmed as a Sub Call. PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 22 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver Only the 7 MSBs representing the All Call I2C-bus address are valid. The LSB in ALLCALLADR register must write a logic 0. If ALLCALL bit = 0 in MODE1 register, the device does not recognize the address programmed in register ALLCALLADR. 7.3.11 PWMALL — brightness control for all LEDn outputs When programmed, the value in this register will be used for PWM duty cycle for all the LEDn outputs and will be reflected in PWM 0 through PWM23 registers. Table 18. PWMALL - brightness control for all LEDn outputs register (address 3Fh) bit description Legend: * default value. Address Register Bit Access Value Description 3Fh PWMALL 7:0 write only 0000 0000* duty cycle for all LEDn outputs Remark: Write to any of the PWM0 to PWM23 registers will overwrite the value in corresponding PWMn register programmed by PWMALL. 7.3.12 IREFALL register: output current value for all LED outputs The output current setting for all outputs is held in this register. When this register is written to or updated, all LED outputs will be set to a current corresponding to this register value. Writes to IREF0 to IREF23 will overwrite the output current settings. Table 19. IREFALL - Output gain control for all LED outputs (address 40h) bit description Legend: * default value. Address Register Bit Access Value Description 40h IREFALL 7:0 write only 00h* current gain setting for all LED outputs 7.3.13 LED driver constant current outputs In LED display applications, PCU9956A provides nearly no current variations from channel to channel and from device to device. The maximum current skew between channels is less than 4 % and less than 6 % between devices. 7.3.13.1 Adjusting output current The PCU9956A scales up the reference current (Iref) set by the external resistor (Rext) to sink the output current (IO) at each output port. The maximum output current for the outputs can be set using Rext. In addition, the constant value for current drive at each of the outputs is independently programmable using command registers IREF0 to IREF23. Alternatively, programming the IREFALL register allows all outputs to be set at one current value determined by the value in IREFALL register. Equation 4 and Equation 5 can be used to calculate the minimum and maximum constant current values that can be programmed for the outputs for a chosen Rext. PCU9956A Product data sheet 900 mV 1 I O _LED_MIN = -------------------  ---  minimum constant current  4 R ext (4) 900 mV 255 I O _LED_MAX =  255  I O _LED_MIN  =  -------------------  --------- 4 R ext (5) All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 23 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 900 mV 1 For a given IREFx setting, I O _LED = IREFx  -------------------  --- . 4 R ext 002aag288 80 IREFx = 255 IO(LEDn) (mA) 60 40 20 0 1 2 4 3 5 6 8 7 9 10 Rext (kΩ) IO(LEDn) (mA) = IREFx  (0.9 / 4) / Rext (k) maximum IO(LEDn) (mA) = 255  (0.9 / 4) / Rext (k) Remark: Default IREFx at power-up = 0. Fig 5. Maximum ILED versus Rext Example 1: If Rext = 1 k, IO_LED_MIN = 225 A, IO_LED_MAX = 57.375 mA (as shown in Figure 6). So each channel can be programmed with its individual IREFx in 256 steps and in 225 A increments to a maximum output current of 57.375 mA independently. 002aah691 60 IO(target) (mA) 50 57.375 40 30 20 10 0 0 Fig 6. PCU9956A Product data sheet 32 64 96 128 160 192 224 255 IREFx[7:0] value IO(target) versus IREFx value with Rext = 1 k All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 24 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver Example 2: If Rext = 2 k, IO_LED_MIN = 112.5 A, IO_LED_MAX = 28.687 mA (as shown in Figure 7). So each channel can be programmed with its individual IREFx in 256 steps and in 112.5 A increments to a maximum output channel of 28.687 mA independently. 002aah667 30 IO(target) (mA) 20 10 0 0 Fig 7. 32 64 96 128 160 192 255 224 IREFx[7:0] value IO(target) versus IREFx value with Rext = 2 k 7.3.14 Overtemperature protection If the PCU9956A chip temperature exceeds its limit (Tmax, see Table 22), all output channels will be disabled until the temperature drops below its limit minus a small hysteresis (Thys, see Table 22). Once the die temperature reduces below the Tmax  Thys, the chip will return to the same condition it was prior to the overtemperature event. 7.4 Active LOW output enable input The active LOW output enable (OE) pin on PCU9956A allows to enable or disable all the LED outputs at the same time. • When a LOW level is applied to OE pin, all the LED outputs are enabled. • When a HIGH level is applied to OE pin, all the LED outputs are high-impedance. The OE pin can be used as a synchronization signal to switch on/off several PCU9956A devices at the same time when LED drive output state is set fully ON (LDRx = 01 in LEDOUTx register) in these devices. This requires an external clock reference that provides blinking period and the duty cycle. The OE pin can also be used as an external dimming control signal. The frequency of the external clock must be high enough not to be seen by the human eye, and the duty cycle value determines the brightness of the LEDs. Remark: Do not use OE as an external blinking control signal when internal global blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an undefined blinking pattern. Do not use OE as an external dimming control signal when internal global dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an undefined dimming pattern. PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 25 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 7.5 Power-on reset When power is applied to VDD, an internal power-on reset holds the PCU9956A in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the PCU9956A registers and I2C-bus state machine are initialized to their default states (all zeroes) causing all the channels to be deselected. Thereafter, VDD must be pulled lower than 1 V and stay LOW for longer than 20 s. The device will reset itself, and allow 2 ms for the device to fully wake up. Remark: In order to guarantee a proper Power-On Reset operation for device, the rising rate of VDD must be less than 3 ms per 1 V or less than 10 ms from 0 V to 3.3 V. Also, VDD must return to 0 V for a minimum of 10 ms before rising again while VDD power is re-cycling. 7.6 Hardware reset recovery When a reset of PCU9956A is activated using an active LOW input on the RESET pin, a reset pulse width of 2.5 s minimum is required. The maximum wait time after RESET pin is released is 1.5 ms. 7.7 Software reset The Software Reset Call (SWRST Call) allows all the devices in the I2C-bus to be reset to the power-up state value through a specific formatted I2C-bus command. To be performed correctly, it implies that the I2C-bus is functional and that there is no device hanging the bus. The maximum wait time after software reset is 1 ms. The SWRST Call function is defined as the following: 1. A START command is sent by the I2C-bus master. 2. The reserved General Call address ‘0000 000’ with the R/W bit set to ‘0’ (write) is sent by the I2C-bus master. 3. Since PCU9956A is a UFm I2C-bus device, no acknowledge is returned to the I2C-bus master. 4. Once the General Call address has been sent, the master sends 1 byte with 1 specific value (SWRST data byte 1): Byte 1 = 06h. If more than 1 byte of data is sent, they will be ignored by the PCU9956A. 5. Once the correct byte (SWRST data byte 1) has been sent, the master sends a STOP command to end the SWRST function: the PCU9956A then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time (tBUF). PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 26 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver General Call address S 0 0 0 0 START condition 0 0 0 SWRST data byte 1 0 1 0 0 this bit is always = 1 0 0 0 1 1 0 1 P this bit is always = 1 STOP condition 002aaf099 Fig 8. PCU9956A Product data sheet SWRST Call All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 27 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 7.8 Individual brightness control with group dimming/blinking A 31.25 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control individually the brightness for each LED. On top of this signal, one of the following signals can be superimposed (this signal can be applied to the 24 LED outputs LED0 to LED23). • A lower 122 Hz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to provide a global brightness control. • A programmable frequency signal from 15 Hz to every 16.8 seconds (8 bits, 256 steps) with programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking control. 1 2 3 4 5 6 7 8 9 10 11 12 251 252 253 254 255 256 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 Brightness Control signal (LEDn) N × 125 ns with N = (0 to 255) (PWMx Register) M × 256 × 125 ns with M = (0 to 255) (GRPPWM Register) 256 × 125 ns = 32 μs (31.25 kHz) Group Dimming signal 256 × 256 × 125 ns = 8.19 ms (122 Hz) 1 2 3 4 5 6 7 8 resulting Brightness + Group Dimming signal 002aaf935 Minimum pulse width for LEDn Brightness Control is 125 ns. Minimum pulse width for Group Dimming is 32 s. When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal will have 1 pulse of the LED Brightness Control signal (pulse width = N  125 ns, with ‘N’ defined in PWMx register). This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 8. Fig 9. Brightness + Group Dimming signals PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 28 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 8. Characteristics of the PCU9956A Ultra Fast-mode I2C-bus The PCU9956A LED controller uses the new Ultra Fast-mode (UFm) I2C-bus to communicate with the UFm I2C-bus capable host controller. Like the Standard mode and Fast-mode Plus (Fm+) I2C-bus, it uses two lines for communication. They are a serial data line (USDA) and a serial clock line (USCL). The UFm is a unidirectional bus that is capable of higher frequency (up to 5 MHz). The UFm I2C-bus slave devices operate in receive-only mode. That is, only I2C writes to PCU9956A are supported. 8.1 Bit transfer One data bit is transferred during each clock pulse. The data on the USDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 10). USDA USCL data line stable; data valid change of data allowed 002aaf113 Fig 10. Bit transfer 8.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 11). USDA USCL S P START condition STOP condition 002aaf114 Fig 11. Definition of START and STOP conditions PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 29 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 8.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 12). USDA MASTER UFm TRANSMITTER USCL SLAVE UFm RECEIVER SLAVE UFm RECEIVER SLAVE UFm RECEIVER 002aaf100 Fig 12. System configuration 8.3 Data transfer The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one bit that is always set to 1. The master generates an extra related clock pulse. USDA data output by master UFm transmitter USCL clock from master 1 2 8 9 S START condition 002aaf101 Fig 13. Data transfer PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 30 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 9. Bus transactions slave address(1) control register S A6 A5 A4 A3 A2 A1 A0 0 START condition 1 X D6 D5 D4 D3 D2 D1 D0 1 register address(2) write only data for register D[7:0] Auto-Increment flag (don’t care) 1 this bit always = 1 P this bit always = 1 STOP condition this bit always = 1 002aag461 (1) See Table 5 for I2C-bus slave address. (2) See Table 7 for register definition. Fig 14. Write to a specific register slave address S A6 A5 A4 A3 A2 A1 A0 0 START condition MODE1 register data(1) control register 1 write only this bit always = 1 1 0 0 0 0 0 0 0 MODE1 register selection Auto-Increment on 1 this bit always = 1 MODE2 register data 1 1 this bit always = 1 this bit always = 1 (cont.) ALLCALLADR register data (cont.) 1 P this bit always = 1 STOP condition 002aag462 (1) AI1, AI0 = 00. See Table 6 for Auto-Increment options. Remark: Care should be taken to load the appropriate value here in the AI1 and AI0 bits of the MODE1 register for programming the part with the required Auto-Increment options. Fig 15. Write to all registers using the Auto-Increment feature PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 31 of 50 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors PCU9956A Product data sheet slave address control register 1 this bit always = 1 0 0 1 0 1 0 1 this bit always = 1 1 1 this bit always = 1 this bit always = 1 (cont.) Auto-Increment on register rollover PWM23 register data PWM0 register data PWM22 register data (cont.) 0 PWM0 register selection write only START condition 1 PWM1 register data PWM22 register data PWM23 register data 1 1 1 1 1 this bit always = 1 this bit always = 1 this bit always = 1 this bit always = 1 this bit always = 1 P STOP condition 002aag463 Fig 16. Multiple writes to Individual Brightness registers only using the Auto-Increment feature PCU9956A 32 of 50 © NXP Semiconductors N.V. 2015. All rights reserved. This example assumes that AIF + AI[1:0] = 101b. 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver Rev. 2 — 29 June 2015 All information provided in this document is subject to legal disclaimers. S A6 A5 A4 A3 A2 A1 A0 0 PWM0 register data PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver slave address(1) new LED All Call I2C address(2) control register sequence (A) S A6 A5 A4 A3 A2 A1 A0 0 START condition 1 1 0 1 1 1 1 1 0 ALLCALLADR register selection write only this bit always = 1 1 1 0 1 0 1 0 this bit always = 1 1 X 1 P this bit always = 1 Auto-Increment on STOP condition multiple LEDs are on at the 9th bit(3) LED All Call I2C address sequence (B) S 1 0 1 0 1 0 1 START condition control register 0 1 1 0 0 0 LEDOUT3 register (LED fully ON) 1 0 1 0 1 0 1 1 0 1 this bit always = 1 1 0 1 0 1 0 1 1 (cont.) this bit always = 1 this bit always = 1 multiple LEDs are on at the 9th bit(3) LEDOUT4 register (LED fully ON) 1 0 Auto-Increment on multiple LEDs are on at the 9th bit(3) 0 0 LEDOUT0 register selection write only this bit always = 1 (cont.) 0 LEDOUT0 register (LED fully ON) 0 1 0 1 0 1 0 1 multiple LEDs are on at the 9th bit(3) LEDOUT5 register (LED fully ON) 1 0 1 0 1 0 1 this bit always = 1 0 1 1 this bit always = 1 P STOP condition 002aah722 (1) In this example, several PCU9956As are used and the same sequence (A) (above) is sent to each of them. (2) ALLCALL bit in MODE1 register is previously set to 1 for this example. (3) OCH bit in MODE2 register is previously set to 1 for this example. Fig 17. LED All Call I2C-bus address programming and LED All Call sequence example PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 33 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 10. Application design-in information VDD = 3.3 V or 5.0 V 10 kΩ(1) 1.1 kΩ (optional) up to 20 V UFm I2C-BUS/ SMBus MASTER USDA USDA USCL USCL VDD OE LED1 LED2 OE RESET LED0 RESET LED3 LED4 PCU9956A LED5 LED6 LED7 REXT LED8 ISET LED9 LED10 LED11 LED12 LED13 LED14 LED15 LED16 LED17 LED18 AD0(2) LED19 AD1 AD2 LED20 LED21 LED22 VSS LED23 VSS C 10 μF 002aag465 (1) OE requires pull-up resistor if control signal from the master is open-drain. (2) I2C-bus address = 1101001 when AD0, AD2 tied to VDD and AD1 tied to VSS (see Table 5). Fig 18. Typical application PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 34 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 10.1 Thermal considerations Since the PCU9956A device integrates 24 linear current sources, thermal considerations should be taken into account to prevent overheating, which can cause the device to go into thermal shutdown. Perhaps the major contributor for device’s overheating is the LED forward voltage mismatch. This is because it can cause significant voltage differences between the LED strings of the same type (e.g., 2 V to 3 V), which ultimately translates into higher power dissipation in the device. The voltage drop across the LED channels of the device is given by the difference between the supply voltage and the LED forward voltage of each LED string. Reducing this to a minimum (e.g., 0.8 V) helps to keep the power dissipation down. Therefore LEDs binning is recommended to minimize LED voltage forward variation and reduce power dissipation in the device. In order to ensure that the device will not go into thermal shutdown when operating under certain application conditions, its junction temperature (Tj) should be calculated to ensure that is below the overtemperature threshold limit (130 C). The Tj of the device depends on the ambient temperature (Tamb), device’s total power dissipation (Ptot), and thermal resistance. The device junction temperature can be calculated by using the following equation: T j = T amb + R th  j-a   P tot (6) where: Tj = junction temperature Tamb = ambient temperature Rth(j-a) = junction to ambient thermal resistance Ptot = (device) total power dissipation An example of this calculation is show below: Conditions: Tamb = 50 C Rth(j-a) = 33.9 C/W (per JEDEC 51 standard for multilayer PCB) ILED = 30 mA / channel IDD(max) = 20 mA VDD = 5 V LEDs per channel = 5 LEDs / channel LED VF(typ) = 3 V per LED (15 V total for 5 LEDs in series) LED VF mismatch = 0.2 V per LED (1 V total for 5 LEDs in series) Vreg(drv) = 0.8 V (This will be present only in the LED string with the highest LED forward voltage.) Vsup = LED VF(typ) + LED VF mismatch + Vreg(drv) = 15 V + 1 V + 0.8 V = 16.8 V PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 35 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver Ptot calculation: Ptot = IC_power + LED drivers_power; IC_power = (IDD  VDD) IC_power = (0.02 A  5 V) = 0.1 W LED drivers_power = [(24  1)  (ILED)  (LED VF mismatch + Vreg(drv))] + (ILED  Vreg(drv)) LED drivers_power = [23  0.03 A  (1 V + 0.8 V)] + (0.03 A  0.8 V)] = 1.266 W Ptot = 0.1 W + 1.266 W = 1.366 W Tj calculation: Tj = Tamb + Rth(j-a)  Ptot Tj = 50 C + (33.9 C/W  1.366 W) = 96.31 C This confirms that the junction temperature is below the minimum overtemperature threshold of 130 C, which ensures the device will not go into thermal shutdown under these conditions. It is important to mention that the value of the thermal resistance junction-to-ambient (Rth(j-a)) strongly depends in the PCB design. Therefore, the thermal pad of the device should be attached to a big enough PCB copper area to ensure proper thermal dissipation (similar to JEDEC 51 standard). Several thermal vias in the PCB thermal pad should be used as well to increase the effectiveness of the heat dissipation (for example, 15 thermal vias). The thermal vias should be distributed evenly in the PCB thermal pad. Finally, it is important to point out that this calculation should be taken as a reference only and therefore evaluations should still be performed under the application environment and conditions to confirm proper system operation. PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 36 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 11. Limiting values Table 20. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD Min Max Unit supply voltage 0.5 +6.0 V VI/O voltage on an input/output pin VSS  0.5 5.5 V Vdrv(LED) LED driver voltage VSS  0.5 20 V IO(LEDn) output current on pin LEDn - 65 mA ISS ground supply current - 2.5 A Ptot total power dissipation Tamb = 25 C - 2.95 W Tamb = 85 C - 1.18 W 65 +150 C 40 +85 C 40 +125 C Tstg storage temperature Tamb ambient temperature Tj junction temperature Conditions operating 12. Thermal characteristics Table 21. Thermal characteristics Symbol Parameter Conditions Rth(j-a) thermal resistance from junction to ambient HTSSOP38 [1] [1] Typ Unit 33.9 C/W Per JEDEC 51 standard for multilayer PCB and wind speed (nm/s) = 0. PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 37 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 13. Static characteristics Table 22. Static characteristics VDD = 3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Min Typ[1] Max Unit 3 - 5.5 V Rext = 2 k; LED[23:0] = off; IREFx = 00h - 11 12 mA Rext = 1 k; LED[23:0] = off; IREFx = 00h - 13 14 mA Rext = 2 k; LED[23:0] = on; IREFx = FFh - 15 19 mA Rext = 1 k; LED[23:0] = on; IREFx = FFh - 17 21 mA VDD = 3.3 V - 100 600 A VDD = 5.5 V - 100 700 A - 2 - V - 1 - V - +0.3VDD V Conditions Supply VDD supply voltage IDD supply current Istb VPOR VPDR standby current power-on reset voltage power-down reset voltage on pin VDD; operating mode; fSCL = 1 MHz on pin VDD; no load; fSCL = 0 Hz; MODE1[4] = 1; VI = VDD no load; VI = VDD or VSS no load; VI = VDD or VSS [2] Inputs USCL, USDA VIL LOW-level input voltage 0.5 VIH HIGH-level input voltage 0.7VDD - IL leakage current VI = VDD or VSS 1 - +1 A Ci input capacitance VI = VSS - 6 10 pF VO = 0.8 V; IREFx = 80h; Rext = 1 k 25 - 30 mA VO = 0.8 V; IREFx = FFh; Rext = 1 k 50 - 60 mA 5.5 V Current controlled outputs (LED[23:0]) IO(LEDn) output current on pin LEDn IO output current variation VDD = 3.0 V; Tamb = 25 C; VO = 0.8 V; IREFx = 80h; Rext = 1 k; guaranteed by design between bits (different ICs, same channel) [3] - - 6 % between bits (2 channels, same IC) [4] - - 4 % Vreg(drv) driver regulation voltage minimum regulation voltage; IREFx = FFh; Rext = 1 k 0.8 1 20 V IL(off) off-state leakage current VO = 20 V - - 1 A - +0.3VDD V OE input, RESET input VIL LOW-level input voltage 0.5 VIH HIGH-level input voltage 0.7VDD - 5.5 V ILI input leakage current 1 - +1 A Ci input capacitance - 3.7 5 pF PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 38 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver Table 22. Static characteristics …continued VDD = 3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit voltage on an input pin 0.5 - +5.5 V Address inputs AD2, AD1, AD0 VI input voltage ILI input leakage current 1 - +1 A Ci input capacitance - 3.7 5 pF rising 130 - 150 C hysteresis 15 - 30 C Overtemperature protection Tth(otp) overtemperature protection threshold temperature [1] Typical limits at VDD = 3.3 V, Tamb = 25 C. [2] VDD must be lowered to 0.8 V in order to reset part. [3] Part-to-part mismatch is calculated: I O  LED0  + I O  LED1  +  + I O  LED22  + I O  LED23    --------------------------------------------------------------------------------------------------------------------------- – ideal output current    24 % =  ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------  100 ideal output current     where ‘ideal output current’ = 28.68 mA (Rext = 1 k, IREFx = 80h). [4] Channel-to-channel mismatch is calculated:   I O  LEDn   where n = 0 to 23    % =  --------------------------------------------------------------------------------------------------------------------------------- – 1  100   I O  LED0  + I O  LED1  +  + I O  LED22  + I O  LED23     --------------------------------------------------------------------------------------------------------------------------  24 PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 39 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 14. Dynamic characteristics Table 23. Dynamic characteristics All the timing limits are valid within the operating supply voltage and ambient temperature range; VDD = 3 V  0.2 V and 5.5 V  0.3 V; Tamb = 40 C to +85 C; and refer to VIL and VIH with an input voltage of VSS to VDD. Symbol Parameter Conditions [1] Min Typ Max Unit fUSCL USCL clock frequency 0 - 5000 kHz tBUF bus free time between a STOP and START condition 0.08 - - s tHD;STA hold time (repeated) START condition 0.05 - - s tSU;STA set-up time for a repeated START condition 0.05 - - s tSU;STO set-up time for STOP condition 0.05 - - s tHD;DAT data hold time 10 - - ns - - - ns [2] tVD;DAT data valid time tSU;DAT data set-up time 30 - - ns tLOW LOW period of the USCL clock 50 - - ns tHIGH HIGH period of the USCL clock 50 - - ns tf fall time of both USDA and USCL signals - - 50 ns tr rise time of both USDA and USCL signals - - 50 ns tSP pulse width of spikes that must be suppressed by the input filter - - 10 ns [1] Minimum USCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either USDA or USCL is held LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation. [2] tVD;DAT is not applicable to the UFm I2C-bus slave device. 0.7 × VDD USDA 0.3 × VDD tr tBUF tf tHD;STA tSP tLOW 0.7 × VDD USCL 0.3 × VDD tHD;STA P S tSU;STA tHD;DAT tHIGH tSU;DAT Sr tSU;STO P 002aag331 Fig 19. Definition of timing PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 40 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver protocol START condition (S) tSU;STA bit 7 MSB tLOW bit 1 (D1) bit 6 tHIGH (always set to 1 by master) bit 0 (D0) STOP condition (P) 9th clock 1 / fUSCL 0.7 × VDD 0.3 × VDD USCL tBUF tf tr 0.7 × VDD 0.3 × VDD USDA tSU;DAT tHD;STA tSU;STO tHD;DAT 002aag332 Rise and fall times refer to VIL and VIH. Fig 20. UFm I2C-bus timing diagram 15. Test information VDD PULSE GENERATOR VI VO RL 50 Ω VDD or VLED open VSS DUT RT CL 50 pF 002aag466 RL = Load resistor for LEDn. CL = Load capacitance includes jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generators. Fig 21. Test circuitry for switching times PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 41 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 16. Package outline +76623SODVWLFWKHUPDOHQKDQFHGWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGV ERG\ZLWKPPOHDGSLWFKPPH[SRVHGGLHSDG 627 ( $ ' ; F \ H[SRVHGGLHSDGVLGH +( = Y $ $ $ 'K   (K $ SLQLQGH[ $ ș /S  /  GHWDLO; ES H Z  PP VFDOH 'LPHQVLRQVPPDUHWKHRULJLQDOGLPHQVLRQV 8QLW PP PD[ QRP PLQ $  $ $ $ ES F              ' 'K ( (K H +H / /S Y                    Z \      1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 2XWOLQH YHUVLRQ 5HIHUHQFHV ,(& -('(& -(,7$ = ș ƒ ƒ ƒ VRWBSR (XURSHDQ SURMHFWLRQ ,VVXHGDWH   627 Fig 22. Package outline SOT1331-1 (HTSSOP38) PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 42 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 17. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 18.3 Wave soldering Key characteristics in wave soldering are: PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 43 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 23) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 24 and 25 Table 24. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 25. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 23. PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 44 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 45 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 19. Soldering: PCB footprints )RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI+76623SDFNDJH 627 +[ *[ 3  Q63[ 636[ 63[ Q63\ +\ %\ 6/\  63\ 63\WRW 636\ *\ $\ 63[WRW 6/[ & ' î 3 ' *HQHULFIRRWSULQWSDWWHUQ 5HIHUWRWKHSDFNDJHRXWOLQHGUDZLQJIRUDFWXDOOD\RXW VROGHUODQG VROGHUODQGSOXVVROGHUSDVWH RFFXSLHGDUHD 636[ 636\ 63[WRW 63\WRW     'LPHQVLRQVLQPP 3 3 $\ %\ & ' ' *[ *\ +[ +\ Q63[ Q63\ 6/[ 6/\ 63[ 63\                  ,VVXHGDWH   VRWBIU Fig 24. PCB footprint for SOT1331-1 (HTSSOP38); reflow soldering PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 46 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 20. Abbreviations Table 26. Abbreviations Acronym Description ACK Acknowledge DUT Device Under Test ESD ElectroStatic Discharge FET Field-Effect Transistor HBM Human Body Model I2C-bus Inter-Integrated Circuit bus LED Light Emitting Diode LSB Least Significant Bit MSB Most Significant Bit NMOS Negative-channel Metal-Oxide Semiconductor PCB Printed-Circuit Board PMOS Positive-channel Metal-Oxide Semiconductor PWM Pulse Width Modulation RGB Red/Green/Blue RGBA Red/Green/Blue/Amber SMBus System Management Bus 21. Revision history Table 27. Revision history Document ID Release date Data sheet status Change notice Supersedes PCU9956A v.2.1 20150629 Product data sheet - PCU9956A v.2 Modifications: PCU9956A v.2 Modifications: PCU9956A v.1 PCU9956A Product data sheet • • Section 7.3.3 “LEDOUT0 to LEDOUT5, LED driver output state”: added remark. Table 8 “MODE1 - Mode register 1 (address 00h) bit description”: Added Table note [3]. 20141014 • Product data sheet - PCU9956A v.1 Section 7.5 “Power-on reset”: added remark. 20140124 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 - © NXP Semiconductors N.V. 2015. All rights reserved. 47 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 22. Legal information 22.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 22.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 22.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PCU9956A Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 48 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 22.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP Semiconductors N.V. 23. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCU9956A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 49 of 50 PCU9956A NXP Semiconductors 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver 24. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.2 7.3 7.3.1 7.3.2 7.3.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Device addresses . . . . . . . . . . . . . . . . . . . . . . . 7 Regular I2C-bus slave address. . . . . . . . . . . . . 7 LED All Call I2C-bus address . . . . . . . . . . . . . 11 LED Sub Call I2C-bus addresses . . . . . . . . . . 12 Control register . . . . . . . . . . . . . . . . . . . . . . . . 12 Register definitions . . . . . . . . . . . . . . . . . . . . . 14 MODE1 — Mode register 1 . . . . . . . . . . . . . . 16 MODE2 — Mode register 2 . . . . . . . . . . . . . . 16 LEDOUT0 to LEDOUT5, LED driver output state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.3.4 GRPPWM, group duty cycle control . . . . . . . . 18 7.3.5 GRPFREQ, group frequency . . . . . . . . . . . . . 18 7.3.6 PWM0 to PWM23, individual brightness control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3.7 IREF0 to IREF23, LED output current value registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.3.8 OFFSET — LEDn output delay offset register 21 7.3.9 LED Sub Call I2C-bus addresses for PCU9956A . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3.10 ALLCALLADR, LED All Call I2C-bus address. 22 7.3.11 PWMALL — brightness control for all LEDn outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3.12 IREFALL register: output current value for all LED outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3.13 LED driver constant current outputs . . . . . . . . 23 7.3.13.1 Adjusting output current . . . . . . . . . . . . . . . . . 23 7.3.14 Overtemperature protection . . . . . . . . . . . . . . 25 7.4 Active LOW output enable input . . . . . . . . . . . 25 7.5 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 26 7.6 Hardware reset recovery . . . . . . . . . . . . . . . . 26 7.7 Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 26 7.8 Individual brightness control with group dimming/blinking . . . . . . . . . . . . . . . . . . . . . . . 28 8 Characteristics of the PCU9956A Ultra Fast-mode I2C-bus . . . . . . . . . . . . . . . . . . . . . . 29 8.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1.1 8.2 8.3 9 10 10.1 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 21 22 22.1 22.2 22.3 22.4 23 24 START and STOP conditions. . . . . . . . . . . . . System configuration . . . . . . . . . . . . . . . . . . . Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . Bus transactions . . . . . . . . . . . . . . . . . . . . . . . Application design-in information. . . . . . . . . Thermal considerations . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Test information . . . . . . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Soldering: PCB footprints . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 30 30 31 34 35 37 37 38 40 41 42 43 43 43 43 43 44 46 47 47 48 48 48 48 49 49 50 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 June 2015 Document identifier: PCU9956A