PHD21N06LT,118

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET FEATURES PHP21N06LT, PHB21N06LT PHD21N06LT SYMBOL QUICK REFERENCE DATA • ’Trench’ technology • Low on-state resistance • Fast switching • Logic level compatible VDSS = 55 V d ID = 19 A RDS(ON) ≤ 75 mΩ (VGS = 5 V) g RDS(ON) ≤ 70 mΩ (VGS = 10 V) s GENERAL DESCRIPTION N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology. Applications:• d.c. to d.c. converters • switched mode power supplies The PHP21N06LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB21N06LT is supplied in the SOT404 (D2PAK) surface mounting package. The PHD21N06LT is supplied in the SOT428 (DPAK) surface mounting package. PINNING PIN SOT404 (D2PAK) SOT78 (TO220AB) DESCRIPTION 1 gate 2 drain 1 3 source tab tab tab 2 1 23 tab SOT428 (DPAK) 1 2 3 1 3 drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS VDGR VGS VGSM ID Drain-source voltage Drain-gate voltage Gate-source voltage Pulsed gate-source voltage Continuous drain current Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ IDM PD Tj, Tstg Pulsed drain current Total power dissipation Operating junction and storage temperature - 55 55 55 ± 15 ± 20 19 13 76 56 175 V V V V A A A W ˚C Tj ≤ 150˚C Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C 1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages. August 1999 1 Rev 1.500 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP21N06LT, PHB21N06LT PHD21N06LT AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy IAS Peak non-repetitive avalanche current CONDITIONS MIN. MAX. UNIT - 34 mJ - 19 A TYP. MAX. UNIT - 2.7 K/W 60 50 - K/W K/W Unclamped inductive load, IAS = 9.7 A; tp = 100 µs; Tj prior to avalanche = 25˚C; VDD ≤ 25 V; RGS = 50 Ω; VGS = 5 V; refer to fig:15 THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS SOT78 package, in free air SOT428 and SOT404 package, pcb mounted, minimum footprint ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS VGS = 0 V; ID = 0.25 mA; VGS(TO) Drain-source breakdown voltage Gate threshold voltage MIN. Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C RDS(ON) Drain-source on-state resistance VGS = 10 V; ID = 10 A VGS = 5 V; ID = 10 A gfs IGSS IDSS Forward transconductance VDS = 25 V; ID = 10 A Gate source leakage current VGS = ±5 V; VDS = 0 V Zero gate voltage drain VDS = 55 V; VGS = 0 V; current Tj = 175˚C Tj = 175˚C TYP. MAX. UNIT 55 50 1.0 0.5 5 - 1.5 55 60 13 10 0.05 - 2.0 2.3 70 75 158 100 10 500 V V V V V mΩ mΩ mΩ S nA µA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 20 A; VDD = 44 V; VGS = 5 V - 9.4 2.2 5.4 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; RD = 1.2 Ω; RG = 10 Ω; VGS = 5 V Resistive load - 7 88 25 25 15 120 40 45 ns ns ns ns Ld Ld Internal drain inductance Internal drain inductance - 3.5 4.5 - nH nH Ls Internal source inductance Measured from tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad - 7.5 - nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 466 95 71 650 135 85 pF pF pF August 1999 2 Rev 1.500 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP21N06LT, PHB21N06LT PHD21N06LT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge IS ISM CONDITIONS MIN. TYP. MAX. UNIT - - 19 A - - 76 A IF = 20 A; VGS = 0 V - 1.2 1.5 V IF = 20 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 30 V - 43 94 - ns nC Normalised Power Derating, PD (%) Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID 100 100 90 tp = 10 us 80 70 10 100 us 60 50 1 ms D.C. 40 10 ms 1 30 100 ms 20 10 0 0.1 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175 1 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 10 Drain-Source Voltage, VDS (V) 100 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp 10 Normalised Current Derating, ID (%) Transient thermal impedance, Zth j-mb (K/W) 100 90 D = 0.5 80 1 70 60 0.2 0.1 0.05 50 40 0.1 0.02 30 P D D = tp/T tp single pulse 20 10 T 0.01 1E-06 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175 1E-04 1E-03 1E-02 1E-01 1E+00 Pulse width, tp (s) Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V August 1999 1E-05 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 3 Rev 1.500 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP21N06LT, PHB21N06LT PHD21N06LT Drain Current, ID (A) 35 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Tj = 25 C VGS = 10V 30 5V 25 20 3.4 V 15 3.2 V 3V 10 2.8 V 5 2.6 V 2.4 V 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2.4 V 3V 3.2 V 0.15 3.4 V 0.1 5V 0.05 VGS = 10V 0 0 5 10 15 20 Drain Current, ID (A) 25 30 -60 35 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID) 4 6 8 10 12 14 Drain current, ID (A) 16 18 20 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C) Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 ˚C = f(Tj) Drain current, ID (A) 2.25 20 VDS > ID X RDS(ON) 18 2 Normalised On-state Resistance 0.25 0.2 175 C 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 Tj = 25 C 2.8V Tj = 25 C Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) Drain-Source On Resistance, RDS(on) (Ohms) 2.6 V VDS > ID X RDS(ON) 0 2 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS) 0.3 Transconductance, gfs (S) Threshold Voltage, VGS(TO) (V) 2 maximum 1.75 16 14 1.5 12 1.25 10 typical minimum 1 8 0.75 6 0.5 4 175 C 2 0.25 Tj = 25 C 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -60 Gate-source voltage, VGS (V) 0 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C) Fig.7. Typical transfer characteristics. ID = f(VGS) August 1999 -40 -20 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 4 Rev 1.500 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET 1.0E-01 PHP21N06LT, PHB21N06LT PHD21N06LT Drain current, ID (A) Source-Drain Diode Current, IF (A) 30 VGS = 0 V 25 1.0E-02 1.0E-03 20 minimum typical 15 1.0E-04 175 C Tj = 25 C maximum 10 1.0E-05 5 0 1.0E-06 0 0.5 1 1.5 2 Gate-source voltage, VGS (V) 2.5 0 3 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 Source-Drain Voltage, VSDS (V) Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj Maximum Avalanche Current, IAS (A) 10000 100 Capacitances, Ciss, Coss, Crss (pF) 10 1000 25 C Ciss 1 Coss 100 Tj prior to avalanche = 150 C Crss 0.1 0.001 10 0.1 1 10 Drain-Source Voltage, VDS (V) 100 0.1 1 10 Avalanche time, tAV (ms) Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0.01 Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load Gate-source voltage, VGS (V) ID = 20A Tj = 25 C VDD = 11 V VDD = 44 V 0 2 4 6 8 10 12 14 Gate charge, QG (nC) 16 18 20 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG) August 1999 5 Rev 1.500 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP21N06LT, PHB21N06LT PHD21N06LT MECHANICAL DATA Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 E SOT78 A A1 P q D1 D L1 L2(1) Q b1 L 1 2 e e 3 c b 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) (1) UNIT A A1 b b1 c D D1 E mm 4.5 4.1 1.39 1.27 0.9 0.7 1.3 1.0 0.7 0.4 15.8 15.2 6.4 5.9 10.3 9.7 e L L1 2.54 15.0 13.5 3.30 2.79 L2 max. P q Q 3.0 3.8 3.6 3.0 2.7 2.6 2.2 Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 TO-220 Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g) Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to mounting instructions for SOT78 (TO220AB) package. 3. Epoxy meets UL94 V0 at 1/8". August 1999 6 Rev 1.500 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP21N06LT, PHB21N06LT PHD21N06LT MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 OUTLINE VERSION D max. D1 E 11 1.60 1.20 10.30 9.70 e Lp HD Q 2.54 2.90 2.10 15.40 14.80 2.60 2.20 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-12-14 99-06-25 SOT404 Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". August 1999 7 Rev 1.500 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP21N06LT, PHB21N06LT PHD21N06LT MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.18. SOT404 : soldering pattern for surface mounting. August 1999 8 Rev 1.500 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP21N06LT, PHB21N06LT PHD21N06LT MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped) SOT428 seating plane y A E A2 A A1 b2 D1 mounting base E1 D HE L2 2 L1 L 1 3 b1 w M A b c e e1 0 10 20 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 2.38 2.22 A1(1) A2 b b1 max. b2 c 0.65 0.45 0.89 0.71 0.89 0.71 1.1 0.9 5.36 5.26 0.4 0.2 D1 E D max. max. max. 6.22 5.98 4.81 4.45 6.73 6.47 E1 min. 4.0 e e1 2.285 4.57 HE max. L 10.4 9.6 2.95 2.55 L1 min. L2 w y max. 0.5 0.7 0.5 0.2 0.2 Note 1. Measured from heatsink back to lead. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ SOT428 EUROPEAN PROJECTION ISSUE DATE 98-04-07 Fig.19. SOT428 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". MOUNTING INSTRUCTIONS August 1999 9 Rev 1.500 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP21N06LT, PHB21N06LT PHD21N06LT Dimensions in mm 7.0 7.0 2.15 1.5 2.5 4.57 Fig.20. SOT428 : soldering pattern for surface mounting. August 1999 10 Rev 1.500 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP21N06LT, PHB21N06LT PHD21N06LT DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification.  Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1999 11 Rev 1.500