PHK12NQ10T,518

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia PHK12NQ10T N-channel TrenchMOS standard level FET Rev. 02 — 24 November 2009 Product data sheet 1. Product profile 1.1 General description Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits „ Low conduction losses due to low on-state resistance 1.3 Applications „ DC-to-DC primary side switching „ Portable equipment 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - - 100 V ID drain current Tsp = 25 °C; VGS = 10 V; see Figure 3 and 1 - - 11.6 A Ptot total power dissipation Tsp = 25 °C;see Figure 2 - - 8.9 W VGS = 10 V; ID = 12 A; VDS = 50 V; Tj = 25 °C; see Figure 11 - 9 - nC VGS = 10 V; ID = 6 A; Tj = 25 °C; see Figure 9 and 10 - 23.7 28 mΩ Dynamic characteristics QGD gate-drain charge Static characteristics RDSon drain-source on-state resistance PHK12NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 S source 2 S source 3 S source 4 G gate 5 D drain 6 D drain 7 D drain 8 D drain Simplified outline 8 Graphic symbol D 5 G 1 mbb076 4 S SOT96-1 (SO8) 3. Ordering information Table 3. Ordering information Type number PHK12NQ10T Package Name Description Version SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - 100 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 150 °C; RGS = 20 kΩ - 100 V VGS gate-source voltage -20 20 V ID drain current Tsp = 100 °C; VGS = 10 V;see Figure 1 - 7.4 A Tsp = 25 °C; VGS = 10 V;see Figure 3 and 1 - 11.6 A IDM peak drain current Tsp = 25 °C; tp ≤ 10 µs; pulsed;see Figure 3 - 48 A Ptot total power dissipation Tsp = 25 °C;see Figure 2 - 8.9 W Tstg storage temperature -55 150 °C Tj junction temperature -55 150 °C Source-drain diode IS source current Tsp = 25 °C - 12 A ISM peak source current Tsp = 25 °C; tp ≤ 10 µs; pulsed - 48 A - 65 mJ Avalanche ruggedness EDS(AL)S non-repetitive VGS = 10 V; Tj(init) = 25 °C; ID = 11.5 A; drain-source avalanche Vsup ≤ 100 V; unclamped; tp = 0.1 ms energy PHK12NQ10T_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 24 November 2009 2 of 12 PHK12NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 03aa25 120 03aa17 120 Ider (%) Pder (%) 80 80 40 40 0 0 0 50 100 150 200 0 50 100 Tsp (°C) Fig 1. 150 200 Tsp (°C) Fig 2. Normalized continuous drain current as a function of solder point temperature Normalized total power dissipation as a function of solder point temperature 003aaa509 102 Limit RDSon = VDS / ID ID (A) tp = 10 μs 10 100 μs 1 ms 1 10 ms DC 100 ms 10−1 10−2 10−1 Fig 3. 1 10 102 103 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage PHK12NQ10T_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 24 November 2009 3 of 12 PHK12NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Rth(j-sp) thermal resistance from see Figure 4 junction to solder point Min Typ Max Unit - - 15 K/W 003aaa510 102 Zth(j-sp) (K/W) 10 δ = 0.5 0.2 0.1 0.05 1 δ= P 0.02 10−1 10−5 Fig 4. t tp single pulse tp T T 10−4 10−3 10−2 10−1 1 t p (s) 10 Transient thermal impedance from junction to solder point as a function of pulse duration PHK12NQ10T_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 24 November 2009 4 of 12 PHK12NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 6. Characteristics Table 6. Symbol Characteristics Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 89 - - V ID = 250 µA; VGS = 0 V; Tj = 25 °C 100 - - V gate-source threshold voltage ID = 1 mA; VDS= VGS; Tj = 150 °C; see Figure 8 1.2 - - V ID = 1 mA; VDS= VGS; Tj = -55 °C; see Figure 8 - - 4.4 V ID = 1 mA; VDS= VGS; Tj = 25 °C; see Figure 8 2 3 4 V VDS = 100 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 100 V; VGS = 0 V; Tj = 150 °C - - 100 µA VGS = 20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = -20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = 10 V; ID = 6 A; Tj = 150 °C; see Figure 9 and 10 - 52.1 61.6 mΩ VGS = 10 V; ID = 6 A; Tj = 25 °C; see Figure 9 and 10 - 23.7 28 mΩ ID = 12 A; VDS = 50 V; VGS = 10 V; Tj = 25 °C; see Figure 11 - 35 - nC - 7.8 - nC - 9 - nC Static characteristics V(BR)DSS VGS(th) IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C;see Figure 12 - 1965 - pF Coss output capacitance VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C;see Figure 11 - 260 - pF Crss reverse transfer capacitance VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C;see Figure 12 - 90 - pF td(on) turn-on delay time - 23 - ns tr rise time VDS = 50 V; RL = 8.3 Ω; VGS = 10 V; RG(ext) = 6 Ω; Tj = 25 °C; ID = 6 A - 21 - ns td(off) turn-off delay time - 52 - ns tf fall time - 11 - ns Source-drain diode VSD source-drain voltage IS = 12 A; VGS = 0 V; Tj = 25 °C; see Figure 13 - 0.83 1 V trr reverse recovery time IS = 12 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 25 V; Tj = 25 °C - 86 - ns Qr recovered charge IS = 12 A; dIS/dt -100 A/µs; VGS = 0 V; VDS = 25 V; Tj = 25 °C - 120 - nC PHK12NQ10T_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 24 November 2009 5 of 12 PHK12NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 003aaa511 12 10 V 5V VGS = 4.1 V ID 003aaa512 12 4.2 V ID (A) (A) 4V 8 8 Tj = 150 °C 3.9 V 3.8 V 4 25 °C 4 3.7 V 3.6 V 3.4 V 0 Fig 5. 0 0.2 0.4 0.6 0 0.8 1 VDS (V) Output characteristics: drain current as a function of drain-source voltage; typical values 0 ID (A) 3 4 5 Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values 03aa32 5 VGS(th) (V) min 10−2 typ max 4 10−3 3 10−4 2 10−5 1 10−6 0 2 4 0 −60 6 VGS (V) Fig 7. 2 VGS (V) 03aa35 10−1 1 Sub-threshold drain current as a function of gate-source voltage Fig 8. typ min 0 60 120 180 Tj (°C) Gate-source threshold voltage as a function of junction temperature PHK12NQ10T_2 Product data sheet max © NXP B.V. 2009. All rights reserved. Rev. 02 — 24 November 2009 6 of 12 PHK12NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 003aaa513 100 RDSon 03al21 3 4.1 V VGS = 4.0 V (mΩ) a 75 2 4.2 V 50 1 5V 25 10 V 0 -60 0 0 Fig 9. 4 8 12 ID (A) Drain-source on-state resistance as a function of drain current; typical values 003aaa516 10 VGS (V) 0 60 120 180 Tj (°C) Fig 10. Normalized drain-source on-state resistance factor as a function of junction temperature 003aaa514 104 C (pF) VDD = 20 V 8 Ciss 50 V 103 80 V 6 Coss 4 102 Crss 2 0 0 10 20 30 40 10 10−1 Fig 11. Gate-source voltage as a function of gate charge; typical values 102 10 Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values PHK12NQ10T_2 Product data sheet 1 VDS (V) QG (nC) © NXP B.V. 2009. All rights reserved. Rev. 02 — 24 November 2009 7 of 12 PHK12NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 003aaa515 12 IS (A) 8 Tj = 150 °C 4 25 °C 0 0.2 0.4 0.6 0.8 1 VSD (V) Fig 13. Source current as a function of source-drain voltage; typical values PHK12NQ10T_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 24 November 2009 8 of 12 PHK12NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 7. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 inches 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 14. Package outline SOT96-1 (SO8) PHK12NQ10T_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 24 November 2009 9 of 12 PHK12NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PHK12NQ10T_2 20091124 Product data sheet - PHK12NQ10T-01 Modifications: PHK12NQ10T-01 (9397 750 11949) • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 20030915 Product data - PHK12NQ10T_2 Product data sheet - © NXP B.V. 2009. All rights reserved. Rev. 02 — 24 November 2009 10 of 12 PHK12NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 9. Legal information 9.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nxp.com. 9.2 Definitions Draft— The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet— A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 9.3 Disclaimers General— Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes— NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use— NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications— Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data— The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values— Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale— NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published athttp://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license— Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control— This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS— is a trademark of NXP B.V. 10. Contact information For more information, please visit:http://www.nxp.com For sales office addresses, please send an email to:salesaddresses@nxp.com PHK12NQ10T_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 24 November 2009 11 of 12 PHK12NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 November 2009 Document identifier: PHK12NQ10T_2