PHP18NQ10T,127

PHP18NQ10T N-channel TrenchMOS standard level FET Rev. 02 — 16 December 2010 Product data sheet 1. Product profile 1.1 General description Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits „ Higher operating power due to low thermal resistance „ Low conduction losses due to low on-state resistance „ Suitable for high frequency applications due to fast switching characteristics 1.3 Applications „ DC-to-DC converters „ Switched-mode power supplies 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 100 V ID drain current Tmb = 25 °C; VGS = 10 V - - 18 A Ptot total power dissipation Tmb = 25 °C - - 79 W VGS = 10 V; ID = 9 A; Tj = 25 °C - 80 90 mΩ VGS = 10 V; ID = 18 A; VDS = 80 V; Tj = 25 °C - 8 - nC Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge PHP18NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 G gate 2 D drain Simplified outline Graphic symbol D mb 3 S source mb D mounting base; connected to drain G mbb076 S 1 2 3 SOT78 (TO-220AB) 3. Ordering information Table 3. Ordering information Type number PHP18NQ10T PHP18NQ10T Product data sheet Package Name Description Version TO-220AB plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB SOT78 All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 December 2010 © NXP B.V. 2010. All rights reserved. 2 of 13 PHP18NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 100 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ - 100 V VGS gate-source voltage ID drain current -20 20 V VGS = 10 V; Tmb = 100 °C - 13 A VGS = 10 V; Tmb = 25 °C - 18 A - 72 A IDM peak drain current pulsed; Tmb = 25 °C Ptot total power dissipation Tmb = 25 °C - 79 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Source-drain diode IS source current Tmb = 25 °C - 18 A ISM peak source current pulsed; Tmb = 25 °C - 72 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy VGS = 10 V; Tj(init) = 25 °C; ID = 11 A; Vsup ≤ 25 V; unclamped; tp = 100 µs; RGS = 50 Ω - 70 mJ IAS non-repetitive avalanche current Vsup ≤ 25 V; VGS = 10 V; Tj(init) = 25 °C; RGS = 50 Ω; unclamped - 18 A 003aae629 100 PD (%) 80 003aae630 100 ID (%) 80 60 60 40 40 20 20 0 0 0 50 100 150 200 0 Tmb (°C) Fig 1. Normalized total power dissipation as a function of mounting base temperature PHP18NQ10T Product data sheet 50 100 150 200 Tmb (°C) Fig 2. Normalized continuous drain current as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 December 2010 © NXP B.V. 2010. All rights reserved. 3 of 13 PHP18NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 102 003aae631 RDS(on) = VDS / ID IDM (A) IAS (A) tp = 10 μs 10 003aae643 102 10 100 μs 25 °C D.C. 1 ms 10 ms 100 ms 1 10−1 1 10 102 Tj prior to avalanche = 150 °C 1 103 10−1 10−3 10−2 10−1 VDS (V) unclamped inductive load Safe operating area; continuous and peak drain currents as a function of drain-source voltage PHP18NQ10T Product data sheet 10 tAV (ms) Tmb = 25 °C; IDM is single pulse Fig 3. 1 Fig 4. Single-shot avalanche rating; avalanche current as a function of avalanche period All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 December 2010 © NXP B.V. 2010. All rights reserved. 4 of 13 PHP18NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Rth(j-mb) thermal resistance from junction to mounting base Rth(j-a) thermal resistance from junction to ambient in free air Min Typ Max Unit - - 1.9 K/W - 60 - K/W 003aae632 10 Zth(j-mb) (K/W) 1 D = 0.5 0.2 0.1 10−1 0.05 0.02 10−2 10−6 tp T t tp single pulse Fig 5. δ= P T 10−5 10−4 10−3 10−2 10−1 1 tp (s) Transient thermal impedance from junction to mounting base as a function of pulse duration PHP18NQ10T Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 December 2010 © NXP B.V. 2010. All rights reserved. 5 of 13 PHP18NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V; Tj = -55 °C 89 - - V ID = 0.25 mA; VGS = 0 V; Tj = 25 °C 100 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = -55 °C - - 6 V ID = 1 mA; VDS = VGS; Tj = 175 °C 1 - - V ID = 1 mA; VDS = VGS; Tj = 25 °C 2 3 4 V VDS = 100 V; VGS = 0 V; Tj = 175 °C - - 500 µA VDS = 100 V; VGS = 0 V; Tj = 25 °C - 0.05 10 µA VGS = 10 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = -10 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = 10 V; ID = 9 A; Tj = 175 °C - - 243 mΩ VGS = 10 V; ID = 9 A; Tj = 25 °C - 80 90 mΩ ID = 18 A; VDS = 80 V; VGS = 10 V; Tj = 25 °C - 21 - nC IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) turn-off delay time tf fall time LD internal drain inductance LS VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C VDS = 50 V; RL = 2.7 Ω; VGS = 10 V; RG(ext) = 5.6 Ω; Tj = 25 °C internal source inductance - 4 - nC - 8 - nC - 633 - pF - 103 - pF - 61 - pF - 6 - ns - 36 - ns - 18 - ns - 12 - ns measured from drain lead to centre of die ; Tj = 25 °C - 4.5 - nH measured from tab to centre of die ; Tj = 25 °C - 3.5 - nH measured from source lead to source bond pad ; Tj = 25 °C - 7.5 - nH Source-drain diode VSD source-drain voltage IS = 18 A; VGS = 0 V; Tj = 25 °C - 0.92 1.2 V trr reverse recovery time - 55 - ns Qr recovered charge IS = 18 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 25 V; Tj = 25 °C - 135 - nC PHP18NQ10T Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 December 2010 © NXP B.V. 2010. All rights reserved. 6 of 13 PHP18NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 003aae633 20 ID (A) 16 VGS = 10 V 8V 6V 003aae634 0.20 RDS(on) (Ω) 0.16 4.6 5.4 5 4.8 5.2 6 12 0.12 5.4 V 8 8 0.08 5.2 V VGS (V) = 10 5V 4 4.8 V 4.6 V 4.4 V 0 0 0.4 0.8 1.2 0.04 0 1.6 2.0 VDS (V) 0 8 12 16 20 ID (A) Tj = 25 °C Fig 6. 4 Tj = 25 °C Output characteristics: drain current as a function of drain-source voltage; typical values Fig 7. 003aae635 20 ID (A) 16 gfs (S) Drain-source on-state resistance as a function of drain current; typical values 003aae636 14 Tj = 25 °C 12 10 12 Tj = 175 °C 8 Tj = 175 °C 8 6 Tj = 25 °C 4 4 2 0 0 0 2 4 6 8 10 VGS (V) 0 8 12 16 20 ID (A) VDS > ID x RDSon Fig 8. 4 VDS > ID x RDSon Transfer characteristics: drain current as a function of gate-source voltage; typical values 003aae637 2.9 Fig 9. Forward transconductance as a function of drain current; typical values 003aae638 4.5 VGS(th) (V) RDS(on) (Ω) maximum 3.5 2.1 typical 2.5 minimum 1.3 1.5 0.5 −60 20 100 180 Tj (°C) 0.5 −60 20 100 180 Tj (°C) ID = 1 mA; VDS = VGS Fig 10. Normalized drain-source on-state resistance factor as a function of junction temperature PHP18NQ10T Product data sheet Fig 11. Gate-source threshold voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 December 2010 © NXP B.V. 2010. All rights reserved. 7 of 13 PHP18NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 003aae639 10−1 ID (A) 003aae640 104 C (pF) 10−2 10−3 minimum 10−4 typical 103 Ciss 102 Coss maximum 10−5 Crss 10−6 0 1 2 3 4 5 10 10−1 1 102 10 VDS (V) VGS (V) Tj = 25 °C; VDS = VGS VGS = 0 V; f = 1 MHz Fig 12. Sub-threshold drain current as a function of gate-source voltage 003aae641 16 VGS (V) 12 VDD = 20 V Fig 13. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aae642 20 IF (A) 16 12 VDD = 80 V Tj = 175 °C 8 Tj = 25 °C 8 4 4 0 0 0 10 20 30 0 QG (nC) 1.2 VGS = 0 V Fig 14. Gate-source voltage as a function of gate charge; typical values Product data sheet 0.8 VSDS (V) Tj = 25 °C; ID = 18 A PHP18NQ10T 0.4 Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 December 2010 © NXP B.V. 2010. All rights reserved. 8 of 13 PHP18NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 7. Package outline Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB SOT78 E A A1 p q mounting base D1 D L1(1) L2(1) Q L b1(2) (3×) b2(2) (2×) 1 2 3 b(3×) c e e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1(2) b2(2) c D D1 E e L L1(1) L2(1) max. p q Q mm 4.7 4.1 1.40 1.25 0.9 0.6 1.6 1.0 1.3 1.0 0.7 0.4 16.0 15.2 6.6 5.9 10.3 9.7 2.54 15.0 12.8 3.30 2.79 3.0 3.8 3.5 3.0 2.7 2.6 2.2 Notes 1. Lead shoulder designs may vary. 2. Dimension includes excess dambar. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC JEITA 3-lead TO-220AB SC-46 EUROPEAN PROJECTION ISSUE DATE 08-04-23 08-06-13 Fig 16. Package outline SOT78 (TO-220AB) PHP18NQ10T Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 December 2010 © NXP B.V. 2010. All rights reserved. 9 of 13 PHP18NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PHP18NQ10T v.2 20101216 Product data sheet - PHB_PHD_PHP18NQ10T v.1 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Type number PHP18NQ10T separated from data sheet PHB_PHD_PHP18NQ10T v.1. PHB_PHD_PHP18NQ10T v.1 19990801 PHP18NQ10T Product data sheet Product specification - All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 December 2010 - © NXP B.V. 2010. All rights reserved. 10 of 13 PHP18NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 9. Legal information 9.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 9.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective PHP18NQ10T Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 December 2010 © NXP B.V. 2010. All rights reserved. 11 of 13 PHP18NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PHP18NQ10T Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 16 December 2010 © NXP B.V. 2010. All rights reserved. 12 of 13 PHP18NQ10T NXP Semiconductors N-channel TrenchMOS standard level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 December 2010 Document identifier: PHP18NQ10T