PHP71NQ03LT,127

PHP/PHB/PHD71NQ03LT TrenchMOS™ logic level FET Rev. 01 — 25 June 2002 Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS™ technology. Product availability: PHP71NQ03LT in SOT78 (TO-220AB) PHB71NQ03LT in SOT404 (D2-PAK) PHD71NQ03LT in SOT428 (D-PAK). 1.2 Features ■ Logic level compatible ■ Low gate charge 1.3 Applications ■ DC to DC converters ■ Switched mode power supplies 1.4 Quick reference data ■ VDS = 30 V ■ Ptot = 120 W ■ ID = 75 A ■ RDSon ≤ 10 mΩ 2. Pinning information Table 1: Pinning - SOT78, SOT404, SOT428 simplified outline and symbol Pin Description 1 gate (g) 2 drain (d) 3 source (s) mb mounting base, connected to drain (d) Simplified outline [1] Symbol mb mb d mb g MBB076 2 2 1 1 3 MBK116 Top view 3 MBK091 MBK106 1 2 3 SOT78 (TO-220) [1] SOT404 (D2-PAK) It is not possible to make connection to pin 2 of the SOT404 or SOT428 packages. SOT428 (D-PAK) s PHP/PHB/PHD71NQ03LT Philips Semiconductors TrenchMOS™ logic level FET 3. Limiting values Table 2: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj ≤ 175 °C - 30 V VDGR drain-gate voltage (DC) 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ - 30 V VGS gate-source voltage (DC) - ±20 V VGSM peak gate-source voltage tp ≤ 50 µs; pulsed; duty cycle = 25 % - ±25 V ID drain current (DC) Tmb = 25 °C; VGS = 10 V; Figure 2 and 3 - 75 A Tmb = 100 °C; VGS = 10 V; Figure 2 - 57.7 A IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 - 240 A Ptot total power dissipation Tmb = 25 °C; Figure 1 - 120 W Tstg storage temperature −55 +175 °C Tj junction temperature −55 +175 °C Source-drain diode IS source (diode forward) current (DC) Tmb = 25 °C - 75 A ISM peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs - 57.7 A © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09821 Product data Rev. 01 — 25 June 2002 2 of 14 PHP/PHB/PHD71NQ03LT Philips Semiconductors TrenchMOS™ logic level FET 03aa16 120 03ai74 120 Pder Ider (%) (%) 80 80 40 40 0 0 50 100 0 150 200 Tmb (°C) 0 P tot P der = ----------------------- × 100% P ° 50 100 150 200 Tmb (°C) ID I der = ------------------- × 100% I ° tot ( 25 C ) D ( 25 C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Normalized continuous drain current as a function of mounting base temperature. 03ai76 103 ID (A) Limit RDSon = VDS / ID tp = 10 µs 102 100 µs DC 1 ms 10 10 ms 1 1 10 VDS (V) 102 Tmb = 25 °C; IDM is single pulse; VGS = 10V. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09821 Product data Rev. 01 — 25 June 2002 3 of 14 PHP/PHB/PHD71NQ03LT Philips Semiconductors TrenchMOS™ logic level FET 4. Thermal characteristics Table 3: Thermal characteristics Symbol Parameter Conditions Rth(j-mb) thermal resistance from junction to mounting base Figure 4 Rth(j-a) thermal resistance from junction to ambient Min Typ Max Unit - - 1.25 K/W SOT78 vertical in still air - 60 - K/W SOT428 SOT428 minimum footprint; mounted on a PCB - 75 - K/W SOT404 and SOT428 SOT404 minimum footprint; mounted on a PCB - 50 - K/W 4.1 Transient thermal impedance 03ai75 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 10-1 δ= P 0.05 tp T 0.02 t tp single pulse T 10-2 10-5 10-4 10-3 10-2 10-1 tp (s) Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09821 Product data Rev. 01 — 25 June 2002 4 of 14 PHP/PHB/PHD71NQ03LT Philips Semiconductors TrenchMOS™ logic level FET 5. Characteristics Table 4: Characteristics Tj = 25 °C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Tj = 25 °C 30 - - V Tj = −55 °C 27 - - V Static characteristics V(BR)DSS drain-source breakdown voltage VGS(th) IDSS gate-source threshold voltage drain-source leakage current ID = 250 µA; VGS = 0 V ID = 1 mA; VDS = VGS; Figure 9 Tj = 25 °C 1 1.9 2.5 V Tj = 175 °C 0.6 - - V Tj = −55 °C - - 2.9 V Tj = 25 °C - 0.05 1 µA Tj = 175 °C - - 500 µA - 10 100 nA Tj = 25 °C - 12 15.2 mΩ Tj = 175 °C - 21.6 27.4 mΩ VGS = 10 V; ID = 25 A; Figure 7 - 8 10 mΩ ID = 50 A; VDD = 15 V; VGS = 5 V; Figure 13 - 13.2 - nC VDS = 30 V; VGS = 0 V IGSS gate-source leakage current VGS = ±20 V; VDS = 0 V RDSon drain-source on-state resistance VGS = 5 V; ID = 25 A; Figure 7 and 8 Dynamic characteristics Qg(tot) total gate charge Qgs gate-source charge - 5.3 - nC Qgd gate-drain (Miller) charge - 4.6 - nC Ciss input capacitance - 1220 - pF Coss output capacitance - 330 - pF Crss reverse transfer capacitance - 140 - pF td(on) turn-on delay time - 15 - ns tr rise time - 150 - ns td(off) turn-off delay time - 13.5 - ns tf fall time - 18 - ns VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11 VDD = 15 V; ID = 25 A; VGS = 4.5 V; RG = 5.6 Ω Source-drain diode VSD source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12 trr reverse recovery time Qr recovered charge IS = 10 A; dIS/dt = −100 A/µs; VGS = 0 V 0.9 1.2 V 29 - ns - 20 - nC © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09821 Product data - Rev. 01 — 25 June 2002 5 of 14 PHP/PHB/PHD71NQ03LT Philips Semiconductors TrenchMOS™ logic level FET 03ai77 80 Tj = 25 °C ID (A) 03ai79 80 10 V 7 V 6 V 5.5 V VDS > ID x RDSon ID (A) 5V 60 60 4.5 V 40 40 4V 20 20 3.5 V Tj = 25 °C 175 °C VGS = 3 V 0 0 0 0.2 0.4 0.6 0.8 1 VDS (V) Tj = 25 °C 0 4 VGS (V) 6 Tj = 25 °C and 175 °C; VDS > ID x RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. 03ai78 20 Tj = 25 °C RDSon (mΩ) 2 VGS = 4.5 V 15 a 1.5 5V 5.5 V 6V 7V 10 V 10 03af18 2 1 5 0.5 0 0 0 20 40 60 80 ID (A) Tj = 25 °C -60 60 120 Tj (°C) 180 R DSon a = ---------------------------R DSon ( 25 °C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09821 Product data 0 Rev. 01 — 25 June 2002 6 of 14 PHP/PHB/PHD71NQ03LT Philips Semiconductors TrenchMOS™ logic level FET 03ai29 3.2 03ai28 10-1 ID (A) 10-2 VGS(th) (V) max 2.4 10-3 typ min typ max 1.6 10-4 min 0.8 10-5 10-6 0 -60 0 60 120 Tj (°C) 180 0 0.8 1.6 2.4 VGS(V) 3.2 Tj = 25 °C; VDS = 5 V ID = 1 mA; VDS = VGS Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. 03ai81 104 C (pF) Ciss 103 Coss 102 10-1 Crss 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09821 Product data Rev. 01 — 25 June 2002 7 of 14 PHP/PHB/PHD71NQ03LT Philips Semiconductors TrenchMOS™ logic level FET 03ai80 80 VGS = 0 V IS (A) 03ai82 10 VGS ID = 50 A (V) Tj = 25 °C 8 60 VDD = 15 V 6 40 4 20 175 °C 2 Tj = 25 °C 0 0 0 0.3 0.6 0.9 VSD (V) 1.2 Tj = 25 °C and 175 °C; VGS = 0 V 0 10 15 20 25 QG (nC) ID = 50 A; VDD = 15 V Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 13. Gate-source voltage as a function of gate charge; typical values. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09821 Product data 5 Rev. 01 — 25 June 2002 8 of 14 PHP/PHB/PHD71NQ03LT Philips Semiconductors TrenchMOS™ logic level FET 6. Package outline Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB E SOT78 A A1 p q mounting base D1 D L2 L1(1) Q b1 L 1 2 3 b c e e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 c D D1 E e L L1(1) L2 max. p q Q mm 4.5 4.1 1.39 1.27 0.9 0.7 1.3 1.0 0.7 0.4 15.8 15.2 6.4 5.9 10.3 9.7 2.54 15.0 13.5 3.30 2.79 3.0 3.8 3.6 3.0 2.7 2.6 2.2 Note 1. Terminals in this zone are not tinned. OUTLINE VERSION REFERENCES IEC SOT78 JEDEC EIAJ 3-lead TO-220AB SC-46 EUROPEAN PROJECTION ISSUE DATE 00-09-07 01-02-16 Fig 14. SOT78 (TO-220AB). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09821 Product data Rev. 01 — 25 June 2002 9 of 14 PHP/PHB/PHD71NQ03LT Philips Semiconductors TrenchMOS™ logic level FET Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D max. D1 E e Lp HD Q mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 11 1.60 1.20 10.30 9.70 2.54 2.90 2.10 15.80 14.80 2.60 2.20 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 99-06-25 01-02-12 SOT404 Fig 15. SOT404 (D2-PAK) © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09821 Product data Rev. 01 — 25 June 2002 10 of 14 PHP/PHB/PHD71NQ03LT Philips Semiconductors TrenchMOS™ logic level FET Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped) SOT428 seating plane y A E A2 A A1 b2 E1 mounting base D1 D HE L2 2 L1 L 1 3 b1 w M A b c e e1 0 10 20 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1(1) A2 b b1 b2 c D D1 min. E mm 2.38 2.22 0.65 0.45 0.93 0.73 0.89 0.71 1.1 0.9 5.46 5.26 0.4 0.2 6.22 5.98 4.0 6.73 6.47 E1 e e1 4.81 2.285 4.57 4.45 HE L L1 min. L2 w y max. 10.4 9.6 2.95 2.55 0.5 0.9 0.5 0.2 0.2 Note 1. Measured from heatsink back to lead. OUTLINE VERSION SOT428 REFERENCES IEC JEDEC JEITA TO-252 SC-63 EUROPEAN PROJECTION ISSUE DATE 99-09-13 01-12-11 Fig 16. SOT428 (D-PAK) © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09821 Product data Rev. 01 — 25 June 2002 11 of 14 PHP/PHB/PHD71NQ03LT Philips Semiconductors TrenchMOS™ logic level FET 7. Revision history Table 5: Revision history Rev Date 01 20020625 CPCN Description Product data; initial version. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09821 Product data Rev. 01 — 25 June 2002 12 of 14 PHP/PHB/PHD71NQ03LT Philips Semiconductors TrenchMOS™ logic level FET 8. Data sheet status Data sheet status[1] Product status[2] Definition Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 9. Definitions 10. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 11. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. Product data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09821 Rev. 01 — 25 June 2002 13 of 14 Philips Semiconductors PHP/PHB/PHD71NQ03LT TrenchMOS™ logic level FET Contents 1 1.1 1.2 1.3 1.4 2 3 4 4.1 5 6 7 8 9 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 © Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 25 June 2002 Document order number: 9397 750 09821