Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com (email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
- © Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
PMN38EN
N-channel TrenchMOS logic level FET
Rev. 02 — 3 October 2007
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package. This product is designed and qualified for use in computing, communications,
consumer and industrial applications only.
1.2 Features
Logic level threshold
Surface-mounted package
Low threshold voltage
Very fast switching
1.3 Applications
Battery powered motor control
Driver FET in DC-to-DC converters
High speed switch in set top box power Load switch in notebook computers
supplies
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 150 °C
-
-
30
V
ID
drain current
Tsp = 25 °C; VGS = 10 V;
see Figure 1 and 3
-
-
5.4
A
Ptot
total power dissipation
Tsp = 25 °C; see Figure 2
-
-
1.75
W
VGS = 4.5 V; ID = 2.8 A;
Tj = 25 °C; see Figure 8 and 9
-
38
46
mΩ
Static characteristics
RDSon
drain-source on-state
resistance
PMN38EN
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pinning
Pin
Symbol
Description
1
D
drain
2
D
drain
3
G
gate
4
S
source
5
D
drain
6
D
drain
Simplified outline
Graphic Symbol
6
5
4
1
2
3
D
G
SOT457 (TSOP6)
mbb076
S
3. Ordering information
Table 3.
Ordering information
Type number
PMN38EN
Package
Name
Description
Version
TSOP6
plastic surface-mounted package (TSOP6); 6 leads
SOT457
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
VDS
drain-source voltage
VGS
gate-source voltage
ID
drain current
Conditions
Min
Tj ≥ 25 °C; Tj ≤ 150 °C
Max
Unit
-
30
V
-20
20
V
Tsp = 100 °C; VGS = 10 V; see Figure 1
-
3.4
A
Tsp = 25 °C; VGS = 10 V; see Figure 1 and 3
-
5.4
A
IDM
peak drain current
Tsp = 25 °C; tp ≤ 10 μs; pulsed; see Figure 3
-
21.6
A
Ptot
total power dissipation
Tsp = 25 °C; see Figure 2
-
1.75
W
Tstg
storage temperature
-55
150
°C
Tj
junction temperature
-55
150
°C
Source-drain diode
IS
source current
Tsp = 25 °C
-
1.45
A
ISM
peak source current
Tsp = 25 °C; tp = 10 μs; pulsed
-
5.8
A
PMN38EN_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 3 October 2007
2 of 12
PMN38EN
NXP Semiconductors
N-channel TrenchMOS logic level FET
03aa25
120
03aa17
120
Ider
(%)
Pder
(%)
80
80
40
40
0
0
0
Ider =
50
ID
ID(25°C )
100
150
Tsp (°C)
200
0
× 100 %
P der =
Fig 1. Normalized continuous drain current as a
function of solder point temperature
50
P tot
P tot (25°C )
100
150
200
× 100 %
Fig 2. Normalized total power dissipation as a
function of solder point temperature
003aab227
102
ID
(A)
Tsp (°C)
Limit RDSon = VDS / ID
tp = 10 μ s
10
100 μ s
1 ms
1
10 ms
DC
100 ms
10-1
10-2
10-1
1
10
102
VDS (V)
Ts p = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PMN38EN_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 3 October 2007
3 of 12
PMN38EN
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
[1]
thermal resistance
see Figure 4
from junction to solder
point
Rth(j-sp)
[1]
Conditions
Min
Typ
Max
Unit
-
-
70
K/W
Mounted on a metal clad board
03aj69
102
Zth(j-sp)
(K/W)
δ = 0.5
0.2
10
0.1
δ=
P
0.05
tp
T
0.02
single pulse
t
tp
T
1
10-4
10-3
10-2
10-1
1
10
tp (s)
102
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration
6. Characteristics
Table 6.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ID = 250 μA; VGS = 0 V;
Tj = -55 °C
27
-
-
V
ID = 250 μA; VGS = 0 V;
Tj = 25 °C
30
-
-
V
0.6
-
-
V
ID =1 mA; VDS = VGS; Tj = -55 °C
-
-
2.2
V
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 7
1
1.5
2
V
VDS = 30 V; VGS = 0 V; Tj = 25 °C
-
0.01
0.1
μA
VDS = 30 V; VGS = 0 V;
Tj = 150 °C
-
-
10
μA
Static characteristics
V(BR)DSS
VGS(th)
IDSS
drain-source
breakdown voltage
gate-source threshold ID = 1 mA; VDS = VGS;
voltage
Tj = 150 °C
drain leakage current
PMN38EN_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 3 October 2007
4 of 12
PMN38EN
NXP Semiconductors
N-channel TrenchMOS logic level FET
Table 6.
Characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IGSS
gate leakage current
VGS = +20 V; VDS = 0 V;
Tj = 25 °C
-
10
100
nA
VGS = -20 V; VDS = 0 V;
Tj = 25 °C
-
10
100
nA
VGS = 10 V; ID = 3 A; Tj = 150 °C
-
49.6
60.9
mΩ
VGS = 4.5 V; ID = 2.8 A;
Tj = 25 °C; see Figure 8 and 9
-
38
46
mΩ
VGS = 10 V; ID = 3 A; Tj = 25 °C;
see Figure 8 and 9
-
31
38
mΩ
RDSon
drain-source on-state
resistance
Dynamic characteristics
QG(tot)
total gate charge
ID = 5 A; VDS = 15 V;
VGS = 4.5 V; Tj = 25 °C;
see Figure 10 and 11
-
6.1
-
nC
QGS
gate-source charge
ID = 5 A; VDS = 15 V;
VGS = 4.5 V; Tj = 25 °C;
see Figure 10 and 11
-
1.7
-
nC
QGD
gate-drain charge
ID = 5 A; VDS = 15 V;
VGS = 4.5 V; Tj = 25 °C;
see Figure 10 and 11
-
2.35
-
nC
Ciss
input capacitance
VDS = 25 V; VGS = 0 V;
f = 1 MHz; Tj = 25 °C;
see Figure 12
-
495
-
pF
Coss
output capacitance
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Tj = 25 °C;
see Figure 12
-
100
-
pF
Crss
reverse transfer
capacitance
VDS = 25 V; VGS = 0 V;
f = 1 MHz; Tj = 25 °C;
see Figure 12
-
70
-
pF
td(on)
turn-on delay time
RG(ext) = 6 Ω; RL = 12 Ω;
VDS = 15 V; VGS = 4.5 V;
Tj = 25 °C
-
14
-
ns
tr
rise time
RG(ext) = 6 Ω; RL = 12 Ω;
VDS = 15 V; VGS = 4.5 V;
Tj = 25 °C
-
19
-
ns
td(off)
turn-off delay time
VDS = 15 V; RL = 12 Ω;
VGS = 4.5 V; RG(ext) = 6 Ω;
Tj = 25 °C
-
28
-
ns
tf
fall time
RG(ext) = 6 Ω; RL = 12 Ω;
VDS = 15 V; VGS = 4.5 V;
Tj = 25 °C
-
16
-
ns
IS = 1.7 A; VGS = 0 V; Tj = 25 °C;
see Figure 13
-
0.75
1.2
V
-
22
-
ns
Source-drain diode
VSD
source-drain voltage
trr
reverse recovery time IS = 2.3 A; dIS/dt = 100 A/μs;
VGS = 0 V; VDS = 30 V; Tj = 25 °C
PMN38EN_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 3 October 2007
5 of 12
PMN38EN
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab228
20
10 6 4.5
3.9
ID
(A)
03aj73
20
ID
(A)
3.5
15
15
3.1
2.9
10
10
2.7
5
Tj = 150 °C
5
2.5
25 °C
2.3
VGS (V) = 2.1
0
0
0
0.2
0.4
0.6
0.8
VDS (V)
1
T j = 25 °C
0
1
2
3
VDS > ID × R DSon
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
03aa36
10-1
ID
(A)
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
003aab229
60
VGS (V) = 3.1
Tj = 25 °C
3.5
RDSon
(mΩ)
10-2
3.9
4.5
6
10
40
10
4
VGS (V)
-3
min
typ
max
10-4
20
10-5
10-6
0
1
2
VGS (V)
3
T j = 25 °C; VDS = VGS
0
0
10
15
ID (A)
20
T j = 25 °C
Fig 7. Sub-threshold drain current as a function of
gate-source voltage
Fig 8. Drain-source on-state resistance as a function
of drain current; typical values
PMN38EN_2
Product data sheet
5
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 3 October 2007
6 of 12
PMN38EN
NXP Semiconductors
N-channel TrenchMOS logic level FET
03af18
2
03aj76
10
VGS
(V)
a
8
1.5
6
1
4
0.5
2
0
-60
a=
0
0
60
120
Tj (°C)
0
180
R DSon
5
10
QG (nC)
15
ID = 5 A; T j = 25 °C; VDS = 15 V
R DSon (25°C )
Fig 9. Normalized drain-source on-state resistance
factor as a function of junction temperature
Fig 10. Gate-source voltage as a function of gate
charge; typical values
03aj75
103
Ciss
C
(pF)
VDS
ID
102
VGS(pl)
Coss
Crss
VGS(th)
VGS
QGS1
QGS2
QGS
QGD
QG(tot)
10
10-1
1
003aaa508
10
VDS (V)
102
VGS = 0 V ; f = 1 M H z
Fig 11. Gate charge waveform definitions
Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PMN38EN_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 3 October 2007
7 of 12
PMN38EN
NXP Semiconductors
N-channel TrenchMOS logic level FET
03aj74
20
IS
(A)
15
10
150 °C
5
Tj = 25 °C
0
0
0.5
1
VSD (V)
1.5
VGS = 0 V
Fig 13. Source current as a function of source-drain voltage; typical values
PMN38EN_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 3 October 2007
8 of 12
PMN38EN
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic surface-mounted package (TSOP6); 6 leads
D
SOT457
E
B
y
A
HE
6
5
X
v M A
4
Q
pin 1
index
A
A1
c
1
2
3
Lp
bp
e
w M B
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
A1
bp
c
D
E
e
HE
Lp
Q
v
w
y
1.1
0.9
0.1
0.013
0.40
0.25
0.26
0.10
3.1
2.7
1.7
1.3
0.95
3.0
2.5
0.6
0.2
0.33
0.23
0.2
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
SOT457
JEITA
SC-74
EUROPEAN
PROJECTION
ISSUE DATE
05-11-07
06-03-16
Fig 14. Package outline SOT457 (TSOP6)
PMN38EN_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 3 October 2007
9 of 12
PMN38EN
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PMN38EN_2
20071003
Product data sheet
-
PMN38EN_1
Modifications:
PMN38EN_1
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
Legal texts have been adapted to the company name where appropriate.
20060113
Product data sheet
PMN38EN_2
Product data sheet
-
-
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 3 October 2007
10 of 12
PMN38EN
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status[1][2]
Product status[3]
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
Definition
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
PMN38EN_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 3 October 2007
11 of 12
PMN38EN
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
10
11
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics . . . . . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Contact information. . . . . . . . . . . . . . . . . . . . . 11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 October 2007
Document identifier: PMN38EN_2
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