PN5331B3HN
Near Field Communication (NFC) controller
Rev. 3.4 — 29 November 2017
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Product data sheet
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1. General description
The PN533 is a highly integrated transceiver module for contactless communication at
13.56 MHz based on the 80C51 microcontroller core. It supports 6 different operating
modes:
•
•
•
•
•
•
ISO/IEC 14443A/MIFARE Reader/Writer
FeliCa Reader/Writer
ISO/IEC 14443B Reader/Writer
ISO/IEC 14443A/MIFARE Card MIFARE 1 KB or MIFARE 4 KB emulation
FeliCa Card emulation
ISO/IEC 18092, ECMA 340 Peer-to-Peer
The PN533 implements a demodulator and decoder for signals from
ISO/IEC 14443A/MIFARE compatible cards and transponders. The PN533 handles the
complete ISO/IEC 14443A framing and error detection (Parity & CRC).
The PN533 supports MIFARE 1 KB or MIFARE 4 KB emulation products. The PN533
supports contactless communication using MIFARE Higher transfer speeds up to
424 kbit/s in both directions.
The PN533 can demodulate and decode FeliCa coded signals. The PN533 handles the
FeliCa framing and error detection. The PN533 supports contactless communication
using FeliCa Higher transfer speeds up to 424 kbit/s in both directions.
The PN533 supports layers 2 and 3 of the ISO/IEC 14443 B Reader/Writer
communication scheme, except anticollision. This must be implemented in firmware as
well as upper layers.
In card emulation mode, the PN533 is able to answer to a Reader/Writer command either
according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The PN533
generates the load modulation signals, either from its transmitter or from the LOADMOD
pin driving an external active circuit. A complete secure card functionality is only possible
in combination with a secure IC using the NFC-WI/S2C interface.
Compliant to ECMA 340 and ISO/IEC 18092 NFCIP-1 Passive and Active communication
modes, the PN533 offers the possibility to communicate to another NFCIP-1 compliant
device, at transfer speeds up to 424 kbit/s.The PN533 handles the complete NFCIP-1
framing and error detection.
The PN533 transceiver can be connected to an external antenna for Reader/Writer or
Card/PICC modes, without any additional active component.
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Near Field Communication (NFC) controller
The PN533 supports the following host interfaces:
• USB 2.0 full speed interface (bus powered or non bus powered)
• High Speed UART (HSU)
PN533 has also a master I2C interface enabling the drive on an I2C peripheral (i.e.
memory).
In addition, a power switch is included to supply power to a secure IC.
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2. Features and benefits
80C51 microcontroller core with 45056 bytes ROM and 1224 bytes RAM
Highly integrated demodulator and decoder
Buffered output drivers to connect an antenna with minimum number of external
components
Integrated RF level detector
Integrated data mode detector
Supports ISO/IEC 14443A/MIFARE
Supports ISO/IEC 14443B (Reader/Writer mode only)
Typical operating distance in Reader/Writer mode for communication to
ISO/IEC 14443A/MIFARE, ISO/IEC 14443B or FeliCa cards up to 50 mm depending
on antenna size and tuning
Typical operating distance in NFCIP-1 mode up to 50 mm depending on antenna size,
tuning and power supply
Typical operating distance in ISO/IEC 14443A/MIFARE or FeliCa card emulation mode
of approximately 100 mm depending on antenna size, tuning and external field
strength
Supports MIFARE 1 KB or MIFARE 4 KB emulation encryption in Reader/Writer mode
and MIFARE higher transfer speed communication at 212 kbit/s and 424 kbit/s
Supports contactless communication according to the FeliCa protocol at 212 kbit/s and
424 kbit/s
Integrated RF interface for NFCIP-1 up to 424 kbit/s
Possibility to communicate on the RF interface above 424 kbit/s using external analog
components
Supported host interfaces
USB 2.0 full speed interface
High-speed UART
Restricted I2C master interface to control an external I2C EEPROM
Dedicated host interrupts
Low power modes
Hard-Power-down mode
Soft-Power-down mode
Automatic wake-up on HSU interfaces when device is in Power-down mode
Programmable timers
27.12 MHz Crystal oscillator
On-Chip PLL to generate internally The 96 MHz for the USB interface
Power modes
USB bus power mode
2.5 V to 3.6 V power supply operating range in non USB bus power mode
Power switch for external secure companion chip
Dedicated IO ports for external device control
Integrated antenna detector for production tests
ECMA 373 NFC-WI interface to connect an external secure IC
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3. Applications
Computing application
Consumer applications
4. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
VBUS
USB Supply Voltage (USB
mode)
Supply Voltage (non USB mode) VBUS = DVDDVSS = 0 V
TVDD, AVDD, DVDD
Supply Voltage
TVDD = AVDD = DVDD
VSS = 0 V
[1]
Min
Typ
Max
Unit
4.02
5
5.25
V
2.5
3.3
3.6
V
2.5
3.3
3.6
V
PVDD
Supply Voltage for host interface VSS = 0 V
1.6
3.6
V
SVDD
Supply Voltage for SAM
interface
VSS = 0 V
(SVDD Switch Enabled)
DVDD
-0.1
DVDD
V
IVBUS
Maximum load current (USB
mode)
measured on VBUS
150
mA
Maximum Inrush current
limitation
At power up(curlimoff = 0)
100
mA
IHPD
Hard Power Down Current (Not
powered from USB)
AVDD = DVDD = TVDD = PVDD
= 3 V, RF level detector off
10
A
ISPD
Soft Power down Current(Not
powered from USB)
AVDD = DVDD = TVDD = PVDD
= 3 V, RF level detector on
30
A
Isuspend
USB suspend Current
AVDD = DVDD = TVDD = PVDD
= 3 V, RF level detector on
(without resistor on DP/DM)
250
A
IDVDD
Digital Supply Current
AVDD = DVDD = TVDD = PVDD
= 3 V, RF level detector on,
SVDD switch off
ISVDD
SVDD Supply Current
SVDD = 3 V, SVDD switch On
IAVDD
Analog Supply Current
AVDD = DVDD = TVDD = PVDD
= 3 V, RF level detector on
6
ITVDD
Transmitter Supply Current
During RF Transmission,
TVDD=3V
60
Ptot
continuous total power
dissipation.
Tamb = -30 to +85 C
Tamb
operating ambient temperature
[1]
[1]
15
mA
30
-30
mA
mA
100
mA
0.55
W
+85
C
DVDD, AVDD and TVDD shall always be at the same supply voltage.
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5. Ordering information
Table 2.
Ordering information
Type number
Package
PN5331B3HN/C270[1]
[1]
Name
Description
Version
HVQFN40
Heatsink Very thin Quad Flat package; 40 pins, plastic,
body 6 x 6 x 0.85 mm; leadless; MSL level 2.
SOT618-1
Refer to Section 17.4 “Licenses”
6. Block diagram
DVDD
PN533
REGULATOR
SVDD
SWITCH
SVDDswitch
I²2C
I2c
SIGOUT SIGIN
POR
SDA/SCL
VBUS
RSTPD_N
sam_switch_en
sam_switch_overload
UART
HSU
Xramif
RAM
ROMif
ROM
P34
IOs
Ports
80C51
MATX
Timer0/1
Timer2
TCB
FIFO
Manager
Intc
CL UART
RAM
FiFO
SFRif
Hostif
PVDD
TIMER
USB
MIFARE Classic Unit
Framing Gen. & Check
Signal Processing
Osc27
AVDD
Clock
Generator
VMID
BG
Sensor
RF
Detector
ADC
Transmit
Control
Demod
Antenna
Driver
TVDD
PCR
Clock
Recovery
USB PLL
Fig 1. Block diagram of PN533
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7. Pinning information
7.1 Pinning
Fig 2. Pin configuration for HVQFN 40 (SOT618-1)
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7.2 Pin description
Table 3.
PN533 Pin description
Symbol
Pin
Type Pad Ref
Voltage
Description
DVSS
1
PWR
Digital ground
LOADMOD
2
O
TVSS1
3
PWR
TX1
4
O
TVDD
5
PWR
TX2
6
O
TVSS2
7
PWR
Transmitter ground: supplies the output stage of TX1 and TX2
AVDD
8
PWR
Analog power supply
VMID
9
PWR AVDD
Internal reference voltage: This pin delivers the internal reference voltage.
RX
10
I
Receiver Input: Input pin for the reception signal, which is the load modulated
13.56 MHZ energy carrier from the antenna circuit
AVSS
11
PWR
AUX1
12
O
DVDD
Auxiliary output 1: This pin delivers analog and digital test signals
AUX2
13
O
DVDD
Auxiliary output 2: This pin delivers analog and digital test signals
DVSS
14
PWR
OSCIN
15
I
AVDD
Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This
pin is also the input for an externally generated clock (fosc = 27.12 MHZ).
OSCOUT
16
O
AVDD
Crystal Oscillator output: Output of the inverting amplifier of the oscillator.
I0
17
I
DVDD
I1
18
I
DVDD
Interface mode lines: selects the used host interface (refer to Table 75
“Config I0_I1 register (address 6103h) bit allocation”for details).
In test mode I0 is used as test signals.
TESTEN
19
I
DVDD
Test enable pin:
DVDD
Load Modulation output provides digital signal for FeliCa and MIFARE card
operating mode
Transmitter ground: supplies the output stage of TX1 and TX2
TVDD
Transmitter 1: transmits modulated 13.56 MHz energy carrier
TVDD
Transmitter2: delivers the modulated 13.56 MHz energy carrier
Transmitter power supply: supplies the output stage of TX1 and TX2
AVDD
Analog ground
Digital Ground
When set to 1 enable the test mode.
When set to 0 reset the TCB and disable the access to the test mode.
P35
20
IO
DVDD
General purpose IO signal
P70_IRQ
21
IO
PVDD
Interrupt request: Output to signal an interrupt event to the host (Port 7 bit 0)
RSTOUT
22
O
PVDD
Output reset signal. When Low it indicates that the circuit is in reset state.
DVSS
23
PWR
DM
24
IO
Digital Ground
PVDD
USB D- data line in USB mode or TX in HSU mode (refer to Table 74 “HOST
interface selection” on page 47for details).
In test mode this signal is used as input and output test signal
DP
25
IO
PVDD
USB D+ data line in USB mode or RX in HSU mode (refer to Table 74 “HOST
interface selection” on page 47 for details).
In test mode this signal is used as input and output test signal.
PVDD
26
PWR
IO pad power supply
DELATT
27
O
PVDD
Optional output for an external 1.5 KOhms resistor connection on D+.
P30
28
IO
PVDD
General purpose IO signal. Can be configured to act either as RX line of the
second serial interface UART or general purpose IO.
In test mode this signal is used as input and output test signal.
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Table 3.
PN533 Pin description …continued
Symbol
Pin
Type Pad Ref
Voltage
Description
P31
29
IO
General purpose IO signal. Can be configured to act either as TX line of the
second serial interface UART or general purpose IO.
PVDD
In test mode this signal is used as input and output test signal.
P32_INT0
30
IO
PVDD
General purpose IO signal. Can also be used as an interrupt source
In test mode this signal is used as input and output test signal.
P33_INT1
31
IO
PVDD
General purpose IO signal. Can be used to generate an HZ state on the
output of the selected interface for the Host communication and to enter into
power down mode without resetting the internal state of PN533.
SCL
32
IO
DVDD
I2C clock line - open drain in output mode
SDA
33
IO
DVDD
I2C data line - open drain in output mode
P34
34
IO
SVDD
General purpose IO signal or clk signal for the SAM
SIGOUT
35
O
SVDD
Contactless communication interface output: delivers a serial data stream
according to NFCIP-1 and output signal for the SAM.
In test mode this signal is used as input and output test signal.
In test mode this signal is used as test signal output.
SIGIN
36
I
SVDD
Contactless communication interface input: accepts a digital, serial data
stream according to NFCIP-1 and input signal from the SAM.
In test mode this signal is used as test signal input.
SVDD
37
PWR
RSTPD_N
38
I
Output power for SAM power supply. Switched on by Firmware with an
overload detection. Used as a reference voltage for SAM communication.
PVDD
Reset and Power Down: When LOW, internal current sources are switched
off, the oscillator is inhibited, and the input pads are disconnected from the
outside world.
With a negative edge on this pin the internal reset phase starts.
DVDD
39
PWR
Digital Power Supply
VBUS
40
PWR
USB power supply.
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8. Functional description
8.1 80C51
The PN533 is controlled via an embedded 80C51 microcontroller core (for more details
http://www.standardics.nxp.com/support/documents/microcontrollers/?scope=80C51). Its
principle features are listed below:
• 6-clock cycle CPU. One machine cycle comprises 6 clock cycles or states (S1 to S6).
An instruction needs at least one machine cycle.
•
•
•
•
•
•
•
•
•
ROM interface
RAM interface to embedded IDATA and XRAM memories (see Figure 4 on page 10)
Peripheral interface (PIF)
Power control module to manage the CPU power consumption
Clock module to control CPU clock during Shutdown and Wake-up modes
Port module interface to configure I/O pads
Interrupt controller
Three timers
Debug UART
The block diagram describes the main blocks described in this 80C51 section.
PN533
Fig 3. PN533 80C51 block description
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8.1.1 PN533 memory map
The memory map of PN533 is composed of 2 main memory spaces: data memory and
program memory. The following figure illustrates the structure.
ROM
XRAM
FFFFH
RE
SE
RV
ED
RE
SE
RV
ED
FFFFH
A000H
BFFFH
6000H
5FFFH
SFR
RAM
FFH
128 BYTES RAM
INDIRECT
ADDRESSING
ONLY
Special Function
Registers
DIRECT
ADDRESSING
7FH
00H
128 BYTES RAM
DIRECT
&
INDIRECT
ADDRESSING
PERIPHERAL
AREA
PIF
RE
SE
RV
ED
8000H
7FFFH
45056 BYTES
ROM
03CFH
976 BYTES
XRAM
0000H
0000H
IDATA
Data Memory Area
Program Memory Area
Fig 4. PN533 memory map overview
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8.1.2 Data memory
Data memory is itself divided into 2 spaces:
• 384-byte IDATA with byte-wide addressing
– 258-byte RAM
– 128-byte SFR
• 1 bank of 64 KB extended RAM (XRAM) with 2-byte-wide addressing
8.1.2.1
IDATA memory
The IDATA memory is mapped into 3 blocks, which are referred as Lower IDATA RAM,
Upper IDATA RAM, and SFR. Addresses to these blocks are byte-wide, which implies an
address space of only 256 bytes. However, 384 bytes can be addressed within IDATA
memory through the use of direct and indirect address mechanisms.
• Direct addressing: the operand is specified by an 8-bit address field in the instruction.
• Indirect addressing: the instruction specifies a register where the address of the
operand is stored.
For the range 80h to FFh, direct addressing will access the SFR space; indirect
addressing accesses Upper IDATA RAM. For the range 00h to 7Fh, Lower IDATA RAM is
accessed, regardless of addressing mode. This behavior is summarized in the table
below:
Table 4.
Address
IDATA memory addressing
Addressing mode
Direct
Indirect
00h to 7Fh
Lower IDATA RAM
Lower IDATA RAM
80h to FFh
SFRs
Upper IDATA RAM
The SFRs and their addresses are described in the Table 5:
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Address
SFR map of NFC controller
Bitaddressable
IP1
B
IE1
ACC
I2CC0N
PSW
T2CON
Byte-addressable
XRAMP
CIU_Status2
CIU_FIFOData
CIU_FIFOLevel
I2CSTA
CIU_Command
T2MOD
I2CDAT
CIU_CommIEn
RCAP2L
I2CADR
CIU_DivIEn
RCAP2H
FITEN
SBUF
FDATA
RWL
T01MOD
SP
T0L
DPL
IP0
P3
IE0
S0CON
T01CON
P3CFGA
P7CFGA
CIU_WaterLevel
Address
P3CFGB
P7CFGB
CIU_Control
CIU_BitFraming
P7
CIU_Coll
CIU_Status1
CIU_CommIrq
T2L
CIU_DivIrq
T2H
CIU_Error
HSU_STA
FSIZE
TWL
HSU_CTR
HSU_PRE
HSU_CNT
FIFOFS
FIFOFF
SFF
T1L
DPH
T0H
T1H
FIT
PCON
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
9Fh
97h
8Fh
87h
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F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
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Table 5.
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Near Field Communication (NFC) controller
8.1.2.2
XRAM memory
The XRAM memory is divided into 2 memory spaces:
• 0000h to 5FFFh: reserved for addressing embedded RAM. For the PN533, only
accesses between 0000h and 03C7h are valid.
• 6000h to 7FFFh: reserved for addressing embedded peripherals. This space is
divided into 32 regions of 256 bytes each. Addressing can be performed using R0 or
R1 and the XRAMP SFR.
The Table 6 depicts the mapping of internal peripherals into XRAM.
Table 6.
Peripheral mapping into XRAM memory space
Base
Address
End
Address
Description
6000h
60FFh
Reserved.
6100h
61FFh
IOs and miscellaneous registers configuration
Refer to Section 8.2 “General purpose IOs configurations” on page 37
6200h
62FFh
Power Clock and Reset controller
Refer to Section 8.5.10 “PCR extension registers” on page 102
6300h
633Fh
Contactless Unit Interface
Refer to Section 8.6 “Contactless Interface Unit (CIU)” on page 108
6340h
FFFFh
Reserved
XRAM is accessed via the dedicated MOVX instructions. There are two access modes:
• 16-bit data pointer (DPTR): the full XRAM address space can be accessed.
• paging mechanism: the upper address byte is stored in the SFR register XRAMP; the
lower byte is stored in either R1 or R0.
The Figure 5 illustrates both mechanisms.
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XRAM
FFFFH
XRAMP = FFh
XRAMP = FFh
FFh
00h
FFh
00h
40 kB
Reserved
XRAMP = 82h
XRAMP = 81h
XRAMP = 80h
XRAMP = 7Fh
XRAMP = 7Eh
MOVX @DPTR,A
MOVX A,@DPTR
XRAMP = 62h
XRAMP = 61h
8000H
7FFFH
XRAMP = 60h
XRAMP = 5Fh Peripheral 32
XRAMP = 5Eh Peripheral 31
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
MOVX @Ri,A
MOVX A,@Ri
PERIPHERAL
AREA
XRAMP = 42h Peripheral 3
XRAMP = 41h Peripheral 2
6000H
5FFFH
XRAMP = 40h Peripheral 1
XRAMP = 3Fh
XRAMP = 3Eh
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
XRAM
XRAMP = 02h
XRAMP = 01h
0000H
XRAMP = 00h
FFh
00h
FFh
00h
FFh
00h
Fig 5. Indirect addressing of XRAM memory space
8.1.3 Program memory
PN533 program memory ranges from 0000h to AFFFh, which is physically mapped to the
44 KB ROM.
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8.1.4 PCON module
The Power Control (PCON) module is configured using the PCON SFR register.
Table 7.
PCON register (SFR: address 87h) bit allocation
Bit
7
Symbol
6
5
4
0
0
0
R/W
R
R
SMOD
Reset
Access
Table 8.
3
2
CPU_PD
-
0
0
0
0
0
R
R
R
R/W
R/W
-
1
0
Description of PCON bits
Bit
Symbol
Description
7
SMOD
Serial MODe:
When set to logic level 1, the baud rate of the Debug UART is doubled
6 to 2
-
Reserved.
1
CPU_PD
Power-down:
When set to logic level 1, the microcontroller goes in Power-down mode
0
Reserved
This bit should only ever contain logic level 0.
8.1.5 Interrupt Controller
The interrupt controller has the following features:
•
•
•
•
8.1.5.1
1interrupt source
Interrupt enable registers IE0 and IE1
Interrupt priority registers IP0 and IP1
Wake-up from Power-down state
Interrupt vectors
The mapping between interrupt sources and interrupt vectors is shown in Table 9.
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Table 9.
Interrupt vector
Interrupt
number
Interrupt
vector
Interrupt sources
Incremental priority level
(conflict resolution level)
0
0003h
External P32_INT0
Highest
1
000Bh
Timer0 interrupt
2
0013h
External P33_INT1
3
001Bh
Timer1 interrupt
4
0023h
Debug UART interrupt
5
002Bh
Timer2 interrupt
6
0033h
NFC-WI interrupt
7
003Bh
Reserved
8
0043h
Reserved
9
004Bh
CIU interrupt 1
10
0053h
CIU interrupt 0
11
005Bh
I2C interrupt
12
0063h
FIFO or HSU interrupts
13
006Bh
USB interrupt
14
0073h
General Purpose IRQ
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8.1.5.2
Interrupt enable: IE0 and IE1 registers
Each interrupt source can be individually enabled or disabled by setting a bit in IE0 or IE1.
In register IE0, a global interrupt enable bit can be set to logic level 0 to disable all
interrupts at once.
The 2 following tables describe IE0.
Table 10.
Interrupt controller IE0 register (SFR: address A8h) bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
IE0_7
IE0_6
IE0_5
IE0_4
IE0_3
IE0_2
IE0_1
IE0_0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Access
Table 11.
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Description of IE0 bits
Bit
Symbol
Description
7
IE0_7
Global interrupt enable
When set to logic 1, the interrupts can be enabled.
When set to logic 0, all the interrupts are disabled.
6
IE0_6
NFC-WI counter interrupt enable
When set to logic 1, NFC-WI interrupt is enabled.
5
IE0_5
Timer2 interrupt enable
When set to logic 1, Timer2 interrupt is enabled.
4
IE0_4
Debug UART interrupt enable
When set to logic 1, Debug UART interrupt is enabled.
3
IE0_3
Timer1 interrupt enable
When set to logic 1, Timer1 interrupt is enabled
2
IE0_2
P33_INT1 interrupt enable
When set to logic 1, P33_INT1 pin interrupt is enabled.
The polarity of P33_INT1 can be inverted (see Table 75 on page 47).
1
IE0_1
Timer0 interrupt enable
When set to logic 1, Timer0 interrupt is enabled.
0
IE0_0
P32_INT0 interrupt enable
When set to logic 1, P32_INT0 pin interrupt is enabled.
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The 2 following tables describe IE1.
Table 12.
Interrupt controller IE1 register (SFR: address E8h) bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
IE1_7
IE1_6
IE1_5
IE1_4
IE1_3
IE1_2
-
-
Reset
Access
Table 13.
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description of IE1 bits
Bit
Symbol
Description
7
IE1_7
General purpose IRQ interrupt enable.
When set to logic 1, enables interrupt function of P34, P35, P50_SCL and P71
according to their respective enable and level control bits. See Table 19 on
page 19, Table 138 on page 104 and Table 144 on page 107.
6
IE1_6
USB interrupt enable.
When set to logic level 1, enables USB interrupt.
5
IE1_5
FIFO and HSU interrupt enable.
When set to logic 1, enables FIFO interrupts, SPI interrupts, HSU interrupt.
4
IE1_4
I2C interrupt enable.
When set to logic 1, enables I2C interrupt.
3
IE1_3
2
IE1_2
CIU interrupt 0 enable.
When set to logic 1, enables CIU interrupt 0: CIU_IRQ_0.
CIU interrupt 1 enable.
When set to logic 1, enables the CIU interrupt 1: CIU_IRQ_1.
1 to 0 -
8.1.5.3
Reserved. This bit must be set to logic level 0.
Interrupt prioritization: IP0 and IP1 registers
Each interrupt source can be individually programmed to be one of two priority levels by
setting or clearing a bit in the interrupt priority registers IP0 and IP1. If two interrupt
requests of different priority levels are received simultaneously, the request with the high
priority is serviced first. On the other hand, if the interrupts are of the same priority,
precedence is resolved by comparing their respective conflict resolution levels (see
Table 9 on page 15
for details). The processing of a low priority interrupt can be interrupted by one with a high
priority.
A RETI (Return From Interrupt) instruction jumps to the address immediately succeeding
the point at which the interrupt was serviced. The instruction found at the return address
will be executed, prior to servicing any pending interrupts.
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The 2 following tables describe IP0.
Table 14.
Interrupt controller IP0 register (SFR: address B8h) bit allocation
Bit
Symbol
Reset
Access
Table 15.
7
6
5
4
3
2
1
0
IP0_7
IP0_6
IP0_5
IP0_4
IP0_3
IP0_2
IP0_1
IP0_0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description of IP0 bits
Bit
Symbol
Description
7
IP0_7
Reserved
6
IP0_6
When set to logic level 1, NFC-WI interrupt is set to high priority.
5
IP0_5
When set to logic level 1, Timer2 interrupt is set to high priority.
4
IP0_4
When set to logic level 1, Debug UART interrupt is set to high priority.
3
IP0_3
When set to logic level 1, Timer1 interrupt is set to high priority.
2
IP0_2
When set to logic level 1, external P33_INT1 pin is set to high priority.
1
IP0_1
When set to logic level 1, Timer0 interrupt is set to high priority.
0
IP0_0
When set to logic level 1, external P32_INT0 pin is set to high priority.
The 2 following tables describe IP1.
Table 16.
Interrupt controller IP1 register (SFR: address F8h) bit allocation
Bit
Symbol
Reset
Access
Table 17.
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7
6
5
4
3
2
1
0
IP1_7
IP1_6
IP1_5
IP1_4
IP1_3
IP1_2
-
0
0
0
0
0
0
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description of IP1 bits
Bit
Symbol
Description
7
IP1_7
When set to logic level 1, General Purpose IRQ interrupt is set to high
priority.
6
IP1_6
When set to logic level 1, USB interrupt is set to high priority.
5
IP1_5
When set to logic level 1, combined FIFO and HSU interrupt is set to
high priority.
4
IP1_4
When set to logic level 1, I2C interrupt is set to high priority.
3
IP1_3
When set to logic level 1, CIU interrupt 0 is set to high priority.
2
IP1_2
When set to logic level 1, CIU interrupt 1 is set to high priority.
1
-
Reserved. This bit must be set to logic level 0.
0
IP1_0
When set to logic level 1, interrupt number 7 is set to high priority.
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8.1.5.4
General purpose IRQ control
The general purpose interrupts are controlled by register GPIRQ.
NOTE: this is not a standard feature of the 8051.
Table 18.
GPIRQ register (address 6107h) bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
gpirq_
level_
P71
gpirq_
level_
DP
gpirq_
level_
P35
gpirq_
level_
P34
gpirq_
enable
_P71
gpirq_
enable_
DP
gpirq_
enable_
P35
gpirq_
enable_
P34
Reset
Access
Table 19.
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description of GPIRQ bits
Bit Symbol
Description
7
-
6
gpirq_level_DP
Configures the polarity of signal on P50 to generate a GPIRQ
interrupt event (assuming gpirq_enable_P50 is set).
When set to logic 0, an interrupt will be generated if P50_SCL is at logic 0.
When set to logic 1, an interrupt will be generated if P50_SCL is at logic 1.
5
gpirq_level_P35
Configures the polarity of signal on P35 to generate a GPIRQ
interrupt event (assuming gpirq_enable_P35 is set).
When set to logic 0, an interrupt will be generated if P35 is at logic 0.
When set to logic 1, an interrupt will be generated if P35 is at logic 1.
4
gpirq_level_P34
Configures the polarity of signal on P34 to generate a GPIRQ
interrupt event (assuming gpirq_enable_P34 is set).
When set to logic 0, an interrupt will be generated if P34 is at logic 0.
When set to logic 1, an interrupt will be generated if P34 is at logic 1.
Remark: If hide_svdd_sig of the register control_rngpower is set and
gpirq_enable_P34 is also set then this bit will be asserted independently
of the level on the pad P34.
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3
-
2
gpirq_enable_DP
1
gpirq_enable_P35 When set to logic 1, enables pad P35 to generate a GPIRQ interrupt
event.
0
gpirq_enable_P34 When set to logic 1, enables pad P34 to generate a GPIRQ interrupt
event.
When set to logic 1, enables pad DP to generate a GPIRQ interrupt event.
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8.1.6 Timer0/1 description
Timer0/1 are general purpose timer/counters. Timer0/1 has the following functionality:
•
•
•
•
Configurable edge or level detection interrupts
Timer or counter operation
4 timer/counter modes
Baud rate generation for Debug UART
Timer0/1 comprises two 16-bit timer/counters: Timer0 and Timer1. Both can be configured
as either a timer or an event counter.
Each of the timers can operate in one of four modes:
•
•
•
•
Mode 0: 13-bit timer/counter
Mode 1: 16-bit timer/counter
Mode 2: 8-bit timer/counter with programmable preload value
Mode 3: two individual 8-bit timer/counters (Timer0 only)
In the ‘timer’ function, the timer/counter is incremented every machine cycle. The count
rate is 1/6 of the CPU clock frequency (CPU_CLK).
In the ‘counter’ function, the timer/counter is incremented in response to a 1-to-0 transition
on the input pins P34 / SIC_CLK (Timer0) or P35 (Timer1). In this mode, the external input
is sampled during state S5 of every machine cycle. If the associated pin is at logic level 1
for a machine cycle, followed by logic level 0 on the next machine cycle, the count is
incremented. The new count value appears in the timer/counter in state S3 of the machine
cycle following the one in which the transition was detected. The maximum count rate is
1/12 of the CPU_CLK frequency. There are no restrictions on the duty cycle of the
external input signal but to ensure that a given level is sampled at least once before it
changes, it should be held for at least one full machine cycle.
The overflow output ‘t1_ovf’ of Timer1 can be used as a baud rate generator for the
Debug UART. The Timer1 interrupt should be disabled in this case. For most applications
which drive the Debug UART, Timer1 is configured for ‘timer’ operation and in auto-reload
mode.
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8.1.6.1
Timer0/1 registers
The Timer0/1 module contains six Special Function Registers (SFRs) which can be
accessed by the CPU.
Table 20.
Timer0/1 Special Function registers list
Name
Size
[bytes]
Address
Offset
Description
Access
T01CON
1
88h
Timer0/1 control register
R/W
T01MOD
1
89h
Timer0/1 mode register
R/W
T0L
1
8Ah
Timer0 timer/counter lower byte
R/W
T1L
1
8Bh
Timer1 timer/counter lower byte
R/W
T0H
1
8Ch
Timer0 timer/counter upper byte
R/W
T1H
1
8Dh
Timer1 timer/counter upper byte
R/W
The firmware performs a register read in state S5 and a register write in state S6. The
hardware loads bits TF0 and TF1 of the register T01CON during state S2 and state S4
respectively. The hardware loads bits IE0 and IE1 of the register T01CON during state S1
and reset these bits during state S2. The registers T0L, T0H, T1L, T1H are updated by the
hardware during states S1, S2, S3 and S4 respectively. At the end of a machine cycle, the
firmware load has overrided the hardware load as the firmware writes in state S6.
Table 21.
Timer0/1 SFR registers CPU state access
CPU STATE
Register
T01CON
Bit
S1
TF0
S2
S3
HW read
TF1
IE0/IE1
TOL
TOH
T1L
HW read
HW write
HW reset
HW write
HW write
HW write
T1H
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S4
HW write
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S6
SW read
SW write
SW read
SW write
SW read
SW write
SW read
SW write
SW read
SW write
SW read
SW write
SW read
SW write
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8.1.6.2
T01CON register
The register is used to control Timer0/1 and report its status.
Table 22.
Timer0/1 T01CON register (SFR address 88h), bit allocation
Bit
Symbol
Reset
Access
Table 23.
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description of Timer0/1 T01CON register bits
Bit
Symbol
Description
7
TF1
Timer1 overflow.
Set to logic level 1 by hardware on a Timer1 overflow. The flag is set to
logic level 0 by the CPU after 2 machine cycles.
6
TR1
Timer1 run control.
Set by firmware only. When set to logic level 1, Timer1 is enabled.
5
TF0
Timer0 overflow.
Set by hardware on a Timer0 overflow. The flag is set to logic level 0 by
the CPU after 2 machine cycles.
4
TR0
Timer0 run control.
Set by firmware only.
When set to logic level 1, Timer0 is enabled.
3
IE1
External Interrupt1 event.
Set to logic level 1 by hardware when an external interrupt is detected on
P33_INT1.
2
IT1
External Interrupt1 control.
Set by firmware only. When set to logic level 1, Interrupt1 triggers on a
falling edge of P33_INT1.
When set to logic level 0, Interrupt1 triggers on a low level of P33_INT1.
1
IE0
External Interrupt0 event.
Set to logic level 1 by hardware when an external interrupt is detected on
P32_INT0.
0
IT0
External Interrupt0 control.
Set by firmware only. When set to logic level 1, Interrupt0 triggered by a
falling edge on P32_INT0.
When set to logic level 0, Interrupt0 triggered by a low level on
P32_INT0.
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8.1.6.3
T01MOD register
This register is used to configure Timer0/1.
Table 24.
Timer 0/1 T01MOD register (SFR address 89h), bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
GATE1
C/T1
M11
M10
GATE0
C/T0
M01
M00
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Access
Table 25.
Description of T01MOD bits
Bit
Symbol
Description
7
GATE1
Timer1 gate control. Set by firmware only.
When set to logic level 1, Timer1 is enabled only when P33_INT1 is high
and bit TR1 of register T01CON is set.
When set to logic 0, Timer1 is enabled.
6
C/T1
Timer1 timer/counter selector. Set by firmware only.
When set to logic level 1, Timer1 is set to counter operation.
When set to logic level 0, Timer1 is set to timer operation.
5 to 4
M[11:10]
Timer1 mode. Set by firmware only.
•
Mode 0: M11 = 0 and M10 = 0
– 8192 counter
– T1L serves as a 5-bit prescaler
•
Mode 1: M11 = 0 and M10 = 1
–
16-bit timer/counter
– T1H and T1L are cascaded
•
Mode 2: M11 = 1 and M10 = 0
– 8-bit auto-reload timer/counter.
– T1H stores value to be reloaded into T1L each time T1L overflows.
•
Mode 3: M11 = 1 and M10 = 1
– Timer1 is stopped (count frozen).
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Table 25.
Description of T01MOD bits …continued
Bit
Symbol
Description
3
GATE0
Timer0 gate control. Set by firmware only.
When set to logic level 1, Timer0 is enabled only when P32_INT0 is high
and bit TR0 of register T01CON is set.
When set to logic level 0, Timer0 is enabled.
2
C/T0
Timer0 timer/counter selector. Set by firmware only.
When set to logic level 1, Timer0 is set to counter operation.
When set to logic level 0, Timer0 is set to timer operation.
1 to 0
8.1.6.4
M[01:00]
Timer0 mode. Set by firmware only.
•
Mode 0: M01 = 0 and M00 = 0
– 8192 timer
– T0L acts as a 5-bit prescaler.
•
Mode 1: M01 = 0 and M00 = 1
– 16-bit timer/counter
– T0H and T0L are cascaded.
•
Mode 2: M01 = 1 and M00 = 0
– 8-bit auto-reload timer/counter
– T0H stores value to be reloaded into T0L each time T0L overflows.
•
Mode 3: M01 = 1 and M00 = 1
– Timer0 split into two 8-bit timer/counters T0H and T0L
– T0H is controlled by the control bit of Timer1: bit TR1 of register
T01CON
– T0L is controlled by standard Timer0 control: “{P32_INT0 OR
(NOT GATE0)} AND bit TR0”.
T0L and T0H registers
These are the actual timer/counter bytes for Timer0: T0L is the lower byte; T0H is the
upper byte.
Table 26.
Bit
Symbol
Reset
Access
Table 27.
6
5
4
3
2
1
0
T0L.6
T0L.5
T0L.4
T0L.3
T0L.2
T0L.1
T0L.0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description of T0L bits
Symbol
7:0
T0L.7 to T0L.0 Timer0 timer/counter lower byte
Bit
Symbol
Reset
Access
Table 29.
Product data sheet
COMPANY PUBLIC
7
T0L.7
Bit
Table 28.
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Timer0/1 T0L register (SFR address 8Ah), bit allocation
Description
Timer0/1 T0H register (SFR address 8Ch), bit allocation
7
6
5
4
3
2
1
0
T0H.7
T0H.6
T0H.5
T0H.4
T0H.3
T0H.2
T0H.1
T0H.0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description of T0H bits
Bit
Symbol
7 to 0
T0H.7 to T0H.0 Timer0 timer/counter upper byte
Description
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8.1.6.5
T1L and T1H registers
These are the actual timer/counter bytes for Timer1. T1L is the lower byte, T1H is the
upper byte.
Table 30.
Timer0/1 T1L register (SFR address 8Bh), bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
T1L.7
T1L.6
T1L.5
T1L.4
T1L.3
T1L.2
T1L.1
T1L.0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Access
Table 31.
Description of T1L bits
Bit
Symbol
7 to 0
T1L.7 to T1L.0 Timer1 timer/counter lower byte
Table 32.
Timer0/1 T1H register (SFR address 8Dh), bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
T1H.7
T1H.6
T1H.5
T1H.4
T1H.3
T1H.2
T1H.1
T1H.0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Access
Table 33.
8.1.6.6
Description
Description of T1H bits
Bit
Symbol
Description
7 to 0
T1H.7 to T1H.0 Timer1 timer/counter upper byte
Incrementer
The two 16-bit timer/counters are built around an 8-bit incrementer. The Timer0/1 are
incremented in the CPU states S1 to S4; the overflow flags are set in CPU states S2 and
S4.
• CPU state S1: TOL is incremented if Timer0 is set to:
– timer operation
– counter operation and when a 1-to-0 transition is detected on P34 / SIC_CLK input.
• CPU state S2: TOH is incremented if:
– T0L overflows. The overflow flag TF0 in register T01CON is updated.
• CPU state S3: T1L is incremented if Timer1 is set to:
– timer operation or
– counter operation and when a 1-to-0 transition is detected on P35 input.
• CPU state S4: T1H is incremented if:
– T1L overflows. The overflow flag TF1 in register T01CON is updated.
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8.1.6.7
Overflow detection
For both the upper and lower bytes of the Timer0/1, an overflow is detected by comparing
the incremented value of the most significant bit with its previous value. An overflow
occurs when this bit changes from logic level 1 to logic level 0. An overflow event in the
lower byte is clocked into a flip-flop and is used in the next state as the increment enable
for the upper byte. An overflow event in the upper byte will set the corresponding overflow
bit in the T01CON register to logic level 1. The upper byte overflow is also clocked into a
flip-flop to generate the output signals ‘t0_ovf’ and ‘t1_ovf’.
The overflow flags TF0 and TF1, found in register T01CON, are loaded during states S2
and S4 respectively. The interrupt controller of the 80C51 scans all requests at state S2.
Thus, an overflow of Timer0 or Timer1 is detected one machine cycle after it occurred.
When the request is serviced, the interrupt routine sets the overflow flag to logic 0.
Execution of the interrupt routine starts on the fourth machine cycles following the timer
overflow. When Timer0/1 receives the acknowledge from the CPU:
• the overflow flag TF0 in register T01CON is set to logic level 0
• two machine cycles later, the overflow flag TF1 in register T01CON is set to logic
level 0
If during the same machine cycle, an overflow flag is set to logic level 0 due to a CPU
acknowledge and set to logic level 1 due to an overflow, the set to logic level 1 is the
strongest.
8.1.7 Timer2 description
Timer2 supports a subset of the standard Timer2 found in the 8052 microcontroller.
Timer2 can be configured into 2 functional modes via the T2CON and T2MOD registers:
• Mode1: Auto-reload up/down counting
• Mode2: Baud rate generation for Debug UART
Timer2 can operate either as a timer or as an event counter.
8.1.7.1
Timer2 registers
Timer2 contains six Special Function Registers (SFRs) which can be accessed by the
CPU.
Table 34.
Timer2 SFR register List
Name
Size
[bytes]
SFR
address
Description
Access
T2CON
1
C8h
Timer2 control register
R/W
T2MOD
1
C9h
Timer2 mode register
R/W
RCAP2L
1
CAh
Timer2 reload lower byte
R/W
RCAP2H
1
CBh
Timer2 reload upper byte
R/W
T2L
1
CCh
Timer2 timer/counter lower byte
R/W
T2H
1
CDh
Timer2 timer/counter upper byte
R/W
Timer2 registers can be written to by either hardware or firmware. If both the hardware
and firmware attempt to update the registers T2H, T2L, RCAP2H or RCAP2L during the
same machine cycle, the firmware write takes precedence. A firmware write occurs in
state S6 of the machine cycle.
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Each increment or decrement of Timer2 occurs in state S1 except when in baud rate
generation mode and configured as a counter. In this mode, Timer2 increments on each
clock cycle. When configured as a timer, Timer2 is incremented every machine cycle.
Since a machine cycle consists of 6 clock periods, the count rate is 1/6 of the CPU clock
frequency.
8.1.7.2
T2CON register
The register is used to control Timer2 and report its status.
Table 35.
Timer2 T2CON register (SFR address C8h) bit allocation
Bit
7
6
5
4
3
2
1
0
TF2
-
RCLK0
TCLK0
-
TR2
C/T2
-
Reset
0
0
0
0
0
0
0
0
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Symbol
Table 36.
Description of T2CON bits
Bit
Symbol
Description
7
TF2
Timer2 overflow
Set to logic level 1 by a Timer2 overflow.
Set to logic level 0 by firmware.
TF2 is not set when in baud rate generation mode.
6
-
5
RCLK0
Reserved.
Timer2 Debug UART Receive Clock selector. Set by firmware only.
When set to logic level 1, Debug UART uses Timer2 overflow pulses.
When set to logic level 0, Debug UART uses overflow pulses from another
source (e.g. Timer1 in a standard configuration).
4
TCLK0
Timer2 Debug UART Transmit Clock selector. Set by firmware only.
When set to logic level 1, Debug UART uses Timer2 overflow pulses.
When set to logic level 0, Debug UART uses overflow pulses from another
source (e.g. Timer1 in a standard configuration).
3
-
Reserved.
2
TR2
Timer2 Run control.
Set by firmware only.
When set to logic level 1, Timer2 is started.
When set to logic level 0, Timer2 is stopped.
1
C/T2
Timer2 Counter/Timer selector.
Set by firmware only.
When set to logic level 1, Timer2 is set to counter operation.
When set to logic level 0, Timer2 is set to timer operation.
0
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Reserved. This bit must be set to logic level 0 by firmware.
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8.1.7.3
T2MOD register
This Special Function Register is used to configure Timer2.
Table 37.
Timer2 T2MOD register (SFR address C9h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
-
-
T2RD
-
DCEN
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R/W
R/W
Table 38.
Description of TMOD bits
Bit
Symbol
Description
7 to 3
-
Reserved.
2
T2RD
Timer2 ReaD flag.
Set by hardware and firmware.
This bit is set to logic level 1 by hardware, if T2H is incremented between
reading T2L and reading T2H. This bit is set to logic level 0, on the trailing
edge of next T2L read.
This bit is used to indicate that the16-bit Timer2 register is not read properly
since the T2H part was incremented by hardware before it was read.
1
-
Reserved
0
DCEN
Timer2 Down Count ENable.
Set by firmware only.
When this bit is set, Timer2 can be configured (in auto_reload mode) as an
up-counter.
When this bit is reset, Timer2 can be configured (in auto-reload mode) as a
down-counter.
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8.1.7.4
T2L, T2H registers
These are the actual timer/counter bytes. T2L is the lower byte, T2H the upper byte.
On the fly reading can give a wrong value since T2H can be changed after T2L is read
and before T2H is read. This situation is indicated by flag T2RD in T2MOD.
These two 8-bit registers are always combined to operate as one 16-bit timer/counter.
Table 39.
Bit
Symbol
Reset
Access
7
6
5
4
3
2
1
0
T2L.7
T2L.6
T2L.5
T2L.4
T2L.3
T2L.2
T2L.1
T2L.0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 40.
Description of T2L bits
Bit
Symbol
Description
7 to 0
T2L.7 to T2L.0
Timer2 timer/counter lower byte
Table 41.
Timer2 T2H register (SFR address CDh) bit allocation
Bit
Symbol
Reset
Access
Table 42.
8.1.7.5
Timer2 T2L register (SFR address CCh) bit allocation
7
6
5
4
3
2
1
0
T2H.7
T2H.6
T2H.5
T2H.4
T2H.3
T2H.2
T2H.1
T2H.0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description of T2H bits
Bit
Symbol
Description
7 to 0
T2H.7 to T2H.0
Timer2 timer/counter upper byte
RCAP2L, RCAP2H registers
These are the reload bytes. In the reload mode the T2H/T2L counters are loaded with the
values found in the RCAP2H/RCAP2L registers respectively.
Table 43.
Bit
Symbol
Reset
Access
6
5
4
3
2
1
0
R2L.6
R2L.5
R2L.4
R2L.3
R2L.2
R2L.1
R2L.0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description of RCAP2L bits
Bit
Symbol
Description
7 to 0
R2L.7 to R2L.0
Timer2 lower reload byte
Table 45.
Timer2 RCAP2H register (SFR address CBh) bit allocation
Symbol
Reset
Access
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7
R2L.7
Table 44.
Bit
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Timer2 RCAP2L register (SFR address CAh) bit allocation
7
6
5
4
3
2
1
0
R2H.7
R2H.6
R2H.5
R2H.4
R2H.3
R2H.2
R2H.1
R2H.0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 46.
Description of RCAP2H bits
Bit
Symbol
Description
7 to 0
R2H.7 to R2H.0
Timer2 upper reload byte
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8.1.8 Debug UART
The Debug UART is implemented to assist debug using UART_RX and UART_TX pins.
8.1.8.1
Feature list
The Debug UART has the following characteristics:
• Full duplex serial port
• Receive buffer to allow reception of a second byte while the first byte is being read out
by the CPU
• Four modes of operation which support 8-bit and 9-bit data transfer at various baud
rates
• Supports multi-processor communication
• Baud rate can be controlled through Timer1 or Timer2 baud rate generator
8.1.8.2
Debug UART functional description
The serial port has a receive buffer: a second byte can be stored while the previous one is
read out of the buffer by the CPU. However, if the first byte has still not been read by the
time reception of the second byte is complete, one of the bytes will be lost.
The receive and transmit data registers of the serial port are both accessed by firmware
via the Special Function Register S0BUF. Writing to S0BUF loads the transmit register;
reading from S0BUF accesses a physically separate receive register.
The serial port can operate in 4 modes. These modes are selected by programming bits
SM0 and SM1 in S0CON:
• Mode 0:
– Serial data are received and transmitted through UART_RX. UART_TX outputs the
shift clock. 8 bits are transmitted/received (LSB first)
Baud rate: fixed at 1/6 of the frequency of the CPU clock
• Mode 1:
– 10 bits are transmitted through UART_TX or received through UART_RX: a start
bit (0), 8 data bits (LSB first), and a stop bit (1)
– Receive: The received stop bit is stored into bit RB8 of register S0CON
– Baud rate: variable (depends on overflow of Timer1 or Timer2)
• Mode 2:
– 11 bits are transmitted through UART_TX or received through UART_RX: start bit
(0), 8 data bits (LSB first), a 9th data bit, and a stop bit (1)
– Transmit: the 9th data bit is taken from bit TB8 of S0CON. For example, the parity
bit could be loaded into TB8.
– Receive: the 9th data bit is stored into RB8 of S0CON, while the stop bit is ignored
– Baud rate: programmable to either 1/16 or 1/32 the frequency of the CPU clock
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• Mode 3:
– 11 bits are transmitted through UART_TX or received through UART_RX: a start
bit (0), 8 data bits (LSB first), a 9th data bit, and a stop bit (1). In fact, mode 3 is the
same as mode 2 in all aspects except the baud rate
– Transmit: as mode 2, the 9th data bit is taken from TB8 of S0CON
– Receive: as mode 2, the 9th data bit is stored into RB8 of S0CON
– Baud rate: depends on overflows of Timer1 or Timer2
The Debug UART initiates transmission and/or reception as follows.
• Transmission is initiated, in modes 0, 1, 2, 3, by any instruction that uses S0BUF as
destination
• Reception is initiated, in mode 0, if RI and REN in S0CON are set to logic 0 and 1
respectively
• Reception is initiated in modes 1, 2, 3 by the incoming start bit if REN in S0CON is set
to a logic 1
The Debug UART contains 2 SFRs:
Table 47.
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Debug UART SFR register list
Name
Size [bytes]
SFR address
Description
Access
S0CON
1
0098h
Control and status register
R/W
S0BUF
1
0099h
Transmit and receive buffer
R/W
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8.1.8.3
S0CON register
The Special Function Register S0CON is the control and status register of the Debug
UART. This register contains the mode selection bits (SM2, SM1, SM0), the 9th data bit
for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI).
Table 48.
Debug UART S0CON register (SFR: address 98h) bit allocation
Bit
Symbol
Reset
Access
Table 49.
Bit
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description of S0CON bits
Symbol Description
7 to 6 SM (0:1) Mode selection bit 0 and 1.
Set by firmware only. The Debug UART has 4 modes (Table 50 “Debug UART
modes” on page 33).
5
SM2
Multi-processor communication enable.
Enables the multi-processor communication feature. Set by firmware only.
In mode 2 and 3:
if SM2 is set to logic level 1, then RI will not be activated and RB8 and
S0BUF will not be loaded if the 9th data bit received is a logic 0
if SM2 is set to logic level 0, it has no influence on the activation of RI and
RB8
In mode 1:
if SM2 is set to logic level 1, then RI will not be activated and RB8 and
S0BUF will not be loaded if no valid stop bit was received
if SM2 is set to logic level 0, it has no influence on the activation of RI and
RB8
In mode 0, SM2 has no influence
4
REN
Serial reception enable.
Set by firmware only.
When set to logic level 1, enables reception.
3
TB8
Transmit data bit.
Set by firmware only.
In modes 2 and 3, the value of TB8 is transmitted as the 9th data bit
In modes 0 and 1, the TB8 bit is not used
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Table 49.
Description of S0CON bits …continued
Bit
Symbol Description
2
RB8
Receive data bit.
Set by hardware and by firmware.[1]
When set to logic level 1:
In modes 2 or 3, the hardware stores the 9th data bit that was received in RB8
In mode 1, the hardware stores the stop bit that was received in RB8
In mode 0, the hardware does not change RB8.
1
TI
Transmit interrupt flag.
TI must be set to logic level 0 by firmware.
In modes 2 or 3, when transmitting, the hardware sets to logic level 1 the
transmit interrupt flag TI at the end of the 9th bit time
In modes 0 or 1, when transmitting, the hardware sets to logic level 1 the
transmit interrupt flag TI at the end of the 8th bit time.
0
RI
Receive interrupt flag.
RI must be set to logic level 0 by firmware.
In modes 2 or 3, when receiving, the hardware sets to logic level 1 the receive
interrupt flag 1 clock period after sampling the 9th data bit (if SM2=1 setting RI
can be blocked, see bit description of SM2 above)
In mode 1, when receiving, the hardware sets to logic level 1 the receive
interrupt flag 1 clock period after sampling the stop bit [2]
In mode 0, when receiving, the hardware sets to logic level 1 RI at the end of
the CPU state 1 of the 9th machine cycle after the machine cycle where the
data reception started by a write to S0CON.
[1]
If SM2 is set to logic 1, loading RB8 can be blocked, see bit description of SM2 above.
[2]
If SM2 is set to logic 1, setting RI can be blocked, see bit description of SM2 above.
Remark: The S0CON register supports a locking mechanism to prevent firmware
read-modify-write instructions to overwrite the contents while hardware is modifying the
contents of the register.
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Table 50.
Debug UART modes
Mode
SM0
SM1
Description
Baud rate
0
0
0
Shift register
fclk/6
1
0
1
8 bits Debug UART
Variable
2
1
0
9 bits Debug UART
fclk/64 or fclk/32
3
1
1
9 bits Debug UART
Variable
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8.1.8.4
S0BUF register
This register is implemented twice. Writing to S0BUF writes to the transmit buffer. Reading
from S0BUF reads from the receive buffer. Only hardware can read from the transmit
buffer and write to the receive buffer.
Table 51.
Debug UART S0BUF Register (SFR: address 99h) bit allocation
Bit
7
6
5
Symbol
3
2
1
0
S0BUF[7:0]
Reset
Access
Table 52.
4
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description of S0BUF bits
Bit
Symbol
7 to 0
S0BUF[7:0]
Description
Writing to S0BUF writes to the transmit buffer.
Reading from S0BUF reads from the receive buffer.
8.1.8.5
Mode 0 baud rate
In mode 0, the baud rate is derived from the CPU states signals and thus:
Baud rate in mode 0
(1)
clk
------6
The next table lists the baud rates in Debug UART mode 0.
Table 53.
8.1.8.6
Baud rates in mode 0
Conditions
Min
Typ
Max
Unit
fCLK
6.78
13.56
27.12
MHz
Baud rate
1.13
2.26
4.52
Mb/s
Mode 2 baud rate
In mode 2, the baud rate depends on the value of bit SMOD from the SFR register PCON.
Baud Rate using mode 2
(2)
SMOD
2
---------------- f clk
32
The next table lists the baud rates in Debug UART mode 2.
Table 54.
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Baud rates in mode 2
Conditions
Min
Typ
Max
Unit
fCLK
6.78
13.56
27.12
MHz
Baud rate (SMOD=0)
212
424
847.5
kb/s
Baud rate (SMOD=1)
424
847.5
1695
kb/s
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8.1.8.7
Mode 1 and 3 baud rates
In modes 1 and 3, the baud rates are determined by the rate of timer1 and timer2 overflow
bits: ‘t1_ovf’ and ‘t2_ovf’. The register bit TCLK0 from the register T2CON selects if
‘t1_ovf’ or ‘t2_ovf’ should be used as a source when transmitting. The register bit RCLK0
from the register T2CON selects if ‘t1_ovf’ or ‘t2_ovf’ should be used as a source when
receiving. The timers interrupt should be disabled when used to define the Debug UART
baud rates.
The data rate is also dependant on the value of the bit SMOD from the SFR register
PCON.
If over1rate is the equivalent ‘t1_ovf’ frequency and over2rate is the equivalent ‘t2_ovf’
frequency then:
Baud rate in mode 1 and 3 when related to timer1 overflow
(3)
SMOD
2
---------------- over1rate
32
See also Section 8.1.8.8 “Baud rates using Timer1 (Debug UART mode 1 and 3)”
Baud rate in mode 1 and 3 when related to timer2 overflow
(4)
1
------ over2rate
16
See also Section 8.1.8.9 “Baud rates using Timer2 (Debug UART mode 1 and 3)”
The next table shows the trigger select:
Table 55.
8.1.8.8
Trigger select
RCLK0
TCLK0
SMOD
receive trigger rate
transmit trigger rate
0
-
0
over1rate/32
-
0
-
1
over1rate/16
-
1
-
-
over2rate/16
-
-
0
0
-
over1rate/32
-
0
1
-
over1rate/16
-
1
-
-
over2rate/16
Baud rates using Timer1 (Debug UART mode 1 and 3)
The Timer1 interrupt should be disabled in this application. The Timer1 itself can be
configured for either ‘timer’ or ‘counter’ operation, and in any of its 3 running modes. In the
most typical applications, it is configured for ‘timer’ operation, in the auto-reload mode
(Timer1 mode 2: high nibble of T01MOD = 0010b). In that case the baud rate is given by
the formula:
Baud rate
(5)
SMOD
f clk
2
---------------- --------------------------------------32
6 256 – T1H
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When rewriting this formula, the value for the Timer1 reload value T1H is calculated from
the desired baud rate as follows:
Timer1 reload value T1H
(6)
SMOD
f clk
2
256 – ---------------------------------------------32 6 Baudrate
One can achieve very low baud rates with Timer1 by leaving the Timer1 interrupt enabled,
and configuring the timer to run as a 16-bit timer (high nibble of T01MOD = 0001b), and
using the Timer1 interrupt to do a 16-bit firmware reload. Note: the frequency fclk is the
internal microcontroller frequency. If there is no clock divider then fclk = fosc.
For details on programming Timer1 to function as baud rate generator for the Debug
UART see Section 8.1.6 “Timer0/1 description” on page 20.
The next table lists the maximum baud rates for using mode 2 of Timer1.
Table 56.
Maximum baud rates using mode 2 of Timer1
Reload value
FF
fCLK divided by
96
SMOD
1
Baud rate at fCLK
Unit
6.78
13.56
27.12
MHz
70.6
141.2
282.5
kb/s
The next table shows commonly used baud rates using mode 2 of Timer1 and a CLK
frequency of 27.12 MHz.
Table 57.
Baud rates using mode 2 of Timer1 with fCLK = 27.12 MHz
Reload value
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fCLK divided by
SMOD
Baud rate at fCLK
Unit
FC
706
0
38.4
kb/s
F9
1412
0
19.2
kb/s
F1
2825
0
9.6
kb/s
E3
5650
0
4.8
kb/s
C5
11300
0
2.4
kb/s
8A
22600
0
1.2
kb/s
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8.1.8.9
Baud rates using Timer2 (Debug UART mode 1 and 3)
Timer2 has a programming mode to function as baud rate generator for the Debug UART.
In this mode the baud rate is given by formula:
Baud rate using Timer2
(7)
f clk
--------------------------------------------------------------------------------16 65536 – (T2RCH,T2RCL)
When rewriting this formula, the value for the Timer2 reload values T2RCH/L is calculated
from the desired baud rate as follows:
Reload value T2RCH/L
(8)
f clk
65536 – ------------------------------------16 Baudrate
For details on programming Timer2 to function as baud rate generator for the Debug
UART (see Section 8.1.7 “Timer2 description”).
Note: the frequency fclk is the internal microcontroller frequency. If there is no clock divider
then fclk = fosc.
The next table lists the maximum baud rates when using Timer2.
Table 58.
Maximum baud rates using Timer2
Reload value T2RCH/L
FFFF
fCLK divided by
16
Baud rate
Unit
6.78
13.56
27.12
MHz
424
847.5
1695
kb/s
8.2 General purpose IOs configurations
This chapter describes the different configurations for the IO pads:
P70_IRQ
P35
P34, alternate function SIC_CLK
P33_INT1
P32_INT0
P31, alternate function UART_TX
P30, alternate function UART_RX
Note that in Hard Power Down mode, these ports are disconnected from their supply rail.
For a given port x, there are three configuration registers:
PxCFGA[n]
PxCFGB[n]
Px[n]
where x is 3 or 7 and n is the bit index.
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At maximum 4 different controllable modes can be supported. These modes are defined
with the following bits:
•
•
•
•
PxCFGA[n]=0 and PxCFGB[n]=0: Open drain
PxCFGA[n]=1 and PxCFGB[n]=0: Quasi Bidirectional (Reset mode)
PxCFGA[n]=0 and PxCFGB[n]=1: input (High Impedance)
PxCFGA[n]=1 and PxCFGB[n]=1: Push/pull output
Px[n] is used to write or read the port value.
Here is the list of the registers used for these GPIO configuration
Table 59.
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Timer0/1 Special Function registers List
Name
Size
[bytes]
SFR address
Description
Access
P3CFGA
1
FCh
Port 3 configuration
R/W
P3CFGB
1
FDh
Port 3 configuration
R/W
P3
1
B0h
Port 3 value
R/W
P7CFGA
1
F4h
Port 7configuration
R/W
P7CFGB
1
F5h
Port 7 configuration
R/W
P7
1
F7h
Port 7 value
R/W
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8.2.1 Pad configurations description
8.2.1.1
Open-drain
DVDD
“0”
xVDD
e_pu
e_hd
PxCFGA[n] = “0”
e_p
PxCFGB[n] = “0”
1
Control
2
3
GPIO pad
en_n
Px[n]
zi
GND
GND
CPU_CLK
output mode
input mode
CPU_CLK
CPU_CLK
Write Px[n]
GPIO pad
en_n
en_n
GPIO pad
zi
Read Px[n]
zi
Fig 6. Open-drain
In open drain configuration, an external pull-up resistor is required to output or read a logic
level 1. When writing polarity Px[n] to logic level 0, the GPIO pad is pulled down to logic
level 0. When writing polarity Px[n] to logic level 1 the GPIO pad is in High Impedance.
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8.2.1.2
Quasi Bidirectional
DVDD
Control
xVDD
e_pu
e_hd
PxCFGA[n] = “1”
e_p
1
PxCFGB[n] = “0”
2
3
GPIO pad
en_n
Px[n]
zi
GND
GND
CPU_CLK
output mode
input mode
CPU_CLK
CPU_CLK
Write Px[n]
GPIO pad
en_n
“1”
en_n
tpushpull
e_p
“0”
e_p
e_hd
e_hd
“1”
e_pu
e_pu
GPIO pad
zi
zi
Read Px[n]
Fig 7. Quasi Bidirectional
In Quasi Bidirectional configuration, e_p is driven to logic level 1 for only one CPU_CLK
period when writing Px[n]. During the tpushpull time the pad drive a strong logic level 1 at its
output. While Px[n] is logic level 1, this state will be held by the weak hold transistor
(e_hd), which implements a latch function. Because of the weaker nature of this hold
transistor, the pad cell can now act as an input as well. A third very weak pull-up transistor
(e_pu) ensures that an open input is read as logic level 1.
On a transition from logic level 0 to logic level 1 externally driven on GPIO pad, when the
voltage on the pad is at the supply voltage divided by 2, the pull-up (e_hd) is activated.
The maximum current that can be sourced by the e_pu and e_hd transistors is 150 A
total at 3.6 V.
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8.2.1.3
Input
DVDD
“0”
xVDD
e_pu
e_hd
PxCFGA[n] = “0”
e_p
PxCFGB[n] = “1”
1
Control
3
GPIO pad
en_n
“1”
Px[n]
2
zi
GND
GND
CPU_CLK
input mode
CPU_CLK
GPIO pad
zi
Read Px[n]
Fig 8. Input
In input configuration, no pull up or hold resistor are internally connected to the pad.
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8.2.1.4
Push-pull output
DVDD
Control
“0”
xVDD
e_pu
e_hd
PxCFGA[n] = “1”
e_p
1
PxCFGB[n] = “1”
3
GPIO pad
en_n
Data
Px[n]
2
zi
GND
GND
CPU_CLK
output mode
CPU_CLK
Write Px[n]
en_n
e_p
GPIO pad
zi
Fig 9. Push-pull output
In push-pull output, the output pin drives a strong logic level 0 or a logic level 1
continuously. It is possible to read back the pin output value.
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8.2.2 GPIO registers description
8.2.2.1
P7CFGA register
Table 60.
P7CFGA register (SFR: address F4h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
-
-
-
-
P7CFGA[0]
Reset
1
1
1
1
1
1
1
1
Access
R
R
R
R
R
R
R
R/W
Table 61.
8.2.2.2
Description of P7CFGA bits
Bit
Symbol
Description
7 to 1
-
Reserved.
0
P7CFGA[0]
In conjuction with P7CFGB[0], it configures the functional mode of
P70_IRQ pin.
P7CFGB register
Table 62.
P7CFGB register (SFR: address F5h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
-
-
-
-
P7CFGB[0]
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R/W
Table 63.
8.2.2.3
Description of P7CFGB bits
Bit
Symbol
Description
7 to 1
-
Reserved.
0
P7CFGB[0]
In conjuction with P7CFGA[0], it configures the functional mode of
P70_IRQ pin.
P7 register
Table 64.
P7 register (SFR: address F7h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
-
-
-
-
P7[0]
Reset
1
1
1
1
1
1
1
1
Access
R
R
R
R
R
R
R
R/W
Table 65.
Bit
Description of P7 bits
Symbol
Description
7 to 1
-
Reserved.
0
P7[0]
Writing to P7[0] writes the corresponding value to the P70_IRQ pin
according to the configuration mode defined by P7CFGA[0] and
P7CFGB[0].
Reading from P7[0] reads the state of P70_IRQ pin.
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8.2.2.4
P3CFGA register
Table 66.
Bit
7
6
5
4
3
2
1
0
P3CFGA[4]
P3CFGA[3]
P3CFGA[2]
P3CFGA[1]
P3CFGA[0]
Symbol
-
-
P3CFGA[5]
Reset
1
1
1
1
1
1
1
1
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Table 67.
8.2.2.5
P3CFGA Register (SFR: address FCh) bit allocation
Description of P3CFGA Register bits
Bit Symbol
Description
7:6
Reserved.
5
P3CFGA[5]
In conjuction with P3CFGB[5], it configures the functional mode of P35
4
P3CFGA[4]
In conjuction with P3CFGB[4], it configures the functional mode of P34
3
P3CFGA[3]
In conjuction with P3CFGB[3], it configures the functional mode of P33_INT1
2
P3CFGA[2]
In conjuction with P3CFGB[2], it configures the functional mode of P32_INT0
1
P3CFGA[1]
In conjuction with P3CFGB[1], it configures the functional mode of P31
0
P3CFGA[0]
In conjuction with P3CFGB[0], it configures the functional mode of P30
P3CFGB register
Table 68.
P3CFGB register (SFR: address FDh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
P3CFGB[5]
P3CFGB[4]
P3CFGB[3]
P3CFGB[2]
P3CFGB[1]
P3CFGB[0]
Reset
0
0
0
0
0
0
0
0
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Table 69.
Bit
Description of P3CFGB bits
Symbol
7 to 6
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Description
Reserved.
5
P3CFGB[5]
In conjuction with P3CFGA[5], it configures the functional mode of P35.
4
P3CFGB[4]
In conjuction with P3CFGA[4], it configures the functional mode of P34.
3
P3CFGB[3]
In conjuction with P3CFGA[3], it configures the functional mode of P33.
2
P3CFGB[2]
In conjuction with P3CFGA[2], it configures the functional mode of P32.
1
P3CFGB[1]
In conjuction with P3CFGA[1], it configures the functional mode of P31.
0
P3CFGB[0]
In conjuction with P3CFGA[0], it configures the functional mode of P30.
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8.2.2.6
P3 register
Table 70.
Bit
P3 register (SFR: address B0h) bit allocation
7
6
5
4
3
2
1
0
Symbol
-
-
P3[5]
P3[4]
P3[3]
P3[2]
P3[1]
P3[0]
Reset
1
1
1
1
1
1
1
1
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Table 71.
Description of P3 bits
Bit
Symbol
Description
7 to 6
-
Reserved.
5
P3[5]
Writing to P3[5] writes the corresponding value to P35 pin according to the
configuration mode defined by P3CFGA[5] and P3CFGB[5].
Reading from P3[5] reads the state of P35 pin.
4
P3[4]
When P34 alternate function SIC_CLK is not used, writing to P3[4] writes the
corresponding value to P34 pin according to the configuration mode defined by
P3CFGA[4] and P3CFGB[4].
Reading from P3[4] reads the state of P34 pin.
3
P3[3]
Writing to P3[3] writes the corresponding value to P33_INT1 pin according to
the configuration mode defined by P3CFGA[3] and P3CFGB[3].
Reading from P3[3] reads the state of P33_INT1 pin.
2
P3[2]
Writing to P3[2] writes the corresponding value to P32_INT0 pin according to
the configuration mode defined by P3CFGA[2] and P3CFGB[2].
Reading from P3[2] reads the state of P32_INT0 pin.
1
P3[1]
When the P31 pin alternate function UART_TX is not used, writing to P3[1]
writes the corresponding value to P31 pin according to the configuration mode
defined by P3CFGA[1] and P3CFGB[1].
Reading from P3[1] reads the state of P31 pin.
0
P3[0]
When the P30 pin alternate function UART_RX is not used, writing to P3[0]
writes the corresponding value to P30 pin according to the configuration mode
defined by P3CFGA[0] and P3CFGB[0].
Reading from P3[0] reads the state of P30 pin.
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8.2.2.7
P5 register
Table 72.
P5 register (SFR: address D7h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
-
-
P5[2]
P5[1]
P5[0]
Reset
1
1
1
1
1
1
1
1
Access
R
R
R
R
R
R
R/W
R/W
Table 73.
Bit
Description of P5 bits
Symbol
Description
7 to 3
-
Reserved.
2
P5[2]
Bit 2 of P5 register is attached to USB signal “MP_ready” that indicates
USB block is ready for a new transaction like write command, write data or
read data.
This bit is polled by embedded firmware that manage USB transactions.
1
Writing to P5[1] writes the corresponding value to SDA I2C pin
according to the open drain configuration mode.
P5[1]
Reading from P5[1] reads the state of SDA I2C pin.
0
Writing to P5[0] writes the corresponding value to SCL of the I2C pin
according to the open drain configuration mode.
P5[0]
Reading from P5[0] reads the state of NSS I2C pin.
Remark: P5 supports only open drain mode
8.3 Host interfaces
PN533 must be able to support different kind of interfaces to communicate with the HOST.
All the interfaces that have to be supported are exclusive.
• USB interface
• High Speed UART (HSU): supporting specific high baud rates
PN533
selif(1:0)
I2C
M
I
F
SPI
CPU
HSU
FIFO
Manager
HOST
RAM
Host Interfaces
Fig 10. Host interface block diagram
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8.3.1 MATX description
After every Power-On or Hard Reset (RSTPD_N at low level), the PN533 also resets its
interfaces and checks the current HOST interface type.
The PN533 identifies the selected HOST interface by means of the logic levels on the
control pins I0 and I1 after the Reset Phase. This is done by a combination of fixed pin
connections
The Power for the MATX is delivered from PVDD.
The firmware must copy the value of the pads I0 and I1 to respectively selif[0] and selif[1].
Table 74.
HOST interface selection
PN533
Pin number
Config_IO_I1
register
selif[1]
selif[0]
DP
DM
18
17
25
24
8.3.1.1
Host Interface selected
HSU
USB non bus
powered
1
0
0
1
RX
DP
TX
DM
HSU
0
0
RX
TX
USB bus
powered
1
1
DP
DM
MATX register
The Config I0_I1 register is used to select the host interface. It manages also the polarity
of P33_INT1.
Table 75.
Config I0_I1 register (address 6103h) bit allocation
Bit
7
Symbol
6
5
int1_pol
-
0
0
R/W
R
Reset
Access
Table 76.
4
3
2
1
0
pad_I1
-
pad_I0
enselif
X
0
X
0
0
0
R/W
R
R/W
R/W
R/W
R/W
Selif[1:0]
Description of Config I0_I1 bits
Bit
Symbol
Description
7
int1_pol
When set to logic 1, the value of the P33_INT1 pin is inverted.
6
-
Reserved.
5
pad_I1
When read this bit gives the state of the I1 pin.
4
-
Reserved.
3
pad_I0
When read this bit gives the state of the I0 pin.
2
enselif
When set to logic 1, this bit indicates that the self bits are valid and that the
selected interface on the MIF can drive the pins.
The firmware must copy the value of the pads I0 and I1 to respectively selif[0]
and selif[1]
1 to 0
Selif[1:0]
These bits are used by the firmware to select the host interface
communication link, see Table 74 on page 47.
When set to logic 0, the MIF cannot drive the IO lines.
8.3.1.2
Pads NSS/P50_SCL/HSU_RX and MOSI/SDA / HSU_TX
The I2C SDA and SCL IO ports are configured in open drain mode. A pull-up resistor is
required for both pins to output or read a logical ‘1’.
In HSU mode, HSU_RX is in input mode and HSU_TX is in push-pull mode.
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8.3.2 I2C interface
It is recommended to refer the I2C standard for more information.
The I2C interface implements a Master I2C bus interface with integrated shift register, shift
timing generation. I2C Standard mode (100 kHz SCLK) and Fast mode (400 kHz SCLK)
are supported.
General Call +W is supported, not hardware General Call (GC +R).
The mains characteristics of the I2C module are:
• Support Master I2C bus
• Standard and Fast mode supported
The I2C module is control through 5 registers:
Table 77.
8.3.2.1
I2C register list
Name
Size
Address
[bytes]
Description
Access
I2CCON
1
D8h (SFR) Control register
R/W
I2CSTA
1
D9h (SFR) Status register
R/W
I2CDAT
1
DAh (SFR) Data register
R/W
I2CADR
1
DBh (SFR) Slave Address register
R/W
I2C functional description
The I2C interface may operate in any of the following two modes:
• Master Transmitter
• Master Receiver
Two types of data transfers are possible on the I2C bus:
• Data transfer from a Master transmitter to a Slave receiver. The first byte transmitted
by the Master is the Slave address. Next follows a number of data bytes. The Slave
returns an acknowledge bit after each received byte.
• Data transfer from a Slave transmitter to a Master receiver. The first byte (the Slave
address) is transmitted by the Master. The Slave then returns an acknowledge bit.
Next follows the data bytes transmitted by the Slave to the Master. The Master returns
an acknowledge bit after each received byte except the last byte. At the end of the last
received byte, a “not acknowledge” is returned.
In a given application, the I2C interface may operate as a Master or as a Slave.
In the Slave mode, the I2C interface hardware looks for its own Slave address and the
general call address. If one of these addresses is detected, an interrupt is requested.
When the PN533 microcontroller wishes to become the bus Master, the hardware waits
until the bus is free before the Master mode is entered so that a possible Slave action is
not interrupted. If bus arbitration is lost in the Master mode, the I2C interface switches to
the Slave mode immediately and can detect its own Slave address in the same serial
transfer.
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8.3.2.2
Master transmitter mode
As a Master, the I2C logic will generate all of the serial clock pulses and the START and
STOP conditions. A transfer is ended with a STOP condition or with a repeated START
condition. Since a repeated START condition is also the beginning of the next serial
transfer, the I2C bus will not be released.
I2C data are output through SDA while P50_SCL outputs the serial clock. The first byte
transmitted contains the Slave address of the receiving device (7-bit SLA) and the data
direction bit. In this case the data direction bit (R/W) will be a logic ‘0’ (W). I2C data are
transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.
START and STOP conditions are output to indicate the beginning and the end of a serial
transfer.
In the Master transmitter mode, a number of data bytes can be transmitted to the Slave
receiver. Before the Master transmitter mode can be entered, I2CCON must be initialized
with the ENS1 bit set to logic level 1 and the STA, STO and SI bits set to logic level 0.
ENS1 must be set to logic level 1 to enable the I2C interface. If the AA bit is set to logic
level 0, the I2C interface will not acknowledge its own Slave address or the general call
address if they are present on the bus. This will prevent the I2C interface from entering a
Slave mode.
The Master transmitter mode may now be entered by setting the STA bit. The I2C
interface logic will then test the I2C bus and generate a start condition as soon as the bus
becomes free. When a START condition is transmitted, the serial interrupt flag (SI) is set
to logic level 1, and the status code in the status register (I2CSTA) will be 08h. This status
code must be used to vector to an interrupt service routine that loads I2CDAT with the
Slave address and the data direction bit (SLA+W). The SI bit in I2CCON must then be set
to logic level 0 before the serial transfer can continue.
When the Slave address and the direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set to logic level 1
again, and a number of status codes in I2CSTA are possible. The appropriate action to be
taken for any of the status codes is detailed in Table 82 on page 55. After a repeated start
condition (state 10h), the I2C interface may switch to the Master receiver mode by loading
I2CDAT with SLA+R.
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8.3.2.3
Master receiver mode
As a Master, the I2C logic will generate all of the serial clock pulses and the START and
STOP conditions. A transfer is ended with a STOP condition or with a repeated START
condition. Since a repeated START condition is also the beginning of the next serial
transfer, the I2C bus will not be released.
The first byte transmitted contains the Slave address of the transmitting device (7-bit SLA)
and the data direction bit. In this case the data direction bit (R/W) will be logic level 1 (R).
I2C data are received via SDA while P50_SCL outputs the serial clock. I2C data are
received 8 bits at a time. After each byte is received, an acknowledge bit is transmitted.
START and STOP conditions are output to indicate the beginning and end of a serial
transfer.
In the Master receiver mode, a number of data bytes are received from a Slave
transmitter. The transfer is initialized as in the Master transmitter mode. When the START
condition has been transmitted, the interrupt service routine must load I2CDAT with the
7-bit Slave address and the data direction bit (SLA+R). The SI bit in I2CCON must then be
set to logic 0 before the serial transfer can continue.
When the Slave address and the data direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set to logic level 1
again, and a number of status codes are possible in I2CSTA. The appropriate action to be
taken for each of the status codes is detailed in Table 83 on page 56. After a repeated
start condition (state 10h), the I2C interface may switch to the Master transmitter mode by
loading I2CDAT with SLA+W.
8.3.2.4
I2CCON register
The CPU can read from and write to this 8-bit SFR. Two bits are affected by the Serial IO
(the I2C interface) hardware: the SI bit is set to logic level 1 when a serial interrupt is
requested, and the STO bit is set to logic level 0 when a STOP condition is present on the
I2C bus. The STO bit is also set to logic level 0 when ENS1 = ‘0’.
Table 78.
Bit
Symbol
Reset
Access
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I2CCON register (SFR: address D8h) bit allocation
7
6
5
4
3
2
CR[2]
ENS1
STA
STO
SI
AA
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Table 79.
Description of I2CCON bits
Bit
Symbol Description
7
CR[2]
Serial clock frequency selection in Master mode.
Together with CR[1:0], this bit determines the clock rate (serial clock frequency)
when the I2C interface is in a Master mode. Special attention has to be made on
the I2C bit frequency in case of dynamic switching of the CPU clock frequency.
6
ENS1
Serial IO enable.
When ENS1 bit is to logic level 0, SDA and P50_SCL are in high impedance. The
state of SDA and P50_SCL is ignored, the I2C interface is in the “not addressed”
Slave state, and the STO bit in I2CCON is forced to logic level 0. No other bits are
affected.
When ENS1 is logic level 1, the I2C interface is enabled, assuming selif[1:0] bits
are 10b (see Table 74 on page 47).
ENS1 should not be used to temporarily release the I2C interface from the I2C
bus since, when ENS1 is set to logic level 0, the I2C bus status is lost. The AA
flag should be used instead.
5
STA
START control.
When the STA bit is set to logic level 1 to enter Master mode, the I2C interface
hardware checks the status of the I2C bus and generates a START condition if
the bus is free. If the bus is not free, then the I2C interface waits for a STOP
condition (which will free the bus) and generates a START condition after a delay
of a half clock period of the internal serial clock generator.
If STA is set to logic level 1, while the I2C interface is already in a Master mode
and one or more bytes are transmitted or received, the I2C interface transmits a
repeated START condition.
STA may be set to logic level 1 at any time. This includes the case when the I2C
interface is the addressed Slave.
When the STA bit is set to logic level 0, no START condition or repeated START
condition will be generated.
4
STO
STOP control.
When the STO bit is set to logic level 1, while the I2C interface is in Master mode,
a STOP condition is transmitted to the I2C bus. When the STOP condition is
detected on the bus, the I2C interface hardware automatically sets STO to logic
level 0.
In Slave mode, STO may be set to logic 1 to recover from an error condition. In
this case, no STOP condition is transmitted to the I2C bus. However, the I2C
interface hardware behaves as if a STOP condition has been received and
switches to the defined “not addressed” Slave Receiver mode.
If the STA and STO bits are both set to logic level 1, the STOP condition is
transmitted to the I2C bus if the I2C interface is in Master mode (in Slave mode,
the I2C interface generates an internal STOP condition which is not transmitted).
The I2C interface then transmits a START condition.
When the STO bit is set to logic level 0, no STOP condition will be generated.
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Table 79.
Description of I2CCON bits …continued
Bit
Symbol Description
3
SI
Serial interrupt flag.
When SI is set to logic level 1, then if the serial interrupt from the I2C interface
port is enabled, the CPU will receive an interrupt. SI is set by hardware when any
one of 25 of the possible 26 states of the I2C interface are entered. The only state
that does not cause SI to be set to logic level 1 is state F8h, which indicates that
no relevant state information is available.
While SI is set by hardware to logic level 1, P50_SCL is held in logic 0 when the
SCL line is logic level 0, and P50_SCL is held in high impedance when the SCL
line is logic level 1.
SI must be set to logic level 0 by firmware.
When the SI flag is set to logic level 0, no serial interrupt is requested, and there
is no stretching of the SCL line via P50_SCL.
The bit IE1_4 of register IE1 (see Table 13 on page 17) has also to be set to logic
level 1 to enable the corresponding I2C interrupt to the CPU.
2
AA
Assert Acknowledge flag.
If AA is set to logic level 1, an acknowledge (low level to SDA) will be returned
during the acknowledge clock pulse on the P50_SCL line when:
•
•
The “own Slave address” has been received.
•
A data byte has been received while the I2C interface is in Master Receiver
mode.
•
A data byte has been received while the I2C interface is in the addressed
Slave Receiver mode.
The general call address has been received while the general call bit (GC) in
I2CADR is set.
When the I2C interface is in the addressed Slave Transmitter mode, state C8h
will be entered after the last serial bit is transmitted. When SI is set to logic
level 0, the I2C interface leaves state C8h, enters the Not-addressed Slave
Receiver mode, and the SDA line remains at logic 1. In state C8h, AA can be set
to logic level 1 again for future address recognition.
When the I2C interface is in the Not-addressed Slave mode, its own Slave
address and the general call address are ignored. Consequently, no
acknowledge is returned, and a serial interrupt is not requested. Thus, the I2C
interface can be temporarily released from the I2C bus while the bus status is
monitored. While the I2C interface is released from the bus, START and STOP
conditions are detected, and I2C data are shifted in. Address recognition can be
resumed at any time by setting AA to logic level 1.
If AA is set to logic level 1 when the I2C own Slave address or the general call
address has been partly received, the address will be recognized at the end of
the byte transmission.
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Table 79.
Bit
Description of I2CCON bits …continued
Symbol Description
1 to 0 CR[1:0] Serial clock frequency selection in Master mode.
CR2 CR1 CR0
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CPU_CLK division factor
I2C bit frequency
0
0
0
10
CPU_CLK/10
0
0
1
20
CPU_CLK/20
0
1
0
30
CPU_CLK/30
0
1
1
40
CPU_CLK/40
1
0
0
80
CPU_CLK/80
1
0
1
120
CPU_CLK/120
1
1
0
160
CPU_CLK/160
1
1
1
(256-T1 reload value)*12
24 ... 3072
CPU_CLK/3072 ... CPU_CLK/24
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8.3.2.5
I2CSTA register
I2CSTA is an 8-bit read-only special function register. The three least significant bits are
always at logic 0. The five most significant bits contain the status code. There are 26
possible status codes. When I2CSTA contains F8h, no relevant state information is
available and no serial interrupt is requested. Reset initializes I2CSTA to F8h. All other
I2CSTA values correspond to defined I2C interface states. When each of these states is
entered, a serial interrupt is requested (SI = ‘1’), this can happen in any CPU cycle, and a
valid status code will be present in I2CSTA. This status code will remain present in I2CSTA
until SI is set to logic 0 by firmware.
Note that I2CSTA changes one CPU_CLK clock cycle after SI changes, so the new status
can be visible in the same machine cycle SI changes or possibly (in one out of six CPU
states) the machine cycle after that. This should not be a problem since you should not
read I2CSTA before either polling SI or entry of the interrupt handler (which in itself takes
several machine cycles).
Table 80.
Bit
I2CSTA register (SFR: address D9h) bit allocation
7
6
5
4
3
2
1
0
Reset
1
1
1
1
1
0
0
0
Access
R
R
R
R
R
R
R
R
Symbol
ST[7:0]
Table 81.
Description of I2CSTA bits
Bit
Symbol
Description
7 to 0
ST[7:0]
Encoded status bit for the different functional mode. Several Status
codes are returned in a certain mode (Master Transmitter, Master
Receiver, Slave Transmitter, Slave Receiver) plus some miscellaneous
status codes that can be returned at any time.
SI=0 =>ST[7:0] = F8
SI=1 => ST[7:0] = status
INTERRUPT/
STATUS
AVAILABLE
IDLE
SI=1
SI=0 => ST[7:0] = F8
Fig 11. I2C state machine of status behavior
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
I2C Master Transmitter Mode status code
Status Status of the I2C Bus
Code and of the
ST[7:0] I2C interface Hardware
To/from I2CDAT
08h
A START condition has been
transmitted
Load SLA+W
X
10h
A repeated START condition
has been transmitted
Load SLA+W
Load SLA+R
SLA+W has been transmitted;
ACK has been received
Load data byte
18h
SLA+W has been transmitted;
NOT ACK has been received
Write data byte in I2CDAT has
been transmitted;
ACK has been received
TO I2CCON
STA STO
I2CDAT
SI
AA
0
0
X
SLA+W will be transmitted ACK will be received
X
0
0
X
As above
X
0
0
X
SLA+W will be transmitted;
the I2C interface will be switched to MST/(TRX or REC) mode
0
0
0
X
Data byte will be transmitted; ACK bit will be received
action
1
0
0
X
Repeated START will be transmitted
No I2CDAT action
0
1
0
X
STOP condition will be transmitted
STO flag will be set to logic level 0
No I2CDAT action
1
1
0
X
STOP condition followed by a START condition will be transmitted
STO flag will be set to logic level 0
Load data byte
0
0
0
X
Data byte will be transmitted
ACK bit will be received
No I2CDAT action
1
0
0
X
Repeated START will be transmitted
action
0
1
0
X
STOP condition will be transmitted
STO flag will be set to logic level 0
No I2CDAT action
1
1
0
X
STOP condition followed by a START condition will be transmitted
STO flag will be set to logic level 0
No
No
28h
Next Action Taken By the I2C interface Hardware
Application firmware Response
I2CDAT
0
0
0
X
Data byte will be transmitted; ACK bit will be received
No I2CDAT action
1
0
0
X
Repeated START will be transmitted
No I2CDAT action
0
1
0
X
STOP condition will be transmitted
STO flag will be set to logic level 0
No I2CDAT action
1
1
0
X
STOP condition followed by a START condition will be transmitted
STO flag will be set to logic level 0
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Table 82.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
I2C Master Transmitter Mode status code …continued
Status Status of the I2C Bus
Code and of the
ST[7:0] I2C interface Hardware
30h
38h
I2CDAT
Write data byte in
has
been transmitted;
NOT ACK has been received
Arbitration lost in SLA+R/W or
Data bytes
To/from
TO
I2CCON
STA STO
SI
AA
Load data byte
0
0
0
X
Data byte will be transmitted; ACK bit will be received
No I2CDAT action
1
0
0
X
Repeated START will be transmitted
No I2CDAT action
0
1
0
X
STOP condition will be transmitted
STO flag will be set to logic level 0
No I2CDAT action
1
1
0
X
STOP condition followed by a START condition will be transmitted
STO flag will be set to logic level 0
No I2CDAT action
0
0
0
X
I2C bus will be released; a Slave mode will be entered
No I2CDAT action
1
0
0
X
A START condition will be transmitted when the bus becomes free
I2C Master Receiver Mode status codes
Status Status of the I2C Bus and
Code the I2C interface Hardware
ST[7:0]
Next Action Taken By the I2C interface Hardware
Application firmware Response
To /from
I2CDAT
TO
I2CCON
STA STO
SI
AA
08h
A START condition has been
transmitted
Load SLA+W
X
0
0
X
SLA+W will be transmitted, ACK will be received
10h
A repeated START condition
has been transmitted
Load SLA+W
X
0
0
X
As above
Load SL+R
X
0
0
X
SLA+W will be transmitted; the I2C interface will be switched to MST/(TRX
or REC) mode
Arbitration lost in SLA+R/W or
Data bytes
No I2CDAT action
0
0
0
X
I2C bus will be released; a Slave mode will be entered
38h
40h
SLA+R has been transmitted;
NOT ACK has been received
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action
1
0
0
X
A START condition will be transmitted when the bus becomes free
No
I2CDAT
action
0
0
0
0
Data byte will be received;
NOT ACK bit will be returned
No I2CDAT action
0
0
0
1
Data byte will be received;
ACK bit will be returned
No I2CDAT action
1
0
0
X
Repeated START condition will be transmitted
action
0
1
0
X
STOP condition will be transmitted;
STO flag will be set to logic level 0
No I2CDAT action
1
1
0
X
STOP condition followed by a START condition will be transmitted;
STO flag will be set to logic level 0
No
I2CDAT
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SLA+R has been transmitted;
ACK has been received
No
I2CDAT
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Table 83.
Next Action Taken By the I2C interface Hardware
Application firmware Response
I2CDAT
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Table 82.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
I2C Master Receiver Mode status codes …continued
Status Status of the I2C Bus and
Code the I2C interface Hardware
ST[7:0]
50h
58h
To /from
TO
I2CCON
STA STO
SI
AA
Read data byte or
0
0
0
0
Data byte will be received;
NOT ACK bit will be returned
Read data byte
0
0
0
1
Data byte will be received;
ACK bit will be returned
Read data byte has been
received; NOT ACK has been
returned
Read data byte
1
0
0
X
Repeated START condition will be transmitted
Read data byte
0
1
0
X
STOP condition will be transmitted;
STO flag will be set to logic level 0
Read data byte
1
1
0
X
STOP condition followed by a START condition will be transmitted;
STO flag will be set to logic level 0
I2C Miscellaneous status codes
Status Status of the I2C Bus and
Code the I2C interface Hardware
I2CSTA
To /from I2CDAT
00h
No I2CDAT action
Bus error
No information available
Next Action Taken By the I2C interface Hardware
Application firmware Response
TO I2CCON
STA STO
No
I2CDAT
action
SI
AA
X
1
0
X
Hardware will enter the “not addressed” Slave mode
--
--
--
--
--
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Read data byte has been
received; ACK has been
returned
Table 84.
F8h
Next Action Taken By the I2C interface Hardware
Application firmware Response
I2CDAT
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Table 83.
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8.3.2.6
I2CDAT register
I2CDAT contains a byte of I2C data to be transmitted or a byte which has just been
received. The CPU can read from and write to this 8-bit SFR while it is not in the process
of shifting a byte. This occurs when the I2C interface is in a defined state and the serial
interrupt flag SI is set to logic level 1. Data in I2CDAT remains stable as long as SI is set to
logic level 1. The first bit to be transmitted is the MSB (bit 7), and, after a byte has been
received, the first bit of received data is located at the MSB of I2CDAT. While data is being
shifted out, data on the bus is simultaneously being shifted in; I2CDAT always contains the
last data byte present on the bus. Thus, in the event of lost arbitration, the transition from
Master Transmitter to Slave Receiver is made with the correct data in I2CDAT.
Table 85.
Bit
I2CDAT register (SFR: address DAh) bit allocation
7
6
5
Access
Table 86.
3
2
1
0
I2CDAT[7:0]
Symbol
Reset
4
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description of I2CDAT bits
Bit
Symbol
Description
7 to 0
I2CDAT[7:0]
I2C data. Eight bits to be transmitted or just received. A logic level 1
in I2CDAT corresponds to a logic level 1 on the I2C bus, and a logic
level 0 corresponds to a logic level 0 on the bus. I2C data shift
through I2CDAT from right to left.
I2CDAT[7:0] and the ACK flag form a 9-bit shift register which shifts in or shifts out an 8-bit
byte, followed by an acknowledge bit. The ACK flag is controlled by the I2C interface
hardware and cannot be accessed by the CPU. I2C data are shifted through the ACK flag
into I2CDAT on the rising edges of clock pulses on P50_SCL. When a byte has been
shifted into I2CDAT, the I2C data are available in I2CDAT, and the acknowledge bit is
returned by the control logic during the ninth clock pulse. I2C data are shifted out from
I2CDAT via a buffer on the falling edges of clock pulses on P50_SCL.
When the CPU writes to I2CDAT, the buffer is loaded with the contents of I2CDAT[7] which
is the first bit to be transmitted to the SDA line. After nine serial clock pulses, the eight bits
in I2CDAT will have been transmitted to the SDA line, and the acknowledge bit will be
present in ACK. Note that the eight transmitted bits are shifted back into I2CDAT.
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8.3.2.7
I2CADR register
The CPU can read from and write to this 8-bit SFR. I2CADR is not affected by the I2C
interface hardware. The content of this register is irrelevant when the I2C interface is in a
Master mode. In the Slave modes, the seven most significant bits must be loaded with the
microcontroller’s own Slave address, and, if the least significant bit is set to logic level 1,
the general call address (00h) is recognized; otherwise it is ignored.
I2CADR register (SFR: address DBh) bit allocation
Table 87.
Bit
7
6
5
4
Symbol
3
2
1
0
SA[6:0]
Reset
Access
GC
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 88.
Description of I2CADR bits
Bit
Symbol
Description
7 to 1
SA[6:0]
Slave address.
These bits correspond to the 7-bit Slave address which will be
recognized on the incoming data stream from the I2C bus. When the
Slave address is detected and the interface is enabled, a serial interrupt
SI will be generated to the CPU.
0
GC
General call.
When set to logic level 1, will cause the I2C logic to watch for the
general call address to be transmitted on the I2C bus. If a general call
address is detected and this bit is set to logic level 1, SI will be set to
logic level 1.
8.3.2.8
I2C_wu_control register
The wake up block has to be enabled before the whole chip enters in Soft-Power-down
mode. The choice of the wake-up conditions is made within the register I2C_wu_control.
Read and Write conditions can be set together.
I2C_wu_control register (address 610Ah) bit allocation
Table 89.
Bit
7
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5
4
3
2
1
0
i2c_wu_en_rd
i2c_wu_en
Symbol
-
-
-
-
-
i2c_wu_en_wr
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R/W
R/W
R/W
Description of I2C_wu_control bits
Table 90.
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Bit
Symbol
Description
7 to 3
-
Reserved.
2
i2c_wu_en_wr
When set to logic level 1, the wake-up is valid for write commands
1
i2c_wu_en_rd
When set to logic level 1, the wake-up is valid for read commands
0
i2c_wu_en
When set to logic level 1, enable the I2C wake-up conditions
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8.3.3 FIFO manager
This block is designed to manage a RAM as a FIFO in order to optimize the data
exchange between the CPU and the HOST.
8.3.3.1
FIFO manager functional description
The RAM used for the FIFO is shared between the SPI and HSU interfaces. Indeed,
these interfaces cannot be used simultaneously. The selection of the interface used is
done by firmware. The FIFO manager block is the common part between the USBB and
the HSU interfaces. It consists of a Data register, a Status register and also some
registers to define the characteristics of the FIFO. These registers are addressed by the
CPU as SFRs.
The RAM used as a FIFO is divided into two part: a receive part and a transmit part.
This block also manages the possible conflicts existing around the FIFO between the
CPU and the interfaces. Indeed, a request coming from the interface (TR_req or
RCV_req) can be simultaneous with a request to access to the data register coming
from the CPU.
sfr_rd
sfr_wr
sfr_sel
CPU
DATA
FIFO
HSU_TR_Req
Manager
HSU_TR_Ack
HSU_RCV_Req
HSU_RCV_Ack
Irq
HSU_DATA
HIGH
SPEED
UART
USB_control
A D Q
USB
Control
USB_DATA
Fig 12. FIFO manager block diagram
9 SFR registers are needed to manage the FIFO manager.
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Table 91.
8.3.3.2
Fifo manager SFR register list
Name
Size
[bytes]
SFR
Description
Address
Access
RWL
1
9Ah
FIFO Receive Waterlevel: Controls the threshold of the
FIFO in reception
R/W
TWL
1
9Bh
FIFO Transmit Waterlevel: Controls the threshold of the R/W
FIFO in transmission
FIFOFS 1
9Ch
FIFO Transmit FreeSpace: Status of the number of
characters which can still be loaded in the FIFO
R/W
FIFOFF 1
9Dh
FIFO Receive Fullness: Status of the number of
received characters in the FIFO
R/W
SFF
1
9Eh
Global Status/Error messages
R
FIT
1
9Fh
Interrupt Source
R/W
FITEN
1
A1h
Interrupt Enable and Reset FIFO
R
FDATA
1
A2h
Data reception/transmission buffer
R/W
FSIZE
1
A3h
Control the size of the FIFO in Reception
R/W
RWL register
This register defines the warning level of the Receive FIFO for the CPU. It implies a FIFO
buffer overflow.
Table 92.
Bit
RWL register (SFR: address 9Ah) bit allocation
7
6
5
Symbol
Reset
Access
Table 93.
8.3.3.3
4
3
2
1
0
RWaterlevel[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description of RWL bits
Bit
Symbol
Description
7 to 0
RWaterlevel[7:0]
Overflow threshold of the Receive FIFO to set a warning
TWL register
This register defines the warning level of the Transmit FIFO for the CPU. It implies a FIFO
buffer underflow.
Table 94.
Bit
TWL register (SFR: address 9Bh) bit allocation
7
6
5
Symbol
Reset
Access
Table 95.
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4
3
2
1
0
TWaterlevel[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description of TWL bits
Bit
Symbol
Description
7 to 0
TWaterlevel[7:0]
Underflow threshold of the Transmit FIFO to set a warning
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8.3.3.4
FIFOFS register
This register indicates the number of bytes that the CPU can still load into the FIFO until
the Transmit FIFO is full.
Table 96.
Bit
FIFOFS register (SFR: address 9Ch) bit allocation
7
6
5
Symbol
Access
Table 97.
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description of FIFOFS register bits
Symbol
Description
7 to 0 TransmitFreespace[7:0]
8.3.3.5
3
TransmitFreespace[7:0]
Reset
Bit
4
Freespace into the FIFO
FIFOFF register
This register indicates the number of bytes already received and loaded into the Receive
FIFO.
Table 98.
Bit
FIFOFF register (SFR: address 9Dh) bit allocation
7
6
5
Symbol
Access
Table 99.
Product data sheet
COMPANY PUBLIC
3
2
1
0
ReceiveFullness[7:0]
Reset
PN5331B3HN
4
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description of FIFOFF bits
Bit
Symbol
Description
7 to 0
ReceiveFullness[7:0]
Number of bytes received in the FIFO
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8.3.3.6
SFF register
The register bits are used to allow the CPU to monitor the status of the FIFO. The primary
purpose is to detect completion of data transfers.
Table 100. SFF register (SFR: address 9Eh) bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
FIFO_EN
-
TWLL
TFF
TFE
RWLH
RFF
RFE
0
0
1
0
1
0
0
1
R/W
R
R
R
R
R
R
R
Reset
Access
Table 101. Description of SFF bits
Bit
Symbol
Description
7
FIFO_EN
Fifo Enable:
Set to logic 1 this bit enables the FIFO manager clock (CPU_CLK).
Set to logic 0 the clock remains low.
6
-
Reserved.
5
TWLL
Transmit WaterlLevelLow:
This bit is set to logic 1 when the number of bytes stored into the
Transmit FIFO is equal or smaller than the threshold TWaterlevel.
4
TFF
Transmit FIFO Full:
This is set to logic 1 if the transmit part of the FIFO is full. It is set to
logic level 0 when a transfer is completed.
3
TFE
Transmit FIFO Empty:
This bit indicates when the transmit part of the FIFO is empty.
It is set to logic 0 when the CPU writes a character in the data register.
2
RWLH
Receive WaterLevel High:
This bit is set to logic 1 when the number of bytes stored into the
Receive FIFO is greater or equal to the threshold RWaterlevel.
1
RFF
Receive FIFO Full:
This bit is set to logic 1 if the receive part of the FIFO is full. It is set to
logic level 0 by reading the FDATA register.
0
RFE
Receive FIFO Empty:
This bit indicates when the receive part of the FIFO is empty.
Set to logic 1, when the Receive FIFO is empty.
Set to logic level 0, when the Receive FIFO contains at least 1 byte.
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8.3.3.7
FIT register
The FIT register contains 6 read-write bits which are logically OR-ed to generate an
interrupt going to the CPU.
Table 102. FIT register (SFR: address 9Fh) bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
Reset
-
WCOL_
IRQ
TWLL_
IRQ
TFF_
IRQ
RWLH_
IRQ
ROVR_
IRQ
RFF_
IRQ
Reset
0
0
0
0
0
0
0
0
Access
W
R
R/W
R/W
R/W
R/W
R/W
R/W
Table 103. Description of FIT bits
Bit Symbol
Description
7
Reset:
Reset
Set to logic 1, Reset defines that the bits set to logic level 1 in the write
command are set to logic level 0 in the register.
6
-
5
WCOL_IRQ Write COLlision IRQ:
Reserved
This bit is set to logic 1 when the transmitted part of the FIFO is already full
(TFF is set to logic 1) and a new character is written by the CPU in the data
register.
4
TWLL_IRQ
Transmit WaterlLevelLow IRQ:
This bit is set to logic 1 when the number of bytes stored into the Transmit FIFO
is equal or smaller than the threshold TWaterlevel.
3
TFF_IRQ
Transmit FIFO Full IRQ:
2
RWLH_IRQ Receive WaterLevel High IRQ: This bit is set to logic 1 when the number of
bytes stored into the Receive FIFO is greater or equal to the threshold
RWaterlevel.
1
ROVR_IRQ Read OVeRrun IRQ: This bit indicates that a read overrun has occured.It
occurs when the receiver part of the FIFO is full and a new data transfer is
completed. Then the new received data is lost and ROVR_IRQ is set.
0
RFF_IRQ
This is set to logic 1 if the transmitted part of the FIFO is full.
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Receive FIFO Full IRQ: This bit is set to logic 1 if the received part of the FIFO
is full.
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8.3.3.8
FITEN register
The FITEN register enables or disables the interrupt requests to the CPU. It is also used
to reset the content of the Receive and Transmit FIFO.
Table 104. FITEN register (SFR: address A1h) bit allocation
Bit
7
Symbol
6
TFLUSH RFLUSH
Reset
Access
5
4
3
2
1
0
EN_
WCOL_
IRQ
EN_
TWLL_
IRQ
EN_
TFF_
IRQ
EN_
RWLH_
IRQ
EN_
ROVR_
IRQ
EN_
RFF_
IRQ
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 105. Description of FITEN bits
Bit Symbol
Description
7
TFLUSH
When set to logic level 1, the pointer of the Transmit FIFO is reset. This bit
and RFLUSH must not be set at the same time.
6
RFLUSH
When set to logic level 1, the pointer of the Receive FIFO is reset. This bit
and TFLUSH must not be set at the same time but one after the other.
5
EN_WCOL_IRQ ENable Write COLlision IRQ:
When set to logic 1, the WCOL_IRQ is enabled.
The bit IE1_5 of register IE1 (see Table 13 on page 17) has also to be set
to logic level 1 to enable the corresponding CPU interrupt.
4
EN_TWLL_IRQ
ENable Transmit WaterlLevelLow IRQ:
When set to logic 1, the TWLL_IRQ is enabled.
The bit IE1_5 of register IE1 (see Table 13 on page 17) has also to be set
to logic level 1 to enable the corresponding CPU interrupt.
3
EN_TFF_IRQ
ENable Transmit FIFO Full IRQ:
When set to logic level 1, the TFF_IRQ is enabled.
The bit IE1_5 of register IE1 (see Table 13 on page 17) has also to be set
to logic level 1 to enable the corresponding CPU interrupt.
2
EN_RWLH_IRQ ENable Receive WaterLevel High IRQ:
When set to logic 1, the RWLH_IRQ is enabled.
The bit IE1_5 of register IE1 (see Table 13 on page 17) has also to be set
to logic level 1 to enable the corresponding CPU interrupt.
1
EN_ROVR_IRQ ENable Read OVeRrun IRQ:
When set to logic 1, the ROVR_IRQ is enabled.
The bit IE1_5 of register IE1 (see Table 13 on page 17) has also to be set
to logic level 1 to enable the corresponding CPU interrupt.
0
EN_RFF_IRQ
ENable Receive FIFO Full IRQ:
When set to logic 1, the RFF_IRQ is enabled.
The bit IE1_5 of register IE1 (see Table 13 on page 17) has also to be set
to logic level 1 to enable the corresponding CPU interrupt.
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8.3.3.9
FDATA register
The FDATA register is used to provide the transmitted and received data bytes. Each data
written in the data register is pushed into the Transmit FIFO. Each data read from the data
register is popped from the Receive FIFO.
Table 106. FDATA register (SFR: address A2h) bit allocation
Bit
7
6
5
4
Symbol
Reset
Access
3
2
1
0
FDATA[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 107. Description of FDATA bits
Bit
Symbol
Description
7 to 0
FDATA[7:0]
Writing to FDATA writes to the transmit buffer.
Reading from FDATA reads from the receive buffer.
8.3.3.10
FSIZE register
This register defines the size of the Receive FIFO. The maximum size is 182 bytes. The
free space not used by the Receive FIFO in the RAM will be allocated to Transmit FIFO.
Table 108. FSIZE register (SFR: address A3h) bit allocation
Bit
7
6
5
Symbol
Reset
Access
4
3
2
1
0
ReceiveSize[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 109. Description of FSIZE bits
Bit
Symbol
Description
7 to 0 ReceiveSize[7:0]
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Size of the Receive FIFO
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8.3.4 High Speed UART (HSU)
The High Speed UART (HSU) provides a high speed link to the host (up to 1.288 Mbit/s).
The HSU is a full duplex serial port. The serial port has a Receive-buffer: in conjunction
with the FIFO manager, the reception of several bytes can be performed without strong
CPU real time constraints. However, if the Receive FIFO still has not been read by the
CPU, and the number of receive bytes is greater than the Receive FIFO size then the new
incoming bytes will be lost.
The HSU receive and transmit data registers are both accessed by firmware in the FIFO
manager FDATA register. Writing to FDATA loads the transmit register, reading from
FDATA accesses the separate receive register.
The characteristics of the UART are the following:
• Full duplex serial port
• Receive buffer to allow reception of byte while the previous bytes are stored into the
FIFO manager
•
•
•
•
•
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8-bit data transfers
Programmable baud rate generator using prescaler for transmission and reception
Based on 27.12 MHz clock frequency
Dedicated protocol preamble filter
Wake-up generator
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tx_data
hsu_txout
Shift Register
tx_shift
tr_req
TX Control
tr_ack
tx_clk
Prescaler
FIFO manager
CPU Interface
hsu_tx_control
hsu_tx_status
Baud rate
Generator
HSU_STA
HSU_CTR
Baud rate_control
HSU_PRE
hsu_rcv_status
hsu_rcv_control
rcv_req_o
Preamble
rcv_req_i
Filter 00 00 FF
rcv_ack
rx_clk
HSU_CNT
rx_irq
hsu_irq
RX Control
1-to-0
Transition
Detector
rx_start
Bit Detector
1FFH rx_shift
Input Shift Register
rx_data
wake-up
generator
hsu_rxin
hsu_on
Fig 13. HSU block diagram
The HSU contains 4 SFRs:
Table 110. HSU SFR register list
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Name
Size [bytes] SFR Address Description
Access
HSU_STA
1
ABh
HSU STAtus register
R/W
HSU_CTR
1
ACh
HSU ConTRol register
R/W
HSU_PRE
1
ADh
HSU PREscaler for baud rate generator
R/W
HSU_CNT
1
AEh
HSU CouNTer for baud rate generator
R/W
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8.3.4.1
Mode of operation
The HSU supports only one operational mode, which has the following characteristics:
• Start bit:
– Start bit is detected when a logic level 0 is asserted on the HSU_RX line.
• 8 data bits:
– The data bits are sent or received LSB first.
• Stop bit:
– During reception, the Stop bit(s) is detected when all the data bits are received and
when Stop bit(s) is sampled to logic level 1. The number of Stop bits is
programmable. It can be 1 or 2.
– During Transmission, after the complete data bit transmission, a variable number
of Stop bit(s) is transmitted. This number is programmable from 1 to 4.
8.3.4.2
HSU Baud rate generator
To reach the high speed transfer rate, the HSU has it own baud rate generator. The baud
rate generator comprises a prescaler and a counter. The prescaler is located before the
counter. The purpose of the prescaler is to divide the frequency of the count signal to
enlarge the range of the counter (at the cost of a lower resolution). The division factor of
the prescaler is equal to 2 to the power HSU_PRE[8:0] (Table 113 on page 71), resulting
in division factors ranging from 1 (20) to 256 (28). The combination of these 2 blocks
defines the bit duration and the bit sampling.
8.3.4.3
HSU preamble filter
Received characters are sent to the FIFO manager after three consecutive characters
have been received: 00 00 FF. When the frame is finished, and before a new frame
arrives, firmware shall write a logic level 1 in the start_frame bit of the HSU_CTR register
to re-activate the preamble filter. If firmware does not write a logic level 1 then all
characters of the frame are sent to the FIFO manager (including the preamble).
8.3.4.4
HSU wake-up generator
The wake-up generator is a 3-bit counter which counts on every rising edge of the
HSU_RX pin. When the counter reaches 5, the hsu_on signal is set to logic level 1 in
order to wake up the PN533. This block is useful in Soft-Power-down mode. The firmware
shall reset this counter just before going in Soft-Power-down by writing a logic level 1 in
the hsu_wu_en bit into the HSU_CTR register.
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8.3.4.5
HSU_STA register
The SFR HSU_STA is the status register of the HSU.
Table 111. HSU_STA register (SFR: address ABh) bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
set_bit
-
-
disable_
preamb
irq_rx_
over_en
irq_rx_fer
_ en
irq_rx_
over
irq_rx_fer
0
0
0
0
0
0
0
0
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Reset
Access
Table 112. Description of HSU_STA bits
Bit
Symbol
Description
7
set_bit
When set to logic 0 during write operation, the bits set to logic 1 in the
write command are written to logic level 0 in the register.
When set to logic 1 during write operation, the bits set to logic 1 in the
write command are written to logic level 1 in the register.
6 to 5 4
Reserved
disable_preamb Preamble filter disable.
When set to logic 1, this bit disables the preamble filtering, it means that
HSU_RX line transmit any received bytes to the FIFO manager.
3
irq_rx_over_en
FIFO overflow interrupt enable.
When set to logic 1, this bit enables the interrupt generation when the bit
irq_rx_over is set to logic 1.
The bit IE1_5 of register IE1 (see Table 13 on page 17) has also to be set
to logic level 1 to enable the corresponding CPU interrupt.
2
irq_rx_fer_en
Framing error interrupt enable.
When set to logic 1, this bit enables the interrupt generation when the bit
irq_rx_fer is set to logic 1.
The bit IE1_5 of register IE1 (see Table 13 on page 17) has also to be set
to logic level 1 to enable the corresponding CPU interrupt.
1
irq_rx_over
Receive FIFO overflow interrupt.
Set to logic 1 when the FIFO manager is full (rcv_ack is set to logic
level 0) and when HSU shift register is ready to send another byte to the
FIFO manager.
0
irq_rx_fer
Framing error interrupt.
Set to logic 1 when a framing error has been detected. Framing error
detection is based on Stop bit sampling.
When Stop bit is expected at logic level 1 but is sampled at logic level 0,
this bit is set to logic level 1.
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8.3.4.6
HSU_CTR register
This register controls the configuration of the HSU.
Table 113. HSU_CTR register (SFR: address ACh) bit allocation
Bit
Symbol
7
6
hsu_wu_
en
start_frame
0
0
0
R/W
R/W
R/W
Reset
Access
5
4
3
2
1
0
rx_stopbit
tx_en
rx_en
soft_reset_n
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
tx_stopbit[1:0]
Table 114. Description of HSU_CTR bits
Bit Symbol
Description
7
HSU wake-up enable.
hsu_wu_en
When set to logic 1 this bit re-activates the NSS / SCL / HSU_RX rising-edge
counter. When the counter is 5 then a signal hsu_on is activated. This signal
is one of the possible wake-up events from Soft-Power-down mode in the
PCR block.
The firmware shall set this bit to logic level 1 just before requesting a
Soft-Power-down mode.
The bit IE1_5 of register IE1 (see Table 13 on page 17) has also to be set to
logic level 1 to enable the corresponding CPU interrupt.
6
start_frame
Enables the preamble filter for next frame.
When set to logic 1 this bit indicates that a new frame is coming. This
re-activates the preamble filter (when enabled), meaning that the first “00 00
FF” characters will not be sent to the FIFO manager.
5:4 tx_stopbit[1:0] Defines the number of stop bit during transmission.
These 2 bits define the number of Stop bit(s) inserted at the end of the
transmitted frame.
The number of Stop bit(s) transmitted is equal to tx_stopbit +1.
3
rx_stopbit
Defines the number of stop bit during reception.
This bit defines the number of Stop bit(s) inserted at the end of the received
frame.
The number of Stop bit(s) expected in reception is equal to rx_stopbit +1.
2
tx_en
Enables the transmission of HSU.
When set to logic 1 this bit enables the transmission of characters.
When set to logic 0, the transmission is disabled only after the completion of
the current transmission.
1
rx_en
Enables the reception of the HSU.
When set to logic 1 this bit enables the reception of characters.
When set to logic 0, the reception is disabled only after the completion of the
current reception.
0
soft_reset_n
HSU Reset.
When set to logic 0, this bit disables the clock of the HSU_RX control,
HSU_TX control and baud rate generator modules.
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8.3.4.7
HSU_PRE register
This register is used to configure the baud rate generator prescaler.The prescaler
enlarges the range of the counter (at the cost of a lower resolution). The division factor of
the prescaler ranges from 1 (20) to 256 (28).
Table 115. HSU_PRE register (SFR: address ADh) bit allocation
Bit
7
6
5
Symbol
Reset
Access
4
3
2
1
0
hsu_prescaler[7:0]
0
0
0
1
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 116. Description of HSU_PRE bits
Bit
Symbol
Description
7 to 0 hsu_prescaler[7:0]
In conjunction with HSU_CNT, defines the HSU baud rate.
Baud rate = fclk / ((hsu_prescaler +1) * hsu_counter)
8.3.4.8
HSU_CNT register
This register is used to configure the baud rate generator counter.
Table 117. HSU_CNT register (SFR: address AEh) bit allocation
Bit
7
6
5
Symbol
Reset
Access
4
3
2
1
0
hsu_counter[7:0]
0
1
1
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 118. Description of HSU_CNT bits
Bit
Symbol
Description
7 to 0 hsu_counter[7:0]
In conjunction with HSU_PRE, defines the HSU baud rate.
Baud rate = fclk / ((hsu_prescaler +1) * hsu_counter)
Here is a table of recommendation for some data rates:
Table 119. Recommendation for HSU data rates
Targeted data
rate
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HSU_CNT
value
HSU_PRE
value
Real HSU
freq
Min
recommended
Host HSU freq
Max
recommended
Host HSU freq
9 600
0x71
0x18
9 516
9 326
9 706
19 200
0x9D
0x08
19 193
18 810
19 576
38 400
0x65
0x06
38 359
37 592
39 126
57 600
0x9D
0x02
57 579
56 428
58 730
115 200
0xEB
0x00
115 404
113 096
117 712
230 400
0x76
0x00
229 831
225 234
234 427
460 800
0x3B
0x00
459 661
450 467
468 854
921 600
0x1D
0x00
935 172
916 468
953 875
1 288 000
0x15
0x00
1 291 429
1 265 600
1 317 257
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8.3.5 USB
The USB module is an USB2.0 compliant device with embedded function.
Special power management features such as a clock divider and clock switch are also
implemented in the device.
8.3.5.1
Features list
The USB module is a USB device only supporting full speed communication scheme. All
embedded functions are passed to the micro controller.
The USB module includes the following features:
•
•
•
•
•
•
•
•
SoftConnect supported
Command GetFrameNumber supported
Interrupt signaling to mController
Control EP0 endpoint of 8 bytes
3 interrupt endpoints of 8 bytes
2 bidirectional bulk endpoints of 64 bytes
resume by host
remote wake up
The endpoints setup is described in the following table.
Table 120. Endpoints Setup
Logical Endpoints OUT Type IN Type
OUT Map IN Map
OUT size IN size
8
Note
Device function description
0
Control
Control
0.0
0.1
1
-
Int
-
0.2
8
2
-
Int
-
0.3
8
3
-
Int
-
0.4
4
Bulk
Bulk
0.5
0.6
8.3.5.2
8
8
64
64
USB interrupt
The interrupt line of the USB module is asserted to indicates to the microcontroller that
there was a transaction on one of the endpoints, or that there is new status information
available.
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8.3.5.3
Resume by host
Resume by host in suspend state: After 3 ms of no USB activity on the bus, the device
goes in suspend. About 2 ms later the device will indicate that it no longer needs the clock
(Clk_Enable_N becomes inactive).
The host can then send a resume to the device. The device needs to wake up and will
require the main clock (USB_Clk_Enable_N becomes active). The main clock starts
running after complete PCR wake up sequence. PLL_LOCK indicates that the main clock
is running stable(a PLL can need several ms to start running at the specified frequency).
The device then knows that the clock is present and can go out of suspend.
3 ms
USB
2 ms
RESUME
IDLE
USB_SUSPEND
USB_Clk_Enable_N
PN533 power down sequence
USB_WakeUp_N
Fig 14. Resume by host/clocks stopped
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Resume by Host before clock is disabled: The host can decide to wake up a
suspended device, before the device has switched off its main clock. The device then
simply goes out of suspend.
3 ms
USB
IDLE
RESUME
USB_SUSPEND
USB_Clk_Enable_N
System clock running
USB_WakeUp_N
Fig 15. Resume by host / clocks running
8.3.5.4
Remote wake up
The remote wake up implemented in the PN533 platform is partly controlled by the micro
controller as depicted below:
3 ms
USB
2 ms
Device receives wake up
command from uC
UpstreamRESUME
IDLE
USB_SUSPEND
USB_Clk_Enable_N
PCR power down sequence
USB_WakeUp_N
Fig 16. RemoteWakeUp by uC
When a remote wake up is requested on an external interrupt (P32_INT0, P33_INT1) or a
RF detector event, the Power Clock and Reset controller (PCR):
• enables the 27.12 MHZ oscillator,
• generates an interrupt to resume the CPU from Power-down mode,
• then the CPU enable the 4 MHZ oscillator, the PLL and the 48 MHZ clock.
The CPU sends a command to the USB module to perform a USB remote wake up, then
the USB module exits from suspend mode and sends a resume on its upstream port.
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Resume by Remote Wake up before clock is disabled: Resume by Remote Wake up
before clock is disabled
If USB_WakeUp_N is made active before the main clock is switched off
(USB_Clk_Enable_N becomes inactive), the device waits until it has been suspended for
2 ms, then wakes up and sends a resume on its upstream port.
8.3.5.5
Softconnect
The following figure shows how the embedded firmware Controlled Connect can be
implemented.
PVDD
DVDD
VBUS
Vbus
Softonnect
USB_UseIntUpRes
Delatt
USB Core
ATX
D+
D-
VSS
PN533
Gnd
Upstream Hub
or Host
Gnd
Fig 17. SoftConnect connection
When USB_SoftConnect_N is active, one of the data lines (D+) must be pulled high. This
is done by using internal switch.
The internal pull up resistor or an external resistor (connected to delatt) can be used to
perform the soft connection. The selection of the pull-up resistor to use is made through
the USB configuration register. Refer to
Table 121 on page 76
Table 121. USB configuration register (6000h)
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Bit
Name
Description
Reset
R/W
7 to 6
-
Reserved
xx
R/W
5
USB_UseIntUpRes It controls switch for internal Upstream resistor 0
when set to logic level 1; external pull up resistor
is used. When set to logic level 0; internal pull
up resistor is used.
R/W
4 to 0
-
R/W
Reserved
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8.3.5.6
USB embedded firmware view
The USB module is mapped into the XRAM memory space. It is accessible into the
peripheral area on the host if internal bus. The communication between the CPU and the
USB module is based on a sequence of command and data exchange.
Table 122. USB Extension memory map
Physical Address
Size
Description
(Bytes)
Peripheral selected
First
Last
0x6003
0x6003
1
Write command to USB module USB
0x6002
0x6002
1
Write data to USB module
0x6001
0x6001
1
Read data from USB
USB
0x6000
0x6000
1
USB configuration
USB
USB
USB Instruction set: The USB instruction set is described here after.
Table 123. USB Instruction set
Name
Recipient
Coding
Data Phase
Get Chip ID
Device
FDh
Read 2 bytes
Get ErrorCode
Device
FFh
Read 1 byte
Get Device Status
Device
FEh
Read 1 byte
Set Device Status
Device
FEh
Write 1 byte
Get Current Frame Number
Device
F5h
Read 2 bytes
Get Interrupt Register
Device
F4h
Read 2 bytes
Set Mode
Device
F3h
Write 2 bytes
Set Endpoints Enable
Device
D8h
Write 2 bytes
Set Address / Enable
Embedded Function
D0h
Write 1 byte
Get Embedded Port Status
Embedded Function
E0h
Read 1 byte
Set Embedded Port Status
Embedded Function
E0h
Write 1 byte
Select Endpoint
Function Control OUT
00h
Read 1 byte (opt)
Function Control IN
01h
Read 1 byte (opt)
Function Endpoint 1 IN
02h
Read 1 byte (opt)
Function Endpoint 2 IN
03h
Read 1 byte (opt)
Function Endpoint 3 IN
04h
Read 1 byte (opt)
Function Endpoint 4 OUT
05h
Read 1 byte (opt)
Function Endpoint 4 IN
06h
Read 1 byte (opt)
Reserved
07h
-
Reserved
08h
-
Reserved
09h
-
Function Control OUT
40h
Read 1 byte
Function Control IN
41h
Read 1 byte
Function Endpoint 1 IN
42h
Read 1 byte
Select Endpoint / Clear
Interrupt
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Table 123. USB Instruction set …continued
Name
Recipient
Coding
Data Phase
Function Endpoint 2 IN
43h
Read 1 byte
Function Endpoint 3 IN
44h
Read 1 byte
Function Endpoint 4 OUT
45h
Read 1 byte
Function Endpoint 4 IN
46h
Read 1 byte
Reserved
47h
-
Reserved
48h
-
Reserved
49h
-
Function Control OUT
40h
Write 1 byte
Function Control IN
41h
Write 1 byte
Function Endpoint 1 IN
42h
Write 1 byte
Function Endpoint 2 IN
43h
Write 1 byte
Function Endpoint 3 IN
44h
Write 1 byte
Function Endpoint 4 OUT
45h
Write 1 byte
Function Endpoint 4 IN
46h
Write 1 byte
Reserved
47h
-
Reserved
48h
-
Reserved
49h
-
Read Buffer
Selected Endpoint
F0h
Read n bytes
Write Buffer
Selected Endpoint
F0h
Write n bytes
Clear Buffer
Selected Endpoint
F2h
Read 1 byte (opt)
Validate Buffer
Selected Endpoint
FAh
none
Set Endpoint Status
Get VChip ID: Command: FDh
Data: Read 2 bytes
The Chip Identification is 12 bits wide. The command divides the chip Identification in
bytes and returns the least significant byte first. The value of this chip ID can be
determined at integration time.
The following table shown the configuration of these 2 bytes:
Table 124. Get Chip ID bytes
Bit Position
7
6
5
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3
2
1
0
DEVREV[1]
Byte 0
Byte 1
4
0
0
0
0
[1]
hardware setting (8 bits) same as DEVREV, see “Device Descriptor”.
[2]
hardware setting (4 bits) same as DEVNAME, see “String Descriptor”
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Get ErrorCode: Command: FFh
Data: Read 1 byte
7
6
5
4
3
2
1
0
X X X 0 0 0 0 0
Power On Value
ErrorCode
ErrorOccured
Reserved
Fig 18. ErrorCode Register
Note that this is a debug command and should not be used for normal operation.
The ’Get Error Code command returns the error code of the last generated error, this
command is for debugging purposes only. The 4 least significant bits form the error code.
Bit 4 ’Error Occurred’ can be cleared by each new transfer.
The following table gives an overview of the Error Codes.
Table 125. Error codes
Error Code
Description
0000
No Error
0001
PID Encoding Error
0010
Unknown PID
0011
Unexpected Packet
0100
Error in Token CRC
0101
Error in Data CRC
0110
Time Out Error
0111
Babble
1000
Error in End of Packet
1001
Sent NAK
1010
Sent Stall
1011
Buffer Overrun Error
1100
Sent Empty Packet (ISO only)
1101
Bitstuff Error
1110
Error in Sync
1111
Wrong Toggle Bit in Data PID, ignored data
Get Device Status: Command: FEh
Data: Read 1 byte
The Get Device Status command returns the Device Status Register. Cf. the Set Device
Status command.
When SuspendChange, ConnectChange and BusReset bit are set, the appropriate bit in
the interrupt register is set and an interrupt is generated to the micro-controller.
The BusReset, SuspendChange and ConnectChange bit are reset by this command.
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Set Device Status: Command: FEh
Data: Write 1 byte
The Set Device Status command changes the Device Status Register. The value of Read
Only bits is ignored.
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0
Power On Value
Connect
ConnectChange
Suspended
SuspendChange
Reset
Reserved. Write 0
Fig 19. Device Status Register
• Connect:
R/W
Writing ’1’ will allow the device to connect its pull up
resistor. Writing ’0’ forces a disconnect. Reading
returns the current connect status.
• ConnectChange:
R
Change of the connect status. Reading clears the
bit.
• Suspended:
R/W
This bit represents the current Suspend state. It is
set to ’1’ when the device hasn’t seen any activity on
its upstream port for more than 3 ms. It is reset to ’0’
on any activity.
When the device is in suspend state (Suspended bit
= ’1’) and the microcontroller writes a ’0’ into it, the
device will generate a remote wake up. When the
device is not suspended, writing a ’0’ has no effect.
Writing a ’1’ into this register has never an effect.
• SuspendChange:
R
The Suspend Change bit is set to ’1’ when the
Suspended bit toggles. The Suspend bit can toggle
because:
– The device goes in the suspended state
– The device receives resume signalling on its
upstream port
The Suspend Change bit is reset after the register
has been read.
• Reset:
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R
The Reset bit is set when the device receives a bus
reset. It is cleared when read.On a bus reset the
device will automatically go to the default state
(unconfigured and responding to address 0).
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Get Current Frame Number: Command: F5h
Data: Read 1 or 2 byte(s)
Data: Write 2 bytes
Get interrupt register: Command: F4h
Data: Read 2 bytes
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0
Power On Value
EmbFuncCtrlOutEnpd
EmbFuncCtrlInEnpd
EmbFuncEnpd1In
EmbFuncEnpd2In
EmbFuncEnpd3In
EmbFuncEnpd4Out
EmbFuncEnpd4In
Reserved
Fig 20. Interrupt Register byte 1
7
6
5
4
3
2
1
0
X X X X 0 0 0 0
Power On Value
Reserved
Resereved
Port 3 Status Register Change
Device Status Register Change
Reverved
Fig 21. Interrupt Register byte 2
This command indicates the origin of an interrupt. The endpoint interrupt bits (bits 0 to 9)
are cleared by selecting the endpoint. The device status register change bit is reset by
reading the device status change register. The Port Status Change Register change bit is
reset by reading the port Status Change Register.
Set Mode:
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Command:
Data:
F3h
Write 2 bytes
0.0.1
Command:
Data:
Set Mode
F3h
Write 2 bytes
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Configuration byte:
7
6
5
4
3
2
1
0
Power On Value
X 0 0 0 0 0 X 1
InterruptOnNAK
Reserved
Reserved
AlwaysPLLClock
Reserved
Reserved
Reserved
Reserved
Fig 22. Configuration byte
• InterruptOnNAK:
A ’1’
indicates that "NAKing" is reported and will generate
interrupt. A ’0’ indicates that only successful
transactions are reported.
• AlwaysPLLClock:
A ’1’
indicates that the internal clocks and PLL are always
running even during suspend state. A ’0’ indicates
that the internal clock, crystal oscillator and PLL are
stopped whenever not needed. To meet the strict
suspend current requirement, this bit needs to be
set to ’0’.
Clock division
7
6
5
4
3
2
1
0
Power On Value
X X 0 0 0 0 1 1
ClkDivFactor
Reserved. Write 0
Fig 23. Clock division
• ClkDivFactor:
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The value indicates clock division factor for CLOCKOUT.
The output frequency is 48 MHz/(N+1) where N is the Clock
Division Factor. The reset value is 3. This will produce the
output frequency of 12 MHz which can then be programmed
up (or down) by the user. This design ensures no glitching
during frequency change. The programmed value will not be
changed by a bus reset.
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Set Endpoints Enable: Command: D8h
Data: Write 2 bytes
Byte 1:
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0
Power On Value
EmbFuncCtrlOutEnpdEnable
EmbFuncCtrlInEnpdEnable
EmbFuncEnpd1InEnable
EmbFuncEnpd2InEnable
EmbFuncEnpd3InEnable
EmbFuncEnpd4OutEnable
EmbFuncEnpd4InEnable
Reserved
Byte 2:
7
6
5
4
3
2
1
0
X X X X X X 0 0
Power On Value
Reserved
Reserved
Reserved
Fig 24. Endpoints enable bytes
This command provides endpoint enable. The enable is defined on physical endpoint level
meaning that for one endpoint the IN and OUT direction can be enabled separately.
Set Address/Enable: Command: D0h
Data: Write 1 byte
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0
Power On Value
DevAddress
DevEnable
Fig 25. Address enable byte
• DevAddress:
• DevEnable:
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The value written becomes the address.
A ‘1’ enables this function
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Get Embedded Port Status: Command: E0h
Data: Read 1 byte
When SuspendChange and BusReset bit are set, the appropriate bit in the interrupt
register is set and an interrupt is generated to the micro-controller.
The Get Embedded Port Status command returns the Embedded Port Status Register.
The BusReset, SuspendChange and ConnectChange bit are reset by this command.
Set Embedded Port Status: Command: E0h
Data: Write 1 byte
The Set Embedded Port Status command changes the Embedded Port Status Register.
The value of Read Only bits is ignored.
7
6
5
4
3
2
1
0
X X X 0 0 0 0 0
Power On Value
Connect
ConnectChange
Suspend
SuspendChange
BusReset
Reserved
Fig 26. Embedded Port Status register
• Connected:
R/W
Writing ’1’ will connect this embedded port. Writing
’0’ will disconnect this embedded port.
• ConnectChange:
R
Change of the connect status. Reading clears the
bit.
• Suspend:
R/W
Embedded port is suspended. Writing ’0’ causes a
remote wake-up if this embedded port is
suspended. Writing a ’1’ has no effect.
• SuspendChange:
R
Suspend state changed. Reading clears the bit
BusReset:REmbedded Port received a SetPortFeature(Reset) request. Reading clears
the bit, puts the port into the enabled state and reports the end of the reset to the host.
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Select Endpoint: Command: 00h - 09h
Data: Read 1 byte (Optional)
This command initializes an internal pointer to the start of the Selected buffer. Optionally,
this command can be followed by a data read, which returns some additional info on the
packet in the buffer.
7
6
5
4
3
2
1
0
X X X 0 0 0 0 0
Power On Value
FullEmptyStatus
StallStatus
SetupPacket
PacketOverwritten
SentNAK
Reserved
Fig 27. Select Endpoint byte
• FullEmptyStatus:
A “1”
indicates the buffer of the selected endpoint is full,
“0” indicates an empty buffer.In case of an OUT
endpoint, this bit is cleared by executing the Clear
Buffer Command, if the buffer has not been over
written.
In case of an IN endpoint, this bit is set by the
Validate Buffer command.
• StallStatus:
• SetupPacket:
A “1”
indicates the selected endpoint is in the stall state.
A “1”
indicates the last received packet for the selected
endpoint was a setup packet.The value of this bit is
updated after each successfully received packet
(i.e. an ACKED package on that particular physical
endpoint).
It is cleared by doing a Select Endpoint/Clear
Interrupt on this endpoint
• PacketOverwritten:
’1’:
The previously received packet was over written by
a setup packet.
The value of this bit is cleared by the ’Select
Endpoint/Clear Interrupt’ command.
• SentNAK:
’1’:
The device has sent a NAK. If the host sends an
OUT packet to a filled OUT buffer, the device returns
NAK. It the host sends an IN token to an empty IN
buffer, the device returns NAK.
This bit is set when a NAK is sent and the Interrupt
On NAK feature is enabled. This bit is reset after the
device has sent an ACK after an OUT packet or
when the device has seen an ACK after sending an
IN packet. This bit is only defined for the two
physical control endpoints.
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Select Endpoint/Clear Interrupt: Command: 40h - 49h
Data: Read 1 byte
Commands 40h to 49h are identical to their Select Endpoint equivalent, with the following
differences:
• The command clears the associated interrupt
• The command clear the Setup and Overwritten bits in case of a control out endpoint
• The read of one byte is mandatory
Set Endpoint Status: Command: 40h - 49h
Data: Write 1 byte
7
6
5
4
3
2
1
0
0 0 0 X X X X 0
Power On Value
Stalled
Reserved
Disable
RateFeedbackMode
Conditional Stall
Fig 28. Endpoint Status byte
• Stalled:
• Disable:
A “1”
indicates the endpoint is stalled.
A “1”
indicates the endpoint is disabled. After a bus-reset
each endpoint is enabled, i.e., this bit is set to ’0’.
• RateFeedbackMode:
’0’:
Interrupt endpoint in ’toggle mode’
’1’:
Interrupt endpoint in ’rate feedback mode’
’1’:
Stall both endpoint zero endpoints, unless the
’Setup Packet’ bit is set. It is only defined for control
OUT endpoints
• Conditional Stall:
Read Buffer: Command: F0h
Data: Read up to n+2 bytes
’n’ is equal to the number of data bytes in the selected buffer.
This command is followed by a number of data reads, which return the contents of the
selected endpoint data buffer. After each read, the internal buffer pointer is incremented
by 1.
The buffer pointer is not reset to the beginning of the buffer by this command. This means
that reading or writing a buffer can be interrupted by any other command (except for
Select Endpoint).
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The data in the buffer are organized as follow:
Table 126. Read buffer bytes
Bit Position
7
6
5
4
3
2
1
0
Byte 0
0/1
0/1
-
-
-
-
-
-
Byte 1
-
Number of Data bytes in buffer
Byte 2
Data byte 0
...
Byte n+1
Data Byte n -1
Write Buffer: Command: F0h
Data: Write up to n+2 bytes
’n’ is equal to the number of data bytes in the selected buffer.
This command is followed by a number of data writes, which load the data buffer of the
selected endpoint. After each write, the internal pointer is incremented by 1. The buffer
pointer is not reset to the beginning of the buffer by the Write Buffer command. This
means that writing a buffer can be interrupted by any other command (except for Select
Endpoint).
The data in the buffer are organized as follow:
Table 127. Write buffer bytes
7
6
5
4
3
2
1
0
Byte 0
Bit Position
0/1
0/1
-
-
-
-
-
-
Byte 1
-
Number of Data bytes in buffer
Byte 2
Data byte 0
...
Byte n+1
Data Byte n -1
Clear Buffer: Command: F2h
Data: Read 1 byte (Optional)
7
6
5
4
3
2
1
0
X X X X X X X 0
Power On Value
PacketOverwritten
Reserved
Fig 29. Clear buffer byte
When a packet is received completely, an internal endpoint buffer full flag is set. All
subsequent packets will be refused by returning a NAK. When the microcontroller has
read the data, it should free the buffer by the Clear Buffer command. When the buffer is
cleared new packets will be accepted.
When bit ’0’ of the optional data byte is ’1’, the previously received packet was over written
by a Setup Packet. A buffer cannot be cleared when its Packet Overwritten bit is set.
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Validate Buffer: Command: FAh
Data: None
When the microprocessor has written data into an IN buffer, it should set the buffer full flag
by the Validate Buffer command.
This indicates that the data in the buffer is valid and can be sent to the host when the next
IN token is received. A control IN buffer cannot be validated when the Packet Overwritten
bit of its corresponding OUT buffer is set.
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8.4 Power management
This chapter defines the power distribution scheme according to the different system
configuration. The PN533 can be supplied by the USB connector on VBUS or directly on
the VBUS, AVDD, DVDD, PVDD and TVDD. Regarding the system configuration (USB
BUS powered, USB non bus powered or HOST powered), the power distribution shall be
different.
8.4.1 USB bus powered
The power distribution is performed from the USB bus. The power delivered to the
different peripherals is controlled by the PN533 chip. The Figure 30 “USB bus
powered”depicts the system approach for the power distribution. When PN533 is supplied
by the USB connector (USB powered) an internal regulator generates the supply voltage
for all the parts, and during the power up phase the inrush current is limited to 100mA.
USB
VBUS
D+
D-
3.6V)
100nF
VBUS
DVDD
100mA
Regulator
PVDD
POR
BG
level shifter+ PADs
VDD
HOST
por-alarm
por-pulse
Digital
Analog
PCR
PLL,OSC, demod,
rf level detect, clock AVDD
gen for demod (IQ),
BG, sensor, rf clock
recovery, VMID.
CPU, UART,RAM, ROM,....
RNG
100nF
SAM
Interface
SAM
SVDD
PN533
Front End
transmitter control
transmitter
TX1
TVDD
100nF
TX2
10uF
filtering
+ Antenna
Fig 31. HOST powered from single source
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8.4.4 HOST powered (double source)
The power distribution is performed from the second source from the Host. The Figure 32
“HOST powered from double source” depicts the system approach for the power
distribution.
VDDPN533 (2.5V -> 3.6V)
100nF
VBUS
DVDD
100mA
Regulator
VDDHOST (1.6V -> 3.6V)
PVDD
POR
BG
por-alarm
por-pulse
100nF
level shifter+ PADs
VDD
HOST
Digital
Analog
PCR
PLL,OSC, demod,
rf level detect, clock AVDD
gen for demod (IQ),
BG, sensor, rf clock
recovery, VMID.
CPU, UART,RAM, ROM,....
RNG
100nF
SAM
Interface
SAM
SVDD
PN533
Front End
transmitter control
transmitter
TX1
TVDD
100nF
TX2
10uF
filtering
+ Antenna
Fig 32. HOST powered from double source
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8.4.5 Low power modes
There are 2 different low power modes.
• “Hard power-down” controlled by the pin RSTPD_N. In that case, the PN533 enters
into the reset state and the maximum consumption depends on the connection of
PN533 to the USB bus or not.
• “Soft power-down” controlled by a register. In that case, the PN533 enters into the idle
state and the maximum consumption depends if PN533 is “USB powered” or not and
if the RF detector is active or not. In that mode the PN533 can be waken up on
external events.
Table 128. Current consumption in power down
Low power mode
Power supply source
Maximum current consumption
Suspend
Powered from USB
200 A (without resistors on D+ / D-)
Suspend with RF detector active Powered from USB
250 A (without resistors on D+ / D-)
hard power-down
Not powered from USB
10 A
soft power-down
Not powered from USB
25 A
soft power-down with RF
detector active
Not powered from USB
30 A
8.4.6 Power-on reset
The Power On Reset (POR) module generates the reset signals for the different parts of
PN533.
The Power On Reset module is used to control the power up, power down and reset
phase of PN533.
As soon as, VDD reaches Vth+Vhys, the system startup phase starts under control of the
PCR.
When the RSTPD_N is asserted, all internal current source are cut and PN533 enters
reset phase.
When the power supply voltage drops below Vth, the IC goes into reset.
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8.4.7 Regulator - short description
The regulator is used to reduce the VBUS voltage to the typical operating voltage of
PN533.
VBUS
VDD
BG
LP
VBG
GND
Fig 33. 3.3 V regulator block diagram
The 3.3V regulator is a linear regulator with resistive feed-back. The regulator uses the
Band-gap for reference voltage
8.4.8 Main switch
In USB bus powered configuration, the PN533 is plugged on a USB connector. The main
switch limits the inrush current to 100 mA max during the powerup. The inrush current
limitation can be disabled through the bit curlimoff (Table 129 “Control_switch_rng register
(address 6106h) bit allocation”).
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8.4.9 SVDD switch
The SVDD switch is used to control power to the secure IC. The switch is controlled by
register Control_switch_rng (address 6106h). The switch is enabled with bit
sic_switch_en. When disabled, the SVDD pin is tied to ground. A current limiter is
incorporated into the switch. Current consumption exceeding 40 mA triggers the limiter
and the status bit sic_switch_overload is set.
Register Control_switch_rng also controls the random generator within the Contactless
Interface Unit (CIU) and the regulator current limitation.
Table 129. Control_switch_rng register (address 6106h) bit allocation
Bit
7
6
5
4
Symbol
-
hide_svdd
_sig
sic_switch
_overload
Reset
0
1
0
0
Access
R
R/W
R
R/W
3
2
1
0
cpu_need
_ rng
random_
dataready
-
0
0
0
1
R/W
R/W
R/W
R
sic_switch curlimoff
_en
Table 130. Description of Control_switch_rng bits
Bit Symbol
Description
7
-
Reserved.
6
hide_svdd_sig
Configures internal state of input signals SIGIN and P34 when
idle. This bit can be used to avoid spikes on SIGIN and P34 when the
SVDD switch is enabled or disabled.
When set to logic 0, internal state of SIGIN and P34 are driven by pads
SIGIN and P34 respectively.
When set to logic 1, internal state of SIGIN is set to logic level 0 and
internal state of P34 is set to logic 1.
5
sic_switch_overload Indicates state of SVDD switch current limiter.
When set to logic 0, indicates that current consumption through SVDD
switch does not exceed limit (40 mA).
When set to logic 1, the SVDD switch current limiter is activated.
4
sic_switch_en
Enables or disables power to SVDD switch.
When set to logic 0, SVDD switch is disabled and SVDD output is tied
to the ground.
When set to logic 1, the SVDD switch is enabled and the SVDD output
delivers power to secure IC and internal pads (SIGIN, SIGOUT and
P34).
3
curlimoff
Configure the regulator to deliver more current than 100 mA.
When set to 0, the 100 mA current limitations is activated.
When set to 1, the 100 mA current limitations is desactivated.
2
cpu_need_rng
Forces random number generator into running mode.
When set to logic 0, random number generator is under control of
Contactless Interface Unit.
When set to logic 1, random number generator is forced to run.
1
random_dataready
Indicates availability of random number.
When set to logic 1, a new random number is available.
Automatically set to logic 0 when register data_rng (address 6105h) is
read.
0
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8.5 Power clock and reset controller
The PCR controller is the controller for the clock generation, power management and
reset architecture for the PN533.
8.5.1 PCR in the system
This block diagram Figure 34 “PN533 Power Management block diagram” shows the
relationship between the PCR, other embedded blocks and external signals.
Table 131. PN533 clock source characteristics
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Clock name
Frequency MHz
Tolerance
Clock source
OSC_CLK27
27.12
14 kHz
OSC 27.12
Output of OSC 27
PLL_CLK96
96
0.25%
USB PLL
Output of USB PLL
USB_CLK
48
0.25%
USB PLL
CPU_CLK
27.12/13.56/6.78
OSC 27
HSU_CLK
27.12
OSC 27
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CPU 80C51
D+
Data/Control
USB
D-
USB
PLL
CLK96_GEN
%2
Gating
CPU_PD
CLOCK_OSCOFF
CPU_CLK
PCR_Control
CLK_ON_N
USB_CLK
USB_INT
CLK48
PLL_CLK96
INT0
STATUS & CONTROL
registers
PLL_LOCK
p32_int0
p33_int1
GPIRQ
27.12MHz
PLL_EN
CLK27_GEN
bit enable
OSC27_STABLE
OSC
27.12MHz
OSC27_CLK
OSC27_EN
%1,2,4
Selection
CPU_CLK
PCR_wakeup
PCR_int0
Gating
POWER_SEQ
SYS_RESET_N
state machine
HSU_CLK
HSU_ON
RS232
OSC27_CLK
RF_DETECT
CL UART
UARTCL_CLK
HPD
Reset
REG_LOW_POWER
PCR
RSTPD_N
POR
VBUS
REGULATOR
DVDD
Fig 34. PN533 Power Management block diagram
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8.5.2 27.12 MHz crystal oscillator
The 27.12 MHz clock applied to the PN533 is the time reference for the embedded
microcontroller. Therefore stability of the clock frequency is an important factor for reliable
operation. It is recommended to adopt the circuit shown in Figure 35.
OSCIN
OSCOUT
PN533
Crystal
27.12 MHz
C
C
Fig 35. 27.12 MHz crystal oscillator connection
8.5.3 PLL for USB clock generation
The 96MHz used by the USB peripheral is derived from the main 27.12MHz by mean of a
semi-fractional PLL. This PLL consists of a ring oscillator running at 96MHZ, an on-chip
70KHz loop filter a divide-by-13 reference divider and a divide-by-46 feedback divider.
The PLL is controlled through several registers (see Table 140 “PCR Control register
(address 6203h) bit allocation”).
Lock
detection
27.12MHz
CLK Ref.
/13
Phase
detector
Lock
Charge
pump
Current Controlled
oscillator
96MHz
CLK Out
/46
Fig 36. USB PLL
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8.5.4 Power-up sequence
In a USB application, the embedded firmware shall start the USB PLL. The embedded
firmware shall follow below sequence:
• Configure MATX in USB mode.
• Enable 96MHz PLL by setting PLL_en bit of PCR control register (6203h) to logic
level 1.
• Wait for the lock of the PLL by polling PLL_lock bit in PCR CER register (6201h).
• When PLL is locked, enable 96 MHz clock by setting CLK_96_en bit of the PCR
control register at logic level one.
• Enable 48 MHz USB clock that is derived from 96MHz clock by setting USB_enable
bit of PCR CER register (6201h) at logic level one.
• Set reset_USB_n bit of PCR control register (6203h) at logic level one.
8.5.5 Low power modes
There are 3 different low power modes.
• Hard-Power-down mode (HPD): controlled by the pin RSTPD_N. The PN533 goes
into reset and power consumption is at a minimum, see Section 8.5.6 “Reset modes”.
• In HSU application, Soft-Power-down mode (SPD): controlled by firmware. See
Section 8.5.7 “Soft-Power-down mode (SPD)” to optimize the power consumption in
this mode.
• In USB application, Suspend mode: controlled by firmware. xxxx
Table 132. Current consumption in low power modes
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Mode
Conditions
Maximum current
consumption
Hard-Power-down
RSTPD_N is set to logic level 0
10 A
Soft-Power-down
with no RF detector
Sequence of Section 8.5.7 is applied
Soft-Power-down
with RF detector active
Sequence of Section 8.5.7 is applied
30 A
Suspend mode
remote wake up disabled
Suspend mode
with remote wake up enabled
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8.5.6 Reset modes
The possible reset mechanisms are listed below:
• Supply rail variation
When DVDD falls below Vth, the POR (Power-On-Reset) asserts an internal reset
signal. The Power Sequencer disables all clocks. When DVDD rises above Vth+Vhys,
the POR deasserts the internal reset signal and the Power Sequencer starts the
power-up sequence. Once the PN533 is out of reset, the RSTOUT_N pin is driven
high.
• Glitch on DVDD
When DVDD falls below Vth for more than 1 s, the POR asserts an internal reset
signal. The power sequencer starts the Power-down sequence. The PN533 goes into
reset and the RSTOUT_N signal is driven low.
• Hard Power-down mode (HPD)
When RSTPD_N is set to logic level 0, the PN533 goes into Hard Power Down (HDP)
mode. The PN533 goes into reset and the RSTOUT_N signal is driven low. The power
consumption is at the minimum. DVDD is tied to ground and ports are disconnected
from their supply rails. The PN533 goes into reset.
8.5.7 Soft-Power-down mode (SPD)
In order to initiate the Soft-Power-down mode with minimal power consumption, the
firmware should:
• Configure I/Os to minimize power consumption
• Shut down unused functions
– Contactless Interface Unit with bit Power-down of SFR register D1h, see Table 180
on page 156.
– Disable the SVDD switch, see Table 130 on page 94
– Power down the RF level detector if RF wake up is not enabled, see Table 288 on
page 198.
• Enable relevant wake-up sources
• Disable unwanted interrupts
• Set to logic level one the CPU_PD bit in PCON register, see Table 7 on page 15
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8.5.8 Suspend mode
After 3 ms of no USB activity on the bus, the device goes in suspend. About 2 ms later the
device will indicate that it no longer needs the clock by setting to logic level one
suspended bit (refer to bit “suspended” of “get device status” USB register at FEh
address).
In order to initiate the Suspend mode with minimal power consumption, the firmware
should:
• Poll the clock_on bit in the CER register at 6201h address
• Configure I/Os to minimize power consumption
• Shut down unused functions
– Contactless Interface Unit with bit Power-down of SFR register D1h, see Table 180
on page 156.
– Disable the SVDD switch, see Table 130 on page 94
– Power down the RF level detector if RF wake up is not enabled, see Table 288 on
page 198.
• Enable relevant wake-up sources; USB wake up source is mandatory
• Disable unwanted interrupts
• Disable CLK_96 MHz Clock, by setting to logic level zero CLK_96_en bit of the PCR
control register at 6203h address
• Disable USB PLL by setting to logic level zero PLL_en bit in PCR control register
• Set logic level one the CPU_PD bit in PCON register, see Table 7 on page 15
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8.5.9 Remote wake-up
The PN533 can be woken up from a Soft-Power-down mode or Suspend mode when an
event occurs on one of the wake up sources, which has been enabled. There are seven
wake-up sources:
•
•
•
•
•
•
•
P32_INT0
P33_INT1
RF field detected
HSU wake-up (valid when in Soft-Power-down mode)
USB wake-up (valid when in Suspend mode)
NFC_WI counters
GPIRQ: P34, P35, DP
When one of these signals is asserted, if its corresponding enable bit is set (see Table 145
on page 107), the Power Sequencer starts the wake-up sequence. The wake up event
can only be serviced if the Power Sequencer is in the Stopped state, which means the
PN533 is fully entered in Soft-Power-down mode.
Figure 37 illustrates the wake-up mechanism, using an event on P33_INT1 as an
example. CPU_CLK is active T1 after the falling edge of P33_INT1 and the PN533 is
ready. T1 depends on the choice of crystal oscillator and its layout. For devices such as
TAS-3225A, TAS-7 or KSS2F, T1 is a maximum of 2 ms. Exit from the Power-down mode
is signaled by CPU_PD going low one clock cycle later.
P33_INT1
(if active low)
OSC27_CLK
CPU_CLK
T1
CPU_PD
Fig 37. Remote wake-up from Power-down with P33 as wake-up source
When woken up, two cases are to be considered: non USB application and USB
application
• In a non USB application, system is ready to operate
• In a USB application, the embedded firmware shall start the USB PLL. It shall then
poll the PLL_lock signal to enable the 96 MHz clocks. When the 96 MHz clock is
enabled, the 48 MHz clock is available.
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8.5.10 PCR extension registers
The PCR is controlled via several registers given in Table 133:
Table 133. PCR registers
Name
Size [bytes] Address offset
Description
Reset
R/W
CFR
1
6200h
Clock Frequency Register
02
R/W
CER
1
6201h
Clock Enable Register
0E
R/W
ILR
1
6202h
Interrupt Level Register
40
R/W
Control
1
6203h
Control
C0
R/W
Status
1
6204h
Status
00
R
Wakeupen
1
6205h
Wake-up Enable
00
R/W
8.5.11 PCR register description
8.5.11.1
CFR register
The Clock Frequency Register is used to select the frequency of the CPU and its
associated peripherals. The clock frequency can be changed dynamically by writing to this
register at any time.
Table 134. PCR CFR register- (address 6200h) bit allocation
Bit
7
6
5
4
3
2
1
Symbol
-
-
-
-
-
-
cpu_freq[1:0]
0
Reset
0
0
0
0
0
0
1
0
Access
R
R
R
R
R
R
R/W
R/W
Table 135. Description of PCR CFR bits
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Bit
Symbol
Description
7 to 2
-
Reserved
1 to 0
cpu_frq[1:0]
Select CPU clock frequency.
cpu_frq[1:0]
CPU clock frequency
00
27.12 MHz
01
13.56 MHz
10
6.78 MHz
11
27.12 MHz
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8.5.11.2
CER register
The Clock Enable Register is used to enable or disable the clock of the USB and HSU
interfaces (frequency is fixed at 27.12 MHz). The clock can be switched on or off at any
time.
This register also contains the PLL_lock signal that the embedded firmware should poll.
Table 136. PCR CER register (address 6201h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
clock_on
PLL_lock
hsu_enable
-
-
usb_enable
Reset
0
0
1
0
1
1
1
0
Access
R
R
R
R
R/W
R
R
R/W
Table 137. Description of PCR CER bits
Bit
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Symbol
Description
7 to 6
-
Reserved.
5
clock_on
USB clock_on signal to poll before entering PN533 into power down.
4
PLL_lock
PLL_lock signal.
3
hsu_enable Enable HSU clock. When 1, HSU is enabled. When 0, HSU is disabled.
2 to 1
-
0
usb_enable Enable USB clock.
Reserved.
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8.5.11.3
ILR register
The Interrupt Level Register is used to program the level of the external interrupts.
Firmware can write to this register at any time.
Table 138. PCR ILR register (address 6202h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
porpulse_
-
enable_pdselif
-
gpirq_level
int1_level
int0_level
latched
Reset
0
1
0
0
0
0
0
0
Access
R
R/W
R
R/W
R
R/W
R/W
R/W
Table 139. Description of PCR ILR bits
Bit Symbol
Description
7
-
Reserved
6
porpulse_latched Indicates that a reset has been generated.
When set to logic level 1, indicates that the system has been reset. The
firmware can write a “0” during the firmware reset sequence.
5
-
Reserved
4
enable_pdselif
Indicates that a reset has been generated.
When set to logic level 1, P33_INT1 directly controls state of host interface
pins:
•
If P33_INT1 is set to logic level 1, host interface output pins are driven
according to selected interface protocol
•
If P33_INT1 is set to logic level 0, host interface output pins are set
into high-impedance state
When set to logic level 0, P33_INT1 does not control host interface pins.
Their state is determined by selected interface protocol.
enable_pdselif
P33_INT1
State of host interface pins
0
x
Active
1
0
High Impedance
1
1
Active
3
-
Reserved.
2
gpirq_level
Selects gpirq interrupt level.
When set to logic level 1, wake-up condition is true when gpirq is high.
When set to logic level 0, wake-up condition is true when gpirq is low.
1
int1_level
Selects P33_INT1 interrupt level.
When set to logic level 1, wake-up condition is true when P33_INT1 is low.
When set to logic level 0, wake-up condition is true when P33_INT1 is
high.
0
int0_level
Selects P32_INT0 interrupt level.
When set to logic level 1, wake-up condition is true when P32_INT0 is
high.
When set to logic level 0, wake-up condition is true when P32_INT0 is low.
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8.5.11.4
PCR Control register
The Control register is used to perform a firmware reset and clear wake-up conditions in
the Status register.
Table 140. PCR Control register (address 6203h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
reset_USB
_n
clock96
_on
PLL_en
-
clear_wakeup_
cond
soft_reset
Reset
1
1
0
0
0
0
0
0
Access
R
R
R/W
R/W
R/W
R
R/W
R/W
Table 141. Description of PCR Control bits
Bit
Symbol
Description
7 to 6 -
Reserved.
5
Enables a USB reset.
reset_USB_n
When set to logic level 1, the reset for the USB block is inactive.
When set to logic level 0, reset for the USB block is active
4
CLK96_on
Enables 96 MHz clock generation.
When set to logic level 1, 96 MHz clocks are enabled.
When set to logic level 0, 96 MHz clocks are disabled.
3
PLL_en
Enables the PLL.
When set to logic level 1, PLL is enabled.
When set to logic level 0, PLL is disabled.
1
clear_wakeup_cond Clears value of wakeupcond in Status register.
When set to logic level 1, wake-up conditions stored in PCR Status
register are set to logic level 0. Bit is set to logic 0 automatically by
hardware.
0
soft_reset
Initiates a firmware reset.
When set to logic level 1, system goes into firmware reset mode. Bit
is set to logic level 0 automatically by hardware after performing
firmware reset sequence.
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8.5.11.5
PCR Status register
The PCR Status register stores the state of the 7 wake-up events, reported within 6 flags.
Table 142. PCR Status register (address 6204h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
Reset
0
gpirq_wu
-
HSU_wu
CIU_wu
USB_wu
int1_wu
int0_wu
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
An event on a given wake-up condition is flagged by a logic level 1 in the associate bit
field.
Table 143. Description of PCR Status bits
Bit Symbol
Description
7
-
Reserved.
6
gpirq_wu
gpirq wake-up event (or function of P34, P35 and DP signals when enabled
and level-controlled).
Set to logic level 1, when PN533 woke up from a GIRQ event (GPIRQ at logic
level 0)[1].
5
-
Reserved.
4
HSU_wu
HSU wake-up event (hsu_on signal).
Set to logic 1, when PN533 woke up from a HSU event (5 rising edges on
HSU_RX) [1].
3
CIU_wu
Contactless wake-up event (RF detected signal or NFC-WI event).
Set to logic 1, when PN533 woke up from a Contactless interrupt [1].
2
USB_wu
USB wake-up event.
Set to logic 1, when the system woke up from a USB interrupt. [1]
1
int1_wu
P33_INT1 wake-up event.
Set to logic 1, when the system woke up from a P33_INT1 interrupt [1].
0
int0_wu
P32_INT0 wake-up event.
Set to logic 1, when the system woke up from a P32_INT0 interrupt.[1].
[1]
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The firmware must set to logic level 0 this bit after reading it (by writing a logic 1 to bit clear_wakeup_cond
in register PCR Control).
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8.5.11.6
Wakeupen register
Register Wakeupen allows the selection of different wake-up events.
Table 144. PCR Wakeupen register (address 6205h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
GPIRQ_
wu_en
-
HSU_on_
en
CIU_wu_
en
clock_on_
en
int1_en
int0_en
Reset
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
Access
Table 145. Description of PCR Wakeupen bits
Bit Symbol
Description
7
-
Reserved.
6
GPIRQ_wu_en
General Purpose IRQ wake-up source enable.
When set to logic 1, a GPIRQ event can wake up PN533.
5
-
Reserved.
4
HSU_on_en
HSU wake-up source enable.
3
CIU_wu_en
When set to logic 1, an HSU event can wake up PN533.
Contactless Interface Unit wake-up source enable.
When set to logic 1, a CIU event (RF detected or NFC-WI event) can
wake up PN533.
2
clock_on_en
USB wake up source enable.
1
int1_en
P33_INT1 wake-up source enable.
0
int0_en
When set to logic 1, a P33_INT1 event can wake up PN533.
P32_INT0 wake-up source enable.
When set to logic 1, a P32_INT0 event can wake up PN533.
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8.6 Contactless Interface Unit (CIU)
The PN533 CIU is a modem for contactless communication at 13.56 MHz. It supports 6
different operating modes
•
•
•
•
•
•
ISO/IEC 14443A/MIFARE Reader/Writer
FeliCa Reader/Writer
ISO/IEC 14443B Reader/Writer
ISO/IEC 14443A/MIFARE KB or MIFARE 4 KB Card emulation
FeliCa Card emulation
ISO/IEC 18092, ECMA 340 NFCIP-1 Peer-to-Peer
The CIU implements a demodulator and decoder for signals from
ISO/IEC 14443A/MIFARE compatible cards and transponders. The CIU handles the
complete ISO/IEC 14443A framing and error detection (Parity & CRC).
The CIU supports MIFARE 1 KB or MIFARE 4 KB emulation products. The CIU supports
contactless communication using MIFARE Higher transfer speeds up to 424 kbit/s in both
directions.
The CIU can demodulate and decode FeliCa coded signals. The CIU digital part handles
the FeliCa framing and error detection. The CIU supports contactless communication
using FeliCa Higher transfer speeds up to 424 kbit/s in both directions.
The CIU supports layers 2 and 3 of the ISO/IEC 1444 B Reader/Writer communication
scheme, except anticollision which must be implemented in firmware as well as upper
layers.
In card emulation mode, the CIU is able to answer to a Reader/Writer command either
according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The CIU
generates the load modulation signals, either from its transmitter or from the LOADMOD
pin driving an external active circuit. A complete secure card functionality is only possible
in combination with a secure IC using the NFC-WI/S2C interface.
Compliant to ECMA 340 and ISO/IEC 18092 NFCIP-1 Passive and Active communication
modes, the CIU offers the possibility to communicate to another NFCIP-1 compliant
device, at transfer speeds up to 424 kbit/s.The CIU handles the complete NFCIP-1
framing and error detection.
The CIU transceiver can be connected to an external antenna for Reader/Writer or
Card/PICC modes, without any additional active component.
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8.6.1 Feature list
•
•
•
•
•
•
Frequently accessed registers placed in SFR space
Highly integrated analog circuitry to demodulate and decode received data
Buffered transmitter drivers to minimize external components to connect an antenna.
Integrated RF level detector
Integrated data mode detector
Typical operating distance of 50 mm in ISO/IEC 14443A/MIFARE or FeliCa in
Reader/Writer mode depending on the antenna size, tuning and power supply
• Typical operating distance of 50 mm in NFCIP-1 mode depending on the antenna
size, tuning and power supply
• Typical operating distance in ISO/IEC 14443A/MIFARE card or FeliCa card operation
mode of about 100 mm depending on the antenna size, tuning and the external field
strength
• Supports MIFARE 1 KB or MIFARE 4 KB emulation encryption in Reader/Writer mode
• Supports MIFARE higher data rate at 212 kbit/s and 424 kbit/s
• Supports contactless communication according to the FeliCa scheme at 212 kbit/s
and 424 kbit/s
•
•
•
•
•
•
•
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Support of the NFC-WI/S2C interface
64 bytes send and receive FIFO-buffer
Programmable timer
CRC Co-processor
Internal self test
2 interrupt sources
Adjustable parameters to optimize the transceiver performance according to the
antenna characteristics
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8.6.2 Simplified block diagram
PN533
80C51
Data
Mode
Detector
Serial
Data
Switch
CL UART
RF
Level
Detector
Analog
Interface
Antenna
FIFO
Contactless Interface Unit
Fig 38. Simplify Contactless Interface Unit (CIU) block diagram
The Analog Interface handles the modulation and demodulation of the analog signals
according to the Card emulation mode, Reader/Writer mode and NFCIP-1 mode
communication scheme.
The RF level detector detects the presence of an external RF-field delivered by the
antenna to the RX pin.
The data mode detector detects a ISO/IEC 14443-A MIFARE, FeliCa or NFCIP-1 mode in
order to prepare the internal receiver to demodulate signals, which are sent to the PN533.
The NFC-WI/S2C interface supports communication to secure IC. It also supports digital
signals for transfer speeds above 424 kbit/s.
The CL UART handles the protocol requirements for the communication schemes in
co-operation with the appropriate firmware. The FIFO buffer allows a convenient data
transfer from the 80C51 to the CIU and vice versa.
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8.6.3 Reader/Writer modes
All indicated modulation indices and modes in this chapter are system parameters. This
means that beside the IC settings a suitable antenna tuning is required to achieve the
optimal performance.
8.6.3.1
ISO/IEC 14443A Reader/Writer
The following diagram describes the communication on a physical level, the
communication overview in the Table 146 describes the physical parameters.
1. PCD to PICC 100% ASK,
Miller Coded,
Transfer speed 106 to 848 kbit/s
Battery
ISO/IEC 14443A
Card / PICC
PN533
HOST
2. PICC to PCD, Subcarrier Load modulation,
Manchester Coded or BPSK,
Transfer speed 106 to 848 kbit/s
Reader/Writer
Fig 39. ISO/IEC 14443A/MIFARE Reader/Writer communication diagram
Table 146. Communication overview for ISO/IEC 14443A/MIFARE Reader/Writer
Communication scheme
Baud rate
ISO/IEC 14443A
MIFARE
106 kbit/s
Bit length
MIFARE higher baud rate
212 kbit/s
128
-------------------------- 9 44s
13,56MHz
64
-------------------------- 4,72s
13,56MHz
424 kbit/s
32
-------------------------- 2 36s
13,56MHz
848 kbit/s
16
-------------------------- 1 18s
13,56MHz
PN533 to
PICC/Card
Modulation
100% ASK
>25% ASK
>25% ASK
>25% ASK
Bit coding
Modified Miller
coding
Modified
Miller coding
Modified
Miller coding
Modified
Miller coding
PICC/Card to
PN533
Modulation
Subcarrier load
modulation
Subcarrier load
modulation
Subcarrier load
modulation
Subcarrier load
modulation
Subcarrier
frequency
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
Bit coding
Manchester coding
BPSK
BPSK
BPSK
The internal CRC co-processor calculates the CRC value according the data coding and
framing defined in the ISO/IEC 14443A part 3, and handles parity generation internally
according to the transfer speed.
With appropriate firmware, the PN533 can handle the complete ISO/IEC 14443A/MIFARE
protocol.
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Fig 40. Data coding and framing according to ISO/IEC 14443A
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8.6.3.2
FeliCa Reader/Writer
The following diagram describes the communication at the physical level. Table 147
describes the physical parameters.
1. Reader/Writer to Card 8 - 30% ASK,
Manchester Coded,
Baud rate 212 to 424 kbit/s
Battery
FeliCa
Card
PN533
HOST
2. Card to Reader/Writer, >12% ASK load modulation,
Manchester Coded,
Baud rate 212 to 424 kbit/s
Reader/Writer
Fig 41. FeliCa Reader/Writer communication diagram
Table 147. Communication overview for FeliCa Reader/Writer
Communication scheme
FeliCa
FeliCa higher baud rate
Baud rate
212 kbit/s
424 kbit/s
Bit length
64
-------------------------- 4,72s
13,56MHz
32
-------------------------- 2,36s
13,56MHz
PN533 to
PICC/Card
Modulation
8 - 30% ASK
8 - 30% ASK
Bit coding
Manchester coding
Manchester coding
PICC/Card to
PN533
Modulation
>12% ASK
>12% ASK
Bit coding
Manchester coding
Manchester coding
With appropriate firmware, the PN533 can handle the FeliCa protocol.
The FeliCa Framing and coding must comply with the following table:
Table 148. FeliCa Framing and Coding
Preamble
00h
00h
00h
SYNC
00h
00h
00h
B2h
LEN
n-Data
CRC
4Dh
To enable the FeliCa communication a 6-byte preamble (00h, 00h, 00h, 00h, 00h, 00h)
and 2-byte SYNC bytes (B2h, 4Dh) are sent to synchronize the receiver.
The following LEN byte indicates the length of the sent data bytes plus the LEN byte itself.
The CRC calculation is done according to the FeliCa definitions with the MSB first.
To transmit data on the RF interface, the 80C51 has to send the LEN and data bytes to the
CIU. The Preamble and SYNC bytes are generated by the CIU automatically and must not
be written to the FIFO. The CIU performs internally the CRC calculation and adds the
result to the frame.
The starting value for the CRC Polynomial is 2 null bytes: (00h), (00h)
Example of frame:
Table 149. FeliCa framing and coding
Preamble
00
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00
00
00
SYNC
00
00
B2
4D
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03
2 Data Bytes
AB
CD
CRC
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8.6.3.3
ISO/IEC 14443B Reader/Writer
The CIU supports layers 2 and 3 of the ISO/IEC 14443B Reader/Writer communication
scheme, except anticollision which must be implemented in firmware as well as upper
layers.
The following diagram describes the communication at the physical level. Table 150
describes the physical parameters.
1. PCD to PICC, 8 - 14% ASK,
NRZ-L Coded,
Transfer speed 106 to 848 kbit/s
Battery
ISO/IEC 14443B
Card / PICC
PN533
HOST
2. PICC to PCD, Subcarrier Load modulation,
BPSK,
Transfer speed 106 to 848 kbit/s
Reader/Writer
Fig 42. ISO/IEC 14443B Reader/Writer communication diagram
With appropriate firmware, the PN533 can handle the ISO/IEC 14443B protocol.
Table 150. Communication overview for ISO/IEC 14443B Reader/Writer
Communication scheme
Baud rate
ISO/IEC 14443B
106 kbit/s
Bit length
Type B higher baud rate
212 kbit/s
128
-------------------------- 9 44s
13,56MHz
8 -14% ASK
16
-------------------------- 1 18s
13,56MHz
Modulation
Bit coding
NRZ-L
NRZ-L
NRZ-L
NRZ-L
PICC/Card to
PN533
Modulation
Subcarrier load
modulation
Subcarrier load
modulation
Subcarrier load
modulation
Subcarrier load
modulation
Subcarrier
frequency
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
Bit coding
BPSK
BPSK
BPSK
BPSK
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8 -14% ASK
32
-------------------------- 2 36s
13,56MHz
848 kbit/s
PN533 to
PICC/Card
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8 -14% ASK
64
-------------------------- 4 78s
13,56MHz
424 kbit/s
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8.6.4 ISO/IEC 18092, ECMA 340 NFCIP-1 operating mode
A NFCIP-1 communication takes place between 2 devices:
• Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication.
• Target: responds to initiator command either in a load modulation scheme in Passive
Communication mode or using a self generated and self modulated RF field for Active
Communication mode.
The NFCIP-1 communication differentiates between Active and Passive communication
modes.
• Active Communication mode means both the initiator and the target are using their
own RF field to transmit data
• Passive Communication mode means that the Target answers to an Initiator
command in a load modulation scheme. The Initiator is active in terms of generating
the RF field.
In order to fully support the NFCIP-1 standard the PN533 supports the Active and Passive
Communications mode at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as
defined in the NFCIP-1 standard.
Battery
Battery
PN533
PN533
HOST
HOST
Initiator: Active
Target: Passive or Active
Fig 43. NFCIP-1 mode
With appropriate firmware, the PN533 can handle the NFCIP-1 protocol, for all
communication modes and data rates, for both Initiator and Target.
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8.6.4.1
ACTIVE Communication mode
Active Communication Mode means both the Initiator and the Target are using their own
RF field to transmit data.
Host
PN533
NFC Initiator
1. Initiator starts the communication
at selected transfer speed
Power to generate
the field
Host
Powered for Digital
Communication
2. Target answers
at the same transfer speed
PN533
NFC Initiator
Host
PN533
NFC Target
Host
PN533
NFC Target
Powered for Digital
Communication
Power to generate
the field
Fig 44. Active NFC mode
The following table gives an overview of the active communication modes:
Table 151. Communication overview for NFC Active Communication mode
Communication scheme
106 kbit/s
212 kbit/s
424 kbit/s
Bit length
128
-------------------------- 9,44s
13,56MHz
64
-------------------------- 4,72s
13,56MHz
32
-------------------------- 2,36s
13,56MHz
100% ASK
8-30%ASK
8-30%ASK
Miller Coded
Manchester Coded
Manchester Coded
100% ASK
8-30%ASK
8-30%ASK
Miller Coded
Manchester Coded
Manchester Coded
Initiator to Target Modulation
Bit coding
Target to Initiator Modulation
Bit coding
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Baud rate
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8.6.4.2
PASSIVE Communication mode
Passive Communication Mode means that the target answers to an Initiator command in a
load modulation scheme.
Host
PN533
NFC Initiator
1. Initiator starts communication
at selected transfer speed
PN533
NFC Target
Power for digital
processing
Power to generate
the field
Host
2. Targets answers using load modulation
at the same transfer speed
PN533
NFC Initiator
Host
Power to generate
the field
PN533
NFC Target
Host
Power for digital
processing
Fig 45. Passive NFC mode
The following table gives an overview of the active communication modes:
Table 152. Communication overview for NFC Passive Communication mode
Communication scheme
Baud rate
ISO/IEC 18092, ECMA 340, NFCIP-1
106 kbit/s
Bit length
212 kbit/s
128
-------------------------- 9,44s
13,56MHz
64
-------------------------- 4 76s
13,56MHz
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424 kbit/s
32
-------------------------- 2 36s
13,56MHz
PN533 to
PICC/Card
Modulation
100% ASK
100% ASK
100% ASK
Bit coding
Modified Miller
coding
Modified
Miller coding
Modified
Miller coding
PICC/Card to
PN533
Modulation
Subcarrier load
modulation
>12% ASK
>12% ASK
Subcarrier
frequency
13.56 MHz/16
No subcarrier
No subcarrier
Bit coding
Manchester coding
Manchester coding
Manchester coding
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8.6.4.3
NFCIP-1 framing and coding
The NFCIP-1 framing and coding in Active and Passive communication modes are
defined in the NFCIP-1 standard: ISO/IEC 18092 or ECMA 340.
8.6.4.4
NFCIP-1 protocol support
The NFCIP-1 protocol is not completely described in this document. For detailed
explanation of the protocol refer to the ISO/IEC 18092 / ECMA340 NFCIP-1 standard.
However the datalink layer is according to the following policy:
• Transaction includes initialization, anticollision methods and data transfer. This
sequence must not be interrupted by another transaction.
• Speed should not be changed during a data transfer
In order not to disturb current infrastructure based on 13.56 MHz general rules to start
NFC communication are defined in the following way:
•
•
•
•
Per default NFCIP-1 device is in target mode, meaning its RF field is switched off.
The RF level detector is active.
Only if application requires the NFCIP-1 device shall switch to Initiator mode.
Initiator shall only switch on its RF field if no external RF field is detected by RF Level
detector during a time of TIDT.
• The initiator performs initialization according to the selected mode.
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8.6.5 Card operating modes
The PN533 can be addressed like a FeliCa or ISO/IEC 14443A/MIFARE card. This means
that the PN533 can generate an answer in a load modulation scheme according to the
ISO/IEC 14443A/MIFARE or FeliCa interface description.
Remark: The PN533 does not support a secure storage of data. This has to be handled
by a dedicated secure IC or a host. The secure IC is optional.
Remark: The PN533 can not be powered by the field in this mode and needs a power
supply.
8.6.5.1
ISO/IEC 14443A/MIFARE card operating mode
With appropriate firmware, the PN533 can handle the ISO/IEC 14443A including the level
4, and the MIFARE protocols.
The following diagram describes the communication at the physical level. Table 153
describes the physical parameters.
1. PCD to PICC, 100% ASK,
Modified Miller Coded,
Transfer speed 106 to 424 kbit/s
Battery
ISO/IEC 14443A
Reader/Writer
PN533
HOST
2. PICC to PCD, Subcarrier Load modulation,
Manchester Coded or BPSK,
Transfer speed 106 to 424kbit/s
Card operating mode
Fig 46. ISO/IEC 14443A/MIFARE card operating mode communication diagram
Table 153. Communication overview for ISO/IEC 14443A/MIFARE Card operating mode
Communication scheme
Baud rate
ISO/IEC 14443A
MIFARE
MIFARE higher baud rate
106 kbit/s
128
-------------------------- 9,44s
13,56MHz
212 kbit/s
424 kbit/s
64
-------------------------- 4 78s
13,56MHz
32
-------------------------- 2 36s
13,56MHz
Reader/Writer
to PN533
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Modulation
100% ASK
100% ASK
100% ASK
Bit coding
Modified Miller
coding
Modified
Miller coding
Modified
Miller coding
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Table 153. Communication overview for ISO/IEC 14443A/MIFARE Card operating mode
Communication scheme
Baud rate
ISO/IEC 14443A
MIFARE
MIFARE higher baud rate
106 kbit/s
128
-------------------------- 9,44s
13,56MHz
212 kbit/s
424 kbit/s
64
-------------------------- 4 78s
13,56MHz
32
-------------------------- 2 36s
13,56MHz
PN533 to
Reader/Writer
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Modulation
Subcarrier load
modulation
Subcarrier load
modulation
Subcarrier load
modulation
Subcarrier
frequency
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
Bit coding
Manchester coding
BPSK
BPSK
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8.6.5.2
FeliCa Card operating mode
With appropriate firmware, the PN533 can handle the FeliCa protocol.
The following diagram describes the communication at the physical level. Table 154
describes the physical parameters.
1. Reader/Writer to Card 8 - 30% ASK,
Manchester Coded,
Baud rate 212 to 424 kbit/s
Battery
FeliCa
Reader/Writer
PN533
HOST
2. Card to Reader/Writer, >12% ASK load modulation,
Manchester Coded,
Baud rate 212 to 424 kbit/s
Card operating mode
Fig 47. FeliCa card operating mode communication diagram
Table 154. Communication overview for FeliCa Card operating mode
Communication scheme
FeliCa
FeliCa higher baud rate
Baud rate
212 kbit/s
424 kbit/s
Bit length
64
-------------------------- 4,72s
13,56MHz
32
-------------------------- 2,36s
13,56MHz
Reader/Writer to
PN533
Modulation
8 - 30% ASK
8 - 30% ASK
Bit coding
Manchester coding
Manchester coding
PN533 to
Reader/Writer
Modulation
>12% ASK
>12% ASK
Bit coding
Manchester coding
Manchester coding
8.6.6 Overall CIU block diagram
The PN533 supports different contactless communication modes. The CIU supports the
internal 80C51 for the different selected communication schemes such as Card Operation
mode, Reader/Writer Operating mode or NFCIP-1 mode up to 424 kbit/s. The CIU
generates bit- and byte-oriented framing and handles error detection according to these
different contactless protocols.
Higher transfer speeds up to 3.39 Mbit/s can be handled by the digital part of the CIU. To
modulate and demodulate the data an external circuit has to be connected to the
communication interface pins SIGIN/SIGOUT.
Remark: The size and tuning of the antenna have an important impact on the achievable
operating distance.
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PN533
80C51
CIU
State Machine
Control Register bank
CIU_Command register
Programmable timer
CIU FIFO control
CIU FIFO control
CIU interrupt control
CIU 64-byte FIFO
CRC16 generation & check
MIFARE Classic unit
Parallel/Serial Converter
Random Number Generator
Bit Counter
Antenna presence Self Test
Parity Generation & Check
Frame Generation & Check
Bit
Bit decoding
decoding
Bit coding
Card Mode Detector
Clock generation
Filtering
Distribution
LOADMOD
Serial Data Switch
Amplitude
Amplitude
Rating
rating
Analog-to-Digital Converter
Reference
Voltage
Temperature
sensor
RF clock
recovery
I-channel
Amplifier(LNA)
Q-channel
Amplifier(LNA)
I-channel
Demodulator
Q-channel
Demodulator
VMID
RX
RF level
Detector
SIGIN
SIGOUT
Transmitter control
TX1 driver
TX2 driver
TX1
TX2
Fig 48. CIU detailed block diagram
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8.6.7 Transmitter control
The signals delivered by the transmitter are on pins TX1 and pin TX2. The supply and
grounds of the transmitter drivers are TVDD, TVSS1 and TVSS2.
The signals delivered are the 13.56 MHz energy carrier modulated by an envelope signal.
It can be used to drive an antenna directly, using a few passive components for matching
and filtering, see Section 13 “Application information” on page 227. The signals on TX1
and TX2 can be configured by the register CIU_TxControl, see Table 213 on page 170.
The modulation index can be set by adjusting the impedance of the drivers. The
impedance of the p-driver can be configured by the registers CIU_CWGsP and
CIU_ModGsP. The impedance of the n-driver can be configured by the registers
CIU_GsNOn and CIU_GsNOFF. Furthermore, the modulation index depends on the
antenna design and tuning.
Remark: It is recommended to use a modulation index in the range of 8% for the FeliCa
and NFCIP-1 communication scheme at 212 and 424 kbit/s.
The registers CIU_TxMode and CIU_TxAuto control the data rate and framing during the
transmission and the setting of the antenna driver to support the different requirements at
the different modes and transfer speeds.
In the following tables, these abbreviations are used:
•
•
•
•
•
RF: 13.56 MHz clock derived from 27.12 MHz quartz divided by 2
RF_n: inverted 13.56 MHz clock
GsPMos: Conductance of the transmitter PMOS
GsNMos: Conductance of the transmitter NMOS
CWGsP: PMOS conductance value for Continuous Wave (see Table 250 on
page 187)
• ModGsP: refers to ModGsP[5:0], PMOS conductance value for Modulation (see
Table 251 on page 187)
• CWGsNOn: refers to CWGsP[5:0], NMOS conductance value for Continuous Wave
(see Table 248 on page 186)
• ModGsNOn: NMOS conductance value for Modulation when generating RF field (see
Table 248 on page 186)
• CWGsNOff: NMOS conductance value for Continuous Wave when no RF is
generated by the PN533 itself (see Table 240 on page 182)
• ModGsNOff: NMOS conductance value for modulation when load Modulation (see
Table 240 on page 182)
Remark: If only 1 driver is switched on, the values for ModGsNOn and CWGsNOn are
used for both drivers.
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Table 155. Settings for TX1
TX1
Force
InvTx1 InvTx1 Envelope TX1
RFEn 100ASK RFON RFOFF
0
1
X
0
X
0
0
GsPMos GsNMos
0
0
ModGsNOff
1
0
CWGsNOff
1
0
1
1
1
CWGsP
X
0
RF
ModGsP
ModGsNON
1
RF
CWGsP
CWGsNON
RF_n ModGsP
ModGsNON
ModGsP
1
X
0
1
RF_n CWGsP
CWGsNON
1
0
X
0
0
ModGsNON
1
RF
0
0
ModGsNON
1
RF_n CWGsP
CWGsNON
1
1
X
CWGsP
If TX1RFEN is set to logic level 0, the pin TX1 is set to logic 0 or 1 depending
on InvTx1RFOFF. The bit Force 100ASK has no effect. Envelope modulates
the transconductance value.
If TX1RFEN is set to logic level 1, the RF phase of TX1 is depending on
InvTx1RFON. The bit Force100ASK has effect; when Envelope is set to
logic level 0, TX1 is pulled to ground.
CWGsNON
Table 156. Settings for TX2
TX2 Force
TX2CW InVTx2 InvTx2 Envelope TX2
RFEn 100ASK
RFON RFOFF
0
X
0
X
0
1
1
X
0
0
0
1
0
0
1
ModGsP
1
1
CWGsP
0
0
CWGsNOff
1
0
CWGsNOff
0
1
CWGsP
1
1
CWGsP
Remarks
ModGsNOff If Tx2RFEn is set to logic 0, the pin TX2 is forced to 0 or 1 depending on
CWGsNOff the InvTx2RFOFF bit. The bit ForceASK100 has no effect. The signal
Envelope modulates the transconductance value
When Tx2CW bit is set, the transconductance values are always
CWGsP or CWGsNOff
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TX2 Force
TX2CW InVTx2 InvTx2 Envelope TX2
RFEn 100ASK
RFON RFOFF
GsPMos GsNMos
1
0
1
0
X
0
1
RF
1
X
0
RF_n
1
RF_n
ModGsP ModGsNOn When TX2RFEn is set to logic level 1 and Force100ASK set to logic
CWGsP CWGsNOn level 0, the phase of TX2 is depending on InvTx2RFON. If Tx2CW bit is
set to logic level 1, the transconductance values are always CWGsP or
ModGsP ModGsNOn CWGsNOn, independent of Envelope.
CWGsP CWGsNOn
X
RF
CWGsP
CWGsNOn
CWGsP
CWGsNOn
CWGsP
ModGsNOn If TX2RFEn is set to logic level 1 and TX2CW to logic level 0, the bit
CWGsNOn Force100ASK has effect; when Envelope is set to logic level 0, TX2 is
pulled to ground.
ModGsNOn
1
0
1
X
X
RF_n
0
0
X
0
0
1
RF
0
1
X
0
1
RF_n
CWGsP
CWGsNOn
0
X
X
RF
CWGsP
CWGsNOn
1
X
X
RF_n
CWGsP
CWGsNOn
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0
X
RF
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Table 156. Settings for TX2 …continued
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8.6.8 RF level detector
The RF level detector is integrated to fulfill NFCIP-1 protocol requirements (e.g. RF
collision avoidance).
Furthermore the RF level detector can be used to wake up the PN533 and to generate an
interrupt.
The sensitivity of the RF level detector is adjustable in a 4-bit range using the bits RFLevel
in register CIU_RFCfg (see Table 246 on page 185). The sensitivity itself depends on the
antenna configuration and tuning.
Possible sensitivity levels at the RX pin are listed below:
Table 157. Setting of the RF level detector
VRx typical [Vpp]
CIU Power-down bit set to logic
CIU_RFCfg setting
with additional amplifier
2
1.9
1.35
1.3
1110b
0.95
0.9
1101b
0.6
0.57
1100b
0.41
0.40
1011b
0.28
0.27
1010b
0.17
0.17
1001b
0.12
0.12
1000b
1xxx1111b
-
0111b[1]
1xxx1110b
0.055
-
0110b[1]
1xxx1101b
0.040
-
0101b[1]
1xxx1100b
-
-
0100b[1]
1xxx1011b[1]
-
-
0011b[1]
1xxx1010b[1]
-
-
0010b[1]
1xxx1001b[1]
-
-
0001b[1]
1xxx1000b[1]
-
0000b[1]
1xxx0111b[1]
0.085
[1]
CIU_RFCfg setting
1111b
Due to noise, it is recommended not to use this setting to avoid misleading results.
To increase the sensitivity of the RF level detector an amplifier can be activated by setting
the bit RFLevelAmp in register CIU_RFCfg to logic level 1 (see Table 246 on page 185).
Remark: With typical antenna, lower sensitivity levels without the additional amplifier set
(below 1000b) can provoke misleading results because of intrinsic noise in the
environment.
Remark: For the same reasons than above, it is recommended to use the RFLevelAmp
only with upper RF level settings (above 1001b).
Remark: During the CIU Power-down mode the additional amplifier of the RF level
detector is automatically switched off to ensure that the power consumption is minimal.
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8.6.9 Antenna presence self test
The goal of the Antenna Presence Self Test is to facilitate at assembly phase the
detection of the absence of the antenna and/or antenna matching components. Such a
detection is done by mean of measuring the current consumption.
8.6.9.1
Principle
The principle is explained with typical antenna tuning and matching components.
CRx
RX
R1
R2
VMID
Cvmid
PN533
L0
RQ
C1
TX1
C0
TVSS1
TVSS2
C2
Antenna
C0
C2
TX2
L0
RQ
C1
3
2
1
Fig 49. Disconnection localization for the antenna detection
The testing operation can be managed via a dedicated register Table 159 on page 128
and requires the transmitter to be activated. When activated by asserting bit 0, the
detector will monitor the current consumption through the internal low dropout voltage
regulator. Any violation to the current limits will be reported via bits 7 and 6 of the register.
Several levels of detection can be programmed through the register to offer a large panel
of compatibility to different type of antennas. The high current threshold can be
programmed from 40 mA to 150 mA with 15 mA steps (total current consumption of the
IC). The low current threshold can be programmed from 5mA to 35 mA with 10 mA step
(total current consumption of the IC).
There is no dedicated pin for the output of the detector. The result of the detection is to be
read out from the antenna test register.
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• Cases 1 and 2: If the antenna and/or the tuning network are not connected, the TVDD
current is higher than the nominal one. The antenna detector detects this higher
consumption and the andet_up bit in andet_control register is set to high
• Case 3: If the EMC filter is not correctly connected, the current within TVDD is lower
than the nominal one. The antenna detector detects this lower consumption and the
andet_bot bit in andet_control register is set to high.
To have this functionality working properly it is needed to have the transmitter generating
some RF in the antenna.
8.6.9.2
Antenna presence detector register
Table 158. andet_control register (address 610Ch) bit allocation
Bit
7
6
andet_bot
andet_up
Reset
0
0
0
0
0
0
0
0
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Symbol
5
4
3
andet_ithl[1:0]
2
1
andet_ithh[2:0]
0
andet_en
Table 159. Description of andet_control bits
Bit
Symbol
Description
7
andet_bot
A too low power consumption has been detected
6
andet_up
A too high power consumption has been detected
5 to 4
andet_ithl[1:0
Set the low current consumption threshold to be detected
Define the overcurrent threshold
00: 6 mA
01: 18 mA
10: 29 mA
11: 40 mA
3 to 1
andet_ithh[2:0]
Set the high current consumption threshold to be detected
000: 38 mA
001: 50 mA
010: 64 mA
011: 76 mA
100: 89 mA
101: 102 mA
110: 115 mA
111: 127 mA
0
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andet_en
Enable the detection of the antenna presence detector functionality.
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8.6.10 Random generator
The random generator is used to generate various random number needed for the
NFCIP-1 protocol, as well as for MIFARE security.
It can also be used for test purpose, by generating random data through the field.
Table 160. Data_rng register (address 6105h) bit allocation
Bit
7
6
5
4
Symbol
3
2
1
0
data_rng
Reset
Access
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 161. Description of Data_rng bits
Bit
Symbol
Description
7 to 0
data_rng
Random number data register.
The Control_switch_rng register can also be used to control the behaviour of the SVDD
switch.
Table 162. Control_switch_rng register (address 6106h) bit allocation
Bit
7
6
5
Symbol
-
Reset
0
1
0
Access
R
R/W
R
4
3
2
1
0
-
cpu_need_
rng
random_
dataready
-
0
0
0
0
1
R/W
R
R/W
R/W
R
hide_svdd_ sic_switch_ sic_switch_
sig
overload
en
Table 163. Description of Control_switch_rng bits
Bit Symbol
Description
7
-
Reserved.
6
hide_svdd_sig
Configure the internal state of SIGIN and P34 in an idle state.
This bit can be used to avoid spikes on SIGIN and P34 when the
SVDD switch becomes enabled or disabled.
When set to logic 0, the internal state of SIGIN and P34 signals are
driven by respectively the pads SIGIN and P34.
When set to logic 1, the internal state of SIGIN is fixed to 0 and the
internal state of P34 is fixed set to logic 1.
5
sic_switch_overload
State of the current limitation of the SVDD switch.
When set to logic 0, it indicates that the current consumption into the
SVDD switch does no exceed the limit.
When set to logic 1, the current limitation of the SVDD switch is
activated by the switch.
4
sic_switch_en
Enable of the SVDD switch.
When set to logic 0, the SVDD switch is disabled and the SVDD output
power is tied to the ground.
When set to logic 1, the SVDD switch is enabled and the SVDD output
deliver power to the secure IC and to the internal pads (SIGIN,
SIGOUT and P34).
3
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Reserved
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Table 163. Description of Control_switch_rng bits …continued
Bit Symbol
Description
2
Force the random number generator in running mode.
cpu_need_rng
When set to logic 0, the random number generator is under control of
the CIU.
When set to logic 1, the random number generator is forced to run.
1
random_dataready
Indicates availability of random number.
When set to logic 1, it indicates that a new random number is
available.
It is automatically set to logic 0 when the register data_rng is read.
0
-
Reserved.
8.6.11 Data mode detector
The data mode detector is able to detect received signals according to the
ISO/IEC 14443A/MIFARE, FeliCa or NFCIP-1 schemes and the standard baud rates for
106 kbit/s, 212 kbit/s and 424 kbit/s in order to prepare the internal receiver in a fast and
convenient way for further data processing.
The data mode detector can only be activated by the AutoColl command (see Section
8.6.20.12 “AutoColl command” on page 147). The mode detector is reset, when no
external RF field is detected by the RF level detector.
sfr_rd
sfr_wr
host_rd
host_wr
Address
Data_in
Data_out
cluart_clk
cluart_reset
CPU access interface
The data mode detector could be switched off during the Autocoll command by setting the
bit ModeDetOff in the register Mode to logic level 1 (see Table 208 on page 167).
CL UART
and
FIFO
test_control
Registers
Register settings
for the detected mode
NFC @ 106 kbit/s / ISO/IEC 14443A
NFC @ 212 kbit/s / FeliCa
NFC @ 424 kbit/s / FeliCa
Data Mode Detector
Receiver
RX
I / Q Demodulator
Fig 50. Data mode detector
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8.6.12 Serial data switch
Two main blocks are implemented in the CIU. A digital block comprising state machines,
coder and decoder logic and an analog block with the modulator and antenna drivers,
receiver and amplifier. The Serial Data Switch is the interface between these two blocks.
The Serial Data Switch can route the interfacing signals to the pins SIGIN and SIGOUT.
SIGOUT and SIGIN are mainly used to enable the NFC-WI/S2C interface in the secure IC
to emulate card functionality with the PN533. SIGIN is capable of processing a digital
signal on transfer speeds above 424 kbit/s. SIGOUT pin can also provide a digital signal
that can be used with an additional external circuit to generate transfer speeds at
106 kbit/s, 212 kbit/s, 424 kbit/s and above.
Load modulation is usually performed internally by the CIU, via TX1 and TX2. However, it
is possible to use LOADMOD to drive an external circuitry performing load modulation at
the antenna (see optional circuitry of Figure 64 on page 227).
The Serial Data Switch is controlled by the registers CIU_TxSel (see Table 218 on
page 172) and CIU_RxSel (see Table 220 on page 173).
8.6.12.1
Serial data switch for driver and loadmod
The following figure shows the serial data switch for pins TX1 and TX2.
DriverSel
Internal
coder
invert if
INVMOD=1
Tristate
TxMIX
1
0
AND
SIGIN
00
01
10
11
To driver TX1 and TX2
0- -> ModGsN/P
1 -->CWGsN/P
Envelope
1
invert if
POLSIGN=0
Fig 51. Serial data switch for TX1 and TX2
SIGIN is in general only used for secure IC communication. If TxMix is set to logic 1 (see
Table 218 on page 172), the driver pins are simultaneously controlled by SIGIN and the
internal coder.
The following figure shows the serial data switch for the LOADMOD pin.
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LoadModSel
Internal
coder
invert if
INVMOD=1
Tristate
TxMIX
0
LOADMOD
Envelope
1
AND
SIGIN
00
01
10
11
invert if
POLSIGN=0
LoadModTst
0
1
RFU
TstBusbit
00
01
10
11
Fig 52. Serial data switch for LOADMOD pin
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8.6.13 NFC-WI/S2C interface support
The NFC-WI/S2C provides the possibility to directly connect a secure IC to the PN533 in
order to act as a contactless smart card IC via the PN533. The interfacing signals can be
routed to the pins SIGIN and SIGOUT. SIGIN can receive either a digital FeliCa or digital
ISO/IEC 14443A signal sent by the secure IC. The SIGOUT pin can provide a digital
signal and a clock to communicate to the secure IC. A secure IC can be a smart card IC
provided by NXP Semiconductors.
The PN533 generates the supply SVDD to the secure IC. The pins SIGIN and SIGOUT
are referred to this supply, as well as pin P34 / SIC_CLK, which can be used as an extra
pin for the connection to a secure IC.
The following figure outlines the supported communication flows via the PN533 to the
secure core IC.
Host
1. Wired Card mode
PN533
Host Interfaces
80C51
P34
FIFO and state machine
CIU
SIGOUT
secure IC
Serial Data Switch
SIGIN
Analog + CL UART
2. Card emulation mode
(Virtual Card mode)
Fig 53. Communication flows supported by the NFC-WI interface
Configured in the Wired Card mode the host controller can directly communicate to the
secure IC via SIGIN/SIGOUT. In this mode the PN533 generates the RF clock and
performs the communication on the SIGOUT line. To enable the Wired Card mode the
clock has to be derived by the internal oscillator of the PN533 (see bits sic_clock_sel in
Table 266 on page 191.)
Configured in Card emulation mode the secure IC can act as contactless smart card IC
via the PN533. In this mode the signal on the SIGOUT line is provided by the RF field of
the external Reader/Writer. To enable the Virtual Card mode the clock derived by the
external RF field has to be used.
The configuration of the NFC-WI/S2C interface differs for the FeliCa and MIFARE scheme
as outlined in the following chapters.
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8.6.13.1
Signal shape for FeliCa NFC-WI/S2C interface support
The FeliCa secure IC is connected to the PN533 via the pins SIGOUT and SIGIN.
The signal at SIGOUT contains the information of the 13.56 MHz clock and the digitized
demodulated signal. The clock and the demodulated signal are combined by using the
logical function exclusive OR; XOR.
To ensure that this signal is free of spikes, the demodulated signal is digitally filtered first.
The time delay for the digital filtering is in the range of one bit length. The demodulated
signal changes only at a positive edge of the clock.
The register CIU_TxSel (see Table 218 on page 172) controls the setting at SIGOUT
clock
demodulated
signal
signal on
SIGOUT
Fig 54. Signal shape for SIGOUT in FeliCa secure IC mode
The response from the FeliCa secure IC is transferred from SIGIN directly to the antenna
driver. The modulation is done according to the register setting of the antenna drivers.
The clock is switched to P34 / SIC_CLK (see sic_clk_p34_en bit in Table 178 on
page 155).
clock
signal on
SIGIN
signal on
antenna
Fig 55. Signal shape for SIGIN in FeliCa secure IC mode
Remark: The signal on antenna is shown in principle only. This signal is sinusoidal. The
clock for SIGIN is the same as the clock for SIGOUT.
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8.6.13.2
Signal shape for ISO/IEC14443A and MIFARE NFC-WI/S2C support
The secure IC, e.g. the SmartMX is connected to the PN533 via the pins SIGOUT, SIGIN
and P34 / SIC_CLK.
The signal at SIGOUT is a digital 13.56 MHz Miller coded signal between PVSS and
SVDD. It is either derived from the external 13.56 MHz carrier signal when in Virtual Card
Mode or internally generated when in Wired Card mode.
The register CIU_TxSel controls the setting at SIGOUT.
Note: The clock settings for the Wired Card mode and the Virtual Card mode differ. Refer
to the description of the bit SicClockSel in register CIU_TestSel1.
Fig 56. Signal shape for SIGOUT in NFC-WI mode
The signal at SIGIN is a digital Manchester coded signal compliant with ISO/IEC 14443A
with a subcarrier frequency of 847.5 kHz generated by the secure IC.
Fig 57. Signal shape for SIGIN in NFC-WI mode
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8.6.13.3
NFC-WI/S2C initiator mode
The PN533 includes 2 counters of 127 and 31, with digital filtering, to enable activation
from the secure IC (ACT_REQ_Si), or the command to go from data to command mode
(ESC_REQ).
Table 164. NFC_WI_control register (address 610Eh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
-
nfc_wi_status
-
nfc_wi_en_
act_req_im
nfc_wi_en_
clk
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R/W
R/W
R/W
Table 165. Description of NFC_WI_control bits
Bit
Symbol
Description
7 to 4
-
Reserved.
3
nfc_wi_status
Indicates a NFC-WI counter has reached its limit.
Set to logic 1, when the counter has reached its limit. It can also
be used as an interrupt for the 80C51 if the IE0_6 bit is set to
logic level 1 (see Table 10 on page 16).
2
-
Reserved.
1
nfc_wi_en_act_req_im Selection of the NFC-WI counter. This bit is used to select the
31 or 127 counter.
When set to logic 0, the 31 counter is selected.
When set to logic 1, the 127 counter is selected.
0
nfc_wi_en_clk
Enable the NFC-WI counters on SIGIN.
When set to logic level 1, the counters can run and count the
clock cycles within 2 and 12 MHz.
8.6.14 Hardware support for FeliCa and NFC polling
8.6.14.1
Polling sequence functionality for initiator
1. Timer: The CIU has a timer, which can be programmed to generate an interrupt at the
end of each timeslot, or if required at the end of the last timeslot only.
2. The receiver can be configured to receive frames continuously. The receiver is ready
to receive immediately after the last frame has been transmitted. This mode is
activated by setting to logic level 1 the bit RxMultiple in the register CIU_RxMode. It
has to be set to logic level 0 by firmware.
3. The CIU adds one byte at the end of every received frame, before it is transferred into
the FIFO buffer. This byte indicates whether the received frame is correct (see
register Err). The first byte of each frame contains the length byte of the frame.
4. The length of one frame is 18 or 20 bytes (+1 byte error Info). The size of the FIFO is
64 bytes. This means 3 frames can be stored in the FIFO at the same time. If more
than 3 frames are expected, the 80C51 has to read out data from the FIFO, before the
FIFO is filled completely. In the case that the FIFO overflows, data is lost. (See error
flag BufferOvfl).
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8.6.14.2
Polling sequence functionality for target
1. The 80C51 has to configure the CIU with the correct polling response parameters for
the Polling command.
2. To activate the automatic polling in target mode, the AutoColl Command has to be
activated.
3. The CIU receives the polling command send out by an initiator and answers with the
polling response. The timeslot is selected automatically (The timeslot itself is
randomly generated, but in the range 0 to TSN, which is defined by the polling
command). The CIU compares the system code, stored in byte 17 and 18 of the
Config Command with the system code received with the polling command by an
initiator. If the system code is equal, the CIU answers according to the configured
polling response. The system code FF(hex) acts as a wildcard for the system code
bytes (i.e. a target of a system code 1234(hex) answers to the polling command with
one of the following system codes 1234(hex), 12FF(hex), FF34 (hex) or FFFF(hex)). If
the system code does not match no answer is sent back by the PN533. If a valid
command, which is not a Polling command, is received by the CIU, no answer is sent
back and the command AutoColl is stopped. The received frame is stored in the FIFO.
8.6.14.3
Additional hardware support for FeliCa and NFC
Additionally to the polling sequence support for the FeliCa mode, the PN533 supports the
check of the LEN-byte.
The received LEN-byte is checked by the registers CIU_FelNFC1 and CIU_FelNFC2:
DataLenMin in register CIU_FelNFC1 defines the minimum length of the accepted frame
length. This register is 6 bits long. Each value represents a length of 4.
DataLenMax in register CIU_FelNFC2 defines the maximum length of the accepted
frame. This register is 6 bits long. Each value represents a length of 4. If set to logic 0 this
limit is switched off. If the length is not in the supposed area, the packed is not transferred
to the FIFO and receiving is kept active.
Example 1:
• DataLenMin = 4
– The length shall be greater or equal 16.
• DataLenMax = 5
– The length shall be smaller than 20. Valid area: 16, 17, 18, 19
Example 2:
• DataLenMin = 9
– The length shall be greater or equal 36.
• DataLenMax = 0
– The length shall be smaller than 256. Valid area: 36 to 255
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8.6.15 CRC co-processor
The CRC preset value of the CRC co-processor can be configured to 0000h, 6363h,
A671h or FFFFh depending of the bits CRCPreset in the register Mode.This is only valid
when using CalcCRC command (see Section 8.6.20.7 “CalcCRC command” on page
145).
During a communication, the preset value of the CRC coprocessor is set according to the
bits CIU_RxMode and CIU_TxMode.
The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1.
The CRC co-processor is configurable to handle the different MSB and LSB requirements
for the different protocols.The bit MSBFirst in the register CIU_Mode indicates that the
data will be loaded with MSB first
The registers CRCResult-Hi and CRCResult-Lo indicate the result of the CRC calculation.
8.6.16 FIFO buffer
An 64*8 bits FIFO buffer is implemented in the CIU. It buffers the input and output data
stream between the 80C51 and the internal state machine of the CIU. Thus, it is possible
to handle data streams with lengths of up to 64 bytes without taking timing constraints into
account.
8.6.16.1
Accessing the FIFO buffer
The FIFO-buffer input and output data bus is connected to the register CIU_FIFOData.
Writing to this register stores one byte in the FIFO-buffer and increments the internal
FIFO-buffer write-pointer. Reading from this register shows the FIFO-buffer contents
stored at the FIFO-buffer read-pointer and decrements the FIFO-buffer read-pointer. The
distance between the write- and read-pointer can be obtained by reading the register
CIU_FIFOLevel.
When the 80C51 starts a command, the CIU may, while the command is in progress,
access the FIFO-buffer according to that command. Physically only one FIFO-buffer is
implemented, which can be used in input- and output direction. Therefore the 80C51 has
to take care, not to access the FIFO-buffer in an unintended way.
8.6.16.2
Controlling the FIFO buffer
Besides writing to and reading from the FIFO-buffer, the FIFO-buffer pointers might be
reset by setting the bit FlushBuffer in the register CIU_FIFOLevel. Consequently, the
FIFOLevel[6:0] bits are set to logic level 0, the bit BufferOvfl in the register CIU_Error is
set to logic level 0, the actually stored bytes are not accessible anymore and the
FIFO-buffer can be filled with another 64 bytes again.
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8.6.16.3
Status information about the FIFO buffer
The 80C51may obtain the following data about the FIFO-buffers status:
• Number of bytes already stored in the FIFO-buffer: FIFOLevel[6:0] in register
CIU_FIFOLevel
• Warning, that the FIFO-buffer is quite full: HiAlert in register CIU_Status1
• Warning, that the FIFO-buffer is quite empty: LoAlert in register CIU_Status1
• Indication, that bytes were written to the FIFO-buffer although it was already full:
BufferOvfl in register CIU_Error.
BufferOvfl can be set to logic level 0 only by setting to logic level 1 bit FlushBuffer in
the register CIU_FIFOLevel.
The CIU can generate an interrupt signal
• If LoAlertIEn in register CIU_CommIEn is set to logic 1, it will set to logic level 1
CIU_IRQ_0 in the register CIU_Status1, when LoAlert in the same register changes to
logic level 1.
• If HiAlertIEN in register CIU_CommIEn is set to logic 1, it will set to logic level 1
CIU_IRQ_0 in the register CIU_Status1, when HiAlert in the same register changes to
logic level 1.
The flag HiAlert is set to logic 1 if only WaterLevel[5:0] bits (as set in register
CIU_WaterLevel) or less can be stored in the FIFO-buffer. It is generated by the following
equation:
HiAlert = 64 – FIFOLenght WaterLevel
The flag LoAlert is set to logic 1 if WaterLevel[5:0] bits (as set in register CIU_WaterLevel)
or less are actually stored in the FIFO-buffer. It is generated by the following equation:
LoAlert = FIFOLenght WaterLevel
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8.6.17 CIU_timer
A timer unit is implemented in the CIU: CIU_timer. The 80C51 use CIU_timer to manage
timing relevant tasks for contactless communication. CIU_timer may be used in one of the
following configurations:
•
•
•
•
•
Timeout-Counter
Watch-Dog Counter
Stop Watch
Programmable One-Shot
Periodical Trigger
CIU_timer can be used to measure the time interval between two events or to indicate that
a specific event occurred after a specific time. CIU_timer can be triggered by events which
will be explained in the following, but it does not itself influence any internal event (e.g. A
timeout during data reception does not influence the reception process automatically).
Furthermore, several timer related bits are set and these bits can be used to generate an
interrupt.
CIU_timer has a input clock of 6.78 MHz (derived from the 27.12 MHz quartz). CIU_timer
consists of 2 stages: 1 prescaler and 1 counter.
The prescaler is a 12 bits counter. The reload value for the prescaler can be defined
between 0 and 4095 in register CIU_TMode and CIU_TPrescaler. This decimal value is
called TPrescaler.
The reload value TReloadVal for the counter is defined with 16 bits in a range from 0 to
65535 in the registers CIU_TReloadVal_Lo and CIU_TReloadVal_Hi.
The current value of CIU_timer is indicated by the registers CIU_TCounterVal_lo and
CIU_TCounterVal_hi.
If the counter reaches 0 an interrupt will be generated automatically indicated by setting
the TimerIRq flag in the register CommonIRq. If enabled, it will set to logic level 1
CIU_IRQ_1 in the register CIU_Status1. TimerIRq flag can be set to logic level 1 or to
logic level 0 by the 80C51. Depending on the configuration, CIU_timer will stop at 0 or
restart with the value of the registers CIU_TReloadVal_Lo and CIU_TReloadVal_Hi.
Status of CIU_timer is indicated by the bit TRunning in the register CIU_Status1.
CIU_timer can be manually started by TStartNow in register Control or manually stopped
by TStopNow in register Control.
Furthermore CIU_timer can be activated automatically by setting the bit TAuto in the
register CIU_TMode to fulfill dedicated protocol requirements automatically.
The time delay of a timer stage is the reload value +1.
Maximum time:
TPrescaler = 4095, TReloadVal = 65535 => 4096*65536/6.78 MHz = 39.59 s
Example:
To indicate 100 ms it is required to count 678 clock cycles. This means the value for
TPrescaler has to be set to TPrescaler = 677.The timer has now an input clock of
100 us. The timer can count up to 65535 timeslots of 100 ms.
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8.6.18 Interrupt request system
The CIU indicates certain events by setting interrupt bits in the register CIU_Status1 and,
in addition it will set to logic level 1 CIU_interrupt1 or CIU_IRQ_0. If this interrupt is
enabled (see Table 12 on page 17) the 80C51 will be interrupted. This allows the
implementation of efficient interrupt-driven firmware.
8.6.18.1
Interrupt sources
The following table shows the integrated interrupt flags, the corresponding source and the
condition for its activation.
The interrupt flag TimerIRq in the register CIU_CommIrq indicates an interrupt set by the
timer unit. The setting is done when the timer decrements from logic level 1 down to logic
level 0.
The TxIRq bit in the register CIU_CommIrq indicates that the transmitter has finished. If
the state changes from sending data to transmitting the end of frame pattern, the
transmitter unit sets automatically the interrupt bit to logic level 1.
The CRC coprocessor sets the flag CRCIRq in the register CIU_DivIrq after having
processed all data from the FIFO buffer. This is indicated by the flag CRCReady set to
logic level 1.
The RxIRq flag in the register CIU_CommIrq indicates an interrupt when the end of the
received data is detected.
The flag IdleIRq in the register CIU_CommIrq is set to level 1 if a command finishes and
the content of the CIU_Command register changes to idle.
The flag HiAlertIRq in the register CIU_CommIrq is set to level 1 if the HiAlert bit is set to
logic 1, that means the Contactless FIFO buffer has reached the level indicated by the
bits WaterLevel[5:0].
The flag LoAlertIRq in the register CIU_CommIrq is set to logic level 1 if the LoAlert bit is
set to logic level 1, that means the Contactless FIFO buffer has reached the level
indicated by the bits WaterLevel[5:0].
The flag RFOnIRq in the register CIU_DivIrq is set to logic level 1, when the RF level
detector detects an external RF field.
The flag RFOffIRq in the register CIU_DivIrq is set to logic level 1, when a present
external RF field is switched off.
The flag ErrIRq in the register CIU_CommIrq indicates an error detected by the CIU
during sending or receiving. This is indicated by any bit set to logic 1 in register CIU_Error.
The flag ModeIRq in the register CIU_DivIrq indicates that the data mode detector has
detected the current mode.
These flags are summarized with 2 interrupt bits within the register CIU_Status1:
• the high priority interrupt sources are summarized with CIU_IRQ_0.
• the low priority interrupt sources are summarized with CIU_IRQ_1.
See the register Table 191 on page 161.
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Table 166. High priority interrupt sources (CIU_IRQ_0)
Interrupt Flag
Interrupt source
Set automatically, WHEN
TxIRq
Transmitter
a transmitted data stream ends
RxIRq
Receiver
a received data stream ends
HiAlertIRq
FIFO-buffer
the FIFO-buffer is getting full
LoAlertIRq
FIFO-buffer
the FIFO-buffer is getting empty
Table 167. Low priority interrupt sources (CIU_IRQ_1)
Interrupt Flag
Interrupt source
Set automatically, WHEN
TimerIRq
Timer Unit
the timer counts from 1 to 0
CRCIRq
CRC-Coprocessor
all data from the FIFO buffer have been processed
IdleIRq
CIU_Command
Register
a command execution finishes
RFOnIRq
RF Level Detector
an external RF field is detected
RFOffIRq
RF Level Detector
a present external RF field is switched off
ErrIRq
CIU
an error is detected
ModeIRq
data mode detector
the mode has been detected
8.6.19 CIU Power Reduction Modes
8.6.19.1
Hard-Power-down
A Hard-Power-down is enabled when RSTPD_N is low. None of the CIU blocks are
running, even the RF level detector.
8.6.19.2
CIU Power-down
The CIU Power-down mode is entered immediately by setting the Power-down bit in the
register CIU_Command. All CIU blocks are switched off, except the 27.12 MHz oscillator
and the RF level detector.
All registers and the FIFO will keep the content during CIU Power-down.
If the bit AutoWakeUp in the register CIU_TxAuto is set and an external RF field is
detected, the CIU Power-down mode is left automatically.
After setting bit Power-down to logic level 0 in the register CIU_Command, it needs
1024 clocks cycle until the CIU Power-down mode is left indicated by the Power-down bit
itself. Setting it to logic 0 does not immediately set it to logic level 0. It is automatically set
to logic level 0 by the CIU when the CIU Power-down mode is left.
When in CIU Power-down mode and DriverSel[1:0] is no set to 00b (see Table 218 on
page 172), to ensure a minimum impedance at the transmitter outputs, the CWGsNOn[3],
CWGsNOff[3], ModGsNOn[3], ModGsNOff[3], CWGsP[5], ModGsP[5] bits are set to logic
level 1, but it is not readable in the registers.
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8.6.19.3
Transmitter Power-down
The Transmitter Power-down mode switches off the internal antenna drivers to turn off the
RF field by setting the bits Tx1RFEn and Tx2RFEn in the register CIU_TxControl to logic
level 0. The receiver is still switched on, meaning the CIU can be accessed by a second
NFC device as a NFCIP-1 target.
Note: In case the bit InitialRFOn has been set to logic 1, when the drivers were already
switched on, it is needed either to set InitialRFOn to logic level 0, before setting the bits
Tx1RFEn and Tx2RFEn in the register CIU_TxControl to logic 0, or to set also the bits
Tx1RFAutoEn and Tx2RFAutoEn in the register CIU_TxAuto to logic level 0.
8.6.20 CIU command set
8.6.20.1
General description
The CIU behaviour is determined by an internal state machine capable to perform a
certain set of commands. Writing the according command code to the CIU_Command
register starts the commands.
Arguments and/or data necessary to process a command are mainly exchanged via the
FIFO buffer.
8.6.20.2
General behaviour
• Each command, that needs a data stream (or data byte stream) as input will
immediately process the data it finds in the FIFO buffer. An exception to this rule is the
Transceive command. Using this command the transmission is started with the
StartSend bit in CIU_BitFraming register.
• Each command that needs a certain number of arguments will start processing only
when it has received the correct number of arguments via the FIFO buffer.
• The FIFO buffer is not cleared automatically at command start. Therefore, it is also
possible to write the command arguments and/or the data bytes into the FIFO buffer
and start the command afterwards.
• Each command may be interrupted by the 80C51 by writing a new command code
into the CIU_Command register e.g.: the Idle command.
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8.6.20.3
Commands overview
Table 168. Command overview
Command
Command code
Action
Idle
0000
No action; cancels current command execution.
Config
0001
Configures the CIU for FeliCa, MIFARE and NFCIP-1
communication.
Generate RandomID 0010
Generates 10-byte random ID number
CalcCRC
0011
Activates the CRC co-processor or perform self-test.
Transmit
0100
Transmits data from the FIFO buffer.
NoCmdChange
0111
No command change. This command can be used to
modify different bits in the CIU_Command register
without touching the command. e.g. Power-down bit.
Receive
1000
Activates the receiver circuitry.
SelfTest
1001
Activates the self-test. Not described in this chapter.
Transceive
1100
If bit Initiator in the register CIU_Control is set to logic 1:
Transmits data from FIFO buffer to the antenna and
activates automatically the receiver after transmission is
finished.
If bit Initiator in the register CIU_Control is set to logic 0:
Receives data from antenna and activates
automatically the transmitter after reception.
8.6.20.4
AutoColl
1101
Handles FeliCa polling (Card operating mode only) and
MIFARE anticollision (Card operating mode only)
MFAuthent
1110
Performs the MIFARE 1 KB or MIFARE 4 KB emulation
authentication in MIFARE Reader/Writer mode only.
Soft Reset
1111
Resets the CIU.
Idle command
The CIU is in idle mode. This command is also used to terminate the actual command.
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8.6.20.5
Config command
To configure the automatic MIFARE Anticollision, FeliCa Polling and NFCID3, the data
used for these transactions have to be stored internally. All the following data have to be
written to the FIFO in this order:
• SENS_RES (2 bytes): in order byte0, byte1
• NFCID1 (3 bytes): in order byte0, byte1, byte 2; the first NFCID1 byte if fixed to 08h
and the check byte is calculated automatically
• SEL_RES (1 byte)
• Polling response (2 bytes (shall be 01h, FEh)+ 6 bytes NFCID2 + 8 bytes Pad +
2 bytes system code)
• NFCID3 (1 byte)
In total 25 bytes which are transferred into an internal buffer with the Config command.
The complete NFCID3 is 10 bytes long and consist of the 3 NFCID1 bytes, the 6 NFCID2
bytes and the NFCID3 byte listed above.
To read out this configuration (after it has been loaded), the command Config with an
empty FIFO buffer has to be started. In this case the 25 bytes are transferred from the
internal buffer to the FIFO.
The CIU has to be configured after each power up, before using the automatic
Anticollision/Polling function (AutoColl command). During a Hard-Power-down (RSTPD_N
set to logic level 0) this configuration remains unchanged.
This command terminates automatically when finished and the active command is Idle.
8.6.20.6
Generate RandomID command
This command generates a 10-byte random number stored in the internal 25 bytes buffer
and overwrites the 10 NFCID3 bytes. This random number might be used for fast
generation of all necessary ID bytes for the automatic Anticollision / Polling function.
Note: To configure the CIU, Config command has to be used first.
This command terminates automatically when finished and the active command is Idle.
8.6.20.7
CalcCRC command
The content of the FIFO is transferred to the CRC co-processor and a CRC calculation is
started. The result is stored in the CRCResult register. The CRC calculation is not limited
to a dedicated number of bytes. The calculation is not stopped when the FIFO gets empty
during the data stream. The next byte written to the FIFO is added to the calculation.
The preset value of the CRC is defined by the CRCPreset bits of the register CIU_Mode,
and the chosen value is loaded to the CRC co-processor when the command is started.
This command has to be terminated by firmware by writing any command to the
CIU_Command register e.g. the Idle command.
If SelfTest in register CIU_AutoTest is set to logic 1, the CRC co-processor is in Self Test
mode and performs a digital self-test. The result of the self-test is written in the FIFO.
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8.6.20.8
Transmit command
The content of the FIFO is transmitted immediately after starting the command. Before
transmitting FIFO content, all relevant register settings have to be set to transmit data in
the selected mode.
This command terminates automatically when the FIFO gets empty and the active
command is Idle. It can be terminated by any other command written to the
CIU_Command register.
8.6.20.9
NoCmdChange command
This command does not influence any ongoing command in the CIU_Command register.
It can be used to manipulate any bit except the command bits in the CIU_Command
register, e.g. the bits RcvOff or Power-down.
8.6.20.10
Receive command
The CIU activates the receiver path and waits for any data stream to be received. The
correct settings for the expected mode have to be set before starting this command.
This command terminates automatically when the receive data stream ends and the
active command is Idle. This is indicated either by the end of frame pattern or by the
length byte depending on the selected framing and speed.
Note: If the bit RxMultiple in the register CIU_RxMode is set to logic 1, the Receive
command does not terminate automatically. It has to be terminated by setting any other
command in the CIU_Command register.
8.6.20.11
Transceive command
This circular command repeats transmitting data from the FIFO and receiving data from
the RF field continuously. If the bit Initiator in the register CIU_Control is set to logic 1, it
indicates that the first action is transmitting and after having finished transmission the
receiver is activated to receive data. If the bit Initiator in the CIU_Control register is set to
logic 0, the first action is receiving and after having received a data stream, the transmitter
is activated to transmit data. In the second configuration the PN533 first acts as a receiver
and if a data stream is received it switches to the Transmit mode.
Table 169. Transceive command scenario
Communication step
1
2
3
4
Initiator =1
Send
Receive
Send
Receive
Initiator=0
Receive
Send
Receive
Send
Each transmission process has to be started with setting bit StartSend in the register
CIU_BitFraming. This command has to be cleared by firmware by writing any command to
the CIU_Command register e.g. the command idle.
Note: If the bit RxMultiple in register CIU_RxMode is set, this command will never leave
the receiving state, because the receiving will not be cancelled automatically.
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8.6.20.12
AutoColl command
This command automatically handles the MIFARE activation and the FeliCa polling in the
Card Operation mode. The bit Initiator in the CIU_Control register has to be set to logic
level 0 for correct operation. During this command, Mode Detector is active if not
deactivated by setting the bit ModeDetOff in the CIU_Mode register. After Mode Detector
detects a mode, the mode dependent registers are set according to the received data. In
case of no external RF field this command resets the internal state machine and returns to
the initial state but it will not be terminated.
When the Autocoll command terminates the Transceive command gets active.
During Autocoll command:
• The CIU interrupt bits, except RfOnIRq, RfOffIRq and SIGINActIRq (see Table 188 on
page 159), are not supported. Only the last received frame will serve the CIU
interrupts.
• During ISO/IEC 14443A activation, TxCRCEn and RxCRCEn bits are defined by the
AutoColl command. The changes cannot be observed at the CIU_TxMode and
CIU_RxMode registers. When the Transceive command is active, the value of the bits
is relevant.
• During Felica activation (polling), TxCRCEn and RxCRCEn bits are always relevant
and are not overruled by the Autocoll command. Their value must be set to logic level
1 according the FeliCa protocol.
Note: Pay attention, that the FIFO will also receive the two CRC check bytes of the last
command, even if they are already checked and correct, and if the state machine
(Anticollision and Select routine) has not been executed, and 106 kbit is detected.
This command can be cleared by firmware by writing any other command to the
CIU_Command register, e.g. the Idle command. Writing the same content again to the
CIU_Command register resets the state machine.
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Fig 58. AutoColl command
• NFCIP-1 106 kbps passive communication mode:
The MIFARE anticollision is finished and the command changes automatically to
Transceive. The FIFO contains the ATR_REQ frame including the start byte F0h. The
bit TargetActivated in the register CIU_Status2 is set to logic 1
• NFCIP-1 212 and 424 kbps passive communication mode:
The FeliCa polling command is finished and the command has automatically changed
to Transceive. The FIFO contains the ATR_REQ frame. The bit TargetActivated in the
register CIU_Status2 is set to logic 1.
• NFCIP-1 106, 212 and 424 kbps active communication mode:
This command is changing automatically to Transceive. The FIFO contains the
ATR_REQ frame. The bit TargetActivated in the register CIU_Status2 is set to logic 0.
For 106 kbps only, the first byte in the FIFO indicates the start byte F0h and the CRC
is added into the FIFO.
• ISO/IEC 14443A/MIFARE (Card Operating mode):
The MIFARE anticollision is finished and the command has automatically changed to
Transceive. The FIFO contains the first command after the Select. The bit
TargetActivated in the register CIU_Status2 is set to logic 1.
• FeliCa (Card Operating mode):
The FeliCa polling command is finished and the command has automatically changed
to Transceive. The FIFO contains the command after the Polling in the FeliCa
protocol. The bit TargetActivated in the register CIU_Status2 is set to logic 1.
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8.6.20.13
MFAuthent command
This command handles the MIFARE authentication in Reader/Writer mode to enable a
secure communication to any MIFARE 1 KB and MIFARE 4 KB emulation card. The
following data shall be written to the FIFO before the command can be activated:
•
•
•
•
•
•
•
•
•
•
•
•
Authentication command code (60h for key A, 61h for key B)
Block address
Sector key byte 0
Sector key byte 1
Sector key byte 2
Sector key byte 3
Sector key byte 4
Sector key byte 5
Card serial number byte 0
Card serial number byte 1
Card serial number byte 2
Card serial number byte 3
In total 12 bytes shall be written to the FIFO.
Note: When the MFAuthent command is active, any FIFO access is blocked. Anyhow if
there is an access to the FIFO, the bit WrErr in the register CIU_Error is set to logic
level 1.
This command terminates automatically when the MIFARE 1KB or MIFARE 4 KB
emulation card is authenticated. The bit MFCrypto1On in the register CIU_Status2 is set
to logic level 1.
This command does not terminate automatically when the card does not answer,
therefore CIU timer should be initialized to automatic mode. In this case, beside the bit
IdleIRq, the bit TimerIRq can be used as termination criteria. During authentication
processing, the bits RxIRq and TxIRq of CIU_CommIrq register are blocked.
The Crypto1On bit is only valid after termination of the MFAuthent command (either after
processing the authentication or after writing the Idle command in the register
CIU_Command).
In case there is an error during the MIFARE authentication, the ProtocolErr bit in the
CIU_Error register is set to logic 1 and the Crypto1On bit in CIU_Status2 register is set to
logic 0.
8.6.20.14
SoftReset command
This command performs a reset of the CIU. The configuration data of the internal buffer
remains unchanged. All registers are set to the reset values.
When SoftReset is finished, the active command switches to Idle.
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8.6.21 CIU tests signals
8.6.21.1
CIU self-test
The CIU has the capability to perform a self-test. To start the self-test the following
procedure has to be performed:
1. Perform a SoftReset.
2. Clear the internal buffer by writing 25 bytes of 00h and perform the Config command.
3. Enable the self-test by writing the value 09h to the register CIU_AutoTest.
4. Write 00h to the FIFO.
5. Start the self-test with the CalcCRC command.
6. The self-test will be performed.
7. When the self-test is finished, the FIFO is contains the following bytes:
– Correct answer for VersionReg equal to 80h:
0x00, 0xaa, 0xe3, 0x29, 0x0c, 0x10, 0x29, 0x6b
0x76, 0x8d, 0xaf, 0x4b, 0xa2, 0xda, 0x76, 0x99
0xc7, 0x5e, 0x24, 0x69, 0xd2, 0xba, 0xfa, 0xbc
0x3e, 0xda, 0x96, 0xb5, 0xf5, 0x94, 0xb0, 0x3a
0x4e, 0xc3, 0x9d, 0x94, 0x76, 0x4c, 0xea, 0x5e
0x38, 0x10, 0x8f, 0x2d, 0x21, 0x4b, 0x52, 0xbf
0xfb, 0xf4, 0x19, 0x94, 0x82, 0x5a, 0x72, 0x9d
0xba, 0x0d, 0x1f, 0x17, 0x56, 0x22, 0xb9, 0x08
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8.6.21.2
CIU test bus
The test bus is implemented for production test purposes. The following configuration can
be used to improve the design of a system using the PN533. The test bus allows to route
internal signals to output pins.
The Observe_testbus register is used to enable this functionality.
Table 170. Observe_testbus register (address 6104h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
-
-
-
-
observe_ciu
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R/W
Table 171. Description of Observe_testbus bits
Bit
Symbol
Description
7 to 1
-
Reserved.
0
observe_ciu
Configure the pads P3x (P30 to P35), RSTOUT_N and P70_IRQ to
observe internal CIU data bus.
When set to logic 1, the pads are configured in output mode and show
the internal data bus D0 to D6 of the CIU. P70_IRQ is the 13.56 MHz
digital clock of CIU (generated from field or crystal).
The test bus signals are selected by accessing TestBusSel in register CIU_TestSel2.
Table 172. TstBusBitSel set to 07h
Test bus bit
Test signal
Comments
D6
sdata
shows the actual received data value.
D5
scoll
shows if in the actual bit a collision has been detected
(106 kbit/s only)
D4
svalid
shows if sdata and scoll are valid
D3
sover
shows that the receiver has detected a stop bit
(ISO/IEC 14443A/MIFARE mode only)
D2
RCV_reset
shows if the receiver is reset
D1
RFon filtered
shows the value of the internal RF level detector
D0
Envelope
shows the output of the internal coder
Table 173. TstBusBitSel set to 0Dh
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Test bus bit
Test signal
Comments
D6
clkstable
shows if the oscillator delivers a stable signal
D5
clk27/8
shows the output signal of the oscillator divided by 8
D4
clk27rf/8
shows the clk27rf signal divided by 8
D3
clk13/4
shows the clk13rf divided by 4
D2
clk27
shows the output signal of the oscillator
D1
clk27rf
shows the RF clock multiplied by 2
D0
clk13rf
shows the RF clock of 13.56 MHz
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8.6.21.3
Test signals at pin AUX
Each signal can be switched to pin AUX1 or AUX2 by setting SelAux1 or SelAux2 in the
register CIU_AnalogTest. See Table 280 on page 195
8.6.21.4
PRBS
Enables the Pseudo Random Bit Stream of 9-bit or 15-bit length sequence, PRBS9 or
PRBS15, according to ITU-TO150. To start the transmission of the defined datastream,
Transmit command has to be activated. The preamble/Sync byte/start bit/parity bit are
generated automatically depending on the selected mode.
Note: All relevant registers to transmit data have to be configured before entering PRBS
mode according ITU-TO150.
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8.6.22 CIU memory map
The registers of the CIU are either map into the SFR or into the XRAM memory space.
Table 174. Contactless Interface Unit SFR memory map
ADDR Byte Register name
size
Description
D1h
1
CIU_Command
Starts and stops the command execution
D2h
1
CIU_CommlEn
Control bits to enable and disable the passing of interrupt
requests
D3h
1
CIU_DivlEn
Control bits to enable and disable the passing of interrupt
requests
D4h
1
CIU_CommIrq
Contains common Interrupt Request flags
D5h
1
CIU_DivIrq
Contains diverse Interrupt Request flags
D6h
1
CIU_Error
Error flags showing the error status of the last command
executed
DFh
1
CIU_Status1
Contains status flags of the CRC, Interrupt Request System and
FIFO buffer
E9h
1
CIU_Status2
Contain status flags of the Receiver, Transmitter and Data Mode
Detector
EAh
1
CIU_FIFOData
in- and output of 64 bytes FIFO buffer
EBh
1
CIU_FIFOLevel
Indicates the number of bytes stored in the FIFO
ECh
1
CIU_WaterLevel Defines the thresholds for FIFO under- and overflow warning
EDh
1
CIU_Control
EEh
1
CIU_BitFraming Adjustments for bit oriented frames
EFh
1
CIU_Coll
Contains miscellaneous Control bits
Bit position of the first bit collision detected on the RF-interface
Table 175. Contactless Interface Unit extension memory map
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ADDR Byte Register name
size
Description
6301h 1
CIU_Mode
Defines general modes for transmitting and receiving
6302h 1
CIU_TxMode
Defines the transmission data rate and framing during
transmission
6303h 1
CIU_RxMode
Defines the transmission data rate and framing during
receiving
6304h 1
CIU_TxControl
Controls the logical behaviour of the antenna driver pins
TX1 and TX2
6305h 1
CIU_TxAuto
Controls the settings of the antenna driver
6306h 1
CIU_TxSel
Selects the internal sources for the antenna driver
1
CIU_RxSel
Selects internal receiver settings
6308h 1
CIU_RxThreshold
Selects thresholds for the bit decoder
6309h 1
CIU_Demod
Defines demodulator settings
630Ah 1
CIU_FelNFC1
Defines the length of the valid range for the received frame
630Bh 1
CIU_FelNFC2
Defines the length of the valid range for the received frame
630Ch 1
CIU_MifNFC
Controls the communication in ISO/IEC 14443/MIFARE and
NFC target mode at 106 kbit/s
630Dh 1
CIU_ManualRCV
Allows manual fine tuning of the internal receiver
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Table 175. Contactless Interface Unit extension memory map …continued
ADDR Byte Register name
size
Description
630Eh 1
CIU_TypeB
Configure the ISO/IEC 14443 type B
630Fh 1
-
Reserved
6310h 1
-
Reserved
6311h 1
CIU_CRCResultMSB Shows the actual MSB values of the CRC calculation
6312h 1
CIU_CRCResultLSB Shows the actual LSB values of the CRC calculation
6313h 1
CIU_GsNOFF
Selects the conductance of the antenna driver pins TX1 and
TX2 for load modulation when own RF field is switched OFF
6314h 1
CIU_ModWidth
Controls the setting of the width of the Miller pause
6315h 1
CIU_TxBitPhase
Bit synchronization at 106 kbit/s
6316h 1
CIU_RFCfg
Configures the receiver gain and RF level
6317h 1
CIU_GsNOn
Selects the conductance of the antenna driver pins TX1 and
TX2 for modulation, when own RF field is switched ON
6318h 1
CIU_CWGsP
Selects the conductance of the antenna driver pins TX1 and
TX2 when not in modulation phase
6319h 1
CIU_ModGsP
Selects the conductance of the antenna driver pins TX1 and
TX2 when in modulation phase
631Ah 1
CIU_TMode
CIU_TPrescaler
Defines settings for the internal timer
631Bh 1
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631Ch 1
CIU_TReloadVal_hi
Describes the 16-bit long timer reload value (Higher 8 bits)
631Dh 1
CIU_TReloadVal_lo
Describes the 16-bit long timer reload value (Lower 8 bits)
631Eh 1
CIU_TCounterVal_hi Describes the 16-bit long timer actual value (Higher 8 bits)
631Fh 1
CIU_TCounterVal_lo Describes the 16-bit long timer actual value (Lower 8 bits)
6320h 1
-
Reserved
6321h 1
CIU_TestSel1
General test signals configuration
6322h 1
CIU_TestSel2
General test signals configuration and PRBS control
6323h 1
CIU_TestPinEn
Enables test signals output on pins.
6324h 1
CIU_TestPinValue
Defines the values for the 8-bit parallel bus when it is used
as I/O bus
6325h 1
CIU_TestBus
Shows the status of the internal test bus
6326h 1
CIU_AutoTest
Controls the digital self-test
6327h 1
CIU_Version
Shows the CIU version
6328h 1
CIU_AnalogTest
Controls the pins AUX1 and AUX2
6329h 1
CIU_TestDAC1
Defines the test value for the TestDAC1
632Ah 1
CIU_TestDAC2
Defines the test value for the TestDAC2
632Bh 1
CIU_TestADC
Show the actual value of ADC I and Q
632Ch 1
-
Reserved for tests
632Dh 1
-
Reserved for tests
632Eh 1
-
Reserved for tests
632Fh 1
CIU_RFlevelDet
Power down of the RF level detector
6330h 1
CIU_SIC_CLK_en
Enables the use of secure IC clock on P34 / SIC_CLK.
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8.6.23 CIU register description
8.6.23.1
CIU register bit behaviour
Depending of the functionality of a register, the access condition to the bits can vary. The
following table describes the access conditions:
Table 176. Behavior of register bits
Abbreviation Behavior
R/W
Read and
Write
Description
These bits can be written and read by the 80C51. Since they are used
only for control means, there content is not influenced by internal
state machines, e.g. CIU_CommIEn may be written and read by the
CPU. It will also be read by internal state machines, but never
changed by them.
DY
DYnamic
R
Read only
W
Write only
These bits can be written and read by the 80C51. Nevertheless, they
may also be written automatically by CIU internal state machines, e.g.
the commands in the CIU_Command register change their values
automatically after their execution.
These registers hold flags, which value is determined by CIU internal
states only, e.g. the CRCReady register can not be written from
external but shows CIU internal states.
These registers are used for control means only. They may be written
by the 80C51 but can not be read. Reading these registers returns
always logic level 0.
These registers are not implemented or reserved for NXP testing use.
Reserved
8.6.23.2
CIU_SIC_CLK_en register (6330h)
Enables the use of P34 / SIC_CLK as secure IC clock.
Table 177. CIU_SIC_CLK_en register (address 6330h) bit allocation
Bit
Symbol
Reset
Access
7
sic_clk_p34_en
0
R/W
6
0
R
5
0
R
4
0
R
3
Errorbusbitenable
0
R/W
2
1
0
Errorbusbitsel[2:0]
0
0
0
R/W
R/W
R/W
Table 178. Description of CIU_SIC_CLK_en bits
Bit
7
Symbol
sic_clk_p34_en
Description
Set to logic 1, this bit configures P34 / SIC_CLK to be used as secure
IC clock: SIC_CLK.
Set to logic 0, P34 / SIC_CLK is in normal mode: P34.
6 to 4 Reserved
3
Errorbusbitenable Set to logic 1, enable the error source selected by Errorbusbitsel on
AUX pads according to SelAux1 and SelAux2 bits (code 1010b).
2 to 0 Errorbusbitsel[2:0] Define the error source on ErrorBusBit:
Value
000
001
010
011
100
101
110
111
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Description
selects ProtocollErr on test bus
selects ParityErr on test bus
selects CRCErr on test bus
selects CollErr on test bus
selects BufferOvfl on test bus
selects RFErr on test bus
selects TempErr on test bus
selects WrErr on test bus
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8.6.23.3
CIU_Command register (D1h or 6331h)
Starts and stops the command execution.
Table 179. CIU_Command register (address D1h or 6331h) bit allocation
Bit
7
6
5
4
Symbol
-
-
RcvOff
Power-down
3
2
1
0
Command
Reset
0
0
1
0
0
0
0
0
Access
R
R
R/W
DY
DY
DY
DY
DY
Table 180. Description of CIU_Command bits
Bit
Symbol
Description
7 to 6
-
Reserved
5
RcvOff
Set to logic 1, the analog part of the receiver is switched off.
4
Power-down Set to logic 1, the CIU Power-down mode is entered. This means, internal
current consuming blocks of the contactless analog module are switched
off, except for the RF level detector.
Set to logic 0, the PN533 starts the wake up procedure. During this
procedure this bit still shows a logic level 1. A logic level 0 indicates that
the PN533 is ready for operations; see Section 8.6.19.2 “CIU Power-down”
on page 142.
Note: The Power-down bit can not be set, when the SoftReset command
has been activated.
3 to 0
Command
Activates a command according the Command Code.
Reading this register shows, which command is actually executed. See
Section 8.6.20 “CIU command set” on page 143.
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8.6.23.4
CIU_CommIEn register (D2h or 6332h)
Control bits to enable and disable the passing of interrupt requests.
Table 181. CIU_CommIEn register (address D2h or 6332h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
TxIEn
RXIEn
SiginAct IEn
ModeIEn
CRCIEn
RfOnIEn
RfOffIEn
Reset
0
0
0
0
0
0
0
0
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 182. Description of CIU_CommIEn bits
Bit
8.6.23.5
Symbol
Description
7
-
Reserved.
6
TxIEn
When set to logic level 1, allows the transmitter interrupt request (indicated
by bit TxIRq) to be propagated to CIU_IRQ_1.
5
RxIEn
When set to logic level 1, allows the receiver interrupt request (indicated
by bit RxIRq) to be propagated to CIU_IRQ_1.
4
IdleIEn
When set to logic level 1, allows the idle interrupt request (indicated by bit
IdleIRq) to be propagated to CIU_IRQ_0.
3
HiAlertIEn
When set to logic level 1, allows the high alert interrupt request (indicated
by bit HiAlertIRq) to be propagated to CIU_IRQ_1.
2
LoAlertIEn
When set to logic level 1, allows the low alert interrupt request (indicated
by bit LoAlertIRq) to be propagated to CIU_IRQ_1.
1
ErrIEn
When set to logic level 1, allows the error interrupt request (indicated by bit
ErrIRq) to be propagated to CIU_IRQ_0.
0
TimerIEn
When set to logic level 1, allows the timer interrupt request (indicated by
bit TimerIRq) to be propagated to CIU_IRQ_0.
CIU_DivIEn register (D3h or 6333h)
Controls bits to enable and disable the passing of interrupt requests.
Table 183. CIU_DivIEn register (address D3h or 6333h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
SiginAct IEn
ModeIEn
CRCIEn
RfOnIEn
RfOffIEn
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R/W
R/W
R/W
R/W
R/W
Table 184. Description of CIU_DivIEn bits
Bit
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Symbol
Description
7 to 5 -
Reserved.
4
SiginAct IEn
Allows the SIGIN active interrupt request to be propagated to CIU_IRQ_0.
3
ModeIEn
When set to logic level 1, allows the mode interrupt request (indicated by
bit ModeIRq) to be propagated to CIU_IRQ_0.
2
CRCIEn
When set to logic level 1, allows the CRC interrupt request (indicated by
bit CRCIRq) to be propagated to CIU_IRQ_0.
1
RfOnIEn
When set to logic level 1, allows the RF field on interrupt request
(indicated by bit RfOnIRq) to be propagated to CIU_IRQ_0.
0
RfOffIEn
When set to logic level 1, allows the RF field off interrupt request
(indicated by bit RfOffIRq) to be propagated to CIU_IRQ_0.
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8.6.23.6
CIU_CommIrq register (D4h or 6334h)
Contains common CIU interrupt request flags.
Table 185. CIU_CommIrq register (address D4h or 6334h) bit allocation
Bit
Symbol
7
6
5
4
Set1
TxIRq
RxIRq
IdleIrq
3
2
HiAltertIRq LoAlertIRq
1
0
ErrIRq
TimerIRq
Reset
0
0
0
1
0
1
0
0
Access
W
DY
DY
DY
DY
DY
DY
DY
Table 186. Description of CIU_CommIRQ bits
Bit Symbol
Description
7
When set to logic 0 during write operation, the bit set to logic level 1 in the write
command are written to logic level 0 in the register.
Set1
When set to logic 1 during write operation, the bit set to logic level 1 in the write
command are written to logic level 1 in the register.
6
TxIRq
Set to logic 1, immediately after the last bit of the transmitted data was sent out.
5
RxIRq
Set to logic 1 when the receiver detects the end of a valid datastream.
If the RxNoErr bit in CIU_RxMode register is set to logic 1, RxIRQ is only set to
logic 1 when data bytes are available in the FIFO.
4
IdleIrq
Set to logic 1, when a command terminates by itself e.g. when the
CIU_Command register changes its value from any command to the Idle
command.
If an unknown command is started, the CIU_Command register changes its value
to the Idle command and the IdleIRq bit is set.
Starting the Idle Command by the 80C51 does not set IdleIRq bit.
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3
HiAltertIRq Set to logic 1, when HiAlert bit in CIU_Status1 register is set to logic level 1. In
opposition to HiAlert, HiAlertIRq stores this event and can only be reset by
Set1 bit.
2
LoAlertIRq Set to logic 1, when LoAlert bit in CIU_Status1 register is set. In opposition to
LoAlert, LoAlertIRq stores this event and can only be reset by Set1 bit.
1
ErrIRq
Set to logic 1, if any error flag in the CIU_Error register is set.
0
TimerIRq
Set to logic 1, when the timer decrements the TimerValue register to zero.
[1]
Remark: All bits in the register CIU_CommIrq shall be set to logic level 0 by firmware.
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8.6.23.7
CIU_DivIrq register (D5h or 6335h)
Contains miscellaneous interrupt request flags.
Table 187. CIU_DivIrq register (address D5h or 6335h) bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
Set2
-
-
SiginActIrq
ModeIRq
CRCIRq
RfOnIRq
RfOffIRq
Reset
0
0
0
X
0
0
X
X
Access
W
R
R
DY
DY
DY
DY
DY
Table 188. Description of CIU_DivIrq bits
Bit
Symbol
Description
7
Set2
When set to logic 0 during write operation, the bit set to logic level 1 in the
write command are written to logic level 0 in the register.
When set to logic 1 during write operation, the bit set to logic level 1 in the
write command are written to logic level 1 in the register.
6 to 5
-
Reserved.
4
SiginActIrq Set to logic level 1, when SIGIN is active. See Section 8.6.13 “NFC-WI/S2C
interface support” on page 133. This interrupt is set when either a rising or
falling edge is detected on SIGIN.
3
ModeIRq
Set to logic 1, when the mode has been detected by the Data Mode Detector.
Note: The Data Mode Detector can only be activated by the AutoColl
command and is terminated automatically having the detected the
communication mode.
Note: The Data Mode Detector is automatically restarted after each RF
reset.
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2
CRCIRq
Set to logic 1, when the CRC command is active and all data are processed.
1
RfOnIRq
Set to logic 1, when an external RF field is detected.
0
RfOffIRq
Set to logic 1, when an present external RF field is switched off.
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8.6.23.8
CIU_Error register (D6h or 6336h)
Error flags showing the error status of the last command executed.
Table 189. CIU_Error register (address D6h or 6336h) bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
WrErr
TempErr
RFErr
BufferOvfl
CollErr
CRCErr
ParityErr
ProtocollErr
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Table 190. Description of CIU_Error bits
Bit Symbol
Description
7
WrErr
Set to logic 1, when data is written into the FIFO by the 80C51 during the
AutoColl command or MFAuthent command or if data is written into the FIFO by
the 80C51 during the time between sending the last bit on the RF interface and
receiving the last bit on the RF interface.
6
TempErr[1]
Set to logic 1, if the internal temperature sensor detects overheating. In this
case the antenna drivers are switched off automatically.
5
RFErr
Set to logic 1, if in active communication mode the counterpart does not switch
on the RF field in time as defined in NFCIP-1 standard.
Note: RFErr is only used in active communication mode. The bit RxFraming or
the bit TxFraming has to be set to 01h to enable this functionality.
4
BufferOvfl
Set to logic 1, if the 80C51 or if the internal state machine (e.g. receiver) tries to
write data into the FIFO buffer although the FIFO buffer is already full.
3
CollErr
Set to logic 1, if a bit-collision is detected. It is set to logic level 0 automatically
at receiver start phase. This flag is only valid during the bitwise anticollision at
106 kbit/s. During communication schemes at 212 and 424 kbit/s this flag is
always set to logic level 0.
2
CRCErr
Set to logic 1, if RxCRCEn in CIU_RxMode register is set to logic level 1 and
the CRC calculation fails. It is set to logic level 0 automatically at receiver
start-up phase.
1
ParityErr
Set to logic 1, if the parity check has failed. It is set to logic level 0 automatically
at receiver start-up phase. Only valid for ISO/IEC 14443A/MIFARE or NFCIP-1
communication at 106 kbit/s.
0
ProtocollErr
Set to logic 1, if one out of the following cases occurs:
[1]
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•
Set to logic 1 if the SOF is incorrect. It is set to logic level 0 automatically at
receiver start-up phase. The bit is only valid for 106 kbit in Active and
Passive Communication mode.
•
If bit DetectSync in CIU_Mode register is set to logic 1 during FeliCa
communication or Active Communication with transfer speeds higher than
106 kbit, ProtocolErr is set to logic 1 in case of a byte length violation.
•
During the AutoColl command, ProtocolErr is set to logic 1, if the Initiator
bit in CIU_Control register is set to logic 1.
•
During the MFAuthent Command, ProtocolErr is set to logic 1, if the
number of bytes received in one data stream is incorrect.
•
Set to logic 1, if the Miller Decoder detects 2 pauses below the minimum
time according to the ISO/IEC 14443A definitions.
Command execution will clear all error flags except for bit TempErr. A setting by firmware is impossible.
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8.6.23.9
CIU_Status1 register (DFh or 6337h)
Contains status flags of the CRC, Interrupt Request System and FIFO buffer.
Table 191. CIU_Status1 register (address DFh or 6337h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol CIU_IRQ_1 CRCOk CRCReady CIU_IRQ_0 TRunning RFOn HiAlert LoAlert
Reset
0
0
1
0
0
X
0
1
Access
R
R
R
R
R
R
R
R
Table 192. Description of CIU_Status1 bits
Bit Symbol
Description
7
CIU_IRQ_1 This bit shows, if any CIU_IRQ_1 source requests attention (with respect to the
setting of the interrupt enable flags, see CIU_CommIEn and CIU_DivIEn
registers).
6
CRCOk
5
CRCReady Set to logic 1, when the CRC calculation has finished. This bit is only valid for the
CRC co-processor calculation using the CalcCRC command.
4
CIU_IRQ_0 This bit shows, if any CIU_IRQ_0 source requests attention (with respect to the
setting of the interrupt enable flags, see CIU_CommIEn and CIU_DivIEn
registers).
3
TRunning
Set to logic 1, the CRC result is zero. For data transmission and reception the bit
CRCOk is undefined (use CRCErr in CIU_Error register). CRCok indicates the
status of the CRC coprocessor, during calculation the value changes to logic
level 0, when the calculation is done correctly, the value changes to logic level 1.
Set to logic 1, the CIU_timer is running, e.g. the CIU_timer will decrement the
CIU_TCounterVal_lo with the next timer clock.
Note: In the gated mode TRunning is set to logic 1, when the CIU_timer is
enabled by the register bits. This bit is not influenced by the gated signal.
2
RFOn
Set to logic 1, if an external RF field is detected. This bit does not store the state
of the RF field.
1
HiAlert
Set to logic 1, when the number of bytes stored in the FIFO buffer fulfils the
following equation:
HiAlert = 64 – FIFOLength WaterLevel
Example:
FIFOLenght = 60 WaterLevel = 4 HiAlert = 1
FIFOLenght = 59 WaterLevel = 4 HiAlert = 0
0
LoAlert
Set to logic 1, when the number of bytes stored in the FIFO buffer fulfills the
following equation:
LoAlert = FIFOLength WaterLevel
Example:
FIFOLenght = 4 WaterLevel = 4 LoAlert = 1
FIFOLenght = 5 WaterLevel = 4 LoAlert = 0
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8.6.23.10
CIU_Status2 register (E9h or 6338h)
Contain status flags of the receiver, transmitter and Data Mode Detector.
Table 193. CIU_Status2 register (address E9h or 6338h) bit allocation
Bit
Symbol
7
6
5
4
3
TempSensClear
-
RFFreqOK
TgActivated
MFCrypto1On
Reset
Access
2
1
0
ModemState[2:0]
0
0
0
0
0
0
0
0
R/W
R
R
DY
DY
R
R
R
Table 194. Description of CIU_Status2 bits
Bit
Symbol
Description
7
TempSensClear
Set to logic 1, this bit clears the temperature error, if the temperature is
below the alarm limit of 125 C.
6
-
Reserved
5
RFFreqOK
Indicates if the frequency detected at the RX pin is in the range of
13.56 MHz.
Set to logic 1, if the frequency at the RX pin is in the range 12 MHz <
RX pin frequency < 15 MHz.
Note: The value of RFFreqOK is not defined if the external RF
frequency is in the range of 9 to 12 MHz or in the range of 15 to
19 MHz.
4
TgActivated
Set to logic 1 if the Select command is received correctly or if the
Polling command was answered.
Note: This bit can only be set during the AutoColl command in Passive
Communication mode or Card operating modes.
Note: This bit is set to logic level 0 automatically by switching off the
RF field.
3
MFCrypto1On
Set to logic level 1, MIFARE Crypto1 unit is switched on and therefore
all data communication with the card is encrypted.
This bit can only be set to logic 1 by a successful execution of the
MFAuthent command. This is only valid in Reader/Writer mode for
MIFARE 1 KB or MIFARE 4 KB emulation cards.
This bit shall be set to logic level 0 by firmware.
2 to 0
ModemState[2:0] ModemState shows the state of the transmitter and receiver state
machines.
Value Description
000 Idle
001 Wait for StartSend in CIU_BitFraming register
010 TxWait: Wait until RF field is present, if TxWaitRF is set to
logic 1. The minimum time for TxWait is defined by the TxWait
register.
011 Transmitting
100 RxWait: Wait until RF field is present, if the bit RxWaitRF is set
to logic 1. The minimum time for RxWait is defined by the
RxWait register
101 Wait for data
110 Receiving
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8.6.23.11
CIU_FIFOData register (EAh or 6339h)
In- and output of 64 byte FIFO buffer.
Table 195. CIU_FIFOData register (address EAh or 6339h) bit allocation
Bit
7
6
5
4
Symbol
Reset
Access
3
2
1
0
FIFOData[7:0]
X
X
X
X
X
X
X
X
DY
DY
DY
DY
DY
DY
DY
DY
Table 196. Description of CIU_FIFOData bits
8.6.23.12
Bit
Symbol
Description
7 to 0
FIFOData[7:0] Data input and output port for the internal 64 bytes FIFO buffer. The FIFO
buffer acts as parallel in/parallel out converter for all data stream in- and
outputs
CIU_FIFOLevel register (EBh or 633Ah)
Indicates the number of bytes stored in the FIFO.
Table 197. CIU_FIFOLevel register (address EBh or 633Ah) bit allocation
Bit
7
Symbol
6
5
4
FlushBuffer
3
2
1
0
FIFOLevel[6:0]
Reset
0
0
0
0
0
0
0
0
Access
W
R
R
R
R
R
R
R
Table 198. Description of CIU_FIFOLevel bits
Bit
Symbol
Description
7
FlushBuffer
Set to logic 1, this bit clears the internal FIFO-buffer’s read- and
write-pointer and the bit BufferOvfl in the CIU_Error register immediately.
Reading this bit will always return logic level 0.
6 to 0 FIFOLevel[6:0] Indicates the number of bytes stored in the FIFO buffer. Writing to the
CIU_FIFOData Register increments, reading decrements FIFOLevel.
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8.6.23.13
CIU_WaterLevel register (ECh or 633Bh)
Defines the thresholds for FIFO under- and overflow warning.
Table 199. CIU_WaterLevel register (address ECh or 633Bh) bit allocation
Bit
7
6
Symbol
-
-
5
4
3
2
1
0
WaterLevel[6:0]
Reset
0
0
0
0
1
0
0
0
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Table 200. Description of CIU_WaterLevel bits
Bit
Symbol
Description
7 to 6
-
Reserved.
5 to 0
WaterLevel[5:0] This register defines a threshold to indicate a FIFO buffer over- or
underflow to the 80C51:
The HiAlert bit in CIU_Status1 register is set to logic 1, if the remaining
number of bytes in the FIFO-buffer space is equal or less than the
defined WaterLevel[5:0] bits.
The LoAlert bit in CIU_Status1 register is set to logic 1, if equal or less
than WaterLevel[5:0] bits are in the FIFO.
Remark: For the calculation of the HiAlert and LoAlert see Table 192
on page 161.
8.6.23.14
CIU_Control register (EDh or 633Ch)
Contains miscellaneous control bits.
Table 201. CIU_Control register (address EDh or 633Ch) bit allocation
Bit
Symbol
7
6
5
4
3
2
TStopNow
TStartNow
WrNFCIP-1IDtoFIFO
Initiator
-
RxLastBits[2:0]
1
0
Reset
0
0
0
0
0
0
0
0
Access
W
W
DY
R/W
R
R
R
R
Table 202. Description of CIU_Control bits
Bit
Symbol
Description
7
TStopNow
Set to logic 1, the timer stops immediately.
6
TStartNow
Reading this bit will always return logic level 0.
Set to logic 1, the timer starts immediately.
Reading this bit will always return logic level 0.
5
WrNFCIP-1IDtoFIFO Set to logic 1, the internal stored NFCID3 (10 bytes) is copied into
the FIFO.
Afterwards the bit is set to logic level 0 automatically.
4
Initiator
Set to logic 1, the PN533 acts as Initiator or Reader/Writer,
otherwise it acts as Target. or a Card.
3
-
Reserved.
2 to 0 RxLastBits[2:0]
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Shows the number of valid bits in the last received byte. If set to
000b, the whole byte is valid.
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8.6.23.15
CIU_BitFraming register (EEh or 633Dh)
Adjustments for bit oriented frames.
Table 203. CIU_BitFraming register (address EEh or 633Dh) bit allocation
Bit
7
Symbol
6
StartSend
5
4
3
RxAlign[2:0]
2
-
1
0
TxLastBits[2:0]
Reset
0
0
0
0
0
0
0
0
Access
W
R/W
R/W
R/W
R
R/W
R/W
R/W
Table 204. Description of CIU_BitFraming bits
Bit
Symbol
Description
7
StartSend
Set to logic 1, the transmission of data starts.
6 to 4
RxAlign[2:0]
Used for reception of bit oriented frames:
This bit is only valid in combination with the Transceive command.
RxAlign[2:0] defines the bit position for the first received bit to be stored
in the FIFO. Further received bits are stored in the following bit positions.
Example:
RxAlign[2:0] = 0: The LSB of the received bit is stored at bit 0, the
second received bit is stored at bit position 1.
RxAlign[2:0] = 1: The LSB of the received bit is stored at bit 1, the
second received bit is stored at bit position 2
RxAlign[2:0] = 7: The LSB of the received bit is stored at bit 7, the
second received bit is stored in the following byte
at bit position 0.
These bits shall only be used for bitwise anticollision at 106 kbit/s in
Passive Communication or Reader/Writer mode. In all other modes it
shall be set to logic level 0.
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3
-
Reserved.
2 to 0
TxLastBits[2:0] Used for transmission of bit oriented frames: TxLastBits defines the
number of bits of the last byte that shall be transmitted. A 000b indicates
that all bits of the last byte shall be transmitted.
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8.6.23.16
CIU_Coll register (EFh or 633Eh)
Defines the first bit collision detected on the RF interface.
Table 205. CIU_Coll register (address EFh or 633Eh) bit allocation
Bit
Symbol
7
6
5
ValuesAfterColl
-
CollPosNotValid
Reset
Access
4
3
2
1
0
CollPos
1
0
1
X
X
X
X
X
R/W
R
R
R
R
R
R
R
Table 206. Description of CIU_Coll bits
Bit
Symbol
Description
7
ValuesAfterColl
If this bit is set to logic 0, all receiving bits will be cleared after a
collision.
This bit shall only be used during bitwise anticollision at 106 kbit/s,
otherwise it shall be set to logic 1.
6
-
Reserved
5
CollPosNotValid Set to logic 1, if no Collision is detected or the Position of the collision is
out of range of the CollPos[4:0] bits.
This bit shall only be interpreted in Passive Communication mode at
106 kbit/s or ISO/IEC 14443A/MIFARE Reader/Writer mode.
4 to 0
CollPos
These bits show the bit position of the first detected collision in a
received frame, only data bits are interpreted.
Example:
00h indicates a bit collision in the 32nd bit.
01h indicates a bit collision in the 1st bit
08h indicates a bit collision in the 8th bit
This bit shall only be interpreted in Passive Communication mode at
106 kbit/s or ISO/IEC 14443A/MIFARE Reader/Writer mode if
CollPosNotValid is set to logic 0.
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8.6.23.17
CIU_Mode register (6301h)
Defines general modes for transmitting and receiving.
Table 207. CIU_Mode register (address 6301h) bit allocation
Bit
7
Symbol
Reset
Access
6
MSBFirst DetectSync
5
TXWaitRF
4
3
2
1
RxWaitRF PolSigin ModeDet
Off
0
CRCPreset
[1:0]
0
0
1
1
1
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 208. Description of CIU_Mode bits
Bit
Symbol
Description
7
MSBFirst
Set to logic 1, the CRC co-processor calculates the CRC with MSB first.
The bit order in the registers CRCResultMSB and the
CIU_CRCResultLSB is reversed.
Note: During RF communication this bit is ignored.
6
DetectSync
If set to logic 1, the CIU waits for the F0h byte before the receiver is
activated and F0h byte is added as a Sync-byte for transmission.
This bit is only valid for 106 kbit/s during NFCIP-1 data exchange
protocol.
In all other modes it shall be set to logic 0.
5
TXWaitRF
Set to logic 1 the transmitter in Reader/Writer or Initiator mode for
NFCIP-1 can only be started, if an own RF field is generated (i.e.
Tx1RFEn and/or Tx2RFen is set to logic level 1).
4
RxWaitRF
Set to logic 1, the counter for RxWait starts only, if an external RF field is
detected in Target mode for NFCIP-1 or in Card Operating mode
3
PolSigin
PolSigin defines the polarity of the SIGIN pin.
Set to logic 1, the polarity of SIGIN pin is active high.
Set to logic 0 the polarity of SIGIN pin is active low.
Note: The internal envelope signal is coded active low.
Note: Changing this bit will generate a SiginActIrq event.
2
ModeDetOff
Set to logic 1, the internal Data Mode Detector is switched off.
Note: The Data Mode Detector is only active during the AutoColl
command.
1 to 0 CRCPreset[1:0] Defines the preset value for the CRC co-processor for the CalCRC
command.
Note: During any communication, the preset values is selected
automatically according to the mode definition in the CIU_RxMode and
CIU_TxMode registers.
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Value
Description
00
00 00
01
63 63
10
A6 71
11
FF FF
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8.6.23.18
CIU_TxMode register (6302h)
Defines the transmission data rate and framing during transmission.
Table 209. CIU_TxMode register (address 6302h) bit allocation
Bit
7
Symbol
6
TxCRCEn
Reset
Access
5
4
TxSpeed[2:0]
3
2
InvMod
TxMix
1
0
TxFraming[1:0]
0
0
0
0
0
0
0
0
R/W
DY
DY
DY
R/W
R/W
DY
DY
Table 210. Description of CIU_TxMode bits
Bit
Symbol
Description
7
TxCRCEn
Set to logic 1, this bit enables the CRC generation during data
transmission.
Note: This bit shall only set to logic 0 at 106 kbit/s.
6 to 4
TxSpeed[2:0]
Defines bit rate while data transmission.
Value
Description
000
106 kbit/s
001
212 kbit/s
010
424 kbit/s
011
848 kbit/s
100
1696 kbit/s
101
Reserved
110 - 111
Reserved
Note: The bit coding for transfer speeds above 424 kbit/s is equivalent
to the bit coding of the Active Communication mode of the 424 kbit/s of
the ISO/IEC18092 / ECMA340.
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3
InvMod
Set to logic 1, the modulation for transmitting data is inverted.
2
TxMix
Set to logic 1, the signal at SIGIN is mixed with the internal coder. See
Section 8.6.12 “Serial data switch” on page 131.
1 to 0
TxFraming[1:0]
Defines the framing used for data transmission.
Value
Description
00
ISO/IEC 14443A/MIFARE and Passive Communication
mode 106 kbit/s
01
Active Communication mode
10
FeliCa and Passive Communication mode at 212 kbit/s
and 424 kbit/s
11
ISO/IEC 14443B
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8.6.23.19
CIU_RxMode register (6303h)
Defines the reception data rate and framing during receiving.
Table 211. CIU_RxMode register (address 6303h) bit allocation
Bit
7
Symbol
6
RXCRCEn
Reset
Access
5
4
RxSpeed[2:0]
3
2
RxNoErr
RxMultiple
1
0
RxFraming[1:0]
0
0
0
0
0
0
0
0
R/W
DY
DY
DY
R/W
R/W
DY
DY
Table 212. Description of CIU_RxMode bits
Bit
Symbol
Description
7
RxCRCEn
Set to logic 1, this bit enables the CRC calculation during reception. The
CRC bytes will not be written within the CIU FIFO.
Note: This bit shall only set to logic level 0 at 106 kbit/s.
6 to 4 RxSpeed[2:0]
Defines the bit rate while data receiving.
The analog part of the CIU handles only transfer speeds up to 424 kbit/s
internally, the digital part of the CIU handles the higher transfer speeds as
well.
Value
Description
000
106 kbit/s
001
212 kbit/s
010
424 kbit/s
011
848 kbit/s
100
1696 kbit/s
101
Reserved
110 - 111
Reserved
Note: The bit coding for transfer speeds above 424 kbit/s is equivalent to
the bit coding of the active communication mode of the 424 kbit/s of the of
the ISO/IEC18092 / ECMA340.
3
RxNoErr
If set to logic 1, a not valid received data stream (less than 4 bits received)
will be ignored. The receiver will remain active.
2
RxMultiple
Set to logic 0, the receiver is deactivated after receiving a data frame.
Set to logic 1, it is possible to receive more than one data frame. This bit
is only valid for 212 and 424 kbit/s to handle the Polling command. Having
set this bit, the receive and transceive commands will not end
automatically. In this case the multiple receiving can only be deactivated
by writing the Idle command to the CIU_Command register or clearing this
bit by the 80C51.
If set to logic 1, at the end of a received data stream an error byte is
added to the FIFO. The error byte is a copy of the CIU_Error register.
1 to 0 RxFraming[1:0] Defines the expected framing for data reception.
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Value
Description
00
ISO/IEC 14443A/MIFARE and Passive Communication
mode 106 kbit/s
01
Active communication mode
10
FeliCa and Passive Communication mode at 212 kbit/s
and 424 kbit/s
11
ISO/IEC 14443B
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8.6.23.20
CIU_TxControl register (6304h)
Controls the logical behavior of the antenna driver pins TX1 and TX2. See alsoTable 155
on page 124 and Table 156 on page 124.
Table 213. CIU_TxControl register (address 6304h) bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
InvTx2
RFon
InvTx1
RFon
InvTx2
RFoff
InvTx1
RFoff
Tx2
CW
CheckRF
Tx2
RFEn
Tx1
RFEn
Reset
Access
1
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
Table 214. Description of CIU_TxControl bits
Bit Symbol
Description
7
InvTx2RFon Set to logic1 and Tx2RFEn set to logic level 1, TX2 output signal is inverted.
6
InvTx1RFon Set to logic1 and Tx1RFEn set to logic level 1, TX1 output signal is inverted.
5
InvTx2RFoff Set to logic1 and Tx2RFEn set to logic level 0, TX2 output signal is inverted.
4
InvTx1RFoff Set to logic1 and Tx1RFEn set to logic level 0, TX1 output signal is inverted.
3
Tx2CW
Set to logic 1, the output signal on pin TX2 will deliver continuously the
un-modulated 13.56 MHz energy carrier.
Set to logic 0, Tx2CW is enabled to modulate of the 13.56 MHz energy carrier.
2
CheckRF
Set to logic 1, Tx2RFEn and Tx1RFEn can not be set if an external RF field is
detected.
Only valid when using in combination with Tx2RFAutoEn and TX1RFAutoEn
bits in CIU_TxAuto register.
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1
Tx2RFEn
Set to logic 1, the output signal on pin TX2 will deliver the 13.56 MHz energy
carrier modulated by the transmission data.
0
Tx1RFEn
Set to logic 1, the output signal on pin TX1 will deliver the 13.56 MHz energy
carrier modulated by the transmission data.
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8.6.23.21
CIU_TxAuto register (6305h)
Controls the setting of the antenna driver.
Table 215. CIU_TxAuto register (address 6305h) bit allocation
Bit
7
Symbol
5
Auto
Force
AutoWakeUp
RFOFF 100ASK
Reset
Access
6
4
-
3
2
CAOn InitialRFOn
1
0
Tx2
RFAutoEn
Tx1
RFAutoEn
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R/W
W
R/W
R/W
Table 216. Description of CIU_TxAuto bits
Bit Symbol
Description
7
AutoRFOff
Set to logic 1, own RF field is switched off after the last data bit has been
transmitted as defined in the NFCIP-1 standard.
6
Force100ASK Set to logic 1, Force100ASK forces a 100% ASK modulation independent of
the setting in CIU_ModGsP register.
5
AutoWakeUp
4
Set to logic 1, the PN533 in CIU Power-down mode can be woken up by the
RF level detector.
Reserved
3
CAOn
Set to logic 1, the collision avoidance is activated and internally the value n is
set in accordance to the ISO/IEC 18092 / ECMA340 NFCIP-1 standards.
2
InitialRFOn
Set to logic 1, the initial RF collision avoidance is performed and the bit
InitialRFOn is set to logic level 0 automatically, if the RF is switched ON.
Note: The driver(s) which should be switched on, have to enabled by
Tx2RFAutoEn and/or Tx1RFAutoEn bits.
Note: If the own RF field is already ON when the bit InitialRFOn is set, it is not
set to logic level 0.
1
Tx2RFAutoEn Set to logic 1, RF is switched on at TX2 (i.e. Tx2RFEn is set to logic level 1)
after the external RF field is switched off according to the time TADT. If the
InitialRFOn and Tx2RFAutoEn bits are set to logic 1, RF is switched on at TX2
if no external RF field is detected during the time TIDT.
Note: The times TADT and TIDT are in accordance to the ISO/IEC 18092/
ECMA340 NFCIP-1 standards.
0
Tx1RFAutoEn Set to logic 1, RF is switched on at TX1(i.e. Tx1RFEn is set to logic level 1)
after the external RF field is switched off according to the time TADT. If the
InitialRFOn and Tx1RFAutoEn bits are set to logic 1, RF is switched on at TX1
if no external RF field is detected during the time TIDT.
Note: The times TADT and TIDT are in accordance to the ISO/IEC 18092/
ECMA340 NFCIP-1 standards.
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8.6.23.22
CIU_TxSel register (6306h)
Selects the sources for the analogue transmitter part
Table 217. CIU_TxSel register (address 6306h) bit allocation
Bit
7
Symbol
Reset
Access
6
5
LoadModSel[1:0]
4
3
DriverSel[1:0]
2
1
0
SigOutSel[3:0]
0
0
0
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 218. Description of CIU_TxSel bits
Bit
Symbol
Description
7 to 6 LoadModSel[1:0] Selects the signal to be output on LOADMOD
Value
5 to 4 DriverSel[1:0]
Description
00
Tristate
01
Modulation signal (envelope) from the internal coder
10
Modulation signal (envelope) from SIGIN
11
Test signal defined by LoadModtest in register
CIU_TestSel1
Selects the signals to be output on Tx1 and Tx2.
Value
Description
00
Tristate
01
Modulation signal (envelope) from the internal coder
10
Modulation signal (envelope) from SIGIN
11
HIGH
Note: The HIGH level depends on the setting of
InvTx1RFON/InvTx1RFOff and InvTx2RFON/InvTx2RFOff.
3 to 0 SigOutSel[3:0]
Select the signal to be output on SIGOUT
0000
Tristate
0001
Low
0010
High
0011
Test bus signal as defined by TestBusBitSel in
CIU_TestSel1.
0100
Modulation signal (envelope) from the internal coder
0101
Serial data stream to be transmitted
0110
Output signal of the receiver circuit (card modulation signal
regenerated and delayed). This signal is used as data
output signal for secure IC interface connection using 3
lines.
Note: To have a valid signal the CIU has to be set to the
receiving mode by either the Transceive or Receive
command. The RxMultiple bit can be used to keep the CIU
in receiving mode.
Note: Do not use this setting in ISO/IEC 14443A/MIFARE
mode. Data collisions will not be transmitted on SIGOUT
when using Manchester coding.
0111
Serial data stream received.
Note: Do not use this setting in ISO/IEC 14443A/MIFARE
mode. Miller coding parameters as the bitlength can vary
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Table 218. Description of CIU_TxSel bits …continued
Bit
Symbol
Description
1000-1011
FeliCa secure IC modulation
1000 RX*
1001 TX
1010 Demodulator comparator output
1011 Reserved
Note: * To have a valid signal the CIU has to be set to the
receiving mode by either the Transceive or Receive
commands. The bit RxMultiple can be used to keep the
CIU in receiving mode
1000-1011
MIFARE secure IC modulation
1100 RX* with RF carrier
1101 TX with RF carrier
1110 RX with RF carrier unfiltered
1111
RX envelope unfiltered
Note: * To have a valid signal the CIU has to be set to the
receiving mode by either the Transceive or Receive
commands. The bit RxMultiple can be used to keep the
CIU in receiving mode
8.6.23.23
CIU_RxSel register (6307h)
Selects internal receiver settings.
Table 219. CIU_RxSel register (address 6307h) bit allocation
Bit
7
Symbol
UartSel[1:0]
Reset
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Access
6
5
4
3
2
1
0
1
0
0
R/W
R/W
R/W
RxWait[5:0]
Table 220. Description of CIU_RxSel bits
Bit
Symbol
7 to 6
UartSel[1:0] Selects the input of the digital part (CL UART) of the CIU
5 to 0
Description
Value
Description
00
Constant Low
01
Envelope signal at SIGIN
10
Modulation signal from the internal analog part
11
Modulation signal from SIGIN pin. Only valid for transfer
speeds above 424 kbit/s
RxWait[5:0] After data transmission, the activation of the receiver is delayed for RxWait
bit-clocks. During this ‘frame guard time’ any signal at pin Rx is ignored.
This parameter is ignored by the Receive command. All other commands
(e.g. Transceive, Autocoll, MFAuthent) use this parameter. Depending on
the mode of the CIU, the counter starts differently. In Passive
Communication mode the counters starts with the last modulation of the
transmitted data stream. In Active Communication mode the counter starts
immediately after the external RF field is switched on.
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8.6.23.24
CIU_RxThreshold register (6308h)
Selects thresholds for the bit decoder.
Table 221. CIU_RxThreshold register (address 6308h) bit allocation
Bit
7
6
Symbol
5
4
MinLevel[3:0]
Reset
Access
3
2
-
1
0
Collevel[2:0]
1
0
0
0
0
1
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Table 222. Description of CIU_RxThreshold bits
8.6.23.25
Bit
Symbol
Description
7 to 4
MinLevel[3:0] Defines the minimum signal strength at the decoder input that shall be
accepted. If the signal strength is below this level, it is not evaluated.
3
-
Reserved
2 to 0
Collevel[2:0]
Defines the minimum signal strength at the decoder input that has to be
reached by the weaker half-bit of the Manchester-coded signal to generate
a bit-collision relatively to the amplitude of the stronger half-bit.
CIU_Demod register (6309h)
Defines demodulator settings.
Table 223. CIU_Demod register (address 6309h) bit allocation
Bit
7
Symbol
6
AddIQ[1:0]
Reset
Access
5
4
3
FixIQ
-
TauRcv[1:0]
2
TauSync[1:0]
1
0
0
1
0
0
1
1
0
1
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Table 224. Description of CIU_Demod bits
Bit
Symbol
Description
7 to 6
AddIQ[1:0]
Defines the use of I and Q channel during reception.
Note: FixIQ has to be set to logic 0 to enable the following settings.
5
FixIQ
Value
Description
00
Select the stronger channel
01
Select the stronger and freeze the selected during
communication
10
Combines the I and Q channel
11
RFU
If set to logic 1 and AddIQ[0] is set to logic level 0, the reception is fixed to
I channel.
If set to logic 1 and AddIQ[0] is set to logic level 1, the reception is fixed to
Q channel.
4
-
Reserved
3 to 2
TauRcv[1:0]
Changes time-constant of internal PLL during data receiving.
1 to 0
TauSync[1:0] Changes time-constant of internal PLL during burst (out of data reception)
Note: If set to 00h, the PLL is frozen during data receiving.
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8.6.23.26
CIU_FelNFC1 register (630Ah)
Defines the length of the FeliCa Sync bytes and the minimum length of the received
frame.
Table 225. CIU_FelNFC1 register (address 630Ah) bit allocation
Bit
Symbol
Reset
Access
7
6
5
4
FelSyncLen[1:0]
3
2
1
0
DataLenMin[5:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 226. Description of CIU_FelNFC1 bits
Bit
Symbol
Description
7 to 6 FelSyncLen[1:0]] Defines the length of the Sync bytes.
Value
Description
00
B2 4D
01
00 B2 4D
10
00 00 B2 4D
11
00 00 00 B2 4D
5 to 0 DataLenMin[5:0] These bits define the minimum length of the accepted frame length.
DataLenMin 4 DataPacketLenght
This parameter is ignored at 106 kbit/s if the DetectSync bit in
CIU_Mode register is set to logic 0. If a received frame is shorter as the
defined DataLenMin value, the frame will be ignored.
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8.6.23.27
CIU_FelNFC2 register (630Bh)
Defines the maximum length of the received frame.
Table 227. CIU_FelNFC2 register (address 630Bh) bit allocation
Bit
Symbol
7
6
WaitForSelected
ShortTimeSlot
0
R/W
Reset
Access
5
4
3
0
0
0
0
R/W
R/W
R/W
R/W
2
1
0
0
0
0
R/W
R/W
R/W
DataLenMax[5:0]
Table 228. Description of CIU_FelNFC2 bits
Bit
Symbol
Description
7
WaitForSelected
Set to logic 1, the AutoColl command is automatically ended only
when:
1. A valid command has been received after performing a valid
Select procedure according to ISO/IEC 14443A.
2. A valid command has been received after performing a valid
Polling procedure according to the FeliCa specification.
Note: If this bit is set, no Active Communication is possible.
Note: Setting this bit reduces the 80C51 interaction in case of a
communication to another device in the same RF field during Passive
Communication mode.
6
ShortTimeSlot
Defines the time slot length for Active Communication mode at
424 kbit/s.
Set to logic 1 a short time slot is used (half of the timeslot
at 212 kbit/s).
Set to logic 0 a long timeslot is used (equal to the timeslot for
212 kbit/s).
5 to 0
DataLenMax[5:0] These bits define the maximum length of the accepted frame length:
DataLenMax 4 DataPacketLenght
Note: If set to logic 0 the maximum data length is 256 bytes.
This parameter is ignored at 106 kbit/s if the bit DetectSync in register
CIU_Mode is set to logic 0.
If a received frame is larger as the defined DataLenMax value, the
frame will be ignored.
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8.6.23.28
CIU_MifNFC register (630Ch)
Defines ISO/IEC 14443A/MIFARE/NFC specific settings in target or card operating mode.
Table 229. CIU_MifNFC register (address 630Ch) bit allocation
Bit
7
Symbol
Reset
Access
6
5
4
SensMiller[2:0]
3
TauMiller[1:0]
2
1
MFHalted
0
TxWait[1:0]
0
1
1
0
0
0
1
0
R/W
R/W
R/W
R/W
R/W
DY
R/W
R/W
Table 230. Description of CIU_MifNFC bits
Bit
Symbol
Description
7 to 5
SensMiller[2:0] This bit defines the sensitivity of the Miller decoder.
4 to 3
TauMiller[1:0]
This bit defines the time constant of the Miller decoder.
2
MFHalted
Set to logic 1, this bit indicates that the CIU is set to HALT mode in
Card Operating mode at 106 kbit/s. This bit is either set by the 80C51
or by the internal state machine and indicates that only the code 52h is
accepted as a Request command.
This bit is automatically set to logic level 0 by RF reset.
1 to 0
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TxWait[1:0]
In combination with TxBitPhase[6:0] in CIU_TxBitPhase register,
defines the additional response time for the target at 106 kbit/s in
Passive Communication mode and during the AutoColl command. See
CIU_TxBitPhase register.
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8.6.23.29
CIU_ManualRCV register (630Dh)
Allows manual fine tuning of the internal receiver.
IMPORTANT NOTE: For standard application it is not recommended to change this
register settings.
Table 231. CIU_ManualRCV register (address 630Dh) bit allocation
Bit
7
6
5
Symbol
-
Reset
0
0
0
0
0
0
0
0
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FastFilt Delay
MF_SO MF_SO
4
ParityDisable
3
2
1
LargeBWPLL ManualHPCF
0
HPCF[1:0]
Table 232. Description of CIU_ManualRCV bits
Bit
Symbol
Description
7
-
Reserved
6
FastFiltMF_SO If this bit is set to logic 1, the internal filter for the Miller-Delay circuit is
set to Fast-Mode
Note: This bit should only be set to logic 1, if the Miller pauses length
expected are less than 400 ns. At 106 kbit/s, the Miller pauses duration
is around 3 s.
5
DelayMF_SO
If this bit is set to logic 1, when SigoutSel=1100b (register 6306h), the
Signal at SIGOUT-pin is delayed according the delay defined by
TxBitPhase[6:0] (register 6315h) and TxWait bits (register 630Ch).
Note: In ISO/IEC 14443A/MIFARE Card MIFARE 1 KB or MIFARE 4 KB
emulation (Virtual Card) mode (DriverSel = 10b and SigoutSel=1110b),
the Signal at SIGIN must then be 128 /fc faster compared to the
ISO/IEC 14443A restrictions on the RF-Field for the Frame Delay Time.
Note: This delay shall only be activated for setting bits SigOutSel to
(1110b) or (1111b) in register CIU_TxSel.
If this bit is set to logic 0, the SIGOUT-pin delay is not adjustable.
Note: In ISO/IEC 14443A/MIFARE card 1 KB or MIFARE 4 KB
emulation (Virtual Card) mode (DriverSel = 10b and SigoutSel=1110b),
the ISO/IEC 14443A restrictions on the RF-Field for the Frame Delay
Time should be adjusted on the secure IC side
4
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ParityDisable
If this bit is set to logic 1, the generation of the Parity bit for transmission
and the parity check for receiving is switched off. The received parity bit
is handled like a data bit.
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Table 232. Description of CIU_ManualRCV bits …continued
Bit
Symbol
Description
3
LargeBWPLL
Set to logic 1, the bandwidth of the internal PLL for clock recovery is
extended.
Note: As the bandwidth is extended, the PLL filtering effect is weaker
and the performance of the communication may be affected.
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2
ManualHPCF
Set to logic 0, the HPCF[1:0] bits are ignored and the HPCF[1:0]
settings are adapted automatically to the receiving mode.
1 to 0
HPCF[1:0]
Selects the High Pass Corner Frequency (HPCF) of the filter in the
internal receiver chain
Value
Description
00
For signals with frequency spectrum down to 106 kHz
01
For signals with frequency spectrum down to 212 kHz
10
For signals with frequency spectrum down to 424 kHz
11
For signals with frequency spectrum down to 848 kHz
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8.6.23.30
CIU_TypeB register (630Eh)
Selects the specific settings for the ISO/IEC 14443B
Table 233. CIU_TypeB register (address 630Eh) bit allocation
Bit
7
Symbol
Reset
Access
6
Rx
Rx
SOFReq EOFReq
5
4
3
2
-
EOFSOF
Width
NoTx
SOF
NoTx
EOF
1
0
TxEGT[1:0]
0
0
0
0
0
0
0
0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Table 234. Description of CIU_TypeB bits
Bit
Symbol
Description
7
RxSOFReq
If this bit is set to logic 1, the SOF is required. A datastream starting
without SOF is ignored.
If this bit is set to logic level 0, a datastream with and without SOF is
accepted. The SOF will be removed and not written into the FIFO.
6
RxEOFReq
If this bit is set to logic 1, the EOF is required. A datastream ending
without EOF will generate a protocol error: ProtocollErr in the CIU_Error
register will be set to logic level 1.
If this bit is set to logic level 0, a datastream with and without EOF is
accepted. The EOF will be removed and not written into the FIFO.
5
-
Reserved.
4
EOFSOFWidth
If this bit is set to logic 1, the SOF and EOF will have the maximum length
defined in the ISO/IEC 14443B.
If this bit is set to logic level 0, the SOF and EOF will have the minimum
length defined in the ISO/IEC 14443B.
3
NoTxSOF
If this bit is set to logic 1, the generation of the SOF is suppressed.
2
NoTxEOF
If this bit is set to logic 1, the generation of the EOF is suppressed.
1 to 0 TxEGT[1:0]
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These bits define the length of the EGT, as defined in the
ISO/IEC 14443B
Value
Description
00
0 bit
01
1 bit
10
2 bits
11
3 bits
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8.6.23.31
CIU_CRCResultMSB register (6311h)
Shows the actual MSB values of the CRC calculation.
Note: The CRC is split into two 8-bit registers. See also the CIU_CRCResultLSB register.
Note: Setting the bit MSBFirst in CIU_Mode register reverses the bit order, the byte order
is not changed
Table 235. CIU_CRCResultMSB register (address 6311h) bit allocation
Bit
7
6
5
Symbol
4
3
2
1
0
CRCResultMSB[7:0]
Reset
1
1
1
1
1
1
1
1
Access
R
R
R
R
R
R
R
R
Table 236. Description of CIU_CRCResultMSB bits
Bit
Symbol
Description
7 to 0 CRCResultMSB[7:0] This register shows the actual value of the most significant byte of
the CRC calculation. It is valid only if CRCReady bit in CIU_Status1
register is set to logic 1.
8.6.23.32
CIU_CRCResultLSB register (6312h)
Shows the actual LSB values of the CRC calculation.
Note: The CRC is split into two 8-bit registers. See also the CIU_CRCResultMSB register.
Note: Setting the bit MSBFirst in CIU_Mode register reverses the bit order, the byte order
is not changed
Table 237. CIU_CRCResultLSB register (address 6312h) bit allocation
Bit
7
6
5
Symbol
4
3
2
1
0
CRCResultLSB[7:0]
Reset
1
1
1
1
1
1
1
1
Access
R
R
R
R
R
R
R
R
Table 238. Description of CIU_CRCResultLSB bits
Bit
Symbol
Description
7 to 0 CRCResultLSB[7:0] This register shows the actual value of the most significant byte of
the CRC register. It is valid only if CRCReady bit in CIU_Status1
register is set to logic 1.
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8.6.23.33
CIU_GsNOff register (6313h)
Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when
there is no RF generated by the PN533.
Table 239. CIU_GsNOff register (address 6313h) bit allocation
Bit
7
Symbol
Reset
Access
6
5
4
3
CWGsNOff[3:0]
2
1
0
ModGsNOff[3:0]
1
0
0
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 240. Description of CIU_GsNOff bits
Bit
Symbol
Description
7 to 4
CWGsNOff[3:0]
The value of this register defines the conductance of the output
N-driver during the time of no modulation and when there is no RF
generated by the PN533 (neither Tx1RFEn nor Tx2RFEn is set to
logic level 1).
Note: The conductance value is binary weighted.
Note: During CIU Power-down mode, if DriverSel[1:0] is not equal to
01b, CWGsNOff[3] is set to logic level 1. This is not readable in the
register.
Note: The value of the register is only used if no RF is generated by
the driver, otherwise the value CWGsNOn in the CIU_GsNOn
register is used.
3 to 0
ModGsNOff[3:0] The value of this register defines the conductance of the output
N-driver for the time of modulation and when there is no RF
generated by the PN533 (neither Tx1RFEn nor Tx2RFEn is set to
logic level 1).
This may be used to regulate the modulation index when doing load
modulation.
Note: The conductance value is binary weighted.
Note: During CIU Power-down, if DriverSel[1:0] is not equal to 01b,
ModGsNOff[3] is set to logic level 1. This is not readable in the
register.
Note: The value of the register is only used if no RF is generated by
the driver, otherwise the value ModGsNOn in the CIU_GsNOn
register is used.
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8.6.23.34
CIU_ModWidth register (6314h)
Controls the setting of the modulation width.
Table 241. CIU_ModWidth register (address 6314h) bit allocation
Bit
7
6
5
Symbol
Reset
Access
4
3
2
1
0
ModWidth[7:0]
0
0
1
0
0
1
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 242. Description of CIU_ModWidth bits
Bit
Symbol
Description
7 to 0
ModWidth[7:0] These bits define the width of the Miller modulation as initiator in Active
and Passive Communication mode as multiples of the carrier frequency
(ModWidth+1 / fc). The maximum value is half the bit period.
Acting as a target in Passive Communication mode at 106 kbit/s or in
Card Operating mode for ISO/IEC 14443A/MIFARE these bits are used
to change the duty cycle of the subcarrier frequency.
Number of cycles with low value: NCLV = (Modwidth modulo 8)+1
Number of cycles with high value: NCHV = 16 - NCLV
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8.6.23.35
CIU_TxBitPhase register (6315h)
Adjust the bit phase at 106 kbit/s during transmission.
Table 243. CIU_TxBitPhase register (address 6315h) bit allocation
Bit
Symbol
7
6
5
4
RcvClkChange
Reset
Access
3
2
1
0
TxBitPhase[6:0]
1
0
0
0
0
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 244. Description of CIU_TxBitPhase bits
Bit
Symbol
Description
7
RcvClkChange
Set to logic 1, the demodulator’s clock is derivated from the external
RF field.
6 to 0
TxBitPhase[6:0] TXBitPhase[6:0] in addition with TxWait bits (register 63 0Ch), define a
delay to adjust the bit synchronization during Passive Communication
mode at 106 kbit/s and in ISO/IEC 14443A/MIFARE Reader/Writer
mode. TxBitphase[6:0] are representing a delay in number of carrier
frequency clock cycles.
Note: The ranges to be used for TxWait[1:0] and TxBitPhase[6:0] are
between:
TXWait=01b and TxBitPhase = 1Bh (equivalent to an added delay of
20 clock cycles) and TXWait=01b and TxBitPhase = 7Fh (equivalent to
an added delay of 120 clock cycles)
TxWait=10b and TxBitPhase = 00h (equivalent to an added delay of
121 clock cycles) and TxWait=10b and TxBitPhase = 0Fh (equivalent
to an added delay of 136 clock cycles)
Note: The delay can vary depending of antenna circuits.
Note: When DriverSel = 01b (the transmitter modulation input is
coming from the internal coder), this delay is added to the waiting
period before transmitting data in all communication modes.
Note: When SigoutSel=1110b (CIU_TxSel register), and DelayMF_SO
=1b (CIU_ManualRCV register), this delay is added on SIGOUT.
Note: II the Signal at SIGIN is 128/fc faster compared to the
ISO/IEC 14443A restrictions on the RF-Field for the Frame Delay
Time, this delay is made so that if the FDT is correct when DriverSel =
01b, the same values of TxWait[1:0] and TxBitPhase[6:0] are also
correct for this configuration when DriverSel = 10b (the transmitter
modulation input is coming from SIGIN).
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8.6.23.36
CIU_RFCfg register (6316h)
Configures the receiver gain and RF level detector sensitivity.
Table 245. CIU_RFCfg register (address 6316h) bit allocation
Bit
Symbol
7
RFLevelAmp
Reset
Access
6
5
4
3
RxGain[2:0]
2
1
0
RFLevel[3:0]
0
1
0
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 246. Description of CIU_RFCfg bits
Bit
Symbol
7
RFLevelAmp Set to logic 1, this bit activates the RF level detector’s amplifier, see
Section 8.6.8 “RF level detector” on page 126.
6 to 4
RxGain[2:0]
3 to 0
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Descrip
tion
This register defines the receivers signal voltage gain factor:
Value
Description
000
18 dB
001
23 dB
010
18 dB
011
23 dB
100
33 dB
101
38 dB
110
43 dB
111
48 dB
RFLevel[3:0] Defines the sensitivity of the RF level detector, for description see Section
8.6.8 “RF level detector” on page 126.
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8.6.23.37
CIU_GsNOn register (6317h)
Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when
generating RF.
Table 247. CIU_GsNOn register (address 6317h) bit allocation
Bit
7
6
Symbol
Reset
Access
5
4
3
CWGsNOn[3:0]
2
1
0
ModGsNOn[3:0]
1
0
0
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 248. Description of CIU_GsNOn bits
Bit
Symbol
Description
7 to 4
CWGsNOn[3:0]
The value of this register defines the conductance of the output
N-driver. during times of no modulation and when the PN533
generates the RF field.
This may be used to regulate the output power and subsequently
current consumption and operating distance.
Note: The conductance value is binary weighted.
Note: During CIU Power-down mode, if DriverSel[1:0] is not equal to
01b, CWGsNOn[3] is set to logic level 1. This is not readable in the
register.
Note: The value of the register is only used if RF is generated by the
driver (either Tx1RFEn or Tx2RFEn is set to logic level 1), otherwise
the value CWGsNOFF in the register CIU_GsNOff is used.
3 to 0
ModGsNOn[3:0]
The value of this register defines the conductance of the output
N-driver for the time of modulation and when the PN533 generates the
RF field.
This may be used to regulate the modulation index.
Note: The conductance value is binary weighted.
Note: During CIU Power-down mode, if DriverSel[1:0] is not equal to
01b, ModGsNOn[3] is set to logic level 1. This is not readable in the
register.
Note: The value of the register is only used if RF is generated by the
driver (either Tx1RFEn or Tx2RFEn is set to logic level 1), otherwise
the value ModGsNOff in the register CIU_GsNOFF is used.
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8.6.23.38
CIU_CWGsP register (6318h)
Defines the conductance of the P-driver.
Table 249. CIU_CWGsP register (address 6318h) bit allocation
Bit
7
6
Symbol
-
-
5
4
3
2
1
0
CWGsP[5:0]
Reset
0
0
1
0
0
0
0
0
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Table 250. Description of CIU_CWGsP bits
Bit
Symbol
Description
7 to 6
-
Reserved.
5 to 0
CWGsP[5:0]
The value of this register defines the conductance of the output P-driver,
during times of no modulation.
This may be used to regulate the output power and subsequently current
consumption and operating distance.
Note: The conductance value is binary weighted.
Note: During CIU Power-down mode, if DriverSel[1:0] is not equal to 01b,
CWGsP[5] is set to logic level 1. This is not readable in the register.
8.6.23.39
CIU_ModGsP register (6319h)
Defines the driver P-output conductance for the time of modulation.
Table 251. CIU_ModGsP register (address 6319h) bit allocation
Bit
7
6
5
4
3
Symbol
-
-
Reset
0
0
1
0
0
Access
R
R
R/W
R/W
R/W
2
1
0
0
0
0
R/W
R/W
R/W
ModGsP[5:0]
Table 252. Description of CIU_ModGsP bits
Bit
Symbol
7 to 6 -
Description
Reserved.
5 to 0 ModGsP[5:0] The value of this register defines the conductance of the output P-driver for
the time of modulation.
This may be used to regulate the modulation index.
Note: The conductance value is binary weighted.
Note: During CIU Power-down mode, if DriverSel[1:0] is not equal to 01b,
ModGsP[5] is set to logic level 1. This is not readable in the register.
Note: If Force100ASK in CIU_TxAuto register is set to logic level 1, the
ModGsP[5:0] setting has no effect.
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8.6.23.40
CIU_TMode register (631Ah)
Defines settings for the internal timer.
Table 253. CIU_TMode register (address 631Ah) bit allocation
Bit
7
Symbol
TAuto
Reset
Access
6
5
TGated[1:0]
4
3
TAutoRestart
2
1
0
TPrescaler_Hi[3:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 254. Description of CIU_TMode bits
Bit
Symbol
Description
7
TAuto
Set to logic 1, the timer starts automatically at the end of the
transmission in all communication modes at all speed, or when
InitialRFOn (in CIU_TxAuto) is set to logic 1 and the external RF field
is switched on. The timer stops immediately after receiving the first
data bit if RxMultiple in the CIU_RxMode register is set to logic
level 0.
If RxMultiple is set to logic 1, the timer never stops. In this case the
timer can be stopped by setting the bit TStopNow in register
CIU_Control to 1.
Set to logic 0 indicates, that the timer is not influenced by the
protocol.
6 to 5
TGated[1:0]
The internal timer is running in gated mode.
Note: In the gated mode, the bit TRunning is logic level 1 when the
timer is enabled by the register bits. This bit does not influence the
gating signal
4
TAutoRestart
Value
Description
00
No gated mode
01
Gated by SIGIN
10
Gated by AUX1
11
Reserved
Set to logic 1 the timer automatically restart its count-down from
TReloadValue defined within when reaches zero.
Set to logic 0 the timer decrements to zero and the bit TimerIRq is set
to logic 1.
3 to 0
TPrescaler_Hi[3:0] Defines higher 4 bits for the TPrescaler.
The following formula is used to calculate fTimer:
f Timer = 6,78MHz T PreScaler
For detailed description see Section 8.6.17 “CIU_timer” on page 140.
Note: TPreScaler is defined with TPreScaler_Hi[3:0] in this register
and TPreScaler_LO[7:0] in CIU_TPrescaler.
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8.6.23.41
CIU_TPrescaler register (631Bh)
Define the LSB of the Timer-Prescaler.
Table 255. CIU_TPrescaler register (address 631Bh) bit allocation
Bit
7
6
5
Symbol
Reset
Access
4
3
2
1
0
TPrescaler_LO[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 256. Description of CIU_TPrescaler bits
Bit
Symbol
Description
7 to 0
TPrescaler_LO[7:0] Defines lower 8 bits for TPrescaler.
The following formula is used to calculate fTimer
f Timer = 6,78MHz T PreScaler
For detailed description see Section 8.6.17 “CIU_timer” on page
140.
Note: The TPreScaler time is defined with TPreScaler_Hi[3:0] in
CIU_TMode and TPreScaler_LO[7:0] in this register.
8.6.23.42
CIU_TReload_hi register (631Ch)
Defines the MSB of the 16-bit long timer reload value.
Table 257. CIU_TReloadVal_hi register (address 631Ch) bit allocation
Bit
7
6
5
Symbol
Reset
Access
4
3
2
1
0
TReloadVal_Hi[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 258. Description of CIU_TReloadVal_hi bits
Bit
Symbol
Description
7 to 0
TReloadVal_Hi[7:0] Defines the higher 8 bits for the TReloadValue.
With a start event the timer loads with the TReloadValue. Changing
this register affects the timer only with the next start event.
Note: The reload value is defined with TReloadVal_Hi[7:0] in this
register and TReloadVal_Lo[7:0] in CIU_TReloadVal_lo
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8.6.23.43
CIU_TReloadVal_lo register (631Dh)
Defines the LSB of the 16 bit long timer reload value.
Table 259. CIU_TReload_lo register (address 631Dh) bit allocation
Bit
7
6
5
Symbol
3
2
1
0
TReloadVal_Lo[7:0]
Reset
Access
4
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 260. Description of CIU_TReload_lo bits
Bit
Symbol
Description
7 to 0 TReloadVal_Lo[7:0] Defines the lower 8 bits for the TReloadValue.
With a start event the timer loads with the TReloadValue. Changing
this register affects the timer only with the next start event.
Note: The reload value is defined with TReloadVal_Lo[7:0] in this
register and TReloadVal_Hi[7:0] in CIU_TReload_Hi.
8.6.23.44
CIU_TCounterVal_hi register (631Eh)
Defines the MSB byte of the current value of the timer.
Table 261. CIU_TCounterVal_hi register (address 631Eh) bit allocation
Bit
7
6
5
Symbol
4
3
2
1
0
TCounterVal_Hi[7:0]
Reset
x
x
x
x
x
x
x
x
Access
R
R
R
R
R
R
R
R
Table 262. Description of CIU_TCounterVal_hi bits
Bit
Symbol
Description
7 to 0 TCounterVal_Hi[7:0]
8.6.23.45
MSB of the current value of the timer (Higher 8 bits).
Register CIU_TCounterVal_lo (631Fh)
Defines the LSB byte of the current value of the timer.
Table 263. CIU_TCounterVal_lo register (address 631Fh) bit allocation
Bit
7
6
5
Symbol
4
3
2
1
0
TCounterVal_LO[7:0]
Reset
x
x
x
x
x
x
x
x
Access
R
R
R
R
R
R
R
R
Table 264. Description of CIU_TCounterVal_lo bits
Bit
Symbol
Description
7 to 0 TCounterVal_LO[7:0]
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LSB of the current value of the timer (Lower 8 bits).
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8.6.23.46
CIU_TestSel1 register (6321h)
General test signal configuration.
Table 265. CIU_TestSel1 register (address 6321h) bit allocation
Bit
7
Symbol
LoadModTst[1:0]
Reset
Access
6
5
4
SICclksel[1:0]
3
2
SICClkD1
1
0
TstBusBitSel[2:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 266. Description of CIU_TestSel1 bits
Bit
Symbol
Description
7 to 6
LoadModTst[1:0]
Defines the test signal for the LOADMOD pin
Note: The bits LoadModSel in register CIU_TxSel has to be set to
logic 1 to enable LoadModTst:
5 to 4
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SICclksel[1:0]
Value
Description
00
Low
01
High
10
RFU
11
TstBusBit as defined by the TestBusBitSel bit of this
register
Defines the source for the 13.56 MHz secure IC clock
Value
Description
00
GND - secure IC clock is switched off
01
Clock derivated by the internal oscillator
10
Internal CIU clock
11
Clock derivated from the RF Field
3
SICClkD1
Set to logic 1, the secure IC clock is delivered to P31 / UART_TX if the
observe_ciu bit is set to logic 1.
2 to 0
TstBusBitSel(2:0] Select the TstBusBit from the test bus.
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8.6.23.47
CIU_TestSel2 register (6322h)
General test signal configuration and PRBS control.
Table 267. CIU_TestSel2 register (address 6322h) bit allocation
Bit
Symbol
7
6
5
TstBusFlip
PRBS9
PRBS15
0
0
R/W
R/W
Reset
Access
4
3
2
0
0
0
R/W
R/W
R/W
1
0
0
0
0
R/W
R/W
R/W
TstBusSel[4:0]
Table 268. Description of CIU_TestSel2 bits
Bit
Symbol
Description
7
TstBusFlip
If set to logic 1, the internal test bus(D6-D0) is mapped to the external
test bus pins by the following order: D4,D3, D2,D6,D5, D0, D1. See
Section 8.6.21.2 “CIU test bus” on page 151.
6
PRBS9
Starts and enables the PRBS9 sequence according ITU-TO150.
Note: All relevant register to transmit data have to be configured before
entering PRBS9 mode.
Note: The data transmission of the defined sequence is started by the
Transmit command.
5
PRBS15
Starts and enables the PRBS15 sequence according ITU-TO150.
Note: All relevant register to transmit data have to be configured before
entering PRBS15 mode.
Note: The data transmission of the defined sequence is started by the
Transmit command.
4 to 0
8.6.23.48
TstBusSel[4:0]
Selects the test bus source. See Section 8.6.21.2 “CIU test bus” on
page 151.
CIU_TestPinEn register (6323h)
Enable the output drivers for the test pins.
Table 269. CIU_TestPinEn register (address 6323h) bit allocation
Bit
7
6
5
Symbol
Reset
Access
4
3
2
1
0
TestPinEn[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 270. Description of CIU_TestPinEn bits
Bit
Symbol
Description
7 to 0
TestPinEn[7:0] Each of the bit enables the output driver for an internal test pin: P70_IRQ
(MSB), RSTOUT_N, P35, P34 / SIC_CLK, P33_INT1, P32_INT0, P31 /
UART_TX, P30 / UART_RX (LSB). DataEn[7] enables P70_IRQ,
DataEn[0] enables P30 / UART_RX.
Note: The data transmission of the defined sequence is started by the
Transmit command.
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8.6.23.49
CIU_TestPinValue register (6324h)
Defines the values for the 7 bit test bus signals to be I/O on P70_IRQ, RSTOUT_N, P35,
P34 / SIC_CLK, P33_INT1, P32_INT0, P31 / UART_TX and P30 / UART_RX pins.
Table 271. CIU_TestPinValue register (address 6324h) bit allocation
Bit
Symbol
7
5
4
useio
Reset
Access
6
3
2
1
0
TestPinValue[6:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 272. Description of CIU_TestPinValue bits
Bit
Symbol
Description
7
useio
Set to logic 1, this bit enables the I/O functionality for the internal test
bus on the pins P70_IRQ (MSB), RSTOUT, P35, P34 / SIC_CLK,
P33_INT1, P32_INT0, P31 / UART_TX, P30 / UART_RX (LSB)
Note: Before using P34 / SIC_CLK as a test output, the SVDD switch
should be closed. See register address 6106h.
6 to 0
TestPinValue[6:0]
UseIO set to logic 1, Read or write the value of the test bus.
UseIO set to logic 0, Read 000_0000. No write.
8.6.23.50
CIU_TestBus register (6325h)
Shows the status of the internal test bus.
Table 273. CIU_TestBus register (address 6325h) bit allocation
Bit
7
6
5
Reset
x
x
x
x
Access
R
R
R
R
Symbol
4
3
2
1
0
x
x
x
x
R
R
R
R
TestBus[7:0]
Table 274. Description of CIU_TestBus bits
Bit
Symbol
Description
7 to 0
TestBus[7:0]
Shows the status of the internal test bus. The test bus is selected by the
register CIU_TestSel2.
See Section 8.6.21.2 “CIU test bus” on page 151.
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8.6.23.51
CIU_AutoTest register (6326h)
Controls the digital self-test.
Table 275. CIU_AutoTest register (address 6326h) bit allocation
Bit
7
6
5
4
Symbol
-
AmpRcv
-
-
3
2
1
0
SelfTest[3:0]
Reset
0
1
0
0
0
0
0
0
Access
R
R
R
R
R/W
R/W
R/W
R/W
Table 276. Description of CIU_AutoTest bits
Bit
Symbol
Description
7
-
Reserved.
6
AmpRcv
Set to logic 1 the internal signal processing in the receiver chain is
performed non-linear. This increases the operating distance in
communication modes at 106 kbit/s.
Note: Due to non linearity the effects of MinLevel and CollLevel in
CIU_RxThreshold register are as well non linear.
5 to 4 -
Reserved
3 to 0 SelfTest[3:0] Enables the digital Self Test. The self-test can be started by the Selftest
command in the CIU_Command register. The self-test is enabled by 1001.
Note: For default operation the self-test has to be disabled (0000).
8.6.23.52
CIU_Version register (6327h)
Shows the version of the CIU.
Table 277. CIU_Version register (address 6327h) bit allocation
Bit
7
Symbol
6
5
4
3
Product[3:0]
2
1
0
Version[3:0]
Reset
1
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Table 278. Description of CIU_Version bits
Bit
PN5331B3HN
Product data sheet
COMPANY PUBLIC
Symbol
Description
7 to 4 Product
Product 1000 (PN533)
3 to 0 Version
Version 0000
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8.6.23.53
CIU_AnalogTest register (6328h)
Controls the pins AUX1 and AUX2.
Table 279. CIU_AnalogTest register (address 6328h) bit allocation
Bit
7
Symbol
Reset
Access
6
5
4
3
AnalogSelAux1[3:0]
2
1
0
AnalogSelAux2[3:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 280. Description of CIU_AnalogTest bits
Bit
Symbol
Description
7 to 4
AnalogSelAux1[3:0] Controls the AUX1 pin. Note: All test signals are described in
Section 8.6.21.3 “Test signals at pin AUX” on page 152.
0000 Tristate
0001 DAC output: register CIU_TestDAC1[1]
0010 DAC output: test signal corr1[1]
0011 DAC output: test signal corr2[1]
0100 DAC output: test signal MinLevel[1]
0101 DAC output: ADC_I[1]
0110 DAC output: ADC_Q[1]
0111 DAC output: ADC_I combined with ADC_Q[1]
1000 Test signal for production test
1001 secure IC clock
1010 ErrorBusBit as described in Table 178 on page 155
1011 Low
1100 TxActive
At 106 kbit/s: High during Start bit, Data bits, Parity and
CRC
At 212 kbit/s and 424 kbit/s: High during Preamble, Sync,
Data bits and CRC
1101 RxActive
At 106 kbit/s: High during Data bits, Parity and CRC
At 212 kbit/s and 424 kbit/s: High during Data bits and CRC
1110 Subcarrier detected
At 106 kbit/s: not applicable
At 212 kbit/s and 424 kbit/s: High during last part of
preamble, Sync, Data bits and CRC.
1111 Test bus bit as defined by the TstBusBitSel in Table 266 on
page 191
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Table 280. Description of CIU_AnalogTest bits …continued
Bit
Symbol
3 to 0
AnalogSelAux2[3:0] Controls the AUX2 pin. Note: All test signals are described in
Section 8.6.21.3 “Test signals at pin AUX” on page 152.
Description
0000 Tristate
0001 DAC output: register CIU_TestDAC2[2]
0010 DAC output: test signal corr1[2]
0011 DAC output: test signal corr2[2]
0100 DAC output: test signal MinLevel[2]
0101 DAC output: ADC_I[2]
0110 DAC output: ADC_Q[2]
0111 DAC output: ADC_I combined with ADC_Q[2]
1000 Test signal for production test
1001 secure IC clock
1010 ErrorBusBit as described in Table 178 on page 155
1011 Low
1100 TxActive
At 106 kbit/s: High during Start bit, Data bits, Parity and
CRC
At 212 kbit/s and 424 kbit/s: High during Preamble, Sync,
Data bits and CRC
1101 RxActive
At 106 kbit/s: High during Data bits, Parity and CRC
At 212 kbit/s and 424 kbit/s: High during Data bits and CRC
1110 Subcarrier detected
At 106 kbit/s: not applicable
At 212 kbit/s and 424 kbit/s: High during last part of
preamble, Sync, Data bits and CRC.
1111 Test bus bit as defined by the TstBusBitSel in Table 265 on
page 191
PN5331B3HN
Product data sheet
COMPANY PUBLIC
[1]
Current output. The use of 1 k pull down resistor on AUX1 is recommended.
[2]
Current output. The use of 1 k pull down resistor on AUX2 is recommended.
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8.6.23.54
CIU_TestDAC1 register (6329h)
Defines the test value for TestDAC1.
Table 281. CIU_TestDAC1 register (address 6329h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
Reset
0
0
X
X
TestDAC1[5:0]
X
X
X
X
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Table 282. Description of CIU_TestDAC1 bits
Bit
Symbol
Description
7 to 6 -
Reserved.
5 to 0 TestDAC1[5:0] Defines the test value for TestDAC1. The output of the DAC1 can be
switched to AUX1 by setting AnalogSelAux1 to 0001 in the
CIU_AnalogTest register.
8.6.23.55
CIU_TestDAC2 register (632Ah)
Defines the test value for TestDAC2.
Table 283. CIU_TestDAC2 register (address 632Ah) bit allocation
Bit
7
6
5
4
3
Symbol
-
-
Reset
0
0
X
X
X
Access
R
R
R/W
R/W
R/W
2
1
0
X
X
X
R/W
R/W
R/W
TestDAC2[6:0]
Table 284. Description of CIU_TestDAC2 bits
8.6.23.56
Bit
Symbol
Description
7 to 6
-
Reserved.
5 to 0
TestDAC2[6:0] Defines the test value for TestDAC2. The output of the DAC2 can be
switched to AUX2 by setting AnalogSelAux2 to 0001 in the
CIU_AnalogTest register.
CIU_TestADC register (632Bh)
Shows the actual value of ADC I and Q channel.
Table 285. CIU_TestADC register (address 632Bh) bit allocation
Bit
7
Symbol
6
5
4
3
ADC_I[3:0]
2
1
0
ADC_Q[3:0]
Reset
X
X
X
X
X
X
X
X
Access
R
R
R
R
R
R
R
R
Table 286. Description of CIU_TestADC bits
PN5331B3HN
Product data sheet
COMPANY PUBLIC
Bit
Symbol
Description
7 to 4
ADC_I[3:0]
Shows the actual value of ADC I channel.
3 to 0
ADC_Q[3:0]
Shows the actual value of ADC Q channel.
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8.6.23.57
CIU_RFlevelDet register (632Fh)
Power down of the RF level detector.
Table 287. CIU_RFlevelDet register (address 632Fh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
pd_rflvldet
-
-
-
-
Reset
Access
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 288. Description of CIU_RFlevelDet bits
Bit
Symbol
Description
7 to 5 -
Reserved. These bits must be set to logic level 0.
4
Power down of the RF level detector.
pd_rfleveldet
When set to logic 1, the RF level detector is in power down mode.
3 to 0 -
PN5331B3HN
Product data sheet
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Reserved. These bits must be set to logic level 0.
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PN5331B3HN
Product data sheet
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8.7 Registers map
8.7.1 Standard registers
Table 289. Standard registers mapping
Register Register
address name
Bit7
Bit6
Bit5
Bit4
6000h to
6102h
Config I0_I1
6104h
Observe_testbus
6105h
Data_rng
6106h
Control_switch_rng
6107h
GPIRQ
int1_pol
pad_I1
pad_I0
enselif
Bit1
Bit0
Selif[1:0]
observe_ciu
data_rng
gpirq_level_P71
hide_svdd_sig
sic_switch_overload
sic_switch_en
gpirq_level_P50
gpirq_level_P35
gpirq_level_P34
gpirq_enable_P71
cpu_need_rng
random_dataready
gpirq_enable_P50
gpirq_enable_P35
gpirq_enable_P34
enoffset
soft_highspeedreg
control_highspeedreg
i2c_wu_en_wr
i2c_wu_en_rd
i2c_wu_en
Reserved
6109h
LDO
610Ah
i2c_wu_control
Reserved
overcurrent_status
sel_overcurrent[1:0]
610Bh
Reserved
Andet_control
andet_bot
andet_up
andet_ithl[1:0]
610Dh
andet_ithh[2:0]
andet_en
Reserved
NFC_WI_control
nfc_wi_status
610Fh
nfc_wi_en_act_req_im
nfc_wi_en_clk
Reserved
6200h
PCR CFR
6201h
PCR CER
6202h
PCR ILR
6203h
PCR Control
6204h
PCR Status
6205h
PCR Wakeupen
cpu_freq[1:0]
hsu_enable
porpulse_latched
enable_pdselif
gpirq_level
Reserved
int1_level
int0_level
clear_wakeup_cond
soft_reset
i2c_wu
gpirq_wu
SPI_wu
HSU_wu
CIU_wu
int1_wu
int0_wu
i2c_wu_en
GPIRQ_wu_en
SPI_on_en
HSU_on_en
CIU_wu_en
int1_en
int0_en
Reserved
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199 of 236
6301h
CIU_Mode
MSBFirst
PolSigin
ModeDetOff
6302h
CIU_TxMode
TxCRCEn
DetectSync
TxSpeed[2:0]
TXWaitRF
RxWaitRF
InvMod
TxMix
TxFraming[1:0]
6303h
CIU_RxMode
RXCRCEn
RxSpeed[2:0]
RxNoErr
RxMultiple
RxFraming[1:0]
6304h
CIU_TxControl
InvTx2RFon
InvTx1RFon
InvTx2RFoff
Tx2CW
CheckRF
6305h
CIU_TxAuto
AutoRFOFF
Force100ASK
AutoWakeUp
CAOn
InitialRFOn
6306h
CIU_TxSel
LoadModSel[1:0]
6307h
CIU_RxSel
UartSel[1:0]
6308h
CIU_RxThreshold
6309h
CIU_Demod
InvTx1RFoff
DriverSel[1:0]
Tx2RFEn
Tx1RFEn
Tx2RFAutoEn
Tx1RFAutoEn
SigOutSel[3:0]
RxWait[5:0]
MinLevel[3:0]
AddIQ[1:0]
CRCPreset[1:0]
Collevel[2:0]
FixIQ
TauRcv[1:0]
TauSync[1:0]
PN5331B3HN
6206h to
6300h
Near Field Communication (NFC) controller
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157534
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6108h
610Eh
Bit2
Reserved
6103h
610Ch
Bit3
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Register Register
address name
630Ah
CIU_FelNFC1
630Bh
CIU_FelNFC2
630Ch
CIU_MifNFC
630Dh
CIU_ManualRCV
630Eh
CIU_TypeB
Bit7
Bit6
Bit5
Bit4
Bit3
FelSyncLen[1:0]
WaitForSelected
Bit0
DataLenMax[5:0]
SensMiller[2:0]
RxSOFReq
Bit1
DataLenMin[5:0]
ShortTimeSlot
TauMiller[1:0]
MFHalted
TxWait[1:0]
FastFiltMF_SO
DelayMF_SO
ParityDisable
LargeBWPLL
ManualHPCF
HPCF[1:0]
RxEOFReq
Reserved
EOFSOFWidth
NoTxSOF
NoTxEOF
TxEGT[1:0]
630Fh to
6310h
Reserved
CIU_CRCResultMSB
6312h
CIU_CRCResultLSB
CRCResultMSB[7:0]
6313h
CIU_GsNOff
6314h
CIU_ModWidth
6315h
CIU_TxBitPhase
6316h
CIU_RFCfg
6317h
CIU_GsNOn
6318h
CIU_CWGsP
6319h
CIU_ModGsP
631Ah
CIU_TMode
631Bh
CIU_TPrescaler
TPrescaler_LO[7:0]
631Ch
CIU_TReloadVal_Hi
TReloadVal_Hi[7:0]
631Dh
CIU_TReloadVal_Lo
TReloadVal_Lo[7:0]
631Eh
CIU_TCounterVal_hi
TCounterVal_Hi[7:0]
631Fh
CIU_TCounterVal_lo
CRCResultLSB[7:0]
CWGsNOff[3:0]
ModGsNOff[3:0]
ModWidth[7:0]
RcvClkChange
TxBitPhase[6:0]
RFLevelAmp
RxGain[2:0]
RFLevel[3:0]
CWGsNOn[3:0]
ModGsNOn[3:0]
Reserved
CWGsP[5:0]
Reserved
ModGsP[5:0]
TAuto
TGated[1:0]
TAutoRestart
TPrescaler_Hi[3:0]
TCounterVal_LO[7:0]
6320h
Reserved
6321h
CIU_TestSel1
6322h
CIU_TestSel2
CIU_TestPinEn
6324h
CIU_TestPinValue
SICclksel[1:0]
PRBS9
SICClkD1
TstBusBitSel[2:0]
PRBS15
TstBusSel[4:0]
TestPinEn[7:0]
useio
TestPinValue[6:0]
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6325h
CIU_TestBus
6326h
CIU_AutoTest
TestBus[7:0]
6327h
CIU_Version
6328h
CIU_AnalogTest
6329h
CIU_TestDAC1
Reserved
632Ah
CIU_TestDAC2
Reserved
632Bh
CIU_TestADC
Reserved
AmpRcv
Reserved
SelfTest[3:0]
Product
Version
AnalogSelAux1[3:0]
AnalogSelAux2[3:0]
TestDAC1[5:0]
TestDAC2[5:0]
ADC_I[3:0]
ADC_Q[3:0]
Reserved
PN5331B3HN
6323h
LoadModTst[1:0]
TstBusFlip
Near Field Communication (NFC) controller
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157534
6311h
632Ch to
632Eh
Bit2
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Product data sheet
COMPANY PUBLIC
Table 289. Standard registers mapping …continued
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Register Register
address name
632Fh
CIU_RFlevelDet
6330h
SIC_CLK
6331h
CIU_Command
6332h
CIU_CommIEn
6333h
CIU_DivIEn
6334h
CIU_CommIrq
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Reserved
Set1
Errorbusbitenable
TxIEn
Power-down
RXIEn
IdleIEn
HiAlertIEn
LoAlertIEn
ErrIEn
SiginAct IEn
ModeIEn
CRCIEn
RfOnIEn
RfOffIEn
IdleIrq
HiAltertIRq
LoAlertIRq
ErrIRq
TimerIRq
SiginActIrq
ModeIRq
CRCIRq
RfOnIRq
RfOffIRq
BufferOvfl
CollErr
CRCErr
ParityErr
ProtocollErr
RFOn
HiAlert
LoAlert
TxIRq
RxIRq
Command
Set2
WrErr
TempErr
RFErr
6337h
CIU_Status1
CIU_IRQ_1
CRCOk
CRCReady
CIU_IRQ_0
TRunning
6338h
CIU_Status2
TempSensClear
RFFreqOK
TgActivated
MFCrypto1On
6339h
CIU_FIFOData
633Ah
CIU_FIFOLevel
633Bh
CIU_WaterLevel
633Ch
CIU_Control
CIU_BitFraming
633Fh to
FFFFh
TimerIEn
ModemState[2:0]
FIFOData[7:0]
FlushBuffer
FIFOLevel[6:0]
WaterLevel[5:0]
TStopNow
TStartNow
WrNFCIP-1IDtoFIF
O
Reserved
CollPosNotValid
StartSend
ValuesAfterColl
Initiator
RxLastBits[2:0]
RxAlign[2:0]
TxLastBits[2:0]
CollPos
Reserved
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CIU_DivIrq
CIU_Error
CIU_Coll
Errorbusbitsel[2:0]
RcvOff
6336h
633Eh
Bit0
pd_rfleveldet
sic_clk_p34_en
6335h
633Dh
Bit1
NXP Semiconductors
PN5331B3HN
Product data sheet
COMPANY PUBLIC
Table 289. Standard registers mapping …continued
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NXP Semiconductors
PN5331B3HN
Product data sheet
COMPANY PUBLIC
8.7.2 SFR registers
Table 290. SFR registers mapping
SFR
address
80h
81h[1]
82h[1]
83h[1]
Register name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
CPU_PD
Reserved
Reserved
SP Stack Pointer
SP[7:0]
DPL Data Pointer Low
DPL[7:0]
DPH Data Pointer High
DPLH7:0]
84h to 86h
Reserved
PCON
SMOD
88h
T01CON
TF1
TR1
TF0
TR0
Reserved
IE1
IT1
IE0
IT0
89h
T01MOD
GATE1
C/T1
M11
M10
GATE0
C/T0
M01
M00
8Ah
T0L
T0L.7
T0L.6
T0L.5
T0L.4
T0L.3
T0L.2
T0L.1
T0L.0
8Bh
T1L
T1L.7
T1L.6
T1L.5
T1L.4
T1L.3
T1L.2
T1L.1
T1L.0
8Ch
T0H
T0H.7
T0H.6
T0H.5
T0H.4
T0H.3
T0H.2
T0H.1
T0H.0
8Dh
T1H
T1H.7
T1H.6
T1H.5
T1H.4
T1H.3
T1H.2
T1H.1
T1H.0
SM0
SM1
SM2
TB8
RB8
TI
RI
8Eh to 97h
Reserved
98h
S0CON
99h
S0BUF
9Ah
RWL
9Bh
TWL
9Ch
FIFOFS
REN
S0BUF[7:0]
RWaterlevel[7:0]
TWaterlevel[7:0]
TransmitFreespace[7:0]
9Dh
FIFOFF
9Eh
SFF
FIFO_EN
Reserved
TWLL
TFF
TFE
RWLH
RFF
RFE
9Fh
FIT
Reset
Reserved
WCOL_IRQ
TWLL_IRQ
TFF_IRQ
RWLH_IRQ
ROVR_IRQ
RFF_IRQ
A0h
Reserved
TFLUSH
RFLUSH
EN_WCOL_IRQ
EN_TWLL_IRQ
EN_TFF_ IRQ
EN_RWLH_IRQ
EN_ROVR_IRQ
EN_RFF_ IRQ
FITEN
A2h
FDATA
A3h
FSIZE
FDATA[7:0]
ReceiveSize[7:0]
A4h to A7h
Reserved
202 of 236
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A8h
IE0
A9h
SPIcontrol
IE0_7
IE0_6
Reserved
IE0_5
IE0_4
IE0_3
IE0_2
IE0_1
IE0_0
Enable
Reserved
CPHA
CPOL
IE1
IE0
TR_FE
RCV_OVR
Reserved
READY
disable_preamb
irq_rx_over_en
irq_rx_fer_en
irq_rx_over
irq_rx_fer
rx_stopbit
tx_en
rx_en
soft_reset_n
AAh
SPIstatus
ABh
HSU_STA
set_bit
Reserved
ACh
HSU_CTR
hsu_wu_en
ADh
HSU_PRE
hsu_prescaler[7:0]
AEh
HSU_CNT
hsu_counter[7:0]
Reserved
start_frame
tx_stopbit[1:0]
PN5331B3HN
A1h
ReceiveFullness[7:0]
Near Field Communication (NFC) controller
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87h
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SFR
address
Register name
Bit7
Bit6
Bit5
AFh
B0h
Bit3
Bit2
Bit1
Bit0
P3[3]
P3[2]
P3[1]
P3[0]
IP0_3
IP0_2
IP0_1
IP0_0
TCLK0
Reserved
TR2
C/T2
CP/RL2
Reserved
P3
Reserved
P3[5]
B1h to B7h
B8h
Bit4
NXP Semiconductors
PN5331B3HN
Product data sheet
COMPANY PUBLIC
Table 290. SFR registers mapping …continued
P3[4]
Reserved
IP0
IP0_7
IP0_6
IP0_5
B9h to C7h
IP0_4
Reserved
C8h
T2CON
Reserved
C9h
T2MOD
CAh
RCLK0
RCAP2L
R2L.7
R2L.6
R2L.5
R2L.4
R2L.3
R2L.2
R2L.1
R2L.0
CBh
RCAP2H
R2H.7
R2H.6
R2H.5
R2H.4
R2H.3
R2H.2
R2H.1
R2H.0
CCh
T2L
T2L.7
T2L.6
T2L.5
T2L.4
T2L.3
T2L.2
T2L.1
T2L.0
CDh
T2H
T2H.7
T2H.6
T2H.5
T2H.4
T2H.3
T2H.2
T2H.1
T2H.0
TimerIEn
Reserved
CEh to CFh
D0h[1]
PSW Program Status Word
D1h
CIU_Command
D2h
CIU_CommIEn
D3h
CIU_DivIEn
D4h
CIU_CommIrq
Set1
D5h
CIU_DivIrq
Set2
WrErr
TempErr
CR[2]
ENS1
T2RD
DCEN
Reserved
PSW[7:0]
Reserved
RcvOff
TxIEn
RXIEn
Command
IdleIEn
HiAlertIEn
LoAlertIEn
ErrIEn
SiginAct IEn
ModeIEn
CRCIEn
RfOnIEn
RfOffIEn
IdleIrq
HiAltertIRq
LoAlertIRq
ErrIRq
TimerIRq
SiginActIrq
ModeIRq
CRCIRq
RfOnIRq
RfOffIRq
RFErr
BufferOvfl
CollErr
CRCErr
ParityErr
ProtocollErr
STA
STO
SI
AA
Reserved
TxIRq
Power-down
RxIRq
Reserved
D6h
CIU_Error
D7h
Reserved
D8h
I2CCON
D9h
I2CSTA
ST[7:0]
DAh
I2CDAT
I2CDAT[7:0]
DBh
I2CADR
CR[1:0]
SA[6:0]
DCh to DEh
GC
Reserved
CIU_Status1
E1h to E7h
Reserved
ACC Accumulator
203 of 236
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E8h
IE1
E9h
CIU_Status2
CIU_IRQ_1
CRCOk
CRCReady
CIU_IRQ_0
TRunning
RFOn
IE1_2
HiAlert
LoAlert
Reserved
IE1_0
ACC[7:0]
IE1_7
Reserved
IE1_5
IE1_4
IE1_3
TempSensClear
Reserved
RFFreqOK
TgActivated
MFCrypto1On
EAh
CIU_FIFOData
EBh
CIU_FIFOLevel
ECh
CIU_WaterLevel
EDh
CIU_Control
TStopNow
EEh
CIU_BitFraming
StartSend
ModemState[2:0]
FIFOData[7:0]
FlushBuffer
FIFOLevel[6:0]
WaterLevel[5:0]
TStartNow
WrNFCIP-1ID to
FIFO
RxAlign[2:0]
Initiator
Reserved
RxLastBits[2:0]
Reserved
TxLastBits[2:0]
PN5331B3HN
DFh
E0h[1]
Near Field Communication (NFC) controller
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SFR
address
EFh
F0h[1]
Register name
CIU_Coll
Bit7
ValuesAfterColl
Bit6
Bit5
Bit4
Bit3
CollPosNotValid
Bit2
Bit1
Bit0
CollPos
B register
B[7:0]
F1h to F3h
Reserved
F4h
P7FGA
P7CFGA[2]
P7CFGA[1]
P7CFGA[0]
F5h
P7FGB
P7CFGB[2]
P7CFGB[1]
P7CFGB[0]
F6h
Reserved
F7h
P7
P7[2]
P7[1]
P7[0]
F8h
IP1
IP1_7
IP1_5
F9h
IP1_4
IP1_3
IP1_2
Reserved
FAh[1]
XRAMP
XRAMP[4:0]
Reserved
FCh
P3FGA
P3CFGA[5]
P3CFGA[4]
P3CFGA[3]
P3CFGA[2]
P3CFGA[1]
P3CFGA[0]
FDh
P3FGB
P3CFGB[5]
P3CFGB[4]
P3CFGB[3]
P3CFGB[2]
P3CFGB[1]
P3CFGB[0]
FEh to FFh
Reserved
This register is not described in this document as it is a standard 80C51 register.
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FBh
[1]
NXP Semiconductors
PN5331B3HN
Product data sheet
COMPANY PUBLIC
Table 290. SFR registers mapping …continued
PN5331B3HN
NXP Semiconductors
Near Field Communication (NFC) controller
9. Limiting values
Table 291. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
PN5331B3HN
Product data sheet
COMPANY PUBLIC
Min
Max
Unit
PVDD,
SVDD,
TVDD,
AVDD,
DVDD
Supply Voltages
Conditions
-0.5
4
V
VBUS
USB Supply Voltage
-0.5
5.5
V
Ptot
Total power dissipation
608
mW
ISVDD
Maximum current in SVDD switch
30
mA
VINRX
Dynamic RX Input voltage Range
input signal at
13.56 MHz
-0.7
AVDD+1
V
VINTX1,
VINTX2
DynamicTX1 input Voltage Range
input signal at
13.56 MHz
-1.2
TVDD+1.3 V
ITX1,
ITX2
Maximum current in transmitter TX1
input signal at
13.56 MHz
-300
300
mA
VESD
Electrostatic discharge voltage
VESDH
ESD Susceptibility (Human Body
model)
EIA/JESD22-A114-E
2.0
kV
VESDM
ESD Susceptibility (Machine model)
EIA/JESD22-A115-A
200
V
VESDC
ESD Susceptibility (Charge Device
model)
EIA/JESD22-C101-C
1.0
kV
Tstg
Storage temperature
-55
150
C
Tj
Junction temperature
-40
100
C
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10. Recommended operating conditions
Table 292. Operating conditions
Symbol
Parameter
Conditions
Tamb
Ambient Temperature
USB Supply Voltage
VSS = 0 V
Supply Voltage (Non USB
mode)
VBUS =DVDD
VSS = 0 V
TVDD,
AVDD,
DVDD
Supply Voltages
TVDD =
AVDD= DVDD
VSS = 0 V
PVDD
Supply Voltage for host
interface
VSS = 0 V
VBUS
Min
Typ
Max
Unit
-30
+25
+85
C
4.02
5
5.25
V
2.5
3.3
3.6
V
[2][3]
2.5
3.3
3.6
V
[3]
1.6
1.8 to 3.3 3.6
V
[1]
[1]
VSS represents DVSS, TVSS1, TVSS2, AVSS.
[2]
AVSS, DVDD and TVDD shall always be on the same voltage level.
[3]
Supply voltage of AVSS, DVDD and TVDD below 3 V reduces the performance (e.g. the achievable operating
distance).
11. Thermal characteristics
Table 293. Thermal characteristics
Symbol Parameter
Rthj-a
PN5331B3HN
Product data sheet
COMPANY PUBLIC
Conditions
thermal resistance
from junction to ambient
in free air
with exposed pad soldered on a
4 layer Jedec PCB-0.5
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157534
Min Typ Max Unit
37
41.1 K/W
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12. Characteristics
Unless otherwise specified, the limits are given for the full operating conditions. The
typical value is given for 25C, DVDD = 3.4 V and PVDD = 3 V in non USB bus power
mode, VBUS = 5 V in USB power mode.
Timings are only given from characterization results.
12.1 Power management characteristics
12.1.1 Current consumption characteristics
Table 294. Current consumption characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
1.3
10
A
IHPD
Hard-Power-down current
(Not powered from USB)
AVDD = DVDD = TVDD =
PVDD = 3 V, RF level
detector off
[5]
ISPD
Soft-Power-down current
(Not powered from USB)
AVDD = DVDD = TVDD =
PVDD = 3 V,
SVDD = 0 V, RF level
detector on
[5]
9
30
A
Isuspend
USB suspend current
VBUS = 5 V,
AVDD = DVDD = TVDD =
PVDD = 3 V, SVDD = 3 V,
PVDD = 3 V
RF level detector on
(without resistor on D)
[5]
120
250
A
IDVDD
Digital supply current
AVDD = DVDD = TVDD =
PVDD = 3 V,
RF level detector on
12
IAVDD
Analog supply current
AVDD = DVDD = TVDD =
PVDD = 3 V,
RF level detector on
3
6
mA
AVDD = DVDD = TVDD =
PVDD = 3 V,
RF level detector off
1.5
5
mA
IAVDDrcvoff
IPVDD
ISVDD
ITVDD
Pad supply current
[2]
30
mA
Output supply current
sam_switch_en set to 1
[3]
30
mA
Continuous wave,
TVDD = 3 V
[1][4]
100
mA
Transmitter supply current
[1]
ITVDD depends on TVDD and the external circuitry connected to Tx1 and Tx2.
[2]
IPVDD depends on the overall load at the digital pins.
[3]
ISVDD depends on the overall load on SVDD pad.
[4]
During operation with a typical circuitry the overall current is below 100 mA.
[5]
ISPD and IHPD are the total currents over all supplies.
60
Typical value using a complementary driver configuration and an antenna matched to
40 between TX1 and TX2 at 13.56 MHz.
PN5331B3HN
Product data sheet
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12.1.2 Voltage regulator characteristics
Table 295. Voltage regulator characteristics
Symbol Parameter
Conditions
Min Typ
Max Unit
VBUS
USB Supply voltage (USB
mode)
VSS = 0 V
4.02 5
5.25 V
DVDD
Supply voltage after Inrush
current limitation (USB mode)
From IDVDD = 0 to
IDVDD = 150 mA
2.95 3.3
3.6
V
IVBUS
Maximum load current (USB
mode)
measured on VBUS
150
mA
Maximum Inrush current
limitation
At power-up
(curlimofff = 0)
100
mA
Vth1
Reset threshold on DVDD falling
Vhys
Vth1 hysteresis
Cdec
DVDD decoupling capacitor
1.90 2.15 2.40 V
[2]
35
60
8
10
85
mV
F
[1]
The internal regulator is only enabled when the USB interface is selected by I0 and I1.
[2]
For more details on Implementation of decoupling capacitor refer to Figure 30, Figure 31 and Figure 32 in
“Power distribution section”.
12.2 Antenna presence self test thresholds
The following values are guaranteed by design. Only functional is done in production for
cases andet_ithl[1:0]=10b and for andet_ithh[2:0]=011b.
Table 296. Antenna presence detection lower levels characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
IAndetH
IDVDD lower current threshold for
antenna presence detection
andet_ithl[1:0] = 00b
5
mA
andet_ithl[1:0] = 01b
15
mA
andet_ithl[1:0] = 10b
25
mA
andet_ithl[1:0] = 11b
35
mA
Table 297. Antenna Presence Detection Upper Levels characteristics
PN5331B3HN
Product data sheet
COMPANY PUBLIC
Symbol
Parameter
Conditions
IAndetH
IDVDD upper current threshold for
antenna presence detection
andet_ithh[2:0] = 000b
45
mA
andet_ithh[2:0] = 001b
60
mA
andet_ithh[2:0] = 010b
75
mA
andet_ithh[2:0] = 011b
90
mA
andet_ithh[2:0] = 100b
105
mA
andet_ithh[2:0] = 101b
120
mA
andet_ithh[2:0] = 110b
135
mA
andet_ithh[2:0] = 111b
150
mA
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12.3 Typical 27.12 MHz Crystal requirements
Table 298. Crystal requirements
Symbol Parameter
Conditions
fXTAL
XTAL frequency
ESR
Equivalent series resistance
CLOAD
Load capacitance
PXTAL
Drive level
Min
Typ
Max
Unit
27.107
27.12
27.133
MHz
100
10
pF
W
100
12.4 Pin characteristics for 27.12 MHz XTAL Oscillator (OSCIN, OSCOUT)
Table 299. Pin characteristics for 27.12 MHz XTAL Oscillator (OSCIN, OSCOUT)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ILeakOSCIN
Input Leakage current
RSTPD_N = 0 V
VIHOSCIN
High level Input voltage
-1
1
mA
0.7AVDD
AVDD
V
VILOSCIN
Low level Input voltage
0
0.3AVDD V
DCOSCIN
DC input voltage
CinOSCIN
OSCIN Input
Capacitance
0.65
V
2
pF
VOHOSCOUT High level output
voltage
1.1
V
VOLOSCOUT Low level output
voltage
0.2
V
2
pF
AVDD = 2.8 V,
VDC = 0.65 V,
VAC = 1 Vpp
CinOSCOUT
Input Capacitance
fOSCIN
Clock Frequency
-500 ppm 27.12 +500 ppm MHZ
DFEC
Duty Cycle of Clock
Frequency
40
NfloorCLK
Clock phase noise floor
Clock phase noise
corner
NFCCLK
[1]
NfloorCLK =
-140dBc/Hz;
-20dB/decade
slope
50
60
%
[1]
-140
dBc/Hz
[1]
50
kHz
NFCLK and NCCLK define the mask for maximum acceptable phase noise of the clock signal at the
OSCIN, OSCOUT inputs. See Figure 59 “27.12 MHz input clock phase noise spectrum mask”.
phase noise (dBc/Hz)
-20dB/decade
Acceptable phase noise area
NfloorCLK
NFCCLK
frequency (Hz)
Fig 59. 27.12 MHz input clock phase noise spectrum mask
PN5331B3HN
Product data sheet
COMPANY PUBLIC
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12.5 RSTPD_N input pin characteristics
Table 300. RSTPD_N input pin characteristics
Symbol Parameter
Conditions
Min
Typ Max
Unit
VIH
High level input voltage
PVDD -0.4
PVDD V
VIL
Low level input voltage
0
0.4
V
IIH
High level input current VI = PVDD
-1
1
A
IIL
Low level input current
-1
1
A
Cin
Input capacitance
VI = 0 V
2.5
pF
12.6 Input pin characteristics for I0, I1 and TESTEN
Table 301. Input pin characteristics for I0, I1 and TESTEN
Symbol
Parameter
VIH
High level input voltage
[1]
0.7 DVDD
DVDD
V
Low level input voltage
[2]
0
0.3 DVDD
V
IIH
High level input current
I0 and I1
VI = DVDD
[3]
-1
1
A
IIL
Low level input current
VI = 0 V
-1
1
A
Cin
Input capacitance
VIL
PN5331B3HN
Product data sheet
COMPANY PUBLIC
Conditions
Min
Typ Max
2.5
Unit
pF
[1]
To minimize power consumption when in Soft-Power-down mode, the limit is DVDD - 0.4 V.
[2]
To minimize power consumption when in Soft-Power-down mode, the limit is 0.4 V.
[3]
TESTEN should never be set to high level in the application. It is used for production test purpose only. It is
recommended to connect TESTEN to ground although there is a pull-down included.
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12.7 RSTOUT_N output pin characteristics
Table 302. RSTOUT_N output pin characteristics
Symbol Parameter
VOH
High level output voltage
Conditions
Min
PVDD = 3 V,
IOH = -4 mA
PVDD = 1.8 V,
IOH= -2 mA
Low level output voltage
VOL
High level output current
IOH
[2]
PVDD = 3 V,
IOL = 4 mA
Low level output current
Max
Unit
0.7 PVDD
PVDD
V
0.7 PVDD
PVDD
V
0
0.3 PVDD V
0.3 PVDD V
PVDD = 1.8 V,
IOL = 2 mA
[2]
0
PVDD = 3 V,
VOH = 0.8 PVDD
[3]
-4
mA
-2
mA
4
mA
2
mA
PVDD = 1.8 V,
VOH= 0.7 PVDD
IOL
PVDD = 3 V,
VOL = 0.2 PVDD
[3]
PVDD = 1.8 V,
VOL = 0.3 PVDD
Load capacitance
Cout
trise,fall
Rise and fall times
PVDD = 3 V,
VOH = 0.8 PVDD,
VOL = 0.2 PVDD,
Cout = 30 pF
[1]
PVDD = 1.8 V,
VOH = 0.7 PVDD,
VOL = 0.3 PVDD,
Cout = 30 pF
[1]
PN5331B3HN
Product data sheet
COMPANY PUBLIC
Typ
30
pF
13.5
ns
10.8
ns
IOH and IOL give the output drive capability from which the rise and fall times may be calculated as a
function of the load capacitance.
[2]
Data at PVDD= 1.8V are only given from characterization results.
[3]
The IOH and IOL give the output driving capability and allow to calculate directly the rise and fall time as
function of the load capacitance
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12.8 Input/output characteristics for pin P70_IRQ
Table 303. Input/output pin characteristics for pin P70_IRQ
Symbol Parameter
Conditions
Unit
0.7 PVDD
PVDD
VIL
Low level input voltage
[2]
0
0.3 PVDD V
VOH
Push-pull mode high
level output voltage
0.7 PVDD
PVDD
V
0.7 PVDD
PVDD
V
0
0.3 PVDD V
0
0.3 PVDD V
PVDD = 3 V,
IOH = -4 mA
PVDD = 1.8 V,
IOH = -2 mA
Push-pull mode low
level output voltage
VOL
[3]
PVDD = 3 V,
IOL = 4 mA
PVDD = 1.8 V,
IOL = 2 mA
Product data sheet
COMPANY PUBLIC
Typ Max
High level input voltage
VIH
PN5331B3HN
Min
[1]
[3]
V
IIH
Input mode high level
input current
VI = DVDD
-1
1
A
IIL
Input mode low level
input current
VI = 0 V
-1
1
A
IOH
High level output
current
PVDD = 3 V,
VOH = 0.8 PVDD
[4]
-4
mA
IOL
Low level output current PVDD = 3 V,
VOL = 0.2 PVDD
[4]
4
mA
ILeak
Input leakage current
Cin
Input capacitance
Cout
Load capacitance
trise,fall
Rise and fall times
RSTPD_N = 0.4 V
-1
1
2.5
A
pF
30
pF
PVDD = 3 V,
VOH = 0.8 PVDD,
VOL = 0.2 PVDD,
Cout= 30 pF
13.5
ns
PVDD = 1.8 V,
VOH = 0.7 PVDD,
VOL = 0.3 PVDD,
Cout = 30 pF
10.8
ns
[1]
To minimize power consumption when in Soft-Power-down mode, the limit is PVDD - 0.4 V.
[2]
To minimize power consumption when in Soft-Power-down mode, the limit is 0.4 V.
[3]
Data at PVDD = 1.8 V are only given from characterization results.
[4]
The IOH and IOL give the output driving capability and allow to calculate directly the rise and fall time as
function of the load capacitance.
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12.9 Input/output pin characteristics for P30 / UART_RX, P31 / UART_TX,
P32_INT0, P33_INT1
Table 304. Input/output pin characteristics for P30 / UART_RX, P31 / UART_TX, P32_INT0,
P33_INT1
Symbol Parameter
Conditions
Unit
0.7 PVDD
PVDD
VIL
Low level input voltage
[2]
0
0.3 PVDD V
VOH
Push-pull mode high
level output voltage
PVDD - 0.4
PVDD
V
PVDD - 0.4
PVDD
V
0
0.4
V
0
0.4
V
PVDD = 3 V,
IOH = -4 mA
[3]
Push-pull mode low level PVDD = 3 V,
output voltage
IOL = 4 mA
VOL
PVDD = 1.8 V,
IOL = 2 mA
Product data sheet
COMPANY PUBLIC
Typ Max
[1]
PVDD = 1.8 V,
IOH = -2 mA
PN5331B3HN
Min
High level input voltage
VIH
[3]
V
IIH
Input mode high level
input current
VI = PVDD
-1
1
A
IIL
Input mode low level
input current
VI = 0 V
-1
1
A
IOH
High level output current PVDD = 3 V,
VOH = 0.8 PVDD
[4]
-4
mA
IOL
Low level output current
PVDD = 3 V,
VOL = 0.2 PVDD
[4]
4
mA
ILeak
Input leakage current
RSTPD_N = 0.4 V
Cin
Input capacitance
Cout
Load capacitance
trise,fall
Rise and fall times
-1
1
2.5
A
pF
30
pF
PVDD = 3 V,
VOH = 0.8 PVDD,
VOL = 0.2 PVDD,
Cout = 30 pF
13.5
ns
PVDD = 1.8 V,
VOH = 0.7 PVDD,
VOL = 0.3 PVDD,
Cout = 30 pF
10.8
ns
[1]
To minimize power consumption when in Soft-Power-down mode, the limit is PVDD - 0.4 V.
[2]
To minimize power consumption when in Soft-Power-down mode, the limit is 0.4 V
[3]
Data at PVDD = 1.8 V are only given from characterization results.
[4]
The IOH and IOL give the output driving capability and allow to calculate directly the rise and fall time as
function of the load capacitance.
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12.10 Input/output pin characteristics for P35
Table 305. Input/output pin characteristics for P35
Symbol Parameter
Typ Max
Unit
High level Input voltage
0.7 DVDD
DVDD
VIL
Low level Input voltage
[2]
0
0.3 DVDD V
VOH
High level output voltage
DVDD = 3 V,
IOH = -4 mA
DVDD - 0.4
DVDD
V
VOL
Low level output voltage
DVDD = 3 V,
IOL = 4 mA
0
0.4
V
IIH
High level input current
VI = DVDD
-1
1
A
IIL
Low level input current
VI = 0 V
-1
1
A
IOH
High level output current
DVDD = 3 V,
VOH = 0.8 PVDD
[4]
IOL
Low level output current
DVDD = 3 V,
VOL = 0.2 PVDD
[4]
ILeak
Input leakage current
RSTPD_N = 0.4 V
Cin
Input Capacitance
Cout
Load Capacitance
trise,fall
Rise and fall times
[1]
Product data sheet
COMPANY PUBLIC
Min
[1]
VIH
PN5331B3HN
Conditions
V
-4
mA
4
mA
-1
1
2.5
DVDD = 3 V,
VOH = DVDD - 0.4,
VOL = 0.4,
Cou t = 30 pF
A
pF
30
pF
16.5
nS
To minimize power consumption when in Soft-Power-down mode, the limit is DVDD - 0.4 V.
[2]
To minimize power consumption when in Soft-Power-down mode, the limit is 0.4 V.
[3]
The IOH and IOL give the output driving capability and allow to calculate directly the rise and fall time as
function of the load capacitance.
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12.11 Input/output pin characteristics for DP and DM
Table 306. Input/output pin characteristics for DP and DM for USB interface
Symbol Parameter
Conditions
High level input voltage
VIH
Min
PVDD = 3.3 V
[1]
Unit
2
3.6
V
0
0.8
V
Low level input voltage
VOH
High level output voltage
PVDD = 3.3 V,
RPD = 1.5 to VSS
2.8
PVDD
V
VOL
Low level output voltage
PVDD = 3.3 V,
RPD = 1.5 to PVDD
0
0.3
V
IOH
High level output current
PVDD = 3.3 V,
VOH = 0.8 PVDD
Low level output current
IOL
PVDD = 3.3 V,
VOL = 0.2 PVDD
PVDD = 1.8 V,
VOL = 0.3 PVDD
[2]
[2]
-4
mA
-2
mA
4
mA
2
mA
IIH
High level input current
VI = PVDD
1
A
IIL
Low level input current
VI = 0 V
1
A
ILeak
Input leakage current
RSTPD_N = 0 V
1
A
Cin
Input capacitance
3.5
pF
Zinp
Input Impedance exclusive of
pullup/pulldown (for low/full
speed)
300
ZDRV
Driver output resistance
28
TFDRATE Full-speed Data rate
-1
2.5
k
44
11.97
12.03
Mb/s
source Jitter total (including
frequency tolerance) to next
transition for paired transition
-3.5
3.5
ns
-4
4
ns
TFDEOP
Source Jitter for differential
transition to SE0 transition
-2
5
ns
TJR1
Receiver Jitter: to next
transition for paired
transitions
-18.5
18.5
ns
-9
9
ns
TFEOPT
Source SE0 interval of EOP
160
175
ns
TFEOPR
Receiver SE0 interval of EOP
82
TFST
Width of SE0 interval during
differential transition
TDJ1
TDJ2
TJR2
Product data sheet
COMPANY PUBLIC
Max
VIL
PVDD = 1.8 V,
VOH = 0.7 PVDD
PN5331B3HN
Typ
ns
14
ns
[1]
The value doesn’t guaranty the power down consumptions. To reach the specified power down
consumptions, the limit is 0.4 V.
[2]
The IOH and IOL give the output driving capability and allow to calculate directly the rise and fall time as
function of the load capacitance.
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Table 307. USB DP/DM differential receiver input levels
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDI
differential input
sensitivity
-
0.2
-
-
V
VCM
differential common
mode voltage
-
0.8
-
2.5
V
Table 308. USB DP/DM driver characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tFR
rise time
CL = 50 pF;
10% to 90% of
[VOH - VOL]
4
-
20
ns
tFF
fall time
CL = 50 pF;
10% to 90% of
[VOH - VOL]
4
-
20
ns
FRFM
differential rise/fall
excluding the first
time matching (tFR/tFF) transition from Idle
state
90
-
111.1
%
VCRS
output signal
crossover voltage
1.3
-
2.0
V
excluding the first
transition from Idle
state
Level 1
+400mV differential
Point 3
Point 4
Point 1
Point 2
Point 5
0V differential
Point 6
-400mV differential
Level 2
0%
Unit interval
100%
Fig 60. Transmit waveform at DP/DM
PN5331B3HN
Product data sheet
COMPANY PUBLIC
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Table 309. Input Pin characteristics for DP for HSU interface
Symbol Parameter
Conditions
Min
Typ
Max
Unit
0.7 PVDD
PVDD
V
0
0.3 PVDD V
VIH
High level Input
voltage
[1]
VIL
Low level Input
voltage
[2]
IIH
High level input
current
Vi = PVDD
1
mA
IIL
Low level input
current
Vi = 0 V
1
mA
ILeak
Input Leakage
current
RSTPD_N = 0 V
1
mA
Cin
Input Capacitance
3.5
pF
-1
2.5
[1]
The value doesn’t guaranty the power down consumptions. To reach the specified power down
consumptions, the limit is PVDD - 0.4 V.
[2]
The value doesn’t guaranty the power down consumptions. To reach the specified power down
consumptions, the limit is 0.4 V.
Table 310. Output Pin characteristics for DM for HSU interface
Symbol
Parameter
Conditions
Min
VOH
High level output
voltage
PVDD = 3 V,
IOH = -4 mA
Low level output
voltage
VOL
High level output
current
IOH
Max
Unit
PVDD -0.4
PVDD
V
PVDD = 1.8 V,
IOH = -2 mA
PVDD -0.4
PVDD
V
PVDD = 3 V,
IOL = -4 mA
0
0.4
V
PVDD = 1.8 V,
IOL = -2 mA
0
0.4
V
PVDD = 3 V,
VOH = 0.8 PVDD
[1]
-4
mA
-2
mA
4
mA
PVDD = 1.8 V,
VOL = 0.3 PVDD
2
mA
RSTPD_N = 0 V
-1
PVDD = 1.8 V,
VOH = 0.7 PVDD
IOL
Low level output
current
ILeak
Input leakage
current
Cout
Load Capacitance
trise,fall
Rise and fall time
PVDD = 3.3 V,
VOL = 0.2 PVDD
PVDD = 3 V,
VOH = 0.8 PVDD,
VOL = 0.2 PVDD,
Cout = 30 pF
[1]
[1]
PVDD = 1.8 V,
VOH = 0.7 PVDD,
VOL = 0.3 PVDD,
Cout = 30 pF
[1]
PN5331B3HN
Product data sheet
COMPANY PUBLIC
Typ
1
mA
30
pF
13.5
nS
10.8
nS
The IOH and IOL give the output driving capability and allow to calculate directly the rise and fall time as
function of the load capacitance
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12.12 Input pin characteristics for SCL
Table 311. Input/output drain output pin characteristics for SCL I2C interface
Symbol Parameter
Conditions
Min
Typ Max
Unit
High level Input voltage
[1]
0.7 PVDD
DVDD
VIL
Low level Input voltage
[2]
0
0.3 DVDD V
VOL
Low level output voltage
DVDD = 3 V,
IOL = -4 mA
0
0.3
V
IIH
High level input current
VI = DVDD
-1
1
A
IIL
Low level input current
VI = 0 V
-1
1
A
ILeak
Input leakage current
RSTPD_N = 0.4 V
-1
Cin
Input Capacitance
Cout
Load Capacitance
VIH
tr
tf
[1]
1
2.5
Rise time SCL
[3]
Fall time SCL
[3]
V
A
pF
30
pF
20
300
ns
20
300
ns
To minimize power consumption when in Soft-Power-down mode, the limit is DVDD - 0.4 V.
[2]
To minimize power consumption when in Soft-Power-down mode, the limit is 0.4 V.
[3]
The PN533 has a slope control according to the I2C specification for the Fast mode. The slope control is
always present and not dependant of the I2C speed.
12.13 Input/output pin characteristics for SDA
Table 312. Input/output pin characteristics for SDA I2C interface
Symbol Parameter
Typ Max
Unit
0.7 PVDD
DVDD
VIL
Low level Input voltage
[2]
0
0.3 DVDD V
VOL
Low level output voltage
DVDD = 3 V,
IOL = -4 mA
0
0.3
V
IIH
High level input current
VI = DVDD
-1
1
A
IIL
Low level input current
VI = 0 V
-1
1
A
ILeak
Input leakage current
RSTPD_N = 0.4 V
-1
1
A
Cin
Input Capacitance
Cout
Load Capacitance
tf
[1]
Product data sheet
COMPANY PUBLIC
Min
[1]
tr
PN5331B3HN
Conditions
High level Input voltage
VIH
2.5
V
pF
30
pF
Rise time SDA
[3]
20
300
ns
Fall time SDA
[3]
20
300
ns
To minimize power consumption when in Soft-Power-down mode, the limit is DVDD - 0.4 V.
[2]
To minimize power consumption when in Soft-Power-down mode, the limit is 0.4 V.
[3]
The PN533 has a slope control according to the I2C specification for the Fast mode. The slope control is
always present and not dependant of the I2C speed.
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12.14 Output pin characteristics for Delatt
Table 313. Output pin characteristics for Delatt
Symbol Parameter
Conditions
Min
Typ Max
Unit
0.7 SVDD
SVDD
Low level Input voltage
0
0.3 PVDD V
IIH
Input mode high level input VI = SVDD
current
-1
1
A
IIL
Input mode low level input
current
VI = 0 V
-1
1
A
ILeak
Input leakage current
RSTPD_N = 0.4 V
-1
Cin
Input Capacitance
VOH
High level Output voltage
VIL
[1]
[1]
V
A
1
2.5
pF
To minimize power consumption when in Soft-Power-down mode, the limit is PVDD - 0.4 V.
12.15 Input pin characteristics for SIGIN
Table 314. Input/output pin characteristics for SIGIN
Symbol Parameter
Conditions
Min
Typ Max
Unit
0.7 SVDD
SVDD
0
0.3 SVDD V
VIH
High level Input voltage
[1]
VIL
Low level Input voltage
[2]
IIH
High level input current
VI = SVDD
-1
1
A
IIL
Low level input current
VI = 0 V
-1
1
A
ILeak
Input leakage current
RSTPD_N = 0.4 V
-1
Cin
Input Capacitance
V
A
1
2.5
pF
[1]
To minimize power consumption when in Soft-Power-down mode, the limit is SVDD - 0.4 V.
[2]
To minimize power consumption when in Soft-Power-down mode, the limit is 0.4 V.
12.16 Output pin characteristics for SIGOUT
Table 315. Output pin characteristics for SIGOUT
Symbol Parameter
PN5331B3HN
Product data sheet
COMPANY PUBLIC
Conditions
Min
Typ Max
Unit
VOH
High level output voltage DVDD - 0.1 < SVDD < DVDD
IOH = -4 mA
SVDD - 0.4
SVDD V
VOL
Low level output voltage DVDD - 0.1 < SVDD < DVDD
IOL = +4 mA
0
0.4
IOH
High level output current DVDD - 0.1 < SVDD < DVDD
IOH = -4 mA
-0.4
mA
IOL
Low level output current
DVDD - 0.1 < SVDD < DVDD
IOL = +4 mA
4
mA
ILeak
Input leakage current
RSTPD_N = 0.4 V
-1
Cin
Input Capacitance
Cout
Load Capacitance
trise,fall
Rise and fall times
1
2.5
SVDD = 3 V,
VOH = 0.8 SVDD,
VOL = 0.2 SVDD,
Cout = 30 pF
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157534
V
A
pF
30
pF
9
ns
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12.17 Input/output pin characteristics for P34
Table 316. Input/output pin characteristics for P34
Symbol Parameter
Conditions
Min
Typ Max
Unit
High level input voltage
[1]
0.7 SVDD
SVDD
VIL
Low level input voltage
[2]
0
0.3 SVDD V
VOH
Push-pull mode high
level output voltage
DVDD - 0.1 < SVDD
< DVDD
IOH = -4 mA
SVDD - 0.4
SVDD
V
VOL
Push_pull mode low
level output voltage
DVDD - 0.1 < SVDD
< DVDD
IOH = +4 mA
0
0.4
V
IIH
Input mode high level
input current
VI = SVDD
-1
1
A
IIL
Input mode low level
input current
VI = 0 V
-1
1
A
IOH
High level output voltage DVDD - 0.1 < SVDD
< DVDD
IOH = -4 mA
-0.4
V
IOL
Low level output voltage DVDD - 0.1 < SVDD
< DVDD
IOL = +4 mA
4
V
-1
VIH
ILeak
Input leakage current
Cin
Input Capacitance
Cout
Load Capacitance
trise,fall
Rise and fall times
RSTPD_N = 0.4 V
V
A
1
2.5
pF
30
DVDD = 0.1 < DVDD
VOH = 0.8 SVDD,
VOL = 0.2 SVDD,
Cout = 30 pF
[3]
pF
13.5
ns
[1]
To minimize power consumption when in Soft-Power-down mode, the limit is SVDD - 0.4 V.
[2]
To minimize power consumption when in Soft-Power-down mode, the limit is 0.4 V.
[3]
IOH and IOL specify the output drive capability from which the rise and fall times may be calculated as a
function of the load capacitance.
12.18 Output pin characteristics for LOADMOD
Table 317. Output pin characteristics for LOADMOD
PN5331B3HN
Product data sheet
COMPANY PUBLIC
Symbol
Parameter
Conditions
Min
VOH
High level output voltage
DVDD = 3 V,
IOH = -4 mA
DVDD - 0.4
DVDD
V
VOL
Low level output voltage
DVDD = 3 V,
IOL = 4 mA
0
0.4
V
Cout
Load Capacitance
10
pF
trise,fall
Rise and fall times
4.5
ns
DVDD = 3 V,
VOH = 0.8 DVDD,
VOL = 0.2 DVDD,
Cout = 10 pF
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157534
Typ Max
Unit
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12.19 Input pin characteristics for RX
Table 318. Input pin characteristics for RX
Symbol
Parameter
Conditions
Min
VINRX
Dynamic Input voltage
Range
signal frequency
at 13.56 MHz
-0.7
Cinrx
RX Input Capacitance
6
10
Rinrx
RX Input Series
resistance
AVDD = 3 V,
Receiver active,
VRX = 1 Vpp,
1.5 V DC offset
315
350 385
VRX,MinIV,Mill
Minimum Dynamic Input
voltage, Miller coded
150 500
mVpp
100 200
mVpp
VRX,MinIV,Man
VRX,MaxIV,Mill
Minimum Dynamic Input
voltage, Manchester
Coded
VRXMod,Man
VRXMod,Man
VRXMod,Man
[1]
PN5331B3HN
Product data sheet
COMPANY PUBLIC
14
pF
AVDD
Vpp
AVDD
Vpp
33
%
106 kbit/s
VRX = 1.5 Vpp,
SensMiller = 3
Minimum modulation
voltage
RxGain = 6 and 7
Minimum modulation
voltage
RxGain = 4 and 5
Minimum modulation
voltage
AVDD +1 V
212 and 424 kbit/s
Maximum Dynamic Input
voltage, Miller coded
106 kbit/s
Minimum Modulation
index,
Miller coded
Unit
106 kbit/s
VRX,MaxIV,Man Maximum Dynamic Input
voltage, Manchester
212 and 424 kbit/s
Coded
VmRX,Mill
Typ Max
[1]
6
mV
[1]
18
mV
[1]
120
mV
RxGain = 0 to 3
The minimum modulation voltage is valid for all modulation schemes except Miller coded signals.
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Fig 61. RX Voltage definitions
12.20 Output pin characteristics for AUX1/AUX2
Table 319. Output pin characteristics for AUX1/AUX2
PN5331B3HN
Product data sheet
COMPANY PUBLIC
Symbol
Parameter
Conditions
Min
VOH
High level output voltage
DVDD = 3 V,
IOH = -4 mA
DVDD - 0.4
DVDD
V
VOL
Low level output voltage
DVDD = 3 V,
IOL = 4 mA
DVSS
DVSS +0.4
V
IOH
High level output current
DVDD = 3 V,
VOH = DVDD -0.3
-4
mA
IOL
Low level output current
DVDD = 3 V, VOL =
DVDD -0.3
4
mA
ILeak
Input leakage current
RSTPD_N = 0 V
-1
Cin
Input Capacitance
Cout
Load Capacitance
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Rev. 3.4 — 29 November 2017
157534
Typ Max
Unit
1
A
15
pF
2.5
pF
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12.21 Output pin characteristics for TX1/TX2
Table 320. Output pin characteristics for TX1/TX2
Symbol
Parameter
Conditions
Min
Typ Max Unit
VOH, C32, 3 V High level output voltage TVDD = 3 V and
ITX = 32 mA,
CWGsN = Fh
150
mV
VOH, C80, 3 V High level output voltage TVDD = 3 V and
ITX = 80 mA,
CWGsN = Fh
400
mV
VOL, C32, 3 V Low level output voltage
TVDD = 2.5V and
ITX = 32 mA,
CWGsN = Fh
240
mV
VOL, C80, 3 V Low level output voltage
TVDD = 2.5 V and
ITX = 80 mA,
CWGsN = Fh
640
mV
Table 321. Output resistance for TX1/TX2
PN5331B3HN
Product data sheet
COMPANY PUBLIC
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ROP,01H
High level output
resistance
TVDD = 3 V, VTX = TVDD 100 mV, CWGsP = 01h
133
180
251
ROP,02H
High level output
resistance
TVDD = 3 V, VTX = TVDD 100 mV, CWGsP = 02h
67
90
125
ROP,04H
High level output
resistance
TVDD = 3 V, VTX = TVDD 100 mV, CWGsP = 04h
34
46
62
ROP,08H
High level output
resistance
TVDD = 3 V, VTX = TVDD 100 mV, CWGsP = 08h
17
23
31
ROP,10H
High level output
resistance
TVDD = 3 V, VTX = TVDD 100 mV, CWGsP = 10h
8.5
12
15.5
ROP,20H
High level output
resistance
TVDD = 3 V, VTX = TVDD 100 mV, CWGsP = 20h
4.7
6
7.8
ROP,3FH
High level output
resistance
TVDD = 3 V, VTX = TVDD 100 mV, CWGsP = 3Fh
2.3
3
4.4
RON,10H
Low level output
resistance
TVDD = 3 V, VTX = TVDD 100 mV, CWGsN = 10h
34
46
62
RON,20H
Low level output
resistance
TVDD = 3 V, VTX = TVDD 100 mV, CWGsN = 20h
17
23
31
RON,40H
Low level output
resistance
TVDD = 3 V, VTX = TVDD 100 mV, CWGsN = 40h
8.5
12
15.5
RON,80H
Low level output
resistance
TVDD = 3 V, VTX = TVDD 100 mV, CWGsN = 80h
4.7
6
7.8
RON,F0H
Low level output
resistance
TVDD = 3 V, VTX = TVDD 100 mV, CWGsN = F0h
2.3
3
4.4
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12.22 Timing for Reset
VDD
Vth+Vhys
Vhys
RSTPD_N
Tresetpon
Thpd
Tresetrstpd
RSTOUT
Fig 62. System reset overview
Table 322. Reset duration time
Symbol
Parameter
Tresetpon
Reset time at power on
THPD
Hard Power-down time
TresetRSTPD_N
Conditions
User dependent
Reset time when RSTPD_N is
released
Min
Typ
Max
Unit
[1]
0.1
0.4
2
ms
[2]
20
[1]
0.1
[1]
Depends on the 27.12 MHz crystal oscillator startup time.
[2]
In the case THPD pulse is shorter than 20 ns, it may happened that the IC would be partially resetted.
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0.4
2
ms
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12.23 Timing for the I2C interface
Table 323. I2C timing specification
Symbol
Parameter
Conditions
Min
Typ Max
Unit
fSCL
SCL clock frequency
400
kHz
tHD; STA
Hold time
(repeated) START condition.
tSU; STA
Set-up time
for a repeated START condition
tSU; STO
Set-up time for STOP condition
600
ns
tLOW
LOW period
of the P50_SCL clock
1300
ns
tHIGH
HIGH period
of the P50_SCL clock
600
ns
tHD; DAT
Data hold time
0
tSU; DAT
Data set-up time
0
After this period,
the first clock
pulse is generated
600
ns
600
ns
900
100
tr
Rise time
P50_SCL and SDA
[1]
tf
Fall time
P50_SCL and SDA
[1]
tBUF
Bus free time between
a STOP and START condition
tStrWuSpd
Stretching time
on P50_SCL
when woken-up
on its own address
tHDSDA
Internal hold time
for SDA
tHDSDA
Internal hold time
for SDA in SPD mode
ns
20
300
ns
20
300
ns
1.3
ms
[2]
330
[3]
ns
270
1
ms
590
ns
ns
[1]
The PN533 has a slope control according to the I2C specification for the Fast mode. The slope control is
always present and not dependant of the I2C speed.
[2]
27.12 MHz quartz starts in less than 800 s. For example, quartz like TAS-3225A, TAS-7 or KSS2F with
appropriate layout.
[3]
The PN533 has an internal hold time of around 270ns for the SDA signal to bridge the undefined region of
the falling edge of P50_SCL.
Fig 63. I2C timing diagram
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12.24 Temperature sensor
Table 324. Temperature sensor characteristics
Symbol
Tsens
[1]
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Parameter
Conditions
CIU Temperature sensor threshold
[1]
Min
Typ Max
Unit
100
125 140
C
Temperature sensor embedded in PN533 does not aim to monitor the temperature. It helps to prevent
catastrophic failure avoiding destruction of the IC. In any case the application must ensure by other means
that ambient temperature do not exceed 85 C as specified in operating condition table.
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13. Application information
Interface supply
RSDA
RSCL
I2C
memory
SDA
SVDD
SCL
SIGOUT
Secure
Core
SIGIN
P34
Supply
CRx
PN533
RX
R1
R2
VMID
Cvmid
VBUS
L0
C1
RQ
TX1
DVDD
PVDD
TVSS1
TVSS2
Host - Processor
RTSPD
Host Interface
C0
C2
C0
C2
Antenna
TX2
L0
C1
RQ
TVDD
IRQ
AVDD
AVSS
DVSS
OSCIN
OSCOUT
27,12
MHZ
Fig 64. Application diagram of PN533
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14. Package outline
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm
A
B
D
SOT618-1
terminal 1
index area
A
E
A1
c
detail X
C
e1
e
1/2
e
20
y
y1 C
v M C A B
w M C
b
11
L
21
10
e
e2
Eh
1/2
1
e
30
terminal 1
index area
40
31
Dh
X
0
2.5
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
5 mm
max.
A1
b
c
D(1)
Dh
E(1)
Eh
e
e1
e2
L
v
w
y
y1
1
0.05
0.00
0.30
0.18
0.2
6.1
5.9
4.25
3.95
6.1
5.9
4.25
3.95
0.5
4.5
4.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT618-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-22
Fig 65. Package outline HVQFN40 (SOT618-1)
This package is MSL level 2.
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15. Abbreviations
Table 325. Abbreviations
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Acronym
Description
ASK
Amplitude Shift keying
CIU
Contactless interface Unit
HPD
Hard Power Down (see Section 8.5.6 on page 99)
HZ
High Impedance
Initiator
Generates RF field at 13.56 MHz and starts the NFCIP-1 communication.
Load modulation Index
The load modulation index is defined as the card’s voltage ratio (Vmax Vmin) / (Vmax + Vmin) measured at the card’s coil.
Modulation Index
The modulation index is defined as the voltage ratio (Vmax - Vmin) /
(Vmax + Vmin).
MSL
Moisture Sensitivity Level
PCD
Proximity Coupling Device. Definition for a Card Reader/ Writer
according to the ISO/IEC 14443 Specification
PCR
Power Clock Reset controller
PICC
Proximity Cards. Definition for a contactless Smart Card according to the
ISO/IEC 14443 specification
SAM
Secure Access Module
SIC
Secure Integrated Circuit (can be a Smart Card IC, a Secure Access
Module (SAM),...)
SPI
Serial Parallel Interface
SPD
Soft Power Down mode (see Section 8.5.7 on page 99)
Target
Responds to initiator command either using load modulation scheme (RF
field generated by Initiator) or using modulation of self-generated RF field
(no RF field generated by initiator during target answer).
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16. Revision history
Table 326. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PN5331B3HN v. 3.3
20171129
Product data sheet
-
PN5331B3HN v. 3.3
Modiifcations:
PN5331B3HN v. 3.3
Modiifcations:
157531
Modiifcations:
•
Security status changed into Company Pubic, no content change
20120927
•
Product data sheet
20081210
•
-
157531
Section 17.4 “Licenses”: updated
Product data sheet
Rev. 3.0
Table 146 “Communication overview for ISO/IEC 14443A/MIFARE Reader/Writer” on page
111 and Table 150 “Communication overview for ISO/IEC 14443B Reader/Writer” on page
114:
- added 848 kbit/s baud rate
157530
1 July 2008
Product data sheet
157510
10 April 2008
Objective data sheet
•
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Rev. 1.0
Initial version
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17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
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Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
17.4 Licenses
Purchase of NXP ICs with ISO/IEC 14443 type B functionality
This NXP Semiconductors IC is ISO/IEC 14443 Type B
software enabled and is licensed under Innovatron’s
Contactless Card patents license for ISO/IEC 14443 B.
The license includes the right to use the IC in systems
and/or end-user equipment.
RATP/Innovatron
Technology
Purchase of NXP ICs with NFC technology
Purchase of an NXP Semiconductors IC that complies with one of the Near
Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481
does not convey an implied license under any patent right infringed by
implementation of any of those standards. Purchase of NXP
Semiconductors IC does not include a license to any NXP patent (or other
IP right) covering combinations of those products with other products,
whether hardware or software.
17.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
MIFARE — is a trademark of NXP B.V.
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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19. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.1.1
8.1.2
8.1.2.1
8.1.2.2
8.1.3
8.1.4
8.1.5
8.1.5.1
8.1.5.2
8.1.5.3
8.1.5.4
8.1.6
8.1.6.1
8.1.6.2
8.1.6.3
8.1.6.4
8.1.6.5
8.1.6.6
8.1.6.7
8.1.7
8.1.7.1
8.1.7.2
8.1.7.3
8.1.7.4
8.1.7.5
8.1.8
8.1.8.1
8.1.8.2
8.1.8.3
8.1.8.4
8.1.8.5
8.1.8.6
8.1.8.7
8.1.8.8
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Quick reference data . . . . . . . . . . . . . . . . . . . . . 4
Ordering information . . . . . . . . . . . . . . . . . . . . . 5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional description . . . . . . . . . . . . . . . . . . . 9
80C51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PN533 memory map. . . . . . . . . . . . . . . . . . . . 10
Data memory . . . . . . . . . . . . . . . . . . . . . . . . . 11
IDATA memory . . . . . . . . . . . . . . . . . . . . . . . . 11
XRAM memory . . . . . . . . . . . . . . . . . . . . . . . . 13
Program memory . . . . . . . . . . . . . . . . . . . . . . 14
PCON module . . . . . . . . . . . . . . . . . . . . . . . . 15
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . 15
Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . 15
Interrupt enable: IE0 and IE1 registers . . . . . . 16
Interrupt prioritization: IP0 and IP1 registers . 17
General purpose IRQ control . . . . . . . . . . . . . 19
Timer0/1 description . . . . . . . . . . . . . . . . . . . . 20
Timer0/1 registers. . . . . . . . . . . . . . . . . . . . . . 21
T01CON register . . . . . . . . . . . . . . . . . . . . . . 22
T01MOD register . . . . . . . . . . . . . . . . . . . . . . 23
T0L and T0H registers . . . . . . . . . . . . . . . . . . 24
T1L and T1H registers . . . . . . . . . . . . . . . . . . 25
Incrementer . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Overflow detection . . . . . . . . . . . . . . . . . . . . . 26
Timer2 description . . . . . . . . . . . . . . . . . . . . . 26
Timer2 registers . . . . . . . . . . . . . . . . . . . . . . . 26
T2CON register . . . . . . . . . . . . . . . . . . . . . . . 27
T2MOD register . . . . . . . . . . . . . . . . . . . . . . . 28
T2L, T2H registers . . . . . . . . . . . . . . . . . . . . . 29
RCAP2L, RCAP2H registers . . . . . . . . . . . . . 29
Debug UART . . . . . . . . . . . . . . . . . . . . . . . . . 30
Feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Debug UART functional description . . . . . . . . 30
S0CON register . . . . . . . . . . . . . . . . . . . . . . . 32
S0BUF register . . . . . . . . . . . . . . . . . . . . . . . . 34
Mode 0 baud rate . . . . . . . . . . . . . . . . . . . . . . 34
Mode 2 baud rate . . . . . . . . . . . . . . . . . . . . . . 34
Mode 1 and 3 baud rates . . . . . . . . . . . . . . . . 35
Baud rates using Timer1 (Debug UART
mode 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . 35
8.1.8.9
8.2
8.2.1
8.2.1.1
8.2.1.2
8.2.1.3
8.2.1.4
8.2.2
8.2.2.1
8.2.2.2
8.2.2.3
8.2.2.4
8.2.2.5
8.2.2.6
8.2.2.7
8.3
8.3.1
8.3.1.1
8.3.1.2
8.3.2
8.3.2.1
8.3.2.2
8.3.2.3
8.3.2.4
8.3.2.5
8.3.2.6
8.3.2.7
8.3.2.8
8.3.3
8.3.3.1
8.3.3.2
8.3.3.3
8.3.3.4
8.3.3.5
8.3.3.6
8.3.3.7
8.3.3.8
8.3.3.9
8.3.3.10
8.3.4
8.3.4.1
8.3.4.2
8.3.4.3
8.3.4.4
8.3.4.5
8.3.4.6
Baud rates using Timer2 (Debug UART
mode 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . 37
General purpose IOs configurations . . . . . . . 37
Pad configurations description. . . . . . . . . . . . 39
Open-drain . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Quasi Bidirectional . . . . . . . . . . . . . . . . . . . . . 40
Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Push-pull output . . . . . . . . . . . . . . . . . . . . . . . 42
GPIO registers description. . . . . . . . . . . . . . . 43
P7CFGA register . . . . . . . . . . . . . . . . . . . . . . 43
P7CFGB register . . . . . . . . . . . . . . . . . . . . . . 43
P7 register . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
P3CFGA register . . . . . . . . . . . . . . . . . . . . . . 44
P3CFGB register . . . . . . . . . . . . . . . . . . . . . . 44
P3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
P5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Host interfaces . . . . . . . . . . . . . . . . . . . . . . . . 46
MATX description . . . . . . . . . . . . . . . . . . . . . . 47
MATX register . . . . . . . . . . . . . . . . . . . . . . . . 47
Pads NSS/P50_SCL/HSU_RX and MOSI/SDA /
HSU_TX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . 48
I2C functional description . . . . . . . . . . . . . . . . 48
Master transmitter mode . . . . . . . . . . . . . . . . 49
Master receiver mode . . . . . . . . . . . . . . . . . . 50
I2CCON register . . . . . . . . . . . . . . . . . . . . . . . 50
I2CSTA register . . . . . . . . . . . . . . . . . . . . . . . 54
I2CDAT register . . . . . . . . . . . . . . . . . . . . . . . 58
I2CADR register . . . . . . . . . . . . . . . . . . . . . . . 59
I2C_wu_control register . . . . . . . . . . . . . . . . . 59
FIFO manager . . . . . . . . . . . . . . . . . . . . . . . . 60
FIFO manager functional description. . . . . . . 60
RWL register . . . . . . . . . . . . . . . . . . . . . . . . . 61
TWL register . . . . . . . . . . . . . . . . . . . . . . . . . 61
FIFOFS register . . . . . . . . . . . . . . . . . . . . . . . 62
FIFOFF register . . . . . . . . . . . . . . . . . . . . . . . 62
SFF register . . . . . . . . . . . . . . . . . . . . . . . . . . 63
FIT register. . . . . . . . . . . . . . . . . . . . . . . . . . . 64
FITEN register . . . . . . . . . . . . . . . . . . . . . . . . 65
FDATA register. . . . . . . . . . . . . . . . . . . . . . . . 66
FSIZE register . . . . . . . . . . . . . . . . . . . . . . . . 66
High Speed UART (HSU). . . . . . . . . . . . . . . . 67
Mode of operation . . . . . . . . . . . . . . . . . . . . . 69
HSU Baud rate generator . . . . . . . . . . . . . . . 69
HSU preamble filter . . . . . . . . . . . . . . . . . . . . 69
HSU wake-up generator . . . . . . . . . . . . . . . . 69
HSU_STA register . . . . . . . . . . . . . . . . . . . . . 70
HSU_CTR register . . . . . . . . . . . . . . . . . . . . . 71
continued >>
PN5331B3HN
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.4 — 29 November 2017
157534
© NXP B.V. 2017. All rights reserved.
233 of 236
PN5331B3HN
NXP Semiconductors
Near Field Communication (NFC) controller
8.3.4.7
8.3.4.8
8.3.5
8.3.5.1
8.3.5.2
8.3.5.3
8.3.5.4
8.3.5.5
8.3.5.6
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.5.9
8.5.10
8.5.11
8.5.11.1
8.5.11.2
8.5.11.3
8.5.11.4
8.5.11.5
8.5.11.6
8.6
8.6.1
8.6.2
8.6.3
8.6.3.1
8.6.3.2
8.6.3.3
8.6.4
8.6.4.1
8.6.4.2
8.6.4.3
8.6.4.4
8.6.5
HSU_PRE register . . . . . . . . . . . . . . . . . . . . . 72
HSU_CNT register . . . . . . . . . . . . . . . . . . . . . 72
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Features list . . . . . . . . . . . . . . . . . . . . . . . . . . 73
USB interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 73
Resume by host . . . . . . . . . . . . . . . . . . . . . . . 74
Remote wake up. . . . . . . . . . . . . . . . . . . . . . . 75
Softconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . 76
USB embedded firmware view . . . . . . . . . . . . 77
Power management . . . . . . . . . . . . . . . . . . . . 89
USB bus powered. . . . . . . . . . . . . . . . . . . . . . 89
USB non bus powered . . . . . . . . . . . . . . . . . . 90
HOST powered (single source) . . . . . . . . . . . 90
HOST powered (double source) . . . . . . . . . . . 91
Low power modes . . . . . . . . . . . . . . . . . . . . . 92
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 92
Regulator - short description . . . . . . . . . . . . . 93
Main switch . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SVDD switch. . . . . . . . . . . . . . . . . . . . . . . . . . 94
Power clock and reset controller. . . . . . . . . . . 95
PCR in the system . . . . . . . . . . . . . . . . . . . . . 95
27.12 MHz crystal oscillator . . . . . . . . . . . . . . 97
PLL for USB clock generation . . . . . . . . . . . . 97
Power-up sequence . . . . . . . . . . . . . . . . . . . . 98
Low power modes . . . . . . . . . . . . . . . . . . . . . 98
Reset modes . . . . . . . . . . . . . . . . . . . . . . . . . 99
Soft-Power-down mode (SPD) . . . . . . . . . . . . 99
Suspend mode . . . . . . . . . . . . . . . . . . . . . . . 100
Remote wake-up . . . . . . . . . . . . . . . . . . . . . 101
PCR extension registers . . . . . . . . . . . . . . . 102
PCR register description. . . . . . . . . . . . . . . . 102
CFR register . . . . . . . . . . . . . . . . . . . . . . . . . 102
CER register . . . . . . . . . . . . . . . . . . . . . . . . . 103
ILR register . . . . . . . . . . . . . . . . . . . . . . . . . . 104
PCR Control register . . . . . . . . . . . . . . . . . . 105
PCR Status register . . . . . . . . . . . . . . . . . . . 106
Wakeupen register . . . . . . . . . . . . . . . . . . . . 107
Contactless Interface Unit (CIU) . . . . . . . . . . 108
Feature list . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Simplified block diagram. . . . . . . . . . . . . . . . 110
Reader/Writer modes . . . . . . . . . . . . . . . . . . 111
ISO/IEC 14443A Reader/Writer . . . . . . . . . . 111
FeliCa Reader/Writer . . . . . . . . . . . . . . . . . . 113
ISO/IEC 14443B Reader/Writer . . . . . . . . . . 114
ISO/IEC 18092, ECMA 340 NFCIP-1 operating
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ACTIVE Communication mode. . . . . . . . . . . 116
PASSIVE Communication mode. . . . . . . . . . 117
NFCIP-1 framing and coding . . . . . . . . . . . . 118
NFCIP-1 protocol support . . . . . . . . . . . . . . . 118
Card operating modes . . . . . . . . . . . . . . . . . 119
8.6.5.1
8.6.5.2
8.6.6
8.6.7
8.6.8
8.6.9
8.6.9.1
8.6.9.2
8.6.10
8.6.11
8.6.12
8.6.12.1
8.6.13
8.6.13.1
8.6.13.2
8.6.13.3
8.6.14
8.6.14.1
8.6.14.2
8.6.14.3
8.6.15
8.6.16
8.6.16.1
8.6.16.2
8.6.16.3
8.6.17
8.6.18
8.6.18.1
8.6.19
8.6.19.1
8.6.19.2
8.6.19.3
8.6.20
8.6.20.1
8.6.20.2
8.6.20.3
8.6.20.4
8.6.20.5
8.6.20.6
8.6.20.7
8.6.20.8
8.6.20.9
8.6.20.10
8.6.20.11
8.6.20.12
8.6.20.13
ISO/IEC 14443A/MIFARE card operating mode .
119
FeliCa Card operating mode . . . . . . . . . . . . 121
Overall CIU block diagram . . . . . . . . . . . . . . 121
Transmitter control . . . . . . . . . . . . . . . . . . . . 123
RF level detector . . . . . . . . . . . . . . . . . . . . . 126
Antenna presence self test . . . . . . . . . . . . . 127
Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Antenna presence detector register. . . . . . . 128
Random generator . . . . . . . . . . . . . . . . . . . . 129
Data mode detector . . . . . . . . . . . . . . . . . . . 130
Serial data switch . . . . . . . . . . . . . . . . . . . . . 131
Serial data switch for driver and loadmod . . 131
NFC-WI/S2C interface support. . . . . . . . . . . 133
Signal shape for FeliCa NFC-WI/S2C interface
support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Signal shape for ISO/IEC14443A and MIFARE
NFC-WI/S2C support . . . . . . . . . . . . . . . . . . 135
NFC-WI/S2C initiator mode . . . . . . . . . . . . . 136
Hardware support for FeliCa and NFC
polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Polling sequence functionality for initiator . . 136
Polling sequence functionality for target . . . 137
Additional hardware support for FeliCa and
NFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
CRC co-processor . . . . . . . . . . . . . . . . . . . . 138
FIFO buffer. . . . . . . . . . . . . . . . . . . . . . . . . . 138
Accessing the FIFO buffer . . . . . . . . . . . . . . 138
Controlling the FIFO buffer . . . . . . . . . . . . . 138
Status information about the FIFO buffer . . . 139
CIU_timer . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Interrupt request system . . . . . . . . . . . . . . . 141
Interrupt sources . . . . . . . . . . . . . . . . . . . . . 141
CIU Power Reduction Modes. . . . . . . . . . . . 142
Hard-Power-down . . . . . . . . . . . . . . . . . . . . 142
CIU Power-down . . . . . . . . . . . . . . . . . . . . . 142
Transmitter Power-down . . . . . . . . . . . . . . . 143
CIU command set . . . . . . . . . . . . . . . . . . . . 143
General description . . . . . . . . . . . . . . . . . . . 143
General behaviour . . . . . . . . . . . . . . . . . . . . 143
Commands overview . . . . . . . . . . . . . . . . . . 144
Idle command . . . . . . . . . . . . . . . . . . . . . . . 144
Config command . . . . . . . . . . . . . . . . . . . . . 145
Generate RandomID command . . . . . . . . . . 145
CalcCRC command . . . . . . . . . . . . . . . . . . . 145
Transmit command . . . . . . . . . . . . . . . . . . . 146
NoCmdChange command . . . . . . . . . . . . . . 146
Receive command . . . . . . . . . . . . . . . . . . . . 146
Transceive command. . . . . . . . . . . . . . . . . . 146
AutoColl command. . . . . . . . . . . . . . . . . . . . 147
MFAuthent command. . . . . . . . . . . . . . . . . . 149
continued >>
PN5331B3HN
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.4 — 29 November 2017
157534
© NXP B.V. 2017. All rights reserved.
234 of 236
PN5331B3HN
NXP Semiconductors
Near Field Communication (NFC) controller
8.6.20.14
8.6.21
8.6.21.1
8.6.21.2
8.6.21.3
8.6.21.4
8.6.22
8.6.23
8.6.23.1
8.6.23.2
8.6.23.3
8.6.23.4
8.6.23.5
8.6.23.6
8.6.23.7
8.6.23.8
8.6.23.9
8.6.23.10
8.6.23.11
8.6.23.12
8.6.23.13
8.6.23.14
8.6.23.15
8.6.23.16
8.6.23.17
8.6.23.18
8.6.23.19
8.6.23.20
8.6.23.21
8.6.23.22
8.6.23.23
8.6.23.24
8.6.23.25
8.6.23.26
8.6.23.27
8.6.23.28
8.6.23.29
8.6.23.30
8.6.23.31
8.6.23.32
8.6.23.33
8.6.23.34
8.6.23.35
8.6.23.36
8.6.23.37
8.6.23.38
8.6.23.39
8.6.23.40
8.6.23.41
8.6.23.42
8.6.23.43
SoftReset command . . . . . . . . . . . . . . . . . . .
CIU tests signals. . . . . . . . . . . . . . . . . . . . . .
CIU self-test . . . . . . . . . . . . . . . . . . . . . . . . .
CIU test bus . . . . . . . . . . . . . . . . . . . . . . . . .
Test signals at pin AUX. . . . . . . . . . . . . . . . .
PRBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CIU memory map . . . . . . . . . . . . . . . . . . . . .
CIU register description . . . . . . . . . . . . . . . .
CIU register bit behaviour . . . . . . . . . . . . . . .
CIU_SIC_CLK_en register (6330h) . . . . . . .
CIU_Command register (D1h or 6331h). . . .
CIU_CommIEn register (D2h or 6332h) . . . .
CIU_DivIEn register (D3h or 6333h). . . . . . .
CIU_CommIrq register (D4h or 6334h). . . . .
CIU_DivIrq register (D5h or 6335h) . . . . . . .
CIU_Error register (D6h or 6336h) . . . . . . . .
CIU_Status1 register (DFh or 6337h) . . . . . .
CIU_Status2 register (E9h or 6338h) . . . . . .
CIU_FIFOData register (EAh or 6339h) . . . .
CIU_FIFOLevel register (EBh or 633Ah) . . .
CIU_WaterLevel register (ECh or 633Bh) . .
CIU_Control register (EDh or 633Ch). . . . . .
CIU_BitFraming register (EEh or 633Dh) . . .
CIU_Coll register (EFh or 633Eh). . . . . . . . .
CIU_Mode register (6301h) . . . . . . . . . . . . .
CIU_TxMode register (6302h) . . . . . . . . . . .
CIU_RxMode register (6303h) . . . . . . . . . . .
CIU_TxControl register (6304h) . . . . . . . . . .
CIU_TxAuto register (6305h) . . . . . . . . . . . .
CIU_TxSel register (6306h) . . . . . . . . . . . . .
CIU_RxSel register (6307h) . . . . . . . . . . . . .
CIU_RxThreshold register (6308h). . . . . . . .
CIU_Demod register (6309h) . . . . . . . . . . . .
CIU_FelNFC1 register (630Ah) . . . . . . . . . .
CIU_FelNFC2 register (630Bh) . . . . . . . . . .
CIU_MifNFC register (630Ch) . . . . . . . . . . .
CIU_ManualRCV register (630Dh) . . . . . . . .
CIU_TypeB register (630Eh) . . . . . . . . . . . .
CIU_CRCResultMSB register (6311h) . . . . .
CIU_CRCResultLSB register (6312h) . . . . .
CIU_GsNOff register (6313h) . . . . . . . . . . . .
CIU_ModWidth register (6314h) . . . . . . . . . .
CIU_TxBitPhase register (6315h). . . . . . . . .
CIU_RFCfg register (6316h) . . . . . . . . . . . .
CIU_GsNOn register (6317h) . . . . . . . . . . . .
CIU_CWGsP register (6318h) . . . . . . . . . . .
CIU_ModGsP register (6319h) . . . . . . . . . . .
CIU_TMode register (631Ah) . . . . . . . . . . . .
CIU_TPrescaler register (631Bh) . . . . . . . . .
CIU_TReload_hi register (631Ch) . . . . . . . .
CIU_TReloadVal_lo register (631Dh) . . . . . .
149
150
150
151
152
152
153
155
155
155
156
157
157
158
159
160
161
162
163
163
164
164
165
166
167
168
169
170
171
172
173
174
174
175
176
177
178
180
181
181
182
183
184
185
186
187
187
188
189
189
190
8.6.23.44 CIU_TCounterVal_hi register (631Eh) . . . . . 190
8.6.23.45 Register CIU_TCounterVal_lo (631Fh) . . . . 190
8.6.23.46 CIU_TestSel1 register (6321h). . . . . . . . . . . 191
8.6.23.47 CIU_TestSel2 register (6322h). . . . . . . . . . . 192
8.6.23.48 CIU_TestPinEn register (6323h) . . . . . . . . . 192
8.6.23.49 CIU_TestPinValue register (6324h) . . . . . . . 193
8.6.23.50 CIU_TestBus register (6325h) . . . . . . . . . . . 193
8.6.23.51 CIU_AutoTest register (6326h) . . . . . . . . . . 194
8.6.23.52 CIU_Version register (6327h) . . . . . . . . . . . 194
8.6.23.53 CIU_AnalogTest register (6328h). . . . . . . . . 195
8.6.23.54 CIU_TestDAC1 register (6329h) . . . . . . . . . 197
8.6.23.55 CIU_TestDAC2 register (632Ah) . . . . . . . . . 197
8.6.23.56 CIU_TestADC register (632Bh) . . . . . . . . . . 197
8.6.23.57 CIU_RFlevelDet register (632Fh) . . . . . . . . 198
8.7
Registers map . . . . . . . . . . . . . . . . . . . . . . . 199
8.7.1
Standard registers . . . . . . . . . . . . . . . . . . . . 199
8.7.2
SFR registers . . . . . . . . . . . . . . . . . . . . . . . . 201
9
Limiting values . . . . . . . . . . . . . . . . . . . . . . . 203
10
Recommended operating conditions . . . . . 204
11
Thermal characteristics . . . . . . . . . . . . . . . . 204
12
Characteristics . . . . . . . . . . . . . . . . . . . . . . . 205
12.1
Power management characteristics. . . . . . . 205
12.1.1
Current consumption characteristics . . . . . . 205
12.1.2
Voltage regulator characteristics . . . . . . . . . 206
12.2
Antenna presence self test thresholds. . . . . 206
12.3
Typical 27.12 MHz Crystal requirements . . . 207
12.4
Pin characteristics for 27.12 MHz XTAL
Oscillator (OSCIN, OSCOUT) . . . . . . . . . . . 207
12.5
RSTPD_N input pin characteristics . . . . . . . 208
12.6
Input pin characteristics for I0, I1 and
TESTEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
12.7
RSTOUT_N output pin characteristics . . . . . 209
12.8
Input/output characteristics for pin P70_IRQ 210
12.9
Input/output pin characteristics for P30 /
UART_RX, P31 / UART_TX, P32_INT0,
P33_INT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
12.10
Input/output pin characteristics for P35 . . . . 212
12.11
Input/output pin characteristics for DP and
DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
12.12
Input pin characteristics for SCL . . . . . . . . . 216
12.13
Input/output pin characteristics for SDA. . . . 216
12.14
Output pin characteristics for Delatt. . . . . . . 217
12.15
Input pin characteristics for SIGIN . . . . . . . . 217
12.16
Output pin characteristics for SIGOUT . . . . 217
12.17
Input/output pin characteristics for P34 . . . . 218
12.18
Output pin characteristics for LOADMOD . . 218
12.19
Input pin characteristics for RX . . . . . . . . . . 219
12.20
Output pin characteristics for AUX1/AUX2 . 220
12.21
Output pin characteristics for TX1/TX2 . . . . 221
12.22
Timing for Reset. . . . . . . . . . . . . . . . . . . . . . 222
continued >>
PN5331B3HN
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.4 — 29 November 2017
157534
© NXP B.V. 2017. All rights reserved.
235 of 236
PN5331B3HN
NXP Semiconductors
Near Field Communication (NFC) controller
12.23
12.24
13
14
15
16
17
17.1
17.2
17.3
17.4
17.5
18
19
Timing for the I2C interface . . . . . . . . . . . . . .
Temperature sensor . . . . . . . . . . . . . . . . . . .
Application information. . . . . . . . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information. . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information. . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2017.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 November 2017
157534