PN7120
NFC controller with integrated firmware, supporting all NFC
Forum modes
Rev. 3.5 — 11 June 2018
312435
1
Product data sheet
COMPANY PUBLIC
Introduction
This document describes the functionality and electrical specification of the NFC
Controller PN7120.
Additional documents describing the product functionality further are available for designin support. Refer to the references listed in this document to get access to the full for full
documentation provided by NXP.
In this document the term „MIFARE Classic card“ refers to a MIFARE Classic IC-based
contactless card.
PN7120
NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
2
General description
PN7120, the best plug'n play full NFC solution - easy integration into any OS
environment, with integrated firmware and NCI interface designed for contactless
communication at 13.56 MHz.
It is the ideal solution for rapidly integrating NFC technology in any application, especially
those running OS environment like Linux and Android, reducing Bill of Material (BOM)
size and cost, thanks to:
• full NFC forum compliancy (see [11]) with small form factor antenna
• embedded NFC firmware providing all NFC protocols as pre-integrated feature
2
• direct connection to the main host or microcontroller, by I C-bus physical and NCI
protocol
• ultra-low power consumption in polling loop mode
• Highly efficient integrated power management unit (PMU) allowing direct supply from a
battery
PN7120 embeds a new generation RF contactless front-end supporting various
transmission modes according to NFCIP-1 and NFCIP-2, ISO/IEC 14443, ISO/IEC
15693, ISO/IEC 18000-3, MIFARE Classic IC-based card and FeliCa card specifications.
It embeds an ARM Cortex-M0 microcontroller core loaded with the integrated firmware
supporting the NCI 1.0 host communication.
The contactless front-end design brings a major performance step-up with on one hand
a higher sensitivity and on the other hand the capability to work in active load modulation
communication enabling the support of small antenna form factor
Supported transmission modes are listed in Figure 1. For contactless card functionality,
the PN7120 can act autonomously if previously configured by the host in such a manner.
PN7120 integrated firmware provides an easy integration and validation cycle as all the
NFC real-time constraints, protocols and device discovery (polling loop) are being taken
care internally. In few NCI commands, host SW can configure the PN7120 to notify for
card or peer detection and start communicating with them.
NFC FORUM
NFC-IP MODES
READER
(PCD - VCD)
CARD
(PICC)
READER FOR NFC FORUM
TAG TYPES 1 TO 4
ISO/IEC 14443 A
ISO/IEC 14443 A
ISO/IEC 14443 B
ISO/IEC 14443 B
P2P ACTIVE
106 TO 424 kbps
INITIATOR AND TARGET
ISO/IEC 15693
MIFARE CLASSIC 1K / 4K
P2P PASSIVE
106 TO 424 kbps
INITIATOR AND TARGET
MIFARE DESFire
Sony FeliCa(1)
aaa-015868
1. According to ISO/IEC 18092 (Ecma 340) standard.
Figure 1. PN7120 transmission modes
PN7120
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PN7120
NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
3
Features and benefits
• Includes NXP ISO/IEC 14443-A and Innovatron ISO/IEC 14443-B intellectual property
licensing rights
• ARM Cortex-M0 microcontroller core
• Highly integrated demodulator and decoder
• Buffered output drivers to connect an antenna with minimum number of external
components
• Integrated RF level detector
• Integrated Polling Loop for automatic device discovery
• RF protocols supported
– NFCIP-1, NFCIP-2 protocol (see [7] and [10])
– ISO/IEC 14443A, ISO/IEC 14443B PICC mode via host interface (see[2] )
– ISO/IEC 14443A, ISO/IEC 14443B PCD designed according to NFC Forum digital
protocol T4T platform and ISO-DEP (see [11])
– FeliCa PCD mode
– MIFARE Classic PCD encryption mechanism (MIFARE Classic 1K/4K)
– NFC Forum tag 1 to 4 (MIFARE Ultralight, Jewel, Open FeliCa tag, MIFARE
DESFire) (see [11])
– ISO/IEC 15693/ICODE VCD mode (see [8])
• Supported host interfaces
– NCI protocol interface according to NFC Forum standardization (see [1])
2
– I C-bus High-speed mode (see[3] )
• Integrated power management unit
– Direct connection to a battery (2.3 V to 5.5 V voltage supply range)
– Support different Hard Power-Down/Standby states activated by firmware
– Autonomous mode when host is shut down
2
• Automatic wake-up via RF field, internal timer and I C-bus interface
• Integrated non-volatile memory to store data and executable code for customization
PN7120
Product data sheet
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PN7120
NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
4
Applications
• All devices requiring NFC functionality especially those running in an Android or Linux
environment
• TVs, set-top boxes, Blu-ray decoders, audio devices
• Home automation, gateways, wireless routers
• Home appliances
• Wearables, remote controls, healthcare, fitness
• Printers, IP phones, gaming consoles, accessories
PN7120
Product data sheet
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PN7120
NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
5
Quick reference data
Table 1. Quick reference data
Symbol
VBAT
Parameter
Conditions
battery supply voltage
Card Emulation and Passive
Target; VSS = 0 V
[1]
Reader, Active Initiator and
Active Target; VSS = 0 V
[1]
VDD
supply voltage
VDD(PAD)
VDD(PAD) supply voltage supply voltage for host
interface
IBAT
battery supply current
Typ
Max Unit
2.3
-
5.5
V
2.7
-
5.5
V
1.65 1.8
1.95 V
1.8 V host supply;
VSS = 0 V
[1]
1.65 1.8
1.95 V
3.3 V host supply;
VSS = 0 V
[1]
3.0
-
3.6
V
in Hard Power Down state;
VBAT = 3.6 V; T = 25 °C
-
10
12
μA
in Standby state;
VBAT = 3.6 V; T = 25 °C
-
-
20
μA
in Monitor state;
VBAT = 2.75 V; T = 25 °C
-
-
12
μA
in low-power polling loop;
VBAT = 3.6 V; T = 25 °C;
loop time = 500 ms
-
150
-
μA
-
-
170
mA
-
-
15
mA
-
180
-
mA
[3]
IO(VDDPAD)
output current on pin
VDD(PAD)
total current which can
be pulled on VDD(PAD)
referenced outputs
Ith(Ilim)
current limit threshold
current
current limiter on VDD(TX)
pin; VDD(TX) = 3.1 V
Ptot
total power dissipation
Reader; IVDD(TX) = 100 mA;
VBAT = 5.5 V
-
-
0.5
W
Tamb
ambient temperature
JEDEC PCB-0.5
-30
+25
+85
°C
[1]
[2]
[3]
[4]
Product data sheet
COMPANY PUBLIC
[2]
internal supply voltage
PCD mode at typical 3 V
PN7120
[2]
Min
[3][4]
VSS represents VSS, VSS1, VSS2, VSS3, VSS4, VSS(PAD) and VSS(TX).
The antenna should be tuned not to exceed this current limit (the detuning effect when coupling with another device must
be taken into account).
The antenna shall be tuned not to exceed the maximum of IVBAT.
This is the threshold of a built-in protection done to limit the current out of VDD(TX) in case of any issue at antenna pins
to avoid burning the device. It is not allowed in operational mode to have IVDD(TX) such that IVBAT maximum value is
exceeded.
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PN7120
NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
6
Ordering information
Table 2. Ordering information
Type number
Package
Name
PN7120A0EV/C1xxxx
PN7120
Product data sheet
COMPANY PUBLIC
Description
Version
VFBGA49 plastic very thin fine-pitch ball grid array
package; 49 balls
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PN7120
NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
7
Marking
aaa-007526
Figure 2. PN7120 package marking (top view)
Table 3. Marking code
PN7120
Product data sheet
COMPANY PUBLIC
Line number
Marking code
Line 1
product version identification
Line 2
diffusion batch sequence number
Line 3
manufacturing code including:
• diffusion center code:
– N: TSMC
– s: Global Foundry
• assembly center code:
– S: APK
– X: ASEN
• RoHS compliancy indicator:
– D: Dark Green; fully compliant RoHS and no halogen and antimony
• manufacturing year and week, 3 digits:
– Y: year
– WW: week code
• product life cycle status code:
– X: means not qualified product
– nothing means released product
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PN7120
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NFC controller with integrated firmware, supporting all NFC Forum modes
8
Block diagram
CLESS
INTERFACE UNIT
CLESS UART
RF DETECT
SENSOR
RX CODEC
DEMOD
ADC
TX CODEC
DRIVER
TxCtrl
PLL
BG
HOST INTERFACE
SIGNAL
PROCESSING
I2C-BUS
ARM
CORTEX M0
DATA
MEMORY
SRAM
VMID
EEPROM
MEMORY
CONTROL
AHB to APB
POWER
MANAGEMENT UNIT
BATTERY
MONITOR
3V
TX-LDO
1.8 V
DSLDO
MISCELLANEOUS
CLOCK MGT UNIT
TIMERS
OSC
380 kHz
OSC
20 MHz
CRC
COPROCESSOR
FRACN
PLL
QUARTZ
OSCILLATOR
CODE
MEMORY
ROM
EEPROM
RANDOM
NUMBER
GENERATOR
aaa-015869
Figure 3. PN7120 block diagram
PN7120
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PN7120
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NFC controller with integrated firmware, supporting all NFC Forum modes
9
Pinning information
9.1 Pinning
G
F
E
D
C
B
A
ball A1
index area
1
2
3
4
5
6
7
aaa-007528
Figure 4. PN7120 pinning (bottom view)
Table 4. PN7120 pin description
PN7120
Product data sheet
COMPANY PUBLIC
Symbol
Pin Type
i.c.
A1
CLK_REQ
[1]
Refer
Description
-
-
internally connected; must be connected to
ground
A2
O
VDD(PAD)
clock request pin
XTAL1
A3
I
VDD
PLL clock input. Oscillator input
i.c.
A4
-
-
internally connected; leave open
i.c.
A5
-
-
internally connected; leave open
i.c.
A6
-
-
internally connected; leave open
i.c.
A7
-
-
internally connected; leave open
I2CSCL
B1
I
VDD(PAD)
I C-bus serial clock input
I2CADR0
B2
I
VDD(PAD)
I C-bus address bit 0 input
i.c.
B3
-
-
internally connected; leave open
i.c.
B4
-
-
internally connected; leave open
i.c.
B5
-
-
internally connected; must be connected to
ground
VSS1
B6
G
n/a
ground
i.c.
B7
-
-
internally connected; leave open
I2CSDA
C1
I/O
VDD(PAD)
I C-bus serial data
VSS(PAD)
C2
G
n/a
pad ground
XTAL2
C3
O
VDD
oscillator output
VSS
C4
G
n/a
ground
n.c.
C5
-
-
not connected
2
2
2
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PN7120
NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
Symbol
Pin Type
VDD
C6
VBAT
Refer
Description
P
n/a
LDO output supply voltage
C7
P
n/a
battery supply voltage
IRQ
D1
O
VDD(PAD)
interrupt request output
BOOST_CTRL
D2
O
VDD(PAD)
booster control, see [5]
VDD(PAD)
D3
P
n/a
pad supply voltage
VSS2
D4
G
n/a
ground
i.c.
D5
-
-
internally connected; leave open
VSS3
D6
G
n/a
ground
i.c.
D7
-
-
internally connected; leave open
VEN
E1
I
VBAT
reset pin. Set the device in Hard Power Down
VSS(DC_DC)
E2
G
n/a
ground
n.c.
E3
-
-
not connected
n.c.
E4
-
-
not connected
n.c.
E5
-
-
not connected
n.c.
E6
-
-
not connected
VDD(TX)
E7
P
n/a
contactless transmitter output supply voltage
for decoupling
i.c.
F1
-
-
internally connected; leave open
i.c.
F2
-
-
internally connected; leave open
VSS4
F3
G
n/a
ground
i.c.
F4
-
-
internally connected; leave open
RXN
F5
I
VDD
negative receiver input
RXP
F6
I
VDD
positive receiver input
VDD(MID)
F7
P
n/a
receiver reference input supply voltage
VBAT2
G1
P
n/a
battery supply voltage; must be connected to
VBAT
VBAT1
G2
P
n/a
battery supply voltage; must be connected to
VBAT
TX1
G3
O
VDD(TX)
antenna driver output
VSS(TX)
G4
G
n/a
contactless transmitter ground
TX2
G5
O
VDD(TX)
antenna driver output
ANT2
G6
P
n/a
antenna connection for Listen mode
ANT1
G7
P
n/a
antenna connection for Listen mode
[1]
PN7120
Product data sheet
COMPANY PUBLIC
[1]
P = power supply; G = ground; I = input, O = output; I/O = input/output.
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PN7120
NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
10 Functional description
2
PN7120 can be connected on a host controller through I C-bus. The logical interface
towards the host baseband is NCI-compliant [1] with additional command set for NXPspecific product features. This IC is fully user controllable by the firmware interface
described in [4].
Moreover, PN7120 provides flexible and integrated power management unit in order to
preserve energy supporting Power Off mode.
In the following chapters you will find also more details about PN7120 with references to
very useful application note such as:
• PN7120 User Manual ([4]):
User Manual describes the software interfaces (API) based on the NFC forum NCI
standard. It does give full description of all the NXP NCI extensions coming in addition
to NCI standard ([1]).
• PN7120 Hardware Design Guide ([5]):
Hardware Design Guide provides an overview on the different hardware design options
offered by the IC and provides guidelines on how to select the most appropriate ones
for a given implementation. In particular, this document highlights the different chip
power states and how to operate them in order to minimize the average NFC-related
power consumption so to enhance the battery lifetime.
• PN7120 Antenna and Tuning Design Guide ([6]):
Antenna and Tuning Design Guide provides some guidelines regarding the way to
design an NFC antenna for the PN7120 chip.
It also explains how to determine the tuning/matching network to place between this
antenna and the PN7120.
Standalone antenna performances evaluation and final RF system validation (PN7120
+ tuning/matching network + NFC antenna within its final environment) are also
covered by this document.
• PN7120 Low-Power Mode Configuration ([9]):
Low-Power Mode Configuration documentation provides guidance on how PN7120
can be configured in order to reduce current consumption by using Low-power polling
mode.
BATTERY/PMU
HOST
CONTROLLER
host interface
control
NFCC
ANTENNA
MATCHING
aaa-016739
Figure 5. PN7120 connection
PN7120
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PN7120
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NFC controller with integrated firmware, supporting all NFC Forum modes
10.1 System modes
10.1.1 System power modes
PN7120 is designed in order to enable the different power modes from the system.
2 power modes are specified: Full power mode and Power Off mode.
Table 5. System power modes description
System power mode
Description
Full power mode
the main supply (VBAT) as well as the host interface supply (VDD(PAD)) is
available, all use cases can be executed
Power Off mode
the system is kept Hard Power Down (HPD)
Full power mode
[VBAT = On && VDD(PAD) = On
VEN = On]
[VBAT = Off || VEN = Off]
Power Off mode
[VEN = Off]
aaa-015871
Figure 6. System power mode diagram
Table 6 summarizes the system power mode of the PN7120 depending on the status of
the external supplies available in the system:
Table 6. System power modes configuration
VBAT
VEN
Power mode
Off
X
Power Off mode
On
Off
Power Off mode
On
On
Full power mode
Depending on power modes, some application states are limited:
Table 7. System power modes description
PN7120
Product data sheet
COMPANY PUBLIC
System power mode
Allowed communication modes
Power Off mode
no communication mode available
Full power mode
Reader/Writer, Card Emulation, P2P modes
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PN7120
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NFC controller with integrated firmware, supporting all NFC Forum modes
10.1.2 PN7120 power states
Next to system power modes defined by the status of the power supplies, the power
states include the logical status of the system thus extend the power modes.
4 power states are specified: Monitor, Hard Power Down (HPD), Standby, Active.
Table 8. PN7120 power states
Power state name
Description
Monitor
The PN7120 is supplied by VBAT which voltage is below its programmable
critical level, VEN voltage > 1.1 V and the Monitor state is enabled. The
system power mode is Power Off mode.
Hard Power Down
The PN7120 is supplied by VBAT which voltage is above its programmable
critical level when Monitor state is enabled and PN7120 is kept in Hard
Power Down (VEN voltage is kept low by host or SW programming) to
have the minimum power consumption. The system power mode is in
Power Off.
Standby
The PN7120 is supplied by VBAT which voltage is above its programmable
critical level when the Monitor state is enabled, VEN voltage is high (by
host or SW programming) and minimum part of PN7120 is kept supplied
to enable configured wake-up sources which allow to switch to Active
state; RF field, Host interface. The system power mode is Full power
mode.
Active
The PN7120 is supplied by VBAT which voltage is above its programmable
critical level when Monitor state is enabled, VEN voltage is high (by host
or SW programming) and the PN7120 internal blocks are supplied. 3
functional modes are defined: Idle, Listener and Poller. The system power
mode is Full power mode.
At application level, the PN7120 will continuously switch between different states to
optimize the current consumption (polling loop mode). Refer to Table 1 for targeted
current consumption in here described states.
The PN7120 is designed to allow the host controller to have full control over its functional
states, thus of the power consumption of the PN7120 based NFC solution and possibility
to restrict parts of the PN7120 functionality.
10.1.2.1 Monitor state
In Monitor state, the PN7120 will exit it only if the battery voltage recovers over the
critical level. Battery voltage monitor thresholds show hysteresis behavior as defined in
Table 26.
PN7120 will autonomously shut-down internal PMU supply to protect the battery from
deep discharge.
10.1.2.2 Hard Power Down (HPD) state
The Hard Power Down state is entered when VDD(PAD) and VBAT are high by setting VEN
voltage < 0.4 V. As these signals are under host control, the PN7120 has no influence on
entering or exiting this state.
PN7120
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PN7120
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NFC controller with integrated firmware, supporting all NFC Forum modes
10.1.2.3 Standby state
Active state is PN7120’s default state after boot sequence in order to allow a quick
configuration of PN7120. It is recommended to change the default state to Standby state
after first boot in order to save power. PN7120 can switch to Standby state autonomously
(if configured by host).
In this state PN7120 most blocks including CPU are no more supplied. Number of wakeup sources exist to put PN7120 into Active state:
2
• I C-bus interface wake-up event
• Antenna RF level detector
• Internal timer event when using polling loop (380 kHz Low-power oscillator is enabled)
If wake-up event occurs, PN7120 will switch to Active state. Any further operation
depends on software configuration and/or wake-up source.
10.1.2.4 Active state
Within the Active state, the system is acting as an NFC device. The device can be in 3
different functional modes: Idle, Poller and Target.
Table 9. Functional modes in active state
Functional modes
Description
Idle
the PN7120 is active and host interface communication is on going. The
RF interface is not activated. If Standby state is de-activated PN7120
stays in Idle mode even when no host communication.
Listener
the PN7120 is active and is listening to external device. The RF interface
is activated.
Poller
the PN7120 is active and is in Poller mode. It polls external device. The
RF interface is activated.
Poller mode:
In this mode, PN7120 is acting as Reader/Writer or NFC Initiator, searching for or
communicating with passive tags or NFC target. Once RF communication has ended,
PN7120 will switch to Idle mode or Standby state to save energy. Poller mode shall be
used with 2.7 V < VBAT < 5.5 V and VEN voltage > 1.1 V. Poller mode shall not be used
with VBAT < 2.7 V. PVDD is within its operational range (see Table 1).
Listener mode:
In this mode, PN7120 is acting as a card or as an NFC Target. Listener mode shall be
used with 2.3 V < VBAT < 5.5 V and VEN voltage > 1.1 V. Once RF communication has
ended, PN7120 will switch to Idle mode or Standby state to save energy.
10.1.2.5 Polling loop
The polling loop will sequentially set PN7120 in different power states (Active or
Standby). All RF technologies supported by PN7120 can be independently enabled
within this polling loop.
There are 2 main phases in the polling loop:
PN7120
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PN7120
NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
• Listening phase. The PN7120 can be in Standby power state or Listener mode
• Polling phase. The PN7120 is in Poller mode
Listening phase
Emulation
Pause
Type A
Type B
Type F
@424
ISO15693
Type F
@212
Polling phase
aaa-016741
Figure 7. Polling loop: all phases enabled
Listening phase uses Standby power state (when no RF field) and PN7120 goes to
Listener mode when RF field is detected. When in Polling phase, PN7120 goes to Poller
mode.
To further decrease the power consumption when running the polling loop, PN7120
features a low-power RF polling. When PN7120 is in Polling phase instead of sending
regularly RF command PN7120 senses with a short RF field duration if there is any NFC
Target or card/tag present. If yes, then it goes back to standard polling loop. With 500 ms
(configurable duration, see [4]) listening phase duration, the average power consumption
is around 150 μA.
PN7120
Product data sheet
COMPANY PUBLIC
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PN7120
NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
Listening phase
Emulation
Pause
Polling phase
aaa-016743
Figure 8. Polling loop: low-power RF polling
Detailed description of polling loop configuration options is given in [4].
10.2 Microcontroller
PN7120 is controlled via an embedded ARM Cortex-M0 microcontroller core.
PN7120 features integrated in firmware are referenced in [4]
10.3 Host interfaces
2
PN7120 provides the support of an I C-bus Slave Interface, up to 3.4 MBaud.
2
The host interface is waken-up on I C-bus address.
To enable and ensure data flow control between PN7120 and host controller, additionally
a dedicated interrupt line IRQ is provided which Active state is programmable. See [4] for
more information.
PN7120
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PN7120
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NFC controller with integrated firmware, supporting all NFC Forum modes
2
10.3.1 I C-bus interface
2
2
The I C-bus interface implements a slave I C-bus interface with integrated shift register,
shift timing generation and slave address recognition.
2
I C-bus Standard mode (100 kHz SCL), Fast mode (400 kHz SCL) and High-speed mode
(3.4 MHz SCL) are supported.
2
The mains hardware characteristics of the I C-bus module are:
•
•
•
•
2
Support slave I C-bus
Standard, Fast and High-speed modes supported
Wake-up of PN7120 on its address only
Serial clock synchronization can be used by PN7120 as a handshake mechanism to
suspend and resume serial transfer (clock stretching)
2
2
The I C-bus interface module meets the I C-bus specification [3] except General call, 10bit addressing and Fast mode Plus (Fm+).
2
10.3.1.1 I C-bus configuration
2
2
The I C-bus interface shares four pins with I C-bus interface also supported by PN7120.
2
When I C-bus is configured in EEPROM settings, functionality of interface pins changes
to one described in Table 10.
2
Table 10. Functionality for I C-bus interface
Pin name
Functionality
I2CADR0
I C-bus address 0
I2CSDA
I C-bus data line
I2CSCL
I C-bus clock line
2
2
2
2
PN7120 supports 7-bit addressing mode. Selection of the I C-bus address is done by 2pin configurations on top of a fixed binary header: 0, 1, 0, 1, 0, 0, I2CADR0, R/W.
2
Table 11. I C-bus interface addressing
2
2
I2CADR0
I C-bus address
(R/W = 0, write)
I C-bus address
(R/W = 1, read)
0
0x50
0x51
1
0x52
0x53
10.4 PN7120 clock concept
There are 4 different clock sources in PN7120:
• 27.12 MHz clock coming either/or from:
– Internal oscillator for 27.12 MHz crystal connection
– Integrated PLL unit which includes a 1 GHz VCO
• 13.56 MHz RF clock recovered from RF field
• Low-power oscillator 20 MHz
• Low-power oscillator 380 kHz
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10.4.1 27.12 MHz quartz oscillator
When enabled, the 27.12 MHz quartz oscillator applied to PN7120 is the time reference
for the RF front end when PN7120 is behaving in Reader mode or NFCIP-1 initiator.
Therefore stability of the clock frequency is an important factor for reliable operation. It is
recommended to adopt the circuit shown in Figure 9.
PN7120
XTAL1
XTAL2
c
crystal
27.12 MHz
c
aaa-015872
Figure 9. 27.12 MHz crystal oscillator connection
Table 12 describes the levels of accuracy and stability required on the crystal.
Table 12. Crystal requirements
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fxtal
crystal frequency
ISO/IEC and FCC
compliancy
-
27.12 -
Δfxtal
crystal frequency accuracy
full operating range
[1]
-100
-
+100 ppm
all VBAT range;
T = 20 °C
[1]
-50
-
+50
ppm
all temperature range;
VBAT = 3.6 V
[1]
-50
-
+50
ppm
MHz
ESR
equivalent series resistance
-
50
100
Ω
CL
load capacitance
-
10
-
pF
Po(xtal)
crystal output power
-
-
100
μW
[1]
This requirement is according to FCC regulations requirements. To meet only ISO/IEC 14443 and ISO/IEC 18092, then ±
14 kHz apply.
10.4.2 Integrated PLL to make use of external clock
When enabled, the PLL is designed to generate a low noise 27.12 MHz for an input clock
13 MHz, 19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz and 52 MHz.
The 27.12 MHz of the PLL is used as the time reference for the RF front end when
PN7120 is behaving in Reader mode or NFC Initiator as well as in NFC Target when
configured in Active communication mode.
The input clock on XTAL1 shall comply with the.following phase noise requirements for
the following input frequency: 13 MHz, 19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz and 52
MHz:
PN7120
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dBc/Hz
-20dBc/Hz
Input reference
noise floor
-140 dBc/Hz
Input reference noise corner
50 kHz
Hz
aaa-007232
Figure 10. Input reference phase noise characteristics
This phase noise is equivalent to an RMS jitter of 6.23 ps from 10 Hz to 1 MHz. For
configuration of input frequency, refer to [8]. There are 6 pre programmed and validated
frequencies for the PLL: 13 MHz, 19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz and 52 MHz.
Table 13. PLL input requirements
Coupling: single-ended, AC coupling;
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclk
clock frequency
ISO/IEC and FCC
compliancy
-
13
-
MHz
-
19.2
-
MHz
-
24
-
MHz
-
26
-
MHz
-
38.4
-
MHz
fi(ref)acc
φn
reference input
frequency accuracy
phase noise
-
52
-
MHz
full operating range;
frequencies typical values:
13 MHz, 26 MHz and 52
MHz
[1]
-25
-
+25
ppm
full operating range;
frequencies typical values:
19.2 MHz, 24 MHz and 38.4
MHz
[1]
-50
-
+50
ppm
-140
-
-
dB/H
z
input noise floor at 50 kHz
Sinusoidal shape
Vi(p-p)
peak-to-peak input
voltage
0.2
-
1.8
V
Vi(clk)
clock input voltage
0
-
1.8
V
0
-
1.8 ± V
10 %
Square shape
Vi(clk)
[1]
clock input voltage
This requirement is according to FCC regulations requirements. To meet only ISO/IEC 14443 and ISO/IEC 18092, then ±
400 ppm limits apply.
For detailed description of clock request mechanisms, refer to [4] and [5].
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10.4.3 Low-power 20 MHz oscillator
Low-power 20 MHz oscillator is used as system clock of the system.
10.4.4 Low-power 380 kHz oscillator
A Low Frequency Oscillator (LFO) is implemented to drive a counter (WUC) wakingup PN7120 from Standby state. This allows implementation of low-power reader polling
loop at application level. Moreover, this 380 kHz is used as the reference clock for write
access to EEPROM memory.
10.5 Power concept
10.5.1 PMU functional description
The Power Management Unit of PN7120 generates internal supplies required by PN7120
out of VBAT input supply voltage:
• VDD: internal supply voltage
• VDD(TX): output supply voltage for the RF transmitter
The Figure 11 describes the main blocks available in PMU:
VBAT
VDD
VBAT1 and VBAT2
DSLDO
BANDGAP
TXLDO
VDD(TX)
NFCC
aaa-016748
Figure 11. PMU functional diagram
10.5.2 DSLDO: Dual Supply LDO
The input pin of the DSLDO is VBAT.
The Low drop-out regulator provides VDD required in PN7120.
10.5.3 TXLDO
This is the LDO which generates the transmitter voltage.
The value of VDD(TX) is configured at 3.1 V ± 0.2 V.
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VDD(TX) value is given according to the minimum targeted VBAT value for which Reader
mode shall work.
For VBAT above 3.1 V, VDD(TX) = 3.1 V:
In Standby state, VDD(TX) is around 2.5 V with some ripples; it toggles between 2.35 V to
2.65 V with a period which depends on the capacitance and load on VDD(TX).
Figure 12 shows VDD(TX) behavior for 3.1 V:
V
VBAT
3.1 V
VDD(TX) set to 3.1 V
time
aaa-015875
Figure 12. VDD(TX) offset disabled behavior
Figure 13 shows the case where the PN7120 is in Standby state:
V
VBAT
2.65 V
2.5 V
2.35 V
time
aaa-007538
Figure 13. VDD(TX) behavior when PN7120 is in Standby state
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10.5.3.1 TXLDO limiter
The TXLDO includes a current limiter to avoid too high current within TX1, TX2 when in
reader or initiator modes.
The current limiter block compares an image of the TXLDO output current to a reference.
Once the reference is reached, the output current gets limited which is equivalent to a
typical output current of 220 mA whatever VBAT = 2.7 V and 180 mA for VBAT = 3.1 V.
10.5.4 Battery voltage monitor
The PN7120 features low-power VBAT voltage monitor which protects the host device
battery from being discharged below critical levels. When VBAT voltage goes below
VBATcritical threshold, then the PN7120 goes in Monitor state. Refer to Figure 14 for
principle schematic of the battery monitor.
The battery voltage monitor is enabled via an EEPROM setting.
The VBATcritical threshold can be configured to 2.3 V or 2.75 V by an EEPROM setting.
At the first start-up, VBAT voltage monitor functionality is OFF and then enabled if properly
configured in EEPROM. The PN7120 monitors battery voltage continuously.
VBAT
enable
EEPROM
REGISTERS
threshold
selection
VBAT
MONITOR
POWER
MANAGEMENT
VDD
low-power
SYSTEM
MANAGEMENT
power off
POWER SWITCHES
VDD(CPU)
DIGITAL
(memories, cpu,
etc,...)
aaa-015877
Figure 14. Battery voltage monitor principle
The value of the critical level can be configured to 2.3 V or 2.75 V by an EEPROM
setting. This value has a typical hysteresis around 150 mV.
10.6 Reset concept
10.6.1 Resetting PN7120
To enter reset there are 2 ways:
PN7120
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• Pulling VEN voltage low (Hard Power Down state)
• if VBAT monitor is enabled: lowering VBAT below the monitor threshold (Monitor state, if
VEN voltage is kept above 1.1 V)
Reset means resetting the embedded FW execution and the registers values to their
default values. Part of these default values is defined from EEPROM data loaded values,
others are hardware defined. See [4] to know which ones are accessible to tune PN7120
to the application environment.
To get out of reset:
• Pulling VEN voltage high with VBAT above VBAT monitor threshold if enabled
Figure 15 shows reset done via VEN pin.
VBAT
VDD(PAD)
VEN
tw(VEN)
tboot
host
communication
possible
aaa-015878
Figure 15. Resetting PN7120 via VEN pin
See Section 15.3.2 for the timings values.
10.6.2 Power-up sequences
There are 2 different supplies for PN7120. PN7120 allows these supplies to be set up
independently, therefore different power-up sequences have to be considered.
10.6.2.1 VBAT is set up before VDD(PAD)
This is at least the case when VBAT pin is directly connected to the battery and when
PN7120 VBAT is always supplied as soon the system is supplied.
As VEN pin is referred to VBAT pin, VEN voltage shall go high after VBAT has been set.
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VBAT
VDD(PAD)
tt(VDD(PAD)-VEN)
tboot
host
communication
possible
VEN
aaa-015879
Figure 16. VBAT is set up before VDD(PAD)
See Section 15.2.3 for the timings values.
10.6.2.2 VDD(PAD) and VBAT are set up in the same time
It is at least the case when VBAT pin is connected to a PMU/regulator which also supply
VDD(PAD).
VBAT
tt(VBAT-VEN)
VDD(PAD)
tboot
host
communication
possible
VEN
aaa-015881
Figure 17. VDD(PAD) and VBAT are set up in the same time
See Section 15.2.3 for the timings values.
10.6.2.3 PN7120 has been enabled before VDD(PAD) is set up or before VDD(PAD) has been cut
off
This can be the case when VBAT pin is directly connected to the battery and when
VDD(PAD) is generated from a PMU. When the battery voltage is too low, then the PMU
might no more be able to generate VDD(PAD). When the device gets charged again, then
VDD(PAD) is set up again.
As the pins to select the interface are biased from VDD(PAD), when VDD(PAD) disappears
the pins might not be correctly biased internally and the information might be lost.
Therefore it is required to make the IC boot after VDD(PAD) is set up again.
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VBAT
VDD(PAD)
tt(VDD(PAD)-VEN)
VEN
tW(VEN)
tboot
host
communication
possible
aaa-015884
Figure 18. VDD(PAD) is set up or cut-off after PN7120 has been enabled
See Section 15.2.3 for the timings values.
10.6.3 Power-down sequence
tVBAT(L)
VBAT
t > 0 ms
(nice to have)
t > 0 ms
VEN
VDD(PAD)
aaa-015886
Figure 19. PN7120 power-down sequence
10.7 Contactless Interface Unit
PN7120 supports various communication modes at different transfer speeds and
modulation schemes. The following chapters give more detailed overview of selected
communication modes.
Remark: all indicated modulation index and modes in this chapter are system
parameters. This means that beside the IC settings a suitable antenna tuning is required
to achieve the optimum performance.
10.7.1 Reader/Writer communication modes
Generally 5 Reader/Writer communication modes are supported:
•
•
•
•
PN7120
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PCD Reader/Writer for ISO/IEC 14443 type A and for MIFARE Classic
PCD Reader/Writer for Jewel/Topaz
PCD Reader/Writer for FeliCa
PCD Reader/Writer for ISO/IEC 14443B
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• VCD Reader/Writer for ISO/IEC 15693/ICODE
10.7.1.1 Communication mode for ISO/IEC 14443 type A, MIFARE Classic and Jewel/Topaz
PCD
The ISO/IEC 14443A/MIFARE Classic PCD communication mode is the general reader
to card communication scheme according to the ISO/IEC 14443A specification. This
modulation scheme is as well used for communications with Jewel/Topaz cards.
Figure 20 describes the communication on a physical level, the communication table
describes the physical parameters (the numbers take the antenna effect on modulation
depth for higher data rates).
PCD to PICC
100 % ASK at 106 kbit/s
> 25 % ASK at 212, 424 or 848 kbit/s
Modified Miller coded
NFCC
ISO/IEC 14443A MIFARE Classic
PCD mode
PICC (Card)
PICC to PCD,
subcarrier load modulation
Manchester coded at 106 kbit/s
BPSK coded at 212, 424 or 848 kbit/s
ISO/IEC 14443A MIFARE Classic
aaa-016749
Figure 20. Read/write mode for ISO/IEC 14443 type A and read/write mode for MIFARE
Classic
Table 14. Communication overview for ISO/IEC 14443 type A and read/write mode for MIFARE Classic
ISO/IEC 14443A/ ISO/IEC 14443A higher transfer speeds
MIFARE Classic/
Jewel/
Topaz
Communication
direction
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
848 kbit/s
Bit length
(128/13.56) μs
(64/13.56) μs
(32/13.56) μs
(16/13.56) μs
100 % ASK
> 25 % ASK
> 25 % ASK
> 25 % ASK
Modified Miller
Modified Miller
Modified Miller
Modified Miller
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
bit coding
Manchester
BPSK
BPSK
BPSK
PN7120 → PICC
(data sent by PN7120 to a modulation on
card)
PN7120 side
bit coding
PICC → PN7120
(data received by PN7120 modulation on
from a card)
PICC side
The contactless coprocessor and the on-chip CPU of PN7120 handle the complete ISO/
IEC 14443A/MIFARE Classic RF-protocol, nevertheless a dedicated external host has to
handle the application layer communication.
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10.7.1.2 FeliCa PCD communication mode
The FeliCa communication mode is the general Reader/Writer to card communication
scheme according to the FeliCa specification. Figure 21 describes the communication on
a physical level, the communication overview describes the physical parameters.
PCD to PICC,
8 - 12 % ASK at 212 or 424 kbits/s
Manchester coded
NFCC
ISO/IEC 18092 - FeliCa
PCD mode
PICC (Card)
PICC to PCD,
load modulation
Manchester coded at 212 or 424 kbits/s
FeliCa card
aaa-016750
Figure 21. FeliCa Reader/Writer communication mode diagram
Table 15. Overview for FeliCa Reader/Writer communication mode
FeliCa
FeliCa higher transfer speeds
Transfer speed
212 kbit/s
424 kbit/s
Bit length
(64/13.56) μs
(32/13.56) μs
modulation on
PN7120 side
8 % - 12 % ASK
8 % - 12 % ASK
bit coding
Manchester
Manchester
modulation on PICC
side
load modulation
load modulation
subcarrier frequency
no subcarrier
no subcarrier
bit coding
Manchester
Manchester
Communication direction
PN7120 → PICC
(data sent by PN7120 to a card)
PICC → PN7120
(data received by PN7120 from a card)
The contactless coprocessor of PN7120 and the on-chip CPU handle the FeliCa
protocol. Nevertheless a dedicated external host has to handle the application layer
communication.
10.7.1.3 ISO/IEC 14443B PCD communication mode
The ISO/IEC 14443B PCD communication mode is the general reader to card
communication scheme according to the ISO/IEC 14443B specification. Figure 22
describes the communication on a physical level, the communication table describes the
physical parameters.
PN7120
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PCD to PICC,
8 - 14 % ASK at 106, 212, 424 or 848 kbit/s
NRZ coded
NFCC
ISO/IEC 14443 Type B
PCD mode
PICC to PCD,
subcarrier load modulation
BPSK coded at 106, 212, 424 or 848 kbit/s
PICC (Card)
ISO/IEC 14443 Type B
aaa-016751
Figure 22. ISO/IEC 14443B Reader/Writer communication mode diagram
Table 16. Overview for ISO/IEC 14443B Reader/Writer communication mode
Communication
direction
ISO/IEC 14443B
ISO/IEC 14443B higher transfer speeds
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
848 kbit/s
Bit length
(128/13.56) μs
(64/13.56) μs
(32/13.56) μs
(16/13.56) μs
8 % - 14 % ASK
8 % - 14 % ASK
8 % - 14 % ASK
8 % - 14 % ASK
NRZ
NRZ
NRZ
NRZ
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
bit coding
BPSK
BPSK
BPSK
BPSK
PN7120 → PICC
(data sent by PN7120 to a modulation on
card)
PN7120 side
bit coding
PICC → PN7120
(data received by PN7120 modulation on
from a card)
PICC side
The contactless coprocessor and the on-chip CPU of PN7120 handles the complete
ISO/IEC 14443B RF-protocol, nevertheless a dedicated external host has to handle the
application layer communication.
10.7.1.4 R/W mode for NFC forum Type 5 Tag
The R/W mode for NFC forum Type 5 Tag (T5T) is the general reader to card
communication scheme according to the ISO/IEC 15693 specification. PN7120 will
communicate with VICC (Type 5 Tag) using only the 26.48 kbit/s with single subcarrier
data rate of the VICC.
NFCC
ISO/IEC 15693
VCD mode
VCD to VICC,
100 % ASK at 26.48 kbit/s
pulse position coded
VICC to VCD,
subcarrier load modulation
Manchester coded at 26.48 kbit/s
Card
(VICC/TAG)
ISO/IEC 15693
aaa-016752
Figure 23. R/W mode for NFC forum T5T communication diagram
Figure 23 and Table 17 show the communication schemes used.
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Table 17. Communication overview for NFC forum T5T R/W mode
Communication direction
PN7120 → VICC
(data sent by PN7120 to a tag)
transfer speed
26.48 kbit/s
bit length
(512/13.56) μs
modulation on PN7120 side
100 % ASK
bit coding
pulse position modulation 1 out of 4 mode
transfer speed
26.48 kbit/s
bit length
(512/13.56) μs
modulation on VICC side
subcarrier load modulation
subcarrier frequency
single subcarrier
bit coding
Manchester
VICC → PN7120
(data received by PN7120 from a tag)
10.7.2 ISO/IEC 18092, Ecma 340 NFCIP-1 communication modes
An NFCIP-1 communication takes place between 2 devices:
• NFC Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication.
• NFC Target: responds to NFC Initiator command either in a load modulation scheme in
Passive communication mode or using a self-generated and self-modulated RF field for
Active communication mode.
The NFCIP-1 communication differentiates between Active and Passive communication
modes.
• Active communication mode means both the NFC Initiator and the NFC Target are
using their own RF field to transmit data
• Passive communication mode means that the NFC Target answers to an NFC
Initiator command in a load modulation scheme. The NFC Initiator is active in terms of
generating the RF field.
PN7120 supports the Active Target, Active Initiator, Passive Target and Passive Initiator
communication modes at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as
defined in the NFCIP-1 standard.
BATTERY
BATTERY
NFCC
NFCC
HOST
HOST
NFC Initiator: Passive or Active Communication modes
NFC Target: Passive or Active Communication modes
aaa-016755
Figure 24. NFCIP-1 communication mode
Nevertheless a dedicated external host has to handle the application layer
communication.
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10.7.2.1 ACTIVE communication mode
Active communication mode means both the NFC Initiator and the NFC Target are using
their own RF field to transmit data.
host
NFC Initiator
NFC Target
power
to generate
the field
host
NFC Initiator
host
NFCC
1. NFC Initiator starts the communication at selected transfer speed
power
for digital
processing
NFCC
host
NFC Target
2. NFC Target answers at the same transfer speed
power
for digital
processing
power
to generate
the field
aaa-016756
Figure 25. Active communication mode
The following table gives an overview of the Active communication modes:
Table 18. Overview for Active communication mode
Communication direction
ISO/IEC 18092, Ecma 340, NFCIP-1
Baud rate
106 kbit/s
212 kbit/s
424 kbit/s
Bit length
(128/13.56) μs
(64/13.56) μs
(32/13.56) μs
modulation
100 % ASK
8 % - 30 % ASK
bit coding
Modified Miller
Manchester
modulation
100 % ASK
8 % - 30 % ASK
bit coding
Miller
Manchester
NFC Initiator to NFC Target
[1]
8 % - 30 % ASK
[1]
Manchester
NFC Target to NFC Initiator
[1]
[1]
8 % - 30 % ASK
[1]
Manchester
This modulation index range is according to NFCIP-1 standard. It might be that some NFC forum type 3 cards does not withstand the full range as based
on FeliCa range which is narrow (8 % to 14 % ASK). To adjust the index, see [6] .
10.7.2.2 Passive communication mode
Passive communication mode means that the NFC Target answers to an NFC Initiator
command in a load modulation scheme.
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host
NFC Initiator
NFC Target
power
to generate
the field
host
NFC Initiator
host
NFCC
1. NFC Initiator starts the communication at selected transfer speed
power
for digital
processing
NFCC
2. NFC Target answers using load modulation at the same transfer speed
host
NFC Target
power
to generate
the field
power
for digital
processing
aaa-016757
Figure 26. Passive communication mode
Table 19 gives an overview of the Passive communication modes:
Table 19. Overview for Passive communication mode
Communication direction
ISO/IEC 18092, Ecma 340, NFCIP-1
Baud rate
106 kbit/s
212 kbit/s
424 kbit/s
Bit length
(128/13.56) μs
(64/13.56) μs
(32/13.56) μs
modulation
100 % ASK
8 % - 30 % ASK
bit coding
Modified Miller
Manchester
Manchester
modulation
subcarrier load
modulation
load modulation
load modulation
subcarrier frequency
13.56 MHz/16
no subcarrier
no subcarrier
bit coding
Manchester
Manchester
Manchester
NFC Initiator to NFC Target
[1]
8 % - 30 % ASK
[1]
NFC Target to NFC Initiator
[1]
This modulation index range is according to NFCIP-1 standard. It might be that some NFC forum type 3 cards does not withstand the full range as based
on FeliCa range which is narrow (8 % to 14 % ASK). To adjust the index, see[6] .
10.7.2.3 NFCIP-1 framing and coding
The NFCIP-1 framing and coding in Active and Passive communication modes are
defined in the NFCIP-1 standard: ISO/IEC 18092 or Ecma 340.
PN7120
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10.7.2.4 NFCIP-1 protocol support
The NFCIP-1 protocol is not completely described in this document. For detailed
explanation of the protocol, refer to the ISO/IEC 18092 or Ecma 340 NFCIP-1 standard.
However the datalink layer is according to the following policy:
• Transaction includes initialization, anticollision methods and data transfer. This
sequence must not be interrupted by another transaction
• PSL shall be used to change the speed between the target selection and the data
transfer, but the speed should not be changed during a data transfer
10.7.3 Card communication modes
PN7120 can be addressed as a ISO/IEC 14443A or ISO/IEC 14443B cards. This means
that PN7120 can generate an answer in a load modulation scheme according to the ISO/
IEC 14443A or ISO/IEC 14443B interface description.
Remark: PN7120 does not support a complete card protocol. This has to be handled by
the host controller.
Table 20 and Table 21 describe the physical parameters.
10.7.3.1 ISO/IEC 14443A/MIFARE Classic card communication mode
Table 20. Overview for ISO/IEC 14443A/MIFARE Classic card communication mode
Communication
direction
ISO/IEC 14443A
ISO/IEC 14443A higher transfer speeds
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
Bit length
(128/13.56) μs
(64/13.56) μs
(32/13.56) μs
modulation on PCD
side
100 % ASK
> 25 % ASK
> 25 % ASK
bit coding
Modified Miller
Modified Miller
Modified Miller
modulation on PN7120 subcarrier load
side
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier frequency
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
bit coding
Manchester
BPSK
BPSK
PCD → PN7120
(data received by
PN7120 from a card)
PN7120 → PCD
(data sent by PN7120
to a card)
PN7120
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10.7.3.2 ISO/IEC 14443B card communication mode
Table 21. Overview for ISO/IEC 14443B card communication mode
Communication
direction
ISO/IEC 14443B
ISO/IEC 14443B higher transfer speeds
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
Bit length
(128/13.56) μs
(64/13.56) μs
(32/13.56) μs
modulation on PCD
side
8 % - 14 % ASK
8 % - 14 % ASK
8 % - 14 % ASK
bit coding
NRZ
NRZ
NRZ
modulation on PN7120 subcarrier load
side
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier frequency
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
bit coding
BPSK
BPSK
BPSK
PCD → PN7120
(data received by
PN7120 from a
Reader)
PN7120 → PCD
(data sent by PN7120
to a Reader)
10.7.4 Frequency interoperability
When in communication, PN7120 is generating some RF frequencies. PN7120 is also
sensitive to some RF signals as it is looking from data in the field.
In order to avoid interference with others RF communication, it is required to tune the
antenna and design the board according to [5].
Although ISO/IEC 14443 and ISO/IEC 18092/Ecma 340 allows an RF frequency of 13.56
MHz ± 7 kHz, FCC regulation does not allow this wide spread and limits the dispersion to
± 50 ppm, which is in line with PN7120 capability.
PN7120
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11 Application design-in information
CLOCK INTERFACE
ANTENNA MATCHING/TUNING CIRCUIT
3
I2CSCL
host controller I2C-bus data
I2CSDA
host controller external interrupt input (optional)
IRQ
host controller GPIO (output) - reset control
VEN
TEST1
n.c.
CLK_REQ
i.c.
n.c.
VDD(PAD)
VBAT
POWER INTERFACE
VDD
controller IO
power supply (1.8 V or 3.3 V)
F4
E6
C5
B7
A7
A6
E7
G7
F6
D2
G3
B1
G5
C1
F5
D1
PN7120
E1
G6
F7
A1
D7
A2
F1
B3
F2
D3
G2
C7
G1
C6
V SS1
VSS(PAD)
Cvdd
1 µF
i.c.
i.c.
i.c.
n.c.
n.c.
i.c.
n.c.
i.c.
n.c.
n.c.
E4
B2
battery power (2.75 V up to 5.5 V)
Cvbat
4.7 µF
E3
C3
C2 B6
Cpvdd
1 µF
D5
Crxp
1 nF/16 V
C4
D4 D6
F3
Ctvdd
1 µF
Rrxp1
1 kΩ
Cs1
Lemc1
560 nH
VDD(TX)
ANT1
RXP
Lemc2
TX1
0Ω
Cp1
xxx(1) pF/50 V
Cemc2
180 pF/16 V
Cp2
xxx(1) pF/50 V
Crxn
ANT2
1 nF/16 V
Cs2
xxx(1) pF/50 V
Rrxn1
1 kΩ
RXN
Rq1
(1)
Cemc1 xxx pF/50 V
180 pF/16 V
560 nH
TX2
Rq2
0Ω
Cant2
xxx(1) pF/50 V
VDD(MID)
i.c.
i.c.
i.c.
VBAT1
VBAT2
E2 G4
VSS(TX)
host controller I2C-bus clock
E5
V SS4
n.c.
BOOST_CTRL
A5
V SS(DC_DC)
I2CADR0
A4
V SS3
XTAL2
host controller I2C-bus
B4
V SS2
HOST INTERFACE
B5
A3
V SS
XTAL1
i.c.
CXTAL 2
10 pF
i.c.
27.12 MHz
xxx(1) pF/50 V
CXTAL 1
10 pF
1
i.c.
2
ANTENNA
Cant1
TEST2
4
Y2
VBAT
Cvbat2
100 nF
Cvmid
100 nF
main ground (GND)
aaa-015905
1. xxx: customer antenna matching tuning.
Figure 27. Application schematic
PN7120
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12 Limiting values
Table 22. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD(PAD) VDD(PAD) supply voltage
VBAT
battery supply voltage
VESD
electrostatic discharge voltage
Tstg
Product data sheet
COMPANY PUBLIC
Min
Max
Unit
supply voltage for host
interface
-
4.2
V
-
6
V
HBM; 1500 Ω, 100 pF;
EIA/JESD22-A114-D
-
1.5
kV
CDM; field induced model;
EIA/JESC22-C101-C
-
500
V
-55
+150 °C
-
0.55
W
storage temperature
all modes
[1]
Ptot
total power dissipation
VRXN(i)
RXN input voltage
0
2.5
V
VRXP(i)
RXP input voltage
0
2.5
V
[1]
PN7120
Conditions
The design of the solution shall be done so that for the different use cases targeted the power to be dissipated from the
field or generated by PN7120 does not exceed this value.
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13 Recommended operating conditions
Table 23. Operating conditions
Symbol
Parameter
Conditions
Tamb
ambient temperature
JEDEC PCB-0.5
VBAT
VDD
supply voltage
VDD(PAD)
VDD(PAD) supply voltage
Ptot
total power dissipation
IO(VDDTX)
output current on pin
VDD(TX)
IBAT
battery supply current
Max
Unit
-30
+25
+85
°C
[1]
2.3
-
5.5
V
Card Emulation and
Passive Target;
VSS = 0 V
[1][2]
2.3
-
5.5
V
Reader, Active Initiator
and Active Target;
VSS = 0 V
[1][2]
2.7
-
5.5
V
1.65
1.8
1.95
V
battery monitor enabled;
VSS = 0 V
supply voltage for host
interface
1.8 V host supply;
VSS = 0 V
[1]
1.65
1.8
1.95
V
3 V host supply;
VSS = 0 V
[1]
3.0
-
3.6
V
-
-
0.5
W
-
-
100
mA
in Hard Power Down
state; VBAT = 3.6 V; T =
25 °C
-
10
12
μA
in Standby state; VBAT =
3.6 V; T = 25 °C
-
-
20
μA
in Monitor state; VBAT =
2.75 V; T = 25 °C
-
-
12
μA
in low-power polling
loop; VBAT = 3.6 V; T =
25 °C; loop time = 500
ms
-
150
-
μA
Reader; IVDD(TX) = 100
mA; VBAT = 5.5 V
[2]
total supply current on
VBAT
PCD mode at typical 3 V
[3]
-
-
170
mA
Ith(Ilim)
current limit threshold
current
current limiter on VDD(TX)
pin; VDD(TX) = 3.1 V
[3][4]
-
180
-
mA
[3]
[4]
Product data sheet
COMPANY PUBLIC
Typ
IVBAT(tot)
[1]
[2]
PN7120
battery supply voltage
Min
VSS represents VSS, VSS1, VSS2, VSS3, VSS4, VSS(PAD) and VSS(TX).
The antenna should be tuned not to exceed this current limit (the detuning effect when coupling with another device must
be taken into account).
The antenna shall be tuned not to exceed the maximum of IVBAT.
This is the threshold of a built-in protection done to limit the current out of VDD(TX) in case of any issue at antenna pins
to avoid burning the device. It is not allowed in operational mode to have IVDD(TX) such that IVBAT maximum value is
exceeded.
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14 Thermal characteristics
Table 24. Thermal characteristics
PN7120
Product data sheet
COMPANY PUBLIC
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Rth(j-a)
thermal resistance
from junction to
ambient
in free air with exposed pad
soldered on a 4 layer JEDEC PCB
-
74
-
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15 Characteristics
15.1 Current consumption characteristics
Table 25. Current consumption characteristics for operating ambient temperature range
Symbol
Parameter
Conditions
Min
Typ
Max Unit
IBAT
battery supply
current
in Hard Power Down state;
VBAT = 3.6 V;
VEN voltage = 0 V
-
10
18
μA
IO(VDDTX)
in Standby state;
VBAT = 3.6 V; including emulation
phase of polling loop
[1]
-
20
35
μA
in Idle and Target Active power
states; VBAT = 3.6 V
[2]
-
6
-
mA
in Initiator Active power state;
VBAT = 3.6 V
[2]
-
13
-
mA
in Monitor state; VBAT = 2.75 V
[3]
-
10
18
μA
[4][5]
-
30
100
mA
-
-
15
mA
output current on pin
VDD(TX)
IO(VDDPAD) output current on pin total current which can be pulled
VDD(PAD)
on VDD(PAD) referenced outputs
[1]
[2]
[3]
[4]
[5]
Refer to Section 10.1.2.4 for the description of the power modes.
Refer to Section 10.1.2.5 for the description of the polling loop.
This is the same value for VBAT = 2.3 V when the monitor threshold is set to 2.3 V.
IVDD(TX) depends on VDD(TX) and on the external circuitry connected to TX1 and TX2.
During operation with a typical circuitry as recommended by NXP in [6], the overall current is below 100 mA even when
loaded by target/card/tag.
15.2 Functional block electrical characteristics
15.2.1 Battery voltage monitor characteristics
Table 26. Battery voltage monitor characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vth
threshold voltage
set to 2.3 V
2.2
2.3
2.4
V
set to 2.75 V
2.65
2.75
2.85
V
100
150
200
mV
Vhys
hysteresis voltage
15.2.2 Reset via VEN
Table 27. Reset timing
PN7120
Product data sheet
COMPANY PUBLIC
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tW(VEN)
VEN pulse width
to reset
3
-
-
μs
tboot
boot time
-
-
2.5
ms
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15.2.3 Power-up timings
Table 28. Power-up timings
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tt(VBAT-VEN)
transition time from pin
VBAT to pin VEN
VBAT, VEN
voltage = HIGH
0
-
-
ms
tt(VDDPAD-VEN)
transition time from pin
VDD(PAD) to pin VEN
VDD(PAD), VEN
voltage = HIGH
0
-
-
ms
tt(VBAT-VDDPAD)
transition time from pin
VBAT to pin VDD(PAD)
VBAT, VDD(PAD) =
HIGH
0
-
-
ms
Conditions
Min
Typ
Max
Unit
20
-
-
ms
Min
Typ
Max
Unit
120
125
130
°C
15.2.4 Power-down timings
Table 29. Power-down timings
Symbol
Parameter
tVBAT(L)
time VBAT LOW
15.2.5 Thermal protection
Table 30. Thermal threshold
Symbol
Parameter
Conditions
Tth(act)otp
overtemperature protection
activation threshold temperature
2
15.2.6 I C-bus timings
Here below are timings and frequency specifications.
tf(HIF3)
tr(HIF3)
tHD;DAT
HIF3 (SDA)
tSU;STA
tHD;STA
tHIGH
tSU;DAT
tLOW
HIF4 (SCL)
aaa-014046
2
Figure 28. I C-bus timings
PN7120
Product data sheet
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2
Table 31. High-speed mode I C-bus timings specification
Symbol
Parameter
Conditions
2
Min
Max
Unit
0
3.4
MHz
fclk(I2CSCL) clock frequency on pin
I2CSCL
I C-bus SCL;
tSU;STA
set-up time for a repeated
START condition
Cb < 100 pF
160
-
ns
tHD;STA
hold time (repeated) START
condition
Cb < 100 pF
160
-
ns
tLOW
LOW period of the SCL clock
Cb < 100 pF
160
-
ns
tHIGH
HIGH period of the SCL clock
Cb < 100 pF
60
-
ns
tSU;DAT
data set-up time
Cb < 100 pF
10
-
ns
tHD;DAT
data hold time
Cb < 100 pF
0
-
ns
tr(I2CSDA)
rise time on pin I2CSDA
I C-bus SDA;
10
80
ns
10
80
ns
Cb < 100 pF
2
Cb < 100 pF
tf(I2CSDA)
fall time on pin I2CSDA
2
I C-bus SDA;
Cb < 100 pF
Vhys
hysteresis voltage
Schmitt trigger inputs;
Cb < 100 pF
0.1VDD(PAD) -
V
Min
Max
Unit
fclk(I2CSCL) clock frequency on pin I2CSCL I C-bus SCL;
Cb < 400 pF
0
400
kHz
tSU;STA
set-up time for a repeated
START condition
Cb < 400 pF
600
-
ns
tHD;STA
hold time (repeated) START
condition
Cb < 400 pF
600
-
ns
tLOW
LOW period of the SCL clock
Cb < 400 pF
1.3
-
μs
tHIGH
HIGH period of the SCL clock
Cb < 400 pF
600
-
ns
tSU;DAT
data set-up time
Cb < 400 pF
100
-
ns
tHD;DAT
data hold time
Cb < 400 pF
0
900
ns
Vhys
hysteresis voltage
Schmitt trigger inputs;
Cb < 400 pF
0.1VDD(PAD) -
2
Table 32. Fast mode I C-bus timings specification
Symbol
Parameter
Conditions
2
PN7120
Product data sheet
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15.3 Pin characteristics
15.3.1 XTAL1 and XTAL2 pins characteristics
Table 33. Input clock characteristics on XTAL1 when using PLL
Symbol
Parameter
Vi(p-p)
δ
Conditions
Min
Typ
Max
Unit
peak-to-peak input voltage
0.2
-
1.8
V
duty cycle
35
-
65
%
Table 34. Pin characteristics for XTAL1 when PLL input
Symbol
Parameter
Conditions
Min
Typ Max
Unit
IIH
HIGH-level input current
VI = VDD
-
-
1
μA
IIL
LOW-level input current
VI = 0 V
1
-
-
μA
Vi
input voltage
-
-
VDD
V
Vi(clk)(p-p)
peak-to-peak clock input
voltage
200
-
-
mV
Ci
input capacitance
-
2
-
pF
all power modes
Table 35. Pin characteristics for 27.12 MHz crystal oscillator
Symbol
Parameter
Conditions
Ci(XTAL1)
XTAL1 input capacitance
Ci(XTAL2)
XTAL2 input capacitance
[1]
VDD = 1.8 V; VDC
= 0.65 V; VAC =
0.9 V(p-p)
[1]
Min
Typ
Max
Unit
-
2
-
pF
-
2
-
pF
See the Figure 27 for example of appropriate connected components. The layout should ensure minimum distance
between the pins and the components.
Table 36. PLL accuracy
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fo(acc)
output frequency
accuracy
deviation added to XTAL1
frequency on RF frequency
generated; worst case
whatever input frequency
-50
-
+50
ppm
15.3.2 VEN input pin characteristics
Table 37. VEN input pin characteristics
PN7120
Product data sheet
COMPANY PUBLIC
Symbol
Parameter
VIH
VIL
Conditions
Min
Typ
Max
Unit
HIGH-level input voltage
1.1
-
VBAT
V
LOW-level input voltage
0
-
0.4
V
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NFC controller with integrated firmware, supporting all NFC Forum modes
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IIH
HIGH-level input current
VEN voltage =
VBAT
-
-
1
μA
IIL
LOW-level input current
VEN voltage =
0V
1
-
-
μA
Ci
input capacitance
-
5
-
pF
15.3.3 Pin characteristics for IRQ, CLK_REQ and BOOST_CTRL
Table 38. Pin characteristics for IRQ, CLK_REQ and BOOST_CTRL
Symbol
Parameter
Conditions
Min
Typ
Max
VOH
HIGH-level output
voltage
IOH < 3 mA
VDD(PAD) - 0.4
-
VDD(PAD) V
VOL
LOW-level output
voltage
IOL < 3 mA
0
-
0.4
V
CL
load capacitance
-
-
20
pF
tf
fall time
high speed
1
-
3.5
ns
slow speed
2
-
10
ns
1
-
3.5
ns
2
-
10
ns
0.4
-
0.75
MΩ
tr
CL = 12 pF max
CL = 12 pF max
rise time
high speed
slow speed
Rpd
[1]
Unit
[1]
pull-down resistance
Activated in HPD and Monitor states.
15.3.4 ANT1 and ANT2 pin characteristics
Table 39. Electrical characteristics of ANT1 and ANT2
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Zi(ANT1-ANT2) input impedance between ANT1 and low impedance
ANT2
-
10
17
Ω
Vth(ANT1)
ANT1 threshold voltage
I = 10 mA
-
3.3
-
V
Vth(ANT2)
ANT2 threshold voltage
I = 10 mA
-
3.3
-
V
15.3.5 Input pin characteristics for RXN and RXP
Table 40. Input pin characteristics for RXN and RXP
PN7120
Product data sheet
COMPANY PUBLIC
Symbol
Parameter
VRXN(i)
Conditions
Min
Typ Max Unit
RXN input voltage
0
-
VDD
V
VRXP(i)
RXP input voltage
0
-
VDD
V
Ci(RXN)
RXN input capacitance
-
12
-
pF
Ci(RXP)
RXP input capacitance
-
12
-
pF
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NFC controller with integrated firmware, supporting all NFC Forum modes
Symbol
Parameter
Conditions
Min
Typ Max Unit
Zi(RXN-
input impedance between
RXN and VDD(MID)
Reader, Card and
P2P modes
0
-
15
kΩ
input impedance between
RXP and VDD(MID)
Reader, Card and
P2P modes
0
-
15
kΩ
VDDMID)
Vi(dyn)(RXN)
RXN dynamic input voltage
Miller coded
106 kbit/s
-
150
200
mV(p-p)
212 to 424 kbit/
s
-
150
200
mV(p-p)
106 kbit/s
-
150
200
mV(p-p)
212 to 424 kbit/
s
-
150
200
mV(p-p)
VDDMID)
Zi(RXP-
Vi(dyn)(RXP)
RXP dynamic input voltage
Miller coded
Vi(dyn)(RXN)
RXN dynamic input voltage
Manchester, NRZ
or BPSK coded;
106 to 848 kbit/s
-
150
200
mV(p-p)
Vi(dyn)(RXP)
RXP dynamic input voltage
Manchester, NRZ
or BPSK coded;
106 to 848 kbit/s
-
150
200
mV(p-p)
Vi(dyn)(RXN)
RXN dynamic input voltage
All data coding; 106
kbit/s to 848 kbit/s
VDD
-
-
V(p-p)
Vi(dyn)(RXP)
RXP dynamic input voltage
All data coding; 106
kbit/s to 848 kbit/s
VDD
-
-
V(p-p)
Vi(RF)
RF input voltage
RF input voltage
detected; Initiator
modes
100
-
mV(p-p)
15.3.6 Output pin characteristics for TX1 and TX2
Table 41. Output pin characteristics for TX1 and TX2
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output
voltage
VDD(TX) = 3.1 V and
IOH = 30 mA;
PMOS driver fully on
VDD(TX) - 150
-
-
mV
VOL
LOW-level output
voltage
VDD(TX) = 3.1 V and
IOL = 30 mA;
NMOS driver fully on
-
-
200
mV
Table 42. Output resistance for TX1 and TX2
PN7120
Product data sheet
COMPANY PUBLIC
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ROL
LOW-level output
resistance
VDD(TX) - 100 mV;
CWGsN = 01h
-
-
80
Ω
ROL
LOW-level output
resistance
VDD(TX) - 100 mV;
CWGsN = 0Fh
-
-
5
Ω
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NFC controller with integrated firmware, supporting all NFC Forum modes
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ROH
HIGH-level output
resistance
VDD(TX) - 100 mV
-
-
4
Ω
15.3.7 Input pin characteristics for I2CADR0
Table 43. Input pin characteristics for I2CADR0
Symbol
Parameter
Conditions
Min
Typ Max
Unit
VIH
HIGH-level input
voltage
0.65VDD(PAD) -
VDD(PAD)
VIL
LOW-level input
voltage
0
-
0.35VDD(PAD) V
IIH
HIGH-level input
current
VI = VDD(PAD);
T = 125 °C
-
-
1
μA
IIL
LOW-level input
current
VI = 0 V;
T = 125 °C
-1
-
-
μA
Ci
input capacitance
-
5
-
pF
V
15.3.8 Pin characteristics for I2CSDA and I2CSCL
Table 44. Pin characteristics for I2CSDA and I2CSCL
Below values are given for VDD(PAD) in the range of 1.8 V; unless specified.
Symbol
Parameter
VOL
Min
Typ
Max
Unit
LOW-level output IOL < 3 mA
voltage
0
-
0.4
V
CL
load capacitance
-
-
10
pF
tf
fall time
CL = 100 pF;
Rpull-up = 1.8 kΩ;
Standard and Fast
mode
30
-
250
ns
CL = 100 pF;
VDD(PAD) = 3.3 V; Rpullup = 3.3 kΩ;
Standard and Fast
mode
30
-
250
ns
CL = 100 pF;
Rpull-up = 1 kΩ;
High-speed mode
80
-
110
ns
CL = 100 pF;
Rpull-up = 1.8 kΩ;
Standard and Fast
mode
30
-
250
ns
tr
PN7120
Product data sheet
COMPANY PUBLIC
rise time
Conditions
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NFC controller with integrated firmware, supporting all NFC Forum modes
Symbol
PN7120
Product data sheet
COMPANY PUBLIC
Parameter
Conditions
Min
Typ
Max
Unit
CL = 100 pF;
VDD(PAD) = 3.3 V;
Rpull-up = 3.3 kΩ;
Standard and Fast
mode
30
-
250
ns
CL = 100 pF;
Rpull-up = 1 kΩ;
High-speed mode
10
-
100
ns
V
VIH
HIGH-level input
voltage
0.7VDD(PAD) -
VDD(PAD)
VIL
LOW-level input
voltage
0
-
0.3VDD(PAD) V
IIH
HIGH-level input
current
VI = VDD(PAD);
high impedance
-
-
1
μA
IIL
LOW-level input
current
VI = 0 V;
high impedance
-1
-
-
μA
Ci
input capacitance
-
5
-
pF
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NFC controller with integrated firmware, supporting all NFC Forum modes
16 Package outline
VFBGA49: plastic very thin fine-pitch ball grid array package; 49 balls
D
B
SOT1320-1
A
ball A1
index area
A
A2
E
A1
detail X
e1
C
e
Øv
Øw
b
C A B
C
y1 C
y
G
F
e
E
e2
D
C
B
A
ball A1
index area
1
2
3
4
5
6
7
X
0
5 mm
scale
Dimensions (mm are the original dimensions)
Unit
mm
A
A1
A2
b
max 1.00 0.25 0.75 0.35
nom 0.90 0.20 0.70 0.30
min 0.80 0.15 0.65 0.25
D
E
e
e1
e2
4.1
4.0
3.9
4.4
4.3
4.2
0.5
3.0
3.0
v
w
y
0.15 0.05 0.08
y1
0.1
sot1320-1_po
Outline
version
References
IEC
JEDEC
JEITA
European
projection
Issue date
11-11-11
11-12-30
SOT1320-1
Figure 29. Package outline, VFBGA49, SOT1320-1, MSL 1
PN7120
Product data sheet
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NFC controller with integrated firmware, supporting all NFC Forum modes
17 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 "Surface mount reflow
soldering description".
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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Product data sheet
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NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 30) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 45 and Table 46
Table 45. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
3
Volume (mm )
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 46. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
3
Volume (mm )
< 350
350 to 2 000
> 2 000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 30.
PN7120
Product data sheet
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NFC controller with integrated firmware, supporting all NFC Forum modes
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 30. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
"Surface mount reflow soldering description".
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Product data sheet
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NFC controller with integrated firmware, supporting all NFC Forum modes
18 Abbreviations
Table 47. Abbreviations
PN7120
Product data sheet
COMPANY PUBLIC
Acronym
Description
API
Application Programming Interface
ASK
Amplitude Shift keying
ASK modulation
index
The ASK modulation index is defined as the voltage ratio (Vmax - Vmin)/
(Vmax + Vmin) × 100 %
Automatic device
discovery
Detect and recognize any NFC peer devices (initiator or target) like: NFC
initiator or target, ISO/IEC 14443-3, -4 Type A&B PICC, MIFARE Classic and
MIFARE Ultralight PICC, ISO/IEC 15693 VICC
BPSK
Bit Phase Shift Keying
Card Emulation
The IC is capable of handling a PICC emulation on the RF interface including
part of the protocol management. The application handling is done by the
host controller.
DEP
Data Exchange Protocol
DSLDO
Dual Supplied LDO
FW
FirmWare
HPD
Hard Power Down
LDO
Low Drop Out
LFO
Low Frequency Oscillator
MOSFET
Metal Oxide Semiconductor Field Effect Transistor
MSL
Moisture Sensitivity Level
NCI
NFC Controller Interface
NFC
Near Field Communication
NFCC
NFC Controller, PN7120 in this data sheet
NFC Initiator
Initiator as defined in ISO/IEC 18092 or ECma 340: NFCIP-1 communication
NFCIP
NFC Interface and Protocol
NFC Target
Target as defined in ISO/IEC 18092 or ECma 340: NFCIP-1 communication
NRZ
Non Return to Zero
P2P
Peer to Peer
PCD
Proximity Coupling Device. Definition for a Card reader/writer device
according to the ISO/IEC 14443 specification or MIFARE Classic
PCD -> PICC
Communication flow between a PCD and a PICC according to the ISO/IEC
14443 specification or MIFARE Classic
PICC
Proximity Interface Coupling Card. Definition for a contactless Smart Card
according to the ISO/IEC 14443 specification or MIFARE Classic
PICC-> PCD
Communication flow between a PICC and a PCD according to the ISO/IEC
14443 specification or MIFARE Classic
PMOS
P-channel MOSFET
PMU
Power Management Unit
PSL
Parameter SeLection
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NFC controller with integrated firmware, supporting all NFC Forum modes
PN7120
Product data sheet
COMPANY PUBLIC
Acronym
Description
TXLDO
Transmitter LDO
UM
User Manual
VCD
Vicinity Coupling Device. Definition for a reader/writer device according to the
ISO/IEC 15693 specification
VCO
Voltage Controlled Oscillator
VICC
Vicinity Integrated Circuit Card
WUC
Wake-Up Counter
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NFC controller with integrated firmware, supporting all NFC Forum modes
19 References
PN7120
Product data sheet
COMPANY PUBLIC
[1]
NFC Controller Interface
(NCI) Technical
Specification
— V1.0
[2]
ISO/IEC 14443
— parts 2: 2001 COR 1 2007 (01/11/2007), part 3: 2001
COR 1 2006 (01/09/2006) and part 4: 2nd edition 2008
(15/07/2008)
[3]
I C Specification
— I C Specification, UM10204 rev4 (13/02/2012)
[4]
PN7120 User Manual
— UM10819 PN7120 User Manual
[5]
PN7120 Hardware Design — AN11565 PN7120 Hardware Design Guide
- Guide
[6]
PN7120 Antenna and
Tuning Design Guide
— AN11564 PN7120 Antenna and Tuning Design Guide
[7]
ISO/IEC 18092 (NFCIP-1)
— edition, 15/032013. This is similar to Ecma 340.
[8]
ISO/IEC 15693
— part 2: 2nd edition (15/12/2006), part 3: 1st edition
(01/04/2001)
[9]
PN7120 Low-Power Mode — AN11562 PN7120 Low-Power Mode Configuration
Configuration
2
2
[10] ISO/IEC 21481 (NFCIP-2)
— edition, 01/07/2012. This is similar to Ecma 352.
[11] NFC Forum Device
Requirements
— V1.3
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NFC controller with integrated firmware, supporting all NFC Forum modes
20 Revision history
Table 48. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PN7120 v. 3.5
20180611
Product data sheet
-
PN7120 v. 3.4
Modifications:
• Editorial updates
PN7120 v. 3.4
20171018
Product data sheet
-
PN7120 v3.3
Modifications:
• Table 17 (Communication overview for NFC Forum T5T R/W mode) updated.
PN7120 v.3.3
20171005
Modifications:
• Descriptive title updated
• Section 2 "General description": Figure 2 updated
• MIFARE branding updated
PN7120 v.3.2
20160704
Modifications:
• Section 10.7.1.4: updated
PN7120 v.3.1
20151008
PN7120 v.3.0
-
PN7120 v.3.2
-
PN7120 v.3.1
Product data sheet
-
PN7120 v.3.0
20150727
Product data sheet
-
PN7120 v.2
PN7120 v.2
20150611
Preliminary data sheet
-
PN7120 v.1
PN7120 v.1
20150506
Objective data sheet
-
-
PN7120
Product data sheet
COMPANY PUBLIC
Product data sheet
Product data sheet
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NFC controller with integrated firmware, supporting all NFC Forum modes
21 Legal information
21.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PN7120
Product data sheet
COMPANY PUBLIC
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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NFC controller with integrated firmware, supporting all NFC Forum modes
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
21.4 Licenses
Purchase of NXP ICs with ISO/IEC 14443 type B functionality
This NXP Semiconductors IC is ISO/IEC
14443 Type B software enabled and is
licensed under Innovatron’s Contactless
Card patents license for ISO/IEC 14443 B.
RATP/Innovatron
Technology
The license includes the right to use the IC
in systems and/or end-user equipment.
Purchase of NXP ICs with NFC technology
Purchase of an NXP Semiconductors IC that complies with one of the
Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/
IEC 21481 does not convey an implied license under any patent right
infringed by implementation of any of those standards. Purchase of NXP
Semiconductors IC does not include a license to any NXP patent (or other
IP right) covering combinations of those products with other products,
whether hardware or software.
21.5 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
2
I C-bus — logo is a trademark of NXP B.V.
MIFARE — is a trademark of NXP B.V.
DESFire — is a trademark of NXP B.V.
ICODE and I-CODE — are trademarks of NXP B.V.
MIFARE Ultralight — is a trademark of NXP B.V.
MIFARE Classic — is a trademark of NXP B.V.
PN7120
Product data sheet
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NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.
Tab. 11.
Tab. 12.
Tab. 13.
Tab. 14.
Tab. 15.
Tab. 16.
Tab. 17.
Tab. 18.
Tab. 19.
Tab. 20.
Tab. 21.
Tab. 22.
Tab. 23.
Tab. 24.
Quick reference data .........................................5
Ordering information ..........................................6
Marking code .....................................................7
PN7120 pin description ..................................... 9
System power modes description ................... 12
System power modes configuration ................ 12
System power modes description ................... 12
PN7120 power states ......................................13
Functional modes in active state .....................14
Functionality for I2C-bus interface ...................17
I2C-bus interface addressing .......................... 17
Crystal requirements ....................................... 18
PLL input requirements ................................... 19
Communication overview for ISO/IEC 14443
type A and read/write mode for MIFARE
Classic ............................................................. 26
Overview
for
FeliCa
Reader/Writer
communication mode ...................................... 27
Overview for ISO/IEC 14443B Reader/
Writer communication mode ............................28
Communication overview for NFC forum
T5T R/W mode ................................................29
Overview for Active communication mode .......30
Overview for Passive communication mode .... 31
Overview for ISO/IEC 14443A/MIFARE
Classic card communication mode ..................32
Overview for ISO/IEC 14443B card
communication mode ...................................... 33
Limiting values ................................................ 35
Operating conditions ....................................... 36
Thermal characteristics ................................... 37
PN7120
Product data sheet
COMPANY PUBLIC
Tab. 25.
Tab. 26.
Tab. 27.
Tab. 28.
Tab. 29.
Tab. 30.
Tab. 31.
Tab. 32.
Tab. 33.
Tab. 34.
Tab. 35.
Tab. 36.
Tab. 37.
Tab. 38.
Tab. 39.
Tab. 40.
Tab. 41.
Tab. 42.
Tab. 43.
Tab. 44.
Tab. 45.
Tab. 46.
Tab. 47.
Tab. 48.
Current consumption characteristics for
operating ambient temperature range ............. 38
Battery voltage monitor characteristics ............38
Reset timing .................................................... 38
Power-up timings ............................................ 39
Power-down timings ........................................ 39
Thermal threshold ........................................... 39
High-speed
mode
I2C-bus
timings
specification .....................................................40
Fast mode I2C-bus timings specification .........40
Input clock characteristics on XTAL1 when
using PLL ........................................................ 41
Pin characteristics for XTAL1 when PLL
input .................................................................41
Pin characteristics for 27.12 MHz crystal
oscillator .......................................................... 41
PLL accuracy .................................................. 41
VEN input pin characteristics .......................... 41
Pin characteristics for IRQ, CLK_REQ and
BOOST_CTRL .................................................42
Electrical characteristics of ANT1 and ANT2 ... 42
Input pin characteristics for RXN and RXP ......42
Output pin characteristics for TX1 and TX2 .....43
Output resistance for TX1 and TX2 .................43
Input pin characteristics for I2CADR0 ............. 44
Pin characteristics for I2CSDA and I2CSCL .... 44
SnPb eutectic process (from J-STD-020D) ..... 48
Lead-free process (from J-STD-020D) ............ 48
Abbreviations ...................................................50
Revision history ...............................................53
All information provided in this document is subject to legal disclaimers.
Rev. 3.5 — 11 June 2018
312435
© NXP B.V. 2018. All rights reserved.
56 / 58
PN7120
NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Fig. 14.
Fig. 15.
Fig. 16.
Fig. 17.
PN7120 transmission modes ............................ 2
PN7120 package marking (top view) ................ 7
PN7120 block diagram ......................................8
PN7120 pinning (bottom view) .......................... 9
PN7120 connection ......................................... 11
System power mode diagram ......................... 12
Polling loop: all phases enabled ......................15
Polling loop: low-power RF polling .................. 16
27.12 MHz crystal oscillator connection .......... 18
Input reference phase noise characteristics .... 19
PMU functional diagram ..................................20
VDD(TX) offset disabled behavior ...................21
VDD(TX) behavior when PN7120 is in
Standby state .................................................. 21
Battery voltage monitor principle ..................... 22
Resetting PN7120 via VEN pin ....................... 23
VBAT is set up before VDD(PAD) ...................24
VDD(PAD) and VBAT are set up in the same
time ..................................................................24
PN7120
Product data sheet
COMPANY PUBLIC
Fig. 18.
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.
Fig. 24.
Fig. 25.
Fig. 26.
Fig. 27.
Fig. 28.
Fig. 29.
Fig. 30.
VDD(PAD) is set up or cut-off after PN7120
has been enabled ........................................... 25
PN7120 power-down sequence ...................... 25
Read/write mode for ISO/IEC 14443 type A
and read/write mode for MIFARE Classic ....... 26
FeliCa Reader/Writer communication mode
diagram ............................................................27
ISO/IEC
14443B
Reader/Writer
communication mode diagram ........................ 28
R/W mode for NFC forum T5T
communication diagram .................................. 28
NFCIP-1 communication mode ....................... 29
Active communication mode ........................... 30
Passive communication mode .........................31
Application schematic ......................................34
I2C-bus timings ............................................... 39
Package outline, VFBGA49, SOT1320-1,
MSL 1 ..............................................................46
Temperature profiles for large and small
components ..................................................... 49
All information provided in this document is subject to legal disclaimers.
Rev. 3.5 — 11 June 2018
312435
© NXP B.V. 2018. All rights reserved.
57 / 58
PN7120
NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
Contents
1
Introduction ......................................................... 1
2
General description ............................................ 2
3
Features and benefits .........................................3
4
Applications .........................................................4
5
Quick reference data .......................................... 5
6
Ordering information .......................................... 6
7
Marking .................................................................7
8
Block diagram ..................................................... 8
9
Pinning information ............................................ 9
9.1
Pinning ............................................................... 9
10
Functional description ......................................11
10.1
System modes .................................................12
10.1.1
System power modes ...................................... 12
10.1.2
PN7120 power states ...................................... 13
10.1.2.1 Monitor state ....................................................13
10.1.2.2 Hard Power Down (HPD) state ........................13
10.1.2.3 Standby state ...................................................14
10.1.2.4 Active state ...................................................... 14
10.1.2.5 Polling loop ...................................................... 14
10.2
Microcontroller ................................................. 16
10.3
Host interfaces .................................................16
10.3.1
I2C-bus interface ............................................. 17
10.3.1.1 I2C-bus configuration .......................................17
10.4
PN7120 clock concept .....................................17
10.4.1
27.12 MHz quartz oscillator ............................. 18
10.4.2
Integrated PLL to make use of external clock ...18
10.4.3
Low-power 20 MHz oscillator .......................... 20
10.4.4
Low-power 380 kHz oscillator ..........................20
10.5
Power concept .................................................20
10.5.1
PMU functional description .............................. 20
10.5.2
DSLDO: Dual Supply LDO .............................. 20
10.5.3
TXLDO ............................................................. 20
10.5.3.1 TXLDO limiter .................................................. 22
10.5.4
Battery voltage monitor ....................................22
10.6
Reset concept ..................................................22
10.6.1
Resetting PN7120 ............................................22
10.6.2
Power-up sequences ....................................... 23
10.6.2.1 VBAT is set up before VDD(PAD) ................... 23
10.6.2.2 VDD(PAD) and VBAT are set up in the same
time .................................................................. 24
10.6.2.3 PN7120 has been enabled before
VDD(PAD) is set up or before VDD(PAD)
has been cut off .............................................. 24
10.6.3
Power-down sequence .................................... 25
10.7
Contactless Interface Unit ............................... 25
10.7.1
Reader/Writer communication modes ..............25
10.7.1.1 Communication mode for ISO/IEC 14443
type A, MIFARE Classic and Jewel/Topaz
PCD ................................................................. 26
10.7.1.2 FeliCa PCD communication mode ...................27
10.7.1.3 ISO/IEC 14443B PCD communication mode ... 27
10.7.1.4 R/W mode for NFC forum Type 5 Tag .............28
10.7.2
ISO/IEC 18092, Ecma 340 NFCIP-1
communication modes .....................................29
10.7.2.1 ACTIVE communication mode .........................30
10.7.2.2 Passive communication mode ......................... 30
10.7.2.3 NFCIP-1 framing and coding ........................... 31
10.7.2.4 NFCIP-1 protocol support ................................32
10.7.3
Card communication modes ............................ 32
10.7.3.1 ISO/IEC 14443A/MIFARE Classic card
communication mode .......................................32
10.7.3.2 ISO/IEC 14443B card communication mode ....33
10.7.4
Frequency interoperability ............................... 33
11
Application design-in information ................... 34
12
Limiting values .................................................. 35
13
Recommended operating conditions .............. 36
14
Thermal characteristics ....................................37
15
Characteristics .................................................. 38
15.1
Current consumption characteristics ................38
15.2
Functional block electrical characteristics ........ 38
15.2.1
Battery voltage monitor characteristics ............ 38
15.2.2
Reset via VEN ................................................. 38
15.2.3
Power-up timings ............................................. 39
15.2.4
Power-down timings ........................................ 39
15.2.5
Thermal protection ...........................................39
15.2.6
I2C-bus timings ................................................39
15.3
Pin characteristics ............................................41
15.3.1
XTAL1 and XTAL2 pins characteristics ........... 41
15.3.2
VEN input pin characteristics ...........................41
15.3.3
Pin characteristics for IRQ, CLK_REQ and
BOOST_CTRL ................................................. 42
15.3.4
ANT1 and ANT2 pin characteristics .................42
15.3.5
Input pin characteristics for RXN and RXP ...... 42
15.3.6
Output pin characteristics for TX1 and TX2 ..... 43
15.3.7
Input pin characteristics for I2CADR0 ..............44
15.3.8
Pin characteristics for I2CSDA and I2CSCL .... 44
16
Package outline .................................................46
17
Soldering of SMD packages .............................47
17.1
Introduction to soldering .................................. 47
17.2
Wave and reflow soldering .............................. 47
17.3
Wave soldering ................................................47
17.4
Reflow soldering .............................................. 48
18
Abbreviations .................................................... 50
19
References ......................................................... 52
20
Revision history ................................................ 53
21
Legal information .............................................. 54
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2018.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 June 2018
Document identifier: PN7120
Document number: 312435