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PN5180 SW quick start guide
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User manual
Document information
Information
Content
Keywords
PN5180, PN5180 SW design, PNEV5180B, NFC NXP Cockpit
Abstract
This user manual is related to the installation procedures of the PN5180
evaluation board, which are related to the installation of the SW sample
projects as well as the re-installation of the original LPC firmware to run the
NFC Cockpit. It describes the steps to be done to become acquainted with the
demo reader especially for SW development.
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Revision history
Revision history
Rev
Date
Description
1.7
20221130
• Updated to match latest released NFC Reader Library v07.05.00.
• Section 7 "Radio Equipment Directive (RED)": added
• Editorial updates
1.6
20180507
Editorial updates
1.5
20170511
MCUXpresso IDE description added
1.4
20170117
Updated description how to flash FW for the NFC Cockpit tool.
1.3
20170105
Updated examples descriptions, reworked firmware update
1.2
20161124
Updated examples descriptions
1.1
20160803
Note in Section 5 regarding the LPCXpresso version added HCE, NFC Forum and MIFARE
DESFire added to the Associated projects
Cockpit version changed from 2.2 to 2.3
Required LPCXpresso version changed from 7.9 to 8.1.4
RTOS options added
1.0
20151126
Initial version
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1
Introduction
This document is the continuation of the “AN11744 - PN5180 Quick start guide” and
describes the installation procedures of the SW development environment and handling
SW example projects using the NFC Reader Library prepared for the PN5180 evaluation
board.
It also describes how to reinstall the original LPC firmware binary to use the NFC Cockpit
again.
In this document, the term „MIFARE Classic card“ refers to a MIFARE Classic IC-based
contactless card, the term “MIFARE DESFire card” refers to a MIFARE DESFire ICbased contactless card, the term “MIFARE Ultralight card” refers to a MIFARE Ultralight
IC-based contactless card.
Projects used and explained in this documentation are based on the NFC Reader Library
v07.05.00 NDA version:
Table 1. Example projects
Example projects delivered with the NFC Reader Library
Example
Description
NfcrdlilbEx1_Basic Discovery
Loop
Explains how to poll for different technologies (Tag, P2P, HCE),
detect and report them. Default configuration parameters are
used.
NfcrdlilbEx3_NFCForum
Explains how to configure the NFC Reader Library for different
P2P modes such as Active Mode, Target Mode, Initiator Mode
and SNEP Client/Server.
NfcrdlilbEx4_MIFARE Classic
Explains the usage of MIFARE Classic card commands.
NfcrdlilbEx5_ISO15693
Explains the usage of this technology and provides an overview
about the most common commands.
NfcrdlilbEx6_LPCD
Explains and demonstrates the usage of LPCD (Low-Power
Card Detection) and its calibration.
NfcrdlibEx7_MIFAREPlus
Explains the usage of a MIFARE Plus card and pre-personal
ization of it.
NfcrdlilbEx8_ HCE_T4T
Explains how to emulate an NFC Forum Type 4 Tag supporting
read and write operations.
NfcrdlilbEx9_ NTagI2C
Explains NTAG-I2C specific commands.
NfcrdlilbEx10_
MIFAREDESFire
Explains the usage of MIFARE DESFire cards. (This example
is delivered with the NFC Reader Library version available via
Secure Files on NXP.com)
Nfcrdlib_SimplifiedAPI ISO
Explains how to use simplified API with different types of cards.
Table 2. Compliance applications
Compliance applications aim to help in certain certification scenarios.
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Example
Description
Nfcrdlib_EMVCo_AnalogComplApp
Used to perform EMVCo 3.0 L1 Analog
compliance validation.
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Table 2. Compliance applications...continued
Compliance applications aim to help in certain certification scenarios.
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Example
Description
Nfcrdlib_EMVCo_InteropComplApp
This example is an Interoperability loopback
Application which is used to perform EMVCo
IOP(L1) with add-on(TTA Bulletin No.195)
compliance validation.
Nfcrdlib_EMVCo_LoopBackComplApp
This example is a loopback Application which
is used to perform EMVCo3.0 L1 digital/analog
compliance validation.
Nfcrdlib_ISO10373_6_PCD_ComplApp
This example is an application which is used
to perform ISO 10373-6 PCD compliance
validation.
Nfcrdlib_ISO10373_6_PICC_ComplApp
This application is used to perform ISO 10373-6
PICC compliance validation.
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2
Managing the PN5180 SW projects with MCUXpresso IDE
The PN5180 SW projects are delivered in a zip package and can be extracted, edited,
compiled, and linked with MCUXpresso IDE.
The MCUXpresso IDE is a low-cost highly integrated software development environment
for NXP MCUs based on Arm Cortex-M cores. It includes all the tools necessary to
develop high-quality software solutions in a timely and cost-effective fashion.
MCUXpresso IDE is based on Eclipse and has many enhancements to simplify
development with NXP microcontrollers. It also features the industry-standard GNU tool
chain, with a choice of a proprietary optimized C library or the standard “Newlib” library.
The MCUXpresso IDE can build an executable of any size with full code optimization.
Designed for simplicity and ease of use, the MCUXpresso IDE provides software
engineers a quick and easy way to develop their applications.
This tool can freely be downloaded from the MCUXpresso website [1]. Before one can
download the software, it is necessary to create an account. Creating an account is free.
2.1 Development environment
To use the PN5180 prepared software package, all components listed in Table 3 are
required.
Table 3. Development environment
Item
Version
Description
PN5180EV5180B
1.0 or higher
PN5180 Customer evaluation board (hardware)
LPC-Link 2 or MCU-Link
1.0
Standalone debug adapter (hardware)
MCUXpresso IDE
11.6.0 or higher Development IDE (PC software)
2.2 Installation procedure of the MCUXpresso IDE
The MCUXpresso IDE is installed into a single directory, of your choice. Unlike many
software packages, the MCUXpresso IDE does not install or use any keys in the
Windows Registry, or use or modify any environment variables (including PATH),
resulting in a very clean installation that does not interfere with anything else on your PC.
Should you wish to use the command-line tools, a command file is provided to set up the
path for the local command window.
Multiple versions can be installed simultaneously without any issues.
The installation starts after double-clicking the installer file.
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Figure 1. Checkbox for NXP debug drivers
Make sure, the checkbox for installing the NXP debug drivers is activated.
During the installation, the user is asked to install some required drivers. The installation
of these drivers shall be accepted.
Figure 2. Windows security dialog
After the setup wizard, has finished, the newly installed IDE can be launched.
Figure 3. MCUXpresso IDE
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2.3 Importing provided SW example projects
The use of quick start panel provides rapid access to the most commonly used features
of the MCUXpresso IDE. Quickstart panel allows easy import projects, create new
projects, build, and debug projects.
The sequence of installing the software projects is indicated:
•
•
•
•
Start the MCUXpresso IDE.
Open new or dedicated workspace
Select the option “Import project(s)” (see picture below).
Browse the root directory of the previously unzipped NFC Reader Library.
– The NFC Reader Library package, provided as .zip file, has to be unpacked first.
Importing as archive will not work and result in broken links.
• The software package is ready for use.
Figure 4. Importing project (1)
In the Quickstart panel on the left-hand side, choose “Import projects(s)”.
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Figure 5. Importing project (2)
Browse the desired package and click “Next”.
Note: Make sure that "Copy projects into workspace" is not checked.
Figure 6. Importing project (3)
For a working demo project, you must import at least four subprojects. One example
project, the NFC Reader Library, FreeRTOS, one chip library and one board library.
When the import process has finished, one can start browsing the code.
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2.4 Building projects
Building projects in a workspace is a simple case of using the Quickstart Panel - ‘Build
all projects’. Alternatively, a single project can be selected in the “Project Explorer View”
and built separately. Note that building a single project may also trigger a build of any
associated library projects.
The project can be built as shown in Figure 7.
Figure 7. Building the project
As a part of the build output, the binary for the “User Flash” file is created. This binary file
can be later also used to update LPC1769 flash memory via USB mass storage interface.
Figure 8. List of projects in “Project Explorer view
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The project settings, compiler and link flags can be changed in the project properties
dialog. To open the project properties dialog, select appropriate project in the “Project
Explorer View” and click “Edit ‘selected-project’ project settings”.
2.5 Running and debugging a project
This description shows how to run the “NfcrdlibEx1_basicDiscoveryLoop” example
application for the PN5180 evaluation development board. The same basic principles
apply for all other examples. In cases where example needs additional configuration this
will be detailed described in the example description.
PN5180 evaluation board should be connected to the computer via LPC-Link 2, as
shown in Figure 9.
Figure 9. PNEV5180B with LPC-Link 2
When debug is started, the program is automatically downloaded to the target and it
is programmed to the LPC1769 flash memory. A default breakpoint is set on the first
instruction in main (). The application is started (by simulating a processor reset), and
code is executed until the default breakpoint is hit.
To start debugging your application on the PN5180, simply highlight the project in the
Project Explorer and then in the Quickstart Panel click Debug, as shown in Figure 10.
The MCUXpresso IDE will first build application, flash application binary and then will
start with debugging.
Before running the project, ensure that the correct microcontroller and the correct build
configurations are chosen. Information about how to do this can be found in the Figure 23
and Section 6.3.
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Figure 10. Launch debug session
Figure 11. Successful compile
Select “LPC-Link 2” as a debug probe.
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Figure 12. Select the launch configuration
After successful software upload, the execution of the project starts immediately, but
might halt at the initial breakpoint. To resume execution, click the resume button.
Figure 13. Debug project
In the console window, application debug outputs of the execution can be seen.
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Figure 14. Application printouts in console window
After the execution has reached the end of the main function, click the Terminate button
to stop the execution. Otherwise rerun of the project will be possible.
Buttons in the debug toolbar provide next functionalities:
Figure 15. Debug buttons
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3
Managing the PN5180 SW projects with Linux and Kinetis platform
Detailed description and guideline, how to import and manage NFC NXP Reader Library
projects for Linux and Kinetis platform, check:
• AN11802 - NFC Reader Library for Linux Installation Guidelines, see [3]
• AN11908 - NFC Reader Library for FRDM-K82F Installation Guidelines, see [4]
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4
Associated projects
All example projects are available for download at the PN5180 product page in the
documents section and are being distributed in one single file.
All projects are packaged into a single installer file. After downloading the zip file, extract
it and run the installer. The installer makes a copy of all documents and SW on the hard
disk.
By default, the projects are preconfigured to be run on the PNEV5180B development
board. This is defined by preprocessor directive PHDRIVER_LPC1769PN5180_BOARD
(properties-> settings->preprocessor) and by macro in “../intfs/ph_NxpBuild_App.h”.
//#define NXPBUILD__PHHAL_HW_RC663
#define NXPBUILD__PHHAL_HW_PN5180
Running the projects with, or without FreeRTOS
All projects described in the following subchapters can be configured to run with or
without FreeRTOS operating system. To enable/disable FreeRTOS support, define
preprocessor directive (properties-> settings->preprocessor) PH_OSAL_FREERTOS or
PH_OSAL_NULLOS.
4.1 Example 1 – Basic Discovery Loop
The Discovery Loop can be seen as the entry point when starting to communicate with
an NFC tag or device. It scans the close environment for tags and devices of different
technologies.
Example is implemented to work in POLL and LISTEN mode of the discovery loop.
Information (like UID, SAK, and product type of MIFARE IC) of the detected tags are
printed out. It also prints information when it gets activated as a target by an external
initiator/reader. Whenever multiple technologies are detected, example select first
detected technology and resolve it.
In passive poll mode, Low Power Card Detection (LPCD) is enabled.
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Figure 16. Discovery Loop in Poll mode
The core function of this example is “BasicDiscoveryLoop_Demo()”, where initialization
of the NFC Reader library and polling for NFC technologies is implemented. After each
polling loop, application is checking polling result and printout information about the
detected tags or devices.
This example is using default DiscoveryLoop configuration, which enables all supported
technologies and it is limited to one device for each technology.
Table 4. Supported technologies
ISO14443P3A
ISO15693- SLI
FeliCa
TYPEF_TARGET_PASSIVE
ISO14443P4A
ISO18000P3M3
TYPEA_TARGET_PASSIVE
TYPEF_TARGET_ACTIVE
ISO18092MPI
ISO14443P3B
TYPEA_TARGET_ACTIVE
4.2 Example 3 – NFC Forum
Explains how to configure the NFC Reader Library for different P2P modes such as
Active Mode, Target Mode, Initiator Mode and SNEP Client/Server.
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In SNEP Server mode, the example waits for a connection from a SNEP Client. When
the connection between client and server is established, client sends a data, and server
read it. The application displays read data in the console window of the LPCXpresso IDE.
In SNEP Client mode, the application tries to connect to a SNEP Server. Once the
connection is established, it transmits an NDEF message to the server.
4.3 Example 4 – MIFARE Classic card communication
This example demonstrates how to configure “DiscoveryLoop” to poll for only one
technology and how to resolve detected card, in this example MIFARE Classic is used.
Once MIFARE Classic card is activated, application printout information like UID, ATQA,
and SAK and perform the authentication with MIFARE Classic card default key. After
successful authentication, basic read/write operations are implemented.
This example is good start in case of working with only one card or to see how to
manage MIFARE Classic cards.
4.4 Example 5 - ISO/IEC 15693
Similar to the previous example, this one is also using only one technology, in that case
ISO/IEC 15693. “DiscoveryLoop” is configured to resolve only one device and in the
example it is shown how to change TX Guard Time for T5T cards. This is implemented in
“phApp_Init()” function.
Once the ICODE SLI tag is resolved and activated, the application prints out the related
card information, like type and UID, and it will read from and write to the memory of the
active tag.
This example is good start in case of working with only one card or to see how to
manage ISO15693 type of the cards.
For a much more extensive example, demonstrating the use of ISO/IEC 15693 and
ISE/IEC 18000-3 Mode 3 tags (ICODE SLI and ICODE ILT). In order to assure ICODE
SLI and ILT detection, check delay-related definitions in the hardware abstraction layer.
Settings are described in Section 4.
4.5 Example 6 - Low-Power Card Detection (LPCD)
This examples shows calibration and usage of the LPCD.
The LPCD calibration and actual card detection loops are separated to show the
capabilities and handling.
For further information on LPCD see chapter "Low-Power Card Detection" (LPCD) in the
PN5180 Datasheet.
4.6 Example 7 – MIFARE Plus
The MIFARE Plus example polls and checks for MIFARE Plus EV1/EV2 cards. After the
detection of a tag, according to the security level, it will demonstrate pre-personalization
in security level-0, SL1-SL3 mixed mode in security level 1 and EVO/EV1 secure
messaging in security level-3.
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4.7 Example 8 – HCE T4T
Example 8 implements a Type 4 Tag card emulation according to NFC Forum Type 4 Tag
specification. The example supports all specified commands such as Select, ReadBinary,
UpdateBinary.
With this example, our reader is in card emulation mode (HCE) and it support reading
and writing data. Default data is configured as an NDEF message as a url www.nxp.com.
The maximum NDEF length that the reader can write is limited by NDEF file size used in
example (default configured as 1024 bytes).
4.8 Example 9 – NTAG-I2C
The NTAG-I2C example demonstrates the use of special features which are supported
by NTAG-I2C. By using POLL mode of the discovery loop, example detect the NTAG
2
I C cards and displays detected tag information like UID, ATQA, SAK, version info and
perform “Page Read” and “PageWrite” commands.
For more details about the NTAG-I2C and its functionalities, consult the related product
page [2]
4.9 Example 10 – MIFARE DESFire card communication
The MIFARE DESFire example demonstrates how to use MIFARE DESFire EV1 cards.
Once MIFARE DESFire card is resolved and activated, it displays MIFARE DESFire
applications created by this example previously. It displays 32bit signed integer which is
incremented after each successful detection of tag.
In case no application is present on the tag, new application is created with two new files
to hold NXPNFCRDLIB version used to create this application and another file to hold
32bit signed integer.
Note: This example including the required modules of the NFC Reader Library is only
available via Secure Files on NXP.com.
4.10 Simplified API ISO
This example is a reference application to demonstrate the usage of Simplified API with
ISO profile. Application contains example of Type A Layer 4, Type B Layer 4, ISO/IEC
15693 and ISO/IEC 180003m3 and MIFARE DESFire card, MIFARE Ultralight card and
MIFARE Classic card communication.
Example demonstrates how to use simplified API, which require, after successful library
initialization, only three commands:
• phNfcLib_Activate()
• phNfcLib_Transmit()
• phNfcLib_Receive()
4.11 EMVCo Analog Compliance Application
This example contains three modes of operations within itself for the user to choose as
below:
• EMVCo loopback application
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• Trans send Type A application
• Trans send Type B application
Above application modes are used to perform EMVCo 3.0 L1 analog compliance
validation. The CPU frequency configured for the host controller platforms should be
sufficient enough to meet EMVCo timing requirements.
4.12 EMVCo Interoperability Compliance Application
This example is an Interoperability loopback Application which is used to perform EMVCo
IOP (L1) with add-on (TTA Bulletin No.195) compliance validation.
The CPU frequency configured for the Host controller platforms should be sufficient
enough to meet EMVCo timing requirements.
The running application can now be used for EMVCo IOP with add-on (TTA Bulletin
No.195) Test suite validation. Test success indicated by Green LED and GPIO and fail
indicated by Red LED and GPIO.
PNEV5180B v2.0 Customer evaluation board LED's and GPIO's indication:
- Red LED - LD201
- Green LED - LD203
- GPIO (indicates Success) - TXD
- GPIO (indicates Fail) - RXD
Success: Green LED On, GPIO high, 500 milliseconds delay GPIO Low and Green LED
Off
Fail: Red LED On, GPIO High, 500 milliseconds delay, GPIO Low and RED LED Off
4.13 EMVCo LoopBack Compliance Application
This example is a LoopBack Application which is used to perform EMVCo3.0 L1 digital/
analog compliance validation.
The CPU frequency configured for the host controller platforms should be sufficient
enough to meet EMVCo timing requirements.
4.14 ISO10373 6 PCD Compliance Application
This example is an application which is used to perform ISO 10373-6 PCD compliance
validation. This example has to be executed in the DUT which has an ISO 14443 based
PCD implementation. The ISO 10373-6 test methods verify the compliance with the ISO
14443 protocols.
This application is developed based on Micropross user manual of ISO 10373-6 PCD
Test Suite v2.0.2 which is executed using MP500 TCL3. It is not executed with other tool
ISO 10373-6 PCD test suite.
4.15 ISO10373 6 PICC Compliance Application
This application is used to perform ISO 10373-6 PICC compliance validation. This
application has to be executed using DUT which must be tested against ISO 10373-6
PICC test methods that verifies the compliance with ISO 14443 protocols.
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This application is developed based on Micropross user manual of ISO 10373-6 PICC
Test Suite v1.3.2 which is executed using MP500 TCL3. It is not executed with other tool
ISO 10373-6 PICC test suite.
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5
Flashing firmware on the LPC1769
Flashing VCOM firmware is the procedure needed to prepare PN5180 evaluation board
to be used with the NFC Cockpit tool. The NFC Cockpit tool is a GUI tool designed to
help finding the right analog settings for your PCB.
VCOM firmware which must be flashed on the LPC1769 is provided with the installer
package of the NXP NFC Cockpit application. It can be found in “\NxpNfcCockpit_
v6.8.0.0\firmware\Secondary_PN5180” folder.
This folder contains several binaries which can be used as VCOM firmware application:
• BootLoader_And_Nfcrdlib_SimplifiedAPI_EMVCo_Secondary.bin
• BootLoader_And_phRfOnOff_Secondary.bin
• BootLoader_And_phUcBal_Secondary.bin
Steps required to flash VCOM application:
Connect the LPC-LINK2 debugger to the PN5180 board as shown in Figure 17.
1. Use an LPC-Link 2 debugger and make the connections with PN5180 board
Figure 17. LPC-Link 2 - PN5180 board connection
Use the MCUXpresso program Flash utility flash to flash bootloader binary to the MCU.
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2. Create (or Open an existing MCUXpresso project) and set the MCU type to LPC1769
3. Choose “Program flash” from menu bar
4. Select bootloader binary, for example, ‘NxpNfcCockpit_v3.10.0.0\firmware\Secondary_
PN5180\BootLoader_And_Nfcrdlib_SimplifiedAPI_EMVCo_Secondary.bin’
5. Set base address to 0x00
6.Press “OK” button and flash the bootloader
Figure 18. Flashing Bootloader.bin
Flash the binary on the PNEV5180B and ensure that the process succeeds.
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7. Inspect program flash output
Figure 19. Flash report
Disconnect the USB cable, remove LPC-Link 2 connection and reset the board.
The board appears as a VCOM device:
Figure 20. PN5180 Board Correctly installed
The PN5180 based evaluation board is ready now to be used with the NXP NFC Cockpit
tool.
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6
Supplementary notes
6.1 General software architecture
The software of the reference reader is based on the NFC Reader Library, see Figure 21.
It intends to be simple, modular, easily readable, and quickly portable by all the
customers. This philosophy is reflected in its architecture which is divided into 4 layers:
•
•
•
•
BAL (Bus abstraction layer),
HAL (Hardware abstraction layer)
PAL (Protocol abstraction layer)
AL (Abstraction layer)
Figure 21. Architecture of the NFC Reader Library
6.1.1 Bus abstraction layer
This layer offers functions to abstract the hardware parts of the LPC1XXX microcontroller.
These functions use the specific libraries available for the LPC1XXX family
microcontroller. Based on these stacks, the communication routines for the relevant
physical media I2C/SPI can be easily designed. These drivers are specific for the
LPC1XXX family and therefore cannot be ported to other microcontrollers.
6.1.2 Hardware abstraction layer
This layer offers functions to abstract the hardware parts of the transceiver CLRC663.
6.1.3 Protocol abstraction layer
Every PAL function is a low-level function realizing a single functionality. It is
encapsulated in a module which is independent from the others. The user can easily
design their application by doing a drag-and-drop of the relevant module.
The following PAL modules are available in this software package:
• ISO/IEC 14443-3A,
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•
•
•
•
•
•
ISO/IEC 14443-3B,
ISO/IEC 14443-4A/B,
MIFARE products
FeliCa
NFC Initiator
NFC Target
6.1.4 Application layer
Lying on the previous software layers, the application layer is on top of the reader
software package. It combines elements of the previous three parts into high-level
functionalities.
6.2 Build configuration
All the projects mentioned in Section 3 are available in debug configuration. Additionally,
the Polling project comprises the release configuration.
• Debug configuration
This configuration is mainly used when the target board is attached to the PC with the
JTAG debugger. It allows the display of debug messages in the console window, which is
useful in the early stage of the project.
• Release configuration
Once the project is debugged and mature, it might be interesting to use the release
configuration, to use the hardware standalone. No debug messages are displayed in the
console window.
The build configuration can be selected as follows:
• Click the project in the project window of the MCUXpresso IDE,
• Right click of the mouse ➔ Select Build Configuration,
• Set active DebugLPC1769 build (or ReleaseLPC1769 build) for LPC1769.
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Figure 22. Select the build configuration
6.3 Setting the MCU
There are many LPC microcontrollers supported by the MCUXpresso IDE build in
compiler. Before compiling a project, the correct MCU must be set.
• Right-click the project ➔ choose properties (at the bottom)
• C/C++ build ➔ MCU settings ➔ expand desired LPC700 MCU group ➔ choose the
correct microcontroller ➔ click OK
Figure 23. Selection of the LPC1769 MCU
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6.4 Level of compiler optimization
When the code size at the current compiler level overloads the FLASH size of the target
board (512 K for the Arm-based microcontroller LPC1769), a higher compiler optimization
level can be selected to reduce the code size of the project.
The following steps can be followed to select a level of compiler optimization:
•
•
•
•
Click the application project in the project window of the LPCXpresso IDE,
Right click of the mouse ➔ Select properties ➔ Select C/C++ build,
Select Settings ➔ Optimization,
Choose the desired level in the combo box.
Figure 24. Select the level of optimization
6.4.1 Optimization issues
When optimization is enabled, it reorders code. What this means is that the code from
multiple C lines will be intermingled. In addition, assignments and initializations might be
pulled out of loops so they are only executed once. Changes like these make the code
confusing to debug. Some symptoms one might see are breakpoints that only work the
first time through, or seeing the debugger’s current line indicator fail to advance or even
move backward when clicking step. It is best to always use –O0 for debugging.
6.5 Removing the initial breakpoint on debug startup
When the debugger starts, it automatically sets a breakpoint at the first statement in the
“main()” function. One can remove this breakpoint as follows:
1. Right-click the project and choose Launch Configurations ➔ Edit current…
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Figure 25. Edit Launch Configurations
Uncheck “Stop on startup at main” option.
Figure 26. Disable breakpoint at main()
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7
Radio Equipment Directive (RED)
The following information is provided per Article 10.8 of the Radio Equipment Directive
2014/53/EU:
(a) Frequency bands in which the equipment operates.
(b) The maximum RF power transmitted.
Table 5. Characteristics
PN
RF Technology
(a) Freq Ranges (EU)
(b) Max Transmitted
Power
PNEV5180B
Near Field
Communication
13.56 MHz +/- 7 kHz
-9 dBm
EUROPEAN DECLARATION OF CONFORMITY (Simplified DoC per Article 10.9 of the
Radio Equipment Directive 2014/53/EU). This apparatus, namely PNEV5180B demo
board, conforms to the Radio Equipment Directive 2014/53/EU.
The full EU Declaration of Conformity for this apparatus can be found at this location:
https://www.nxp.com/products/:OM25180FDK.
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8
References
[1]
[2]
[3]
[4]
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MCUXpresso download website https://www.nxp.com/design/:MCUXPRESSO
NTAG-I2C https://www.nxp.com/products/:NT3H1101_NT3H1201
Application note - AN11802 NFC Reader Library for Linux Installation Guidelines
Application note - AN11908 NFC Reader Library for FRDM guidelines
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9
Legal information
9.1 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
9.2 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
towards customer for the products described herein shall be limited in
accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their
applications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
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Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Suitability for use in non-automotive qualified products — Unless
this data sheet expressly states that this specific NXP Semiconductors
product is automotive qualified, the product is not suitable for automotive
use. It is neither qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts no liability for
inclusion and/or use of non-automotive qualified products in automotive
equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warranty
of the product for such automotive applications, use and specifications, and
(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Evaluation products — This product is provided on an “as is” and “with all
faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates
and their suppliers expressly disclaim all warranties, whether express,
implied or statutory, including but not limited to the implied warranties of noninfringement, merchantability and fitness for a particular purpose. The entire
risk as to the quality, or arising out of the use or performance, of this product
remains with customer.
In no event shall NXP Semiconductors, its affiliates or their suppliers
be liable to customer for any special, indirect, consequential, punitive
or incidental damages (including without limitation damages for loss of
business, business interruption, loss of use, loss of data or information, and
the like) arising out the use of or inability to use the product, whether or not
based on tort (including negligence), strict liability, breach of contract, breach
of warranty or any other theory, even if advised of the possibility of such
damages.
Notwithstanding any damages that customer might incur for any reason
whatsoever (including without limitation, all damages referenced above and
all direct or general damages), the entire liability of NXP Semiconductors,
its affiliates and their suppliers and customer’s exclusive remedy for all of
the foregoing shall be limited to actual damages incurred by customer based
on reasonable reliance up to the greater of the amount actually paid by
customer for the product or five dollars (US$5.00). The foregoing limitations,
exclusions and disclaimers shall apply to the maximum extent permitted by
applicable law, even if any remedy fails of its essential purpose.
Translations — A non-English (translated) version of a document, including
the legal information in that document, is for reference only. The English
version shall prevail in case of any discrepancy between the translated and
English versions.
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Security — Customer understands that all NXP products may be subject to
unidentified vulnerabilities or may support established security standards or
specifications with known limitations. Customer is responsible for the design
and operation of its applications and products throughout their lifecycles
to reduce the effect of these vulnerabilities on customer’s applications
and products. Customer’s responsibility also extends to other open and/or
proprietary technologies supported by NXP products for use in customer’s
applications. NXP accepts no liability for any vulnerability. Customer should
regularly check security updates from NXP and follow up appropriately.
Customer shall select products with security features that best meet rules,
regulations, and standards of the intended application and make the
ultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may be
provided by NXP.
NXP has a Product Security Incident Response Team (PSIRT) (reachable
at PSIRT@nxp.com) that manages the investigation, reporting, and solution
release to security vulnerabilities of NXP products.
NXP — wordmark and logo are trademarks of NXP B.V.
AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE,
Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle,
Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore,
Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS,
ULINKpro, μVision, Versatile — are trademarks or registered trademarks
of Arm Limited (or its subsidiaries) in the US and/or elsewhere. The related
technology may be protected by any or all of patents, copyrights, designs
and trade secrets. All rights reserved.
DESFire — is a trademark of NXP B.V.
FeliCa — is a trademark of Sony Corporation.
ICODE and I-CODE — are trademarks of NXP B.V.
MIFARE — is a trademark of NXP B.V.
Purchase of NXP ICs with NFC technology — Purchase of an NXP
Semiconductors IC that complies with one of the Near Field Communication
(NFC) standards ISO/IEC 18092 and ISO/IEC 21481 does not convey an
implied license under any patent right infringed by implementation of any of
those standards. Purchase of NXP Semiconductors IC does not include a
license to any NXP patent (or other IP right) covering combinations of those
products with other products, whether hardware or software.
User manual
Notice: All referenced brands, product names, service names, and
trademarks are the property of their respective owners.
Kinetis — is a trademark of NXP B.V.
9.3 Licenses
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9.4 Trademarks
MIFARE Classic — is a trademark of NXP B.V.
MIFARE Plus — is a trademark of NXP B.V.
MIFARE Ultralight — is a trademark of NXP B.V.
NTAG — is a trademark of NXP B.V.
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Tables
Tab. 1.
Tab. 2.
Tab. 3.
Example projects ...............................................3
Compliance applications ................................... 3
Development environment ................................ 5
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Tab. 4.
Tab. 5.
Supported technologies ...................................16
Characteristics .................................................29
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Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Checkbox for NXP debug drivers ......................6
Windows security dialog ....................................6
MCUXpresso IDE .............................................. 6
Importing project (1) ..........................................7
Importing project (2) ..........................................8
Importing project (3) ..........................................8
Building the project ........................................... 9
List of projects in “Project Explorer view ........... 9
PNEV5180B with LPC-Link 2 ..........................10
Launch debug session .................................... 11
Successful compile ..........................................11
Select the launch configuration ....................... 12
Debug project ..................................................12
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Fig. 14.
Fig. 15.
Fig. 16.
Fig. 17.
Fig. 18.
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.
Fig. 24.
Fig. 25.
Fig. 26.
Application printouts in console window .......... 13
Debug buttons .................................................13
Discovery Loop in Poll mode .......................... 16
LPC-Link 2 - PN5180 board connection .......... 21
Flashing Bootloader.bin ...................................22
Flash report ..................................................... 23
PN5180 Board Correctly installed ................... 23
Architecture of the NFC Reader Library .......... 24
Select the build configuration .......................... 26
Selection of the LPC1769 MCU ...................... 26
Select the level of optimization ........................27
Edit Launch Configurations ............................. 28
Disable breakpoint at main() ........................... 28
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Contents
1
2
2.1
2.2
2.3
2.4
2.5
3
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
5
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.2
6.3
6.4
6.4.1
6.5
7
8
9
Introduction ......................................................... 3
Managing the PN5180 SW projects with
MCUXpresso IDE .................................................5
Development environment .................................5
Installation procedure of the MCUXpresso
IDE ..................................................................... 5
Importing provided SW example projects .......... 7
Building projects ................................................ 9
Running and debugging a project ....................10
Managing the PN5180 SW projects with
Linux and Kinetis platform ...............................14
Associated projects .......................................... 15
Example 1 – Basic Discovery Loop ................. 15
Example 3 – NFC Forum ................................ 16
Example 4 – MIFARE Classic card
communication .................................................17
Example 5 - ISO/IEC 15693 ............................ 17
Example 6 - Low-Power Card Detection
(LPCD) ............................................................. 17
Example 7 – MIFARE Plus .............................. 17
Example 8 – HCE T4T .................................... 18
Example 9 – NTAG-I2C ...................................18
Example 10 – MIFARE DESFire card
communication .................................................18
Simplified API ISO ...........................................18
EMVCo Analog Compliance Application ..........18
EMVCo Interoperability Compliance
Application ....................................................... 19
EMVCo LoopBack Compliance Application ..... 19
ISO10373 6 PCD Compliance Application .......19
ISO10373 6 PICC Compliance Application ......19
Flashing firmware on the LPC1769 ................. 21
Supplementary notes ........................................24
General software architecture ..........................24
Bus abstraction layer ....................................... 24
Hardware abstraction layer ..............................24
Protocol abstraction layer ................................ 24
Application layer .............................................. 25
Build configuration ........................................... 25
Setting the MCU .............................................. 26
Level of compiler optimization ......................... 27
Optimization issues ..........................................27
Removing the initial breakpoint on debug
startup .............................................................. 27
Radio Equipment Directive (RED) ................... 29
References ......................................................... 30
Legal information .............................................. 31
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© 2022 NXP B.V.
All rights reserved.
For more information, please visit: http://www.nxp.com
Date of release: 5 December 2022
Document identifier: UM10954