PPC5121VY400

Freescale Semiconductor Data Sheet: Technical Data Document Number: MPC5121E Rev. 5, 02/2012 MPC5121E/MPC5123 MPC5121E/MPC5123  Data Sheet The MPC5121e/MPC5123 integrates a high performance e300 CPU core based on the Power Architecture® Technology with a rich set of peripheral functions focused on communications and systems integration. Major features of the MPC5121e/MPC5123 are: • e300 Power Architecture processor core • Power modes include doze, nap, sleep, deep sleep, and hibernate • AXE – Auxiliary Execution Engine • MBX Lite – 2D/3D graphics engine (not available in MPC5123) • DIU – Display interface unit • DDR1, DDR2, and LPDDR/mobile-DDR SDRAM memory controller • MEM – 128 KB on-chip SRAM • USB 2.0 OTG controller with integrated physical layer (PHY) • DMA subsystem • EMB – Flexible multi-function external memory bus interface • NFC – NAND flash controller • LPC – LocalPlus interface • 10/100Base Ethernet • PCI interface, version 2.3 • PATA – Parallel ATA integrated development environment (IDE) controller • SATA – Serial ATA controller with integrated physical layer (PHY) • SDHC – MMC/SD/SDIO card host controller • PSC – Programmable serial controller • I2C – inter-integrated circuit communication interfaces • S/PDIF – Serial audio interface • CAN – Controller area network • BDLC – J1850 interface • VIU – Video Input, ITU-656 compliant • RTC – On-Chip real-time clock © Freescale Semiconductor, Inc., 2010-2012. All rights reserved. 516 TEPBGA 27 mm x 27 mm • On-chip temperature sensor • IIM – IC Identification module Table of Contents 1 2 3 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.1 516-TEPBGA Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.2 Pinout Listings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Electrical and Thermal Characteristics . . . . . . . . . . . . . . . . . .17 3.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .17 3.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . .17 3.1.2 Recommended Operating Conditions . . . . . . . .18 3.1.3 DC Electrical Specifications. . . . . . . . . . . . . . . .19 3.1.4 Electrostatic Discharge . . . . . . . . . . . . . . . . . . .22 3.1.5 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . .23 3.1.6 Thermal Characteristics. . . . . . . . . . . . . . . . . . .24 3.2 Oscillator and PLL Electrical Characteristics . . . . . . . .25 3.2.1 System Oscillator Electrical Characteristics . . .26 3.2.2 RTC Oscillator Electrical Characteristics . . . . . .26 3.2.3 System PLL Electrical Characteristics. . . . . . . .26 3.2.4 e300 Core PLL Electrical Characteristics . . . . .27 3.3 AC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .28 3.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.3.2 AC Operating Frequency Data. . . . . . . . . . . . . .28 3.3.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.4 External Interrupts . . . . . . . . . . . . . . . . . . . . . . .32 3.3.5 SDRAM (DDR) . . . . . . . . . . . . . . . . . . . . . . . . .32 3.3.6 PCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.3.7 LPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.3.8 NFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 3.3.9 PATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.3.10 SATA PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4 5 6 3.3.11 FEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.3.12 USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.3.13 On-Chip USB PHY . . . . . . . . . . . . . . . . . . . . . . 60 3.3.14 SDHC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.3.15 DIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.3.16 SPDIF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3.17 CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3.18 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3.19 J1850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.3.20 PSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.3.21 GPIOs and Timers . . . . . . . . . . . . . . . . . . . . . . 73 3.3.22 Fusebox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.3.23 IEEE 1149.1 (JTAG) . . . . . . . . . . . . . . . . . . . . . 74 3.3.24 VIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 System Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.1 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . . 76 4.2 System and CPU Core AVDD Power Supply Filtering. 76 4.3 Connection Recommendations . . . . . . . . . . . . . . . . . . 77 4.4 Pull-Up/Pull-Down Resistor Requirements . . . . . . . . . 78 4.4.1 Pull-Down Resistor Requirements for TEST pin 78 4.4.2 Pull-Up Requirements for the PCI Control Lines78 4.5 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.5.1 TRST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.5.2 e300 COP / BDM Interface . . . . . . . . . . . . . . . . 79 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.2 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . 83 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 MPC5121E/MPC5123 Data Sheet, Rev. 5 2 Freescale Semiconductor Ordering Information Figure 1 shows a simplified MPC5121e/MPC5123 block diagram. DDR1/DDR2 Memory not available in MPC5123 NFC PATA VIU Multi-Port Memory Controller DIU MBX Lite Graphics Engine with Vector Processing DMA 64-Channel 128 KB SRAM JTAG/COP e300 Power Architecture 32 KB Instruction Cache 32 KB Data Cache RESET/ CLOCK Temp Fuse 200 MHz CSB Bus (64-bit) 83 MHz IP Bus EMB LPC AXE Engine 8 KB Instruction Cache 200 MHz AHB (32-bit) Display Functionally Multiplexed I/O FEC USB2 + PHY USB2 ULPI SATA + PHY PCI RTC PSC × 12 CFM SPDIF SDHC J1850 CAN × 4 I2 C × 3 GPIO GPT WDT IPIC PMC 83 MHz (max) IP Bus Figure 1. Simplified MPC5121e/MPC5123 Block Diagram 1 Ordering Information Table 1. MPC5121e Orderable Part Numbers Freescale Part Number Speed (MHz) Temperature (ambient) Qualification Package Availability MPC5121VY400B 400 0 oC to 70 oC Consumer RoHS and Pb-free Tray MPC5121VY400BR 400 0 oC to 70 oC Consumer RoHS and Pb-free Tape and Reel MPC5121YVY400B 400 –40 oC to 85 oC MPC5121YVY400BR 400 –40 oC oC Industrial RoHS and Pb-free Tray to 85 oC Industrial RoHS and Pb-free Tape and Reel to 85 oC Automotive—AEC RoHS and Pb-free Tray Automotive—AEC RoHS and Pb-free Tape and Reel SPC5121YVY400B 400 –40 SPC5121YVY400BR 400 –40 oC to 85 oC Table 2. MPC5123 Orderable Part Numbers Freescale Part Number Speed (MHz) Temperature (ambient) Qualification Package Availability MPC5123VY400B 400 0 oC to 70 oC Consumer RoHS and Pb-free Tray Consumer RoHS and Pb-free Tape and Reel Industrial RoHS and Pb-free Tray MPC5123VY400BR 400 MPC5123YVY400B 400 0 oC to 70 oC –40 oC to 85 oC MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 3 Ordering Information Table 2. MPC5123 Orderable Part Numbers (continued) Freescale Part Number Speed (MHz) Temperature (ambient) Qualification Package Availability MPC5123YVY400BR 400 –40 oC to 85 oC SPC5123YVY400B SPC5123YVY400BR 400 400 Industrial RoHS and Pb-free Tape and Reel o o Automotive—AEC RoHS and Pb-free Tray o o Automotive—AEC RoHS and Pb-free Tape and Reel –40 C to 85 C –40 C to 85 C MPC5121E/MPC5123 Data Sheet, Rev. 5 4 Freescale Semiconductor Pin Assignments 2 Pin Assignments This section details pin assignments. 2.1 1 A 516-TEPBGA Ball Map 2 3 4 VSS VSS SATA_ RXN VSS VSS SATA_ RX_VS SA 5 B VSS C VSS D SATA_ VDDA_ 1P2 E SATA_ TXN F SATA_ TXP G SATA_ NFC_R TX_VS E SA H NFC_R PATA_ NFC_C NFC_A NFC_C /B LE LE DACK E0 J PATA_I PATA_I PATA_I OCHR NTRQ OR DY K PATA_ CE1 SATA_ SATA_ XTALO XTALI VSS VSS 6 7 8 9 10 11 12 13 14 15 16 17 VSS PSC8_ 3 VSS PSC7_ PSC6_ VDD_I PSC11 0 3 O _1 VSS PSC10 PSC2_ VDD_I PSC0_ _1 1 O 4 VSS SATA_ SATA_ SATA_ PSC9_ PSC9_ PSC8_ VDD_I PLL_V VDDA_ VDDA_ 3 1 1 O SSA 3P3 VREG VSS VSS VSS NFC_ WE NFC_ WP VSS PATA_ DRQ 19 20 21 22 23 24 USB2_ VBUS_ PWR_F AULT VDD_I PSC11 O _4 VSS PSC2_ PSC1_ VDD_I PSC0_ 4 4 O 0 VSS VSS VSS VSS VDD_I O VDD_I O VDD_I O VSS VSS 26 VSS VSS USB_X TALI VSS PCI_C LK VSS VSS PCI_R EQ2 USB_U USB_V USB_V USB_R USB_PL PCI_G ID SSA SSA REF L_GND NT2 PCI_G NT0 PCI_R EQ1 VDD_I O PCI_A D28 VSS VSS VSS USB_V USB_P HIB_M VBAT_ USB_V USB_V DDA_B LL_PW RTC DDA BUS ODE IAS R3 VSS 25 USB_V USB_X VDD_I SSA_B TALO O IAS GPIO3 CAN2_ 1 RX SATA_ AVDD_ PSC_ PSC9_ PSC8_ PSC7_ PSC6_ PSC11 PSC10 PSC10 PSC2_ PSC1_ PSC0_ GPIO3 CAN1_ RTC_X USB_V USB_V VDDA_ FUSE MCLK_ 0 2 2 1 _2 _3 _0 0 0 3 0 RX TALI DDA SSA 1P2 WR IN SATA_V SATA_P SATA_R SATA_A PSC9_ PSC9_ PSC8_ PSC8_ PSC7_ PSC11 PSC10 PSC2_ PSC1_ PSC0_ CAN2_ GPIO2 DDA_1 LL_VDD ESREF NAVIZ 4 2 4 0 1 _3 _4 2 2 2 TX 9 P2 A1P2 VSS 18 SATA_ USB2_ SATA_ PSC7_ PSC7_ PSC6_ PSC6_ PSC6_ PSC11 PSC10 PSC2_ PSC1_ PSC1_ PSC0_ CAN1_ GPIO2 RTC_X USB_D USB_D USB_T RX_VS DRVVB RXP 4 3 4 2 0 _0 _2 3 3 1 1 TX 8 TALO M P PA SA US VSS VDD_I O VSS VDD_I O PCI_RS VDD_I O T_OUT PCI_A D30 VDD_I O PCI_G NT1 PCI_R EQ0 PCI_A D29 PCI_A PCI_C/ D26 BE3 PCI_A D31 VSS PCI_A D24 VSS PCI_A D21 PCI_A D27 PCI_A D25 PCI_A D23 PCI_A D20 PCI_A D18 PCI_A D19 PCI_A PCI_IR D17 DY PATA_I VDD_I VDD_I PATA_I SOLAT O O OW E VSS VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C ORE ORE ORE ORE ORE ORE ORE ORE VSS PCI_ID PCI_A SEL D22 L EMB_A EMB_A EMB_A EMB_A PATA_ D03 D02 D01 D00 CE2 VSS VDD_C ORE VSS VSS VSS VSS VSS VSS VDD_C ORE VSS PCI_A D16 VDD_I PCI_C/ VDD_I PCI_D O O BE2 EVSEL M EMB_A D06 VDD_C ORE VSS VSS VSS VSS VSS VSS VDD_C ORE PCI_T RDY PCI_F RAME PCI_S TOP PCI_P ERR PCI_S ERR N EMB_A EMB_A EMB_A EMB_A D10 D09 D08 D07 VDD_I O VDD_C ORE VSS VSS VSS VSS VSS VSS VDD_C ORE VDD_I O PCI_P AR VSS PCI_C/ BE1 VSS PCI_A D15 P EMB_A EMB_A EMB_A EMB_A EMB_A VDD_I D15 D14 D11 D13 D12 O VDD_C ORE VSS VSS VSS VSS VSS VSS VDD_C ORE VDD_I PCI_C/ PCI_A O D09 BE0 PCI_A D13 PCI_A D14 PCI_A D12 R EMB_A VDD_I EMB_A VDD_I EMB_A D17 O D16 O D19 VDD_C ORE VSS VSS VSS VSS VSS VSS VDD_C ORE PCI_A D03 PCI_A D06 PCI_A D10 PCI_A D11 PCI_A D08 T EMB_A EMB_A EMB_A EMB_A EMB_A D22 D18 D20 D21 D23 VSS VDD_C ORE VSS VSS VSS VSS VSS VSS VDD_C ORE VSS SYS_PL VDD_I L_AVDD O PCI_A D05 VDD_I O PCI_A D07 U EMB_A D25 VSS VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C ORE ORE ORE ORE ORE ORE ORE ORE VSS SYS_PL PCI_IN PCI_A L_AVSS D00 TA PCI_A D02 PCI_A D04 V EMB_A EMB_A EMB_A EMB_A EMB_A D26 D27 D28 D30 X01 W EMB_A EMB_A EMB_A LPC_A LPC_C VDD_I D31 X00 X02 X03 O S0 Y LPC_C VDD_I LPC_C VDD_I LPC_O O O S2 S1 E AA LPC_R LPC_A PSC4_ LPC_C PSC4_ WB 1 LK 3 CK AB PSC4_ 0 AC VDD_ PSC5_ PSC4_ PSC5_ PSC3_ MEM_I MDM0 0 4 1 2 O MDQ8 AD PSC5_ PSC5_ 2 3 MDQ1 1 AE VDD_I O AF VSS VSS VSS EMB_A D05 EMB_A D24 PSC4_ 2 VSS VSS VSS VSS EMB_A D04 VSS EMB_A D29 VDD_I O VDD_ MEM_I O VSS PSC3_ MDQ1 MVTT0 MDQ5 1 PSC3_ MDQS 3 0 MDQ6 VDD_ VDD_I PSC5_ MDQ2 MEM_I MDQ7 O 4 O VDD_I PSC3_ PSC3_ MDQ0 O 0 4 MDQ3 VSS MDQ4 VSS MDQ1 0 VSS VSS VSS MVRE F VDD_ MDQ1 MDQS MEM_I 4 2 O VDD_ MDQS MDQ1 MEM_I 1 6 O MDM1 MDQ1 8 VDD_ VDD_ MEM_I MEM_I O O MDQ1 9 VSS MDQ2 0 VDD_ MDQ1 MEM_I MVTT2 2 O VSS MDQ1 3 MDQ1 7 MDQ9 MVTT1 MDQ1 5 CORE _PLL_ AVDD VSS SYS_X TALI VSS PCI_A D01 TDO PORE SET HRES ET TEST SYS_X TALO J1850_ TX TDI VSS TMS CKSTP _OUT I2C2_S VDD_I J1850_ VDD_I DA O RX O VSS VSS MA1 MA5 VDD_ MEM_I O MA14 SPDIF I2C1_S I2C1_S MCKE _TXCL CL DA K VDD_ MDQ2 MDQ3 MEM_I 5 0 O MBA1 VSS MA7 MA11 VDD_ MEM_I MODT O VSS I2C0_S SPDIF I2C2_S CL _RX CL MDQ2 3 MBA0 MA0 MA4 MA9 MA13 MWE MCS CORE _PLL_ AVSS SPDIF _TX VSS I2C0_S DA VDD_ MDQ2 MDQ2 MVTT3 MEM_I 4 8 O VSS MA2 MA6 VDD_ MEM_I O MA12 MA15 VSS VDD_I O VDD_I O VSS MCK MCK MBA2 MA3 MA8 MA10 MRAS MCAS VDD_I O MDQ2 1 MDM2 MDQ2 7 MDQS 3 MDQ2 2 MDQ3 1 MDQ2 9 MDQ2 6 MDM3 VSS SRESE T VSS IRQ1 TRST TCK IRQ0 Figure 2. Ball Map for the MPC5121e 516 TEPBGA Package MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 5 Pin Assignments 2.2 Pinout Listings Table 3 provides the pin-out listing for the MPC5121e/MPC5123. Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 1 of 12) Signal Package Pin Number Pad Type Power Supply Notes DDR Memory Interface (67 Total) MDQ0 AF5 DDR VDD_MEM_IO — MDQ1 AB6 DDR VDD_MEM_IO — MDQ2 AE4 DDR VDD_MEM_IO — MDQ3 AF6 DDR VDD_MEM_IO — MDQ4 AF7 DDR VDD_MEM_IO — MDQ5 AB8 DDR VDD_MEM_IO — MDQ6 AD6 DDR VDD_MEM_IO — MDQ7 AE6 DDR VDD_MEM_IO — MDQ8 AC7 DDR VDD_MEM_IO — MDQ9 AF8 DDR VDD_MEM_IO — MDQ10 AB9 DDR VDD_MEM_IO — MDQ11 AD7 DDR VDD_MEM_IO — MDQ12 AE9 DDR VDD_MEM_IO — MDQ13 AF10 DDR VDD_MEM_IO — MDQ14 AC9 DDR VDD_MEM_IO — MDQ15 AF11 DDR VDD_MEM_IO — MDQ16 AD10 DDR VDD_MEM_IO — MDQ17 AF12 DDR VDD_MEM_IO — MDQ18 AD11 DDR VDD_MEM_IO — MDQ19 AB12 DDR VDD_MEM_IO — MDQ20 AD12 DDR VDD_MEM_IO — MDQ21 AB13 DDR VDD_MEM_IO — MDQ22 AF14 DDR VDD_MEM_IO — MDQ23 AD13 DDR VDD_MEM_IO — MDQ24 AE13 DDR VDD_MEM_IO — MDQ25 AC13 DDR VDD_MEM_IO — MDQ26 AF15 DDR VDD_MEM_IO — MDQ27 AB14 DDR VDD_MEM_IO — MDQ28 AE16 DDR VDD_MEM_IO — MDQ29 AD15 DDR VDD_MEM_IO — MDQ30 AC15 DDR VDD_MEM_IO — MPC5121E/MPC5123 Data Sheet, Rev. 5 6 Freescale Semiconductor Pin Assignments Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 2 of 12) Signal Package Pin Number Pad Type Power Supply Notes MDQ31 AB15 DDR VDD_MEM_IO — MDM0 AC6 DDR VDD_MEM_IO — MDM1 AE8 DDR VDD_MEM_IO — MDM2 AF13 DDR VDD_MEM_IO — MDM3 AF16 DDR VDD_MEM_IO — MDQS0 AD5 DDR VDD_MEM_IO — MDQS1 AD8 DDR VDD_MEM_IO — MDQS2 AC11 DDR VDD_MEM_IO — MDQS3 AD14 DDR VDD_MEM_IO — MBA0 AD16 DDR VDD_MEM_IO — MBA1 AC16 DDR VDD_MEM_IO — MBA2 AF19 DDR VDD_MEM_IO — MA0 AD17 DDR VDD_MEM_IO — MA1 AB16 DDR VDD_MEM_IO — MA2 AE18 DDR VDD_MEM_IO — MA3 AF20 DDR VDD_MEM_IO — MA4 AD18 DDR VDD_MEM_IO — MA5 AB17 DDR VDD_MEM_IO — MA6 AE19 DDR VDD_MEM_IO — MA7 AC18 DDR VDD_MEM_IO — MA8 AF21 DDR VDD_MEM_IO — MA9 AD19 DDR VDD_MEM_IO — MA10 AF22 DDR VDD_MEM_IO — MA11 AC19 DDR VDD_MEM_IO — MA12 AE21 DDR VDD_MEM_IO — MA13 AD20 DDR VDD_MEM_IO — MA14 AB19 DDR VDD_MEM_IO — MA15 AE22 DDR VDD_MEM_IO — MWE AD21 DDR VDD_MEM_IO — MRAS AF23 DDR VDD_MEM_IO — MCAS AF24 DDR VDD_MEM_IO — MCS AD22 DDR VDD_MEM_IO — MCKE AB20 DDR VDD_MEM_IO — MCK AF17 DDR VDD_MEM_IO — MCK AF18 DDR VDD_MEM_IO — MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 7 Pin Assignments Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 3 of 12) Signal Package Pin Number Pad Type Power Supply Notes MODT AC21 DDR VDD_MEM_IO — LPC Interface (8 Total) LPC_CLK AA4 General IO VDD_IO — LPC_OE Y5 General IO VDD_IO — LPC_RW AA1 General IO VDD_IO — LPC_CS0 W5 General IO VDD_IO — LPC_CS1 Y3 General IO VDD_IO — LPC_CS2 Y1 General IO VDD_IO — LPC_ACK AA2 General IO VDD_IO — LPC_AX03 W4 General IO VDD_IO — EMB Interface (35 Total) EMB_AX02 W3 General IO VDD_IO — EMB_AX01 V5 General IO VDD_IO — EMB_AX00 W2 General IO VDD_IO — EMB_AD31 W1 General IO VDD_IO — EMB_AD30 V4 General IO VDD_IO — EMB_AD29 U5 General IO VDD_IO — EMB_AD28 V3 General IO VDD_IO — EMB_AD27 V2 General IO VDD_IO — EMB_AD26 V1 General IO VDD_IO — EMB_AD25 U1 General IO VDD_IO — EMB_AD24 U3 General IO VDD_IO — EMB_AD23 T5 General IO VDD_IO — EMB_AD22 T1 General IO VDD_IO — EMB_AD21 T4 General IO VDD_IO — EMB_AD20 T3 General IO VDD_IO — EMB_AD19 R5 General IO VDD_IO — EMB_AD18 T2 General IO VDD_IO — EMB_AD17 R1 General IO VDD_IO — EMB_AD16 R3 General IO VDD_IO — EMB_AD15 P1 General IO VDD_IO — EMB_AD14 P2 General IO VDD_IO — EMB_AD13 P4 General IO VDD_IO — EMB_AD12 P5 General IO VDD_IO — MPC5121E/MPC5123 Data Sheet, Rev. 5 8 Freescale Semiconductor Pin Assignments Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 4 of 12) Signal Package Pin Number Pad Type Power Supply Notes EMB_AD11 P3 General IO VDD_IO — EMB_AD10 N1 General IO VDD_IO — EMB_AD09 N2 General IO VDD_IO — EMB_AD08 N3 General IO VDD_IO — EMB_AD07 N4 General IO VDD_IO — EMB_AD06 M1 General IO VDD_IO — EMB_AD05 M3 General IO VDD_IO — EMB_AD04 M5 General IO VDD_IO — EMB_AD03 L1 General IO VDD_IO — EMB_AD02 L2 General IO VDD_IO — EMB_AD01 L3 General IO VDD_IO — EMB_AD00 L4 General IO VDD_IO — PATA Interface (9 Total) PATA_CE1 K1 General IO VDD_IO ATA name: CS0 PATA_CE2 L5 General IO VDD_IO ATA name: CS1 PATA_ISOLATE K3 General IO VDD_IO — PATA_IOR J1 General IO VDD_IO ATA name: DIOR PATA_IOW K5 General IO VDD_IO ATA name: DIOW PATA_IOCHRDY J2 General IO VDD_IO ATA name: IORDY PATA_INTRQ J3 General IO VDD_IO — PATA_DRQ J4 General IO VDD_IO ATA name: DMARQ PATA_DACK H2 General IO VDD_IO ATA name: DMACK NFC Interface (7 Total) NFC_WP G4 General IO VDD_IO — NFC_R/B H1 General IO VDD_IO — NFC_WE G3 General IO VDD_IO — NFC_RE G2 General IO VDD_IO — NFC_ALE H4 General IO VDD_IO — NFC_CLE H5 General IO VDD_IO — NFC_CE0 H3 General IO VDD_IO — I2C Interface (6 Total) I2C0_SCL AC23 General IO VDD_IO — I2C0_SDA AD26 General IO VDD_IO — I2C1_SCL AB22 General IO VDD_IO — MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 9 Pin Assignments Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 5 of 12) Signal Package Pin Number Pad Type Power Supply Notes I2C1_SDA AB23 General IO VDD_IO — I2C2_SCL AC25 General IO VDD_IO — I2C2_SDA AA22 General IO VDD_IO — IRQ Interface (2 Total) IRQ0 AC26 General IO VDD_IO — IRQ1 AB25 General IO VDD_IO — CAN Interface (4 Total) CAN1_RX C19 Analog Input VBAT_RTC — CAN1_TX A18 General IO VDD_IO — CAN2_RX B19 Analog Input VBAT_RTC — CAN2_TX E16 General IO VDD_IO — J1850 Interface (2 Total) J1850_TX Y22 General IO VDD_IO — J1850_RX AA24 General IO VDD_IO — SPDIF Interface (3 Total) SPDIF_TXCLK AB21 General IO VDD_IO — SPDIF_TX AD24 General IO VDD_IO — SPDIF_RX AC24 General IO VDD_IO — PCI (54 Total) PCI_INTA U23 PCI VDD_IO — PCI_RST_OUT F22 PCI VDD_IO — PCI_AD00 U24 PCI VDD_IO — PCI_AD01 V26 PCI VDD_IO — PCI_AD02 U25 PCI VDD_IO — PCI_AD03 R22 PCI VDD_IO — PCI_AD04 U26 PCI VDD_IO — PCI_AD05 T24 PCI VDD_IO — PCI_AD06 R23 PCI VDD_IO — PCI_AD07 T26 PCI VDD_IO — PCI_AD08 R26 PCI VDD_IO — PCI_AD09 P23 PCI VDD_IO — PCI_AD10 R24 PCI VDD_IO — PCI_AD11 R25 PCI VDD_IO — PCI_AD12 P26 PCI VDD_IO — MPC5121E/MPC5123 Data Sheet, Rev. 5 10 Freescale Semiconductor Pin Assignments Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 6 of 12) Signal Package Pin Number Pad Type Power Supply Notes PCI_AD13 P24 PCI VDD_IO — PCI_AD14 P25 PCI VDD_IO — PCI_AD15 N26 PCI VDD_IO — PCI_AD16 L22 PCI VDD_IO — PCI_AD17 K25 PCI VDD_IO — PCI_AD18 J26 PCI VDD_IO — PCI_AD19 K24 PCI VDD_IO — PCI_AD20 J25 PCI VDD_IO — PCI_AD21 H26 PCI VDD_IO — PCI_AD22 K23 PCI VDD_IO — PCI_AD23 J24 PCI VDD_IO — PCI_AD24 H24 PCI VDD_IO — PCI_AD25 J23 PCI VDD_IO — PCI_AD26 G25 PCI VDD_IO — PCI_AD27 J22 PCI VDD_IO — PCI_AD28 F26 PCI VDD_IO — PCI_AD29 G24 PCI VDD_IO — PCI_AD30 F24 PCI VDD_IO — PCI_AD31 H22 PCI VDD_IO — PCI_C/BE0 P22 PCI VDD_IO — PCI_C/BE1 N24 PCI VDD_IO — PCI_C/BE2 L24 PCI VDD_IO — PCI_C/BE3 G26 PCI VDD_IO — PCI_PAR N22 PCI VDD_IO — PCI_FRAME M23 PCI VDD_IO 1 PCI_TRDY M22 PCI VDD_IO 1 PCI_IRDY K26 PCI VDD_IO 1 PCI_STOP M24 PCI VDD_IO 1 PCI_DEVSEL L26 PCI VDD_IO 1 PCI_IDSEL K22 PCI VDD_IO — PCI_SERR M26 PCI VDD_IO 1 PCI_PERR M25 PCI VDD_IO 1 PCI_REQ0 G23 PCI VDD_IO 1 PCI_REQ1 E26 PCI VDD_IO 1 PCI_REQ2 D26 PCI VDD_IO 1 MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 11 Pin Assignments Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 7 of 12) Signal Package Pin Number Pad Type Power Supply Notes PCI_GNT0 E25 PCI VDD_IO — PCI_GNT1 G22 PCI VDD_IO — PCI_GNT2 E24 PCI VDD_IO — PCI_CLK C26 PCI VDD_IO — PSC Interface (61 Total) PSC_MCLK_IN C17 General IO VDD_IO — PSC0_0 D16 General IO VDD_IO — PSC0_1 A17 General IO VDD_IO — PSC0_2 E15 General IO VDD_IO — PSC0_3 C16 General IO VDD_IO — PSC0_4 B16 General IO VDD_IO — PSC1_0 C15 General IO VDD_IO — PSC1_1 A16 General IO VDD_IO — PSC1_2 E14 General IO VDD_IO — PSC1_3 A15 General IO VDD_IO — PSC1_4 D14 General IO VDD_IO — PSC2_0 C14 General IO VDD_IO — PSC2_1 B14 General IO VDD_IO — PSC2_2 E13 General IO VDD_IO — PSC2_3 A14 General IO VDD_IO — PSC2_4 D13 General IO VDD_IO — PSC3_0 AF3 General IO VDD_IO — PSC3_1 AB5 General IO VDD_IO — PSC3_2 AC4 General IO VDD_IO — PSC3_3 AD4 General IO VDD_IO — PSC3_4 AF4 General IO VDD_IO — PSC4_0 AB1 General IO VDD_IO — PSC4_1 AA3 General IO VDD_IO — PSC4_2 AB3 General IO VDD_IO — PSC4_3 AA5 General IO VDD_IO — PSC4_4 AC2 General IO VDD_IO — PSC5_0 AC1 General IO VDD_IO — PSC5_1 AC3 General IO VDD_IO — PSC5_2 AD1 General IO VDD_IO — MPC5121E/MPC5123 Data Sheet, Rev. 5 12 Freescale Semiconductor Pin Assignments Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 8 of 12) Signal Package Pin Number Pad Type Power Supply Notes PSC5_3 AD2 General IO VDD_IO — PSC5_4 AE3 General IO VDD_IO — PSC6_0 A11 General IO VDD_IO — PSC6_1 C10 General IO VDD_IO — PSC6_2 A10 General IO VDD_IO — PSC6_3 B9 General IO VDD_IO — PSC6_4 A9 General IO VDD_IO — PSC7_0 B8 General IO VDD_IO — PSC7_1 E10 General IO VDD_IO — PSC7_2 C8 General IO VDD_IO — PSC7_3 A8 General IO VDD_IO — PSC7_4 A7 General IO VDD_IO — PSC8_0 E9 General IO VDD_IO — PSC8_1 D8 General IO VDD_IO — PSC8_2 C7 General IO VDD_IO — PSC8_3 B6 General IO VDD_IO — PSC8_4 E8 General IO VDD_IO — PSC9_0 C6 General IO VDD_IO — PSC9_1 D7 General IO VDD_IO — PSC9_2 E7 General IO VDD_IO — PSC9_3 D6 General IO VDD_IO — PSC9_4 E6 General IO VDD_IO — PSC10_0 C13 General IO VDD_IO — PSC10_1 B13 General IO VDD_IO — PSC10_2 A13 General IO VDD_IO — PSC10_3 C12 General IO VDD_IO — PSC10_4 E12 General IO VDD_IO — PSC11_0 A12 General IO VDD_IO — PSC11_1 B11 General IO VDD_IO — PSC11_2 C11 General IO VDD_IO — PSC11_3 E11 General IO VDD_IO — PSC11_4 D11 General IO VDD_IO — VDD_IO 2 JTAG (5 Total) TCK AB26 General IO MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 13 Pin Assignments Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 9 of 12) Signal Package Pin Number Pad Type Power Supply Notes TDI Y23 General IO VDD_IO 3 TDO W22 General IO VDD_IO — TMS Y25 General IO VDD_IO 3 TRST AA26 General IO VDD_IO 3 Test / Debug (2 Total) 4 , 5 TEST W25 General IO VDD_IO CKSTP_OUT Y26 General IO VDD_IO — System Control (3 Total) HRESET W24 General IO VDD_IO 6, 2 PORESET W23 General IO VDD_IO 4, 2 SRESET V22 General IO VDD_IO 6, 2 System Clock (2 Total) SYS_XTALI V24 Analog Input SYS_PLL_AVDD Oscillator Input SYS_XTALO W26 Analog Output SYS_PLL_AVDD Oscillator Output RTC (3 Total) RTC_XTALI C20 Analog Input VBAT_RTC Oscillator Input RTC_XTALO A20 Analog Output VBAT_RTC Oscillator Output HIB_MODE D18 Analog Output VBAT_RTC — GP Input Only (4 Total) GPIO28 A19 Analog Input VBAT_RTC — GPIO29 E17 Analog Input VBAT_RTC — GPIO30 C18 Analog Input VBAT_RTC — GPIO31 B18 Analog Input VBAT_RTC — DDR Reference Voltage MVREF AB11 Analog Input Voltage Reference for SSTL input pads USB – PHY without Power and Ground Supplies (7 Total) USB_XTALI C24 Analog Input USB_PLL_PWR3 Oscillator Input USB_XTALO B24 Analog Output USB_PLL_PWR3 Oscillator Output USB_DP A23 Analog IO USB_VDDA — USB_DM A22 Analog IO USB_VDDA — USB_TPA A24 Analog Output — USB PHY debug output USB_VBUS D21 Analog IO — — MPC5121E/MPC5123 Data Sheet, Rev. 5 14 Freescale Semiconductor Pin Assignments Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 10 of 12) Signal Package Pin Number Pad Type Power Supply Notes USB_UID E19 Analog Input — — USB digital IOs (2 Total) USB2_VBUS_PWR_FA ULT B21 General IO VDD_IO — USB2_DRVVBUS A21 General IO VDD_IO — SATA PHY without Power and Ground Supplies (7 Total) SATA_XTALI C3 Analog Input SATA_VDDA_3P3 Oscillator Input SATA_XTALO C2 Analog Output SATA_VDDA_3P3 Oscillator Output SATA_ANAVIZ E5 Analog Output — SATA PHY debug output SATA_TXN E1 Analog Output SATA_VDDA_1P2 — SATA_TXP F1 Analog Output SATA_VDDA_1P2 — SATA_RXP A5 Analog Input SATA_VDDA_1P2 — SATA_RXN A4 Analog Input SATA_VDDA_1P2 — Power and Ground Supplies (without SATA PHY and USB PHY) VDD_CORE K10, K11, K12, K13, K14, K15, K16, K17, L10, L17, M10, M17, N10, N17, P10, P17, R10, R17, T10, T17, U10, U11, U12, U13, U14, U15, U16, U17 Power — — VDD_IO B10, B15, B25, D9, D10, D15, F11, F13, F14, F19, F23, F25, H21, J5, K2, K4, L23, L25, N6, N21, P6, P21, R2, R4, T23, T25, W6, W21, Y2, Y4, AA23, AA25, AE1, AE2, AE24, AE25, AF2, AF25 Power — — VDD_MEM_IO AA8, AA13, AA14, AB18, AC5, AC10, AC14, AC20, AD9, AE5, AE10, AE15, AE20 Power — — MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 15 Pin Assignments Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 11 of 12) Signal Package Pin Number Pad Type Power Supply Notes VSS A2, A3, A25, B1,B2, B3, B5, B7, B12, B17, B20, B22, B26, C1, C4, C23, C25, D2, D12, D17, D24, D25, E18, F2, F3, F4, F5, F6, F8, F10, F16, F17, F21, G5, H6, H23, H25, K6, K21, L6, L11, L12, L13, L14, L15, L16, L21, M2, M4, M11, M12, M13, M14, M15, M16, N5, N11, N12, N13, N14, N15, N16, Ground — — VSS N23, N25, P11, P12, P13, P14, P15, P16, R11, R12, R13, R14, R15, R16, T6, T11, T12, T13, T14, T15, T16, T21, U2, U4, U6, U21, V23, V25, Y24, AA6, AA10, AA11, AA16, AA17, AA21, AB2, AB4, AB10, AB24, AC8, AC12, AC17, AC22, AD3, AD25, AE7, AE12, AE17, AE23, AE26 Ground — — SYS_PLL_AVDD T22 Analog Power — — SYS_PLL_AVSS U22 Analog Ground — — CORE_PLL_AVDD AA19 Analog Power — — CORE_PLL_AVSS AD23 Analog Ground — — VBAT_RTC D19 Power — — AVDD_FUSEWR C9 Power — — MVTT0 AB7 Analog Input SSTL(DDR2) Termination (ODT) Voltage MVTT1 AF9 Analog Input SSTL(DDR2) Termination (ODT) Voltage MVTT2 AE11 Analog Input SSTL(DDR2) Termination (ODT) Voltage MVTT3 AE14 Analog Input SSTL(DDR2) Termination (ODT) Voltage Power and Ground Supplies (USB PHY) USB_PLL_GND E23 Analog Ground — — USB_PLL_PWR3 D23 Analog Power — — USB_RREF E22 Analog Power — — USB_VSSA_BIAS B23 Analog Ground — — MPC5121E/MPC5123 Data Sheet, Rev. 5 16 Freescale Semiconductor Pin Assignments Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 12 of 12) Signal Package Pin Number Pad Type Power Supply Notes USB_VDDA_BIAS D22 Analog Power — — USB_VSSA C22, E20, E21 Analog Ground — — USB_VDDA C21, D20 Analog Power — — Power and Ground Supplies (SATA PHY) 1 2 3 4 5 6 SATA_RESREF E4 Analog Power — — SATA_VDDA_3P3 D4 Analog Power — — SATA_VDDA_1P2 C5, D1, E2 Analog Power — — SATA_VDDA_VREG D5 Analog Power — — SATA_PLL_VDDA1P2 E3 Analog Power — — SATA_PLL_VSSA D3 Analog Ground — — SATA_RX_VSSA A6, B4 Analog Ground — — SATA_TX_VSSA G1 Analog Ground — — This pins should have an external pull-up resistor. Follow PCI specification and see System Design Information. This pin contains an enabled internal Schmitt trigger. These JTAG pins have internal pull-up P-FETs. This pin can not be configured. This pin is an input only. This pin can not be configured. This test pin must be tied to VSS. This pin is an input or open-drain output. This pin can not be configured. There is an internal pull-up resistor implemented. NOTE This table indicates only the pins with permananently enabled internal pull-up, pull-down, or Schmitt trigger. Most of the digital I/O pins can be configured to enable internal pull-up, pull-down, or Schmitt trigger. See the MPC5121e Microcontroller Reference Manual, IO Control chapter. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 17 Electrical and Thermal Characteristics 3 Electrical and Thermal Characteristics 3.1 DC Electrical Characteristics 3.1.1 Absolute Maximum Ratings The tables in this section describe the MPC5121e/MPC5123 DC Electrical characteristics. Table 4 gives the absolute maximum ratings. Table 4. Absolute Maximum Ratings1 Characteristic Symbol Min Max Unit SpecID VDD_CORE –0.3 1.47 V D1.1 VDD_IO, VDD_MEM_IO –0.3 3.6 V D1.2 MVREF –0.3 3.6 V MVTT –0.3 3.6 V SYS_PLL_AVDD –0.3 3.6 V D1.3 CORE_PLL_AVDD –0.3 3.6 V D1.4 VBAT_RTC –0.3 3.6 V D1.5 Supply voltage – FUSE Programming AVDD_FUSEWR –0.3 3.6 V D1.6 Supply voltage – SATA PHY analog SATA_VDDA_3P3 –0.3 3.6 V D1.8 SATA_VDDA_VREG –0.3 2.6 V D1.9 SATA_VDDA_1P2 –0.3 1.47 V D1.10 SATA_PLL_VDDA1P2 –0.3 1.47 V D1.11 USB_PLL_PWR3 –0.3 3.6 V D1.12 USB_VDDA –0.3 3.6 V D1.13 USB_VDDA_BIAS –0.3 3.6 V D1.14 USB_VBUS –0.3 3.6 V D1.15 Input voltage (VDD_IO) Vin –0.3 VDD_IO + 0.3 V D1.16 Input voltage (VDD_MEM_IO) Vin –0.3 VDD_MEM_IO + 0.3 V D1.17 Input voltage (VBAT_RTC) Vin –0.3 VBAT_RTC + 0.3 V D1.18 Input voltage overshoot Vinos — 1 V D1.19 Input voltage undershoot Vinus — 1 V D1.20 Storage temperature range Tstg  55 150 oC D1.21 Supply voltage – e300 core and peripheral logic Supply voltage – I/O buffers Input reference voltage (DDR/DDR2) Termination Voltage (DDR2) Supply voltage – System APLL, System Oscillator Supply voltage – e300 APLL Supply voltage – RTC (Hibernation) Supply voltage – SATA PHY voltage regulator Supply voltage – SATA PHY Tx/Rx Supply voltage – SATA PHY PLL Supply voltage – USB PHY PLL and OSC Supply voltage – USB PHY transceiver Supply voltage – USB PHY bandgap bias Input voltage – USB PHY cable 1 Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage. MPC5121E/MPC5123 Data Sheet, Rev. 5 18 Freescale Semiconductor Electrical and Thermal Characteristics 3.1.2 Recommended Operating Conditions Table 5 gives the recommended operating conditions. 3) Table 5. Recommended Operating Conditions Characteristic Supply voltage – e300 core and peripheral logic Symbol Min1 Typ Max1 VDD_CORE 1.33 1.4 1.47 — — State Retention voltage – e300 core and peripheral logic 2 1.08 Supply voltage – standard I / O buffers Unit SpecID V D2.1 V D2.2 VDD_IO 3.0 3.3 3.6 V D2.3 Supply voltage – memory I / O buffers (DDR) VDD_MEM_IO_DDR 2.3 2.5 2.7 V D2.4 Supply voltage – memory I/O buffers (DDR2, LPDDR) VDD_MEM_IO_DDR2 VDD_MEM_IO_LPDDR 1.7 1.8 1.9 V D2.5 MVREF 0.49 × VDD_MEM_IO 0.50 × VDD_MEM_IO 0.51 × VDD_MEM_IO V D2.6 MVTT MVREF – 0.04 MVREF MVREF + 0.04 V D2.7 SYS_PLL_AVDD 3.0 3.3 3.6 V D2.8 CORE_PLL_AVDD 3.0 3.3 3.6 V D2.9 VBAT_RTC 3.0 3.3 3.6 V D2.10 Supply voltage – FUSE Programming AVDD_FUSEWR 3.3 3.6 V D2.11 Supply voltage – SATA PHY analog and OSC SATA_VDDA_3P3 3.0 3.6 V D2.13 2.6 V D2.14 Input Reference Voltage (DDR/DDR2) Termination Voltage (DDR2) Supply voltage – System APLL, System Oscillator Supply voltage – e300 APLL Supply voltage – RTC (Hibernation)3 3.3 Supply voltage – SATA PHY voltage regulator SATA_VDDA_VREG 1.7 Supply voltage – SATA PHY Tx/Rx SATA_VDDA_1P2 1.14 1.2 1.47 V D2.15 SATA_PLL_VDDA1P2 1.33 1.4 1.47 V D2.16 USB_PLL_PWR3 3.0 3.3 3.6 V D2.17 USB_VDDA 3.0 3.3 3.6 V D2.18 USB_VDDA_BIAS 3.0 3.3 3.6 V D2.19 USB_VBUS 1.4 — 3.6 V D2.20 Vin 0 — VDD_IO V D2.21 VinDDR 0 — VDD_MEM_IO V D2.22 V D2.23 V D2.24 oC D2.25 o D2.26 Supply voltage – SATA PHY PLL Supply voltage – USB PHY PLL and OSC Supply voltage – USB PHY transceiver Supply voltage – USB PHY bandgap bias Input voltage – USB PHY cable Input voltage – standard I/O buffers Input voltage – memory I/O buffers (DDR) _DDR Input voltage – memory I/O buffers (DDR2) VinDDR2 0 — VDD_MEM_I O_DDR2 Input voltage – memory I/O buffers (LPDDR) VinLPDDR 0 — VDD_MEM_I O_LPDR Ambient operating temperature range TA –40 — +85 Junction operating temperature range TJ –40 — +125 C 1 These are recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. The State Retention voltage can be applied to VDD_CORE after the device is placed in Deep-Sleep mode. 3 VBAT_RTC should not be supplied by a battery of voltage less than 3.0 V. 2 MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 19 Electrical and Thermal Characteristics 3.1.3 DC Electrical Specifications Table 6 gives the DC Electrical characteristics for the MPC5121e/MPC5123 at recommended operating conditions. Table 6. DC Electrical Specifications Characteristic Condition Symbol Min Max Unit SpecID Input high voltage Input type = TTL VDD_IO VIH 0.51 × VDD_IO — V D3.1 Input high voltage Input type = TTL VDD_MEM_IO_DDR VIH MVREF + 0.15 — V D3.2 Input high voltage Input type = TTL VDD_MEM_IO_DDR2 VIH MVREF + 0.125 — V D3.3 Input high voltage Input type =  TTL VDD_MEM_IO_LPDDR VIH 0.7 × VDD_MEM_IO_LPDDR — V D3.4 Input high voltage Input type = PCI VDD_IO VIH 0.5 × VDD_IO — V D3.5 Input high voltage Input type = Schmitt VDD_IO VIH 0.65 × VDD_IO — V D3.6 Input high voltage SYS_XTALI crystal mode1 Bypass mode2 CVIH Vxtal + 0.4V (VDD_IO/2) + 0.4V — V D3.7 Input high voltage SATA_XTALI crystal mode Bypass mode SVIH Vxtal + 0.4V (VDD_IO/2) + 0.4V — V D3.8 Input high voltage USB_XTALI crystal mode Bypass mode UVIH Vxtal + 0.4V (VDD_IO/2) + 0.4V — V D3.9 Input high voltage RTC_XTALI crystal mode3 RVIH (VBAT_RTC/5) + 0.5V (VBAT_RTC/2) + 0.4V — V D3.10 Bypass mode4 Input low voltage Input type = TTL VDD_IO VIL — 0.42 × VDD_IO V D3.11 Input low voltage Input type = TTL VDD_MEM_IO_DDR VIL — MVREF – 0.15 V D3.12 Input low voltage Input type = TTL VDD_MEM_IO_DDR2 VIL — MVREF – 0.125 V D3.13 Input low voltage Input type =  TTL VDD_MEM_IO_LPDDR VIL — 0.3 × VDD_MEM_IO_LPDDR V D3.14 Input low voltage Input type = PCI VDD_IO VIL — 0.3 × VDD_IO V D3.15 Input low voltage Input type = Schmitt VDD_IO VIL — 0.35 × VDD_IO V D3.16 Input low voltage SYS_XTALI crystal mode Bypass mode CVIL — Vxtal – 0.4 (VDD_IO/2) – 0.4 V D3.17 Input low voltage SATA_XTALI crystal mode Bypass mode SVIL — Vxtal – 0.4 V (VDD_IO/2) – 0.4 V D3.18 Input low voltage USB_XTALI crystal mode Bypass mode UVIL — Vxtal – 0.4 (VDD_IO/2) – 0.4 V D3.19 Input low voltage RTC_XTALI crystal mode Bypass mode RVIL — (VBAT_RTC/5) – 0.5 (VBAT_RTC/2) – 0.4 V D3.20 Input leakage current Vin = 0 or VDD_IO/VDD_MEM_IO_DDR/2 (depending on input type)5 IIN 2.5 2.5 µA D3.21 Input leakage current SYS_XTALI Vin = 0 or VDD_IO IIN — 20 µA D3.22 MPC5121E/MPC5123 Data Sheet, Rev. 5 20 Freescale Semiconductor Electrical and Thermal Characteristics Table 6. DC Electrical Specifications (continued) Characteristic Condition Input leakage current RTC_XTALI Vin = 0 or VDD_IO Symbol Min Max Unit SpecID IIN — 1.0 µA D3.23 Input current, pullup resistor6 Pullup VDD_IO Vin = VIL IINpu 25 150 µA D3.24 Input current, pulldown resistor 8 Pulldown VDD_IO Vin = VIH IINpd 25 150 µA D3.25 Output high voltage IOH is driver dependent7 VDD_IO VOH 0.8 × VDD_IO — V D3.26 V D3.27 V D3.28 7 Output high voltage IOH is driver dependent VDD_MEM_IO_DDR VOHDDR 1.90 Output high voltage IOH is driver dependent7 VDD_MEM_IO_DDR2 VOHDDR2 1.396 Output high voltage IOH is driver dependent7 VDD_MEM_IO_LPDDR VOHLPDDR VDD_MEM_IO – 0.28 — V D3.28 Output low voltage IOL is driver dependent7 VDD_IO VOL — 0.2 × VDD_IO V D3.30 Output low voltage IOL is driver dependent7 VDD_MEM_IO_DDR VOLDDR — 0.36 V D3.31 Output low voltage IOL is driver dependent7 VDD_MEM_IO_DDR2 VOLDDR2 — 0.28 V D3.32 Output low voltage IOL is driver dependent7 VDD_MEM_IO_LPDDR VOLLPDDR — 0.28 V D3.33 — — Differential cross point voltage  (DDR MCK/MCK) — VOXMCK 0.5 × VDD_MEM_IO – 0.125 0.5 × VDD_MEM_IO + 0.125 V D3.34 DC Injection Current Per Pin8 — ICS 1.0 1.0 mA D3.35 Input Capacitance (digital pins) — Cin — 7 pF D3.36 Input Capacitance (analog pins) — Cin — 10 pF D3.37 On Die Termination (DDR2) — RODT 120 180  D3.38 1 2 3 4 5 6 This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case, Vextal – Vxtal - 400mV criteria has to be met for oscillator’s comparator to produce output clock. This parameter is meant for those who do not use quartz crystals or resonators, but signal generator clock to drive, in bypass mode. In that case, drive only the EXTAL pin not connecting anything to other pin for the oscillator’s comparator to produce output clock. This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case, drive one of the XTAL_IN or XTAL_OUT pins not connecting anything to other pin for the oscillator’s comparator to produce output clock. This parameter is meant for those who do not use quartz crystals or resonators, but signal generator clock to drive, in bypass mode. In that case, drive only the xtal_in pin not connecting anything to other pin for the oscillator’s comparator to produce output clock. Leakage current is measured with output drivers disabled and pull-up/pull-downs inactive. Pullup current is measured at VIL and pulldown current is measured at VIH. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 21 Electrical and Thermal Characteristics 7 See Table 7 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin as listed in Table 3. 8 All injection current is transferred to VDD_IO/VDD_MEM_IO. An external load is required to dissipate this current to maintain the power supply within the specified voltage range. Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation. Table 7. I/O Pads—Drive Current, Slew Rate Pad Type Supply Voltage Drive Select/Slew Rate Control Rise time max (ns) Fall time max (ns) General IO VDD_IO = 3.3V configuration 3 (11) 1.4 1.6 configuration 2 (10) 9.8 12 D3.42 configuration 1 (01) 19 24 D3.43 configuration 0 (00) 140 183 D3.44 configuration 3 (011) 2 2 16.2 16.2 D3.45 VDD_MEM_IO = 1.8V (LPDDR) configuration 0 (000) 1 1 4.6 4.6 D3.46 8.1 8.1 D3.47 5.3 5.3 D3.48 13.4 13.4 D3.49 11 17 D3.50 DDR VDD_MEM_IO = 2.5V (DDR) configuration 1 (001) VDD_MEM_IO = 1.8V (DDR2) configuration 2 (010) 1 1 configuration 6 (110) PCI VDD_IO = 3.3V configuration 1 (1) 1.4 1.4 configuration 0 (0) 2 2 Current Current SpecID Ioh (mA) Iol (mA) 35 35 D3.41 D3.51 1 Notes: 1. General IO – Rise and Fall Times at Drive load 50pF. 2. PCI – Rise and Fall Times at Drive load 10pF. 3. DDR – for LPDDR/Mobile-DDR, slew rate is measured between 20% of VDD_MEM_IO and 80% of VDD_MEM_IO. 4. DDR – for DDR, DDR2, rising signals, slew rate is measured between VDD_MEM_IO × 0.5 and ViHAC. For falling signals, slew rate is measured between VDD_MEM_IO × 0.5 and ViLAC. 5. DDR – Rise and Fall Times terminated at the destination with 50 ohm to MVTT (0.5 × VDD_MEM_IO), with 4 pF representing the DDR input capacitance. MPC5121E/MPC5123 Data Sheet, Rev. 5 22 Freescale Semiconductor Electrical and Thermal Characteristics 3.1.4 Electrostatic Discharge CAUTION This device contains circuitry that protects against damage due to high-static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages. Operational reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (GND or VDD ). Table 10 gives package thermal characteristics for this device. Table 8. ESD and Latch-Up Protection Characteristics Symbol Rating Min Max Unit SpecID VHBM Human Body Model (HBM) – JEDEC JESD22-A114-B 2000 — V D4.1 VMM Machine Model (MM) – JEDEC JESD22-A115 200 — V D4.2 VCDM Charge Device Model (CDM) – JEDEC JESD22-C101 500 — V D4.3 3.1.5 Power Dissipation Power dissipation of the MPC5121e/MPC5123 is caused by 4 different components: the dissipation of the internal or core digital logic (supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by SYS_PLL_AVDD and CORE_PLL_AVDD), the dissipation of the IO logic (supplied by VDD_MEM_IO and VDD_IO) and the dissipation of the PHYs (supplied by own supplies). Table 9 details typical measured core and analog power dissipation figures for a range of operating modes. However, the dissipation due to the switching of the IO pins can not be given in general, but must be calculated for each application case using the following formula: P IO = P IOint +  N  C  VDD_IO 2 f Eqn. 1 M where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f is the switching frequency and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the device must not exceed the value that would cause the maximum junction temperature to be exceeded. Eqn. 2 P total = P core + P analog + P IO + PPHYs Table 9. Power Dissipation Core Power Supply (VDD_CORE) SpecID High-Performance Mode Unit e300 = 300 MHz, CSB = 200 MHz Operational1 800 mW D5.1 Deep-Sleep 1 mW D5.2 Hibernation 20 uW D5.3 1 PLL/OSC Power Supplies (SYS_PLL_AVDD, CORE_PLL_AVDD) Typical 25 mW D5.4 Unloaded I/O Power Supplies (VDD_IO, VDD_MEM_IO) MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 23 Electrical and Thermal Characteristics Table 9. Power Dissipation (continued) Core Power Supply (VDD_CORE) SpecID High-Performance Mode Unit e300 = 300 MHz, CSB = 200 MHz Typical 300 mW D5.5 PHY Power Supplies (USB_VDDA, SATA_VDDA) Typical 1 200 mW D5.6 Typical core power is measured at VDD_CORE = 1.4 V, Tj = 25 oC. NOTE The maximum power depends on the supply voltage, process corner, junction temperature, and the concrete application and clock configurations. The worst case power consumption could reach a maximum of 2000 mW. 3.1.6 Thermal Characteristics Table 10. Thermal Resistance Data Symbol TEPBGA TEPBGA 2 Value Unit SpecID Junction to Ambient Natural Single layer board (1s) Convection1,2 RJA 31 24 30 °C/W D6.1 Junction to Ambient Natural Four layer board (2s2p) Convection1,3 RJMA 22 17 22 °C/W D6.2 Junction to Ambient (@200 Single layer board (1s) ft/min)1,3 RJMA 25 19 24 °C/W D6.3 Junction to Ambient (@200 Four layer board (2s2p) ft/min)1,3 RJMA 19 14 19 °C/W D6.4 — RJB 14 9 14 °C/W D6.5 — RJC 9 7 8 °C/W D6.6 JT 2 7 2 °C/W D6.7 Rating Junction to Board4 Junction to Case5 Junction to Package Top6 1 2 3 4 5 6 Board Layers Natural Convection Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. MPC5121E/MPC5123 Data Sheet, Rev. 5 24 Freescale Semiconductor Electrical and Thermal Characteristics 3.1.6.1 Heat Dissipation An estimation of the chip-junction temperature, TJ, can be obtained from the following equation: TJ = TA + ( R JA  PD ) Eqn. 3 where: TA = ambient temperature for the package ( º C ) R JA = junction to ambient thermal resistance ( º C / W ) PD = power dissipation in package ( W ) The junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board, and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is correct depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: R JA = R JC + R CA Eqn. 4 where: R JA = junction to ambient thermal resistance ( º C / W ) R JC = junction to case thermal resistance ( º C / W ) R CA = case to ambient thermal resistance ( º C / W ) R JC is device related and cannot be influenced by the user. You control the thermal environment to change the case to ambient thermal resistance, R CA. For instance, you can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for ceramic packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance. The junction to case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used for hand estimations or for a computational fluid dynamics (CFD) thermal model. To determine the junction temperature of the device in the application after prototypes are available, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (  JT  PD ) Eqn. 5 where: TT = thermocouple temperature on top of package ( º C )  JT = thermal characterization parameter ( º C / W ) PD = power dissipation in package ( W ) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned, so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over approximately one mm of wire extending MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 25 Electrical and Thermal Characteristics from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 3.2 Oscillator and PLL Electrical Characteristics The MPC5121e/MPC5123 System requires a system-level clock input SYS_XTALI. This clock input may be driven directly from an external oscillator or with a crystal using the internal oscillator. There is a separate oscillator for the independent Real Time Clock (RTC) system. The MPC5121e/MPC5123 clock generation uses two phase locked loop (PLL) blocks. • The system PLL (SYS_PLL) takes an external reference frequency and generates the internal system clock. The system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL configuration. The e300 core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The e300 core clock frequency is determined by the system clock frequency and the settings of the CORE_PLL configuration. • The USB PHY contains its own oscillator with the input USB_XTALI and an embedded PLL. The SATA PHY contains its own oscillator with the input SATA_XTALI and an embedded PLL. 3.2.1 System Oscillator Electrical Characteristics Table 11. System Oscillator Electrical Characteristics Characteristic SYS_XTALI frequency Symbol Min Typical Max Unit SpecID fsys_xtal 15.6 33.3 35.0 MHz O1.1 The system oscillator can work in oscillator mode or in bypass mode to support an external input clock as clock reference. t CYCLE t DUTY t DUTY t FALL t RISE CV IH VM SYS_XTALI CLK VM VM CV IL Figure 3. Timing Diagram—SYS_XTALI Table 12. SYS_XTALI Timing Sym t CYCLE Description SYS_XTALI cycle time1, 2 3 Min Max Units SpecID 64.1 28.57 ns O.1.2 t RISE SYS_XTALI rise time 1 4 ns O.1.3 t FALL time4 1 4 ns O.1.4 40 60 % O.1.5 t DUTY SYS_XTALI fall SYS_XTALI duty cycle5 1 The SYS_XTALI frequency and system PLL settings must be chosen such that the resulting system frequencies do not exceed their respective maximum or minimum operating frequencies. See the MPC5121e Microcontroller Reference Manual. 2 The MIN/Max cycle times are calculated using 1/f sys_xtal (MIN/MAX) where the fsys_xtal (MIN/MAX) (15.6/35 MHz) are taken from Table 11. 3 Rise time is measured from 20% of vdd to 80% of V . DD MPC5121E/MPC5123 Data Sheet, Rev. 5 26 Freescale Semiconductor Electrical and Thermal Characteristics 4 5 Fall time is measured from 20% of vdd to 80% of VDD. SYS_XTALI duty cycle is measured at V M. 3.2.2 RTC Oscillator Electrical Characteristics Table 13. RTC Oscillator Electrical Characteristics Characteristic RTC_XTALI frequency 3.2.3 Symbol Min Typical Max Unit SpecID frtc_xtal — 32.768 — kHz O2.1 System PLL Electrical Characteristics Table 14. System PLL Specifications Characteristic Symbol Min Typical Max Unit SpecID fsys_xtal 16 33.3 67 MHz O3.1 tjitter — — 10 ps O3.2 fVCOsys 400 — 800 MHz O3.3 Sys PLL VCO output jitter (Dj), peak to peak / cycle fVCOjitterDj — — 40 ps O3.4 Sys PLL VCO output jitter (Rj), RMS 1 sigma fVCOjitterRj — — 12 ps O3.5 tlock1 — — 200 s O3.6 tlock2 — — 170 s O3.7 Sys PLL input clock frequency1 Sys PLL input clock Sys PLL VCO jitter2 frequency Sys PLL relock time—after power up3 Sys PLL relock time—when power was on4 1 The SYS_XTALI frequency and PLL Configuration bits must be chosen such that the resulting system frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. 2 This represents total input jitter—short term and long term combined. Two different types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected. Systemic jitter is passed into and through the PLL to the internal clock circuitry. 3 PLL relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLK are reached during the power-on reset sequence. 4 PLL relock time is the maximum amount of time required for the PLL lock after the PLL has been disabled and subsequently re-enabled during sleep modes. 3.2.4 e300 Core PLL Electrical Characteristics The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled core PLL. Table 15. e300 PLL Specifications Characteristic Symbol Min Typical Max Unit SpecID fcore 200 — 400 MHz O4.1 fVCOcore 400 — 800 MHz O4.3 e300 PLL input clock frequency fCSB_CLK 50 — 200 MHz O4.4 e300 PLL input clock cycle time tCSB_CLK 5 — 20 ns O4.5 tlock — — 200 s O4.6 e300 frequency1 e300 PLL VCO frequency e300 PLL relock time 2 1 MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 27 Electrical and Thermal Characteristics 1 The frequency and e300 PLL Configuration bits must be chosen such that the resulting system frequencies, CPU (core) frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies in Table 16. There is a hard coded relationship between fcore and fVCOcore (fcore = fVCOcore/2). 2 PLL relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes. MPC5121E/MPC5123 Data Sheet, Rev. 5 28 Freescale Semiconductor Electrical and Thermal Characteristics 3.3 AC Electrical Characteristics 3.3.1 Overview Hyperlinks to the indicated timing specification sections are provided in the following: • AC Operating Frequency Data • SDHC • Resets • DIU • External Interrupts • SPDIF • SDRAM (DDR) • CAN • PCI • I2C • LPC • J1850 • NFC • PSC • PATA • GPIOs and Timers • SATA PHY • Fusebox • FEC • IEEE 1149.1 (JTAG) • USB ULPI • VIU • On-Chip USB PHY AC Test Timing Conditions: Unless otherwise noted, all test conditions are as follows: • • • • 3.3.2 TA = –40 to 85 oC VDD_CORE = 1.33 to 1.47 V VDD_IO = 3.0 to 3.6 V Input conditions: All Inputs: tr, tf  1 ns Output Loading: All Outputs: 50 pF AC Operating Frequency Data Table 16 provides the operating frequency information for the MPC5121e/MPC5123. Table 16. Clock Frequencies Min Max Units SpecID e300 Processor Core 200 400 MHz A1.1 SDRAM Clock 28.6 200 MHz A1.2 CSB Bus Clock 50.0 200 MHz A1.3 IP Bus Clock 8.3 83 MHz A1.4 PCI Clock 4.43 66 MHz A1.5 LPC Clock 2.08 83 MHz A1.6 MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 29 Electrical and Thermal Characteristics Table 16. Clock Frequencies (continued) Min Max Units SpecID NFC Clock 2.08 83 MHz A1.7 DIU Clock 0.78 100 MHz A1.8 SDHC Clock 0.78 66.6 MHz A1.9 MBX Clock 6.25 100 MHz A1.10 NOTES: 1. The SYS_XTALI frequency, Sys PLL, and CORE PLL settings must be chosen so that the resulting e300 clk, csb_clk, MCK, frequencies do not exceed their respective maximum or minimum operating frequencies. 2. The values are valid for the user operation mode. There can be deviations for test modes. 3. The selection of the peripheral clock frequencies needs to take care about requirements for baud rates and minimum frequency limitation. 4.The DDR data rate is 2× the DDR memory bus frequency. See the MPC5121e Microcontroller Reference Manual for more information on the clock subsystem. 3.3.3 Resets The MPC5121e/MPC5123 has three reset pins: • • • PORESET—Power on Reset HRESET—Hard Reset SRESET—Software Reset These signals are asynchronous I / O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires the same input characteristics as other MPC5121e/MPC5123 inputs, as specified in Section 3.1, “DC Electrical Characteristics.” As long as VDD is not stable the HRESET output is not stable. Table 17. Reset Rise / Fall Timing Description Min Max Unit SpecID PORESET1 fall time — 1 ms A3.4 PORESET rise time — 1 ms A3.5 HRESET2,3 fall time — 1 ms A3.6 HRESET rise time — 1 ms A3.7 SRESET fall time — 1 ms A3.8 SRESET rise time — 1 ms A3.9 1 Make sure that the PORESET does not carry any glitches. The MPC5121e/MPC5123 has no filter to prevent them from getting into the chip. 2 HRESET and SRESET must have a monotonous rise time. 3 The assertion of HRESET becomes active at Power on Reset without any SYS_XTALI clock. The timing relationship is shown in Figure 4. MPC5121E/MPC5123 Data Sheet, Rev. 5 30 Freescale Semiconductor Electrical and Thermal Characteristics SYS_XTALI PORESET tHRVAL HRESET tSRVAL SRESET tS_POR_CONF tEXEC RST_CONF[31:0] ADDR[31:0] tH_POR_CONF Figure 4. Power-Up Behavior SYS_XTALI tPORHold PORESET tHRVAL HRESET tSRVAL SRESET tS_POR_CONF tEXEC RST_CONF[31:0] ADDR[31:0] tH_POR_CONF Figure 5. Power-On Reset Behavior MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 31 Electrical and Thermal Characteristics SYS_XTALI PORESET tHRHOLD tHRVAL HRESET tSRVAL SRESET tHR_SR_Delay tEXEC RST_CONF[31:0] ADDR[31:0] no new fetch of the RST_CONF Figure 6. HRESET Behavior SYS_XTALI PORESET tSRHOLD HRESET tSRMIN SRESET tEXEC RST_CONF[31:0] ADDR[31:0] no new fetch of the RST_CONF Figure 7. SRESET Behavior Table 18. Reset Timing Symbol tPORHOLD Description Time PORESET must be held low before a qualified reset occurs Value SYS_XTALI SpecID 4 cycles A3.10 26810 cycles A3.11 tHRVAL Time HRESET is asserted after a qualified reset occurs tSRVAL Time SRESET is asserted after assertion of HRESET 32 cycles A3.12 tEXEC Time between SRESET assertion and first core instruction fetch 4 cycles A3.13 MPC5121E/MPC5123 Data Sheet, Rev. 5 32 Freescale Semiconductor Electrical and Thermal Characteristics Table 18. Reset Timing (continued) Symbol Description Value SYS_XTALI SpecID tS_POR_CONF Reset configuration setup time before assertion of PORESET 1 cycle A3.14 tH_POR_CONF Reset configuration hold time after assertion of PORESET 1 cycle A3.15 tHR_SR_DELAY Time from falling edge of HRESET to falling edge of SRESET 4 cycles A3.16 tHRHOLD Time HRESET must be held low before a qualified reset occurs 4 cycles A3.17 tSRHOLD Time SRESET must be held low before a qualified reset occurs 4 cycles A3.18 Time SRESET is asserted after it has been qualified 1 cycles A3.19 tSRMIN 3.3.4 External Interrupts The MPC5121e/MPC5123 provides three different kinds of external interrupts: • • • IRQ interrupts GPIO interrupts with simple interrupt capability (not available in power-down mode) WakeUp interrupts Table 19. IPIC Input AC Timing Specifications1 Description IPIC inputs—minimum pulse witdh 1 Symbol Min Unit SpecID tPICWID 2T ns A4.1 T is the IP bus clock cycle. T = 12 ns is the minimum value (for the maximum IP bus freqency of 83 MHz). IPIC inputs must be valid for at least tPICWID to ensure proper operation in edge triggered mode. 3.3.5 SDRAM (DDR) The MPC5121e/MPC5123 memory controller supports three types of DDR devices: • • • DDR-1 (SSTL_2 class II interface) DDR-2 (SSTL_18 interface) LPDDR/Mobile-DDR (1.8V I/O supply voltage) JEDEC standards define the minimum set of requirements for complient memory devices: — JEDEC STANDARD, DDR2 SDRAM SPECIFICATION, JESD79-2C, May 2006 — JEDEC STANDARD, Double Data Rate (DDR) SDRAM Specification, JESD79E, May 2005 — JEDEC STANDARD, Low Power Double Data Rate (LPDDR) SDRAM Specification, JESD79-4, May 2006 The MPC5121e/MPC5123 supports the configuration of two output drive strengths for DDR2 and LPDDR: • • Full drive strength Half drive strengh (intended for ligther loads or point-to-point environments) The MPC5121e/MPC5123 memory controller supports dynamic on-die termination in the host device and in the DDR2 memory device. This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in the DC Electrical Characteristics. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 33 Electrical and Thermal Characteristics 3.3.5.1 DDR and DDR2 SDRAM AC Timing Specifications Table 20. DDR and DDR2 (DDR2-400) SDRAM Timing Specifications At recommended operating conditions with VDD_MEM_IO of 5% Parameter Symbol Min Max Unit Clock cycle time, CL=x tCK 5000 — ps CK HIGH pulse width tCH 0.47 0.53 tCK 12 , A5.3 tCK 12 , A5.4 CK LOW pulse width SpecID A5.1 tCL 0.47 tDQSS 0.25 0.25 tCK 2 3 , A5.5 Address and control output setup time relative to MCK rising edge tOS(base) (tCK/2 – 750) — ps 2 3 , A5.6 Address and control output hold time relative to MCK rising edge tOH(base) (tCK/2 – 750) — ps 2 3 , A5.7 DQ and DM output setup time relative to DQS tDS1(base) (tCK/4 – 500) — ps 2, 3 A5.8 DQ and DM output hold time relative to DQS tDH1(base) (tCK/4 – 500) — ps 2, 3 A5.9 DQS-DQ skew for DQS and associated DQ inputs tDQSQ –(tCK/4 – 600) (tCK/4 – 600) ps 2 A5.10 DQS window start position related to CAS read command tDQSEN TBD TBD ps 1,2,3,4,5 A5.11 Skew between MCK and DQS transitions 0.53 Notes 1 Measured with clock pin loaded with differential 100 termination resistor. All transitions measured at mid-supply (VDD_MEM_IO/2). 3 Measured with all outputs except the clock loaded with 50  termination resistor to V DD_MEM_IO/2. 4 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low. 5 Window position is given for t DQSEN = 2.0 tCK. For other values of tDQSEN, window position is shifted accordingly. 2 Figure 8 shows the DDR SDRAM write timing. tCL tCH MCK tCK DQS tDQSS DQ, DM(out) tDS tDH Figure 8. DDR Write Timing Figure 9 and Figure 10 shows the DDR SDRAM read timing. MPC5121E/MPC5123 Data Sheet, Rev. 5 34 Freescale Semiconductor Electrical and Thermal Characteristics DQS(in) Any DQ(in) tDQSQ tDQSQ Figure 9. DDR Read Timing, DQ vs DQS Command Read Address tOS tOH DQS (in) tDQSEN (min) tDQSEN Figure 10. DDR Read Timing, DQSEN Figure 11 provides the AC test load for the DDR bus. Output Z0 = 50  RL = 50  VDD_MEM_IO/2 Figure 11. DDR AC Test Load 3.3.6 PCI The PCI interface on the MPC5121e/MPC5123 is designed to PCI Version 2.3 and supports 33 and 66 MHz PCI operations. See the PCI Local Bus Specification; the component section specifies the electrical and timing parameters for PCI components with the intent that components connect directly together whether on the planar or an expansion board, without any external buffers or other glue logic. Parameters apply at the package pins, not at expansion board edge connectors. The PCI_CLK is used as output clock, the MPC5121e/MPC5123 is a PCI host device only. Figure 12 shows the clock waveform and required measurement points for 3.3 V signaling environments. Table 21 summarizes the clock specifications. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 35 Electrical and Thermal Characteristics t cyc t high t low 0.6Vcc PCI CLK 0.5Vcc 0.4Vcc 0.3Vcc 0.4Vcc, p-to-p (minimum) 0.2Vcc Figure 12. PCI CLK Waveform 2 Table 21. PCI CLK Specifications 66 MHz1 Sym Description 33 MHz Units SpecID Min2 Max Min Max tcyc PCI CLK Cycle Time1,3 15 30 30 — ns A6.1 thigh PCI CLK High Time 6 — 11 — ns A6.2 t low PCI CLK Low Time 6 — 11 — ns A6.3 1.5 4 1 4 V/ns A6.4 — PCI CLK Slew Rate2 1 In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLK requirements vary depending upon whether the clock frequency is above 33 MHz. 2 Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 12. 3 The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter. Table 22. PCI Timing Parameters1 66 MHz Sym tval Description CLK to Signal Valid Delay – bused signals1,2,3 tval(ptp) CLK to Signal Valid Delay – point to point1,2,3 33 MHz Units SpecID 11 ns A6.5 2 12 ns A6.6 2 — ns A6.7 28 ns A6.8 Min2 Max Min Max 2 6 2 2 6 2 — t on Float to Active Delay1 t off Active to Float Delay1 t su Input Setup Time to CLK – bused signals3,4 3 — 7 — ns A6.9 t su(ptp) Input Setup Time to CLK – point to point3,4 5 — 10,12 — ns A6.10 0 — 0 — ns A6.11 th Input Hold Time from CLK4 14 1 See the timing measurement conditions in the PCI Local Bus Specification. It is important that all driven signal transitions drive to their Voh or Vol level within one Tcyc. 2 Minimum times are measured at the package pin with the load circuit, and maximum times are measured with the load circuit as shown in the PCI Local Bus Specification. 3 REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused. MPC5121E/MPC5123 Data Sheet, Rev. 5 36 Freescale Semiconductor Electrical and Thermal Characteristics 4 See the timing measurement conditions in the PCI Local Bus Specification. For Measurement and Test Conditions, see the PCI Local Bus Specification. 3.3.7 LPC The Local Plus Bus is the external bus interface of the MPC5121e/MPC5123. A maximum of eight configurable chip selects (CS) are provided. There are two main modes of operation: non-MUXed and MUXED. The reference clock is the LPC CLK. The maximum bus frequency is 83 MHz. Definition of Acronyms and Terms: WS = Wait State DC = Dead Cycle HC = Hold Cycle DS = Data Size in Bytes BBT = Burst Bytes per Transfer AL = Address latch enable Length ALT = Chip select/Address Latch Timing tLPCck = LPC clock period Table 23. LPC Timing Sym tOD Description CS[x], ADDR, R/W, TSIZ, DATA (wr), TS, OE valid after LPC CLK (Output Delay related to LPC CLK) Min Max Units SpecID 0 5 ns A7.1 t1 Non-MUXed non-Burst CS[x] pulse width (2 + WS) × tLPCck (2 + WS) × tLPCck ns A7.2 t2 ADDR, R/W, TSIZ, DATA (wr) valid before CS[x] assertion tLPCck – tOD tLPCck + tOD ns A7.3 t3 OE assertion after CS[x] assertion tLPCck – tOD tLPCck + tOD ns A7.4 t4 ADDR, R/W, TSIZ, Data (wr) hold after CS[x] negation tLPCck – tOD (HC + 1) × tLPCck + tOD ns A7.5 t5 TS pulse width tLPCck tLPCck ns A7.6 t6 DATA (rd) setup before LPC CLK 4 — ns A7.7 t7 DATA (rd) input hold 0 (DC + 1) × tLPCck ns A7.8 t8 Non-MUXed read Burst CS[x] pulse width ns A7.9 t9 Burst ACK pulse width t10 Burst DATA (rd) input hold t11 Read Burst ACK assertion after CS[x] assertion t12 Non-muxed write Burst CS[x] pulse width t13 Write Burst ADDR, R/W, TSIZ, DATA (wr) hold after CS[x] negation (2 + WS + BBT/DS) × tLPCck (2 + WS + BBT/DS) × tLPCck (BBT/DS) × tLPCck (BBT/DS) × tLPCck ns A7.10 0 — ns A7.11 (2 + WS) × tLPCck (2 + WS) × tLPCck ns A7.12 ns A7.13 ns A7.14 (2.5 + WS + BBT/DS) × tLPCck (2.5 + WS + BBT/DS) × tLPCck 0.5 × tLPCck – tOD (HC + 0.5) × tLPCck + tOD MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 37 Electrical and Thermal Characteristics Table 23. LPC Timing (continued) Sym Description Min Max Units SpecID (2.5 + WS) × tLPCck – tOD (2.5 + WS) × tLPCck + tOD ns A7.15 tLPCck – tOD — ns A7.16 0.5 × tLPCck – tOD 0.5 × tLPCck + tOD ns A7.17 AL × 2 × tLPCck – tOD AL × 2 × tLPCck ns A7.18 t14 Write Burst ACK assertion after CS[x] assertion t15 Write Burst DATA valid t16 Non-MUXed Mode: asynchronous write Burst ADDR valid before write DATA valid t17 MUXed Mode: ADDR cycle t18 MUXed Mode: ALE cycle AL × tLPCck AL × tLPCck ns A7.19 t19 Non-MUXed Mode Page Burst: ADDR cycle tLPCck – tOD tLPCck ns A7.20 t20 Non-MUXed Mode Page Burst: Burst DATA (rd) input setup before next ADDR cycle tOD + t6 ns A7.21 ns A7.22 t21 — Non-MUXed Mode Page Burst: Burst DATA (rd) input hold after next ADDR cycle 0 t22 MUXed Mode: non-Burst CS[x] pulse width (ALT × (AL × 2) + 2 + WS) × tLPCck (ALT × (AL × 2) + 2 + WS) × tLPCck ns A7.23 t23 MUXed Mode: read Burst CS[x] pulse width [ALT (AL × 2) + 2 + WS + BBT/DS] × tLPCck [ALT × (AL × 2)+2+WS +BBT/DS] × tLPCck ns A7.24 t24 MUXed Mode: write Burst CS[x] pulse width [ALT × (AL × 2) + 2.5 + WS + BBT/DS] × tLPCck [ALT × (AL × 2)+2.5+WS +BBT/DS] × tLPCck ns A7.25 — MPC5121E/MPC5123 Data Sheet, Rev. 5 38 Freescale Semiconductor Electrical and Thermal Characteristics 3.3.7.1 Non-MUXed Mode 3.3.7.1.1 Non-MUXed Non-Burst Mode tLPCck LPC CLK t1 CS[x] ADDR t2 t3 t4 OE R/W DATA (wr) t6 t7 DATA (rd) ACK t5 TS TSIZ[1:0] Figure 13. Timing Diagram – Non-MUXed Non-Burst Mode NOTE ACK is asynchonous input signal and has no timing requirements. ACK needs to be deasserted after CS[x] is deasserted. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 39 Electrical and Thermal Characteristics 3.3.7.1.2 Non-MUXed Synchronous Read Burst Mode LPC_CLK t8 CS[x] t2 t4 Valid Address ADDR t5 TS t3 OE R/W t10 t6 t7 DATA (rd) t11 t9 ACK Figure 14. Timing Diagram – Non-MUXed Synchronous Read Burst Mode 3.3.7.1.3 Non-MUXed Synchronous Write Burst Mode LPC_CLK t12 CS[x] t2 t13 Valid Address ADDR t5 TS R/W t15 t15 DATA (wr) t9 ACK t14 Figure 15. Timing Diagram – Non-MUXed Synchronous Write Burst MPC5121E/MPC5123 Data Sheet, Rev. 5 40 Freescale Semiconductor Electrical and Thermal Characteristics 3.3.7.1.4 Non-MUXed Asynchronous Read Burst Mode (Page Mode) LPC_CLK t8 CS[x] t2 t4 Valid Address (Page address) ADDR[31:n+1] t19 Valid Address ADDR[n:0] Valid Address t5 TS t3 OE t20 t6 R/W t21 t10 t7 DATA (rd) t11 t9 ACK Figure 16. Timing Diagram – Non-MUXed Asynchronous Read Burst 3.3.7.1.5 Non-MUXed Aynchronous Write Burst Mode LPC_CLK t12 t2 CS[x] t13 Valid Address (Page address) ADDR[31:n+1] Valid Address ADDR[n:0] Valid Address t16 t5 TS R/W t15 t15 DATA (wr) t9 ACK t14 Figure 17. Timing Diagram – Non-MUXed Aynchronous Write Burst MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 41 Electrical and Thermal Characteristics 3.3.7.2 MUXed Mode 3.3.7.2.1 MUXed Non-Burst Mode LPC_CLK t17 AD[31:0] (wr) Address Valid Write Data t6 AD[31:0] (rd) t7 Address t4 R/W t18 ALE t5 TS t22 CS[x] t3 OE ACK TSIZ[1:0] Figure 18. Timing Diagram – MUXed Non-Burst Mode NOTE ACK is asynchonous input signal and has no timing requirements. ACK needs to be deasserted after CS[x] is deasserted. MPC5121E/MPC5123 Data Sheet, Rev. 5 42 Freescale Semiconductor Electrical and Thermal Characteristics 3.3.7.2.2 MUXed Synchronous Read Burst Mode LPC_CLK t6 t17 AD[31:0] (rd) t10 t7 Address t18 ALE t5 TS t23 CSx t3 OE R/W t9 t11 ACK Figure 19. Timing Diagram – MUXed Synchronous Read Burst 3.3.7.2.3 MUXed Synchronous Write Burst Mode LPC_CLK t17 AD[31:0] (wr) t15 t15 t13 Address t18 ALE t5 TS t24 CSx R/W t14 t9 ACK Figure 20. Timing Diagram – MUXed Synchronous Write Burst MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 43 Electrical and Thermal Characteristics 3.3.8 NFC The NAND flash controller (NFC) implements the interface to standard NAND Flash memory devices. This section describes the timing parameters of the NFC. NFC_CLE tCLH tCLS tCS tCH NFC_CE[1:0] tWP NFC_WE tALS tALH NFC_ALE tDS NFIO[7:0] tDH command Figure 21. Command Latch Cycle Timing NFC_CLE tCLS tCH tCS NFC_CE[1:0] tWC tWH tWP NFC_WE tALH tALS NFC_ALE tDS NFIO[7:0] tDH Address Figure 22. Address Latch Cycle Timing MPC5121E/MPC5123 Data Sheet, Rev. 5 44 Freescale Semiconductor Electrical and Thermal Characteristics NFC_CLE tCLS tCS NFC_CE[1:0] tWC tWH tWP NFC_WE NFC_ALE tDS NFIO[15:0] tDH Data to NF Figure 23. Write Data Latch Timing NFC_CLE NFC_CE[1:0] tRC tREH tRP NFC_RE tAR tREA tRHZ NFC_ALE NFIO[15:0] Data from NF tRR R/B Figure 24. Read Data Latch Timing MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 45 Electrical and Thermal Characteristics NFC_RE tss NFIO[15:0] NFC SYMMETRIC MODE(SYM=1) Figure 25. Read Data Latch Timing in Symmetric Mode Table 24. NFC Timing Characteristics in asymmetric mode(SYM=0)1 Timing parameter 1 Description Min. value Max. value Unit SpecID tCLS NFC_CLE setup Time T+1 — ns A8.1 tCLH NFC_CLE Hold Time T–1 — ns A8.2 tCS NFC_CE[1:0] Setup Time 2T – 1 — ns A8.3 tCH NFC_CE[1:0] Hold Time 3T — ns A8.4 tWP NFC_WP Pulse Width T–1 — ns A8.5 tALS NFC_ALE Setup Time T–1 — ns A8.6 tALH NFC_ALE Hold Time T–1 — ns A8.7 tDS Data Setup Time T–2 — ns A8.8 tDH Data Hold Time T–1 — ns A8.9 tWC Write Cycle Time 2T — ns A8.10 tWH NFC_WE Hold Time T–1 — ns A8.11 tRR Ready to NFC_RE Low 5T + 2 — ns A8.12 tRP NFC_RE Pulse Width 1.5T – 1 — ns A8.13 tRC READ Cycle Time 2T — ns A8.14 tREH NFC_RE High Hold Time 0.5T — ns A8.15 T is the flash clock cycle. T = 45 ns, frequency = 22 MHz (boot configuration, IP bus = 66 MHz) T = 36 ns, frequency = 27 MHz (maximum configurable frequency, IP bus = 83 MHz) MPC5121E/MPC5123 Data Sheet, Rev. 5 46 Freescale Semiconductor Electrical and Thermal Characteristics Table 25. NFC Timing Characteristics in Symmetric mode(SYM=1)1 Timing Parameter 3.3.9 Min. value Max. value Unit SpecID tCLS NFC_CLE Setup time T — ns A8.21 tCLH NFC_CLE Hold time T — ns A8.22 tCS NFC_CE[1:0] Setup time T-2 — ns A8.23 tCH NFC_CE[1:0] Hold time 1.5T-1 — ns A8.24 tWP NFC_WE Pulse width 0.5T+1 — ns A8.25 tALS NFC_ALE Setup time T — ns A8.26 tALH NFC_ALE Hold time T — ns A8.27 tDS Data Setup time 0.5T-3 — ns A8.28 tDH Data Hold time 0.5T — ns A8.29 tWC Write Cycle time T — ns A8.30 tWH NFC_WE Hold time 0.5T-1 — ns A8.31 tRR Ready to NFC_RE low 5T+2 — ns A8.32 tRP NFC_RE pulse width 0.5T — ns A8.33 tRC Read Cycle time T — ns A8.34 tREH NFC_RE High hold time 0.5T — ns A8.35 9.6 — ns A8.36 tSS 1 Description NFC Read Data setup time T is the flash clock cycle. T = 45 ns, frequency = 22 MHz (boot configuration, IP bus = 66 MHz) T = 36 ns, frequency = 27 MHz (maximum configurable frequency, IP bus = 83 MHz) PATA The MPC5121e/MPC5123 ATA Controller (PATA) is completely software programmable. It can be programmed to operate with ATA protocols using their respective timing, as described in the ANSI ATA-4 specification. The ATA interface is completely asynchronous in nature. Signal relationships are based on specific fixed timing in terms of timing units ( nanoseconds ). ATA data setup and hold times, with respect to Read / Write strobes, are software programmable inside the ATA Controller. Data setup and hold times are implemented using counters. The counters count the number of ATA clock cycles needed to meet the ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification and how to program an ATA Controller and ATA drive for different ATA protocols and their respective timing. See the MPC5121e Microcontroller Reference Manual. The MPC5121e/MPC5123 ATA Host Controller design makes data available coincidentally with the active edge of the WRITE strobe in PIO and Multiword DMA modes. • • Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample setup-time beyond that required by the ATA-4 specification. Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold-time beyond that required by the ATA-4 specification. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 47 Electrical and Thermal Characteristics All ATA transfers are programmed in terms of system clock cycles ( IP bus clocks ) in the ATA Host Controller timing registers. This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate with the drive. Faster ATA modes ( i.e., UDMA 0, 1, 2 ) are supported when the system is running at a sufficient frequency to provide adequate data transfer rates. Adequate data transfer rates are a function of the following: • • • The MPC5121e/MPC5123 operating frequency ( IP bus clock frequency ) Internal MPC5121e/MPC5123 bus latencies Other system load dependent variables The ATA clock is the same frequency as the IP bus clock in MPC5121e/MPC5123. See the MPC5121e Microcontroller Reference Manual. NOTE All output timing numbers are specified for nominal 50 pF loads. 3.3.9.1 PATA Timing Parameters In the timing equations, some timing parameters are used. These parameters depend on the implementation of the ATA interface in silicon, the bus transceiver used, the cable delay and cable skew. The parameters shown in Table 3-26 specify the ATA timing. Table 3-26. PATA Timing Parameters Name Controlled by Value SpecID PATA Bus clock period MPC5121E/MPC5123 15 ns A9.1 ti_ds Set-up time ATA_DATA to ATA_IORDY edge (UDMA-in only) MPC5121E/MPC5123 2 ns A9.2 ti_dh Hold time ATA_IORDY edge to ATA_DATA (UDMA-in only) MPC5121E/MPC5123 5 ns A9.3 tco Propagation delay bus clock L-to-H to: ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0, ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA, ATA_BUFFER_EN MPC5121E/MPC5123 2 ns A9.4 tsu Set-up time ATA_DATA to bus clock L-to-H MPC5121E/MPC5123 2 ns A9.5 tsui Set-up time ATA_IORDY to bus clock H-to-L MPC5121E/MPC5123 2 ns A9.6 thi Hold time ATA_IORDY to bus clock H to L MPC5121E/MPC5123 2 ns A9.7 tskew1 Max difference in propagation delay bus clock L-to-H to any of following signals: ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0, ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA (WRITE), ATA_BUFFER_EN MPC5121E/MPC5123 1.7 ns A9.8 tskew2 Max difference in buffer propagation delay for any of following signals: ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0, ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA (WRITE), ATA_BUFFER_EN Transceiver A9.9 tskew3 Max difference in buffer propagation delay for any of following signals: ATA_IORDY, ATA_DATA (read) Transceiver A9.10 Max buffer propagation delay Transceiver A9.11 T tbuf Meaning tcable1 Cable propagation delay for ata_data Cable A9.12 tcable2 Cable propagation delay for control signals: ATA_DIOR, ATA_DIOW, ATA_IORDY, ATA_DMACK Cable A9.13 MPC5121E/MPC5123 Data Sheet, Rev. 5 48 Freescale Semiconductor Electrical and Thermal Characteristics Table 3-26. PATA Timing Parameters (continued) Name Meaning Controlled by Value SpecID tskew4 Max difference in cable propagation delay between: ATA_IORDY and ATA_DATA (read) Cable A9.14 tskew5 Max difference in cable propagation delay between: ATA_DIOR, ATA_DIOW, ATA_DMACK and ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0, ATA_DATA (write) Cable A9.15 tskew6 Max difference in cable propagation delay without accounting for ground bounce Cable A9.16 3.3.9.2 PIO Mode Timing A timing diagram for the PIO read mode is given in Figure 26. t2r t1 t9 ADDR t5 DIOR t6 Read Data (15:0) tA IORDY IORDY trd1 Figure 26. PIO Read Mode Timing To fulfill read mode timing, the different timing parameters given in Table 3-27 must be observed. Table 3-27. Timing Parameters PIO Read ATA Parameter PIO Read Mode Timing Parameter t1 t1 t1(min) = (time_1 × T) – (tskew1 + tskew2 + tskew5) calculate and programming time_1. 1 A9.20 t2 t2r t2(min) = (time_2r × T) – (tskew1 + tskew2 + tskew5) calculate and programming time_2r. 1 A9.21 t9 t9 t9(min) = (time_9 × T) – (tskew1 + tskew2 + tskew6) calculate and programming time_9. 1 A9.22 Value How to meet SpecID MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 49 Electrical and Thermal Characteristics Table 3-27. Timing Parameters PIO Read (continued) 1 ATA Parameter PIO Read Mode Timing Parameter t5 t5 t5(min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 t6 t6 0 tA tA tA(min) = (1.5 + time_ax) × T –  (tco + tsui + tcable2 + tcable2 + 2 × tbuf) calculate and programming time_ax. 1 A9.25 trd trd1 trd1(max) = (–trd) + (tskew3 + tskew4) trd1(min) = (time_pio_rdx – 0.5 ) × T – (tsu + thi) (time_pio_rdx – 0.5) × T > tsu + thi + tskew3 + tskew4 calculate and programming time_pio_rdx. 1 A9.26 t0 — t0(min) = (time_1 + time_2 + time_9) × T time_1, time_2r, time_9 A9.27 Value How to meet If not met, increase time_2r — SpecID A9.23 A9.24 See the MPC5121e Microcontroller Reference Manual. In PIO write mode, timing waveforms are somewhat different as shown in Figure 27. t1 t2r t9 ADDR DIOR DIOW buffer_en Write Data (15:0) ton tA tB t4 toff t1 IORDY IORDY Figure 27. PIO Write Mode Timing To fulfill this timing, several parameters need to be observed as shown in Table 3-28. MPC5121E/MPC5123 Data Sheet, Rev. 5 50 Freescale Semiconductor Electrical and Thermal Characteristics Table 3-28. Timing Parameters PIO Write PIO Write ATA Mode Timing Parameter Parameter 1 Value How to meet SpecID t1 t1 t1(min) = time_1 × T – (tskew1 + tskew2 + tskew5) time_1. 1 A9.30 t2 t2r t2(min) = time_2w × T – (tskew1 + tskew2 + tskew5) calculate and programming time_2w. 1 A9.31 t9 t9 t9(min) = time_9 × T – (tskew1 + tskew2 + tskew6) time_9. 1 A9.32 t3 — t3(min) = (time_2w – time_on) × T – (tskew1 + tskew2 + tskew5) If not met, increase time_2w A9.33 t4 t4 t4(min) = time_4 × T – tskew1 calculate and programming time_4. 1 A9.34 tA tA tA = (1.5 + time_ax) × T  – (tco + tsui + tcable2 + tcable2 + 2 × tbuf) calculate and programming time_ax. 1 A9.35 t0 — t0(min) = (time_1 + time_2 + time_9) × T time_1, time_2r, time_9 A9.36 — — Avoid bus contention when switching buffer on  by making ton long enough — — — Avoid bus contention when switching buffer off  by making toff long enough — A9.37 A9.38 See the MPC5121e Microcontroller Reference Manual. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 51 Electrical and Thermal Characteristics 3.3.9.3 Timing in Multiword DMA Mode Timing in multiword DMA mode is given in Figure 28 and Figure 29. tk1 DMARQ ADDR DMACK DIOR tm td tk tkjn Read Data (15:0) tgr tfr Figure 28. MDMA Read Timing tk1 DMARQ ADDR DMACK buffer_en DIOW tm ton td1 tk td tkjn toff Write Data (15:0) Figure 29. MDMA Write Timing To meet this timing, a number of timing parameters must be controlled as shown in Table 3-29. MPC5121E/MPC5123 Data Sheet, Rev. 5 52 Freescale Semiconductor Electrical and Thermal Characteristics Table 3-29. Timing Parameters MDMA Read and Write 1 ATA Parameter MDMA Read/Write Timing Parameter tm, ti tm tm(min) = ti(min) = (time_m × T) – (tskew1 + tskew2 + tskew5) calculate and programming time_m. 1 A9.40 td td, td1 td1(min) = td(min) = (time_d × T) – (tskew1 + tskew2 + tskew6) calculate and programming time_d. 1 A9.41 tk tk tk(min) = (time_k × T) – (tskew1 + tskew2 + tskew6) calculate and programming time_k. 1 A9.42 t0 — t0(min) = (time_d + time_k) × T time_d, time_k A9.43 tg(read) tgr tgr(min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr(min-drive) = td – te(drive) time_d. 1 A9.44 tf(read) tfr tfr(min-drive) — A9.45 tg(write) — tg(min-write) = time_d × T – (tskew1 + tskew2 + tskew5) time_d A9.46 tf(write) — tf(min-write) = time_k × T – (tskew1 + tskew2 + tskew6) time_k A9.47 tL — tL(max) = [(time_d + time_k – 2) × T] – [tsu + tco + (2 × tbuf) + (2 × tcable2)] time_d, time_k A9.48 tn, tj tkjn tn = tj = tkjn = [max(time_k,. time_jn) × T] – (tskew1 + tskew2 + tskew6) calculate and programming time_jn. 1 A9.49 — ton toff ton = (time_on × T) – tskew1 toff = (time_off × T) – tskew1 — A9.50 Value =0 How to meet SpecID See the MPC5121e Microcontroller Reference Manual. 3.3.9.4 UDMA In Timing Diagrams UDMA mode timing is more complicated than PIO mode or MDMA mode. In this section, timing diagrams for UDMA in are given: • • • Figure 30 gives timing for UDMA in transfer start Figure 31 gives timing for host terminating UDMA in transfer Figure 32 gives timing for device terminating UDMA in transfer. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 53 Electrical and Thermal Characteristics tack ADDR DMARQ DMACK tenv DIOR DIOW tc1 tc1 IORDY Data Read tds tdh Figure 30. UDMA In Transfer Start Timing Diagram MPC5121E/MPC5123 Data Sheet, Rev. 5 54 Freescale Semiconductor Electrical and Thermal Characteristics ADDR tack DMARQ DMACK DIOR trp DIOW tc1 tc1 tmli tx1 IORDY tmli tzah Data Read tds tzah tdh ton tdzfs tcvh toff Data Write buffer_en Figure 31. UDMA In Host Terminates Transfer ADDR tack DMARQ DMACK DIOR DIOW tmli tc1 tc1 tss1 tli5 IORDY tmli Data Read tds tdh tzah tzah ton tdzfs tcvh toff Data Write buffer_en Figure 32. UDMA In Device Terminates Transfer Timing parameters are explained in Table 30. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 55 Electrical and Thermal Characteristics Table 30. Timing Parameters UDMA in Burst ATA Parameter UDMA In Timing Parameter tack tack tenv Value How to Meet SpecID tack(min) = (time_ack × T) – (tskew1 + tskew2) calculate and programming time_ack. 1 A9.51 tenv tenv(min) = (time_env × T) – (tskew1 + tskew2) tenv(max) = (time_env × T) + (tskew1 + tskew2) calculate and programming time_env. 1 A9.52 tds tds1 tds – (tskew3) – ti_ds > 0 A9.53 tdh tdh1 tdh – (tskew3) – ti_dh > 0 tskew3, ti_ds, ti_dh should be low enough tcyc tc1 (tcyc – tskew ) > T Bus clock period T big enough A9.55 trp trp trp(min) = time_rp × T – (tskew1 + tskew2 + tskew6) calculate and programming time_rp. 1 A9.56 — tx12 (time_rp × T) – [tco + tsu + 3T + (2 × tbuf) + (2 × tcable2)] > trfs (drive) calculate and programming time_rp. 1 A9.57 tmli tmli1 tmli1(min) = (time_mlix + 0.4) × T calculate and programming time_mlix. 1 A9.58 tzah tzah tzah(min) = (time_zah + 0.4) × T calculate and programming time_zah. 1 A9.59 tdzfs tdzfs tdzfs = (time_dzfs × T) – (tskew1 + tskew2) calculate and programming time_dzfs. 1 A9.60 tcvh tcvh tcvh = (time_cvh × T) – (tskew1 + tskew2) calculate and programming time_cvh. 1 A9.61 — ton toff3 ton = (time_on × T) – tskew1 toff = (time_off × T) – tskew1 — A9.54 A9.62 1 See the MPC5121e Microcontroller Reference Manual. A special timing requirement in the ATA host requires the internal DIOW to go only high three clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. 3 Make ton and toff large enough to avoid bus contention. 2 3.3.9.5 UDMA Out Timing Diagrams UDMA mode timing is more complicated than PIO mode or MDMA mode. In this section, timing diagrams for UDMA out are given: • • • Figure 33 gives timing for UDMA out transfer start Figure 34 gives timing for host terminating UDMA out transfer Figure 35 gives timing for device terminating UDMA out transfer MPC5121E/MPC5123 Data Sheet, Rev. 5 56 Freescale Semiconductor Electrical and Thermal Characteristics tack ADDR DMARQ DMACK tenv DIOW DIOR tcyc tcyc buffer_en ton tdzfs tdvs tdvh tdvs Data Write tli1 IORDY trfs1 Figure 33. UDMA Out Transfer Start Timing Diagram ADDR tack DMARQ DMACK tss DIOW DIOR tcyc tli2 tcyc1 tdzfs_mli tcvh toff Data Write IORDY tli3 buffer_en Figure 34. UDMA Out Host Terminates Transfer MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 57 Electrical and Thermal Characteristics r ADDR tack DMARQ tli2 DMACK DIOW DIOR trfs1 tcyc tdzfs_mli tcvh toff Data Write IORDY buffer_en Figure 35. UDMA Out Device Terminates Transfer Timing parameters are explained in Table 31. Table 31. Timing Parameters UDMA Out Burst ATA Parameter UDMA Out Timing Parameter tack tack tenv Value How to meet SpecID tack(min) = (time_ack × T) – (tskew1 + tskew2) calculate and program time_ack. 1 A9.63 tenv tenv(min) = (time_env × T) – (tskew1 + tskew2) tenv(max) = (time_env × T) + (tskew1 + tskew2) calculate and program time_env. 1 A9.64 tdvs tdvs tdvs = (time_dvs × T) – (tskew1 + tskew2) calculate and program time_dvs. 1 A9.65 tdvh tdvh tdvs = (time_dvh × T) – (tskew1 + tskew2) calculate and program time_dvh. 1 A9.66 tcyc tcyc tcyc = time_cyc × T – (tskew1 + tskew2) calculate and program time_cyc. 1 A9.67 t2cyc — t2cyc = time_cyc × 2 × T calculate and program time_cyc. 1 A9.68 trfs1 trfs1 trfs1 = 1.6 × T + tsui + tco + tbuf + tbuf — A9.69 — tdzfs tdzfs = time_dzfs × T – (tskew1) calculate and program time_dzfs. 1 A9.70 tss tss tss = time_ss × T – (tskew1 + tskew2) calculate and program time_ss. 1 A9.71 tmli tdzfs_mli tdzfs_mli = max(time_dzfs, time_mli) × T – (tskew1 + tskew2) — A9.72 tli tli1 tli1 > 0 — A9.73 MPC5121E/MPC5123 Data Sheet, Rev. 5 58 Freescale Semiconductor Electrical and Thermal Characteristics Table 31. Timing Parameters UDMA Out Burst (continued) 1 ATA Parameter UDMA Out Timing Parameter tli tli2 tli2 > 0 — A9.74 tli tli3 tli3 > 0 — A9.75 tcvh tcvh tcvh = (time_cvh × T) – (tskew1 + tskew2) calculate and program time_cvh. 1 A9.76 — ton toff ton = time_on × T – tskew1 toff = time_off × T – tskew1 — A9.77 Value How to meet SpecID See the MPC5121e Microcontroller Reference Manual. 3.3.10 SATA PHY 1.5 Gbps SATA PHY Layer See “Serial ATA: High Speed Serialized AT Attachment” Revision 1.0a, 7-January-2003. 3.3.11 FEC AC Test Timing Conditions: • Output Loading All Outputs: 25 pF Table 32. MII Rx Signal Timing Symbol Min Max Unit SpecID 1 RXD [ 3 : 0 ], RX_DV, RX_ER to RX_CLK setup 5 — ns A11.1 2 RX_CLK to RXD [ 3 : 0 ], RX_DV, RX_ER hold 5 — ns A11.2 3 4 1 Description RX_CLK pulse width high 35% RX_CLK pulse width low 35% 65% 65% RX_CLK Period1 A11.3 RX_CLK Period1 A11.4 RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification. 3 RX_CLK (Input) 4 RXD[3:0] (inputs) RX_DV RX_ER 1 2 Figure 36. Ethernet Timing Diagram – MII Rx Signal MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 59 Electrical and Thermal Characteristics Table 33. MII Tx Signal Timing Symbol Min Max Unit SpecID 5 TX_CLK rising edge to TXD [ 3 : 0 ], TX_EN, TX_ER invalid 3 — ns A11.5 6 TX_CLK rising edge to TXD [ 3 : 0 ], TX_EN, TX_ER valid — 25 ns A11.6 7 TX_CLK pulse width high 35% 65% TX_CLK Period1 A11.7 65% 1 A11.8 8 1 Description TX_CLK pulse width low 35% TX_CLK Period The TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must provide a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See the IEEE 802.3 Specification. 7 TX_CLK (Input) 5 8 TXD[3:0] (Outputs) TX_EN TX_ER 6 Figure 37. Ethernet Timing Diagram – MII Tx Signal Table 34. MII Async Signal Timing Symbol 9 Description CRS, COL minimum pulse width CRS, COL Min Max Unit SpecID 1.5 — TX_CLK Period A11.9 9 Figure 38. Ethernet Timing Diagram – MII Async Table 35. MII Serial Management Channel Signal Timing Symbol 1 Description Min Max Unit SpecID 10 MDC falling edge to MDIO output delay 0 25 ns A11.10 11 MDIO ( input ) to MDC rising edge setup 10 — ns A11.11 12 MDIO ( input ) to MDC rising edge hold 0 — ns A11.12 1 13 MDC pulse width high 160 — ns A11.13 14 MDC pulse width low 1 160 — ns A11.14 15 MDC period2 400 — ns A11.15 MDC is generated by MPC5121e/MPC5123 with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED control register is changed during operation. See the MPC5121e/MPC5123 Reference Manual. MPC5121E/MPC5123 Data Sheet, Rev. 5 60 Freescale Semiconductor Electrical and Thermal Characteristics 2 The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII characteristic) by programming the FEC MII_SPEED control register. See the MPC5121e/MPC5123 Reference Manual. 13 14 MDC (Output) 15 10 MDIO (Output) MDIO (Input) 11 12 Figure 39. Ethernet Timing Diagram – MII Serial Management MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 61 Electrical and Thermal Characteristics 3.3.12 USB ULPI This section specifies the USB ULPI timing. For more information refer to UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20, 2004. Clock TSC THC TSD THD Control In (dir, nxt) Data In (8-bit) TDC TDC Control Out (stp) TDD Data Out (8-bit) Figure 40. ULPI Timing Diagram Table 36. Timing Specifications – ULPI Symbol Min Max Units SpecID 15 — ns A12.1 TSC, TSD Setup time (control in, 8-bit data in) — 6.0 ns A12.2 THC, THD Hold time (control in, 8-bit data in) 0.0 — ns A12.3 TDC, TDD Output delay (control out, 8-bit data out) — 9.0 ns A12.4 TCK Description Clock Period NOTE Output timing is specified at a nominal 50 pF load. 3.3.13 On-Chip USB PHY The USB PHY is an USB2.0 compatible PHY integrated on-chip. See Chapter 7 in the USB Specification Rev. 2.0 at www.usb.org. 3.3.14 SDHC Figure 41 shows the timings of the SDHC. MPC5121E/MPC5123 Data Sheet, Rev. 5 62 Freescale Semiconductor Electrical and Thermal Characteristics SD4 SD2 SD1 SD5 MMCx_CLK SD3 MMCx_CMD MMCx_DAT_0 Output from SDHC to card MMCx_DAT_1 MMCx_DAT_2 MMCx_DAT_3 SD6 MMCx_CMD MMCx_DAT_0 Input from card to SDHC MMCx_DAT_1 MMCx_DAT_2 MMCx_DAT_3 SD7 SD8 Figure 41. SDHC Timing Diagram Table 37 lists the timing parameters. . Table 37. MMC/SD Interface Timing Parameters ID Parameter Symbols Min Max Unit SpecID Card Input Clock Clock Frequency (Low Speed) fPP1 0 400 kHz A14.1 Clock Frequency (SD/SDIO Full Speed/High Speed) fPP2 0 25/50 MHz A14.2 Clock Frequency (MMC Full Speed/High Speed) fPP3 0 20/52 MHz A14.3 Clock Frequency (Identification Mode) fOD4 100 400 kHz A14.4 SD2 Clock Low Time (Full Speed/High Speed) tWL 10/7 ns A14.5 SD3 Clock High Time (Full Speed/High Speed) tWH 10/7 ns A14.6 SD4 Clock Rise Time (Full Speed/High Speed) tTLH 10/3 ns A14.7 SD5 Clock Fall Time (Full Speed/High Speed) tTHL 10/3 ns A14.8 TH+3 ns A14.9 SD1 SDHC Output / Card Inputs CMD, DAT (Reference to CLK) SD6 SDHC Output Delay tOD TH5 – 3 SDHC Input / Card Outputs CMD, DAT (Reference to CLK) SD7 SDHC Input Setup Time tISU 2.5 ns A14.10 SD8 SDHC Input Hold Time tIH 2.5 ns A14.11 1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0 ~ 25 MHz. 3 In normal data transfer mode for MMC card, clock frequency can be any value between 0 ~ 20 MHz. 4 In card identification mode, card clock must be 100 kHz ~ 400 kHz, voltage ranges from 2.7 to 3.6 V. 5 Suggested ClockPeriod = T, CLK_DIVIDER (in SDHC Clock Rate Register) = D, then TH = [(D + 1)/2]/(D + 1) × T where the value is rounded. 2 MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 63 Electrical and Thermal Characteristics 3.3.15 DIU The DIU is a display controller designed to manage the TFT LCD display. 3.3.15.1 Interface to TFT LCD Panels, Functional Description Figure 42 shows the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with positive polarity. The sequence of events for active matrix interface timing is: • • • • DIU_CLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode, DIU_CLK runs continuously. This signal frequency could be from 5 to 100 MHz depending on the panel type. DIU_HSYNC causes the panel to start a new line. It always encompasses at least one DIU_CLK pulse. DIU_VSYNC causes the panel to start a new frame. It always encompasses at least one DIU_HSYNC pulse. DIU_DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off. DIU_VSYNC DIU_HSYNC LINE 1 LINE 3 LINE 2 LINE 4 LINE n-1 LINE n DIU_HSYNC DIU_DE 1 2 3 m-1 m DIU_CLK DIU_LD[23:0] Figure 42. Interface Timing Diagram for TFT LCD Panels 3.3.15.2 Interface to TFT LCD Panels, Electrical Characteristics Figure 43 shows the horizontal timing (timing of one line), including the horizontal sync pulse and the data. All parameters shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DIU_CLK signal (meaning the data and sync. signals change at the rising edge of it) and active-high polarity of the DIU_HSYNC, DIU_VSYNC and DIU_DE signal. You can select the polarity of the DIU_HSYNC and DIU_VSYNC signal via the SYN_POL register, whether active-high or active-low, the default is active-high. The DIU_DE signal is always active-high. And, pixel clock inversion and a flexible programmable pixel clock delay is also supported, programed via the DIU Clock Config Register (DCCR) in the system clock module. MPC5121E/MPC5123 Data Sheet, Rev. 5 64 Freescale Semiconductor Electrical and Thermal Characteristics tHSP Start of line tPWH tFPH tSW tBPH tPCP DIU_CLK 11 Invalid Data DIU_LD[23:0] 2 3 DELTA_X Invalid Data DIU_HSYNC DIU_DE Figure 43. TFT LCD Interface Timing Diagram – Horizontal Sync Pulse Figure 44 shows the vertical timing (timing of one frame), including the vertical sync pulse and the data. All parameters shown in the diagram are programmable. tVSP Start of Frame tSH tBPV tPWV tFPV tHSP DIU_HSYNC DIU_LD[23:0] (Line Data) 1 Invalid Data 2 3 Invalid Data DELTA_Y DIU_VSYNC DIU_DE Figure 44. TFT LCD Interface Timing Diagram – Vertical Sync Pulse Table 38 shows timing parameters of signals. Table 38. LCD Interface Timing Parameters – Pixel Level Name Description Value Unit SpecID tPCP Display Pixel Clock Period 151 ns A15.1 tPWH HSYNC Pulse Width PW_H × tPCP ns A15.2 tBPH HSYNC Back Porch Width BP_H × tPCP ns A15.3 MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 65 Electrical and Thermal Characteristics Table 38. LCD Interface Timing Parameters – Pixel Level (continued) Name 1 Description Value Unit SpecID tFPH HSYNC Front Porch Width FP_H × tPCP ns A15.4 tSW Screen Width DELTA_X × tPCP ns A15.5 tHSP HSYNC (Line) Period (PW_H + BP_H + DELTA_X + FP_H) × tPCP ns A15.6 tPWV VSYNC Pulse Width PW_V × tHSP ns A15.7 tBPV VSYNC Back Porch Width BP_V × tHSP ns A15.8 tFPV VSYNC Front Porch Width FP_V × tHSP ns A15.9 tSH Screen Height DELTA_Y × tHSP ns A15.10 tVSP VSYNC (Frame) Period (PW_V + BP_V + DELTA_Y + FP_H) × tHSP ns A15.11 Display interface pixel clock period immediate value (in nanosecond). The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register; The PW_H, BP_H, and FP_H parameters are programmed via the HSYN_PARA register; And the PW_V, BP_V and FP_V parameters are programmed via the VSYN_PARA register. See appropriate section in the reference manual for detailed descriptions on these parameters. Figure 45 shows the synchronous display interface timing for access level, and Table 39 lists the timing parameters. tCHD tCSU tDHD tDSU DIU_HSYNC DIU_VSYNC DIU_DE DIU_CLK tCKH tCKL DIU_LD[23:0] Figure 45. LCD Interface Timing Diagram – Access Level Table 39. LCD Interface Timing Parameters – Access Level Parameter Description Min Typ Max Unit SpecID tCKH LCD Interface Pixel Clock High Time tPCP × 0.4 tPCP × 0.5 tPCP × 0.6 ns A15.12 tCKL LCD Interface Pixel Clock Low Time tPCP × 0.4 tPCP × 0.5 tPCP × 0.6 ns A15.13 tDSU LCD Interface Data Setup Time 5.0 — — ns A15.14 tDHD LCD Interface Data Hold Time 6.0 — — ns A15.15 tCSU LCD Interface Control Signal Setup Time 5.0 — — ns A15.16 tCHD LCD Interface Control Signal Hold Time 6.0 — — ns A15.17 MPC5121E/MPC5123 Data Sheet, Rev. 5 66 Freescale Semiconductor Electrical and Thermal Characteristics 3.3.16 SPDIF The Sony/Philips Digital Interface (SPDIF) timing is totally asynchronous, therefore there is no need for relationship with the clock. 3.3.17 CAN The CAN functions are available as TX and CAN3/4_RX pins at normal IO pads and as CAN1/2 RX pins at the VBAT_RTC domain. There is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured. 3.3.18 I2C This section specifies the timing parameters of the Inter-Integrated Circuit (I2C) interface. Refer to the I2C Bus Specification. Table 40. I2C Input Timing Specifications – SCL and SDA Symbol 1 Start condition hold time Min Max Units SpecID 2 — IP-Bus Cycle1 A18.1 Cycle1 A18.2 2 Clock low time 8 — 4 Data hold time 0.0 — ns A18.3 6 Clock high time 4 — IP-Bus Cycle1 A18.4 7 Data setup time 0.0 — ns A18.5 8 9 1 Description Start condition setup time ( for repeated start condition only ) Stop condition setup time 2 2 — — IP-Bus IP-Bus Cycle1 A18.6 IP-Bus Cycle1 A18.7 Inter Peripheral Clock is defined in the MPC5121e/MPC5123 Reference Manual. Table 41. I2C Output Timing Specifications – SCL and SDA Symbol Description Min 11 Start condition hold time 6 21 Clock low time 33 SCL / SDA rise time 41 Max Units SpecID — IP-Bus Cycle2 A18.8 10 — IP-Bus Cycle2 A18.9 — 7.9 ns A18.10 Data hold time 7 — 5 SCL / SDA fall time — 7.9 ns A18.12 61 Clock high time 10 — IP-Bus Cycle2 A18.13 — Cycle2 A18.14 2 A18.15 Cycle2 A18.16 1 71 1 8 91 Data setup time 2 Start condition setup time ( for repeated start condition only ) Stop condition setup time 20 10 — — IP-Bus Cycle2 IP-Bus IP-Bus Cycle IP-Bus A18.11 1 Programming IFDR with the maximum frequency results in the minimum output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed in IFDR. 2 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Inter Peripheral Clock is defined in the MPC5121e/MPC5123 Reference Manual. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 67 Electrical and Thermal Characteristics NOTE Output timing is specified at a nominal 50 pF load. 6 2 5 SCL 3 1 4 7 9 8 SDA Figure 46. Timing Diagram – I2C Input / Output 3.3.19 J1850 See the MPC5121e/MPC5123 Reference Manual. 3.3.20 PSC The Programmable Serial Controllers (PSC) support different modes of operation (UART, Codec, AC97, SPI). UART is an asynchronous interface, there is no AC characteristic. 3.3.20.1 Codec Mode (8,16,24 and 32-bit)/I2S Mode Table 42. Timing Specifications – 8,16, 24, and 32-bit CODEC/I2S Master Mode Symbol 1 1 Description Bit Clock cycle time, programmed in CCS register Min Typ Max Units SpecID 40.0 — — ns A20.1 A20.2 2 Clock duty cycle 45 50 55 %1 3 Bit Clock fall time — — 7.9 ns A20.3 4 Bit Clock rise time — — 7.9 ns A20.4 5 FrameSync valid after clock edge — — 8.4 ns A20.5 6 FrameSync invalid after clock edge — — 8.4 ns A20.6 7 Output Data valid after clock edge — — 9.3 ns A20.7 8 Input Data setup time 6.0 — — ns A20.8 Bit Clock cycle time NOTE Output timing is specified at a nominal 50 pF load. MPC5121E/MPC5123 Data Sheet, Rev. 5 68 Freescale Semiconductor Electrical and Thermal Characteristics 1 BitClk Output (CLKPOL=0) 3 2 2 4 BitClk Output (CLKPOL=1) 4 5 3 FrameSync Output (SyncPol = 1) 6 FrameSync Output (SyncPol = 0) 7 TxD Output 8 RxD Input Figure 47. Timing Diagram – 8, 16, 24, and 32-bit CODEC/I2S Master Mode Table 43. Timing Specifications – 8, 16, 24, and 32-bit CODEC/I2S Slave Mode Symbol 1 1 Description Bit Clock cycle time Min Typ Max Units SpecID 40.0 — — ns A20.9 A20.10 2 Clock duty cycle — 50 — %1 3 FrameSync setup time 1.0 — — ns A20.11 4 Output Data valid after clock edge — — 14.0 ns A20.12 5 Input Data setup time 1.0 — — ns A20.13 6 Input Data hold time 1.0 — — ns A20.14 Bit Clock cycle time NOTE Output timing is specified at a nominal 50 pF load. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 69 Electrical and Thermal Characteristics 1 BitClk Input (CLKPOL=0) 2 2 BitClk Input (CLKPOL=1) FrameSync Input (SyncPol = 1) 3 FrameSync Input (SyncPol = 0) 4 TxD Output 5 RxD Input 6 Figure 48. Timing Diagram – 8,16, 24, and 32-bit CODEC/I2S Slave Mode 3.3.20.2 AC97 Mode Table 44. Timing Specifications – AC97 Mode Symbol Description Min Typ Max Units SpecID 1 Bit Clock cycle time — 81.4 — ns A20.15 2 Clock pulse high time — 40.7 — ns A20.16 3 Clock pulse low time — 40.7 — ns A20.17 4 FrameSync valid after rising clock edge — — 13.0 ns A20.18 5 Output Data valid after rising clock edge — — 14.0 ns A20.19 6 Input Data setup time 1.0 — — ns A20.20 7 Input Data hold time 1.0 — — ns A20.21 NOTE Output timing is specified at a nominal 50 pF load. MPC5121E/MPC5123 Data Sheet, Rev. 5 70 Freescale Semiconductor Electrical and Thermal Characteristics 1 BitClk (CLKPOL=0) Input 4 FrameSync (SyncPol = 1) Output 5 3 2 Sdata_out Output 6 7 Sdata_in Input Figure 49. Timing Diagram – AC97 Mode 3.3.20.3 SPI Mode Table 45. Timing Specifications – SPI Master Mode, Format 0 (CPHA = 0) Symbol Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A20.26 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.27 3 Slave select clock delay, programable in the PSC CCS register 30.0 — ns A20.28 4 Output Data valid after Slave Select (SS) — 8.9 ns A20.29 5 Output Data valid after SCK — 8.9 ns A20.30 6 Input Data setup time 6.0 — ns A20.31 7 Input Data hold time 1.0 — ns A20.32 8 Slave disable lag time — TSCK ns A20.33 9 Sequential Transfer delay, programmable in the PSC CTUR / CTLR register 15.0 — ns A20.34 10 Clock falling time — 7.9 ns A20.35 11 Clock rising time — 7.9 ns A20.36 NOTE Output timing is specified at a nominal 50 pF load. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 71 Electrical and Thermal Characteristics 1 SCK (CLKPOL=0) Output 2 10 2 11 SCK (CLKPOL=1) Output 11 10 9 8 3 SS Output 5 4 MOSI Output 6 6 MISO Input 7 7 Figure 50. Timing Diagram – SPI Master Mode, Format 0 (CPHA = 0) Table 46. Timing Specifications – SPI Slave Mode, Format 0 (CPHA = 0) Symbol Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A20.37 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.38 3 Slave select clock delay 1.0 — ns A20.39 4 Input Data setup time 1.0 — ns A20.40 5 Input Data hold time 1.0 — ns A20.41 6 Output data valid after SS — 14.0 ns A20.42 7 Output data valid after SCK — 14.0 ns A20.43 8 Slave disable lag time 0.0 — ns A20.44 9 Minimum Sequential Transfer delay = 2 × IP Bus clock cycle time 30.0 — — A20.45 NOTE Output timing is specified at a nominal 50 pF load. MPC5121E/MPC5123 Data Sheet, Rev. 5 72 Freescale Semiconductor Electrical and Thermal Characteristics 1 SCK (CLKPOL=0) Input 2 2 SCK (CLKPOL=1) Input 9 8 3 SS Input 5 4 MOSI Input 7 6 MISO Output Figure 51. Timing Diagram – SPI Slave Mode, Format 0 (CPHA = 0) Table 47. Timing Specifications – SPI Master Mode, Format 1 (CPHA = 1) Symbol Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A20.46 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.47 3 Slave select clock delay, programable in the PSC CCS register 30.0 — ns A20.48 4 Output data valid — 8.9 ns A20.49 5 Input Data setup time 6.0 — ns A20.50 6 Input Data hold time 1.0 — ns A20.51 7 Slave disable lag time — TSCK ns A20.52 8 Sequential Transfer delay, programable in the PSC CTUR / CTLR register 15.0 — ns A20.53 9 Clock falling time — 7.9 ns A20.54 10 Clock rising time — 7.9 ns A20.55 NOTE Output timing is specified at a nominal 50 pF load. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 73 Electrical and Thermal Characteristics 1 9 SCK (CLKPOL=0) Output 2 2 10 10 9 SCK (CLKPOL=1) Output 8 7 3 SS Output 4 MOSI Output 5 MISO Input 6 Figure 52. Timing Diagram – SPI Master Mode, Format 1 (CPHA = 1) Table 48. Timing Specifications – SPI Slave Mode, Format 1 (CPHA = 1) Symbol Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A20.56 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.57 3 Slave select clock delay 0.0 — ns A20.58 4 Output data valid — 14.0 ns A20.59 5 Input Data setup time 2.0 — ns A20.60 6 Input Data hold time 1.0 — ns A20.61 7 Slave disable lag time 0.0 — ns A20.62 8 Minimum Sequential Transfer delay = 2 × IP-Bus clock cycle time 30.0 — ns A20.63 NOTE Output timing is specified at a nominal 50 pF load. MPC5121E/MPC5123 Data Sheet, Rev. 5 74 Freescale Semiconductor Electrical and Thermal Characteristics 1 SCK (CLKPOL=0) Input 2 2 SCK (CLKPOL=1) Input 8 7 3 SS Input 5 6 MOSI Input 4 MISO Output Figure 53. Timing Diagram – SPI Slave Mode, Format 1 (CPHA = 1) 3.3.21 GPIOs and Timers The MPC5121e/MPC5123 contains several sets of I/Os that do not require special setup, hold, or valid requirements. The external events (GPIO or timer inputs) are asynchronous to the system clock. The inputs must be valid for at least tIOWID to ensure proper capture by the internal IP clock. Table 49. GPIO/Timers Input AC Timing Specifications Symbol tIOWID 1 Description GPIO/Timers inputs—minimum pulse width Min Unit SpecID 2T1 ns A21.1 T is the IP bus clock cycle. T= 12 ns is the minimum value (for the maximum IP bus frequency of 83 MHz). 3.3.22 Fusebox Table 50 gives the Fusebox specification. Table 50. Fusebox Characteristics Symbol tFUSEWR Program Description time1 for Fuse IFUSEWR Program current to program one fuse bit 1 Min Max Units SpecID 125 — us A22.1 — 10 mA A22.2 The program length is defined by the value defined in the EPM_PGM_LENGTH bits of the IIM module. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 75 Electrical and Thermal Characteristics 3.3.23 IEEE 1149.1 (JTAG) Table 51. JTAG Timing Specification Symbol Characteristic Min Max Unit SpecID — TCK frequency of operation 0 25 MHz A23.1 1 TCK cycle time 40 — ns A23.2 2 TCK clock pulse width measured at 1.5 V 1.08 — ns A23.3 3 TCK rise and fall times 0 3 ns A23.4 1 4 TRST setup time to tck falling edge 10 — ns A23.5 5 TRST assert time 5 — ns A23.6 2 6 Input data setup time 5 — ns A23.7 7 Input data hold time 15 — ns A23.8 TCK to output data valid3 0 30 ns A23.9 9 TCK to output high impedance3 0 30 ns A23.10 10 TMS, TDI data setup time. 5 — ns A23.11 11 TMS, TDI data hold time. 1 — ns A23.12 12 TCK to TDO data valid. 0 15 ns A23.13 13 TCK to TDO high impedance. 0 15 ns A23.14 8 1 TRST is an asynchronous signal. The setup time is for test purposes only. Non-test, other than TDI and TMS, signal input timing with respect to TCK. 3 Non-test, other than TDO, signal output timing with respect to TCK. 2 1 2 VM TCK 3 2 VM VM 3 VM = Midpoint Voltage Figure 54. Timing Diagram – JTAG Clock Input MPC5121E/MPC5123 Data Sheet, Rev. 5 76 Freescale Semiconductor Electrical and Thermal Characteristics TCK 4 TRST 5 Figure 55. Timing Diagram – JTAG TRST TCK 6 7 Input Data Valid Data Inputs 8 Output Data Valid Data Outputs 9 Data Outputs Figure 56. Timing Diagram – JTAG Boundary Scan TCK 10 11 Input Data Valid TDI, TMS 12 Output Data Valid TDO 13 TDO Figure 57. Timing Diagram – Test Access Port MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 77 Electrical and Thermal Characteristics 3.3.24 VIU The Video Input Unit (VIU) is an interface which accepts the ITU656 format compatible video stream. Figure 58 shows the VIU interface timing and Table 52 lists the timing parameters. VIU_PIX_CLK fPIX_CLK tDHD tDSU VIU_DATA[9:0] Figure 58. VIU Interface Timing Diagram Table 52. VIU Interface Timing Parameters Parameter Min Typ Max Unit SpecID VIU Pixel Clock Frequency — — 83 MHz A24.1 tDSU VIU Data Setup Time 2.5 — — ns A24.2 tDHD VIU Data Hold Time 2.5 — — ns A24.3 fPIX_CK Description MPC5121E/MPC5123 Data Sheet, Rev. 5 78 Freescale Semiconductor System Design Information 4 System Design Information 4.1 Power Up/Down Sequencing Power sequencing between the 1.4 V power supply VDD_CORE and the remaining supplies is required to prevent excessive current during power up phase. The required power sequence is as follows: • • • • • 4.2 Use 12 V/millisecond or slower time for all supplies. Power up VDD_IO, PLL_AVDD, VBAT_RTC (if not applied permanently), VDD_MEM_IO, USB PHY, and SATA PHY supplies first in any order and then power up VDD_CORE. If required, AVDD_FUSEWR should be powered up afterwards. All the supplies must reach the specified operating conditions before the PORESET can be released. For power down, drop AVDD_FUSEWR to 0 V first, drop VDD_CORE to 0 V, and then drop all other supplies. VDD_CORE should not exceed VDD_IO, VDD_MEM_IO, VBAT_RTC, or PLL_AVDDs by more than 0.4 V at any time, including power-up. System and CPU Core AVDD Power Supply Filtering Each of the independent PLL power supplies require filtering external to the device. The following drawing Figure 59 is a recommendation for the required filter circuit. Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. All traces should be as low impedance as possible, especially ground pins to the ground plane. The filter for System/Core PLLVDD to VSS should be connected to the power and ground planes, respectively, not fingers of the planes. In addition to keeping the filter components for System/Core PLLVDD as close as practical to the body of the MPC5121e as previously mentioned, special care should be taken to avoid coupling switching power supply noise or digital switching noise onto the portion of that supply between the filter and the MPC5121e. R1 = 10  AVDD device pin Power supply source C1 = 1 F C2 = 0.1 F Figure 59. Power Supply Filtering The capacitors for C2 in Figure 59 should be rated X5R or better due to temperature performance. It is recommended to add a bypass capacitance of at least 1 µF for the VBAT_RTC pin. 4.3 Connection Recommendations To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to VDD_IO. Unused active high inputs should be connected to VSS. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD and VSS pins of the MPC5121e/MPC5123. The unused AVDD_FUSEWR power should be connected to VSS directly or via a resistor. For DDR or LPDDR modes the unused pins MVTT[3:0] for DDR2 Termination voltage can be unconnected. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 79 System Design Information The SATA PHY needs to be powered even if it is not used in an application. In this case, you should not enable the SATA oscillator and the SATA PHY by software. SATA_XTALI SATA_XTALO VSS NC NC NC SATA_ANAVIZ SATA_RESREF NC NC SATA_TXP SATA_TXN NC NC SATA_RXP SATA_RXN MPC5121e/ MPC5123 SATA_VDDA_3P3 SATA_VDDA_1P2 SATA_VDDA_VREG SATA_PLL_VDDA1P2 VDD_IO VDD_CORE 1.7–2.6 V VDD_CORE SATA_PLL_VSSA SATA_RX_VSSA SATA_TX_VSSA VSS VSS VSS Figure 60. Recommended Connection for Pins of Unused SATA PHY VSS NC USB_XTALI MPC5121e/MPC5123 USB_XTALO NC USB_TPA Weak pull-up or pull-down USB_DP USB_DN VDD_IO VSS VSS VSS VSS VSS VSS USB_VBUS USB_UID USB_PLL_GND USB_PLL_PWR3 USB_RREF VSS VDD_IO USB_VSSA USB_VDDA USB_VSSA_BIAS USB_VDDA_BIAS Figure 61. Recommended connection for pins of unused USB PHY 4.4 Pull-Up/Pull-Down Resistor Requirements The MPC5121e/MPC5123 requires external pull-up or pull-down resistors on certain pins. 4.4.1 Pull-Down Resistor Requirements for TEST pin The MPC5121e/MPC5123 requires a pull-down resistor on the test pin TEST. MPC5121E/MPC5123 Data Sheet, Rev. 5 80 Freescale Semiconductor System Design Information 4.4.2 Pull-Up Requirements for the PCI Control Lines PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain stable values when no agent is actively driving the bus. This includes PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL, PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ. Refer to the PCI Local Bus specification. 4.5 JTAG The MPC5121e/MPC5123 provides you with an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a Common On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The COP Interface provides access to the MPC5121e/MPC5123’s embedded e300 processor and to other on-chip resources. This interface provides a means for executing test routines and for performing software development and debug functions. 4.5.1 TRST Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification but is provided on all processors that implement the Power Architecture. To obtain a reliable power-on reset performance, the TRST signal must be asserted during power-on reset. 4.5.1.1 TRST and PORESET The JTAG interface can control the direction of the MPC5121e/MPC5123 I/O pads via the boundary scan chain. The JTAG module must be reset before the MPC5121e/MPC5123 comes out of power-on reset; do this by asserting TRST before PORESET is released. For more details refer to the Reset and JTAG Timing Specification. PORESET Required assertion of TRST Optional assertion of TRST TRST Figure 62. PORESET vs. TRST 4.5.2 e300 COP / BDM Interface There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector. 4.5.2.1 Boards Interfacing the JTAG Port via a COP Connector The MPC5121e/MPC5123 functional pin interface and internal logic provides access to the embedded e300 processor core through the Freescale standard COP / BDM interface. Table 53 gives the COP / BDM interface signals. The pin order shown reflects only the COP / BDM connector order. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 81 System Design Information Table 53. COP / BDM Interface Signals BDM Pin # MPC5121e/MPC5123 I / O Pin BDM Connector Internal Pull Up / Down External Pull Up / Down I/O1 16 — GND — — — 15 CKSTP_OUT ckstp_out — 10 k Pull-up I 14 — KEY — — — 13 HRESET hreset Pull-up 10 k Pull-up O 12 — GND — — — 11 SRESET sreset Pull-up 10 k Pull-up O 10 — N/C — — — 9 TMS tms Pull-up 10 k Pull-up O 8 CKSTP_IN ckstp_in — 10 k Pull-up O 7 TCK tck Pull-up 10 k Pull-up O 6 — VDD 2 — — — 5 Note3 halted3 — — I See 4 TRST trst Pull-up 10 k Pull-up O 3 TDI tdi Pull-up 10 k Pull-up O 2 See Note4 qack4 — — O 1 TDO tdo — — I 1 With respect to the emulator tool’s perspective: Input is really an output from the embedded e300 core. Output is really an input to the core. 2 From the board under test, power sense for chip power. 3 HALTED is not available from e300 core. 4 Input to the e300 core to enable / disable soft-stop condition during breakpoints. MPC5121e/MPC5123 internally ties CORE_QACK to GND in its normal / functional mode (always asserted). For a board with a COP (common on-chip processor) connector that accesses the JTAG interface and needs to reset the JTAG module, only wiring TRST and PORESET is not recommended. To reset the MPC5121e/MPC5123 via the COP connector, the HRESET pin of the COP should be connected to the HRESET pin of the MPC5121e/MPC5123. The circuitry shown in Figure 63 allows the COP to assert HRESET or TRST separately, while any other board sources can drive PORESET. MPC5121E/MPC5123 Data Sheet, Rev. 5 82 Freescale Semiconductor System Design Information PORESET PORESET COP Header 13 11 HRESET 1 2 3 4 5 6 7 8 11 13 10 12 K VDD_IO 10 k 10 k SRESET VDD_IO 4 TRST TRST 14 9 10 k TMS VDD_IO TMS 12 7 9 HRESET VDD_IO SRESET 16 COP Connector Physical Pinout 10 k 3 VDD_IO VDD_IO 62 1 10 k TCK TCK TDO TDO 10 k TDI VDD_IO TDI 15 16 15 CKSTP_OUT 10 k VDD_IO CKSTP_OUT 8 CKSTP_IN 5 (3) halted 2 (4) qack 10 10 k VDD_IO CKSTP_IN (LPC_CLK) NC NC NC Figure 63. COP Connector Diagram 4.5.2.2 Boards Without COP Connector If the JTAG interface is not used, TRST should be tied to PORESET, so that it is asserted when the system reset signal (PORESET) is asserted. This ensures that the JTAG scan chain is initialized during power on. Figure 64 shows the connection of the JTAG interface without COP connector. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 83 System Design Information PORESET HRESET SRESET PORESET 10 k HRESET VDD_IO 10 k VDD_IO SRESET TRST 10 k VDD_IO TMS 10 k VDD_IO TCK 10 k VDD_IO TDI CKSTP_OUT TDO Figure 64. TRST Wiring for Boards without COP Connector MPC5121E/MPC5123 Data Sheet, Rev. 5 84 Freescale Semiconductor Package Information 5 Package Information This section details package parameters and dimensions. The MPC5121e/MPC5123 is available in a Thermally Enhanced Plastic Ball Grid Array (TEPBGA), see Section 5.1, “Package Parameters,” and Section 5.2, “Mechanical Dimensions,” for information on the TEPBGA. 5.1 Package Parameters Table 54. TEPBGA Parameters 5.2 Package outline 27 mm  27 mm Interconnects 516 Pitch 1.00 mm Module height (typical) 2.25 mm Solder Balls 96.5 Sn/3.5Ag (VY package) Ball diameter (typical) 0.6 mm Mechanical Dimensions Figure 65 shows the mechanical dimensions and bottom surface nomenclature of the MPC5121e/MPC5123 516 PBGA package. MPC5121E/MPC5123 Data Sheet, Rev. 5 Freescale Semiconductor 85 Package Information Figure 65. Mechanical Dimension and Bottom Surface Nomenclature of the MPC5121e/MPC5123 TEPBGA 1 All dimensions are in millimeters. Dimensions and tolerances per ASME Y14.5M-1994. 3 Maximum solder ball diameter measured parallel to datum A. 4 Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 2 MPC5121E/MPC5123 Data Sheet, Rev. 5 86 Freescale Semiconductor Product Documentation 6 Product Documentation This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com. Table 55 provides a revision history for this document. Table 55. Document Revision History Revision Substantive Change(s) Rev. 0, DraftA First Draft (5/2008) Rev. 0, DraftB Second Draft (5/2008) Rev. 0, DraftC Third Draft (7/2008) Rev. 1 Advance Information (10/2008) Rev. 2 Technical Data (2/2009) Rev. 3 Technical Data (2/2009). Corrected Table 5, Footnote 3. Rev. 3.1 Technical Data (12/2009). Interim release for removing AVDD_FUSERD throughout document, changing pin D9 to VDD_IO, and adding D9 to list of pins for VDD_IO. Rev. 4 Technical Data (1/2010). Minor editorial and graphical updates.  No technical updates. Rev 5 — Updated table “DDR and DDR2 SDRAM Timing Specification”, removed the row of ‘MCK AC differential crosspoint voltage' . — Updated table “Thermal Resistance Data”. — Added table “NFC Timing Characteristics in Symmetric Mode ”and added figure “Read data latch timing in Symmetric Mode”. —Published as Rev. 5 MPC5121E/MPC5123 Data Sheet, Rev. 5 87 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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