PTN36043BXZ

PTN36043 USB Type-C SuperSpeed active switch Rev. 2 — 19 February 2018 Product data sheet 1. General description PTN36043 is a very small, low power 2 differential channel 2 to 1 active multiplex/demultiplexer switch with integrated SuperSpeed USB 3.1 Gen 1 (also known as USB 3.0) redriver IC that can switch two differential signals to one of two locations. The active switch has optimized performance with minimized crosstalk, as required by the high-speed serial interface for USB Type-C connector. PTN36043 allows expansion of existing high-speed ports for very low power consumption. With integrated USB 3.1 Gen 1 redriver, signal quality is enhanced by performing receive equalization on the deteriorated input signal followed by transmit de-emphasis maximizing system link performance. With its superior differential signal conditioning and enhancement capability, the device delivers significant flexibility and performance scaling for various systems with different PCB characteristics and cable channel conditions and still benefit from optimum power consumption. PTN36043 has built-in advanced power management capability that enables significant power savings under various different USB 3.1 Gen 1 Low-power modes (U2/U3). It can detect link electrical conditions and can dynamically activate/de-activate internal circuitry and logic. The device performs these actions without host software intervention and conserves power. PTN36043 is powered from a 1.8 V supply and is available in a small DHX2QFN18 package (2.4 mm  2.0 mm  0.35 mm) with 0.4 mm pitch. 2. Features and benefits  2 bidirectional differential channel, 2 : 1 multiplex/demultiplexer switch, supports USB 3.1 Gen 1 specification (SuperSpeed only)  Compliant to SuperSpeed USB 3.1 Gen 1 standard  Pin out data flow matches USB Type-C connector pin assignments  Two control pins for each channel to select optimized signal conditions  Receive equalization on each channel to recover from InterSymbol Interference (ISI) and high-frequency losses, with provision to choose equalization gain settings per channel  Transmit de-emphasis on each channel delivers pre-compensation suited to channel conditions  Output swing adjustment  Integrated termination resistors provide impedance matching on both transmit and receive sides  Automatic receiver termination detection  Low active power: 203 mW/113 mA (typical) for VDD = 1.8 V PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch  Power-saving states:  1.35 mW/0.75 mA (typical) when in U2/U3 states  0.81 mW/0.45 mA (typical) when no connection detected  Excellent differential and common return loss performance  14 dB differential and 15 dB common-mode return loss for 10 MHz to 1250 MHz  Flow-through pinout to ease PCB layout and minimize crosstalk effects  Power supply: VDD = 1.8 V (typical)  Compliant with JESD 78 Class II latch up test standard  Very thin DHX2QFN18 package: 2.4 mm x 2.0 mm x 0.35 mm, 0.4 mm pitch  ESD protection exceeds 7000 V HBM per JDS-001-2012 and 1000 V CDM per JESD22-C101  Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA  Operating temperature range: 40°C to +85°C 3. Applications      USB 3.1 Gen 1 application for USB Type-C connectors Smart Phones, Tablets/Mobile Devices Desktop/Notebook Computers Docking Stations USB 3.1 Gen 1 Peripherals such as flat panel display, consumer/storage devices, printers or USB 3.1 Gen 1 capable hubs/repeaters 4. Ordering information Table 1. Ordering information Type number PTN36043BX Topside marking Package 43 DHX2QFN18 plastic dual in-line compatible thermal enhanced extremely thin quad flat package; no leads; 18 terminals; body 2.4 mm  2.0 mm  0.35 mm Name Description Version SOT1442-1 4.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method PTN36043BX PTN36043BXY DHX2QFN18 REEL 13" Q1/T1 *STANDARD 10000 MARK SMD DP PTN36043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 Minimum order quantity Temperature Tamb = 40 C to +85 C © NXP Semiconductors N.V. 2018. All rights reserved. 2 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 5. Block diagram VDD = 1.8 V PTN36043 line driver TX_CON_1+ TX_CON_1− RX TERMINATION DETECTION line driver equalizer TX_AP_+ TX_AP_− TX_CON_2+ TX_CON_2− EMPHASIS FILTER SIGNAL DETECTION line driver RX_AP_+ RX_AP_− equalizer RX_CON_1+ RX_CON_1− EMPHASIS FILTER RX TERMINATION DETECTION SIGNAL DETECTION equalizer RX_CON_2+ RX_CON_2− DEVICE CONTROL AND MANAGEMENT SEL Fig 1. PTN36043 Product data sheet CH1_SET1 CH1_SET2 CH2_SET1 CH2_SET2 aaa-017471 Block diagram of PTN36043 All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 3 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 6. Pinning information RX_AP_+ RX_AP_- SEL TX_AP_+ TX_AP_- 18 17 16 15 14 6.1 Pinning CH1_SET1 1 RX_CON_1+ 2 13 CH2_SET1 12 TX_CON_2+ 11 TX_CON_2- 10 CH2_SET2 PTN36043 7 8 9 RX_CON_2- RX_CON_2+ VDD1V8 GND TX_CON_1- 4 6 CH1_SET2 TX_CON_1+ 3 5 RX_CON_1- aaa-016462 Transparent top view Fig 2. Pin configuration for DHX2QFN18 6.2 Pin description Table 3. PTN36043 Product data sheet Pin description Symbol Pin Type Description RX_AP_+ 18 Output RX_AP_ 17 USB 3.1 Gen 1 differential output signals of the RX path to application processor TX_AP_+ 15 Input TX_AP_ 14 USB 3.1 Gen 1 differential input signals of the TX path from application processor TX_CON_1+ 6 Output USB 3.1 Gen 1 differential output signals of the TX path to connector side port 1 Input USB 3.1 Gen 1 differential input signals of the RX path from connector side port 1 Output USB 3.1 Gen 1 differential output signals of the TX path to connector side port 2 Input USB 3.1 Gen 1 differential input signals of the RX path from connector side port 2 TX_CON_1 7 RX_CON_1+ 2 RX_CON_1 3 TX_CON_2+ 12 TX_CON_2 11 RX_CON_2+ 9 RX_CON_2 8 All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 4 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch Table 3. Pin description …continued Symbol Pin Type Description SEL 16 input Output selection control When SEL=0, RX_AP_/TX_AP_ are connected to RX_CON_2/TX_CON_2, and RX_CON_1/TX_CON_1 are connected to VDD thru low ohmic resistor (50 ). When SEL=1, RX_AP_/TX_AP_ are connected to RX_CON_1/TX_CON_1, and RX_CON_2/TX_CON_2 are connected to VDD thru low ohmic resistor (50 ). PTN36043 Product data sheet Ternary input OS/DE/EQ control pins for channel facing the application processor side 10 Ternary input OS/DE/EQ control pins for channel facing the connector side 5 Power Power supply (1.8 V typical) Center Pad Power Ground. Center pad must be connected to GND plane for both electrical grounding and thermal relief purposes. CH1_SET1 1 CH1_SET2 4 CH2_SET1 13 CH2_SET2 VDD1V8 GND All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 5 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 7. Functional description Refer to Figure 1 “Block diagram of PTN36043”. PTN36043 is a high speed 2 to 1 active switch with integrated SuperSpeed USB 3.1 Gen 1 redriver meant to be used for signal integrity enhancement on various platforms - smart phone, tablet, notebook, hub, A/V display and peripheral devices, for example. With its high fidelity differential signal conditioning capability and wide configurability, this device is flexible and versatile enough for use under a variety of system environments. The following sections describe the individual block functions and capabilities of the device in more detail. 7.1 Receive equalization, transmitter de-emphasis and output swing level controls On the high-speed signal path, the device performs receive equalization (EQ) and transmitter de-emphasis (DE) and output swing control (OS). In addition, the device provides flat frequency gain by boosting output signal. Both flat and frequency selective gains prepare the system to cover up to losses further down the link. Table 4 lists DE/OS/EQ configuration options of the channel toward application processor side. Table 4. CH1_SET1 LOW OPEN HIGH Application Processor side DE/OS/EQ configuration options RX_AP_ De-emphasis RX_AP_  Output Swing TX_AP_ LOW 3.9 dB 1100 mV 3.0 dB OPEN 3.5 dB 900 mV 3.0 dB HIGH 0 dB 1100 mV 3.0 dB LOW 0 dB 900 mV 3.0 dB OPEN 3.9 dB 1100 mV 0 dB HIGH 3.5 dB 900 mV 0 dB LOW 0 dB 1100 mV 0 dB OPEN 0 dB 900 mV 0 dB HIGH 5.3 dB 1100 mV 6.0 dB CH1_SET2 Equalizer Table 5 lists DE/OS/EQ configuration options of the channel toward connector side. PTN36043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 6 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch Table 5. Connector side DE/OS/EQ configuration options CH2_SET1 CH2_SET2 TX_CON_1 TX_CON_2 De-emphasis TX_CON_1 TX_CON_2 Output Swing RX_CON_1 RX_CON_2 Equalizer LOW LOW 5.3 dB 1100 mV 0 dB OPEN 3.9 dB 1100 mV 0 dB HIGH 3.5 dB 900 mV 0 dB LOW 5.1 dB 900 mV 0 dB OPEN 3.9 dB 1100 mV 6.0 dB HIGH 3.5 dB 900 mV 6.0 dB LOW 5.3 dB 1100 mV 6.0 dB OPEN 5.1 dB 900 mV 6.0 dB HIGH 5.3 dB 1100 mV 9.0 dB OPEN HIGH 7.2 Device states and power management PTN36043 has implemented an advanced power management scheme that operates in tune with USB 3.1 Gen 1 bus electrical condition. Although the device does not decode USB power management commands (related to USB 3.1 Gen 1 U1/U2/U3 transitions) exchanged between USB 3.1 Gen 1 host and peripheral/device, it relies on bus electrical conditions and SEL pin setting to decide to be in one of the following states: • Active state wherein device is fully operational, USB data is transported on either port 1 or port 2 in Figure 1. In this state, USB connection exists and the Receive Termination indication remains active. But there is no need for Receive Termination detection. • Power-saving state wherein either port 1 or port 2 is kept enabled. In this state, squelching, detection and/or Receive termination detection circuitry are active. Based on USB connection, there are two possibilities: – No USB connection. – A USB connection exists and the link is in USB 3.1 Gen 1 U2/U3 mode. • Off state when PTN36043 is not being powered (i.e., VDD1V8 = 0 V), special steps should be done to prevent back-current issues on control pins such SEL or CH1/2_SET1/2 pins when these pins' states are not low. These pins can be controlled through two different ways. – pull-up/pull-down resistors - make sure these pull-up resistors' VDD is the same power source as to power PTN36043. When power to PTN36043 is off, power to these pull-up resistors will be off as well. – external processor's GPIO - if PTN36043 is turned off when the external processor's power stays on, processor should configure these GPIOs connected to these control pins as output low (< 0.4 V) or tri-state mode (configure GPIOs as input mode). This will make sure no current will be flowing into PTN36043 through these control pins. PTN36043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 7 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 7.3 SEL input pin PTN36043 is designed with 1:2 high speed de-multiplexer configuration. TX_AP_± and RX_AP_± can be connected to either TX_CON_1± and RX_CON_1±, or TX_CON_2± and RX_CON_2± by changing the SEL input state. Table 6. SEL input setting SEL Function 0 TX_CON_2± and RX_CON_2± are connected to TX_AP_± and RX_AP_± TX_CON_1± and RX_CON_1± are connected to VDD thru low ohmic resistor (50 ). 1 TX_CON_1± and RX_CON_1± are connected to TX_AP_± and RX_AP_± TX_CON_2± and RX_CON_2± are connected to VDD thru low ohmic resistor (50 ). 8. Application guideline for Control of CHx_SETx and SEL input pins PTN36043 implements ternary control IO logic on CHx_SETx and SEL control pins to detect HIGH (connected to VDD), LOW (connected to GND) or left unconnected condition (OPEN). For all control pins except SEL, all 3 pin conditions are applicable. If the SEL pin is left unconnected (OPEN), the internal logic treats it as LOW. To minimize the current consumption of IO circuitry on SEL pin, it is recommended this pin be driven from 1.8 V capable push-pull IO. If 1.8 V push-pull IO is not available in the application, the SEL pin can be driven from an open drain grounded NMOS GPIO with external pull-up resistor to the 1.8 V supply of PTN36043. The recommended value of the external pull-up resistor is 30 k. PTN36043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 8 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 9. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDD(1V8) supply voltage (1.8 V) [1] VI input voltage [1] Tstg storage temperature VESD electrostatic discharge voltage Min Max Unit 0.3 +2.2 V 0.3 +2.2 V 65 +150 C HBM [2] - 7000 V CDM [3] - 1000 V [1] All voltage values (except differential voltages) are with respect to network ground terminal. [2] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model - Component level; Electrostatic Discharge Association, Rome, NY, USA. [3] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA. 10. Recommended operating conditions Table 8. Operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD(1V8) supply voltage (1.8 V) 1.8 V supply option 1.7 1.8 1.9 V VI input voltage CMOS inputs 0.3 VDD(1V8) +2.2 V differential pairs 0.3 - +2.2 V operating in free air 40 - +85 C Tamb ambient temperature PTN36043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 9 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 11. Characteristics 11.1 Device characteristics Table 9. Device characteristics Symbol Parameter Conditions Min Typ Max Unit tstartup start-up time between supply voltage within operating range (90 % of VDD) until automatic receiver termination detection - - 6 ms trcfg1 setting reconfiguration time any configuration pin change (from one setting to another setting) to specified operating characteristics; device is supplied with valid supply voltage - - 3 ms trcfg2 port reconfiguration time Switching from one port to the other port (i.e., Port 1 to Port 2 or vice versa) until automatic receiver detection; device is supplied with valid supply voltage - - 7 ms tPD(dif) differential propagation delay between 50 % level at input and output; see Figure 3 - - 0.5 ns tidle idle time default wait time to wait before getting into Power-saving state - 300 400 ms time for exiting from Power-saving state and get into Active state; see Figure 5 - - 115 s td(pwrsave-act) delay time from power-save to active td(act-idle) delay time from active to idle reaction time for squelch detection circuit; see Figure 4 - 9 14 ns td(idle-act) delay time from idle to active reaction time for squelch detection circuit; see Figure 4 - 5 11 ns DDNEXT f < 2.5 GHz Differential near-end crosstalk between TX and RX signal pairs within the same port - 50 - dB Rth(j-a) thermal resistance from junction to ambient JEDEC still air test environment; value is based on simulation under JEDEC still air test environment with 2S2P(4L) JEDEC PCB - 96 - C/W jt junction to top of case thermal characterization parameter to case top; at ambient temperature of 85 C; value is based on simulation under JEDEC still air test environment with 2S2P(4L) JEDEC PCB - 1.0 - C/W IDD supply current Active state OS = 1100 mV/DE = 3.9 dB for both AP side and CON side - 113 - mA OS = 900 mV/DE = 3.5 dB for AP side,  OS = 1100 mV/DE = 3.9 dB for CON side - 108 - mA OS = 900 mV/DE = 0 dB for AP side,  OS = 1100 mV/DE = 3.9 dB for CON side - 103 - mA U2/U3 Power-saving state - 0.75 - mA no USB connection state - 0.45 - mA PTN36043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 10 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch IN+ in VSQTH VDC_CM IN− tPD(dif) tPD(dif) td(idle-act) td(act-idle) OUT+ out VDC_CM OUT− 002aag025 Fig 3. Propagation delay channel A, RX Fig 4. LFPS electrical idle transitions in U0/U1 modes U2 exit LFPS U2 exit LFPS channel A, TX channel B, RX U2 exit handshake LFPS U2 exit handshake LFPS channel B, TX 002aag026 RECOVERY RECOVERY RECOVERY RECOVERY block active td(pwrsave-act) 002aag028 Fig 5. U2/U3 exit behavior PTN36043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 11 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 11.2 Receiver AC/DC characteristics Table 10. Receiver AC/DC characteristics Symbol Parameter Conditions ZRX_DC receiver DC common-mode impedance Min Typ Max Unit 18 - 30  ZRX_DIFF_DC DC differential impedance RX pair 72 - 120  ZRX_HIGH_IMP common-mode input impedance DC common-mode input impedance when output of redriver is not terminated 25 - - k VRX(diff)(p-p) peak-to-peak differential receiver voltage 100 - 1200 mV VRX_DC_CM RX DC common mode voltage - 1.8 - V VRX_CM_AC_P RX AC common-mode voltage peak - - 150 mV Vth(i) signal detector input threshold voltage differential peak-to-peak value 75 - 150 mV RLDD11,RX RX differential mode return loss 10 MHz to 1250 MHz 12 14 - dB 1250 MHz to 2500 MHz 7 8.5 - dB 2500 MHz to 3000 MHz 6 7.5 - dB 10 MHz to 1250 MHz 12 15 - dB 1250 MHz to 2500 MHz 8 10 - dB 2500 MHz to 3000 MHz 7 9 - dB RLCC11,RX PTN36043 Product data sheet RX common mode return loss All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 12 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 11.3 Transmitter AC/DC characteristics Table 11. Transmitter AC/DC characteristics Symbol Parameter ZTX_DC Conditions Min Typ Max Unit transmitter DC common-mode impedance 18 - 30  ZTX_DIFF_DC DC differential impedance 72 - 120  VTX_DIFFp-p differential peak-to-peak output voltage 800 900 1000 mV RL = 100  OS = 900 mV OS = 1100 mV 1000 1100 1200 mV - 1.3 VDD(1V8) V device input fed with differential signal - - 100 mV when link is in electrical idle - - 10 mV 160 180 200 ps positive voltage swing to sense the receiver termination detection - 0.5  600 VTX_DIFFp-p mV TX receiver termination detect charging resistance output resistor of the transmitter when it does RX detection - 3.1 - k tr(tx) transmit rise time measured using 20 % and 80 % levels; see Figure 6 40 55 75 ps tf(tx) transmit fall time measured using 20 % and 80 % levels; see Figure 6 40 55 75 ps t(r-f)tx difference between transmit rise and fall time measured using 20 % and 80 % levels - - 20 ps RLDD11,TX TX differential mode return loss 10 MHz to 1250 MHz 12 13.5 - dB 1250 MHz to 2500 MHz 6.5 8 - dB VTX_DC_CM transmitter DC common-mode voltage VTX_CM_ACpp_ACTIV TX AC common-mode peak-to-peak output voltage (active state) VTX_IDL_DIFF_ACpp electrical idle differential peak-to-peak output voltage tW(deemp)TX transmitter de-emphasis pulse width VTX_RCV_DETECT voltage change allowed during receiver detection RTX_RCV_DETECT 2500 MHz to 3000 MHz RLCC11,TX 5 6.5 - dB 12 14 - dB 1250 MHz to 2500 MHz 8 10 - dB 2500 MHz to 3000 MHz 9 10 - dB TX common mode return loss 10 MHz to 1250 MHz 80 % 20 % tr(tx) tf(tx) 002aag027 Fig 6. PTN36043 Product data sheet Output rise and fall times All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 13 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 11.4 Ternary control inputs Table 12. Ternary control inputs CHx_SETx characteristics[1] Symbol Parameter VIH Min Typ Max Unit HIGH-level input voltage Trigger level of the Schmitt Trigger buffer when input is going from LOW to HIGH 0.70  VDD VDD VDD + 0.3 V VIL LOW-level input voltage Trigger level of the Schmitt Trigger buffer when input is going from HIGH to LOW 0.3 0 0.30  VDD V Rpu(ext) external pull-up resistor connected between VDD1V8 and setting pin; for detection of HIGH condition 0 - 30 k Rpd(ext) external pull-down resistor connected between setting pin and GND; for detection of LOW condition 0 - 30 k for detection of OPEN condition 250 - - k setting pin is driven LOW by external GPIO 45 - - A - - +45 A 6 - +6 A Zext(OPEN) external impedance Conditions IIL LOW-level input current IIH HIGH-level input current setting pin is driven HIGH (to 1.8 V) by external GPIO ILext(OPEN) external leakage current of external GPIO; for reliable detection of OPEN condition CL(ext) external load capacitance on setting pin; for reliable detection of OPEN condition - - 150 pF Rpu(int) internal pull-up resistance for detection of Ternary setting - 50 - k Rpd(int) internal pull-down resistance for detection of Ternary setting - 50 - k Min Typ Max Unit [1] See Section 8 for application guidelines for the Ternary control pins. Table 13. Ternary control input SEL characteristics[1] Symbol Parameter VIH HIGH-level input voltage Trigger level of the Schmitt Trigger buffer when input is going from LOW to HIGH 0.70  VDD VDD VDD + 0.3 V VIL LOW-level input voltage Trigger level of the Schmitt Trigger buffer when input is going from HIGH to LOW 0.3 0 0.30  VDD V Rpu(ext) external pull-up resistor connected between VDD1V8 and setting pin; for detection of HIGH condition 0 - 30 k Rpd(ext) external pull-down resistor connected between setting pin and GND; for detection of LOW condition 0 - 30 k for detection of OPEN condition and will be interpreted as LOW condition 250 - - k setting pin is driven LOW by external GPIO 45 - - A Zext(OPEN) external impedance IIL LOW-level input current PTN36043 Product data sheet Conditions All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 14 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch Table 13. Ternary control input SEL characteristics[1] …continued Symbol Parameter IIH Min Typ Max Unit HIGH-level input current setting pin is driven HIGH (to 1.8 V) by external GPIO - - +45 A CL(ext) external load capacitance on setting pin; for reliable detection of OPEN condition - - 150 pF Rpu(int) internal pull-up resistance for detection of Ternary setting - 50 - k Rpd(int) internal pull-down resistance for detection of Ternary setting - 50 - k [1] Conditions See Section 8 for application guidelines for the Ternary control pins. PTN36043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 15 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 12. Package outline '+;4)1SODVWLFGXDOLQOLQHFRPSDWLEOHWKHUPDOHQKDQFHGVXSHUWKLQTXDGIODWSDFNDJHQROHDGV WHUPLQDOVERG\[[PP ' % 627 $ WHUPLQDO LQGH[DUHD $ $ $ ( GHWDLO; H / H / & ‘Y ‘Z E   & $ % & \ & \ N   H (K H H  WHUPLQDO LQGH[DUHD    / ; N 'K  PP VFDOH 'LPHQVLRQVPPDUHWKHRULJLQDOGLPHQVLRQV 8QLW PP $ $ $ E / / ' 'K ( (K        PD[   QRP                 PLQ   H H H N     Y Z \ \     VRWBSR 2XWOLQH YHUVLRQ 5HIHUHQFHV ,(& -('(& -(,7$ ,VVXHGDWH   627 Fig 7. (XURSHDQ SURMHFWLRQ Package outline SOT1442-1 (DHX2QFN18) PTN36043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 16 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 13. Packing information 13.1 SOT1442-1 (DHXQFN18); Reel dry pack, SMD, 13" Q1/T1 standard product orientation; Orderable part number ending ,518 or Y; Ordering code (12NC) ending 518 13.1.1 Packing method %DUFRGHODEHO 'U\DJHQW %DJ (6'SULQW 5HODWLYHKXPLGLW\ LQGLFDWRU 0RLVWXUHFDXWLRQ SULQW (6'HPERVVHG 7DSH 5HHODVVHPEO\ %DUFRGHODEHO *XDUGEDQG 3ULQWHGSODQRER[ &LUFXODUVSURFNHWKROHVRSSRVLWHWKH ODEHOVLGHRIUHHO &RYHUWDSH 4$VHDO &DUULHUWDSH 6SDFHIRUDGGLWLRQDO ODEHO 3UHSULQWHG(6' ZDUQLQJ %DUFRGHODEHO 'U\SDFN,'VWLFNHU 3ULQWHGSODQRER[ DDD Fig 8. PTN36043 Product data sheet Reel dry pack for SMD All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 17 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch Table 14. Dimensions and quantities Reel dimensions d  w (mm) [1] SPQ/PQ (pcs) [2] Reels per box Outer box dimensions l  w  h (mm) 330  8 10 000 1 342  338  39 [1] d = reel diameter; w = tape width. [2] Packing quantity dependent on specific product type. View ordering and availability details at NXP order portal, or contact your local NXP representative. 13.1.1.1 Product orientation 47 47 SLQ 47 47 DDD DDD Tape pocket quadrants Fig 9. 13.1.1.2 Pin 1 is in quadrant Q1/T1 Product orientation in carrier tape Carrier tape dimensions 4 mm W K0 A0 B0 P1 T direction of feed 001aao148 Fig 10. Carrier tape dimensions Table 15. Carrier tape dimensions In accordance with IEC 60286-3. PTN36043 Product data sheet A0 (mm) B0 (mm) K0 (mm) T (mm) P1 (mm) W (mm) 2.25  0.1 2.65  0.1 0.53  0.05 0.25  0.03 4.0  0.1 8.0 + 0.3 /  0.1 All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 18 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 13.1.1.3 Reel dimensions A Z W2 B ØC ØD detail Z 001aao149 Fig 11. Schematic view of reel Table 16. Reel dimensions In accordance with IEC 60286-3. PTN36043 Product data sheet A [nom] (mm) W2 [max] (mm) B [min] (mm) C [min] (mm) D [min] (mm) 330 14.4 1.5 12.8 20.2 All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 19 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 13.1.1.4 Barcode label Fixed text Country of origin i.e. "Made in....." or "Diffused in EU [+] Assembled in...... Packing unit (PQ) identification 2nd traceability lot number* 2nd (youngest) date code* 2nd Quantity* Traceability lot number Date code With linear barcode Quantity With linear barcode Type number NXP 12NC With linear barcode NXP SEMICONDUCTORS MADE IN >COUNTRY< [PRODUCT INFO] (33T) PUID: B.0987654321 (30T) LOT2 (31D) REDATE (30D) DATE2 (32T) ORIG (30Q) QTY2 (31T) PMC (31P) MSL/PBT (1T) LOT MSL/PBT (9D) DATE (Q) QTY HALOGEN FREE (30P) TYPE RoHS compliant (1P) CODENO Optional product information* Re-approval date code* Origin code Product Manufacturing Code MSL at the Peak Body solder temperature with tin/lead* MSL at the higher lead-free Peak Body Temperature* 2D matrix with all data (including the data identifiers) Additional info if halogen free product Additional info on RoHS Lead-free symbol 001aak714 Fig 12. Example of typical box and reel information barcode label Table 17. PTN36043 Product data sheet Barcode label dimensions Box barcode label l  w (mm) Reel barcode label l  w (mm) 100  75 100  75 All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 20 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PTN36043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 21 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 13) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 18 and 19 Table 18. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 19. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2 000 > 2 000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 13. PTN36043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 22 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 13. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PTN36043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 23 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 15. Soldering (1) SYMM 18 14 18X (0.3) 13 1 18X (0.2) (0.45) (2.1) SYMM (1.4) 14X (0.4) 10 4 ( 0.2) typ via 5 9 (1.7) land pattern example scale: 25x; all dimensions are in mm 0.05 min all around 0.05 max all around metal solder mask opening solder mask opening metal under solder mask non solder mask defined (preferred) solder mask defined aaa-021290 Fig 14. PCB footprint for SOT1442-1 (DHX2QFN18); reflow soldering PTN36043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 24 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch (0.95) SYMM 18 14 18X (0.3) 13 1 18X (0.2) (2.1) SYMM (1.3) 14X (0.4) 10 4 metal typ 5 9 (1.7) solder paste example, based on 0.1 mm thick stencil exposed pad, 88 % printed solder coverage by area scale: 30x; all dimensions are in mm aaa-021333 Fig 15. Solder paste example PTN36043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 25 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 16. Abbreviations Table 20. Abbreviations Acronym Description A/V Audio/Video device AIO All In One computer platform CDM Charged-Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model I2C-bus Inter-Integrated Circuit bus I/O Input/Output IC Integrated Circuit ISI InterSymbol Interference LFPS Low Frequency Periodic Signaling PCB Printed-Circuit Board RX Receive (or Receiver) SI Signal Integrity TX Transmit (or Transmitter) USB Universal Serial Bus 17. Revision history Table 21. Revision history Document ID Release date Data sheet status Change notice Supersedes PTN36043 v.2 20180219 Product data sheet - PTN36043 v.1.3 Modifications: PTN36043 v.1.3 Modifications: PTN36043 v.1.2 Modifications: PTN36043 v.1.1 Modifications: PTN36043 v.1 PTN36043 Product data sheet • Table 3 “Pin description” and Table 6 “SEL input setting”: Updated description for pin SEL from “in high impedance state for USB Type-C Safe State support” to “connected to VDD thru low ohmic resistor (50 )” 20171117 • 20160822 • - PTN36043 v.1.2 Product data sheet - PTN36043 v.1.1 Full DS release to web; replaces short data sheet PTN36043_SDS 20160802 • Product data sheet Table 3 “Pin description” and Table 6 “SEL input setting”: Updated description for pin SEL from “connected to VDD thru low ohmic resistor (50 )” to “in high impedance state for USB Type-C Safe State support” Product data sheet - PTN36043 v.1 Table 2 “Ordering options”: Removed 500 piece minimum order quantity 20160415 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 - © NXP Semiconductors N.V. 2018. All rights reserved. 26 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PTN36043 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 27 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PTN36043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 19 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 28 of 29 PTN36043 NXP Semiconductors USB Type-C SuperSpeed active switch 20. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 6 Receive equalization, transmitter de-emphasis and output swing level controls . . . . . . . . . . . . 6 7.2 Device states and power management . . . . . . 7 7.3 SEL input pin . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 Application guideline for Control of CHx_SETx and SEL input pins . . . . . . . . . . . . . . . . . . . . . . 8 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9 10 Recommended operating conditions. . . . . . . . 9 11 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10 11.1 Device characteristics. . . . . . . . . . . . . . . . . . . 10 11.2 Receiver AC/DC characteristics . . . . . . . . . . . 12 11.3 Transmitter AC/DC characteristics . . . . . . . . . 13 11.4 Ternary control inputs . . . . . . . . . . . . . . . . . . . 14 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 13 Packing information . . . . . . . . . . . . . . . . . . . . 17 13.1 SOT1442-1 (DHXQFN18); Reel dry pack, SMD, 13" Q1/T1 standard product orientation; Orderable part number ending ,518 or Y; Ordering code (12NC) ending 518 . . . . . . . . . . . . . . . . 17 13.1.1 Packing method . . . . . . . . . . . . . . . . . . . . . . . 17 13.1.1.1 Product orientation . . . . . . . . . . . . . . . . . . . . . 18 13.1.1.2 Carrier tape dimensions . . . . . . . . . . . . . . . . . 18 13.1.1.3 Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . 19 13.1.1.4 Barcode label . . . . . . . . . . . . . . . . . . . . . . . . . 20 14 Soldering of SMD packages . . . . . . . . . . . . . . 21 14.1 Introduction to soldering . . . . . . . . . . . . . . . . . 21 14.2 Wave and reflow soldering . . . . . . . . . . . . . . . 21 14.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21 14.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22 15 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 26 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 26 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 27 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27 18.2 18.3 18.4 19 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 28 28 29 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2018. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 February 2018 Document identifier: PTN36043