PTN36221AHXZ

PTN36221A Single-channel SuperSpeed USB 3.0 redriver Rev. 2.1 — 25 August 2015 Product data sheet 1. General description The PTN36221A is a small, low power, high performance SuperSpeed USB 3.0 redriver that enhances signal quality by performing receive equalization on the deteriorated input signal followed by transmit de-emphasis maximizing system link performance. With its superior differential signal conditioning and enhancement capability, the device delivers significant flexibility and performance scaling for various systems with different PCB trace and cable channel conditions and still benefit from optimum power consumption. PTN36221A is a single-channel device that supports data signaling rate of 5 Gbit/s. The PTN36221A has built-in advanced power management capability that enables significant power saving under various different USB 3.0 Low-power modes (U2/U3). The device performs these actions without host software intervention and conserves power. The PTN36221A is powered by a 1.8 V supply. It is available in X2QFN12 1.6 mm  1.6 mm  0.35 mm package with 0.4 mm pitch. 2. Features and benefits            Supports single-channel USB 3.0 redriver at 5 Gbit/s Compliant to SuperSpeed USB 3.0 standard Supports Low Frequency Periodic Signaling (LFPS) and is USB3.0 compatible Adjustable receive equalization, transmit de-emphasis and output swing functions  Selectable receive equalization to recover from InterSymbol Interference (ISI) and high-frequency losses  Selectable transmit de-emphasis and output swing delivers pre-compensation suited to channel conditions  Selectable output swing adjustment Integrated termination resistors provide impedance matching on both transmit and receive paths Automatic receiver termination detection Low power management scheme (When VDD = 1.8 V, Vos = 1000 mV)  97 mW active power  5 mW in U2/U3 state  1 mW with no connection  18 W in Deep power saving state Support hot plug with automatic receiver detect Power supply: 1.8 V  5 % ESD 8 kV HBM, 1 kV CDM for data path Operating temperature range: 40 C to +85 C PTN36221A NXP Semiconductors Single-channel SuperSpeed USB 3.0 redriver  Package offered: X2QFN12 package 1.6 mm  1.6 mm  0.35 mm, 0.4 mm pitch 3. Applications        Smart phones, tablets Active cables Notebook/netbook/nettop platforms Docking stations Desktop and AIO platforms Server and storage platforms USB 3.0 peripherals such as consumer/storage devices, printers, or USB 3.0 capable hubs/repeaters 4. System context diagrams The system context diagrams in Figure 1 illustrate PTN36221A usage. Rx TXP PTN36221A RXN TXN TXP RXP PTN36221A TXN RXN RXP TXP NOTEBOOK/ DESKTOP USB sync cable plug CONNECTOR Tx USB cable/ dongle CONNECTOR RXP APPLICATION PROCESSOR/ USB HOST CONTROLLER CONNECTOR MOBILE DEVICE USB PERIPHERAL/ AV DISPLAY WITH HUB APPLICATION PROCESSOR/ USB HOST CONTROLLER Tx Rx PTN36221A RXN TXN TXP RXP PTN36221A TXN RXN CONNECTOR MOBILE HOST 002aah762 Fig 1. PTN36221A context diagrams PTN36221A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 25 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 2 of 24 PTN36221A NXP Semiconductors Single-channel SuperSpeed USB 3.0 redriver 5. Ordering information Table 1. Ordering information Type number Topside mark Package Name Description Version PTN36221AHX 1A*[1] X2QFN12 plastic, super thin quad flat package; no leads; 12 terminals; body 1.6  1.6  0.35 mm[2] SOT1355-1 [1] Where * = week of the month. [2] Maximum package height = 0.4 mm. 5.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method Minimum order quantity Temperature PTN36221AHX PTN36221AHXHP X2QFN12 Reel 13” Q2/T3 *Standard mark SMD 10000 Tamb = 40 C to +85 C PTN36221AHXZ X2QFN12 Reel 7” Q2/T3 *Standard mark 5000 Tamb = 40 C to +85 C 6. Block diagram VSS VDD VDD PTN36221A VDD line driver equalizer RXP RXN TXP TXN EMPHASIS FILTER SIGNAL DETECTION DEVICE CONTROL AND MANAGEMENT RX TERMINATION DETECTION 002aah759 EN Fig 2. PTN36221A Product data sheet EQ OS DE Block diagram of PTN36221A All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 25 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 3 of 24 PTN36221A NXP Semiconductors Single-channel SuperSpeed USB 3.0 redriver 7. Pinning information 8 DE VSS OS NCT2 5 6 EQ 8 DE 10 9 EN 12 TXN NCT1 6 OS Transparent top view 11 5 1 NCT2 VDD 4 EQ RXP 7 3 7 PTN36221AHX 2 RXN RXP 2 PTN36221AHX VSS 4 RXN 3 EN NCT1 10 9 TXP 1 TXP VDD 11 12 TXN 7.1 Pinning Bottom view 002aah760 Refer to Section 12 for package-related information. Fig 3. Pin configuration for X2QFN12 7.2 Pin description Table 3. Pin description Symbol Pin Type Description High-speed differential signals RXP 4 self-biasing differential input Differential signal from SuperSpeed USB 3.0 transmitter. RXP makes a differential pair with RXN. The input to this pin must be AC-coupled externally. RXN 3 self-biasing differential input Differential signal from SuperSpeed USB 3.0 transmitter. RXN makes a differential pair with RXP. The input to this pin must be AC-coupled externally. TXP 11 self-biasing differential output Differential signal to SuperSpeed USB 3.0 receiver. TXP makes a differential pair with TXN. The output of this pin must be AC-coupled externally. TXN 12 self-biasing differential output Differential signal to SuperSpeed USB 3.0 receiver. TXN makes a differential pair with TXP. The output of this pin must be AC-coupled externally. Control and configuration signals PTN36221A Product data sheet NCT1 10 CMOS input Test pin 1. Leave open or connect to ground for functional mode. NCT2 5 analog input Test pin 2. Leave open or connect to ground for functional mode. EN 9 CMOS input Chip enable input (active HIGH); internal 260 k pull-up resistor. All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 25 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 4 of 24 PTN36221A NXP Semiconductors Single-channel SuperSpeed USB 3.0 redriver Table 3. Pin description …continued Symbol Pin Type Description DE 8 Trinary input Programmable output de-emphasis level setting for the output channel. [DE] = LOW: 0 dB open: 3.5 dB (default) HIGH: 6 dB EQ 7 Trinary input Equalizer control for the input channel. [EQ] = LOW: 3 dB open: 6 dB (default) HIGH: 9 dB OS 6 Trinary input Differential output swing control. [OS] = LOW: 900 mV open: 1000 mV (default) HIGH: 1100 mV Supply voltage VDD 1 Power 1.8 V supply. Ground connection VSS 2 Ground Ground supply (0 V). 8. Functional description Refer to Figure 2 “Block diagram of PTN36221A”. PTN36221A is a single-channel SuperSpeed USB 3.0 redriver meant to be used for signal integrity enhancement on various platforms — smart phone, tablet, active cable, notebooks, docking station, desktop, AIO, peripheral devices, etc. With its high fidelity differential signal conditioning capability and wide configurability, this chip is flexible enough for use under a variety of system environments. The following sections describe the individual block functions and capabilities of the device in more detail. 8.1 Receive equalization On the high-speed signal path, the device performs receive equalization providing frequency selective gain to configuration pin EQ setting. Table 4 lists the configuration options available in this device. Table 4. PTN36221A Product data sheet EQ configuration options EQ SuperSpeed USB 3.0 signal equalization gain at 2.5 GHz LOW (0 V) 3 dB Open 6 dB (default) HIGH (1.8 V) 9 dB All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 25 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 5 of 24 PTN36221A NXP Semiconductors Single-channel SuperSpeed USB 3.0 redriver 8.2 Transmit de-emphasis The PTN36221A device enhances High Frequency (HF) signal content further by performing de-emphasis on the high-speed signals. In addition, the device provides flat frequency gain by boosting output signal. Both flat and frequency selective gains prepare the system to cover up for losses further down the link. Table 5 lists de-emphasis configuration options of PTN36221A. Table 5. DE configuration options DE SuperSpeed USB 3.0 signal de-emphasis gain LOW (0 V) 0 dB Open 3.5 dB (default) HIGH (1.8 V0 6 dB Figure 4 illustrates de-emphasis as a function of time. 1 bit 1 to N bits 1 bit 1 to N bits VTX_DIFF_DEp-p VTX_CM_DC VTX_DIFFp-p 002aag010 Fig 4. Differential output with de-emphasis 8.3 Device states and power management PTN36221A has implemented an advanced power management scheme that operates in tune with USB 3.0 bus electrical condition. Though the device does not decode USB power management commands (related to USB 3.0 U1/U2/U3 transitions) exchanged between USB 3.0 host and peripheral/device, it relies on bus electrical conditions to decide to be in one of the following states: • Active state wherein device is fully operational, USB data is transported. In this state, USB connection exists, but there is no need for Receive Termination detection. • Power-saving states: – U2/U3 state – No connection state • Deep power-saving state: When EN is LOW, this chip is in shut-down state. The Receive Termination Detection circuitry is implemented as part of a transmitter and detect whether a load device with equivalent DC impedance ZRX_DC is present. PTN36221A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 25 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 6 of 24 PTN36221A NXP Semiconductors Single-channel SuperSpeed USB 3.0 redriver 9. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Min Max Unit supply voltage [1] 0.3 +2.5 V VI input voltage [1] 0.3 VDD + 0.5 V Tstg storage temperature 65 +150 C HBM for high-speed pins [2] - 8000 V HBM for control pins [2] - 4000 V CDM for high-speed pins [3] - 1000 V CDM for control pins [3] - 500 V VDD VESD Parameter Conditions electrostatic discharge voltage [1] All voltage values (except differential voltages) are with respect to network ground terminal. [2] Human Body Model: ANSI/ESDA/JEDEC JDS-001-2012 (Revision of ANSI/ESDA/JEDEC JS-001-2011), ESDA/JEDEC Joint standard for ESD sensitivity testing, Human Body Model - Component level; Electrostatic Discharge Association, Rome, NY, USA; JEDEC Solid State Technology Association, Arlington, VA, USA. [3] Charged Device Model; JESD22-C101E December 2009 (Revision of JESD220C101D, October 2008), standard for ESD sensitivity testing, Charged Device Model - Component level; JEDEC Solid State Technology Association, Arlington, VA, USA. 10. Recommended operating conditions Table 7. Operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD supply voltage 1.8 V supply option 1.71 1.8 1.89 V VI input voltage control and configuration pins (for example, EQ, DE, OS and EN) 0.3 VDD VDD + 0.3 V Tamb ambient temperature operating in free air 40 - +85 C PTN36221A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 25 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 7 of 24 PTN36221A NXP Semiconductors Single-channel SuperSpeed USB 3.0 redriver 11. Characteristics 11.1 Device characteristics Table 8. Device characteristics VDD = 1.8 V  5 %; Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit tstartup start-up time between supply voltage within operating range to specified operating characteristics (90 % of VDD) until first automatic receiver termination detection - - 6 ms ts(HL) HIGH to LOW settling time enable to disable; power-down time; EN HIGH  LOW change to deep power-saving state; device is supplied with valid supply voltage - - 1 ms ts(LH) LOW to HIGH settling time disable to enable; start-up time; EN LOW  HIGH change to specified operating characteristics; device is supplied with valid supply voltage - - 6 ms trcfg reconfiguration time any configuration pin change (from one setting to another setting) to specified operating characteristics; device is supplied with valid supply voltage - - 115 ms tPD(dif) differential propagation delay between 50 % level at input and output; see Figure 5 - - 0.5 ns tidle idle time default wait time to wait before getting into Power-saving state - 300 400 ms time for exiting from Power-saving state and get into Active state; see Figure 7 - 0.1 115[1] s td(pwrsave-act) delay time from power-save to active td(act-idle) delay time from active reaction time for squelch detection circuit and to idle transmitter output buffer; see Figure 6 - 9 14 ns td(idle-act) delay time from idle to active reaction time for squelch detection circuit and transmitter output buffer; see Figure 6 - 9 14 ns IDD supply current Active state; Tx de-emphasis = 3.5 dB; Rx equalization gain = 6 dB; Tx output signal swing (peak-to-peak) = 1000 mV - 57 - mA U2/U3 Power-saving state - 2.8 mA no USB connection state - 0.4 mA Deep power-saving state; EN = LOW - 10 A JEDEC still air test environment - 138.5 - C/W Rth(j-a) [1] thermal resistance from junction to ambient When special U2/U3 Power-saving mode is ON. PTN36221A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 25 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 8 of 24 PTN36221A NXP Semiconductors Single-channel SuperSpeed USB 3.0 redriver IN+ in VHSSQ VDC_CM IN− tPD(dif) tPD(dif) td(idle-act) td(act-idle) OUT+ out VDC_CM OUT− 002aag025 Fig 5. Propagation delay Fig 6. aaa-011397 Electrical idle transitions in U0/U1 modes Ux exit LFPS signaling input VHSSQ td(pwrsave-act) output aaa-011398 Fig 7. Power-save exit time 11.2 Receiver AC/DC characteristics Table 9. Receiver AC/DC characteristics VDD = 1.8 V  5 %; Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter ZRX_DC receiver DC common-mode impedance Conditions Min Typ Max Unit 18 - 30  ZRX_DIFF_DC DC differential impedance RX pair 72 - 120  ZIH HIGH-level input impedance DC input; common-mode 25 - - k VRX_DIFFp-p differential input peak-to-peak voltage receiver VRX_DC_CM RX DC common mode voltage VRX_CM_AC_P RX AC common-mode voltage Vth(i) VHSSQ 100 - 1200 mV - 1.8 - V peak - - 150 mV input threshold voltage differential peak-to-peak value 100 - - mV high-speed squelch detection threshold voltage (differential signal amplitude) differential peak-to-peak value - 100 - mV PTN36221A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 25 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 9 of 24 PTN36221A NXP Semiconductors Single-channel SuperSpeed USB 3.0 redriver 11.3 Transmitter AC/DC characteristics Table 10. Transmitter AC/DC characteristics VDD = 1.8 V  5 %; Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions ZTX_DC transmitter DC common-mode impedance ZTX_DIFF_DC DC differential impedance TX pair VTX_DIFFp-p differential peak-to-peak output voltage RL = 100  OS = open Min Typ Max Unit 18 - 30  72 - 120  900 1000 1100 mV OS = HIGH 1000 1100 1200 mV OS = LOW 800 900 1000 mV - 1.3 VDD V VTX_DC_CM transmitter DC common-mode voltage VTX_CM_ACpp_ACTIV TX AC common-mode peak-to-peak output voltage (active state) device input fed with differential signal - - 100 mV VTX_IDL_DIFF_ACpp electrical idle differential peak-to-peak output voltage when link is in electrical idle - - 10 mV VTX_RCV_DETECT voltage change allowed during receiver detection positive voltage swing to sense the receiver termination detection - - 600 mV tr(tx) transmit rise time measured using 20 % and 80 % levels; see Figure 8 40 55 75 ps tf(tx) transmit fall time measured using 80 % and 20 % levels; see Figure 8 40 55 75 ps t(r-f)tx difference between transmit rise and fall time measured using 20 % and 80 % levels - - 15 ps 80 % 20 % tr(tx) tf(tx) 002aag027 Fig 8. PTN36221A Product data sheet Output rise and fall times All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 25 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 10 of 24 PTN36221A NXP Semiconductors Single-channel SuperSpeed USB 3.0 redriver 11.4 Jitter performance Table 11 provides jitter performance of PTN36221A under a specific set of conditions that is illustrated by Figure 9. Table 11. Jitter performance characteristics Unit Interval (UI) = 200 ps. Symbol Parameter Conditions tjit(o)(p-p) peak-to-peak output jitter time total jitter at test point C tjit(dtrm)(p-p) peak-to-peak deterministic jitter time tjit(rndm)(p-p) peak-to-peak random jitter time Min Typ Max Unit [1] - 0.19 - UI [1] - 0.11 - UI [1][2] - 0.08 - UI [1] Measured at test point C with K28.5 pattern, VID = 1000 mV (peak-to-peak), 5 Gbit/s; 3.5 dB de-emphasis from source. [2] Random jitter calculated as 14.069 times the RMS random jitter for 1012 bit error rate. less than 76.2 cm (30-inch) FR4 trace AWG SIGNAL SOURCE test point A test point C test point B PTN36221A SMA connector SMA connector 002aah761 Source jitter measurements: total peak-to-peak jitter = 21 ps peak-to-peak deterministic jitter = 8 ps random jitter = 0.95 ps (RMS value) Fig 9. Jitter measurement setup 11.5 Control inputs Table 12. Control input characteristics for EN pin VDD = 1.8 V  5 %; Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter VIH Min Typ Max Unit HIGH-level input voltage 0.65  VDD - - V VIL LOW-level input voltage - - 0.35  VDD V ILI input leakage current - 7 20 A Rpu(int) internal pull-up resistance - 230 - k PTN36221A Product data sheet Conditions measured with input at VIH(max) and VIL(min) All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 25 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 11 of 24 PTN36221A NXP Semiconductors Single-channel SuperSpeed USB 3.0 redriver Table 13. Trinary control input characteristics for DE, EQ, and OS pins VDD = 1.8 V  5 %; Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-level input voltage 0.75  VDD VDD VDD + 0.3 V VIL LOW-level input voltage 0.3 0 0.25  VDD V IIH HIGH-level input current - - 45 A IIL LOW-level input current 45 - - A Zext(open) external impedance for detection of open condition 250 - - k IL leakage current of external GPIO; for detection of open condition 6 - +6 A CL load capacitance for reliable detection of open condition - - 35 pF ILI input leakage current EN = LOW; measured with input at VIH(max) and VIL(min) - - 1 A Rpu(int) internal pull-up resistance for detection of trinary setting - 50 - k Rpd(int) internal pull-down resistance for detection of trinary setting - 50 - k PTN36221A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 25 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 12 of 24 PTN36221A NXP Semiconductors Single-channel SuperSpeed USB 3.0 redriver 12. Package outline X2QFN12: plastic, super thin quad flat package; no leads; 12 terminals; body 1.6 x 1.6 x 0.35 mm D B SOT1355-1 A terminal 1 index area A A1 E c detail X e1 1/2 e e C b 3 C A B C v w 6 y1 C y L 1/2 e 2 7 1 8 e2 terminal 1 index area 12 e X 9 L1 0 2 mm scale Dimensions (mm are the original dimensions) Unit mm A A1 b c D E e max 0.40 0.05 0.25 1.65 1.65 nom 0.35 0.20 0.127 1.60 1.60 min 0.30 0.00 0.15 1.55 1.55 e1 0.4 1.2 e2 L L1 0.4 0.4 0.3 0.2 0.6 0.5 0.4 v w y y1 0.07 0.05 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT1355-1 --- MO-255 --- sot1355-1_po European projection Issue date 13-12-23 14-01-13 Fig 10. Package outline SOT1355-1 (X2QFN12) PTN36221A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 25 August 2015 © NXP Semiconductors N.V. 2015. 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