PTN5100DBSMP

PTN5100D USB Type-C power delivery PHY and protocol IC Rev. 1 — 2 August 2016 Product data sheet 1. General description PTN5100D is a single port USB Type-C Power Delivery (PD) PHY and Protocol IC that provides Type-C Configuration channel interface and USB PD Physical and Protocol layer functions to a System PD Port Policy Controller (Policy Engine and Device Policy Manager, Alternate mode controller). It complies with USB PD[1] and Type-C[2] specifications. PTN5100D is architected to deliver robust performance, compliant behavior, configurability and system implementation flexibility that are essential to tide over interoperability and compliance hurdles in the platform applications. PTN5100D can support system realization of the following PD roles: (i) Consumer only (ii) Consumer/Provider. Further, it is register programmed to operate in Type-C specific Upstream Facing Port (UFP). It can work along with the PD policy controller to operate in other modes (DFP, DRP). PTN5100D operates from platform power supply VDD, or it can also be powered from USB power VBUS directly. The host interface operates on VIO supply to facilitate interfacing to systems that use IO supply rail different from VDD supply rail. It provides SPI/I2C interface for system host control/status update. The interface choice is pre-configured in NXP factory. PTN5100D is available in a small footprint package option: HVQFN20 4 mm x 4 mm, 0.5 mm pitch. 2. Features and benefits 2.1 USB PD and Type-C Features Complies with USB PD[1] and USB Type-C[2] specifications.  Supports implementation of various system PD roles: Consumer, Consumer/Provider  Supports Type-C role configurability  Type-C role (UFP, DFP)  Implements UFP role pull down behavior to handle dead battery condition on battery powered platforms  Implements 'Rd' indication on CC pin  Cooperatively works under the control of Policy controller MCU for power delivery negotiation and contract(s), Alternate mode and VDM exchanges  Implements BMC (de)coding, 4B5B symbol (de)coding, CRC generation/checking, PD packet assembling/disassembling including Preamble, SOP, EOP, Good CRC response, Retries, Hard and Cable resets  PD PHY and Protocol layer interface control and status update handled via SPI/I2C interface PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC  DRP and DFP roles can be supported 2.2 System protection features  Back current protection on all pins when PTN5100D is unpowered  CC1 and CC2 pins are 5.5 V tolerant  VBUS pin and VBUS power path MOSFET enable pins are 28 V tolerant 2.3 General  Delivers (active LOW enable) gate control signals for PMOS Power MOSFETs on VBUS source and sink power paths  Provides dedicated IO pin (CC_ORIENT) for indicating Cable/plug orientation  Delivers up to 30 mA (max) for powering Policy controller MCU  Supports SPI slave interface (SPI modes 1 and 2 supported) up to 30 MHz  Supports I2C slave interface standard mode (100 kHz), Fast mode (400 kHz) and Fast mode plus (1 MHz)  I2C Device slave address programmable up to 3 values  Supports 3.3 V or 1.8 V capable I2C-bus or SPI interface  Supports register access - device configuration, control and status/interrupt interfacing through Slave I2C-bus interface  Power supplies - VDD (3.3 V 10 %) or VBUS  Tolerant up to 28 V on VBUS and operational up to maximum of 25 V on VBUS  Operating temperature 20 C to 85 C  ESD 8 kV HBM, 1 kV CDM  Package: HVQFN20 4 mm  4 mm, 0.5 mm pitch. 3. Applications  PC accessories/peripherals: Docking, Mobile Monitors, Multi-Function Monitors, Portable/External hard drives, Dongles and accessories, etc. 4. Ordering information Table 1. Ordering information Type number Topside marking Package Name Description Version PTN5100DBS 51D0 HVQFN20 plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 4  4  0.85 mm[2] SOT917-4 PTN5100DABS 51DA HVQFN20 plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 4  4  0.85 mm[3] SOT917-4 [1] Total height after printed-circuit board mounting 2 V 0.05 VDDIO - - V VDDIO < 2 V 0.1VDDIO - - V 0 - 0.4 V 0 - 0.2 VDDIO V VOL Conditions LOW-level output voltage VDDIO > 2 V at 3mA sink current VDDIO < 2 V PTN5100D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 2 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 19 of 37 PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC Table 11. I2C characteristics …continued Applicable across operating temperature and power supply ranges as per Section 10 (unless otherwise noted). Typical values are specified at 27 C (unless otherwise noted).[1] Symbol Parameter Conditions IOL LOW-level output current VOL = 0.4 V; Min Typ Max Unit 3 - - mA 20 - - mA 6 - - mA 10 - 10 A - - 10 pF Standard and Fast modes VOL = 0.4 V; Fast mode plus VOL = 0.6 V; Fast mode IIL LOW-level input current CI Capacitance of IO pin tHD;STA Hold time (repeated) START condition Fast mode plus; After this period, the first clock pulse is generated 0.26 - - s tLOW LOW period of I2C clock Fast mode plus 0.5 - - s tHIGH HIGH period of I2C clock Fast mode plus 0.26 - - s tSU;STA Setup time (repeated) START condition Fast mode plus 0.26 - - s tHD;DAT Data Hold time Fast mode plus 0 - - s tSU;DAT Data Setup time Fast mode plus 50 - - ns tr Rise time of I2C_SCL and I2C_SDA signals Fast mode plus - - 120 ns tf Fall time of I2C_SCL and Fast mode plus I2C_SDA signals - - 120 ns tSU;STO Setup time for STOP condition Fast mode plus 0.26 - - s tBUF Bus free time between STOP and START condition Fast mode plus 0.5 - - s tVD;DAT Data valid time Fast mode plus 0.45 - - s tVD;ACK Data valid acknowledge time Fast mode plus 0.45 - - s tSP Pulse width of spikes that must be suppressed by input filter - - 50 ns [1] Pin voltage - 0.1VDDIO to 0.9VIO, max VDDIO is I2C-bus pull up voltage. PTN5100D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 2 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 20 of 37 PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC tf SDA tr tSU;DAT 70 % 30 % 70 % 30 % cont. tHD;DAT tf tVD;DAT tHIGH tr 70 % 30 % SCL 70 % 30 % 70 % 30 % tHD;STA 70 % 30 % cont. tLOW 9th clock 1 / fI2C S 1st clock cycle tBUF tf SDA tSU;STA tHD;STA tVD;ACK tSP tSU;STO 70 % 30 % SCL Sr P 9th clock Fig 8. S aaa-020541 I2C timing diagram PTN5100D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 2 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 21 of 37 PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC 11.5 SPI characteristics Table 12. SPI interface: AC/DC characteristics Applicable across operating temperature and power supply ranges as per Section 10 (unless otherwise noted). Typical values are specified at 27 C (unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit fSPI SPI clock frequency (SPI_CLK) Applies to both TX and RX - - 20 MHz tSPI;HI SPI clock HIGH time 20 - - ns tSPI;LO SPI clock LOW time 20 - - ns tSPI;rise SPI clock (LOW to HIGH) rise time 0.1 - - V/ns tSPI;fall SPI clock (HIGH to LOW) fall time 0.1 - - V/ns tSPI;CSNS SPI_CS Not Setup time Relative to SPI clock pin 0 - - ns tSPI;CSNH SPI_CS Not Hold time Relative to SPI clock pin 0 - - ns tSPI;DINS Data In Setup time Applies to SPI_MOSI_I2C_SDA; 5 relative to SPI clock - - ns tSPI;DINH Data In Hold time Applies to SPI_MOSI_I2C_SDA; 5 relative to SPI clock - - ns tSPI;DONS SPI clock edge to Valid Data Out Applies to SPI_MISO - - 7 ns tSPI;DONH SPI clock edge to Data Out Hold time Applies to SPI_MISO 0 - CL;SPI Maximum IO capacitance supported SPI_CLK_I2C_SCL, SPI_MOSI_I2C_SDA - - 10 pF CIN;SPI Maximum IO capacitance SPI_MISO, SPI_CS - - 10 pF VIH;SPI HIGH-level input voltage SPI_MISO 0.7 V_MCUP WR - - V VIL;SPI LOW-level input voltage SPI_MISO - - 0.3 V_MCU PWR V VOL;SPI LOW-level output voltage SPI_CLK_I2C_SCL, SPI_CS, SPI_MOSI_I2C_SDA - - 0.5 V V_MCUP WR  0.5 - - V ns IOL = 4 mA VOH;SPI HIGH-level output voltage SPI_CLK_I2C_SCL, SPI_CS, SPI_MOSI_I2C_SDA ILIH;EN HIGH-level input leakage current VI = 3.3 V 1 - 1 A ILIL;EN LOW-level input leakage current VI = GND 1 - 1 A IOH = 4 mA PTN5100D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 2 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 22 of 37 PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC SPI_CS tSPI;FALL tSPI;CSNH tSPI;CSNS SPI_CLK tSPI;DINH tSPI;DINS MOSI tSPI;RISE MSB LSB HIGH-Z HIGH-Z MISO Fig 9. aaa-020542 SPI write timing SPI_CS tSPI;HI tSPI;LO SPI_CLK tSPI;DONH MISO MSB LSB tSPI;DONS MOSI aaa-020543 Fig 10. SPI read timing 11.6 CONTROL IO characteristics Table 13. Control I/O characteristics Applicable across operating temperature and power supply ranges as per Section 10 (unless otherwise noted). Typical values are specified at 27 C (unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit System side CMOS output pins (CC_ORIENT) VOH HIGH-level Output voltage IOH = 2 mA VIO 0.4 - VOL LOW-level Output voltage IOL = 4 mA - - 0.5 V CI Capacitance of IO pin - - 20 pF ILIH,EN HIGH-level input leakage current VI = 3.3 V 1 - 1 A ILIL,EN LOW-level input leakage current VI = GND 1 - 1 A applies to CC_CTRL1, TST0 - - 0.4 V applies to SLV_ADDR - - 0.3  VDD V V System side input pins (CC_CTRL1, SLV_ADDR, TST0) VIL LOW-level input voltage PTN5100D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 2 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 23 of 37 PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC Table 13. Control I/O characteristics Applicable across operating temperature and power supply ranges as per Section 10 (unless otherwise noted). Typical values are specified at 27 C (unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-level input voltage applies to SLV_ADDR 0.7  VDD - - V CI Capacitance of IO pin applies to CC_CTRL1 only - - 20 pF applies to SLV_ADDR - - 20 pF ILIH,EN HIGH-level input leakage current VI = 3.3 V 1 - 1 A ILIL,EN LOW-level input leakage current VI = GND 1 - 1 A - - 0.5 V - - 20 pF System side open drain interface pins (INT_N); pulled up to VDDIO VOL LOW-level Output voltage CI Capacitance of IO pin IOL = 4 mA FET enable pins (EN_USBSRC, EN_USBFET1, EN_USBFET2) VOL,EN LOW-level output voltage IOL = 4 mA; - - 0.5 V VIH,EN HIGH-level input voltage FET enable pins are in Hi-Z 0.7x V_MCUPW R 25 V ILIH,EN HIGH-level input leakage current VI = 25 V 1 - 1 A ILIL,EN LOW-level input leakage current VI = GND 1 - 1 A [1] VFET_Bias is the bias voltage on the FET enable pins PTN5100D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 2 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 24 of 37 PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC 12. Package outline HVQFN20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 4 x 4 x 0.85 mm A B D SOT917-4 terminal 1 index area A E A1 c detail X e1 e 6 10 C C A B C v w b y y1 C L 11 5 e Eh e2 1 15 terminal 1 index area 20 X 16 Dh 0 5 mm scale Dimensions Unit mm A A1 b max 1.00 0.05 0.30 nom 0.85 0.25 min 0.80 0.20 c D(1) Dh E(1) Eh e e1 e2 L v 0.2 4.1 4.0 3.9 3.0 2.9 2.8 4.1 4.0 3.9 3.0 2.9 2.8 0.5 2 2 0.35 0.30 0.25 0.1 w y 0.05 0.08 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT917-4 References IEC JEDEC JEITA MO-220 --- sot917-4_po European projection Issue date 14-10-27 14-11-07 Fig 11. Package outline SOT917-4 (HVQFN20) PTN5100D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 2 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 25 of 37 PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC 13. Packing information 13.1 SOT917-4: HVQFN20; Reel dry pack, SMD, 13"; Q2/T3 turned product orientation; Orderable part number ending ,528 or MP; Ordering code (12NC) ending 528 13.1.1 Packing method %DUFRGHODEHO 'U\DJHQW %DJ (6'SULQW 5HODWLYHKXPLGLW\ LQGLFDWRU 0RLVWXUHFDXWLRQ SULQW (6'HPERVVHG 7DSH 5HHODVVHPEO\ %DUFRGHODEHO *XDUGEDQG 3ULQWHGSODQRER[ &LUFXODUVSURFNHWKROHVRSSRVLWHWKH ODEHOVLGHRIUHHO &RYHUWDSH 4$VHDO &DUULHUWDSH 6SDFHIRUDGGLWLRQDO ODEHO 3UHSULQWHG(6' ZDUQLQJ %DUFRGHODEHO 'U\SDFN,'VWLFNHU 3ULQWHGSODQRER[ DDD Fig 12. Reel dry pack for SMD PTN5100D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 2 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 26 of 37 PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC Table 14. Dimensions and quantities Reel dimensions d  w (mm) [1] SPQ/PQ (pcs)[2] Reels per box Outer box dimensions l  w  h (mm) 330  12 6000 1 342  338  27 [1] d = reel diameter; w = tape width. [2] Packing quantity dependent on specific product type. View ordering and availability details at NXP order portal, or contact your local NXP representative. 13.1.2 Product orientation 47 47 EDOO 47 47 DDD DDD Tape pocket quadrants Ball 1 is in quadrant Q2/T3 Fig 13. Product orientation in carrier tape 13.1.3 Carrier tape dimensions PP : . $ % 3 7 GLUHFWLRQRIIHHG DDR Fig 14. Carrier tape dimensions Table 15. Carrier tape dimensions In accordance with IEC 60286-3. PTN5100D Product data sheet A0 (mm) B0 (mm) K0 (mm) T (mm) P1 (mm) W (mm) 4.30  0.10 4.30  0.10 1.10  0.10 0.30  0.05 8.0  0.10 12  0.30 All information provided in this document is subject to legal disclaimers. Rev. 1 — 2 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 27 of 37 PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC 13.1.4 Reel dimensions $ = : % ‘& ‘' GHWDLO= DDR Fig 15. Schematic view of reel Table 16. Reel dimensions In accordance with IEC 60286-3. PTN5100D Product data sheet A [nom] (mm) W2 [max] (mm) B [min] (mm) C [min] (mm) D [min] (mm) 330 18.4 1.5 12.8 20.2 All information provided in this document is subject to legal disclaimers. Rev. 1 — 2 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 28 of 37 PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC 13.1.5 Barcode label )L[HGWH[W &RXQWU\RIRULJLQ LH0DGHLQRU 'LIIXVHGLQ(8>@ $VVHPEOHGLQ 3DFNLQJXQLW34LGHQWLILFDWLRQ QGWUDFHDELOLW\ORWQXPEHU QG\RXQJHVWGDWHFRGH QG4XDQWLW\ 7UDFHDELOLW\ORWQXPEHU 'DWHFRGH :LWKOLQHDUEDUFRGH 4XDQWLW\ :LWKOLQHDUEDUFRGH 7\SHQXPEHU 1;31& :LWKOLQHDUEDUFRGH 1;36(0,&21'8&7256 0$'(,1!&28175352'8&7,1)2@ 447< 2SWLRQDOSURGXFWLQIRUPDWLRQ 5HDSSURYDOGDWHFRGH 2ULJLQFRGH 3URGXFW0DQXIDFWXULQJ&RGH 06/DWWKH3HDN%RG\VROGHU WHPSHUDWXUHZLWKWLQOHDG  06/DWWKHKLJKHUOHDGIUHH 3HDN%RG\7HPSHUDWXUH 'PDWUL[ZLWKDOOGDWD LQFOXGLQJWKHGDWDLGHQWLILHUV +$/2*(1)5(( 37 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 17. temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 17. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PTN5100D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 2 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 31 of 37 PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC 15. Soldering: PCB footprints )RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI+94)1SDFNDJH 627 +[ *[ 3 '   & Q63[ 63[ +\ 63\WRW 63\ *\ Q63\ 6/\ %\ $\ 63[WRW ; 6/[  %[  $[ 5HFRPPHQGHGVWHQFLOWKLFNQHVVPP   VROGHUODQG VROGHUODQGSOXVVROGHUSDVWH VROGHUSDVWHGHSRVLW VROGHUUHVLVW RFFXSLHGDUHD 'LPHQVLRQVLQPP GHWDLO; 'LPHQVLRQVPPDUHWKHRULJLQDOGLPHQVLRQV 3 $[ $\ %[ %\ & ' 6/[ 6/\ 63[WRW 63\WRW 63[ 63\ *[ *\ +[ +\ Q63[ Q63\                 ,VVXHGDWH      VRWBIU Fig 18. PCB footprint for SOT917-4 (HVQFN20); reflow soldering PTN5100D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 2 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 32 of 37 PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC 16. Abbreviations Table 20. Abbreviations Acronym Description AP Application Processor ASIC Application Specific Integrated Circuit CDM Charged Device Model, an ESD standard CPU Central Processing Unit DBP Dead Battery Provisioning DFP Downstream Facing Port DRP Dual Role Port EC Embedded Controller FS USB Full Speed signaling HBM Human Body Model, an ESD standard HS USB High Speed signaling LDO Low Drop-Out regulator LS USB Low Speed signaling MM Machine Model, an ESD standard OC Over-Current condition OCD Over-Current Detection PCH Platform Controller Hub PD Power Delivery specification PMIC Power Management IC POR Power ON Reset SS USB3.0 Super Speed Signaling UFP Upstream Facing Port USB Universal Serial Bus 17. References PTN5100D Product data sheet [1] USB Power Delivery Specification Revision 2.0 Version 1.09 April 2015 [2] USB Type-C Cable and Connector Specification Revision 1.1, April 2015 [3] AN11661 NXP USB Type-C PD Controller Application Programming Guide [4] UM10204, “I2C-bus specification and user manual”; NXP Semiconductors, Revision 03 June 19, 2007 All information provided in this document is subject to legal disclaimers. Rev. 1 — 2 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 33 of 37 PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC 18. Revision history Table 21. Revision history Document ID Release date Data sheet status Change notice Supersedes PTN5100D v.1 20160802 Product data sheet - - PTN5100D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 2 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 34 of 37 PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PTN5100D Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 1 — 2 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 35 of 37 PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PTN5100D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 2 August 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 36 of 37 PTN5100D NXP Semiconductors USB Type-C power delivery PHY and protocol IC 21. Contents 1 2 2.1 2.2 2.3 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.4.1 7.4.1.1 7.4.1.2 7.4.1.3 7.4.2 7.4.3 7.4.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 USB PD and Type-C Features . . . . . . . . . . . . . 1 System protection features . . . . . . . . . . . . . . . . 2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 Type-C Configuration Channel functional block 7 USB Power Delivery Function . . . . . . . . . . . . . 7 Power FET control . . . . . . . . . . . . . . . . . . . . . . 9 MCU interface and control . . . . . . . . . . . . . . . 10 I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 10 I2C writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C address auto-incrementing . . . . . . . . . . . 11 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Register interface . . . . . . . . . . . . . . . . . . . . . . 11 Relevant Interface pins - SLV_ADDR, SPI_CLK_I2C_SCL, SPI_MOSI_I2C_SDA, SPI_CS, SPI_MISO, INT_N . . . . . . . . . . . . . . 11 7.5 Power supplies . . . . . . . . . . . . . . . . . . . . . . . 11 8 PTN5100D - Use case view . . . . . . . . . . . . . . 12 8.1 System use case illustration . . . . . . . . . . . . . . 13 8.1.1 Type-C cable adapter with PTN5100D . . . . . 13 8.1.1.1 Application description . . . . . . . . . . . . . . . . . . 13 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14 10 Recommended operating conditions. . . . . . . 15 11 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 16 11.1 Device characteristics. . . . . . . . . . . . . . . . . . . 16 11.2 USB PD and Type-C characteristics. . . . . . . . 17 11.3 Power AC/DC characteristics . . . . . . . . . . . . 19 11.4 I2C characteristics . . . . . . . . . . . . . . . . . . . . . 19 11.5 SPI characteristics . . . . . . . . . . . . . . . . . . . . . 22 11.6 CONTROL IO characteristics . . . . . . . . . . . . . 23 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 25 13 Packing information . . . . . . . . . . . . . . . . . . . . 26 13.1 13.1.1 13.1.2 13.1.3 13.1.4 13.1.5 14 14.1 14.2 14.3 14.4 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 SOT917-4: HVQFN20; Reel dry pack, SMD, 13"; Q2/T3 turned product orientation; Orderable part number ending ,528 or MP; Ordering code (12NC) ending 528 . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Packing method . . . . . . . . . . . . . . . . . . . . . . . 26 Product orientation . . . . . . . . . . . . . . . . . . . . . 27 Carrier tape dimensions . . . . . . . . . . . . . . . . . 27 Reel dimensions . . . . . . . . . . . . . . . . . . . . . . 28 Barcode label . . . . . . . . . . . . . . . . . . . . . . . . . 29 Soldering of SMD packages . . . . . . . . . . . . . . 30 Introduction to soldering. . . . . . . . . . . . . . . . . 30 Wave and reflow soldering. . . . . . . . . . . . . . . 30 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 30 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 31 Soldering: PCB footprints . . . . . . . . . . . . . . . 33 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 34 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Revision history . . . . . . . . . . . . . . . . . . . . . . . 35 Legal information . . . . . . . . . . . . . . . . . . . . . . 36 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 36 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Contact information . . . . . . . . . . . . . . . . . . . . 37 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2016. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 August 2016 Document identifier: PTN5100D