INTEGRATED CIRCUITS
DATA SHEET
XA-S3
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D,
low voltage (2.7 V–5.5 V), I2C, 2 UARTs,
16 MB address range
Product specification
Supersedes data of 2000 Dec 01
2013 Sep 04
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
• Three standard counter/timers with enhanced features. All timers
GENERAL DESCRIPTION
The XA-S3 device is a member of NXP Semiconductors’ XA
(eXtended Architecture) family of high performance 16-bit
single-chip microcontrollers.
have a toggle output capability.
• Watchdog timer.
• 5-channel 16-bit Programmable Counter Array (PCA).
• I2C-bus serial I/O port with byte-oriented master and slave
The XA-S3 device combines many powerful peripherals on one
chip. With its high performance A/D converter, timers/counters,
watchdog, Programmable Counter Array (PCA), I2C interface, dual
UARTs, and multiple general purpose I/O ports, it is suited for
general multipurpose high performance embedded control functions.
functions.
• Two enhanced UARTs with independent baud rates.
• Seven software interrupts.
• Active low reset output pin indicates all reset occurrences
Specific features of the XA-S3
• 2.7 V to 5.5 V operation.
• 32 K bytes of on-chip EPROM/ROM program memory.
• 1024 bytes of on-chip data RAM.
• Supports off-chip addressing up to 16 megabytes (24 address
(external reset, watchdog reset and the RESET instruction). A
reset source register allows program determination of the cause
of the most recent reset.
• 50 I/O pins, each with four programmable output configurations.
• 30 MHz operating frequency at 2.7 V to 5.5 V VDD.
• Power saving operating modes: Idle and Power-down. Wake-up
lines). A clock output reference is added to simplify external bus
interfacing.
• High performance 8-channel 8-bit A/D converter with automatic
from power-down via an external interrupt is supported.
channel scan and repeated read functions. Completes a
conversion in 4.46 microseconds at 30 MHz. Alternate operating
mode allows 10-bit conversion results.
• 68-pin PLCC and 80-pin PQFP packages.
ORDERING INFORMATION
ROMless
ROM
EPROM
TEMPERATURE RANGE (°C)
AND PACKAGE
FREQ.
(MHz)
DRAWING
NUMBER
PXAS30KBA
PXAS33KBA
PXAS37KBA
OTP
0 to +70, Commercial
68-pin Plastic Leaded Chip Carrier
30
SOT188-21
PXAS30KBBE
PXAS33KBBE
PXAS37KBBE
OTP
0 to +70, Commercial
80-pin Plastic Low Profile Quad Flat Pack
30
SOT315-1
PXAS30KFA
PXAS33KFA
PXAS37KFA
OTP
–40°C to +85°C, Industrial 68-pin Plastic
Leaded Chip Carrier
30
SOT188-21
PXAS30KFBE
PXAS33KFBE
PXAS37KFBE
OTP
–40°C to +85°C, Industrial 80-pin Plastic Low
Profile Quad Flat Pack
30
SOT315-1
NOTE:
1. Corrected SOT number; no physical change.
2013 Sep 04
2
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
PIN CONFIGURATIONS
P2.2/A14D10
2
P2.3/A15D11
V DD
3
P2.4/A16D12
P4.0/ECI
4
P2.5/A17D13
P4.1/CEX0
5
P2.6/A18D14
P4.2/CEX1
6
P2.7/A19D15
P4.3/CEX2
7
XTAL2
P4.4/CEX3
8
V SS
P4.5/CEX4
9
XTAL1
P4.6/A20
68-pin PLCC package
1
68
67
66
65
64
63
62
61
P4.7/A21 10
60 P2.1/A13D9
11
59 P2.0/A12D8
P3.1/TxD0 12
58 P0.7/A11D7
P3.2/INT0 13
57 P0.6/A10D6
P3.3/INT1 14
56 P0.5/A9D5
P3.0/RxD0
P3.4/T0 15
55 VSS
P3.5/T1/BUSW 16
54 VDD
P3.6/WRL 17
53 P0.4/A8D4
PLASTIC LEADED CHIP CARRIER
P3.7/RD 18
52 P0.3/A7D3
RSTOUT 19
51 P0.2/A6D2
VSS 20
50 RST
VDD 21
49 CLKOUT
EA/WAIT/VPP 22
48
P5.0/AD0 23
47 ALE/PROG
P5.1/AD1 24
46
P5.2/AD2 25
45 P0.0/A4D0
P0.1/A5D1
44 P6.1/A23
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
P5.4/AD4
P5.5/AD5
P5.6/AD6/SCL
P5.7/AD7/SDA
AVREF–
AVREF+
AVDD
AVSS
P1.0/A0/WRH
P1.1/A1
P1.2/A2
P1.3/A3
P1.4/RxD1
P1.5/TxD1
P1.6/T2
P1.7/T2EX
P6.0/A22
P5.3/AD3 26
2013 Sep 04
PSEN
3
SU00936
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
NC
P4.6/A20
P4.5/CEX4
P4.4/CEX3
P4.3/CEX2
P4.2/CEX1
P4.1/CEX0
P4.0/ECI
V DD
V DD
V SS
V SS
XTAL1
XTAL2
P2.7/A19D15
P2.6/A18D14
P2.5/A17D13
P2.4/A16D12
P2.3/A15D11
P2.2/A14D10
80-pin LQFP package
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
NC
1
60 NC
P4.7/A21
2
59 P2.1/A13D9
P3.0/RxD0
3
58 P2.0/A12D8
P3.1/TxD0
4
57 P0.7/A11D7
P3.2/INT0
5
56 P0.6/A10D6
P3.3/INT1
6
55 P0.5/A9D5
P3.4/T0
7
54 VSS
P3.5/T1/BUSW
8
53 VSS
P3.6/WRL
9
52 VDD
P3.7/RD 10
RSTOUT
51 VDD
LOW PROFILE PLASTIC QUAD FLAT PACK
11
50 P0.4/A8D4
VSS 12
49 P0.3/A7D3
VSS 13
48 P0.2/A6D2
VDD 14
47 RST
VDD 15
46 CLKOUT
EA/WAIT/VPP 16
2013 Sep 04
45 PSEN
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AVREF–
AVREF+
AV DD
AV DD
AVSS
AVSS
P1.0/A0/WRH
P1.1/A1
P1.2/A2
P1.3/A3
P1.4/RxD1
P1.5/TxD1
P1.6/T2
P1.7/T2EX
P6.0/A22
41 P6.1/A23
P5.7/AD7/SDA
42 P0.0/A4D0
P5.6/AD6/SCL
P5.2/AD2 19
P5.3/AD3 20
P5.5/AD5
43 P0.1/A5D1
P5.4/AD4
44 ALE/PROG
P5.1/AD1 18
NC
P5.0/AD0 17
4
SU00937
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
LOGIC SYMBOL
VDD
VSS
XTAL1
ECI
CEX0
PORT4
CEX1
XTAL2
CEX2
CEX3
CEX4
A20
AVDD
A21
AVREF+
AVREF–
PORT5
AVSS
CLKOUT
A/D
INPUTS
ALE
PSEN
SCL
RSTOUT
SDA
RST
A22
PORT6
EA/WAIT
A23
WRH/A0
A1
PORT0
PORT2
TxD1
T2
T2EX
RxD0
TxD0
INT0
INT1
T0
ADDRESS AND DATA BUS
PORT1
A3
RxD1
PORT3
A2
T1/BUSW
WRL
RD
SU00847A
2013 Sep 04
5
NXP Semiconductors
Product specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
BLOCK DIAGRAM
XA CPU Core
Program
Memory
Bus
SFR
bus
UART 0
32K Bytes
ROM/EPROM
1024 Bytes
Static RAM
Data
Bus
UART 1
I2C
Port 0
Timer 0, 1
Port 1
Port 2
Timer 2
Port 3
Watchdog
Timer
Port 4
PCA
Port 5
Input Port/
A/D
Port 6
SU00846
2013 Sep 04
6
XA-S3
NXP Semiconductors
Product specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
XA-S3
PIN DESCRIPTIONS
MNEMONIC
PIN NUMBER
TYPE
NAME AND FUNCTION
PLCC
LQFP
VSS
1, 20, 55
12, 13,
53, 54,
69, 70
I
Ground: 0 V reference.
VDD
2, 21, 54
14, 15,
51, 52,
71, 72
I
Power Supply: This is the power supply voltage for normal, idle, and power down
operation.
RST
50
47
I
Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to
take on their default states, and the processor to begin execution at the address contained
in the reset vector.
RSTOUT
19
11
O
Reset Output: This pin outputs a low whenever the XA-S3 processor is reset for any
reason. This includes an external reset via the RST pin, watchdog reset, and the RESET
instruction.
ALE/PROG
47
44
I/O
Address Latch Enable/Program Pulse: A high output on the ALE pin signals external
circuitry to latch the address portion of the multiplexed address/data bus. A pulse on ALE
occurs only when it is needed in order to process a bus cycle.
PSEN
48
45
O
Program Store Enable: The read strobe for external program memory. When the
microcontroller accesses external program memory, PSEN is driven low in order to enable
memory devices. PSEN is only active when external code accesses are performed.
EA/WAIT/VPP
22
16
I
External Access/Bus Wait: The EA input determines whether the internal program
memory of the microcontroller is used for code execution. The value on the EA pin is
latched as the external reset input is released and applies during later execution. When
latched as a 0, external program memory is used exclusively. When latched as a 1, internal
program memory will be used up to its limit, and external program memory used above that
point. After reset is released, this pin takes on the function of bus WAIT input. If WAIT is
asserted high during an external bus access, that cycle will be extended until WAIT is
released.
XTAL1
68
68
I
Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the
internal clock generator circuits.
XTAL2
67
67
I
Crystal 2: Output from the oscillator amplifier.
CLKOUT
49
46
O
Clock Output: This pin outputs a buffered version of the internal CPU clock. The clock
output may be used in conjunction with the external bus to synchronize WAIT state
generators, etc. The clock output may be disabled by software.
AVDD
33
28, 29
I
Analog Power Supply: Positive power supply input for the A/D converter.
AVSS
34
30, 31
I
Analog Ground.
AVREF+
32
27
I
A/D Positive Reference Voltage: High end reference for the A/D converter.
AVREF–
31
26
I
A/D Negative Reference Voltage: Low end reference for the A/D converter.
P0.0 – P0.7
45, 46,
51–53,
56–58
42, 43,
48–50,
55–57
I/O
Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. Port 0 latches have
1s written to them and are configured in the quasi-bidirectional mode during reset. The
operation of port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to the section on I/O port
configuration and the DC Electrical Characteristics for details.
When the external program/data bus is used, Port 0 becomes the multiplexed low
data/instruction byte and address lines 4 through 11.
2013 Sep 04
7
NXP Semiconductors
Product specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
MNEMONIC
P1.0 – P1.7
P2.0 – P2.7
PIN NUMBER
XA-S3
TYPE
NAME AND FUNCTION
32–39
I/O
Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type. Port 1 latches have
1s written to them and are configured in the quasi-bidirectional mode during reset. The
operation of port 1 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to the section on I/O port
configuration and the DC Electrical Characteristics for details.
35
32
O
36
37
38
39
40
41
42
33
34
35
36
37
38
39
O
O
O
I
O
I/O
O
59–66
58, 59,
61–66
I/O
PLCC
LQFP
35–42
Port 1 also provides various special functions as described below:
A0/WRH (P1.0)
Address bit 0 of the external address bus when the eternal data
bus is configured for an 8-bit width. When the external data bus
is configured for a 16-bit width, this pin becomes the high byte
write strobe.
A1 (P1.1):
Address bit 1 of the external address bus.
A2 (P1.2):
Address bit 2 of the external address bus.
A3 (P1.3):
Address bit 3 of the external address bus.
RxD1 (P1.4):
Serial port 1 receiver input.
TxD1 (P1.5):
Serial port 1 transmitter output.
T2 (P1.6):
Timer/counter 2 external count input or overflow output.
T2EX (P1.7):
Timer/counter 2 reload/capture/direction control.
Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. Port 2 latches have
1s written to them and are configured in the quasi-bidirectional mode during reset. The
operation of port 2 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to the section on I/O port
configuration and the DC Electrical Characteristics for details.
When the external program/data bus is used in 16-bit mode, Port 2 becomes the
multiplexed high data/instruction byte and address lines 12 through 19. When the external
data/address bus is used in 8-bit mode, the number of address lines that appear on Port 2
is user programmable in groups of 4 bits.
P3.0 – P3.7
P4.0 – P4.7
2013 Sep 04
11–18
3–10
I/O
11
12
13
14
15
16
3
4
5
6
7
8
I
O
I
I
I/O
I/O
17
18
9
10
O
O
3–10
73–79, 2
I/O
3
4
5
6
7
8
9
10
73
74
75
76
77
78
79
2
I
I/O
I/O
I/O
I/O
I/O
O
O
Port 3: Port 3 is an 8-bit I/O port with a user-configurable output type. Port 3 latches have
1s written to them and are configured in the quasi-bidirectional mode during reset. The
operation of port 3 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to the section on I/O port
configuration and the DC Electrical Characteristics for details.
Port 3 also provides the various special functions as described below:
RxD0 (P3.0):
Receiver input for serial port 0.
TxD0 (P3.1):
Transmitter output for serial port 0.
INT0 (P3.2):
External interrupt 0 input.
INT1 (P3.3):
External interrupt 1 input.
T0 (P3.4):
Timer/counter 0 external count input or overflow output.
T1 / BUSW (P3.5):
Timer/counter 1 external count input or overflow output. The
value on this pin is latched as an external chip reset is
completed and defines the default external data bus width.
WRL (P3.6):
External data memory low byte write strobe.
RD (P3.7):
External data memory read strobe.
Port 4: Port 4 is an 8-bit I/O port with a user-configurable output type. Port 4 latches have
1s written to them and are configured in the quasi-bidirectional mode during reset. The
operation of Port 4 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to the section on I/O port
configuration and the DC Electrical Characteristics for details.
Port 4 also provides various special functions as described below:
ECI (P4.0):
PCA External clock input.
CEX0 (P4.1):
Capture/compare external I/O for PCA module 0.
CEX1 (P4.2):
Capture/compare external I/O for PCA module 1.
CEX2 (P4.3):
Capture/compare external I/O for PCA module 2.
CEX3 (P4.4):
Capture/compare external I/O for PCA module 3.
CEX4 (P4.5):
Capture/compare external I/O for PCA module 4.
A20 (P4.6):
Address bit 20 of the external address bus.
A21 (P4.7):
Address bit 21 of the external address bus.
8
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
MNEMONIC
P5.0 – P5.7
PIN NUMBER
PLCC
LQFP
23–30
17–20,
22–25
TYPE
NAME AND FUNCTION
I/O
Port 5: Port 5 is an 8-bit I/O port with a user-configurable output type. Port 5 latches have
1s written to them and are configured in the quasi-bidirectional mode during reset. The
operation of Port 5 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to the section on I/O port
configuration and the DC Electrical Characteristics for details.
Port 5 also provides various special functions as described below. Port 5 pins used as A/D
inputs must be configured by the user to the high impedance mode.
P6.0 – P6.7
23
24
25
26
27
28
29
30
17
18
19
20
22
23
24
25
I
I
I
I
I
I
I/O
I/O
43, 44
40, 41
I/O
43
44
40
41
O
O
AD0 (P5.0):
AD1 (P5.1):
AD2 (P5.2):
AD3 (P5.3):
AD4 (P5.4):
AD5 (P5.5):
AD6/SCL (P5.6):
AD7/SDA (P5.7):
A/D channel 0 input.
A/D channel 1 input.
A/D channel 2 input.
A/D channel 3 input.
A/D channel 4 input.
A/D channel 5 input.
A/D channel 6 input. I2C serial clock input/output.
A/D channel 7 input. I2C serial data input/output.
Port 6: Port 6 is a 2-bit I/O port with a user-configurable output type. Port 6 latches have
1s written to them and are configured in the quasi-bidirectional mode during reset. The
operation of Port 6 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to the section on I/O port
configuration and the DC Electrical Characteristics for details.
Port 6 also provides special functions as described below:
A22 (P6.0):
Address bit 22 of the external address bus.
A23 (P6.1):
Address bit 23 of the external address bus.
Table 1. Special Function Registers
NAME
DESCRIPTION
SFR
Address
BIT FUNCTIONS AND ADDRESSES
MSB
LSB
Reset
Value
3F7
3F6
3F5
3F4
3F3
3F2
3F1
3F0
ADCON#* A/D control register
43E
–
–
–
–
ADRES
ADMOD
ADSST
ADINT
3FF
3FE
3FD
3FC
3FB
3FA
3F9
3F8
ADCS#*
A/D channel select register
43F
ADCS7
ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
ADCS0
ADCFG#
A/D timing configuration
4B9
–
–
–
–
ADRSH0#
ADRSH1#
ADRSH2#
ADRSH3#
ADRSH4#
ADRSH5#
ADRSH6#
ADRSH7#
ADRSL#
A/D high byte result, channel 0
A/D high byte result, channel 1
A/D high byte result, channel 2
A/D high byte result, channel 3
A/D high byte result, channel 4
A/D high byte result, channel 5
A/D high byte result, channel 6
A/D high byte result, channel 7
Two LSBs of 10-bit A/D result
4B0
4B1
4B2
4B3
4B4
4B5
4B6
4B7
4B8
BCR#
Bus configuration register
46A
BTRH
Bus timing register high byte
469
BTRL
Bus timing register low byte
468
CCON#*
PCA counter control
41A
CMOD#
PCA mode control
490
CH#
PCA counter high byte
48B
00h
CL#
PCA counter low byte
48A
00h
CCAPM0#
PCA module 0 mode
491
–
ECOM0
CAPP0
CAPN0
MAT0
TOG0
PWM0
ECCF0
00h
CCAPM1#
PCA module 1 mode
492
–
ECOM1
CAPP1
CAPN1
MAT1
TOG1
PWM1
ECCF1
00h
2013 Sep 04
A/D Timing Configuration
00h
00h
0Fh
xx
xx
xx
xx
xx
xx
xx
xx
xx
–
–
CLKD
WAITD
BUSD
BC2
BC1
BC0
DW1
DW0
DWA1
DWA0
DR1
DR0
DRA1
DRA0
FFh
WM1
WM0
ALEW
–
CR1
CR0
CRA1
CRA0
EFh
2D7
2D6
2D5
2D4
2D3
2D2
2D1
2D0
CF
CR
–
CCF4
CCF3
CCF2
CCF1
CCF0
00h
CIDL
WDTE
–
–
–
CPS1
CPS0
ECF
00h
9
Note 1
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
NAME
DESCRIPTION
SFR
Address
MSB
BIT FUNCTIONS AND ADDRESSES
LSB
Reset
Value
CCAPM2#
PCA module 2 mode
493
–
ECOM2
CAPP2
CAPN2
MAT2
TOG2
PWM2
ECCF2
00h
CCAPM3#
PCA module 3 mode
494
–
ECOM3
CAPP3
CAPN3
MAT3
TOG3
PWM3
ECCF3
00h
CCAPM4#
PCA module 4 mode
495
–
ECOM4
CAPP4
CAPN4
MAT4
TOG4
PWM4
ECCF4
00h
CCAP0H#
CCAP1H#
CCAP2H#
CCAP3H#
CCAP4H#
CCAP0L#
CCAP1L#
CCAP2L#
CCAP3L#
CCAP4L#
CS
DS
ES
PCA module 0 capture high byte
PCA module 1 capture high byte
PCA module 2 capture high byte
PCA module 3 capture high byte
PCA module 4 capture high byte
PCA module 0 capture low byte
PCA module 1 capture low byte
PCA module 2 capture low byte
PCA module 3 capture low byte
PCA module 4 capture low byte
Code segment
Data segment
Extra segment
497
499
49B
49D
49F
496
498
49A
49C
49E
443
441
442
I2CON#*
I2C control register
42C
I2STAT#
I2C status register
46C
I2DAT#
I2C
data register
46D
I2ADDR#
I2C address register
46E
IEH*
Interrupt enable high byte
427
IEL#*
Interrupt enable low byte
426
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
00h
00h
00h
367
366
365
364
363
362
361
360
CR2
ENA
STA
STO
SI
AA
CR1
CR0
00h
0
0
0
F8h
I2C Status Code/Vector
xx
I2C Slave Address
GC
33F
33E
33D
33C
33B
33A
339
338
–
–
–
–
ETI1
ERI1
ETI0
ERI0
337
336
335
334
333
332
331
330
EA
EAD
EPC
ET2
ET1
EX1
ET0
EX0
377
376
375
374
373
372
371
370
–
EI2
EC4
EC3
EC2
EC1
EC0
00h
00h
00h
IELB#*
Interrupt enable B low byte
42E
–
IPA0
Interrupt priority A0
4A0
–
PT0
–
PX0
00h
IPA1
Interrupt priority A1
4A1
–
PT1
–
PX1
00h
IPA2#
Interrupt priority A2
4A2
–
PPC
–
PT2
00h
IPA3#
Interrupt priority A3
4A3
–
–
–
PAD
00h
IPA4
Interrupt priority A4
4A4
–
PTI0
–
PRI0
00h
IPA5
Interrupt priority A5
4A5
–
PTI1
–
PRI1
00h
IPB0#
Interrupt priority B0
4A8
–
PC1
–
PC0
00h
IPB1#
Interrupt priority B1
4A9
–
PC3
–
PC2
00h
IPB2#
Interrupt priority B2
4AA
–
PI2
–
PC4
P0*
P1*
Port 0
Port 1
430
431
P2*
Port 2
432
P3*
Port 3
433
P4#*
2013 Sep 04
Port 4
434
00h
387
386
385
384
383
382
381
380
A11D7
A10D6
A9D5
A8D4
A7D3
A6D2
A5D1
A4D0
38F
38E
38D
38C
38B
38A
389
388
T2EX
T2
TxD1
RxD1
A3
A2
A1
A0/WRH
397
396
395
394
393
392
391
390
A19D15
A18D14
A17D13
A16D12
A15D11
A14D10
A13D9
A12D8
39F
39E
39D
39C
39B
39A
399
398
RD
WRL
T1
T0
INT1
INT0
TxD0
RxD0
3A7
3A6
3A5
3A4
3A3
3A2
3A1
3A0
A21
A20
CEX4
CEX3
CEX2
CEX1
CEX0
ECI
10
00h
FFh
FFh
FFh
FFh
FFh
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
NAME
P5#*
DESCRIPTION
Port 5
BIT FUNCTIONS AND ADDRESSES
SFR
Address
MSB
3AF
3AE
3AD
3AC
3AB
3AA
3A9
3A8
435
AD7/SDA
AD6/SCL
AD5
AD4
AD3
AD2
AD1
AD0
3B1
3B0
A23
A22
–
–
–
–
–
–
LSB
Reset
Value
FFh
P6#*
Port 6
436
FFh
P0CFGA
Port 0 configuration A
470
Note 5
P1CFGA
Port 1 configuration A
471
Note 5
P2CFGA
Port 2 configuration A
472
Note 5
P3CFGA
Port 3 configuration A
473
Note 5
P4CFGA# Port 4 configuration A
474
Note 5
P5CFGA# Port 5 configuration A
475
Note 5
P6CFGA# Port 6 configuration A
476
P0CFGB
Port 0 configuration B
4F0
Note 5
P1CFGB
Port 1 configuration B
4F1
Note 5
P2CFGB
Port 2 configuration B
4F2
Note 5
P3CFGB
Port 3 configuration B
4F3
Note 5
P4CFGB# Port 4 configuration B
4F4
Note 5
P5CFGB# Port 5 configuration B
4F5
Note 5
P6CFGB# Port 6 configuration B
4F6
PCON*
Power control register
404
PSWH*
Program status word (high byte)
401
PSWL*
–
–
–
–
Note 5
–
–
–
–
–
–
227
226
225
224
223
222
221
220
Note 5
–
–
–
–
–
–
PD
IDL
20F
20E
20D
20C
20B
20A
209
208
SM
TM
RS1
RS0
IM3
IM2
IM1
IM0
207
206
205
204
203
202
201
200
00h
Note 2
C
AC
–
–
–
V
N
Z
216
215
214
213
212
211
210
402
C
AC
F0
RS1
RS0
V
F1
P
Note 3
RSTSRC# Reset source register
463
–
–
–
–
–
R_WD
R_CMD
R_EXT
Note 7
RTH0
RTH1
RTL0
RTL1
455
457
454
456
S0CON*
80C51 compatible PSW
Timer 0 reload register, high byte
Timer 1 reload register, high byte
Timer 0 reload register, low byte
Timer 1 reload register, low byte
Serial port 0 control register
400
–
217
PSW51*
Program status word (low byte)
–
420
S0STAT#*
Serial port 0 extended status
421
S0BUF
S0ADDR
S0ADEN
Serial port 0 data buffer register
Serial port 0 address register
Serial port 0 address enable
460
461
462
S1CON*
Serial port 1 control register
424
S1STAT#*
S1BUF
S1ADDR
Serial port 1 extended status
Serial port 1 data buffer register
Serial port 1 address register
425
464
465
2013 Sep 04
Note 2
00h
00h
00h
00h
307
306
305
304
303
302
301
300
SM0_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
30F
30E
30D
30C
30B
30A
309
308
–
–
–
ERR0
FE0
BR0
OE0
STINT0
00h
00h
xx
00h
00h
327
326
325
324
323
322
321
320
SM0_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
32F
32E
32D
32C
32B
32A
329
328
–
–
–
ERR1
FE1
BR1
OE1
STINT1
11
00H
00h
xx
00h
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
NAME
DESCRIPTION
SFR
Address
S1ADEN
Serial port 1 address enable
466
SCR
System configuration register
440
BIT FUNCTIONS AND ADDRESSES
MSB
LSB
Reset
Value
00h
–
–
–
–
PT1
PT0
CM
PZ
21F
21E
21D
21C
21B
21A
219
218
00h
SSEL*
Segment selection register
403
ESWEN
R6SEG
R5SEG
R4SEG
R3SEG
R2SEG
R1SEG
R0SEG
00h
SWE
Software interrupt enable
47A
–
SWE7
SWE6
SWE5
SWE4
SWE3
SWE2
SWE1
00h
SWR*
Software interrupt request
42A
T2CON*
Timer 2 control register
418
357
356
355
354
353
352
351
350
–
SWR7
SWR6
SWR5
SWR4
SWR3
SWR2
SWR1
2C7
2C6
2C5
2C4
2C3
2C2
2C1
2C0
TF2
EXF2
RCLK0
TCLK0
EXEN2
TR2
C/T2
CP/RL2
2CF
2CE
2CD
2CC
2CB
2CA
2C9
2C8
–
–
RCLK1
TCLK1
–
–
T2OE
DCEN
T2MOD*
Timer 2 mode control
419
TH2
TL2
T2CAPH
T2CAPL
Timer 2 high byte
Timer 2 low byte
Timer 2 capture, high byte
Timer 2 capture, low byte
459
458
45B
45A
TCON*
Timer 0 and 1 control register
410
TH0
TH1
TL0
TL1
Timer 0 high byte
Timer 1 high byte
Timer 0 low byte
Timer 1 low byte
451
453
450
452
TMOD
Timer 0 and 1 mode control
45C
TSTAT*
Timer 0 and 1 extended status
411
2FF
WDCON*
Watchdog control register
41F
PEW2
WDL
WFEED1
WFEED2
Watchdog timer reload
Watchdog feed 1
Watchdog feed 2
45F
45D
45E
00h
00h
00h
00h
00h
00h
00h
287
286
285
284
283
282
281
280
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00h
00h
00h
00h
00h
GATE
C/T
M1
M0
GATE
C/T
M1
28F
28E
28D
28C
–
–
–
–
2FE
2FD
2FC
2FB
PRE1
PRE0
–
–
M0
28B
28A
289
288
–
T1OE
–
T0OE
2FA
2F9
2F8
WDRUN
WDTOF
–
00h
00h
Note 6
00h
xx
xx
NOTES:
* SFRs are bit addressable.
# SFRs are modified from or added to XA-G3 SFRs.
1. At reset, the BCR is loaded with the binary value 00000a11, where “a’ is the value on the BUSW pin. This defaults the address bus size to 24 bits.
2. SFR is loaded from the reset vector.
3. All bits except F1, F0, and P are loaded from the reset vector. Those bits are all 0.
4. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other
purposes in future XA derivatives. The reset value shown for these bits is 0.
5. Port configurations default to quasi-bidirectional when the XA begins execution from internal code memory after reset, based on the
condition found on the EA pin. Thus, all PnCFGA registers will contain FF, and PnCFGB register will contain 00 when the XA begins
execution using internal code memory. When the XA begins execution using external code memory, the default configuration for pins that
are associated with the external bus will be push-pull. The PnCFGA and PnCFGB register contents will reflect this difference.
6. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes.
7. The RSTSRC register reflects the cause of the last XA-S3 reset. One bit will be set to 1, the others will be cleared to 0.
8. The XA guards writes to certain bits (typically interrupt flags) that may be altered directly by a peripheral function. This prevents loss of an
interrupt or other status if a bit was written directly by a peripheral action during the time between the read and write portions of an
instruction that performs a read-modify-write operation. Examples of such instructions are:
and
s0con,#$fb
clr
tr0
setb
ti_0
XA-S3 SFR bits that are guarded in this manner are: ADINT (in ADCON); CF, CCF4, CCF3, CCF2, CCF1, and CCF0 (in CCON); SI (in
I2CON); TI_0 and RI_0 (in S0CON); TI_1 and RI_1 (in S1CON); FE0, BR0, and OE0 (in S0STAT); FE1, BR1, and OE1 (in S1STAT); TF2 (in
T2CON); TF1, TF0, IE1, and IE0 (in TCON); and WDTOF (in WDCON).
9. The XA-S3 implements an 8-bit SFR bus, as stated in Chapter 8 of the XA User Guide. All SFR accesses must be 8-bit operations. Attempts
to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data in the upper byte.
2013 Sep 04
12
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
FFFFFh
Up to 16 MB
Total Code
Memory
8000h
7FFFh
32 kB On-chip
Code Memory
0000h
SU01219
Figure 1. XA-S3 program memory map
Data Segment 0
Other Data Segments
FFFFh
FFFFh
Data Memory
(Indirectly Addressed,
Off-Chip)
Data Memory
(Indirectly Addressed,
Off-Chip)
0400h
03FFh
Data Memory
(Directly or Indirectly
Addressable, On-Chip
1 kB
On-Chip Data
Memory
(RAM)
0040h
003Fh
(Bit-Addressable
Data Area)
Data Memory
(Directly or Indirectly
Addressable, On-Chip
0020h
001Fh
0400h
03FFh
Directly
Addressed
Data
(1 k per
Segment)
Data Memory
(Directly or Indirectly
Addressable, On-Chip
0040h
003Fh
0020h
001Fh
(Bit-Addressable
Data Area)
Data Memory
(Directly or Indirectly
Addressable, Off-Chip
0000h
0000h
SU01220
Figure 2. XA-S3 data memory map
2013 Sep 04
13
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
FUNCTIONAL DESCRIPTION
of register ADRSL. These bits must be read before another
conversion is begun.
Analog to Digital converter
A/D conversions are begun by setting the A/D Start and STatus bit in
ADCON. In the single scan mode, all of the channels selected by
bits in the ADCS register will be converted once. The ADINT flag is
set when the last channel is converted. In the continuous scan
mode, the A/D converter continuously converts all A/D channels
selected by bits in the ADCS register. The ADINT flag is set when all
channels have been converted once.
Details of XA-S3 functions will be described in the following sections.
The XA-S3 has an 8-channel, 8-bit A/D converter with 8 sets of result
registers, single scan and multiple scan operating modes. The A/D
also has a 10-bit conversion mode that provides greater result
resolution. The A/D input range is limited to 0 to AVDD (3.3 V max.).
The A/D inputs are on Port 5. Analog Power and Ground as well as
AVREF+ and AVREF– must be supplied in order for the A/D converter to
be used. Prior to enabling the A/D converter or driving analog signals
into the A/D inputs, the port configurations for the pins being used as
A/D inputs must be set to the “off” (high impedance, input only) mode.
The A/D converter can generate an interrupt when the ADINT flag is
set. This will occur if the A/D interrupt is enabled (via the EAD bit in
IEL), the interrupt system is enabled (via the EA bit in IEL), and the
A/D interrupt priority (specified in IPA3 bits 3 to 0) is higher than the
currently running code (PSW bits IM3 through IM0) and any other
pending interrupt. ADINT must be cleared by software.
A/D timing can be adapted to the application clock frequency in
order to provide the fastest possible conversion.
A/D converter operation is controlled through the ADCON (A/D Control)
register, see Figure 1. Bits in ADCON start and stop the A/D, flag
conversion completion, and select the converter operating modes. When
10-bit resolution is needed, the A/D mode may be set to give 10 result
bits by setting the ADRES bit to 1. In this mode, the A/D takes longer to
complete a conversion, and the timing must be set differently in ADCFG.
A/D Timing Configuration
The A/D sampling and conversion timing may be optimized for the
particular oscillator frequency and input drive characteristics of the
application. Because A/D operation is mostly dependent on real-time
effects (charging time of sampling capacitors, settling time of the
comparator, etc.), A/D conversion times are not necessarily much
longer at slower clock frequencies. The A/D timing is controlled by
the ADCFG register, as shown in Figure 3, Table 2 and Table 3.
A/D Conversion Modes
The A/D converter supports a single scan mode and a continuous
scan mode. In either mode, one or more A/D channels may be
converted. The ADCS register determines which channels are
converted. If the corresponding bit in the ADCS register is set, that
channel is selected for conversions, otherwise that channel is
skipped. The ADCS register is detailed in Figure 2.
The primary effect of ADCFG settings is to adjust the A/D sample
and hold time to be relatively constant over various clock
frequencies. Two settings (value 6 and B) are provided to allow fast
conversions with a lower external source driving the A/D inputs.
These settings provide double the sample time at the same
frequency. Of course, settings intended for lower frequencies may
also be used at higher frequencies in order to increase the A/D
sampling time, but this method has the side effect of significantly
increasing A/D conversion times.
For any A/D conversion, the results are stored in ADRSHn,
corresponding to the A/D channel just converted. For a 10-bit
conversion, the two least significant bits are read from the upper end
ADCON
Address:43Eh
Bit Addressable
Reset Value: 00h
BIT
ADCON.7
ADCON.6
ADCON.5
ADCON.4
ADCON.3
ADCON.2
SYMBOL
—
—
—
—
ADRES
ADMOD
ADCON.1
ADSST
ADCON.0
ADINT
MSB
—
LSB
—
—
—
ADRES ADMOD ADSST
ADINT
FUNCTION
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Selects 8-bit (0) or 10-bit (1) conversion mode.
A/D mode select.
1 = continuous scan of selected inputs after a start of the A/D.
0 = single scan of selected inputs after a start of the A/D.
A/D start and status. Setting this bit by software starts the A/D conversion of the selected A/D
inputs. ADSST remains set as long as the A/D is in operation. In continuous conversion mode,
ADSST will remain set unless the A/D is stopped by software. While ADSST is set, new start
commands are ignored. An A/D conversion is progress may be aborted by software clearing
ADSST.
A/D conversion complete/interrupt flag. This flag is set when all selected A/D channels are
converted in either the single scan or continuous scan modes. Must be cleared by software.
SU01229
Figure 1. A/D Control Register (ADCON)
2013 Sep 04
14
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
ADCS
Address:43Fh
Bit Addressable
Reset Value: 00h
BIT
ADCS.7
ADCS.6
ADCS.5
ADCS.4
ADCS.3
ADCS.2
ADCS.1
ADCS.0
MSB
LSB
ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0
SYMBOL
ADCS7
ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
ADCS0
FUNCTION
A/D channel 7 select bit.
A/D channel 6 select bit.
A/D channel 5 select bit.
A/D channel 4 select bit.
A/D channel 3 select bit.
A/D channel 2 select bit.
A/D channel 1 select bit.
A/D channel 0 select bit.
SU00939
Figure 2. A/D Channel Select Register (ADCS)
ADCFG
Address:4B9h
Not bit Addressable
Reset Value: 00h
BIT
ADCFG.7
ADCFG.6
ADCFG.5
ADCFG.4
ADCFG.3–0
MSB
—
SYMBOL
—
—
—
—
ADCFG
LSB
—
—
—
A/D Timing Configuration
FUNCTION
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
A/D timing configuration (see text and table).
SU00940
Figure 3. A/D Timing Configuration Register (ADCFG)
Table 2. A/D Timing Configuration
Conversion Time
Max. Oscillator
Frequency (MHz)
Osc. Clocks
µsec at max. Osc.
Sampling
p g Time
(Osc. Clocks)
6.66
72
10.81
4
1h (0001)
10
76
7.6
6
2h (0010)
11.11
80
7.2
8
3h (0011)
13.33
96
7.2
8
4h (0100)
16.66
100
6.0
10
5h (0101)
20
104
5.2
12
6h (0110)1
20
116
5.8
24
7h (0111)
22.2
108
4.86
14
8h (1000)
23.3
124
5.32
14
9h (1001)
26.6
128
4.81
16
Ah (1010)
30
132
4.4
18
ADCFG 3 0
ADCFG.3–0
0h (0000)
Bh
(1011)1
30
146
4.87
32
Ch (1100)
–
136
4.25
20
Dh (1101)
–
152
4.56
20
Eh (1110)
–
172
4.7
22
Fh (1111)
–
176
4.4
24
NOTE:
1. These settings provide additional A/D input sampling time, in order to allow accurate readings with a higher external source impedance.
2013 Sep 04
15
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
Table 3. A/D Timing Configuration for 10-bit Mode
Conversion Time
Max. Oscillator
Frequency (MHz)
Osc. Clocks
µsec at max. Osc.
Sampling
p g Time
(Osc. Clocks)
0h (0000)
6.66
88
13.21
4
1h (0001)
8
92
9.2
6
ADCFG 3 0
ADCFG.3–0
2h (0010)
8
96
8.64
8
3h (0011)
12
116
8.7
8
4h (0100)
12
120
7.2
10
5h (0101)
12
124
6.2
12
6h (0110)
12
136
6.8
24
7h (0111)
12
128
5.77
14
8h (1000)
13
148
6.35
14
9h (1001)
13
152
5.71
16
Ah (1010)
13
156
5.2
18
Bh (1011)
13
170
5.67
32
Ch (1100)
13
160
5.0
20
Dh (1101)
16
180
5.41
20
Eh (1110)
20
204
5.57
22
Fh (1111)
20
208
5.2
24
A/D Inputs
In order to obtain accurate measurements with the A/D Converter,
the source drive must be sufficient to adequately charge the
sampling capacitor during the sampling time. Figure 4 shows the
equivalent resistance and capacitance related to the A/D inputs.
A/D timing configurations indicated in Table 1 allow for full A/D
ADN+1
ADN
accuracy (according to the A/D specifications) assuming a source
resistance of less than or equal to 20kΩ. Larger source resistances
may be accommodated by increasing the sampling time with a
different A/D timing configuration.
SmN+1
RmN+1
SmN
RmN
TO COMPARATOR
+
Multiplexer
RS
VANALOG
CS
CC
INPUT
Rm (multiplexer resistance)
CS (pin capacitance)
CC (sampling capacitor)
RS (source resistance)
=
=
=
=
3 kΩ maximum
10 pF maximum
2 pF maximum
Recommended less than 20kΩ for full specified accuracy. This allows time for the sampling
capacitor (CC) to fully charge while the multiplexer switch is closed. Please note that sampling
causes the analog input to present a varying load to the pin.
SU00948
Figure 4. A/D Input: Equivalent Circuit
2013 Sep 04
16
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
A/D Accuracy
The XA-S3 A/D in 10 -bit mode is specified with 16 samples
averaged in order to factor out on-chip noise. In an application
where averaging 16 samples is not practical, the accuracy
specifications may be de-rated according to the number of samples
that are actually taken. The graph in Figure 5 shows the relationship
of additional A/D error to the number of samples that are averaged.
For example, if a single A/D reading is used with no averaging, the
A/D accuracy should be de-rated by ±1.25 LSB.
1.50
Additional Error (LSB)
1.25
1.00
0.75
0.50
0.25
0.00
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Number of Samples
15
16
SU01227
Figure 5. A/D accuracy by number of averaging samples
(Pertains to 10-bit mode only. Note that 10-bit mode is only specified up to fC = 20 MHz.)
I2CON
Address:42Ch
Bit Addressable
Reset Value: 00h
BIT
I2CON.7
I2CON.6
I2CON.5
SYMBOL
CR2
ENA
STA
I2CON.4
I2CON.3
STO
SI
I2CON.2
AA
I2CON.1
I2CON.0
CR1
CR0
MSB
CR2
LSB
ENA
STA
STO
SI
AA
CR1
CR0
FUNCTION
I2C Rate Control, with CR1 and CR0. See text and table.
Enable I2C port. When ENA = 1, the I2C port is enabled.
Start flag. Setting STA to 1 causes the I2C interface to attempt to gain mastership of the bus by
generating a Start condition.
Stop flag. Setting STO to 1 causes the I2C interface to attempt to generate a Stop condition.
Serial Interrupt. SI is set by the I2C hardware when a new I2C state is entered, indicating that
software needs to respond. SI causes an I2C interrupt if enabled and of sufficient priority.
Assert Acknowledge. Setting AA to 1 causes the I2C hardware to automatically generate
acknowledge pulses for various conditions (see text).
I2C Rate Control, with CR2 and CR0. See text and table.
I2C Rate Control, with CR2 and CR1. See text and table.
SU00941
Figure 6.
2013 Sep 04
I2C
Control Register (I2CON)
17
NXP Semiconductors
Product specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
I2C Interface
If the STA and STO bits are both set, then a STOP condition is
transmitted to the I2C bus if the interface is in a master mode (in a
slave mode, the hardware generates an internal STOP condition
which is not transmitted). The I2C interface then transmits a START
condition.
The I2C interface on the XA-S3 is identical to the standard byte-style
I2C interface found on devices such as the 8xC552 except for the
rate selection. The I 2C interface conforms to the 100 kHz I2C
specification, but may be used at rates up to 400 kHz
(non-conforming).
STO = 0: When the STO bit is reset, no STOP condition will be
generated.
Important: Before the I2C interface may be used, the port pins
P5.6 and 5.7, which correspond to the I2C functions SCL and SDA
respectively, must be set to the open drain mode.
SI, the Serial Interrupt flag
SI = 1: When the SI flag is set, and the EA (interrupt system
enable) and EI2 (I2C interrupt enable) bits are also set, an I2C
interrupt is requested. SI is set by hardware when one of 25 of the
26 possible I2C interface states is entered. The only state that does
not cause SI to be set is state F8H, which indicates that no relevant
state information is available.
The processor interfaces to the I2C logic via the following four
special function registers: I2CON (I2C control register), I2STA (I2C
status register), I2DAT (I2C data register), and I2ADR (I2C slave
address register). The I2C control logic interfaces to the external I2C
bus via two port 5 pins: P5.6/SCL (serial clock line) and P5.7/SDA
(serial data line).
While SI is set, the low period of the serial clock on the SCL line is
stretched, and the serial transfer is suspended. A high level on the
SCL line is unaffected by the serial interrupt flag. SI must be reset
by software.
The Control Register, I2CON
This register is shown in Figure 6. Two bits are affected by the I2C
hardware: the SI bit is set when a serial interrupt is requested, and
the STO bit is cleared when a STOP condition is present on the I2C
bus. The STO bit is also cleared when ENA = “0”.
SI = 0: When the SI flag is reset, no serial interrupt is requested,
and there is no stretching of the serial clock on the SCL line.
ENA, the I2C Enable Bit
ENA = 0: When ENA is “0”, the SDA and SCL outputs are not
driven. SDA and SCL input signals are ignored, SIO1 is in the “not
addressed” slave state, and the STO bit in I2CON is forced to “0”.
No other bits are affected. P5.6 and P5.7 may be used as open
drain I/O ports.
AA, the Assert Acknowledge flag
AA = 1: If the AA flag is set, an acknowledge (low level to SDA) will
be returned during the acknowledge clock pulse on the SCL line when:
• The “own slave address” has been received.
• The general call address has been received while the general call
ENA = 1: When ENA is “1”, SIO1 is enabled. The P5.6 and P5.7
port latches must be set to logic 1.
bit (GC) in I2ADR is set.
• A data byte has been received while the I2C interface is in the
ENA should not be used to temporarily release the I2C-bus since,
when ENA is reset, the I2C-bus status is lost. The AA flag should be
used instead (see description of the AA flag in the following text).
master receiver mode.
• A data byte has been received while the I2C interface is in the
addressed slave receiver mode.
In the following text, it is assumed the ENA = “1”.
AA = 0: If the AA flag is reset, a not acknowledge (high level to
SDA) will be returned during the acknowledge clock pulse on the
SCL line when:
STA, the START flag
STA = 1: When the STA bit is set to enter a master mode, the I2C
hardware checks the status of the I2C bus and generates a START
condition if the bus is free. If the bus is not free, the I2C interface
waits for a STOP condition (which will free the bus) and generates a
START condition after a delay of a half clock period of the internal
serial clock generator.
• A data byte has been received while the I2C interface is in the
master receiver mode.
• A data byte has been received while the I2C interface is in the
addressed slave receiver mode.
If STA is set while the I2C interface is already in a master mode and
one or more bytes are transmitted or received, the hardware
transmits a repeated START condition. STA may be set at any time.
STA may also be set when the I2C interface is an addressed slave.
When the I2C interface is in the addressed slave transmitter mode,
state C8H will be entered after the last serial data byte is
transmitted. When SI is cleared, the I2C interface leaves state C8H,
enters the not addressed slave receiver mode, and the SDA line
remains at a high level. In state C8H, the AA flag can be set again
for future address recognition.
STA = 0: When the STA bit is reset, no START condition or
repeated START condition will be generated.
When the I2C interface is in the not addressed slave mode, its own
slave address and the general call address are ignored. Consequently,
no acknowledge is returned, and a serial interrupt is not requested.
Thus, the hardware can be temporarily released from the I2C bus
while the bus status is monitored. While the hardware is released from
the bus, START and STOP conditions are detected, and serial data is
shifted in. Address recognition can be resumed at any time by setting
the AA flag. If the AA flag is set when the part’s own slave address or
the general call address has been partly received, the address will be
recognized at the end of the byte transmission.
STO, the STOP flag
STO = 1: When the STO bit is set while the I2C interface is in a
master mode, a STOP condition is transmitted to the I2C bus. When
the STOP condition is detected on the bus, the hardware clears the
STO flag. In a slave mode, the STO flag may be set to recover from
an error condition. In this case, no STOP condition is transmitted to
the I2C bus. However, the hardware behaves as if a STOP condition
has been received and switches to the defined “not addressed” slave
receiver mode. The STO flag is automatically cleared by hardware.
2013 Sep 04
XA-S3
18
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
The I2C Status Register, I2STA
CR0, CR1, and CR2, the Clock Rate Bits
These three bits determine the serial clock frequency when the I2C
interface is in a master mode. An I2C rate of 100kHz or lower is
typical and can be derived from many oscillator frequencies. The
various serial rates are shown in Table 4. A variable bit rate may
also be used if Timer 1 is not required for any other purpose while
the I2C hardware is in a master mode. The frequencies shown in
Table 4 are unimportant when the I2C hardware is in a slave mode.
In the slave modes, the hardware will automatically synchronize with
the incoming clock frequency.
I2STA is an 8-bit read-only special function register. The three least
significant bits are always zero. The five most significant bits contain
the status code. There are 26 possible status codes. When I2STA
contains F8H, no relevant state information is available and no serial
interrupt is requested. All other I2STA values correspond to defined
hardware interface states. When each of these states is entered, a
serial interrupt is requested (SI = “1”).
NOTE: A detailed I2C interface description and usage
information, including example driver code, will be provided in
a separate document.
Table 4. I2C Rate Control
Frequency
q
y Select
(CR2, CR1, CR0)
Clock Divisor
Example I2C Rates at Specific Oscillator Frequencies
8 MHz
12 MHz
16 MHz
20 MHz
24 MHz
30 MHz
20
(400)1
–
–
–
–
–
1h (0001)
40
(200)1
(300)1
(400)1
–
–
–
2h (0010)
68
(116.65)1
(176.46)1
(235.29)1
(294.12)1
(352.94)1
–
(181.82)1
(227.27)1
(272.73)1
(340.91)1
0h (0000)
3h (0011)
88
90.91
(136.36)1
4h (0100)
160
50
75
100
(125)1
(150)1
(187.5)1
5h (0101)
272
29.41
44.12
58.82
73.53
88.24
(110.29)1
6h (0110)
352
22.73
34.09
45.45
56.82
68.18
85.23
7h (0111)
(Timer
1)2
(Timer
1)2
(Timer
1)2
(Timer
1)2
(Timer
1)2
(Timer
1)2
(Timer 1)2
NOTES:
1. The XA-S3 I2C interface does not conform to the 400kHz I2C specification (which applies to rates greater than 100kHz) in all details, but
may be used with care where higher rates are required by the application.
2. The timer 1 overflow is used to clock the I2C interface. The resulting bit rate is 1/2 of the timer overflow rate.
2013 Sep 04
19
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
XA-S3 Timer/Counters
The CCON SFR contains the run control bit for the PCA and the
flags for the PCA timer (CF) and each module (refer to Figure 11).
To run the PCA the CR bit (CCON.6) must be set by software. The
PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when
the PCA counter overflows and an interrupt will be generated if the
ECF bit in the CMOD register is set, The CF bit can only be cleared
by software. Bits 0 through 4 of the CCON register are the flags for
the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set
by hardware when either a match or a capture occurs. These flags
also can only be cleared by software. The PCA interrupt system
shown in Figure 9.
The XA-S3 has three general purpose counter/timers, two of which may
also be used as baud rate generators for either or both of the UARTs.
Timer 0 and 1
These are identical to the standard XA-G3 timer 0 and 1.
Timer 2
This is identical to the standard XA-G3 timer 2.
Programmable Counter Array (PCA)
The Programmable Counter Array available on the XA-S3 is a
special 16-bit Timer that has five 16-bit capture/compare modules
associated with it. Each of the modules can be programmed to
operate in one of four modes: rising and/or falling edge capture,
software timer, high-speed output, or pulse width modulator. Each
module has a pin associated with it in port 1. Module 0 is connected
to P4.1(CEX0), module 1 to P4.2(CEX1), etc. The basic PCA
configuration is shown in Figure 7.
Each module in the PCA has a special function register associated
with it. These registers are: CCAPM0 for module 0, CCAPM1 for
module 1, etc. (see Figure 12). The registers contain the bits that
control the mode that each module will operate in. The ECCF bit
(CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module)
enables the CCF flag in the CCON SFR to generate an interrupt
when a match or compare occurs in the associated module. PWM
(CCAPMn.1) enables the pulse width modulation mode. The TOG
bit (CCAPMn.2) when set causes the CEX output associated with
the module to toggle when there is a match between the PCA
counter and the module’s capture/compare register. The match bit
MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter
and the module’s capture/compare register.
The PCA timer is a common time base for all five modules and can
be programmed to run at: the TCLK rate (Osc/4, Osc/16, or Osc/64),
the Timer 0 overflow, or the input on the ECI pin (P4.0). When the
ECI input is used, the falling edge clocks the PCA counter. The timer
count source is determined from the CPS1 and CPS0 bits in the
CMOD SFR as follows (see Figure 10):
CPS1 CPS0 PCA Timer Count Source
0
X
TCLK (Osc/4, Osc/16, or Osc/64)
1
0
Timer 0 overflow
1
1
ECI (PCA External Clock Input (max rate = Osc/4)
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5)
determine the edge that a capture input will be active on. The CAPN
bit enables the negative edge, and the CAPP bit enables the
positive edge. If both bits are set both edges will be enabled and a
capture will occur for either transition. The last bit in the register
ECOM (CCAPMn.6) when set enables the comparator function.
Figure 13 shows the CCAPMn settings for the various PCA
functions.
In the CMOD SFR are three additional bits associated with the PCA.
They are CIDL which allows the PCA to stop during idle mode,
WDTE which enables or disables the watchdog function on
module 4, and ECF which when set causes an interrupt and the
PCA overflow flag CF (in the CCON SFR) to be set when the PCA
timer overflows. These functions are shown in Figure 8. In addition,
each PCA module may generate a separate interrupt.
There are two additional registers associated with each of the PCA
modules. They are CCAPnH and CCAPnL and these are the
registers that store the 16-bit count when a capture occurs or a
compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output.
The watchdog timer function is implemented in module 4 (see
Figure 17).
16 BITS
MODULE 0
P4.1/CEX0
MODULE 1
P4.2/CEX1
MODULE 2
P4.3/CEX2
MODULE 3
P4.4/CEX3
MODULE 4
P4.5/CEX4
16 BITS
PCA TIMER/COUNTER
TIME BASE FOR PCA MODULES
MODULE FUNCTIONS:
16-BIT CAPTURE
16-BIT TIMER
16-BIT HIGH SPEED OUTPUT
8-BIT PWM
WATCHDOG TIMER (MODULE 4 ONLY)
SU01303
Figure 7. Programmable Counter Array (PCA)
2013 Sep 04
20
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
TO PCA
MODULES
TCLK
(OSC/4, OSC/16,
OR OSC/64)
OVERFLOW
CH
INTERRUPT
CL
16–BIT UP COUNTER
TIMER 0
OVERFLOW
EXTERNAL INPUT
(P4.0/ECI)
01
10
11
DECODE
IDLE
CIDL
CF
WDTE
––
––
––
CPS1
CPS0
ECF
CMOD
(490H)
CR
––
CCF4
CCF3
CCF2
CCF1
CCF0
CCON
(41AH)
SU01304
Figure 8. PCA Timer/Counter
CF
CR
––
CCF4
CCF3
CCF2
CCF1
CCF0
CCON
(41AH)
PCA TIMER/COUNTER
MODULE 0
IEL.5
EPC
MODULE 1
IEL.7
EA
TO
INTERRUPT
PRIORITY
DECODER
MODULE 2
MODULE 3
MODULE 4
CMOD.0
ECF
CCAPMn.0
ECCFn
SU01305
Figure 9. PCA Interrupt System
2013 Sep 04
21
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
CMOD Address = 490H
Reset Value = 00H
CIDL
WDTE
–
–
–
CPS1
7
6
5
4
3
2
Bit:
CPS0
1
ECF
0
Symbol
Function
CIDL
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.
WDTE
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.
–
Not implemented, reserved for future use.*
CPS1
PCA Count Pulse Select bit 1.
CPS0
PCA Count Pulse Select bit 0.
CPS1
0
1
1
ECF
CPS0
X
0
1
PCA Timer Count Source
TClk (Osc/4, Osc/16, or Osc/64)
Timer 0 overflow
ECI (PCA External Clock Input (max rate = Osc/4)
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. In that case, the reset or inactive value of the new bit will be
0, and its active value will be 1. The value read from a reserved bit is indeterminate.
** fOSC = oscillator frequency
SU01306
Figure 10. CMOD: PCA Counter Mode Register
CCON Address = 41AH
Reset Value = 00H
Bit Addressable
Bit:
CF
CR
–
CCF4
CCF3
CCF2
CCF1
CCF0
7
6
5
4
3
2
1
0
Symbol
Function
CF
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
CR
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
–
Not implemented, reserved for future use*.
CCF4
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF3
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF2
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF1
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF0
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
Each of CCF4 through CCF0 generates its own interrupt, and has its own interrupt vector.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. In that case, the reset or inactive value of the new bit will be
0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01307
Figure 11. CCON: PCA Counter Control Register
2013 Sep 04
22
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
CCAPMn Address
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
491H
492H
493H
494H
495H
Reset Value = 00H
Not Bit Addressable
Bit:
–
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
7
6
5
4
3
2
1
0
Symbol
Function
–
ECOMn
CAPPn
CAPNn
MATn
Not implemented, reserved for future use*.
Enable Comparator. ECOMn = 1 enables the comparator function.
Capture Positive, CAPPn = 1 enables positive edge capture.
Capture Negative, CAPNn = 1 enables negative edge capture.
Match. When MATn = 1, a match of the PCA counter with this module’s compare/capture register causes the CCFn bit
in CCON to be set, flagging an interrupt.
Toggle. When TOGn = 1, a match of the PCA counter with this module’s compare/capture register causes the CEXn
pin to toggle.
Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output.
Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt.
TOGn
PWMn
ECCFn
NOTE:
*User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. In that case, the reset or inactive value of the new bit will be 0,
and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01308
Figure 12. CCAPMn: PCA Modules Compare/Capture Registers
–
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
X
0
0
0
0
0
0
0
No operation
MODULE FUNCTION
X
X
1
0
0
0
0
X
16-bit capture by a positive-edge trigger on CEXn
X
X
0
1
0
0
0
X
16-bit capture by a negative trigger on CEXn
X
X
1
1
0
0
0
X
16-bit capture by a transition on CEXn
X
1
0
0
1
0
0
X
16-bit Software Timer
X
1
0
0
1
1
0
X
16-bit High Speed Output
X
1
0
0
0
0
1
0
8-bit PWM
X
1
0
0
1
X
0
X
Watchdog Timer
Figure 13. PCA Module Modes (CCAPMn Register)
PCA Capture Mode
To use one of the PCA modules in the capture mode either one or
both of the CCAPM bits CAPN and CAPP for that module must be
set. The external CEX input for the module (on port 1) is sampled for
a transition. When a valid transition occurs the PCA hardware loads
the value of the PCA counter registers (CH and CL) into the
module’s capture registers (CCAPnL and CCAPnH). If the CCFn bit
for the module in the CCON SFR and the ECCFn bit in the CCAPMn
SFR are set then an interrupt will be generated. Refer to Figure 14.
counter and the module’s capture registers. To activate this mode
the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must
be set (see Figure 16).
Pulse Width Modulator Mode
All of the PCA modules can be used as PWM outputs. Figure 17
shows the PWM function. The frequency of the output depends on
the source for the PCA timer. All of the modules will have the same
frequency of output because they all share the PCA timer. The duty
cycle of each module is independently variable using the module’s
capture register CCAPLn. When the value of the PCA CL SFR is
less than the value in the module’s CCAPLn SFR the output will be
low, when it is equal to or greater than the output will be high. When
CL overflows from FF to 00, CCAPLn is reloaded with the value in
CCAPHn. the allows updating the PWM without glitches. The PWM
and ECOM bits in the module’s CCAPMn register must be set to
enable the PWM mode.
16-bit Software Timer Mode
The PCA modules can be used as software timers by setting both
the ECOM and MAT bits in the modules CCAPMn register. The PCA
timer will be compared to the module’s capture registers and when a
match occurs an interrupt will occur if the CCFn (CCON SFR) and
the ECCFn (CCAPMn SFR) bits for the module are both set (see
Figure 15).
High Speed Output Mode
In this mode the CEX output (on port 4) associated with the PCA
module will toggle each time a match occurs between the PCA
2013 Sep 04
23
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
CF
CR
––
CCF4
CCF3
CCF2
CCF1
CCF0
CCON
(41AH)
PCA INTERRUPT
(TO CCFn)
PCA TIMER/COUNTER
CH
CL
CCAPnH
CCAPnL
CAPTURE
CEXn
––
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
0
0
0
0
ECCFn
CCAPMn, n= 0 to 4
(491H–495H)
SU01309
Figure 14. PCA Capture Mode
CF
WRITE TO
CCAPnH
––
CCF4
CCF3
CCF2
CCF1
CCF0
CCON
(41AH)
RESET
CCAPnH
WRITE TO
CCAPnL
0
CR
PCA INTERRUPT
CCAPnL
(TO CCFn)
1
ENABLE
MATCH
16–BIT COMPARATOR
CH
CL
PCA TIMER/COUNTER
––
ECOMn
CAPPn
CAPNn
0
0
MATn
TOGn
PWMn
0
0
ECCFn
CCAPMn, n= 0 to 4
(491H–495H)
SU01310
Figure 15. PCA Compare Mode
2013 Sep 04
24
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
CF
WRITE TO
CCAPnH
CR
CCF4
CCF3
CCF2
CCF1
CCON
(41AH)
CCF0
RESET
CCAPnH
WRITE TO
CCAPnL
0
––
PCA INTERRUPT
CCAPnL
(TO CCFn)
1
ENABLE
MATCH
16–BIT COMPARATOR
TOGGLE
CH
CEXn
CL
PCA TIMER/COUNTER
––
ECOMn
CAPPn
CAPNn
0
0
MATn
TOGn
PWMn
1
CCAPMn, n: 0..4
(491H–495H)
ECCFn
0
SU01311
Figure 16. PCA High Speed Output Mode
CCAPnH
CCAPnL
0
CL < CCAPnL
ENABLE
8–BIT
COMPARATOR
CEXn
CL >= CCAPnL
1
CL
OVERFLOW
PCA TIMER/COUNTER
––
ECOMn
CAPPn
CAPNn
MATn
TOGn
0
0
0
0
PWMn
ECCFn
CCAPMn, n: 0..4
(491H–495H)
0
SU01312
Figure 17. PCA PWM Mode
2013 Sep 04
25
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
CIDL
WRITE TO
CCAP4H
––
––
––
CPS1
CPS0
ECF
CMOD
(490H)
RESET
CCAP4H
WRITE TO
CCAP4L
0
WDTE
CCAP4L
MODULE 4
1
ENABLE
MATCH
16–BIT COMPARATOR
CH
RESET
CL
PCA TIMER/COUNTER
––
ECOMn
CAPPn
CAPNn
MATn
0
0
1
TOGn
X
PWMn
ECCFn
0
X
CCAPM4
(495H)
SU01313
Figure 18. PCA Watchdog Timer m(Module 4 only)
PCA Watchdog Timer
An on-board watchdog timer is available with the PCA to improve
the reliability of the system without increasing chip count. Watchdog
timers are useful for systems that are susceptible to noise, power
glitches, or electrostatic discharge. Module 4 is the only PCA
module that can be programmed as a watchdog. However, this
module can still be used for other modes if the watchdog is not
needed.
The first two options are more reliable because the watchdog timer
is never disabled as in option #3. If the program counter ever goes
astray, a match will eventually occur and cause an internal reset.
The second option is also not recommended if other PCA modules
are being used. Remember, the PCA timer is the time base for all
modules; changing the time base for other modules would not be a
good idea. Thus, in most applications the first solution is the best
option.
Figure 18 shows a diagram of how the watchdog works. The user
pre-loads a 16-bit value in the compare registers. Just like the other
compare modes, this 16-bit value is compared to the PCA timer
value. If a match is allowed to occur, an internal reset will be
generated. This will not cause the RST pin to be driven low.
Figure 19 shows the code for initializing the watchdog timer. Module
4 can be configured in either compare mode, and the WDTE bit in
CMOD must also be set. The user’s software then must periodically
change (CCAP4H,CCAP4L) to keep a match from occurring with the
PCA timer (CH,CL). This code is given in the WATCHDOG routine in
Figure 19.
In order to hold off the reset, the user has three options:
1. periodically change the compare value so it will never match the
PCA timer,
This routine should not be part of an interrupt service routine,
because if the program counter goes astray and gets stuck in an
infinite loop, interrupts will still be serviced and the watchdog will
keep getting reset. Thus, the purpose of the watchdog would be
defeated. Instead, call this subroutine from the main program within
216 count of the PCA timer.
2. periodically change the PCA timer value so it will never match
the compare values, or
3. disable the watchdog by clearing the WDTE bit before a match
occurs and then re-enable it.
2013 Sep 04
26
NXP Semiconductors
Product specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
INIT_WATCHDOG:
MOV CCAPM4, #4CH
MOV CCAP4L, #0FFH
MOV CCAP4H, #0FFH
OR CMOD, #40H
;
;
;
;
;
;
;
;
XA-S3
Module 4 in compare mode
Write to low byte first
Before PCA timer counts up to
FFFF Hex, these compare values
must be changed
Set the WDTE bit to enable the
watchdog timer without changing
the other bits in CMOD
;
;********************************************************************
;
; Main program goes here, but CALL WATCHDOG periodically.
;
;********************************************************************
;
WATCHDOG:
CLR EA
; Hold off interrupts
MOV CCAP4L, #00
; Next compare value is within
MOV CCAP4H, CH
; 255 counts of the current PCA
SETB EA
; timer value
RET
Figure 19. PCA Watchdog Timer Initialization Code
Watchdog Timer
transmit register, and reading SnBUF accesses a physically
separate receive register.
This is a standard XA-G3 watchdog timer. This watchdog timer
always comes up running at reset. The watchdog acts the same on
EPROM, ROM, and ROMless parts, as in the XA-G3.
The serial port can operate in 4 modes:
Mode 0: Serial I/O expansion mode. Serial data enters and exits
through RxDn. TxDn outputs the shift clock. 8 bits are
transmitted/received (LSB first). (The baud rate is fixed at 1/16 the
oscillator frequency.)
UARTs
Standard XA-S3 UART0 and UART1 with double buffered transmit
register. A flag has been added to SnSTAT that is set if any of the
status flags (BRn, FEn, or OEn) is set for the corresponding UART
channel. This allows polling for UART errors quickly at the interrupt
service routine. Baud rate sources may be timer 1 or timer 2.
Mode 1: Standard 8-bit UART mode. 10 bits are transmitted
(through TxDn) or received (through RxDn): a start bit (0), 8 data
bits (LSB first), and a stop bit (1). On receive, the stop bit goes into
RB8 in Special Function Register SnCON. The baud rate is variable.
The XA-S3 includes 2 UART ports that are compatible with the
enhanced UART used on the XA-G3.
Mode 2: Fixed rate 9-bit UART mode. 11 bits are transmitted
(through TxD) or received (through RxD): start bit (0), 8 data bits
(LSB first), a programmable 9th data bit, and a stop bit (1). On
Transmit, the 9th data bit (TB8_n in SnCON) can be assigned the
value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could
be moved into TB8_n. On receive, the 9th data bit goes into RB8_n
in Special Function Register SnCON, while the stop bit is ignored.
The baud rate is programmable to 1/32 of the oscillator frequency.
The UART has separate interrupt vectors for each UART’s transmit
and receive functions. The UART transmitter has been double
buffered, allowing packed transmission of data with no gaps
between bytes and less critical interrupt service routine timing. A
break detect function has been added to the UART. This operates
independently of the UART itself and provides a start-of-break
status bit that the program may test. An Overrun Error flag allows
detection of missed characters in the received data stream. The
double buffered UART transmitter may require some software
changes if code is used that was written for the original XA-G3
single buffered UART.
Mode 3: Standard 9-bit UART mode. 11 bits are transmitted
(through TxDn) or received (through RxDn): a start bit (0), 8 data
bits (LSB first), a programmable 9th data bit, and a stop bit (1).
In fact, Mode 3 is the same as Mode 2 in all respects except baud
rate. The baud rate in Mode 3 is variable.
Each UART baud rate is determined by either a fixed division of the
oscillator (in UART modes 0 and 2) or by the timer 1 or timer 2
overflow rate (in UART modes 1 and 3).
In all four modes, transmission is initiated by any instruction that
uses SnBUF as a destination register. Reception is initiated in
Mode 0 by the condition RI_n = 0 and REN_n = 1. Reception is
initiated in the other modes by the incoming start bit if REN_n = 1.
Timer 1 defaults to clock both UART0 and UART1. Timer 2 can be
programmed to clock either UART0 through T2CON (via bits R0CLK
and T0CLK) or UART1 through T2MOD (via bits R1CLK and
T1CLK). In this case, the UART not clocked by T2 could use T1 as
the clock source.
The serial port receive and transmit registers are both accessed at
Special Function Register SnBUF. Writing to SnBUF loads the
2013 Sep 04
27
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
CLOCKING SCHEME/BAUD RATE GENERATION
Serial Port Control Register
The serial port control and status register is the Special Function
Register SnCON, shown in Figure 21. This register contains not only
the mode selection bits, but also the 9th data bit for transmit and
receive (TB8_n and RB8_n), and the serial port interrupt bits (TI_n
and RI_n).
The XA UARTS clock rates are determined by either a fixed division
(modes 0 and 2) of the oscillator clock or by the Timer 1 or Timer 2
overflow rate (modes 1 and 3).
The clock for the UARTs in XA runs at 16x the Baud rate. If the
timers are used as the source for Baud Clock, since maximum
speed of timers/Baud Clock is Osc/4, the maximum baud rate is
timer overflow divided by 16 i.e. Osc/64.
TI Flag
In order to allow easy use of the double buffered UART transmitter
feature, the TI_n flag is set by the UART hardware under two
conditions. The first condition is the completion of any byte
transmission. This occurs at the end of the stop bit in modes 1, 2, or
3, or at the end of the eighth data bit in mode 0. The second
condition is when SnBUF is written while the UART transmitter is
idle. In this case, the TI_n flag is set in order to indicate that the
second UART transmitter buffer is still available.
In Mode 0, it is fixed at Osc/16. In Mode 2, however, the fixed rate
is Osc/32.
Pre-scaler
for all Timers T0
T0,1,2
12
controlled by PT1, PT0
bits in SCR
Typically, UART transmitters generate one interrupt per byte
transmitted. In the case of the XA UART, one additional interrupt is
generated as defined by the stated conditions for setting the TI_n
flag. This additional interrupt does not occur if double buffering is
bypassed as explained below. Note that if a character oriented
approach is used to transmit data through the UART, there could be
a second interrupt for each character transmitted, depending on the
timing of the writes to SBUF. For this reason, it is generally better to
bypass double buffering when the UART transmitter is used in
character oriented mode. This is also true if the UART is polled
rather than interrupt driven, and when transmission is character
oriented rather than message or string oriented. The interrupt occurs
at the end of the last byte transmitted when the UART becomes idle.
Among other things, this allows a program to determine when a
message has been transmitted completely. The interrupt service
routine should handle this additional interrupt.
00
Osc/4
01
Osc/16
10
Osc/64
11
reserved
Baud Rate for UART Mode 0:
Baud_Rate = Osc/16
Baud Rate calculation for UART Mode 1 and 3:
Baud_Rate = Timer_Rate/16
Timer_Rate = Osc/(N*(Timer_Range– Timer_Reload_Value))
where N = the TCLK prescaler value: 4, 16, or 64.
and Timer_Range = 256 for timer 1 in mode 2.
65536 for timer 1 in mode 0 and timer 2
in count up mode.
The timer reload value may be calculated as follows:
Timer_Reload_Value = Timer_Range–(Osc/(Baud_Rate*N*16))
NOTES:
1.. The maximum baud rate for a UART in mode 1 or 3 is Osc/64.
2.. The lowest possible baud rate (for a given oscillator frequency
and N value) may be found by using a timer reload value of 0.
3.. The timer reload value may never be larger than the timer range.
4.. If a timer reload value calculation gives a negative or fractional
result, the baud rate requested is not possible at the given
oscillator frequency and N value.
The recommended method of using the double buffering in the
application program is to have the interrupt service routine handle a
single byte for each interrupt occurrence. In this manner the program
essentially does not require any special considerations for double
buffering. Unless higher priority interrupts cause delays in the servicing
of the UART transmitter interrupt, the double buffering will result in
transmitted bytes being tightly packed with no intervening gaps.
Baud Rate for UART Mode 2:
Baud_Rate = Osc/32
9-bit Mode
Please note that the ninth data bit (TB8) is not double buffered. Care
must be taken to insure that the TB8 bit contains the intended data
at the point where it is transmitted. Double buffering of the UART
transmitter may be bypassed as a simple means of synchronizing
TB8 to the rest of the data stream.
Using Timer 2 to Generate Baud Rates
Timer T2 is a 16-bit up/down counter in XA. As a baud rate
generator, timer 2 is selected as a clock source for either/both
UART0 and UART1 transmitters and/or receivers by setting TCLKn
and/or RCLKn in T2CON and T2MOD. As the baud rate generator,
T2 is incremented as Osc/N where N = 4, 16 or 64 depending on
TCLK as programmed in the SCR bits PT1, and PTO. So, if T2 is
the source of one UART, the other UART could be clocked by either
T1 overflow or fixed clock, and the UARTs could run independently
with different baud rates.
Bypassing Double Buffering
The UART transmitter may be used as if it is single buffered. The
recommended UART transmitter interrupt service routine (ISR)
technique to bypass double buffering first clears the TI_n flag upon
entry into the ISR, as in standard practice. This clears the interrupt
that activated the ISR. Secondly, the TI_n flag is cleared immediately
following each write to SnBUF. This clears the interrupt flag that would
otherwise direct the program to write to the second transmitter buffer.
If there is any possibility that a higher priority interrupt might become
active between the write to SnBUF and the clearing of the TI_n flag,
the interrupt system may have to be temporarily disabled during that
sequence by clearing, then setting the EA bit in the IEL register.
T2CON
0x418
bit5
bit4
RCLK0
TCLK0
T2MOD
0x419
bit5
bit4
RCLK1
TCLK1
Prescaler Select for Timer Clock (TCLK)
SCR
0x440
2013 Sep 04
28
bit3
bit2
PT1
PT0
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
SnSTAT Address: S0STAT 421
S1STAT 425
Bit Addressable
Reset Value: 00H
MSB
—
LSB
—
—
—
FEn
BRn
OEn
STINTn
BIT
SYMBOL FUNCTION
SnSTAT.3 FEn
Framing Error flag is set when the receiver fails to see a valid STOP bit at the end of the frame.
Cleared by software.
SnSTAT.2 BRn
Break Detect flag is set if a character is received with all bits (including STOP bit) being logic ‘0’. Thus
it gives a “Start of Break Detect” on bit 8 for Mode 1 and bit 9 for Modes 2 and 3. The break detect
feature operates independently of the UARTs and provides the START of Break Detect status bit that
a user program may poll. Cleared by software.
SnSTAT.1 OEn
Overrun Error flag is set if a new character is received in the receiver buffer while it is still full (before
the software has read the previous character from the buffer), i.e., when bit 8 of a new byte is
received while RI in SnCON is still set. Cleared by software.
SnSTAT.0 STINTn
This flag must be set to enable any of the above status flags to generate a receive interrupt (RIn). The
only way it can be cleared is by a software write to this register.
SU00607B
Figure 20. Serial Port Extended Status (SnSTAT) Register
(See also Figure 22 regarding Framing Error flag)
UART INTERRUPT SCHEME
Error (FE) flag. In a Mode 1 reception, if SM2 = 1, the receive
interrupt will not be activated unless a valid stop bit is received.
There are separate interrupt vectors for each UART’s transmit and
receive functions.
Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART
to recognize certain addresses in the serial bit stream by using
hardware to make the comparisons. This feature saves a great deal
of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART
modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be
automatically set when the received byte contains either the “Given”
address or the “Broadcast” address. The 9 bit mode requires that
the 9th information bit is a 1 to indicate that the received information
is an address and not data. Automatic address recognition is shown
in Figure 23.
Table 5. Interrupt Vector Locations for UARTs
Vector Address
Interrupt Source
Arbitration
A0H – A3H
UART 0 Receiver
9
A4H – A7H
UART 0 Transmitter
10
A8H – ABH
UART 1 Receiver
11
ACH – AFH
UART 1 Transmitter
12
NOTE:
The transmit and receive vectors could contain the same ISR
address to work like a 8051 interrupt scheme
Error Handling, Status Flags and Break Detect
XA UARTs have several error flags as described in Figures 20 and
22.
Using the Automatic Address Recognition feature allows a master to
selectively communicate with one or more slaves by invoking the
Given slave address or addresses. All of the slaves may be
contacted by using the Broadcast address. Two special Function
Registers are used to define the slave’s address, SADDR, and the
address mask, SADEN. SADEN is used to define which bits in the
SADDR are to be used and which bits are “don’t care”. The SADEN
mask can be logically ANDed with the SADDR to create the “Given”
address which the master will use for addressing each of the slaves.
Use of the Given address allows multiple slaves to be recognized
while excluding others. The following examples will help to show the
versatility of this scheme:
Multiprocessor Communications
Modes 2 and 3 have a special provision for multiprocessor
communications. In these modes, 9 data bits are received. The 9th
one goes into RB8. Then comes a stop bit. The port can be
programmed such that when the stop bit is received, the serial port
interrupt will be activated only if RB8 = 1. This feature is enabled by
setting bit SM2 in SCON. A way to use this feature in multiprocessor
systems is as follows:
When the master processor wants to transmit a block of data to one
of several slaves, it first sends out an address byte which identifies
the target slave. An address byte differs from a data byte in that the
9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no
slave will be interrupted by a data byte. An address byte, however,
will interrupt all slaves, so that each slave can examine the received
byte and see if it is being addressed. The addressed slave will clear
its SM2 bit and prepare to receive the data bytes that will be coming.
The slaves that weren’t being addressed leave their SM2s set and
go on about their business, ignoring the coming data bytes.
SADDR =
SADEN =
Given
=
1100 0000
1111 1101
1100 00X0
Slave 1
SADDR =
SADEN =
Given
=
1100 0000
1111 1110
1100 000X
In the above example SADDR is the same and the SADEN data is
used to differentiate between the two slaves. Slave 0 requires a 0 in
bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is
ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
SM2 has no effect in Mode 0, and in Mode 1 can be used to check
the validity of the stop bit although this is better done with the Framing
2013 Sep 04
Slave 0
29
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be
selected at the same time by an address which has bit 0 = 0 (for
slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.
In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary to make bit 2 = 1 to exclude slave 2.
In a more complex system the following could be used to select
slaves 1 and 2 while excluding slave 0:
Slave 0
SADDR =
SADEN =
Given
=
1100 0000
1111 1001
1100 0XX0
Slave 1
SADDR =
SADEN =
Given
=
1110 0000
1111 1010
1110 0X0X
SADDR =
SADEN =
Given
=
1110 0000
1111 1100
1110 00XX
Slave 2
SnCON
Address:
S0CON 420
S1CON 424
The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are teated as
don’t-cares. In most cases, interpreting the don’t-cares as ones, the
broadcast address will be FF hexadecimal.
Upon reset SADDR and SADEN are loaded with 0s. This produces
a given address of all “don’t cares” as well as a Broadcast address
of all “don’t cares”. This effectively disables the Automatic
Addressing mode and allows the microcontroller to use standard
UART drivers which do not make use of this feature.
MSB
SM0
Bit Addressable
Reset Value: 00H
LSB
SM1
SM2
REN
TB8
RB8
TI
RI
Where SM0, SM1 specify the serial port mode, as follows:
SM0
0
0
1
1
SM1
0
1
0
1
Mode
0
1
2
3
Description
shift register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
fOSC/16
variable
fOSC/32
variable
BIT
SYMBOL FUNCTION
SnCON.5 SM2
Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then RI
will not be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI will not be activated if a
valid stop bit was not received. In Mode 0, SM2 should be 0.
SnCON.4 REN
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
SnCON.3 TB8
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. The TB8 bit is not
double buffered. See text for details.
SnCON.2 RB8
In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, if SM2=0, RB8 is the stop bit that was
received. In Mode 0, RB8 is not used.
SnCON.1 TI
Transmit interrupt flag. Set when another byte may be written to the UART transmitter. See text for details.
Must be cleared by software.
SnCON.0 RI
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the end of the stop bit time
in the other modes (except see SM2). Must be cleared by software.
SU00597C
Figure 21. Serial Port Control (SnCON) Register
2013 Sep 04
30
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
D0
D1
D2
D3
START
BIT
D4
D5
D6
D7
D8
DATA BYTE
ONLY IN
MODE 2, 3
STOP
BIT
if 0, sets FE
—
—
—
—
FEn
BRn
OEn
STINTn
SnSTAT
SU00598
Figure 22. UART Framing Error Detection
D0
D1
D2
D3
SM0_n
D4
SM1_n
1
1
D5
D6
SM2_n
REN_n
TB8_n
1
X
1
1
0
RECEIVED ADDRESS D0 TO D7
D7
D8
RB8_n
TI_n
RI_n
SnCON
COMPARATOR
PROGRAMMED ADDRESS
IN UART MODE 2 OR MODE 3 AND SM2 = 1:
INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”
– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES
– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
SU00613
Figure 23. UART Multiprocessor Communication, Automatic Address Recognition
Clocking / Baud Rate Generation
The latched values of EA and BUSW are NOT automatically
updated when an internal reset occurs. RSTOUT may be used to
apply an external reset to the XA-S3 in order to update the
previously latched EA and BUSW values. However, since RSTOUT
reflects ALL reset sources, it cannot simply be fed back into the RST
pin without other logic.
Same as for the XA-G3.
I/O Port Output Configuration
Port output configurations are the same as for the XA-G3: open
drain, quasi-bidirectional, push-pull, and off.
The reset source identification register (RSTSRC) indicates the cause
of the most recent XA reset. The cause may have been an externally
applied reset signal, execution of the RESET instruction, or a
Watchdog reset. Figure 24 shows the fields in the RSTSRC register.
External Bus
The external bus operates in the same manner as the XA-G3, but
all 24 address lines are brought out to the outside world. This
allows for a maximum of 16 Mbytes of code memory and 16
Mbytes of data memory.
Power Reduction Modes
The XA-S3 supports Idle and Power Down modes of power
reduction. The idle mode leaves some peripherals running in order
to allow them to activate the processor when an interrupt is
generated. The power down mode stops the oscillator in order to
absolutely minimize power. The processor can be made to exit
power down mode via a reset or one of the external interrupt inputs
(INT0 or INT1). This will occur if the interrupt is enabled and its
priority is higher than that defined by IM3 through IM0. In power
down mode, the power supply voltage may be reduced to the RAM
keep-alive voltage VRAM. This retains the RAM, register, and SFR
contents at the point where power down mode was entered. VDD
must be raised to within the operating range before power down
mode is exited.
Clock Output
The CLKOUT pin allows easier external bus interfacing in some
situations. This output reflects the X1 clock input to the XA, but is
delayed to match the external bus outputs and strobes. The default
is for CLKOUT to be on at reset, but it may be turned off via the
CLKD bit that has been added to the BCR register.
Reset
Active low reset input, the same as the XA-G3.
The associated RSTOUT pin provides an external indication via an
active low open drain output when an internal reset occurs. The
RSTOUT pin will be driven low when the RST pin is driven low,
when a Watchdog reset occurs or the RESET instruction is
executed. This signal may be used to inform other devices in a
system that the XA-S3 has been reset.
2013 Sep 04
31
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
RSTSRC
Address:463h
Not bit Addressable
Reset Value: see below
BIT
RSTSRC.7
RSTSRC.6
RSTSRC.5
RSTSRC.4
RSTSRC.3
RSTSRC.2
RSTSRC.1
RSTSRC.0
SYMBOL
—
—
—
—
—
R_WD
R_CMD
R_EXT
MSB
—
LSB
—
—
—
—
R_WD
R_CMD R_EXT
FUNCTION
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Indicates that the last reset was caused by a watchdog timer overflow.
Indicates that the last reset was caused by execution of the RESET instruction.
Indicates that the last reset was caused by the external RST input.
SU00942
Figure 24. Reset source register (RSTSRC)
INTERRUPTS
exception interrupts (plus reset), and 16 traps. The maskable event
interrupts share a global interrupt disable bit (the EA bit in the IEL
register) and each also has a separate individual interrupt enable bit
(in the IEL or IEH registers). Only three bits of the IPA register
values are used on the XA-S3. Each event interrupt can be set to
occur at one of 8 priority levels via bits in the Interrupt Priority (IP)
registers, IPA0 through IPA5. The value 0 in the IPA field gives the
interrupt priority 0, in effect disabling the interrupt. A value of 1 gives
the interrupt a priority of 9, the value 2 gives priority 10, etc. The
result is the same as if all four bits were used and the top bit set for
all values except 0. Details of the priority scheme may be found in
the XA User Guide.
XA-S3 interrupt sources include the following:
• External interrupts 0 and 1 (2)
• Timer 0, 1, and 2 interrupts (3)
• PCA: 1 global and 5 channel interrupts (6)
• A/D interrupt (1)
• UART 0 transmitter and receiver interrupts (2)
• UART 1 transmitter and receiver interrupts (2)
• I2C interrupt (1)
• Software interrupts (7)
The complete interrupt vector list for the XA-S3, including all
4 interrupt types, is shown in the following tables. The tables include
the address of the vector for each interrupt, the related priority
register bits (if any), and the arbitration ranking for that interrupt
source. The arbitration ranking determines the order in which
interrupts are processed if more than one interrupt of the same
priority occurs simultaneously.
There are a total of 17 hardware interrupt sources, enable bits,
priority bit sets, etc.
The XA-S3 supports a total of 17 maskable event interrupt sources
(for the various XA peripherals), seven software interrupts, 5
EXCEPTION/TRAPS PRECEDENCE
DESCRIPTION
VECTOR ADDRESS
ARBITRATION RANKING
Reset (h/w, watchdog, s/w)
0000–0003
0 (High)
Breakpoint
0004–0007
1
Trace
0008–000B
1
Stack Overflow
000C–000F
1
Divide by 0
0010–0013
1
User RETI
0014–0017
1
TRAP 0–15 (software)
0040–007F
1
2013 Sep 04
32
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
EVENT INTERRUPTS
FLAG BIT
VECTOR ADDRESS
ENABLE BIT
INTERRUPT
PRIORITY
ARBITRATION
RANKING
External Interrupt 0
IE0
0080–0083
EX0
IPA0.2–0 (PX0)
2
Timer 0 Interrupt
TF0
0084–0087
ET0
IPA0.6–4 (PT0)
3
DESCRIPTION
External Interrupt 1
IE1
0088–008B
EX1
IPA1.2–0 (PX1)
4
Timer 1 Interrupt
TF1
008C–008F
ET1
IPA1.6–4 (PT1)
5
Timer 2 Interrupt
TF2 (EXF2)
0090–0093
ET2
IPA2.2–0 (PT2)
6
PCA Interrupt
CCF0–CCF4, CF
0094–0097
EPC
IPA2.6–4 (PPC)
7
A/D Interrupt
ADINT
0098–009B
EAD
IPA3.2–0 (PAD)
8
Serial Port 0 Rx
RI_0
00A0–00A3
ERI0
IPA4.2–0 (PRI0)
9
Serial Port 0 Tx
TI_0
00A4–00A7
ETI0
IPA4.6–4 (PTI0)
10
Serial Port 1 Rx
RI_1
00A8–00AB
ERI1
IPA5.2–0 (PRI1)
11
Serial Port 1 Tx
TI_1
00AC–00AF
ETI1
IPA5.6–4 (PTI1)
12
PCA channel 0
CCF0
00C0–00C3
EC0
IPB0.2–0 (PC0)
17
PCA channel 1
CCF1
00C4–00C7
EC1
IPB0.6–4 (PC1)
18
PCA channel 2
CCF2
00C8–00CB
EC2
IPB1.2–0 (PC2)
19
PCA channel 3
CCF3
00CC–00CF
EC3
IPB1.6–4 (PC3)
20
PCA channel 4
CCF4
00D0–00D3
EC4
IPB2.2–0 (PC4)
21
SI
00D4–00D7
EI2
IPB2.6–4 (PI2)
22
I2C Interrupt
SOFTWARE INTERRUPTS
FLAG BIT
VECTOR ADDRESS
ENABLE BIT
INTERRUPT PRIORITY
Software Interrupt 1
DESCRIPTION
SWR1
0100–0103
SWE1
(fixed at 1)
Software Interrupt 2
SWR2
0104–0107
SWE2
(fixed at 2)
Software Interrupt 3
SWR3
0108–010B
SWE3
(fixed at 3)
Software Interrupt 4
SWR4
010C–010F
SWE4
(fixed at 4)
Software Interrupt 5
SWR5
0110–0113
SWE5
(fixed at 5)
Software Interrupt 6
SWR6
0114–0117
SWE6
(fixed at 6)
Software Interrupt 7
SWR7
0118–011B
SWE7
(fixed at 7)
2013 Sep 04
33
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
Operating temperature under bias
–55 to +125
°C
Storage temperature range
–65 to +150
°C
0 to +13.0
V
Voltage on EA/VPP pin to VSS
Voltage on any other pin to VSS
–0.5 to VDD+0.5 V
V
Maximum IOL per I/O pin
15
mA
Power dissipation (based on package heat transfer, not device power consumption)
1.5
W
DC ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, unless otherwise specified.
Tamb = 0 to +70°C for commercial, Tamb = –40°C to +85°C for industrial, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
MIN
IDD
Power supply current, operating
5.0 V, 30 MHz
IID
Power supply current, Idle mode
5.0 V, 30 MHz
IPD
Power supply current, Power Down mode
VRAM
RAM keep-alive voltage
1.5
VIL
Input low voltage
–0.5
VIH
Input high voltage, except XTAL1, RST
5.0 V, 3.0 V
TYP
5
5.0 V, 3.0 V, –40 to +85°C
MAX
UNIT
80
mA
35
mA
100
µA
150
µA
V
0.22 VDD
V
VDD = 5.0 V
2.2
V
VDD = 3.0 V
2.0
V
For both 3.0 V and 5.0 V
0.7 VDD
VIH1
Input high voltage to XTAL1, RST
VOL
Output low voltage, all ports, ALE, PSEN4, CLKOUT
IOL = 3.2 mA, VDD = 5.0 V
VOH1
Output high voltage, all ports, ALE, PSEN2, CLKOUT
IOH = –100 µA, VDD = 4.5 V
2.4
V
IOH = –30 µA, VDD = 2.7 V
2.0
V
IOH = –3.2 mA, VDD = 4.5 V
2.4
V
IOH = –1.0 mA, VDD = 2.7 V
2.2
V
IOL = 1.0 mA, VDD = 3.0 V
VOH2
Output high voltage, all ports ALE,
PSEN3,
CLKOUT
capacitance1
V
0.5
V
0.4
V
CIO
Input/Output pin
15
pF
IIL
Logical 0 input current, all ports7
VIN = 0.45 V
–50
µA
ILI
Input leakage current, all ports6
VIN = VIL or VIH
±10
µA
ITL
Logical 1 to 0 transition current, all ports5
At VDD = 5.5 V
–650
µA
At VDD = 2.7 V
–250
µA
NOTES:
1. Maximum 15pF for EA/VPP.
2. Ports in quasi-bidirectional mode with weak pullup (applies to ALE, PSEN only during RESET).
3. Ports in PUSH-PULL mode, both pullup and pulldown assumed to be the same strength.
4. In all output modes.
5. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when
VIN is approximately 2 V.
6. Measured with port in high impedance mode.
7. Measured with port in quasi-bidirectional mode.
8. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
15 mA
Maximum IOL per port pin:
26 mA
Maximum IOL per 8-bit port:
71 mA
Maximum total IOL for all outputs:
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
2013 Sep 04
34
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
8-BIT MODE A/D CONVERTER DC ELECTRICAL CHARACTERISTICS
Tamb = 0 to +70°C for commercial, Tamb = –40 to +85°C for industrial, unless otherwise specified.
SYMBOL
PARAMETER
AVDD
Analog supply voltage
AIDD
Analog supply current (operating)
AIID
Analog supply current (Idle mode)
AIPD
Analog supply current (Power-Down mode)
TEST CONDITIONS
LIMITS
UNIT
MIN
MAX
2.7
3.3
V
2.5
mA
2.5
µA
Commercial temperature range
100
µA
Industrial temperature range
150
µA
Port 5 = 0 to AVDD
AVIN
Analog input voltage
RREF
Resistance between VREF+ and VREF–
CIA
Analog input capacitance
15
pF
DLe
Differential non-linearity1, 2, 3
±1
LSB
ILe
Integral non-linearity1, 4
±1
LSB
±2.5
LSB
±1
%
±3
LSB
±1
LSB
–60
dB
error1, 5
OSe
Offset
Ge
Gain error1, 6
error1, 7
Ae
Absolute voltage
MCTC
Channel-to-channel matching
Ct
Crosstalk between inputs of
port8
0 – 100 kHz
AVSS –0.2
AVDD +0.2
V
125
225
kΩ
NOTES:
1. Conditions: AVREF– = 0 V; AVREF+ = 3.07 V.
2. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. See Figure 25.
3. The ADC is monotonic, there are no missing codes.
4. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 25.
5. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
the straight line which fits the ideal transfer curve. See Figure 25.
6. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. See Figure 25.
7. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve.
8. This should be considered when both analog and digital signals are input simultaneously to Port 5. Parameter is guaranteed bydesign.
2013 Sep 04
35
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
10-BIT10 MODE A/D CONVERTER DC ELECTRICAL CHARACTERISTICS
Tamb = 0 to +70°C for commercial, Tamb = –40 to +85°C for industrial, unless otherwise specified.
SYMBOL
PARAMETER
AVDD
Analog supply voltage
AIDD
Analog supply current (operating)
AIID
Analog supply current (Idle mode)
AIPD
Analog supply current (Power-Down mode)
AVIN
Analog input voltage
RREF
Resistance between VREF+ and VREF–
CIA
Analog input capacitance
DLe
Differential non-linearity1, 2, 3
ILe
Integral non-linearity1, 4
Offset
Ge
Gain error1, 6
2.7
3.3
V
2.5
mA
2.5
µA
Commercial temperature range
100
µA
Industrial temperature range
150
µA
Port 5 = 0 to AVDD
AVSS –0.2
AVDD +0.2
V
125
225
kΩ
15
pF
±1 9
LSB
±2.5 9
LSB
9
±1 9
averaging)1, 7
Absolute voltage error (with
MCTC
Channel-to-channel matching
port8
UNIT
MAX
±6
Ae
Crosstalk between inputs of
LIMITS
MIN
error1, 5
OSe
Ct
TEST CONDITIONS
±8
0 – 100 kHz
9
LSB
%
LSB
±1
LSB
–60
dB
NOTES:
1. Conditions: AVREF– = 0 V; AVREF+ = 3.07 V.
2. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. See Figure 25.
3. The ADC is monotonic, there are no missing codes.
4. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 25.
5. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
the straight line which fits the ideal transfer curve. See Figure 25.
6. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. See Figure 25.
7. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve.
8. This should be considered when both analog and digital signals are input simultaneously to Port 5. Parameter is guaranteed bydesign.
9. 10-bit mode only.
10. 10-bit mode is only operational up to fC = 20 MHz.
2013 Sep 04
36
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
Offset
error
OSe
Gain
error
Ge
255
Full Scale
error
FSe
254
253
252
251
250
(2)
7
Code
Out
(1)
6
5
(5)
4
(4)
3
(3)
2
1
1 LSB
(ideal)
0
1
2
3
4
5
6
7
250
251
252
253
254
255
256
AVIN (LSBideal)
Offset
error
OSe
1 LSB =
AVREF+
– AVREF–
256
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential non-linearity (DLe).
(4) Integral non-linearity (ILe).
(5) Center of a step of the actual transfer curve.
SU01010
Figure 25. ADC Conversion Characteristic
2013 Sep 04
37
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
AC ELECTRICAL CHARACTERISTICS (5 V)
VDD = 4.5 V to 5.5 V; Tamb = 0 to +70°C for commercial, Tamb = –40°C to +85°C for industrial.
SYMBOL
FIGURE
LIMITS
PARAMETER
MIN
MAX
0
30
UNIT
External Clock
fC
32
Oscillator frequency
tC
32
Clock period and CPU timing cycle
MHz
tCHCX
32
tCLCX
32
tCLCH
32
Clock rise time (Note 7)
5
ns
tCHCL
32
Clock fall time (Note 7)
5
ns
1/fC
ns
Clock high-time (Note 7)
tC * 0.5
ns
Clock low time (Note 7)
tC * 0.4
ns
Address Cycle
tLHLL
26, 28, 30
ALE pulse width (programmable)
(V1 * tC) – 6
ns
tAVLL
26, 28, 30
Address valid to ALE de-asserted (set-up)
(V1 * tC) – 12
ns
tLLAX
26, 28, 30
Address hold after ALE de-asserted
(tC/2) – 10
ns
(V2 * tC) – 10
ns
Code Read Cycle
tPLPH
26
PSEN pulse width
tLLPL
26
ALE de-asserted to PSEN asserted
tAVIVA
26
Address valid to instruction valid, ALE cycle (access time)
(V3 * tC) – 36
ns
tAVIVB
27
Address valid to instruction valid, non-ALE cycle (access time)
(V4 * tC) – 29
ns
tPLIV
26
PSEN asserted to instruction valid (enable time)
(V2 * tC) – 29
ns
tPHIX
26
Instruction hold after PSEN de-asserted
tPHIZ
26
Bus 3-State after PSEN de-asserted
tIXUA
26
Hold time of unlatched part of address after instruction latched
(tC/2) – 7
ns
0
ns
tC – 8
ns
0
ns
(V7 * tC) – 10
ns
Data Read Cycle
tRLRH
28
RD pulse width
tLLRL
28
ALE de-asserted to RD asserted
tAVDVA
28
Address valid to data input valid, ALE cycle (access time)
(V6 * tC) – 36
ns
tAVDVB
29
Address valid to data input valid, non-ALE cycle (access time)
(V5 * tC) – 29
ns
tRLDV
28
RD low to valid data in (enable time)
(V7 * tC) – 29
ns
tRHDX
28
Data hold time after RD de–asserted
tRHDZ
28
Bus 3-State after RD de-asserted (disable time)
tDXUA
28
Hold time of unlatched part of address after data latched
(tC/2) – 7
ns
0
ns
tC – 8
ns
0
ns
Data Write Cycle
tWLWH
30
WR pulse width
(V8 * tC) – 10
ns
tLLWL
30
ALE falling edge to WR asserted
(V12 * tC) – 10
ns
tQVWX
30
Data valid before WR asserted (data set-up time)
(V13 * tC) – 22
ns
tWHQX
30
Data hold time after WR de-asserted (Note 6)
(V11 * tC) – 5
ns
tAVWL
30
Address valid to WR asserted (address set-up time) (Note 5)
(V9 * tC) – 22
ns
tUAWH
30
Hold time of unlatched part of address after WR is de-asserted
(V11 * tC) – 7
ns
tWTH
31
WAIT stable after bus strobe (RD, WR, or PSEN) asserted
tWTL
31
WAIT hold after bus strobe (RD, WR, or PSEN) asserted
Wait Input
NOTES ON PAGE 41.
2013 Sep 04
38
(V10 * tC) – 30
(V10 * tC) – 5
ns
ns
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
AC ELECTRICAL CHARACTERISTICS (5 V RANGE) (continued)
This set of parameters is referenced to the XA-S3 clock output.
SYMBOL
FIGURE
LIMITS
PARAMETER
MIN
MAX
UNIT
Address Cycle
tCHLH
26
CLKOUT rising edge to ALE rising edge
–
13
ns
tCLLL
26
CLKOUT falling edge to ALE falling edge
–
9
ns
tCHAV
26
CLKOUT rising edge to address valid
–
18
ns
tCHAX
26
CLKOUT rising edge to address changing (hold time)
2
–
ns
Code Read Cycle
tCHPL
26
CLKOUT rising edge to PSEN asserted
–
14
ns
tCHPH
26
CLKOUT rising edge to PSEN de-asserted
–
12
ns
tIVCH
26
Instruction valid to CLKOUT rising edge (setup time)
20
–
ns
tCHIX
26
CLKOUT rising edge to instruction changing (hold time)
0
–
ns
tCHIZ
26
CLKOUT rising edge to Bus 3-State (code read)
–
tC–8
ns
–
12
ns
Data Read Cycle
tCHRL
28
CLKOUT rising edge to RD asserted
tCHRH
28
CLKOUT rising edge to RD de-asserted
–
10
ns
tDVCH
28
Data valid to CLKOUT rising edge (setup time)
20
–
ns
tCHDX
28
CLKOUT rising edge to Data changing (hold time)
0
–
ns
tCHDZ
28
CLKOUT rising edge to Bus 3-State (data read)
–
tC–8
ns
Data Write Cycle
tCHWL
30
CLKOUT falling edge to WR asserted
–
12
ns
tCHWH
30
CLKOUT rising edge to WR de-asserted
–
10
ns
tQVCH
30
Data valid to CLKOUT rising edge (setup time)
4
–
ns
tCHQX
30
CLKOUT rising edge to Data changing (hold time)
0
–
ns
31
WAIT valid prior to CLKOUT rising edge8
21
4
ns
Wait Input
tCHWTH
NOTES ON PAGE 41.
2013 Sep 04
39
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
AC ELECTRICAL CHARACTERISTICS (3 V)
VDD = 2.7 V to 4.5 V; Tamb = 0 to +70°C for commercial, Tamb = –40°C to +85°C for industrial.
SYMBOL
FIGURE
LIMITS
PARAMETER
MIN
MAX
UNIT
Address Cycle
tLHLL
26, 28, 30
ALE pulse width (programmable)
(V1 * tC) – 10
ns
tAVLL
26, 28, 30
Address valid to ALE de-asserted (set-up)
(V1 * tC) – 18
ns
tLLAX
26, 28, 30
Address hold after ALE de-asserted
(tC/2) – 12
ns
(V2 * tC) – 12
ns
Code Read Cycle
tPLPH
26
PSEN pulse width
tLLPL
26
ALE de-asserted to PSEN asserted
tAVIVA
26
Address valid to instruction valid, ALE cycle (access time)
(V3 * tC) – 58
ns
tAVIVB
27
Address valid to instruction valid, non-ALE cycle (access time)
(V4 * tC) – 52
ns
tPLIV
26
PSEN asserted to instruction valid (enable time)
(V2 * tC) – 52
ns
tPHIX
26
Instruction hold after PSEN de-asserted
tPHIZ
26
Bus 3-State after PSEN de-asserted
tIXUA
26
Hold time of unlatched part of address after instruction latched
(tC/2) – 9
ns
0
ns
tC – 8
ns
0
ns
(V7 * tC) – 12
ns
(tC/2) – 9
ns
Data Read Cycle
tRLRH
28
RD pulse width
tLLRL
28
ALE de-asserted to RD asserted
tAVDVA
28
Address valid to data input valid, ALE cycle (access time)
(V6 * tC) – 58
ns
tAVDVB
29
Address valid to data input valid, non-ALE cycle (access time)
(V5 * tC) – 52
ns
tRLDV
28
RD low to valid data in (enable time)
(V7 * tC) – 52
ns
tRHDX
28
Data hold time after RD de–asserted
tRHDZ
28
Bus 3-State after RD de-asserted (disable time)
tDXUA
28
Hold time of unlatched part of address after data latched
0
ns
tC – 8
ns
0
ns
Data Write Cycle
tWLWH
30
WR pulse width
(V8 * tC) – 12
ns
tLLWL
30
ALE falling edge to WR asserted
(V12 * tC) – 10
ns
tQVWX
30
Data valid before WR asserted (data set-up time)
(V13 * tC) – 28
ns
tWHQX
30
Data hold time after WR de-asserted (Note 6)
(V11 * tC) – 8
ns
tAVWL
30
Address valid to WR asserted (address set-up time) (Note 5)
(V9 * tC) – 28
ns
tUAWH
30
Hold time of unlatched part of address after WR is de-asserted
(V11 * tC) – 10
ns
tWTH
31
WAIT stable after bus strobe (RD, WR, or PSEN) asserted
tWTL
31
WAIT hold after bus strobe (RD, WR, or PSEN) asserted
Wait Input
NOTES ON PAGE 41.
2013 Sep 04
40
(V10 * tC) – 40
(V10 * tC) – 5
ns
ns
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
AC ELECTRICAL CHARACTERISTICS (3 V RANGE) (continued)
This set of parameters is referenced to the XA-S3 clock output.
SYMBOL
FIGURE
LIMITS
PARAMETER
MIN
MAX
UNIT
Address Cycle
tCHLH
26
CLKOUT rising edge to ALE rising edge
–
15
ns
tCLLL
26
CLKOUT falling edge to ALE falling edge
–
11
ns
tCHAV
26
CLKOUT rising edge to address valid
–
29
ns
tCHAX
26
CLKOUT rising edge to address changing (hold time)
2
–
ns
Code Read Cycle
tCHPL
26
CLKOUT rising edge to PSEN asserted
–
16
ns
tCHPH
26
CLKOUT rising edge to PSEN de-asserted
–
15
ns
tIVCH
26
Instruction valid to CLKOUT rising edge (setup time)
30
–
ns
tCHIX
26
CLKOUT rising edge to instruction changing (hold time)
0
–
ns
tCHIZ
26
CLKOUT rising edge to Bus 3-State (code read)
–
tC–8
ns
–
20
ns
Data Read Cycle
tCHRL
28
CLKOUT rising edge to RD asserted
tCHRH
28
CLKOUT rising edge to RD de-asserted
–
16
ns
tDVCH
28
Data valid to CLKOUT rising edge (setup time)
28
–
ns
tCHDX
28
CLKOUT rising edge to Data changing (hold time)
0
–
ns
tCHDZ
28
CLKOUT rising edge to Bus 3-State (data read)
–
tC–8
ns
Data Write Cycle
tCHWL
30
CLKOUT falling edge to WR asserted
–
19
ns
tCHWH
30
CLKOUT rising edge to WR de-asserted
–
16
ns
tQVCH
30
Data valid to CLKOUT rising edge (setup time)
4
–
ns
tCHQX
30
CLKOUT rising edge to Data changing (hold time)
0
–
ns
31
WAIT valid prior to CLKOUT rising edge8
30
4
ns
Wait Input
tCHWTH
NOTES:
1. Load capacitance for all outputs = 50 pF.
2. Variables V1 through V13 reflect programmable bus timing, which is programmed via the Bus Timing registers (BTRH and BTRL). Refer to
the XA User Guide for details of the bus timing settings.
V1) This variable represents the programmed width of the ALE pulse as determined by the ALEW bit in the BTRL register. V1 = 0.5 if the
ALEW bit = 0, and 1.5 if the ALEW bit = 1.
V2) This variable represents the programmed width of the PSEN pulse as determined by the CR1 and CR0 bits or the CRA1, CRA0, and
ALEW bits in the BTRL register.
– For a bus cycle with no ALE, V2 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. Note that during burst
mode code fetches, PSEN does not exhibit transitions at the boundaries of bus cycles. V2 still applies for the purpose of
determining peripheral timing requirements.
– For a bus cycle with an ALE, V2 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10, and 5 if
CRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5) = 2.
Example: if CRA1/0 = 10 and ALEW = 1, the V2 = 4 – (1.5 + 0.5) = 2.
V3) This variable represents the programmed length of an entire code read cycle with ALE. This time is determined by the CRA1 and
CRA0 bits in the BTRL register. V3 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10, and
5 if CRA1/0 = 11).
V4) This variable represents the programmed length of an entire code read cycle with no ALE. This time is determined by the CR1 and
CR0 bits in the BTRL register. V4 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11.
V5) This variable represents the programmed length of an entire data read cycle with no ALE. This time is determined by the DR1 and
DR0 bits in the BTRH register. V5 = 1 if DR1/0 = 00, 2 if DR1/0 = 01, 3 if DR1/0 = 10, and 4 if DR1/0 = 11.
V6) This variable represents the programmed length of an entire data read cycle with ALE. The time is determined by the DRA1 and
DRA0 bits in the BTRH register. V6 = the total bus cycle duration (2 if DRA1/0 = 00, 3 if DRA1/0 = 01, 4 if DRA1/0 = 10, and
5 if DRA1/0 = 11).
2013 Sep 04
41
NXP Semiconductors
Product specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
XA-S3
This variable represents the programmed width of the RD pulse as determined by the DR1 and DR0 bits or the DRA1, DRA0 in the
BTRH register, and the SLEW bit in the BTRL register. Note that during a 16-bit operation on an 8-bit external bus, RD remains low
and does not exhibit a transition between the first and second byte bus cycles. V7 still applies for the purpose of determining
peripheral timing requirements. The timing for the first byte is for a bus cycle with ALE, the timing for the second byte is for a bus
cycle with no ALE.
– For a bus cycle with no ALE, V7 = 1 if DR1/0 = 00, 2 if DR1/0 = 01, 3 if DR1/0 = 10, and 4 if DR1/0 = 11.
– For a bus cycle with an ALE, V7 = the total bus cycle duration (2 if DRA1/0 = 00, 3 if DRA1/0 = 01, 4 if DRA1/0 = 10, and
5 if DRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5).
Example: if DRA1/0 = 00 and ALEW = 0, then V7 = 2 – (0.5 +0.5) = 1.
V8) This variable represents the programmed width of the WRL and/or WRH pulse as determined by the WM1 bit in the BTRL register.
V8 = 1 if WM1 = 0, and 2 if WM1 = 1.
V9) This variable represents the programmed address setup time for a write as determined by the data write cycle duration (defined by
DW1 and DW0 or the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in the BTRL register, and the value of V8.
– For a bus cycle with an ALE, V9 = the total bus write cycle duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 = 10, and
5 if DWA1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8) minus the number of clocks used by data
hold time (0 if WM0 = 0 and 1 if WM0 = 1).
Example: If DWA1/0 = 10, WM0 = 1, and WM1 = 1, then V9 = 4 – 1 – 2 = 1.
– For a bus cycle with no ALE, V9 = the total bus cycle duration (2 if DW1/0 = 00, 3 if DW1/0 = 01, 4 if DW1/0 = 10, and
5 if DW1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data
hold time (0 if WMo = 0 and 1 if WM0 = 1).
Example: If DW1/0 = 11, WM0 = 1, and WM1 = 0, then V9 = 5 – 1 – 1 = 3.
V10) This variable represents the length of a bus strobe for calculation of WAIT set-up and hold times. The strobe may be RD (for data
read cycles), WRL and/or WRH (for data write cycles), or PSEN (for code read cycles), depending on the type of bus cycle being
widened by WAIT. V10 = 2 for WAIT associated with a code read cycle using PSEN. V10 = V8 for a data write cycle using WRL
and/or WRH. V10 = V7 – 1 for a data read cycle using RD. This means that a single clock data read cycle cannot be stretched using
WAIT. If WAIT is used to vary the duration of data read cycles, the RD strobe width must be set to be at least two clocks in duration.
Also see Note 4.
V11)
This variable represents the programmed write hold time as determined by the WM0 bit in the BTRL register. V11 0 if the WM0 bit = 0,
and 1 if the WM0 bit = 1.
V12) this variable represents the programmed period between the end of the ALE pulse and the beginning of the WRL and/or WRH pulse
as determined by the data write cycle duration (defined by the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in the BTRL
register, and the values of V1 and V8. V12 = the total bus cycle duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 = 10, and 5
if DWA1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold
time (0 if WM0 = 0 and 1 if WM0 = 1), minus the width of the ALE pulse (V1).
Example: If SWA1/0 = 11, WM0 = 1, WM1 = 0, and ALEW = 1, then V12 = 5 – 1 – 1 – 1.5 = 1.5.
V13) This variable represents the programmed data setup time for a write as determined by the data write cycle duration (defined by DW1
and DW0 or the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in the BTRL register, and the values of V1 and V8.
– For a bus cycle with an ALE, V13 = the total bus cycle duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 = 10, and
5 if DWA1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by
data hold time (0 if WM0 = 0 and 1 if WM0 = 1), minus the number of clocks used by ALE (V1 + 0.5).
Example: If DWA1/0 = 11, WM0 = 1, WM1 = 1, and ALEW = 0, then V13 = 5 – 1 – 2 – 1 = 1.
– For a bus cycle with no ALE, V13 = the total bus cycle duration (2 if DW1/0 = 00, 3 if DW1/0 = 01, 4 if DW1/0 = 10, and
5 if DW1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by
data hold time (0 if WM0 = 0 and 1 if WM0 = 1).
Example: If DW1/0 = 01, WM0 = 1, and WM1 = 0, then V13 = 3 – 1 – 1 = 1.
3. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA User Guide section on the External
Bus for details.
4. When code is being fetched for execution on the external bus, a burst mode fetch is used that dows not have PSEN edges in every fetch
cycle. This would be A3–A0 for an 8-bit bus, and A3–A1 for a 16-bit bus. Also, a 16-bit read operation conducted on an 8-bit wide bus
similarly does not include two separate RD strobes. So, a rising edge on the low order address line (A0) must be used to trigger a WAIT in
the second half of such a cycle.
5. This parameter is provided for peripherals that have the data clocked in on the falling edge of the WR strobe. This is not usually the case
and in most applications this parameter is not used.
6. Please note that the XA-S3 requires that extended data bus hold time (WM0 = 1) to be used with external bus write cycles.
7. Applies only to an external clock source, not when a crystal is connected to the XTAL1 and XTAL2 pins.
8. WAIT should not change between these times.
V7)
2013 Sep 04
42
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
AC WAVEFORMS
CLKOUT
tCHLH
tCLLL
tCHPL
tCHPH
tLHLL
ALE
tCHAX
tCHAV
tPHIZ
tCHIZ
tPLPH
tLLPL
PSEN
tAVLL
Multiplexed
Address and Data
tIVCH
tLLAX
tPLIV
A4–A11 or A4–A23
tCHIX
tPHIX
INSTR IN*
tIXUA
tAVIVA
Unmultiplexed
Address
A0 or A1–A3, A12–A23
*INSTR IN is either D0–D7 or D0–D15, depending on the bus width (8 or 16 bits).
SU00943A
Figure 26. External Program Memory Read Cycle (ALE Cycle)
PSEN
Multiplexed
Address and Data
INSTR IN*
tAVIVB
Unmultiplexed
Address
A0 or A1–A3, A12–A23
*INSTR IN is either D0–D7 or D0–D15, depending on the bus width (8 or 16 bits).
Figure 27. External Program Memory Read Cycle (Non-ALE Cycle)
2013 Sep 04
43
SU00949
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
CLKOUT
tCHRL
tCHRH
tLHLL
ALE
tRHDZ
tCHDZ
tRLRH
tLLRL
RD
tAVLL
Multiplexed
Address and Data
tDVCH
tLLAX
tRLDV
A4–A11 or A4–A23
tCHDX
tRHDX
DATA IN*
tDXUA
tAVDVA
Unmultiplexed
Address
A0 or A1–A3, A12–A23
*DATA IN is either D0–D7 or D0–D15, depending on the bus width (8 or 16 bits).
SU00944
Figure 28. External Data Memory Read Cycle (ALE Cycle)
RD
Multiplexed
Address and Data
D0–D7
tAVDVB
Unmultiplexed
Address
A0–A3, A12–A23
SU00950A
Figure 29. External Data Memory Read Cycle (Non-ALE Cycle)
2013 Sep 04
44
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
CLKOUT
tCHWL
tCHWH
tCHQZ
ALE
tLLWL
tWLWH
tCHQX
tWHQX
WR
tAVLL
Multiplexed
Address and Data
tQVWX
tLLAX
tQVCH
A4–A11 or A4–A23
DATA OUT*
tUAWH
tAVWL
Unmultiplexed
Address
A0 or A1–A3, A12–A23
*DATA OUT is either D0–D7 or D0–D15, depending on the bus width (8 or 16 bits).
SU00945
Figure 30. External Data Memory Write Cycle
XTAL1
tCRAR
ALE
ADDRESS BUS
WAIT
BUS STROBE
(WRL, WRH,
RD, OR PSEN)
tCHWTH
tCHWTL
tWTH
(The dashed line shows the strobe without WAIT.)
tWTL
SU01068
Figure 31. WAIT Signal Timing
2013 Sep 04
45
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
VDD–0.5
0.7VDD
0.2VDD–0.1
0.45V
tCHCL
tCHCX
tCLCH
tCLCX
tC
SU00842
Figure 32. External Clock Drive
VDD–0.5
0.2VDD+0.9
0.2VDD–0.1
0.45V
NOTE:
AC inputs during testing are driven at VDD –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at the 50% point of transitions.
SU00703A
Figure 33. AC Testing Input/Output
VLOAD+0.1V
VLOAD
VOH–0.1V
TIMING
REFERENCE
POINTS
VLOAD–0.1V
VOL+0.1V
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL ≥ ±20mA.
SU00011
Figure 34. Float Waveform
VDD
RST
VDD
VDD
VDD
VDD
RST
EA
EA
(NC)
XTAL2
(NC)
XTAL2
CLOCK SIGNAL
XTAL1
CLOCK SIGNAL
XTAL1
VSS
VSS
SU00591B
SU00590B
Figure 35. IDD Test Condition, Active Mode
All other pins are disconnected
2013 Sep 04
Figure 36. IDD Test Condition, Idle Mode
All other pins are disconnected
46
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
90
Max. IDD (Active)
80
70
mA
60
Typical IDD (Active)
50
40
Max. IDD (Idle)
30
Typical IDD (Idle)
20
10
0
0
5
10
15
20
25
Frequency (MHz)
SU01228
Figure 37. IDD vs. Frequency
Valid only within frequency specification of the device under test.
VDD–0.5
0.7VDD
0.2VDD–0.1
0.45V
tCHCL
tCHCX
tCLCH
tCLCX
tCL
SU00608A
Figure 38. Clock Signal Waveform for IDD Tests in Active and Idle Modes
tCLCH = tCHCL = 5 ns
VDD
VDD
VDD
RST
EA
(NC)
XTAL2
XTAL1
VSS
SU00585A
Figure 39. IDD Test Condition, Power Down Mode
All other pins are disconnected. VDD=2 V to 5.5 V
2013 Sep 04
47
30
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
EPROM CHARACTERISTICS
Security Bits
The XA-S3 is programmed by using a modified Improved
Quick-Pulse Programming algorithm. This algorithm is essentially
the same as that used by 80C51 family EPROM parts. However
different pins are used for many programming functions.
With none of the security bits programmed the code in the program
memory can be verified. When only security bit 1 is programmed,
MOVC instructions executed from external program memory are
disabled from fetching code bytes from the internal memory. All
further programming of the EPROM is disabled. When security bits
1 and 2 are programmed, in addition to the above, verify mode is
disabled. When all three security bits are programmed, all of the
conditions above apply and all external program memory execution
is disabled. (See Table 6.)
The XA-S3 contains three signature bytes that can be read and
used by an EPROM programming system to identify the device. The
signature bytes identify the device as an XA-S3 manufactured by
Philips.
Table 6. Program Security Bits
PROGRAM LOCK BITS
SB1
SB2
SB3
PROTECTION DESCRIPTION
1
U
U
U
No Program Security features enabled.
2
P
U
U
MOVC instructions executed from external program memory are disabled from fetching code bytes
from internal memory and further programming of the EPROM is disabled.
3
P
P
U
Same as 2, also verify is disabled.
4
P
P
P
Same as 3, external execution is disabled. Internal data RAM is not accessible.
NOTES:
1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.
ROM CODE SUBMISSION
When submitting ROM code for the XA-S3, the following must be specified:
1. 32k byte user ROM data
2. ROM security bits.
ADDRESS
CONTENT
BIT(S)
COMMENT
0000H to 7FFFH
DATA
7:0
User ROM Data
8020H
SEC
0
ROM Security Bit 1
8020H
SEC
1
ROM Security Bit 2
0 = enable security
1 = disable security
8020H
SEC
3
ROM Security Bit 3
0 = enable security
1 = disable security
Trademark phrase of Intel Corporation.
2013 Sep 04
48
NXP Semiconductors
Product specification
XA 16-bit microcontroller
XA-S3
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V),
I 2C, 2 UARTs, 16 MB address range
PLCC68: plastic leaded chip carrier; 68 leads
SOT188-2
eD
eE
y
X
60
A
44
43 Z E
61
bp
b1
w M
68
1
E
HE
pin 1 index
A
e
A4 A1
(A 3)
β
9
Lp
27
k
detail X
10
26
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm dimensions are derived from the original inch dimensions)
A4
A1
UNIT A
D(1) E(1)
e
HD
A3
eD
eE
bp b1
max.
min.
4.57
4.19
mm
inches
0.51
0.180
0.02
0.165
0.53
0.33
0.81
0.66
HE
k
24.33 24.33
23.62 23.62 25.27 25.27 1.22
1.27
24.13 24.13
22.61 22.61 25.02 25.02 1.07
0.25
3.3
0.01
0.021 0.032 0.958 0.958
0.05
0.13
0.013 0.026 0.950 0.950
0.93
0.89
0.93
0.89
Lp
v
w
y
1.44
1.02
0.18
0.18
0.1
ZD(1) ZE(1)
max. max.
2.16
β
2.16
45 o
0.995 0.995 0.048 0.057
0.007 0.007 0.004 0.085 0.085
0.985 0.985 0.042 0.040
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT188-2
112E10
MS-018
EDR-7319
2013 Sep 04
49
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
01-11-14
NXP Semiconductors
Product specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
2013 Sep 04
50
XA-S3
SOT315-1
NXP Semiconductors
Product specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
NOTES
2013 Sep 04
51
XA-S3
NXP Semiconductors
Product specification
XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit
A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs,16 MB address range
XA-S3
DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Qualification
This document contains data from the preliminary specification.
Product data sheet
Production
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
property or environmental damage. NXP Semiconductors
and its suppliers accept no liability for inclusion and/or use
of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
DISCLAIMERS
Limited warranty and liability Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information. NXP Semiconductors takes no responsibility
for the content in this document if provided by an
information source outside of NXP Semiconductors.
Applications Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Right to make changes NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
2013 Sep 04
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NXP Semiconductors
Product specification
XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit
A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs,16 MB address range
Limiting values Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product claims resulting from customer design and use of
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
Semiconductors’ product specifications.
Translations A non-English (translated) version of a
document is for reference only. The English version shall
prevail in case of any discrepancy between the translated
and English versions.
Terms and conditions of commercial sale NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an
individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
TRADEMARKS
Notice: All referenced brands, product names, service
names and trademarks are the property of their respective
owners.
I2C-bus logo is a trademark of NXP B.V.
No offer to sell or license Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
Quick reference data The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
2013 Sep 04
XA-S3
53
NXP Semiconductors
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors.
Changes to content include: Corrected SOT188-3 to SOT188-2; changed data sheet specification to Product;
updated legal definitions and disclaimers.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: salesaddresses@nxp.com
© NXP B.V. 2013
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R05/10/pp54
Date of release: 2013 Sep 04
Document order number:
9397 750 07816
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