Freescale Semiconductor, Inc.
Data Sheet
Document Number: MC9S08SG32
Rev. 9, 04/2015
MC9S08SG32 with Addenda
Covers: MC9S08SG32 and
MC9S08SG16
Rev. 9 of the MC9S08SG32 data sheet (covering MC9S08SG32 and MC9S08SG16) has three parts:
• The revision 2 addendum to revision 8.1 of the data sheet, immediately following this cover page.
• The revision 1 addendum to revision 8 of the data sheet.
• Revision 8 of the data sheet, following the addendums. The changes described in the addendums have
not been implemented in the specified pages.
© 2015 Freescale Semiconductor, Inc. All rights reserved.
Freescale Semiconductor, Inc.
Data Sheet Addendum
Document Number: MC9S08SG32AD
Rev. 2, 04/2015
Addendum to Rev. 8.1 of the
MC9S08SG32
Covers: MC9S08SG32 and
MC9S08SG16
This addendum identifies changes to Rev. 8.1 of the MC9S08SG32 data sheet (covering MC9S08SG32
and MC9S08SG16). The changes described in this addendum have not been implemented in the
specified pages.
1
Update to the “Nonvolatile Register Summary” table
for NVFTRIM and NVOPT
Location:
Table 4-4. Nonvolatile Register Summary, Page 47
For the NVFTRIM and NVOPT registers in Table 4-4, “Nonvolatile Register Summary,” all reserved bits
should be marked as “—” (not “0”).
2
Update to the “Instruction Set Summary” table for BRA
and BRN
Location:
Table 7-2. Instruction Set Summary (Sheet 3 of 9), Page 106
In Table 7-2, “Instruction Set Summary,” remove “(if I = 1)” from the BRA instruction and remove “(if
I = 0)” from the BRN instruction. The BRA and BRN instructions do not depend on the I bit.
© 2015 Freescale Semiconductor, Inc. All rights reserved.
Freescale Semiconductor
MC9S08SG32 DataSheet
Addendum
by: Microcontroller Solutions Group
This is the MC9S08SG32 DataSheet set consisting of the following files:
• MC9S08SG32 DataSheet Addendum, Rev 1
• MC9S08SG32 DataSheet, Rev 8
© Freescale Semiconductor, Inc., 2012. All rights reserved.
MC9S08SG32
Rev. 8.1, 03/2012
Freescale Semiconductor
Addendum
MC9S08SG32AD
Rev. 1, 02/2012
MC9S08SG32 Data Sheet
Addendum
by: Microcontroller Solutions Group
This errata document describes updates to the
MC9S08SG32 Data Sheet, order number MC9S08SG32.
For convenience, the addenda items are grouped by
revision. Please check our website at
http://www.freescale.com for the latest updates.
© Freescale Semiconductor, Inc., 2012. All rights reserved.
Table of Contents
1
2
Addendum for Revision 8.0. . . . . . . . . . . . . . . . . . 2
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Addendum for Revision 8.0
1
Addendum for Revision 8.0
Table 1. MC9S08SG32 Rev. 1 Addendum
Location
Description
Chapter “Memory”/ Section
In Figure 4-1. MC9S08SG32/MC9S08SG16 Memory Map for device MC9S08SG16 change the
“MC9S08SG32 Series
value of “Unimplemented Bytes” from “26,538” to “26,528”.
Memory Map”/Figure 4-1.
0x0000
0x0000
MC9S08SG32/MC9S08SG16
DIRECT PAGE REGISTERS
DIRECT PAGE REGISTERS
0x007F
0x007F
Memory Map/Page 39
0x0080
0x0080
RAM
1024 BYTES
RAM
1024 BYTES
0x047F
0x0480
0x17FF
0x1800
UNIMPLEMENTED
4992 BYTES
0x047F
0x0480
0x17FF
0x1800
HIGH PAGE REGISTERS
HIGH PAGE REGISTERS
0x185F
0x1860
0x185F
0x1860
UNIMPLEMENTED
0x7FFF
0x8000
UNIMPLEMENTED
4992 BYTES
26,528 BYTES
UNIMPLEMENTED
0x7FFF
0x8000
26,528 BYTES
UNIMPLEMENTED
16,384 BYTES
FLASH
32768 BYTES
0xBFFF
0xC000
FLASH
16,384 BYTES
0xFFFF
0xFFFF
MC9S08SG32
MC9S08SG16
MC9S08SG32 Data Sheet Addendum, Rev. 1
2
Freescale Semiconductor
Addendum for Revision 8.0
Table 1. MC9S08SG32 Rev. 1 Addendum
Location
Description
Chapter “Electrical
Update Table A-3. Thermal Characteristics as follows:
Characteristics”/Section
• —Change the value for row “Thermal resistance,Single-layer board/28-pin TSSOP/Airflow
“Thermal
@200ft/min.” from 71 to 72 C/W
Characteristics”/Table A-3.
—Change the value for 16-pin TSSOP/Thermalresistance
Thermal Characteristics/Page
1.Single layer board / Airflow @ 200ft/min. from 108 to 113 C/W.
293
2.Four layer board / Airflow @ 200ft/min. from 78 to 84 C/W.
• Update parameter 4 of Table “A-3.Thermal Characteristics” .
Chapter “Electrical
Characteristics”/Section “DC
Characteristics”/Table A-6. DC
Characteristics/Page 298
In the Table “DC Characteristics” add note 11 and 12 for parameter #18.
Note 11: Device functionality is guaranteed between the LVD threshold VLVD0 and VDD Min.
When VDD is below the minimum operating voltage (VDD Min), the analog parameters for the
IO pins, ACMP and ADC, are not guaranteed to meet data sheet performance parameters.
Note 12: In addition to LVD, it is recommended to also use the LVW feature. LVW can trigger an
interrupt and be used as an indicator to warn that the VDD is dropping,so that the software can
take actions accordingly before the VDD drops below VDD Min.
MC9S08SG32 Data Sheet Addendum, Rev. 1
Freescale Semiconductor
3
Revision History
Table 1. MC9S08SG32 Rev. 1 Addendum
Location
Description
Chapter “Electrical
Characteristics”/Section
“Flash Specifications”/Table
“A-16. Flash
Characteristics”/Page 323
2
In Table A-16 Flash Characteristics/row 9/column "Characteristic", change the temperature
parameter names as follows:
Standard: -40oC to +125oC
HT: -40oC to +150oC
T = 25oC
Revision History
Table 2 provides a revision history for this document.
Table 2. Revision History Table
Rev. Number
1.0
Substantive Changes
• Initial release.
Changes done in Chapter “Electrical Characteristics”.
Date of Release
02/2012
MC9S08SG32 Data Sheet Addendum, Rev. 1
4
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reserved.
MC9S08SG32AD
Rev. 1
02/2012
MC9S08SG32
MC9S08SG16
Data Sheet
Now Includes High-Temperature (up to 150 °C) Devices!
HCS08
Microcontrollers
MC9S08SG32
Rev. 8
5/2010
freescale.com
MC9S08SG32 Series Features
8-Bit HCS08 Central Processor Unit (CPU)
• 40-MHz HCS08 CPU (central processor unit)
• 36-MHz HCS08 CPU for temperatures greater
than 125 °C
• HC08 instruction set with added BGND instruction
• Support for up to 32 interrupt/reset sources
On-Chip Memory
• FLASH read/program/erase over full operating
voltage and temperature from –40 up to 150 °C
• Random-access memory (RAM)
• Security circuitry to prevent unauthorized access
to RAM and FLASH contents
Power-Saving Modes
• Two very low power stop modes
• Reduced power wait mode
• Very low power real time counter for use in run,
wait, and stop
Clock Source Options
• Oscillator (XOSC) — Loop-control Pierce
oscillator; Crystal or ceramic resonator range of
31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz
• Internal Clock Source (ICS) — Internal clock
source module containing a frequency-locked loop
(FLL) controlled by internal or external reference;
precision trimming of internal reference allows
0.2% resolution and:
• 1.5% deviation over temperature –40 to 125 °C
• 3% deviation for temperature > 125 °C
• ICS supports bus frequencies from 2 MHz to
20 MHz
System Protection
• Watchdog computer operating properly (COP)
reset with option to run from dedicated 1-kHz
internal clock source or bus clock
• Low-voltage detection with reset or interrupt;
selectable trip points
• Illegal opcode detection with reset
• Illegal address detection with reset
• FLASH block protect
Development Support
• Single-wire background debug interface
• Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
• On-chip, in-circuit emulation (ICE) debug module
containing two comparators and 9 trigger modes.
Eight-deep FIFO for storing change-of-flow
address and event-only data. Debug module
supports both tag and force breakpoints
Peripherals
• ADC — 16-channel, 10-bit resolution, 2.5 μs
conversion time, automatic compare function,
temperature sensor, internal bandgap reference
channel; runs in stop3
• ACMP — Analog comparators with selectable
interrupt on rising, falling, or either edge of
comparator output; compare option to fixed
internal bandgap reference voltage; output can be
optionally routed to TPM module; runs in stop3
• SCI — Full duplex non-return to zero (NRZ); LIN
master extended break generation; LIN slave
extended break detection; wake up on active edge
• SPI — Full-duplex or single-wire bidirectional;
Double-buffered transmit and receive; Master or
Slave mode; MSB-first or LSB-first shifting
• IIC — Up to 100 kbps with maximum bus loading;
Multi-master operation; Programmable slave
address; Interrupt driven byte-by-byte data
transfer; supports broadcast mode and 10-bit
addressing
• MTIM — 8-bit modulo counter with 8-bit prescaler
and overflow interrupt
• TPMx — Two 2-channel timer pwm modules
(TPM1, TPM2); Selectable input capture, output
compare, or buffered edge- or center-aligned
PWM on each channel
• RTC — (Real-time counter) 8-bit modulus counter
with binary or decimal based prescaler; External
clock source for precise time base, time-of-day,
calendar or task scheduling functions; Free
running on-chip low power oscillator (1 kHz) for
cyclic wake-up without external components, runs
in all MCU modes
Input/Output
• 22 general purpose I/O pins (GPIOs)
• 8 interrupt pins with selectable polarity
• Ganged output option for PTB[5:2] and PTC[3:0];
allows single write to change state of multiple pins
• Hysteresis and configurable pull up device on all
input pins; Configurable slew rate and drive
strength on all output pins
Package Options
• 28-TSSOP, 20-TSSOP, 16-TSSOP (20-pin
package options not available on high-temperature
rated devices).
MC9S08SG32 Data Sheet
Covers MC9S08SG32
MC9S08SG16
MC9S08SG32
Rev. 8
5/2010
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2007-2010. All rights reserved.
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
Number
Revision
Date
1
6/2007
Updated the TPM module, incorporated minor revisions for the Tj, PTxSE slew
rate, FPROT and Appendix B packaging information. -SAMPLES DRAFT-
2
10/2007
Qualify Draft includes updates to TPM module and the Electricals appendix.
Also, revised the order numbering information.
3
5/2008
Updated some electricals and made some minor grammatical/formatting revisions. Corrected the SPI block module version. Removed incorrect ADC temperature sensor value from the Features section. Updated the package information
with a special mask set identifier.
4
5/2008
Added the EMC Radiated Emissions data. Removed the Susceptibility Data.
Updated the Corporate addresses on the back cover.
5
03/2009
Added the High Temperature Device Specifications and updated the charts.
04/2009
Updated ADC characteristics for Temp Sensor Slope to be a range of
25 C–150 C
, added Control Timing table row 2 to separate standard characteristics from the AEC Grade 0 characteristics, and included the text, “AEC Grade 0”
to the text of footnote 3 for Table B-1 Device Numbering System. Added notes to
the ADC chapter specifying that, for this device, there are only 16 analog input
pins and consequently no APCTL3 register. Updated the Literature Request
information on the back cover.
10/2009
Revised Table A-6 DC Characteristics, Row 24 Bandgap Voltage Reference for
AEC Grade 0 from 1.21V to 1.22 V. Removed AEC Grade 0 (red diamond) from
the Table A-9 ICS Frequency Specifications, Row 9 Total deviation of trimmed
DCO output frequency over voltage and temperature so that it is not listed for
AEC Grade 0.
6
7
Description of Changes
MC9S08SG32 Data Sheet, Rev. 8
6
Freescale Semiconductor
Revision
Number
8
Revision
Date
5/2010
Description of Changes
• In the A.9 ICS Characteristic table, changed row 9 parameter classification
from a D to a P to indicate that these parameters are guaranteed during
production testing on each individual device.
• In the A.16 Flash Charateristic table, added the AEC temperature range to
row 9.
• Revised Figure 2-1 so that the RESET pin shows the overbar.
© Freescale Semiconductor, Inc., 2007-2010. All rights reserved.
This product incorporates SuperFlash® Technology licensed from SST.
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
7
MC9S08SG32 Data Sheet, Rev. 8
8
Freescale Semiconductor
Contents
Section Number
Title
Page
Chapter 1
Device Overview ...................................................................... 21
Chapter 2
Pins and Connections ............................................................. 25
Chapter 3
Modes of Operation ................................................................. 33
Chapter 4
Memory ..................................................................................... 39
Chapter 5
Resets, Interrupts, and General System Control.................. 61
Chapter 6
Parallel Input/Output Control.................................................. 77
Chapter 7
Central Processor Unit (S08CPUV3) ...................................... 95
Chapter 8
Analog Comparator 5-V (S08ACMPV3)................................ 115
Chapter 9
Analog-to-Digital Converter (S08ADC10V1)........................ 123
Chapter 10
Inter-Integrated Circuit (S08IICV2) ....................................... 151
Chapter 11
Internal Clock Source (S08ICSV2)........................................ 171
Chapter 12
Modulo Timer (S08MTIMV1).................................................. 185
Chapter 13
Real-Time Counter (S08RTCV1) ........................................... 195
Chapter 14
Serial Communications Interface (S08SCIV4)..................... 205
Chapter 15
Serial Peripheral Interface (S08SPIV3) ................................ 225
Chapter 16
Timer Pulse-Width Modulator (S08TPMV3) ......................... 241
Chapter 17
Development Support ........................................................... 269
Appendix A
Electrical Characteristics...................................................... 291
Appendix B
Ordering Information and Mechanical Drawings................ 325
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
9
Contents
Section Number
Title
Page
Chapter 1
Device Overview
1.1
1.2
1.3
Devices in the MC9S08SG32 Series............................................................................................... 21
MCU Block Diagram ...................................................................................................................... 22
System Clock Distribution .............................................................................................................. 24
Chapter 2
Pins and Connections
2.1
2.2
Device Pin Assignment ................................................................................................................... 25
Recommended System Connections ............................................................................................... 27
2.2.1 Power ................................................................................................................................ 27
2.2.2 Oscillator (XOSC) ............................................................................................................ 28
2.2.3 RESET .............................................................................................................................. 28
2.2.4 Background / Mode Select (BKGD/MS).......................................................................... 29
2.2.5 General-Purpose I/O and Peripheral Ports........................................................................ 29
Chapter 3
Modes of Operation
3.1
3.2
3.3
3.4
3.5
3.6
Introduction ..................................................................................................................................... 33
Features ........................................................................................................................................... 33
Run Mode........................................................................................................................................ 33
Active Background Mode................................................................................................................ 33
Wait Mode ....................................................................................................................................... 34
Stop Modes...................................................................................................................................... 34
3.6.1 Stop3 Mode....................................................................................................................... 35
3.6.2 Stop2 Mode....................................................................................................................... 36
3.6.3 On-Chip Peripheral Modules in Stop Modes.................................................................... 36
Chapter 4
Memory
4.1
4.2
4.3
4.4
4.5
MC9S08SG32 Series Memory Map ............................................................................................... 39
Reset and Interrupt Vector Assignments ......................................................................................... 40
Register Addresses and Bit Assignments........................................................................................ 41
RAM................................................................................................................................................ 48
FLASH ............................................................................................................................................ 48
4.5.1 Features ............................................................................................................................. 49
4.5.2 Program and Erase Times ................................................................................................. 49
4.5.3 Program and Erase Command Execution ......................................................................... 50
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
11
Section Number
4.6
4.7
Title
Page
4.5.4 Burst Program Execution.................................................................................................. 51
4.5.5 Access Errors .................................................................................................................... 53
4.5.6 FLASH Block Protection.................................................................................................. 53
4.5.7 Vector Redirection ............................................................................................................ 54
Security............................................................................................................................................ 54
FLASH Registers and Control Bits ................................................................................................. 56
4.7.1 FLASH Clock Divider Register (FCDIV) ........................................................................ 56
4.7.2 FLASH Options Register (FOPT and NVOPT)................................................................ 57
4.7.3 FLASH Configuration Register (FCNFG)........................................................................ 58
4.7.4 FLASH Protection Register (FPROT and NVPROT)....................................................... 58
4.7.5 FLASH Status Register (FSTAT)...................................................................................... 59
4.7.6 FLASH Command Register (FCMD)............................................................................... 60
Chapter 5
Resets, Interrupts, and General System Control
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Introduction ..................................................................................................................................... 61
Features ........................................................................................................................................... 61
MCU Reset...................................................................................................................................... 61
Computer Operating Properly (COP) Watchdog............................................................................. 62
Interrupts ......................................................................................................................................... 63
5.5.1 Interrupt Stack Frame ....................................................................................................... 64
5.5.2 Interrupt Vectors, Sources, and Local Masks.................................................................... 65
Low-Voltage Detect (LVD) System ................................................................................................ 67
5.6.1 Power-On Reset Operation ............................................................................................... 67
5.6.2 Low-Voltage Detection (LVD) Reset Operation............................................................... 67
5.6.3 Low-Voltage Warning (LVW) Interrupt Operation........................................................... 67
Reset, Interrupt, and System Control Registers and Control Bits ................................................... 67
5.7.1 System Reset Status Register (SRS) ................................................................................. 68
5.7.2 System Background Debug Force Reset Register (SBDFR) ............................................ 69
5.7.3 System Options Register 1 (SOPT1) ................................................................................ 70
5.7.4 System Options Register 2 (SOPT2) ................................................................................ 71
5.7.5 System Device Identification Register (SDIDH, SDIDL) ................................................ 72
5.7.6 System Power Management Status and Control 1 Register (SPMSC1) ........................... 73
5.7.7 System Power Management Status and Control 2 Register (SPMSC2) ........................... 74
Chapter 6
Parallel Input/Output Control
6.1
6.2
6.3
6.4
Port Data and Data Direction .......................................................................................................... 77
Pull-up, Slew Rate, and Drive Strength........................................................................................... 78
Ganged Output ................................................................................................................................ 79
Pin Interrupts ................................................................................................................................... 80
6.4.1 Edge-Only Sensitivity ....................................................................................................... 80
MC9S08SG32 Data Sheet, Rev. 8
12
Freescale Semiconductor
Section Number
6.5
6.6
Title
Page
6.4.2 Edge and Level Sensitivity................................................................................................ 81
6.4.3 Pull-up/Pull-down Resistors ............................................................................................. 81
6.4.4 Pin Interrupt Initialization................................................................................................. 81
Pin Behavior in Stop Modes............................................................................................................ 81
Parallel I/O and Pin Control Registers ............................................................................................ 82
6.6.1 Port A Registers ................................................................................................................ 83
6.6.2 Port B Registers ................................................................................................................ 87
6.6.3 Port C Registers ................................................................................................................ 91
Chapter 7
Central Processor Unit (S08CPUV3)
7.1
7.2
7.3
7.4
7.5
Introduction ..................................................................................................................................... 95
7.1.1 Features ............................................................................................................................. 95
Programmer’s Model and CPU Registers ....................................................................................... 96
7.2.1 Accumulator (A) ............................................................................................................... 96
7.2.2 Index Register (H:X)......................................................................................................... 96
7.2.3 Stack Pointer (SP) ............................................................................................................. 97
7.2.4 Program Counter (PC) ...................................................................................................... 97
7.2.5 Condition Code Register (CCR) ....................................................................................... 97
Addressing Modes........................................................................................................................... 99
7.3.1 Inherent Addressing Mode (INH)..................................................................................... 99
7.3.2 Relative Addressing Mode (REL)..................................................................................... 99
7.3.3 Immediate Addressing Mode (IMM)................................................................................ 99
7.3.4 Direct Addressing Mode (DIR) ........................................................................................ 99
7.3.5 Extended Addressing Mode (EXT) ................................................................................ 100
7.3.6 Indexed Addressing Mode .............................................................................................. 100
Special Operations......................................................................................................................... 101
7.4.1 Reset Sequence ............................................................................................................... 101
7.4.2 Interrupt Sequence .......................................................................................................... 101
7.4.3 Wait Mode Operation...................................................................................................... 102
7.4.4 Stop Mode Operation...................................................................................................... 102
7.4.5 BGND Instruction........................................................................................................... 103
HCS08 Instruction Set Summary .................................................................................................. 104
Chapter 8
Analog Comparator 5-V (S08ACMPV3)
8.1
8.2
8.3
8.4
Introduction ................................................................................................................................... 115
8.1.1 ACMP Configuration Information .................................................................................. 115
8.1.2 ACMP/TPM Configuration Information......................................................................... 115
Features ......................................................................................................................................... 117
Modes of Operation....................................................................................................................... 117
Block Diagram .............................................................................................................................. 117
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
13
Section Number
8.5
8.6
8.7
Title
Page
External Signal Description .......................................................................................................... 119
Memory Map ................................................................................................................................ 119
8.6.1 Register Descriptions ...................................................................................................... 119
Functional Description .................................................................................................................. 121
Chapter 9
Analog-to-Digital Converter (S08ADC10V1)
9.1
9.2
9.3
9.4
9.5
Introduction ................................................................................................................................... 123
9.1.1 Channel Assignments...................................................................................................... 123
9.1.2 Analog Power and Ground Signal Names ...................................................................... 124
9.1.3 Alternate Clock ............................................................................................................... 124
9.1.4 Hardware Trigger ............................................................................................................ 124
9.1.5 Temperature Sensor ........................................................................................................ 124
9.1.6 Features ........................................................................................................................... 127
9.1.7 ADC Module Block Diagram ......................................................................................... 127
External Signal Description .......................................................................................................... 128
9.2.1 Analog Power (VDDA) .................................................................................................... 129
9.2.2 Analog Ground (VSSA) ................................................................................................... 129
9.2.3 Voltage Reference High (VREFH) ................................................................................... 129
9.2.4 Voltage Reference Low (VREFL)..................................................................................... 129
9.2.5 Analog Channel Inputs (ADx) ........................................................................................ 129
Register Definition ........................................................................................................................ 129
9.3.1 Status and Control Register 1 (ADCSC1) ...................................................................... 130
9.3.2 Status and Control Register 2 (ADCSC2) ...................................................................... 131
9.3.3 Data Result High Register (ADCRH)............................................................................. 132
9.3.4 Data Result Low Register (ADCRL) .............................................................................. 132
9.3.5 Compare Value High Register (ADCCVH).................................................................... 133
9.3.6 Compare Value Low Register (ADCCVL) ..................................................................... 133
9.3.7 Configuration Register (ADCCFG) ................................................................................ 133
9.3.8 Pin Control 1 Register (APCTL1) .................................................................................. 135
9.3.9 Pin Control 2 Register (APCTL2) .................................................................................. 136
9.3.10 Pin Control 3 Register (APCTL3) .................................................................................. 137
Functional Description .................................................................................................................. 138
9.4.1 Clock Select and Divide Control .................................................................................... 138
9.4.2 Input Select and Pin Control ........................................................................................... 139
9.4.3 Hardware Trigger ............................................................................................................ 139
9.4.4 Conversion Control ......................................................................................................... 139
9.4.5 Automatic Compare Function......................................................................................... 142
9.4.6 MCU Wait Mode Operation............................................................................................ 143
9.4.7 MCU Stop3 Mode Operation.......................................................................................... 143
9.4.8 MCU Stop2 Mode Operation.......................................................................................... 144
Initialization Information .............................................................................................................. 144
MC9S08SG32 Data Sheet, Rev. 8
14
Freescale Semiconductor
Section Number
9.6
Title
Page
9.5.1 ADC Module Initialization Example ............................................................................. 144
Application Information................................................................................................................ 146
9.6.1 External Pins and Routing .............................................................................................. 146
9.6.2 Sources of Error .............................................................................................................. 148
Chapter 10
Inter-Integrated Circuit (S08IICV2)
10.1 Introduction ................................................................................................................................... 151
10.1.1 Module Configuration..................................................................................................... 151
10.1.2 Features ........................................................................................................................... 153
10.1.3 Modes of Operation ........................................................................................................ 153
10.1.4 Block Diagram ................................................................................................................ 154
10.2 External Signal Description .......................................................................................................... 154
10.2.1 SCL — Serial Clock Line ............................................................................................... 154
10.2.2 SDA — Serial Data Line ................................................................................................ 154
10.3 Register Definition ........................................................................................................................ 154
10.3.1 IIC Address Register (IICA) ........................................................................................... 155
10.3.2 IIC Frequency Divider Register (IICF)........................................................................... 155
10.3.3 IIC Control Register (IICC1) .......................................................................................... 158
10.3.4 IIC Status Register (IICS)............................................................................................... 159
10.3.5 IIC Data I/O Register (IICD) .......................................................................................... 160
10.3.6 IIC Control Register 2 (IICC2) ....................................................................................... 160
10.4 Functional Description .................................................................................................................. 161
10.4.1 IIC Protocol..................................................................................................................... 161
10.4.2 10-bit Address................................................................................................................. 165
10.4.3 General Call Address ...................................................................................................... 166
10.5 Resets ............................................................................................................................................ 166
10.6 Interrupts ....................................................................................................................................... 166
10.6.1 Byte Transfer Interrupt.................................................................................................... 166
10.6.2 Address Detect Interrupt ................................................................................................. 166
10.6.3 Arbitration Lost Interrupt................................................................................................ 166
10.7 Initialization/Application Information .......................................................................................... 168
Chapter 11
Internal Clock Source (S08ICSV2)
11.1 Introduction ................................................................................................................................... 171
11.1.1 Module Configuration..................................................................................................... 171
11.1.2 Features ........................................................................................................................... 173
11.1.3 Block Diagram ................................................................................................................ 173
11.1.4 Modes of Operation ........................................................................................................ 174
11.2 External Signal Description .......................................................................................................... 175
11.3 Register Definition ........................................................................................................................ 175
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
15
Section Number
Title
Page
11.3.1 ICS Control Register 1 (ICSC1) ..................................................................................... 176
11.3.2 ICS Control Register 2 (ICSC2) ..................................................................................... 177
11.3.3 ICS Trim Register (ICSTRM)......................................................................................... 178
11.3.4 ICS Status and Control (ICSSC)..................................................................................... 178
11.4 Functional Description .................................................................................................................. 179
11.4.1 Operational Modes.......................................................................................................... 179
11.4.2 Mode Switching .............................................................................................................. 181
11.4.3 Bus Frequency Divider ................................................................................................... 182
11.4.4 Low Power Bit Usage ..................................................................................................... 182
11.4.5 Internal Reference Clock ................................................................................................ 182
11.4.6 Optional External Reference Clock ................................................................................ 182
11.4.7 Fixed Frequency Clock ................................................................................................... 183
Chapter 12
Modulo Timer (S08MTIMV1)
12.1 Introduction ................................................................................................................................... 185
12.1.1 MTIM Configuration Information .................................................................................. 185
12.1.2 Features ........................................................................................................................... 187
12.1.3 Modes of Operation ........................................................................................................ 187
12.1.4 Block Diagram ................................................................................................................ 188
12.2 External Signal Description .......................................................................................................... 188
12.3 Register Definition ........................................................................................................................ 189
12.3.1 MTIM Status and Control Register (MTIMSC) ............................................................. 190
12.3.2 MTIM Clock Configuration Register (MTIMCLK) ....................................................... 191
12.3.3 MTIM Counter Register (MTIMCNT)........................................................................... 192
12.3.4 MTIM Modulo Register (MTIMMOD).......................................................................... 192
12.4 Functional Description .................................................................................................................. 193
12.4.1 MTIM Operation Example ............................................................................................. 194
Chapter 13
Real-Time Counter (S08RTCV1)
13.1 Introduction ................................................................................................................................... 195
13.1.1 Features ........................................................................................................................... 197
13.1.2 Modes of Operation ........................................................................................................ 197
13.1.3 Block Diagram ................................................................................................................ 198
13.2 External Signal Description .......................................................................................................... 198
13.3 Register Definition ........................................................................................................................ 198
13.3.1 RTC Status and Control Register (RTCSC).................................................................... 199
13.3.2 RTC Counter Register (RTCCNT).................................................................................. 200
13.3.3 RTC Modulo Register (RTCMOD) ................................................................................ 200
13.4 Functional Description .................................................................................................................. 200
13.4.1 RTC Operation Example................................................................................................. 201
MC9S08SG32 Data Sheet, Rev. 8
16
Freescale Semiconductor
Section Number
Title
Page
13.5 Initialization/Application Information .......................................................................................... 202
Chapter 14
Serial Communications Interface (S08SCIV4)
14.1 Introduction ................................................................................................................................... 205
14.1.1 Features ........................................................................................................................... 207
14.1.2 Modes of Operation ........................................................................................................ 207
14.1.3 Block Diagram ................................................................................................................ 208
14.2 Register Definition ........................................................................................................................ 210
14.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) .............................................................. 210
14.2.2 SCI Control Register 1 (SCIC1) ..................................................................................... 211
14.2.3 SCI Control Register 2 (SCIC2) ..................................................................................... 212
14.2.4 SCI Status Register 1 (SCIS1) ........................................................................................ 213
14.2.5 SCI Status Register 2 (SCIS2) ........................................................................................ 215
14.2.6 SCI Control Register 3 (SCIC3) ..................................................................................... 216
14.2.7 SCI Data Register (SCID)............................................................................................... 217
14.3 Functional Description .................................................................................................................. 217
14.3.1 Baud Rate Generation ..................................................................................................... 217
14.3.2 Transmitter Functional Description ................................................................................ 218
14.3.3 Receiver Functional Description..................................................................................... 219
14.3.4 Interrupts and Status Flags.............................................................................................. 221
14.3.5 Additional SCI Functions ............................................................................................... 222
Chapter 15
Serial Peripheral Interface (S08SPIV3)
15.1 Introduction ................................................................................................................................... 225
15.1.1 Features ........................................................................................................................... 227
15.1.2 Block Diagrams .............................................................................................................. 227
15.1.3 SPI Baud Rate Generation .............................................................................................. 229
15.2 External Signal Description .......................................................................................................... 230
15.2.1 SPSCK — SPI Serial Clock............................................................................................ 230
15.2.2 MOSI — Master Data Out, Slave Data In ...................................................................... 230
15.2.3 MISO — Master Data In, Slave Data Out ...................................................................... 230
15.2.4 SS — Slave Select........................................................................................................... 230
15.3 Modes of Operation....................................................................................................................... 231
15.3.1 SPI in Stop Modes .......................................................................................................... 231
15.4 Register Definition ........................................................................................................................ 231
15.4.1 SPI Control Register 1 (SPIC1) ...................................................................................... 231
15.4.2 SPI Control Register 2 (SPIC2) ...................................................................................... 232
15.4.3 SPI Baud Rate Register (SPIBR).................................................................................... 233
15.4.4 SPI Status Register (SPIS) .............................................................................................. 234
15.4.5 SPI Data Register (SPID)................................................................................................ 235
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
17
Section Number
Title
Page
15.5 Functional Description .................................................................................................................. 236
15.5.1 SPI Clock Formats .......................................................................................................... 236
15.5.2 SPI Interrupts .................................................................................................................. 239
15.5.3 Mode Fault Detection ..................................................................................................... 239
Chapter 16
Timer Pulse-Width Modulator (S08TPMV3)
16.1 Introduction ................................................................................................................................... 241
16.1.1 TPM Configuration Information ..................................................................................... 241
16.1.2 TPM Pin Repositioning .................................................................................................. 241
16.1.3 Features ........................................................................................................................... 243
16.1.4 Modes of Operation ........................................................................................................ 243
16.1.5 Block Diagram ................................................................................................................ 244
16.2 Signal Description ......................................................................................................................... 246
16.2.1 Detailed Signal Descriptions........................................................................................... 246
16.3 Register Definition ........................................................................................................................ 250
16.3.1 TPM Status and Control Register (TPMxSC) ................................................................ 250
16.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL).................................................... 251
16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL).................................... 252
16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) .......................................... 253
16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) .......................................... 254
16.4 Functional Description .................................................................................................................. 256
16.4.1 Counter............................................................................................................................ 256
16.4.2 Channel Mode Selection ................................................................................................. 258
16.5 Reset Overview ............................................................................................................................. 261
16.5.1 General............................................................................................................................ 261
16.5.2 Description of Reset Operation....................................................................................... 261
16.6 Interrupts ....................................................................................................................................... 261
16.6.1 General............................................................................................................................ 261
16.6.2 Description of Interrupt Operation.................................................................................. 262
16.7 The Differences from TPM v2 to TPM v3.................................................................................... 263
Chapter 17
Development Support
17.1 Introduction ................................................................................................................................... 269
17.1.1 Forcing Active Background ............................................................................................ 269
17.1.2 Features ........................................................................................................................... 270
17.2 Background Debug Controller (BDC) .......................................................................................... 270
17.2.1 BKGD Pin Description ................................................................................................... 271
17.2.2 Communication Details .................................................................................................. 272
17.2.3 BDC Commands ............................................................................................................. 276
17.2.4 BDC Hardware Breakpoint............................................................................................. 278
MC9S08SG32 Data Sheet, Rev. 8
18
Freescale Semiconductor
Section Number
Title
Page
17.3 On-Chip Debug System (DBG) .................................................................................................... 279
17.3.1 Comparators A and B...................................................................................................... 279
17.3.2 Bus Capture Information and FIFO Operation ............................................................... 279
17.3.3 Change-of-Flow Information .......................................................................................... 280
17.3.4 Tag vs. Force Breakpoints and Triggers ......................................................................... 280
17.3.5 Trigger Modes................................................................................................................. 281
17.3.6 Hardware Breakpoints .................................................................................................... 283
17.4 Register Definition ........................................................................................................................ 283
17.4.1 BDC Registers and Control Bits ..................................................................................... 283
17.4.2 System Background Debug Force Reset Register (SBDFR) .......................................... 285
17.4.3 DBG Registers and Control Bits..................................................................................... 286
Appendix A
Electrical Characteristics
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9
A.10
A.11
A.12
Introduction ....................................................................................................................................291
Parameter Classification.................................................................................................................291
Absolute Maximum Ratings...........................................................................................................291
Thermal Characteristics..................................................................................................................293
ESD Protection and Latch-Up Immunity .......................................................................................295
DC Characteristics..........................................................................................................................296
Supply Current Characteristics.......................................................................................................302
External Oscillator (XOSC) Characteristics ..................................................................................306
Internal Clock Source (ICS) Characteristics ..................................................................................308
Analog Comparator (ACMP) Electricals .......................................................................................309
ADC Characteristics.......................................................................................................................310
AC Characteristics..........................................................................................................................316
A.12.1 Control Timing ................................................................................................................316
A.12.2 TPM/MTIM Module Timing ...........................................................................................318
A.12.3 SPI....................................................................................................................................319
A.13 Flash Specifications........................................................................................................................323
A.14 EMC Performance..........................................................................................................................324
A.14.1 Radiated Emissions..........................................................................................................324
Appendix B
Ordering Information and Mechanical Drawings
B.1 Ordering Information .....................................................................................................................325
B.1.1 Device Numbering Scheme .............................................................................................326
B.2 Package Information and Mechanical Drawings ...........................................................................326
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
19
Section Number
Title
Page
MC9S08SG32 Data Sheet, Rev. 8
20
Freescale Semiconductor
Chapter 1
Device Overview
The MC9S08SG32 devices are members of the low-cost, high-performance HCS08 family of 8-bit
microcontroller units (MCUs). The MC9S08SG32 Series high-temperature devices have been qualified to
meet or exceed AEC Grade 0 requirements to allow them to operate up to 150 °C TA. All MCUs in the
family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory
types, and package types.
1.1
Devices in the MC9S08SG32 Series
Table 1-1 summarizes the feature set available in the MC9S08SG32 series of MCUs.
t
Table 1-1. MC9S08SG32 Series Features by MCU and Package
Feature
MC9S08SG32
MC9S08SG16
FLASH size (bytes)
32768
16384
RAM size (bytes)
1024
1024
Pin quantity
28
ACMP
20
16
28
yes
ADC channels
16
12
20
yes
8
16
12
DBG
yes
yes
ICS
yes
yes
IIC
yes
yes
MTIM
yes
yes
8
8
Pin Interrupts
Pin I/O
22
16
16
12
22
16
RTC
yes
yes
SCI
yes
yes
SPI
yes
yes
TPM1 channels
yes
yes
TPM2 channels
yes
yes
XOSC
yes
yes
8
12
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
21
Chapter 1 Device Overview
1.2
MCU Block Diagram
The block diagram in Figure 1-1 shows the structure of the MC9S08SG32 Series MCU.
BKGD/MS
RESET
HCS08 CORE
DEBUG MODULE (DBG)
PTA7/TPM2CH1
BDC
PTA6/TPM2CH0
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
SCL
IIC MODULE (IIC)
LVD
COP
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER FLASH
(MC9S08SG32 = 32,768
BYTES)(MC9S08SG16 = 16,384
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI)
USER RAM
(MC9S08SG32 = 1024 BYTES)
(MC9S08SG16 = 1024 BYTES)
16-BIT TIMER/PWM
MODULE (TPM1)
REAL-TIME COUNTER (RTC)
40-MHz INTERNAL CLOCK
SOURCE (ICS)
16-BIT TIMER/PWM
MODULE (TPM2)
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
TCLK
EXTAL
XTAL
PORT A
8-BIT MODULO TIMER
MODULE (MTIM)
PTA3/PIA3/SCL/ADP3
PTA2/PIA2/SDA/ACMPO/ADP2
SDA
PTA1/PIA1/TPM2CH0/ADP1/ACMP–
PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+
SS
MISO
MOSI
SPSCK
RxD
TxD
TCLK
TPM1CH0
TPM1CH1
Δ
Δ
PORT B
CPU
Δ
Δ
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
PTB3/PIB3/MOSI/ADP7
PTB2/PIB2/SPSCK/ADP6
PTB1/PIB1/TxD/ADP5
TCLK
TPM2CH0
PTB0/PIB0/RxD/ADP4
TPM2CH1
ACMPO
ANALOG COMPARATOR
(ACMP)
ACMP–
PTC7/ADP15
PTC6/ADP14
ACMP+
VSS
VDDA/VREFH
VSSA/VREFL
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
VDDA
VSSA
ADP15-ADP0
PORT C
PTC5/ADP13
VOLTAGE REGULATOR
VDD
Δ
Δ
Δ
Δ
VREFH
VREFL
PTC4/ADP12
PTC3/ADP11
:Q!A "D
PTC1/TPM1CH1/ADP9
PTC0/TPM1CH0/ADP8
NOTE
• PTC7-PTC0 and PTA7-PTA6 are not available on 16-pin Packages
• PTC7-PTC4 and PTA7-PTA6 are not available on 20-pin Packages
• For the 16-pin and 20-pin packages: VDDA/VREFH and VSSA/VREFL are
double bonded to VDD and VSS respectively.
Δ = Pin can be enabled as part of the ganged output drive feature
Figure 1-1. MC9S08SG32 Series Block Diagram
MC9S08SG32 Data Sheet, Rev. 8
22
Freescale Semiconductor
Chapter 1 Device Overview
Table 1-2 provides the functional version of the on-chip modules.
Table 1-2. Module Versions
Module
Version
Analog Comparator (5V)
(ACMP)
3
Analog-to-Digital Converter
(ADC10)
1
Central Processor Unit
(CPU)
3
Inter-Integrated Circuit
(IIC)
2
Internal Clock Source
(ICS)
2
Low Power Oscillator
(XOSC)
1
Modulo Timer
(MTIM)
1
On-Chip In-Circuit Emulator
(DBG)
2
Real-Time Counter
(RTC)
1
Serial Peripheral Interface
(SPI)
3
Serial Communications Interface
(SCI)
4
Timer Pulse Width Modulator
(TPM)
3
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
23
Chapter 1 Device Overview
1.3
System Clock Distribution
Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock
inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module
function.
The following defines the clocks used in this MCU:
• BUSCLK — The frequency of the bus is always half of ICSOUT.
• ICSOUT — Primary output of the ICS and is twice the bus frequency.
• ICSLCLK — Development tools can select this clock source to speed up BDC communications in
systems where the bus clock is configured to run at a very slow frequency.
• ICSERCLK — External reference clock can be selected as the RTC clock source and as the
alternate clock for the ADC module.
• ICSIRCLK — Internal reference clock can be selected as the RTC clock source.
• ICSFFCLK — Fixed frequency clock can be selected as clock source for the TPM1, TPM2 and
MTIM modules.
• LPOCLK — Independent 1-kHz clock source that can be selected as the clock source for the COP
and RTC modules.
• TCLK — External input clock source for TPM1, TPM2 and MTIM and is referenced as TPMCLK
in TPM chapters.
TCLK
1 kHZ
LPO
LPOCLK
COP
RTC
TPM1
TPM2
MTIM
SCI
SPI
ICSERCLK
ICSIRCLK
ICS
ICSFFCLK
÷2
ICSOUT
÷2
FFCLK*
SYNC*
BUSCLK
ICSLCLK
XOSC
CPU
EXTAL
BDC
XTAL
* The fixed frequency clock (FFCLK) is internally
synchronized to the bus clock and must not exceed one half
of the bus clock frequency.
ADC
IIC
ADC has min and max
frequency
requirements.See the
ADC chapter and
electricals appendix for
details.
FLASH
FLASH has frequency
requirements for program
and erase operation. See
the electricals appendix
for details.
Figure 1-2. System Clock Distribution Diagram
MC9S08SG32 Data Sheet, Rev. 8
24
Freescale Semiconductor
Chapter 2
Pins and Connections
This section describes signals that connect to package pins. It includes pinout diagrams, recommended
system connections, and detailed discussions of signals.
2.1
Device Pin Assignment
The following figures show the pin assignments for the MC9S08SG32 Series devices.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PTC5/ADP13
PTC4/ADP12
RESET
BKGD/MS
VDD
VDDA/VREFH
VSSA/VREFL
VSS
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
PTC3/ADP11
PTC2/ADP10
PTC6/ADP14
PTC7/ADP15
PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+
PTA1/PIA1/TPM2CH0/ADP1/ACMP–
PTA2/PIA2/SDA/ACMPO/ADP2
PTA3/PIA3/SCL/ADP3
PTA6/TPM2CH0
PTA7/TPM2CH1
PTB0/PIB0/RxD/ADP4
PTB1/PIB1/TxD/ADP5
PTB2/PIB2/SPSCK/ADP6
PTB3/PIB3/MOSI/ADP7
PTC0/TPM1CH0/ADP8
PTC1/TPM1CH1/ADP9
Figure 2-1. 28-Pin TSSOP
RESET
BKGD/MS
VDD
VSS
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
PTC3/ADP11
PTC2/ADP10
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+
PTA1/PIA1/TPM2CH0/ADP1/ACMP–
PTA2/PIA2/SDA/ACMPO/ADP2
PTA3/PIA3/SCL/ADP3
PTB0/PIB0/RxD/ADP4
PTB1/PIB1/TxD/ADP5
PTB2/PIB2/SPSCK/ADP6
PTB3/PIB3/MOSI/ADP7
PTC0/TPM1CH0/ADP8
PTC1/TPM1CH1/ADP9
Figure 2-2. 20-Pin TSSOP1
1. 20-Pin TSSOP package not available for the high-temperature rated devices.
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
25
Chapter 2 Pins and Connections
RESET
BKGD/MS
VDD
VSS
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+
PTA1/PIA1/TPM2CH0/ADP1/ACMP–
PTA2/PIA2/SDA/ACMPO/ADP2
PTA3/PIA3/SCL/ADP3
PTB0/PIB0/RxD/ADP4
PTB1/PIB1/TxD/ADP5
PTB2/PIB2/SPSCK/ADP6
PTB3/PIB3/MOSI/ADP7
Figure 2-3. 16-Pin TSSOP
MC9S08SG32 Data Sheet, Rev. 8
26
Freescale Semiconductor
Chapter 2 Pins and Connections
2.2
Recommended System Connections
Figure 2-4 shows pin connections that are common to MC9S08SG32 Series application systems.
MC9S08SG32
BACKGROUND HEADER
PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+
BKGD/MS
VDD
PTA1/PIA1/TPM2CH0/ADP1/ACMP–
VDD
PTA2/PIA2/SDA/ACMPO/ADP2
PORT
A
4.7 kΩ–10 kΩ
PTA3/PIA3/SCL/ADP3
RESET
OPTIONAL
MANUAL
RESET
PTA6/TPM2CH0
PTA7/TPM2CH1
0.1 μF
PTB0/PIB0/RxD/ADP4
PTB1/PIB1/TxD/ADP5
PTC0/TPM1CH0/ADP8
PTB2/PIB2/SPSCK/ADP6
PTC1/TPM1CH1/ADP9
PTB3/PIB3/MOSI/ADP7
PORT
B
PTC2/ADP10
PTC3/ADP11
PTB4/TPM2CH1/MISO
PORT
C
PTC4/ADP12
PTB5/TPM1CH1/SS
PTB6/SDA/XTAL
PTC5/ADP13
PTB7/SCL/EXTAL
PTC6/ADP14
PTC7/ADP15
RF
RS
VDD
+
5V
CBLK +
10 μF
CBY
0.1 μF
C1
X1
C2
VSS
NOTE 1
SYSTEM
POWER
VDDA\VREFH
CBY
0.1 μF
VSSA\VREFL
NOTES:
1. External crystal circuit not required if using the internal clock option.
2. RESET pin can only be used to reset into user mode, you can not enter BDM using RESET pin. BDM can be entered by
holding MS low during POR or writing a 1 to BDFR in SBDFR with MS low after issuing BDM command.
3. RC filter on RESET pin recommended for noisy environments.
4. For the 16-pin and 20-pin packages: VDDA/VREFH and VSSA/VREFL are double bonded to VDD and VSS respectively.
Figure 2-4. Basic System Connections
2.2.1
Power
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all
I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated
lower-voltage source to the CPU and other internal circuitry of the MCU.
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
27
Chapter 2 Pins and Connections
Typically, application systems have two separate capacitors across the power pins. In this case, there
should be a bulk electrolytic capacitor, such as a 10-μF tantalum capacitor, to provide bulk charge storage
for the overall system and a 0.1-μF ceramic bypass capacitor located as near to the MCU power pins as
practical to suppress high-frequency noise. Each pin must have a bypass capacitor for best noise
suppression.
VDDA and VSSA are the analog power supply pins for MCU. This voltage source supplies power to the
ADC module. A 0.1 μF ceramic bypass capacitor should be located as near to the MCU power pins as
practical to suppress high-frequency noise. The VREFH and VREFL pins are the voltage reference high and
voltage reference low inputs, respectively for the ADC module. For this MCU, VDDA shares the VREFH
pin and these pins are available only in the 28-pin packages. In the 16-pin and 20-pin packages, they are
double bonded to the VDD pin. For this MCU, VSSA shares the VREFL pin and these pins are available only
in the 28-pin packages. In the 16-pin and 20-pin packages, they are double bonded to the VSS pin.
2.2.2
Oscillator (XOSC)
Immediately after reset, the MCU uses an internally generated clock provided by the clock source
generator (ICS) module. For more information on the ICS, see Chapter 11, “Internal Clock Source
(S08ICSV2).”
The oscillator (XOSC) in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic
resonator. Rather than a crystal or ceramic resonator, an external oscillator can be connected to the EXTAL
input pin.
Refer to Figure 2-4 for the following discussion. RS (when used) and RF should be low-inductance
resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have
too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically
designed for high-frequency applications.
RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup; its value
is not generally critical. Typical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to humidity and
lower values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific
crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin
capacitance when selecting C1 and C2. The crystal manufacturer typically specifies a load capacitance
which is the series combination of C1 and C2 (which are usually the same size). As a first-order
approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin
(EXTAL and XTAL).
2.2.3
RESET
RESET is a dedicated pin with open-drain drive containing an internal pull-up device. Internal power-on
reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin is
normally connected to the standard 6-pin background debug connector so a development system can
directly reset the MCU system. If desired, a manual external reset can be added by supplying a simple
switch to ground (pull reset pin low to force a reset).
MC9S08SG32 Data Sheet, Rev. 8
28
Freescale Semiconductor
Chapter 2 Pins and Connections
Whenever any reset is initiated (whether from an external signal or from an internal system), the RESET
pin is driven low for about 66 bus cycles. The reset circuitry decodes the cause of reset and records it by
setting a corresponding bit in the system reset status register (SRS).
•
•
•
2.2.4
NOTE
This pin does not contain a clamp diode to VDD and should not be driven
above VDD.
The voltage measured on the internally pulled up RESET pin will not be
pulled to VDD. The internal gates connected to this pin are pulled to
VDD. If the RESET pin is required to drive to a VDD level, an external
pullup should be used.
In EMC-sensitive applications, an external RC filter is recommended on
the RESET. See Figure 2-4 for an example.
Background / Mode Select (BKGD/MS)
During a power-on-reset (POR) or background debug force reset (see Section 5.7.2, “System Background
Debug Force Reset Register (SBDFR),” for more information), the BKGD/MS pin functions as a mode
select pin. Immediately after any reset, the pin functions as the background pin and can be used for
background debug communication. The BKGD/MS pin contains an internal pullup device.
If nothing is connected to this pin, the MCU enters normal operating mode at the rising edge of the internal
reset after a POR or force BDC reset. If a debug system is connected to the 6-pin standard background
debug header, it can hold BKGD/MS low during a POR or immediately after issuing a background debug
force reset, which will force the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the maximum bus clock rate, so there must never be any significant capacitance
connected to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.2.5
General-Purpose I/O and Peripheral Ports
The MC9S08SG32 Series of MCUs support up to 22 general-purpose I/O pins which are shared with
on-chip peripheral functions (timers, serial I/O, ADC, etc.).
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,
software can select one of two drive strengths and enable or disable slew rate control. When a port pin is
configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a
pull-up device. Immediately after reset, all of these pins are configured as high-impedance general-purpose
inputs with internal pull-up devices disabled.
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
29
Chapter 2 Pins and Connections
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. For information about controlling these pins as general-purpose I/O
pins, see Chapter 6, “Parallel Input/Output Control.”
The MC9S08SG32 Series devices contain a ganged output drive feature that allows a safe and reliable
method of allowing pins to be tied together externally to produce a higher output current drive. See Section
6.3, “Ganged Output” for more information for configuring the port pins for ganged output drive.
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program should either enable on-chip pull-up
devices or change the direction of unused pins to outputs so they do not float.
When using the 20-pin devices, either enable on-chip pullup devices or
change the direction of non-bonded PTC7-PTC4 and PTA7-PTA6 pins to
outputs so the pins do not float.
When using the 16-pin devices, either enable on-chip pullup devices or
change the direction of non-bonded out PTC7-PTC0 and PTA7-PTA6 pins
to outputs so the pins do not float.
Table 2-1. Pin Availability by Package Pin-Count
Priority
Pin Number
Lowest
28-pin 20-pin1 16-pin
Port Pin
Highest
Alt 1
Alt 2
Alt 3
Alt 4
Alt 5
1
—
—
PTC5
ADP13
2
—
—
PTC4
ADP12
3
1
1
4
2
2
3
3
4
4
RESET2
BKGD
5
6
VDD
7
8
VDDA
VREFH
VSSA
VREFL
VSS
9
5
5
PTB7
SCL3
10
6
6
PTB6
SDA3
EXTAL
XTAL
11
7
7
PTB5
TPM1CH1
SS
PTC05
12
8
8
PTB4
TPM2CH16
MISO
PTC05
13
9
—
PTC3
PTC05
ADP11
14
10
—
PTC2
PTC05
ADP10
4
PTC05
ADP9
4
PTC05
ADP8
5
15
16
MS
11
12
—
—
4
PTC1
TPM1CH1
PTC0
TPM1CH0
17
13
9
PTB3
PIB3
MOSI
PTC0
ADP7
18
14
10
PTB2
PIB2
SPSCK
PTC05
ADP6
MC9S08SG32 Data Sheet, Rev. 8
30
Freescale Semiconductor
Chapter 2 Pins and Connections
Table 2-1. Pin Availability by Package Pin-Count (continued)
Priority
Pin Number
Lowest
28-pin 20-pin1 16-pin
Port Pin
Highest
Alt 1
Alt 2
Alt 3
Alt 4
19
15
11
PTB1
PIB1
TxD
ADP5
20
16
12
PTB0
PIB0
RxD
ADP4
21
—
—
PTA7
TPM2CH16
22
—
—
PTA6
TPM2CH06
23
17
13
PTA3
PIA3
SCL3
3
Alt 5
ADP3
ACMPO
ADP2
24
18
14
PTA2
PIA2
SDA
25
19
15
PTA1
PIA1
TPM2CH06
26
20
16
PTA0
PIA0
TPM1CH04
27
—
—
PTC7
ADP15
28
—
—
PTC6
ADP14
TCLK
ADP17
ACMP-7
ADP07
ACMP+7
1
The 20-pin package is not available for the high-temperature rated devices.
Pin is open drain with an internal pullup that is always enabled. Pin does not contain a clamp diode to VDD
and should not be driven above VDD. The voltage measured on the internally pulled up RESET will not be
pulled to VDD. The internal gates connected to this pin are pulled to VDD.
3 IIC pins can be repositioned using IICPS in SOPT2, default reset locations are PTA2, PTA3.
2
4
TPM1CHx pins can be repositioned using T1CHxPS bits in SOPT2, default reset locations are PTA0, PTB5.
This port pin is part of the ganged output feature. When pin is enabled for ganged output, it will have priority
over all digital modules. The output data, drive strength and slew-rate control of this port pin will follow the
configuration for the PTC0 pin, even in 16-pin packages where PTC0 doesn’t bond out.
6 TPM2CHx pins can be repositioned using T2CHxPS bits in SOPT2, default reset locations are PTA1, PTB4.
7 If ACMP and ADC are both enabled, both will have access to the pin.
5
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
31
Chapter 2 Pins and Connections
MC9S08SG32 Data Sheet, Rev. 8
32
Freescale Semiconductor
Chapter 3
Modes of Operation
3.1
Introduction
The operating modes of the MC9S08SG32 Series are described in this chapter. Entry into each mode, exit
from each mode, and functionality while in each of the modes are described.
3.2
•
•
•
3.3
Features
Active background mode for code development
Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation
is maintained
Stop modes — System clocks are stopped and voltage regulator is in standby
— Stop3 — All internal circuits are powered for fast recovery
— Stop2 — Partial power down of internal circuits, RAM content is retained
Run Mode
This is the normal operating mode for the MC9S08SG32 Series. This mode is selected upon the MCU
exiting reset if the BKGD/MS pin is high. In this mode, the CPU executes code from internal memory with
execution beginning at the address fetched from memory at 0xFFFE–0xFFFF after reset.
3.4
Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for
analyzing MCU operation during software development.
Active background mode is entered in any of the following ways:
• When the BKGD/MS pin is low during POR or immediately after issuing a background debug
force reset (see Section 5.7.2, “System Background Debug Force Reset Register (SBDFR)”)
• When a BACKGROUND command is received through the BKGD/MS pin
• When a BGND instruction is executed
• When encountering a BDC breakpoint
• When encountering a DBG breakpoint
After entering active background mode, the CPU is held in a suspended state waiting for serial background
commands rather than executing instructions from the user application program.
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
33
Chapter 3 Modes of Operation
Background commands are of two types:
• Non-intrusive commands, defined as commands that can be issued while the user program is
running. Non-intrusive commands can be issued through the BKGD/MS pin while the MCU is in
run mode; non-intrusive commands can also be executed when the MCU is in the active
background mode. Non-intrusive commands include:
— Memory access commands
— Memory-access-with-status commands
— BDC register access commands
— The BACKGROUND command
• Active background commands, which can only be executed while the MCU is in active background
mode. Active background commands include commands to:
— Read or write CPU registers
— Trace one user program instruction at a time
— Leave active background mode to return to the user application program (GO)
The active background mode is used to program a bootloader or user application program into the FLASH
program memory before the MCU is operated in run mode for the first time. When the MC9S08SG32
Series is shipped from the Freescale Semiconductor factory, the FLASH program memory is erased by
default unless specifically noted so there is no program that could be executed in run mode until the
FLASH memory is initially programmed. The active background mode can also be used to erase and
reprogram the FLASH memory after it has been previously programmed.
For additional information about the active background mode, refer to the Development Support chapter.
3.5
Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the
wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and
resumes processing, beginning with the stacking operations leading to the interrupt service routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can
be used. Only the BACKGROUND command and memory-access-with-status commands are available
when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access,
but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND
command can be used to wake the MCU from wait mode and enter active background mode.
3.6
Stop Modes
One of two stop modes is entered upon execution of a STOP instruction when STOPE in SOPT1. In any
stop mode, the bus and CPU clocks are halted. The ICS module can be configured to leave the reference
clocks running. See Chapter 11, “Internal Clock Source (S08ICSV2),” for more information.
MC9S08SG32 Data Sheet, Rev. 8
34
Freescale Semiconductor
Chapter 3 Modes of Operation
Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various
conditions. The selected mode is entered following the execution of a STOP instruction.
Table 3-1. Stop Mode Selection
STOPE
ENBDM 1
0
x
1
LVDE
LVDSE
PPDC
Stop Mode
x
x
Stop modes disabled; illegal opcode reset if STOP instruction executed
1
x
x
Stop3 with BDM enabled 2
1
0
Both bits must be 1
x
Stop3 with voltage regulator active
1
0
Either bit a 0
0
Stop3
1
0
Either bit a 0
1
Stop2
1
ENBDM is located in the BDCSCR, which is only accessible through BDC commands, see Section 17.4.1.1, “BDC Status and
Control Register (BDCSCR)”.
2 When in Stop3 mode with BDM enabled, The S
IDD will be near RIDD levels because internal clocks are enabled.
3.6.1
Stop3 Mode
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time
counter (RTC), LVD system, ACMP, ADC, SCI or any pin interrupts.
If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking
the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the
appropriate interrupt vector.
3.6.1.1
LVD Enabled in Stop3 Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. For configuring the LVD system for interrupt or reset, refer to Section 5.6, “Low-Voltage
Detect (LVD) System”. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the
time the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode.
For the ADC to operate in stop mode, the LVD must be enabled when entering stop3.
For the ACMP to operate in stop mode with compare to internal bandgap option, the LVD must be enabled
when entering stop3.
3.6.1.2
Active BDM Enabled in Stop3 Mode
Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This
register is described in Chapter 17, “Development Support.” If ENBDM is set when the CPU executes a
STOP instruction, the system clocks to the background debug logic remain active when the MCU enters
stop mode. Because of this, background debug communication remains possible. In addition, the voltage
regulator does not enter its low-power standby state but maintains full internal regulation.
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
35
Chapter 3 Modes of Operation
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After entering background debug mode, all background
commands are available.
3.6.2
Stop2 Mode
Stop2 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most
of the internal circuitry of the MCU is powered off in stop2 with the exception of the RAM. Upon entering
stop2, all I/O pin control signals are latched so that the pins retain their states during stop2.
Exit from stop2 is performed by asserting the wake-up pin (RESET) on the MCU.
In addition, the real-time counter (RTC) can wake the MCU from stop2, if enabled.
Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR):
• All module control and status registers are reset
• The LVD reset function is enabled and the MCU remains in the reset state if VDD is below the LVD
trip point (low trip point selected due to POR)
• The CPU takes the reset vector
In addition to the above, upon waking up from stop2, the PPDF bit in SPMSC2 is set. This flag is used to
direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched
until a 1 is written to PPDACK in SPMSC2.
To maintain I/O states for pins that were configured as general-purpose I/O before entering stop2, the user
must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers
before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to
PPDACK, then the pins will switch to their reset states when PPDACK is written.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
3.6.3
On-Chip Peripheral Modules in Stop Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.2, “Stop2
Mode,” and Section 3.6.1, “Stop3 Mode,” for specific information on system behavior in stop modes.
MC9S08SG32 Data Sheet, Rev. 8
36
Freescale Semiconductor
Chapter 3 Modes of Operation
Table 3-2. Stop Mode Behavior
Mode
Peripheral
Stop2
Stop3
CPU
Off
Standby
RAM
Standby
Standby
FLASH
Off
Standby
Parallel Port Registers
Off
Standby
ADC
Off
Optionally On1
ACMP
Off
Optionally On2
BDM
Off3
Optionally On
ICS
Off
Optionally On4
IIC
Off
Standby
5
LVD/LVW
Off
Optionally On
MTIM
Off
Standby
RTC
Optionally On
Optionally On
SCI
Off
Standby
SPI
Off
Standby
TPM
Off
Standby
Standby
Optionally On6
Off
Optionally On7
States Held
States Held
Voltage Regulator
XOSC
I/O Pins
1
2
3
4
5
6
7
Requires the asynchronous ADC clock and LVD to be enabled, else in
standby.
Requires the LVD to be enabled when compare to internal band-up reference
option is enabled.
If ENBDM is set when entering stop2, the MCU will actually enter stop3.
IRCLKEN and IREFSTEN set in ICSC1, else in standby.
If LVDSE is set when entering stop2, the MCU will actually enter stop3.
Voltage regulator will be on if BDM is enabled or if LVD is enabled when
entering stop3.
ERCLKEN and EREFSTEN set in ICSC2, else in standby. For high frequency
range (RANGE in ICSC2 set) requires the LVD to also be enabled in stop3.
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
37
Chapter 3 Modes of Operation
MC9S08SG32 Data Sheet, Rev. 8
38
Freescale Semiconductor
Chapter 4
Memory
4.1
MC9S08SG32 Series Memory Map
As shown in Figure 4-1, on-chip memory in the MC9S08SG32 Series series of MCUs consists of RAM,
FLASH program memory for nonvolatile data storage, and I/O and control/status registers. The registers
are divided into three groups:
• Direct-page registers (0x0000 through 0x007F)
• High-page registers (0x1800 through 0x185F)
• Nonvolatile registers (0xFFB0 through 0xFFBF)
0x0000
0x007F
0x0080
0x0000
DIRECT PAGE REGISTERS
0x007F
0x0080
DIRECT PAGE REGISTERS
RAM
1024 BYTES
RAM
1024 BYTES
0x047F
0x0480
0x17FF
0x1800
UNIMPLEMENTED
4992 BYTES
0x047F
0x0480
UNIMPLEMENTED
4992 BYTES
0x17FF
0x1800
HIGH PAGE REGISTERS
HIGH PAGE REGISTERS
0x185F
0x1860
0x185F
0x1860
UNIMPLEMENTED
0x7FFF
0x8000
26,528 BYTES
UNIMPLEMENTED
0x7FFF
0x8000
26,538 BYTES
UNIMPLEMENTED
16,384 BYTES
FLASH
32768 BYTES
0xBFFF
0xC000
FLASH
16,384 BYTES
0xFFFF
0xFFFF
MC9S08SG32
MC9S08SG16
Figure 4-1. MC9S08SG32/MC9S08SG16 Memory Map
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
39
Chapter 4 Memory
4.2
Reset and Interrupt Vector Assignments
Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table
are the labels used in the Freescale Semiconductor provided equate file for the MC9S08SG32 Series.
Table 4-1. Reset and Interrupt Vectors
Address
(High/Low)
Vector
Vector Name
0xFFC0:0xFFC1
Reserved
—
0xFFC2:0xFFC3
ACMP
Vacmp
0xFFC4:0xFFC5
Reserved
—
0xFFC6:0xFFC7
Reserved
—
0xFFC8:0xFFC9
Reserved
—
0xFFCA:0xFFCB
MTIM Overflow
Vmtim
0xFFCC:0xFFCD
RTC
Vrtc
0xFFCE:0xFFCF
IIC
Viic
0xFFD0:0xFFD1
ADC Conversion
Vadc
0xFFD2:0xFFD3
Reserved
—
0xFFD4:0xFFD5
Port B Pin Interrupt
Vportb
0xFFD6:0xFFD7
Port A Pin Interrupt
Vporta
0xFFD8:0xFFD9
Reserved
—
0xFFDA:0xFFDB
SCI Transmit
Vscitx
0xFFDC:0xFFDD
SCI Receive
Vscirx
0xFFDE:0xFFDF
SCI Error
Vsc1err
0xFFE0:0xFFE1
SPI
Vspi
0xFFE2:0xFFE3
TPM2 Overflow
Vtpm2ovf
0xFFE4:0xFFE5
TPM2 Channel 1
Vtpm2ch1
0xFFE6:0xFFE7
TPM2 Channel 0
Vtpm2ch0
0xFFE8:0xFFE9
TPM1 Overflow
Vtpm1ovf
0xFFEA:0xFFEB
Reserved
—
0xFFEC:0xFFED
Reserved
—
0xFFEE:0xFFEF
Reserved
—
0xFFF0:0xFFF1
Reserved
—
0xFFF2:0xFFF3
TPM1 Channel 1
Vtpm1ch1
0xFFF4:0xFFF5
TPM1 Channel 0
Vtpm1ch0
0xFFF6:0xFFF7
Reserved
—
0xFFF8:0xFFF9
Low Voltage Detect
Vlvd
0xFFFA:0xFFFB
Reserved
—
0xFFFC:0xFFFD
SWI
Vswi
0xFFFE:0xFFFF
Reset
Vreset
MC9S08SG32 Data Sheet, Rev. 8
40
Freescale Semiconductor
Chapter 4 Memory
4.3
Register Addresses and Bit Assignments
The registers in the MC9S08SG32 Series are divided into these groups:
• Direct-page registers are located in the first 128 locations in the memory map; these are accessible
with efficient direct addressing mode instructions.
• High-page registers are used much less often, so they are located above 0x1800 in the memory
map. This leaves more room in the direct page for more frequently used registers and RAM.
• The nonvolatile register area consists of a block of 16 locations in FLASH memory at
0xFFB0–0xFFBF. Nonvolatile register locations include:
— NVPROT and NVOPT are loaded into working registers at reset
— An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to
secure memory
Because the nonvolatile register locations are FLASH memory, they must be erased and
programmed like other FLASH memory locations.
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation
instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all
user-accessible direct-page registers and control bits.
The direct page registers in Table 4-2 can use the more efficient direct addressing mode, which requires
only the lower byte of the address. Because of this, the lower byte of the address in column one is shown
in bold text. In Table 4-3 and Table 4-4, the whole address in column one is shown in bold. In Table 4-2,
Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart from the
bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0
indicates this unused or reserved bit always reads as a 0 and should be written as 0. A shaded cell with a 1
indicates this unused or reserved bit always reads as a 1and should be written as 1. Shaded cells with dashes
indicate unused or reserved bit locations that could read as 1s or 0s.
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
41
Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 1 of 3)
Address
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
PTAD7
PTAD6
—
—
PTAD3
PTAD2
PTAD1
PTAD0
PTADD7
PTADD6
—
—
PTADD3
PTADD2
PTADD1
PTADD0
PTBD7
PTBD6
PTBD5
PTBD4
PTBD3
PTBD2
PTBD1
PTBD0
PTBDD7
PTBDD6
PTBDD5
PTBDD4
PTBDD3
PTBDD2
PTBDD1
PTBDD0
PTCD7
PTCD6
PTCD5
PTCD4
PTCD3
PTCD2
PTCD1
PTCD0
PTCDD7
PTCDD6
PTCDD5
PTCDD4
PTCDD3
PTCDD2
PTCDD1
PTCDD0
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008–0
x000D
0x000E
PTAD
PTADD
PTBD
PTBDD
PTCD
PTCDD
Reserved
Reserved
ACMPSC
ACME
ACBGS
ACF
ACIE
ACO
ACOPE
ACMOD1
ACMOD0
0x000F
0x0010
0x0011
0x0012
0x0013
0x0014
0x0015
0x0016
0x0017
0x0018
0x0019–0
x001B
0x001C
0x001D
0x001E
0x001F
0x0020
0x0021
0x0022
0x0023
0x0024
0x0025
0x0026
0x0027
0x0028
0x0029
0x002A
Reserved
ADCSC1
ADCSC2
ADCRH
ADCRL
ADCVH
ADCVL
ADCCFG
APCTL1
APCTL2
—
—
—
—
—
—
—
—
COCO
AIEN
ADCO
ADACT
ADTRG
ACFE
—
—
Reserved
MTIMSC
MTIMCLK
MTIMCNT
MTIMMOD
TPM1SC
TPM1CNTH
TPM1CNTL
TPM1MODH
TPM1MODL
TPM1C0SC
TPM1C0VH
TPM1C0VL
TPM1C1SC
TPM1C1VH
TPM1C1VL
ADCH
ACFGT
—
—
0
0
0
0
0
0
ADR9
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
0
0
0
0
0
0
ADCV9
ADCV8
ADCV7
ADCV6
ADCV5
ADCV4
ADCV3
ADCV2
ADCV1
ADCV0
ADLPC
ADIV
ADLSMP
MODE
ADICLK
ADPC7
ADPC6
ADPC5
ADPC4
ADPC3
ADPC2
ADPC1
ADPC0
ADPC15
ADPC14
ADPC13
ADPC12
ADPC11
ADPC10
ADPC9
ADPC8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TOF
TOIE
TRST
TSTP
0
0
0
0
0
0
CLKS
PS
CNT
MOD
TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
0
0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
CH1F
CH1IE
MS1B
MS1A
ELS1B
ELS1A
0
0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
MC9S08SG32 Data Sheet, Rev. 8
42
Freescale Semiconductor
Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 2 of 3)
Address
0x002B–0
x0037
0x0038
0x0039
0x003A
0x003B
0x003C
0x003D
0x003E
0x003F
0x0040–0
x0047
0x0048
0x0049
0x004A
0x004B
0x004C–0
x004F
0x0050
0x0051
0x0052
0x0053
0x0054
0x0055
0x0056–0
x0057
0x0058
0x0059
0x005A
0x005B
0x005C
0x005D
0x005E–0
x005F
0x0060
0x0061
0x0062
0x0063
0x0064
0x0065
Register
Name
Reserved
SCIBDH
SCIBDL
SCIC1
SCIC2
SCIS1
SCIS2
SCIC3
SCID
Reserved
ICSC1
ICSC2
ICSTRM
ICSSC
Reserved
SPIC1
SPIC2
SPIBR
SPIS
Reserved
SPID
Reserved
IICA
IICF
IICC1
IICS
IICD
IICC2
Reserved
TPM2SC
TPM2CNTH
TPM2CNTL
TPM2MODH
TPM2MODL
TPM2C0SC
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LBKDIE
RXEDGIE
0
SBR12
SBR11
SBR10
SBR9
SBR8
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
LBKDIF
RXEDGIF
0
RXINV
RWUID
BRK13
LBKDE
RAF
R8
T8
TXDIR
TXINV
ORIE
NEIE
FEIE
PEIE
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IREFS
IRCLKEN
IREFSTEN
EREFS
ERCLKEN EREFSTEN
CLKS
RDIV
BDIV
RANGE
HGO
LP
TRIM
0
0
0
IREFST
OSCINIT
FTRIM
—
—
—
—
—
—
—
—
—
—
CLKST
—
—
—
—
—
—
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0
0
0
MODFEN
BIDIROE
0
SPISWAI
SPC0
0
SPPR2
SPPR1
SPPR0
0
SPR2
SPR1
SPR0
SPRF
0
SPTEF
MODF
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AD7
AD6
AD5
AD4
AD3
AD2
AD1
0
TXAK
RSTA
0
0
0
SRW
IICIF
RXAK
MULT
ICR
IICEN
IICIE
MST
TX
TCF
IAAS
BUSY
ARBL
DATA
GCAEN
ADEXT
0
0
0
AD10
AD9
AD8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
0
0
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
43
Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 3 of 3)
Address
0x0066
0x0067
0x0068
0x0069
0x006A
0x006B
0x006C
0x006D
0x006E
0x006F 0x007F
Register
Name
TPM2C0VH
TPM2C0VL
TPM2C1SC
TPM2C1VH
TPM2C1VL
Reserved
RTCSC
RTCCNT
RTCMOD
Reserved
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
CH1F
CH1IE
MS1B
MS1A
ELS1B
ELS1A
0
0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
—
—
—
—
RTIF
—
RTCLKS
RTIE
RTCPS
RTCCNT
RTCMOD
—
—
—
—
—
—
—
—
—
—
—
—
MC9S08SG32 Data Sheet, Rev. 8
44
Freescale Semiconductor
Chapter 4 Memory
High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers
so they have been located outside the direct addressable memory space, starting at 0x1800.
Table 4-3. High-Page Register Summary (Sheet 1 of 2)
Address
0x1800
0x1801
0x1802
0x1803
0x1804 –
0x1805
0x1806
0x1807
0x1808
0x1809
0x180A
0x180B–0
x180F
0x1810
0x1811
0x1812
0x1813
0x1814
0x1815
0x1816
0x1817
0x1818
0x1819–0x
181F
0x1820
0x1821
0x1822
0x1823
0x1824
0x1825
0x1826
0x1827–
0x183F
0x1840
0x1841
0x1842
0x1843
0x1844
Register Name
SRS
SBDFR
SOPT1
SOPT2
Reserved
Bit 7
6
5
4
3
2
1
POR
PIN
COP
ILOP
ILAD
0
LVD
0
0
0
0
0
0
0
0
BDFR
STOPE
0
0
IICPS
0
0
COPT
Bit 0
COPCLKS
COPW
0
ACIC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
—
—
—
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
—
—
—
T2CH1PS T2CH0PS T1CH1PS T1CH0PS
SDIDH
SDIDL
Reserved
SPMSC1
—
—
—
—
—
LVWF
LVWACK
LVWIE
LVDRE
LVDSE
LVDE
0
BGBE
SPMSC2
0
0
LVDV
LVWV
PPDF
PPDACK
—
PPDC
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 15
14
13
12
11
10
9
Bit 8
DBGCAH
DBGCAL
DBGCBH
DBGCBL
DBGFH
DBGFL
DBGC
DBGT
DBGS
Reserved
FCDIV
FOPT
Reserved
FCNFG
FPROT
FSTAT
FCMD
Reserved
PTAPE
PTASE
PTADS
Reserved
PTASC
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
DBGEN
ARM
TAG
BRKEN
RWA
RWAEN
RWB
RWBEN
TRGSEL
BEGIN
0
0
TRG3
TRG2
TRG1
TRG0
AF
BF
ARMF
0
CNT3
CNT2
CNT1
CNT0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DIVLD
PRDIV8
KEYEN
FNORED
0
0
0
0
—
—
—
—
—
—
—
0
0
KEYACC
0
0
0
0
DIV
SEC
FPS
FCBEF
FCCF
FPVIOL
—
0
FPDIS
FACCERR
0
FBLANK
0
0
FCMD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PTAPE7
PTAPE6
—
—
PTAPE3
PTAPE2
PTAPE1
PTAPE0
PTASE7
PTASE6
—
—
PTASE3
PTASE2
PTASE1
PTASE0
PTADS7
PTADS6
—
—
PTADS3
PTADS2
PTADS1
PTADS0
—
—
—
—
—
—
—
—
0
0
0
0
PTAIF
PTAACK
PTAIE
PTAMOD
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
45
Chapter 4 Memory
Table 4-3. High-Page Register Summary (Sheet 2 of 2)
Address
Register Name
0x1845
0x1846
0x1847
0x1848
0x1849
0x184A
0x184B
0x184C
0x184D
0x184E
0x184F
0x1850
PTAPS
PTAES
Reserved
PTBPE
PTBSE
PTBDS
Reserved
PTBSC
PTBPS
PTBES
Reserved
PTCPE
0x1851
0x1852
0x1853
0x1854
0x1855
0x1856
0x1857–
0x185F
PTCSE
PTCDS
GNGC
Reserved
Reserved
Reserved
Reserved
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
PTAPS3
PTAPS2
PTAPS1
PTAPS0
0
0
0
0
PTAES3
PTAES2
PTAES1
PTAES0
—
—
—
—
—
—
—
—
PTBPE7
PTBPE6
PTBPE5
PTBPE4
PTBPE3
PTBPE2
PTBPE1
PTBPE0
PTBSE7
PTBSE6
PTBSE5
PTBSE4
PTBSE3
PTBSE2
PTBSE1
PTBSE0
PTBDS7
PTBDS6
PTBDS5
PTBDS4
PTBDS3
PTBDS2
PTBDS1
PTBDS0
—
—
—
—
—
—
—
—
0
0
0
0
PTBIF
PTBACK
PTBIE
PTBMOD
0
0
0
0
PTBPS3
PTBPS2
PTBPS1
PTBPS0
0
0
0
0
PTBES3
PTBES2
PTBES1
PTBES0
—
—
—
—
—
—
—
—
PTCPE7
PTCPE6
PTCPE5
PTCPE4
PTCPE3
PTCPE2
PTCPE1
PTCPE0
PTCSE7
PTCSE6
PTCSE5
PTCSE4
PTCSE3
PTCSE2
PTCSE1
PTCSE0
PTCDS7
PTCDS6
PTCDS5
PTCDS4
PTCDS3
PTCDS2
PTCDS1
PTCDS0
GNGPS7
GNGPS6
GNGPS5
GNGPS4
GNGPS3
GNGPS2
GNGPS1
GNGEN
—
—
—
—
—
1
1
1
—
—
—
—
—
1
1
1
—
—
—
—
—
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MC9S08SG32 Data Sheet, Rev. 8
46
Freescale Semiconductor
Chapter 4 Memory
Nonvolatile FLASH registers, shown in Table 4-4, are located in the FLASH memory. These registers
include an 8-byte backdoor key, NVBACKKEY, which can be used to gain access to secure memory
resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the
FLASH memory are transferred into corresponding FPROT and FOPT working registers in the high-page
registers to control security and block protection options.
Table 4-4. Nonvolatile Register Summary
Address
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
FTRIM
—
—
—
—
—
—
0xFFAE
0xFFAF
0xFFB0 –
0xFFB7
0xFFB8 –
0xFFBC
0xFFBD
NVFTRIM
NVTRIM
NVBACKKEY
0
Reserved
—
—
0xFFBE
0xFFBF
Reserved
NVOPT
TRIM
8-Byte Comparison Key
—
—
—
—
NVPROT
—
—
—
—
FPS
FPDIS
—
—
—
—
—
—
KEYEN
FNORED
0
0
0
0
—
—
SEC
Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily
disengage memory security. This key mechanism can be accessed only through user code running in secure
memory. (A security key cannot be entered directly through background debug commands.) This security
key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the
only way to disengage security is by mass erasing the FLASH if needed (normally through the background
debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset,
program the security bits (SEC) to the unsecured state (1:0).
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
47
Chapter 4 Memory
4.4
RAM
The MC9S08SG32 Series includes static RAM. The locations in RAM below 0x0100 can be accessed
using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit
manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed
program variables in this area of RAM is preferred.
The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on the
contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage
does not drop below the minimum value for RAM retention (VRAM).
For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the
MC9S08SG32 Series, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct
page RAM can be used for frequently accessed RAM variables and bit-addressable program variables.
Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated
to the highest address of the RAM in the Freescale Semiconductor-provided equate file).
LDHX
TXS
#RamLast+1
;point one past RAM
;SP fADCK
xx
0
17 ADCK cycles
Subsequent continuous 10-bit;
fBUS > fADCK
xx
0
20 ADCK cycles
Subsequent continuous 8-bit;
fBUS > fADCK/11
xx
1
37 ADCK cycles
Subsequent continuous 10-bit;
fBUS > fADCK/11
xx
1
40 ADCK cycles
The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.
The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For
example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1
ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:
Conversion time =
23 ADCK cyc
8 MHz/1
+
5 bus cyc
8 MHz
= 3.5 μs
Number of bus cycles = 3.5 μs x 8 MHz = 28 cycles
NOTE
The ADCK frequency must be between fADCK minimum and fADCK
maximum to meet ADC specifications.
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
141
Chapter 9 Analog-to-Digital Converter (S08ADC10V1)
9.4.5
Automatic Compare Function
The compare function is enabled by the ACFE bit. The compare function can be configured to check for
an upper or lower limit. After the input is sampled and converted, the compare value (ADCCVH and
ADCCVL) is subtracted from the conversion result. When comparing to an upper limit (ACFGT = 1), if
the conversion result is greater-than or equal-to the compare value, COCO is set. When comparing to a
lower limit (ACFGT = 0), if the result is less than the compare value, COCO is set. An ADC interrupt is
generated upon the setting of COCO if the ADC interrupt is enabled (AIEN = 1).
The subtract operation of two positive values (the conversion result less the compare value) results in a
signed value that is 1-bit wider than the bit-width of the two terms. The final value transferred to the
ADCRH and ADCRL registers is the result of the subtraction operation, excluding the sign bit. The value
of the sign bit can be derived based on ACFGT control setting. When ACFGT=1, the sign bit of any value
stored in ADCRH and ADCRL is always 0, indicating a positive result for the subtract operation. When
ACFGT = 1, the sign bit of any result is always 1, indicating a negative result for the subtract operation.
Upon completion of a conversion while the compare function is enabled, if the compare condition is not
true, COCO is not set and no data is transferred to the result registers.
NOTE
The compare function can monitor the voltage on a channel while the MCU
is in wait or stop3 mode. The ADC interrupt wakes the MCU when the
compare condition is met.
An example of compare operation eases understanding of the compare feature. If the ADC is configured
for 10-bit operation, ACFGT=0, and ADCCVH:ADCCVL= 0x200, then a conversion result of 0x080
causes the compare condition to be met and the COCO bit is set. A value of 0x280 is stored in
ADCRH:ADCRL. This is signed data without the sign bit and must be combined with a derived sign bit
to have meaning. The value stored in ADCRH:ADCRL is calculated as follows.
The value to interpret from the data is (Result – Compare Value) = (0x080 – 0x200) = –0x180. A standard
method for handling subtraction is to convert the second term to its 2’s complement, and then add the two
terms. First calculate the 2’s complement of 0x200 by complementing each bit and adding 1. Note that
prior to complementing, a sign bit of 0 is added so that the 10-bit compare value becomes a 11-bit signed
value that is always positive.
%101 1111 1111
+
B) — A trigger occurs when the address is either less than
the value in comparator A or greater than the value in comparator B.
MC9S08SG32 Data Sheet, Rev. 8
282
Freescale Semiconductor
Chapter 17 Development Support
17.3.6
Hardware Breakpoints
The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions
described in Section 17.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the
CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a
force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction
queue. If a tagged opcode reaches the end of the pipe, the CPU executes a BGND instruction to go to active
background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to
finish the current instruction and then go to active background mode.
If the background mode has not been enabled (ENBDM = 1) by a serial WRITE_CONTROL command
through the BKGD pin, the CPU will execute an SWI instruction instead of going to active background
mode.
17.4
Register Definition
This section contains the descriptions of the BDC and DBG registers and control bits.
Refer to the high-page register summary in the device overview chapter of this data sheet for the absolute
address assignments for all DBG registers. This section refers to registers and control bits only by their
names. A Freescale-provided equate or header file is used to translate these names into the appropriate
absolute addresses.
17.4.1
BDC Registers and Control Bits
The BDC has two registers:
• The BDC status and control register (BDCSCR) is an 8-bit register containing control and status
bits for the background debug controller.
• The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address.
These registers are accessed with dedicated serial BDC commands and are not located in the memory
space of the target MCU (so they do not have addresses and cannot be accessed by user programs).
Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written
at any time. For example, the ENBDM control bit may not be written while the MCU is in active
background mode. (This prevents the ambiguous condition of the control bit forbidding active background
mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS,
WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial
BDC command. The clock switch (CLKSW) control bit may be read or written at any time.
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
283
Chapter 17 Development Support
17.4.1.1
BDC Status and Control Register (BDCSCR)
This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL)
but is not accessible to user programs because it is not located in the normal memory map of the MCU.
7
R
6
5
4
3
BKPTEN
FTS
CLKSW
BDMACT
ENBDM
2
1
0
WS
WSF
DVF
W
Normal
Reset
0
0
0
0
0
0
0
0
Reset
inActive
BDM:
1
1
0
0
1
0
0
0
= Unimplemented or Reserved
Figure 17-5. BDC Status and Control Register (BDCSCR)
Table 17-2. BDCSCR Register Field Descriptions
Field
Description
7
ENBDM
Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly
after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal
reset clears it.
0 BDM cannot be made active (non-intrusive commands still allowed)
1 BDM can be made active to allow active background mode commands
6
BDMACT
Background Mode Active Status — This is a read-only status bit.
0 BDM not active (user application program running)
1 BDM active and waiting for serial commands
5
BKPTEN
BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select)
control bit and BDCBKPT match register are ignored.
0 BDC breakpoint disabled
1 BDC breakpoint enabled
4
FTS
3
CLKSW
Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the
BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register
causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue,
the CPU enters active background mode rather than executing the tagged opcode.
0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that
instruction
1 Breakpoint match forces active background mode at next instruction boundary (address need not be an
opcode)
Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC
clock source.
0 Alternate BDC clock source
1 MCU bus clock
MC9S08SG32 Data Sheet, Rev. 8
284
Freescale Semiconductor
Chapter 17 Development Support
Table 17-2. BDCSCR Register Field Descriptions (continued)
Field
Description
2
WS
Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function.
However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active
background mode where all BDC commands work. Whenever the host forces the target MCU into active
background mode, the host should issue a READ_STATUS command to check that BDMACT = 1 before
attempting other BDC commands.
0 Target CPU is running user application code or in active background mode (was not in wait or stop mode when
background became active)
1 Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or stop to
active background mode
1
WSF
Wait or Stop Failure Status — This status bit is set if a memory access command failed due to the target CPU
executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a
BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command
that failed, then return to the user program. (Typically, the host would restore CPU registers and stack values and
re-execute the wait or stop instruction.)
0 Memory access did not conflict with a wait or stop instruction
1 Memory access command failed because the CPU entered wait or stop mode
0
DVF
Data Valid Failure Status — This status bit is not used in the MC9S08SG32 Series because it does not have
any slow access memory.
0 Memory access did not conflict with a slow memory access
1 Memory access command failed because CPU was not finished with a slow memory access
17.4.1.2
BDC Breakpoint Match Register (BDCBKPT)
This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS
control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC
commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is
not accessible to user programs because it is not located in the normal memory map of the MCU.
Breakpoints are normally set while the target MCU is in active background mode before running the user
application program. For additional information about setup and use of the hardware breakpoint logic in
the BDC, refer to Section 17.2.4, “BDC Hardware Breakpoint.”
17.4.2
System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial background mode command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
285
Chapter 17 Development Support
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
BDFR1
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
1
BDFR is writable only through serial background mode debug commands, not from user programs.
Figure 17-6. System Background Debug Force Reset Register (SBDFR)
Table 17-3. SBDFR Register Field Description
Field
Description
0
BDFR
Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.
17.4.3
DBG Registers and Control Bits
The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control
and status registers. These registers are located in the high register space of the normal memory map so
they are accessible to normal application programs. These registers are rarely if ever accessed by normal
user application programs with the possible exception of a ROM patching mechanism that uses the
breakpoint logic.
17.4.3.1
Debug Comparator A High Register (DBGCAH)
This register contains compare value bits for the high-order eight bits of comparator A. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.2
Debug Comparator A Low Register (DBGCAL)
This register contains compare value bits for the low-order eight bits of comparator A. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.3
Debug Comparator B High Register (DBGCBH)
This register contains compare value bits for the high-order eight bits of comparator B. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.4
Debug Comparator B Low Register (DBGCBL)
This register contains compare value bits for the low-order eight bits of comparator B. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
MC9S08SG32 Data Sheet, Rev. 8
286
Freescale Semiconductor
Chapter 17 Development Support
17.4.3.5
Debug FIFO High Register (DBGFH)
This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have
no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte of
each FIFO word, so this register is not used and will read 0x00.
Reading DBGFH does not cause the FIFO to shift to the next word. When reading 16-bit words out of the
FIFO, read DBGFH before reading DBGFL because reading DBGFL causes the FIFO to advance to the
next word of information.
17.4.3.6
Debug FIFO Low Register (DBGFL)
This register provides read-only access to the low-order eight bits of the FIFO. Writes to this register have
no meaning or effect.
Reading DBGFL causes the FIFO to shift to the next available word of information. When the debug
module is operating in event-only modes, only 8-bit data is stored into the FIFO (high-order half of each
FIFO word is unused). When reading 8-bit words out of the FIFO, simply read DBGFL repeatedly to get
successive bytes of data from the FIFO. It isn’t necessary to read DBGFH in this case.
Do not attempt to read data from the FIFO while it is still armed (after arming but before the FIFO is filled
or ARMF is cleared) because the FIFO is prevented from advancing during reads of DBGFL. This can
interfere with normal sequencing of reads from the FIFO.
Reading DBGFL while the debugger is not armed causes the address of the most-recently fetched opcode
to be stored to the last location in the FIFO. By reading DBGFH then DBGFL periodically, external host
software can develop a profile of program execution. After eight reads from the FIFO, the ninth read will
return the information that was stored as a result of the first read. To use the profiling feature, read the FIFO
eight times without using the data to prime the sequence and then begin using the data to get a delayed
picture of what addresses were being executed. The information stored into the FIFO on reads of DBGFL
(while the FIFO is not armed) is the address of the most-recently fetched opcode.
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
287
Chapter 17 Development Support
17.4.3.7
Debug Control Register (DBGC)
This register can be read or written at any time.
7
6
5
4
3
2
1
0
DBGEN
ARM
TAG
BRKEN
RWA
RWAEN
RWB
RWBEN
0
0
0
0
0
0
0
0
R
W
Reset
Figure 17-7. Debug Control Register (DBGC)
Table 17-4. DBGC Register Field Descriptions
Field
Description
7
DBGEN
Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
0 DBG disabled
1 DBG enabled
6
ARM
Arm Control — Controls whether the debugger is comparing and storing information in the FIFO. A write is used
to set this bit (and ARMF) and completion of a debug run automatically clears it. Any debug run can be manually
stopped by writing 0 to ARM or to DBGEN.
0 Debugger not armed
1 Debugger armed
5
TAG
Tag/Force Select — Controls whether break requests to the CPU will be tag or force type requests. If
BRKEN = 0, this bit has no meaning or effect.
0 CPU breaks requested as force type requests
1 CPU breaks requested as tag type requests
4
BRKEN
Break Enable — Controls whether a trigger event will generate a break request to the CPU. Trigger events can
cause information to be stored in the FIFO without generating a break request to the CPU. For an end trace, CPU
break requests are issued to the CPU when the comparator(s) and R/W meet the trigger requirements. For a
begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL does not affect the timing of
CPU break requests.
0 CPU break requests not enabled
1 Triggers cause a break request to the CPU
3
RWA
R/W Comparison Value for Comparator A — When RWAEN = 1, this bit determines whether a read or a write
access qualifies comparator A. When RWAEN = 0, RWA and the R/W signal do not affect comparator A.
0 Comparator A can only match on a write cycle
1 Comparator A can only match on a read cycle
2
RWAEN
Enable R/W for Comparator A — Controls whether the level of R/W is considered for a comparator A match.
0 R/W is not used in comparison A
1 R/W is used in comparison A
1
RWB
R/W Comparison Value for Comparator B — When RWBEN = 1, this bit determines whether a read or a write
access qualifies comparator B. When RWBEN = 0, RWB and the R/W signal do not affect comparator B.
0 Comparator B can match only on a write cycle
1 Comparator B can match only on a read cycle
0
RWBEN
Enable R/W for Comparator B — Controls whether the level of R/W is considered for a comparator B match.
0 R/W is not used in comparison B
1 R/W is used in comparison B
MC9S08SG32 Data Sheet, Rev. 8
288
Freescale Semiconductor
Chapter 17 Development Support
17.4.3.8
Debug Trigger Register (DBGT)
This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired
to 0s.
7
6
TRGSEL
BEGIN
0
0
R
5
4
0
0
3
2
1
0
TRG3
TRG2
TRG1
TRG0
0
0
0
0
W
Reset
0
0
= Unimplemented or Reserved
Figure 17-8. Debug Trigger Register (DBGT)
Table 17-5. DBGT Register Field Descriptions
Field
Description
7
TRGSEL
Trigger Type — Controls whether the match outputs from comparators A and B are qualified with the opcode
tracking logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate
through the opcode tracking logic and a trigger event is only signalled to the FIFO logic if the opcode at the match
address is actually executed.
0 Trigger on access to compare address (force)
1 Trigger if opcode at compare address is executed (tag)
6
BEGIN
Begin/End Trigger Select — Controls whether the FIFO starts filling at a trigger or fills in a circular manner until
a trigger ends the capture of information. In event-only trigger modes, this bit is ignored and all debug runs are
assumed to be begin traces.
0 Data stored in FIFO until trigger (end trace)
1 Trigger initiates data storage (begin trace)
3:0
TRG[3:0]
Select Trigger Mode — Selects one of nine triggering modes, as described below.
0000 A-only
0001 A OR B
0010 A Then B
0011 Event-only B (store data)
0100 A then event-only B (store data)
0101 A AND B data (full mode)
0110 A AND NOT B data (full mode)
0111 Inside range: A ≤ address ≤ B
1000 Outside range: address < A or address > B
1001 – 1111 (No trigger)
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
289
Chapter 17 Development Support
17.4.3.9
Debug Status Register (DBGS)
This is a read-only status register.
R
7
6
5
4
3
2
1
0
AF
BF
ARMF
0
CNT3
CNT2
CNT1
CNT0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 17-9. Debug Status Register (DBGS)
Table 17-6. DBGS Register Field Descriptions
Field
Description
7
AF
Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A
condition was met since arming.
0 Comparator A has not matched
1 Comparator A match
6
BF
Trigger Match B Flag — BF is cleared at the start of a debug run and indicates whether a trigger match B
condition was met since arming.
0 Comparator B has not matched
1 Comparator B match
5
ARMF
Arm Flag — While DBGEN = 1, this status bit is a read-only image of ARM in DBGC. This bit is set by writing 1
to the ARM control bit in DBGC (while DBGEN = 1) and is automatically cleared at the end of a debug run. A
debug run is completed when the FIFO is full (begin trace) or when a trigger event is detected (end trace). A
debug run can also be ended manually by writing 0 to ARM or DBGEN in DBGC.
0 Debugger not armed
1 Debugger armed
3:0
CNT[3:0]
FIFO Valid Count — These bits are cleared at the start of a debug run and indicate the number of words of valid
data in the FIFO at the end of a debug run. The value in CNT does not decrement as data is read out of the FIFO.
The external debug host is responsible for keeping track of the count as information is read out of the FIFO.
0000 Number of valid words in FIFO = No valid data
0001 Number of valid words in FIFO = 1
0010 Number of valid words in FIFO = 2
0011 Number of valid words in FIFO = 3
0100 Number of valid words in FIFO = 4
0101 Number of valid words in FIFO = 5
0110 Number of valid words in FIFO = 6
0111 Number of valid words in FIFO = 7
1000 Number of valid words in FIFO = 8
MC9S08SG32 Data Sheet, Rev. 8
290
Freescale Semiconductor
Appendix A
Electrical Characteristics
A.1
Introduction
This section contains electrical and timing specifications for the MC9S08SG32 Series of microcontrollers
available at the time of publication. The MC9S08SG32 Series includes both:
• Standard (STD)— devices that are standard-temperature rated. Table rows marked with a♦
indicate electrical characteristics that apply to these devices.
• AEC Grade 0 — devices that are high-temperature rated. Table rows marked with a♦ indicate
electrical characteristics that apply to AEC Grade 0 devices.
A.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table A-1. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved through the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
A.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table A-2 may affect device reliability or cause
permanent damage to the device. For functional operating conditions, refer to the remaining tables in this
section.
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
291
Appendix A Electrical Characteristics
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable
pull-up resistor associated with the pin is enabled.
Table A-2. Absolute Maximum Ratings
Rating
AEC Grade 0
#
Standard
Temp Rated
♦
♦
V
♦
♦
♦
♦
± 25
mA
♦
♦
–55 to 150
°C
♦
♦
Symbol
Value
Unit
1
Supply voltage
VDD
–0.3 to +5.8
V
2
Maximum current into VDD
IDD
120
mA
3
Digital input voltage
VIn
–0.3 to VDD + 0.3
4
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
5
Storage temperature range
Tstg
1
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values.
2 All functional non-supply pins except RESET are internally clamped to V
SS and VDD.
3 Power supply must maintain regulation within operating V
DD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if the clock rate is very low (which would reduce overall power consumption).
MC9S08SG32 Data Sheet, Rev. 8
292
Freescale Semiconductor
Appendix A Electrical Characteristics
A.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the
MCU design. To take PI/O into account in power calculations, determine the difference between actual pin
voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high
pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table A-3. Thermal Characteristics
C
—
Rating
Symbol
Value
Unit
AEC Grade 0
#
Standard
Temp
Rated
Operating temperature range
(packaged)
Temperature Code W
–40 to 150
—
Temperature Code J
–40 to 140
—
1
Temperature Code M
TA
°C
–40 to 125
Temperature Code V
–40 to 105
Temperature Code C
–40 to 85
♦
♦
♦
♦
♦
—
—
—
Thermal resistance, Single-layer board
D
Airflow @200
ft/min
Natural
Convection
71
91
20-pin TSSOP
94
114
16-pin TSSOP
108
133
Airflow @200
ft/min
Natural
Convection
51
58
20-pin TSSOP
68
75
16-pin TSSOP
78
92
28-pin TSSOP
θJA
2
°C/W
♦
♦
♦
♦
♦
♦
♦
♦
♦
—
♦
Thermal resistance, Four-layer board
D
28-pin TSSOP
3
θJA
°C/W
135
4
D
Maximum junction temperature
°C
TJ
155
—
—
♦
—
♦
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
293
Appendix A Electrical Characteristics
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Eqn. A-1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O VSS
VIH
5V
0.65 x VDD
—
—
V
3V
0.7 x VDD
—
—
V
♦ ♦
♦ ♦
♦ ♦
♦ —
— ♦
♦ ♦
♦ ♦
5V
—
—
0.35 x
VDD
V
♦ ♦
3V
—
—
0.35 x
VDD
V
♦ ♦
—
0.06 x VDD
—
—
V
♦ ♦
C voltage
5
5 V, ILoad = –20
mA
♦ ♦
♦ —
— ♦
♦ ♦
♦ ♦
high-drive strength
C
3
Symbol
P
AllI/O pins
5 V, ILoad = 10 mA
—
—
0.8
V
C
high-drive strength
3 V, ILoad = 5 mA
—
—
0.8
V
0
—
100
mA
0
—
50
mA
Output
D low
current
Max total IOL for
all ports
P Input high voltage; all digital inputs
6
C
P
Input low voltage; all digital inputs
VIL
7
C
8
AEC Grade 0
#
Standard
Temp
Rated
C Input hysteresis
Vhys
MC9S08SG32 Data Sheet, Rev. 8
296
Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-6. DC Characteristics (continued)
C
Characteristic
Symbol
9
P Input leakage current (per pin)
|IIn|
Condition
Min
Typ1
Max
Unit
AEC Grade 0
#
Standard
Temp
Rated
VIn = VDD or VSS
—
—
1
μA
♦
—
temperature > 125
C
—
—
2
μA
—
♦
VIn = VDD or VSS;
temperature
—
—
1
μA
♦
—
VIn = VDD or VSS
—
—
2
μA
♦
—
—
0.2
2
μA
—
♦
Hi-Z (off-state) leakage current (per
pin)
input/output port pins
P
|IOZ|
RESET
10
VIn = VDD or VSS;
temperature > 125
C
Input/Output Port pins
Pullup or Pulldown2 resistors;
when enabled
11
♦ ♦
—
17
37
52
kΩ
—
17
37
52
kΩ
VIN > VDD
0
—
2
mA
VIN < VSS,
0
—
–0.2
mA
♦
♦
♦
♦
♦
Total MCU limit,
includes
VIN > VDD
0
—
25
mA
♦ ♦
sum of all stressed pins
VIN < VSS,
0
—
–5
mA
CIn
—
—
—
8
pF
I/O pins R ,R
PU PD
P
RESET3
C
RPU
DC injection current 4, 5, 6, 7
Single pin limit
12 D
IIC
13 D Input Capacitance, all pins
14 D RAM retention voltage
VRAM
—
—
0.6
1.0
V
15 D POR re-arm
voltage8
VPOR
—
0.9
1.4
2.0
V
16 D POR re-arm
time9
tPOR
—
10
—
—
μs
3.9
4.0
4.0
4.1
4.1
4.2
V
3.88
3.98
4.0
4.1
4.12
4.22
V
Low-voltage detection threshold
—
high range
17
P
VDD falling
VDD rising
—
VLVD1
—
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
—
—
♦
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
297
Appendix A Electrical Characteristics
Table A-6. DC Characteristics (continued)
C
Characteristic
Symbol
Low-voltage detection threshold
—
low range
18
P
VDD falling
VDD rising
Low-voltage warning threshold —
high range 1
19
P
VDD falling
VDD rising
Low-voltage warning threshold —
high range 0
20
P
VDD falling
VDD rising
Low-voltage warning threshold
low range 1
21
P
VDD falling
VDD rising
Low-voltage warning threshold —
low range 0
22
P
VDD falling
VDD rising
23
24
Low-voltage inhibit reset/recover
T hysteresis
P Bandgap Voltage Reference10
VLVD0
VLVW3
VLVW2
VLVW1
VLVW0
Vhys
VBG
Min
Typ1
Max
Unit
2.48
2.54
2.56
2.62
2.64
2.70
V
4.5
4.6
4.6
4.7
4.7
4.8
V
4.48
4.58
4.6
4.7
4.72
4.82
4.2
4.3
4.3
4.4
4.4
4.5
4.18
4.28
4.3
4.4
4.42
4.52
2.84
2.90
2.92
2.98
2.66
2.72
5V
3V
Condition
—
—
—
—
—
AEC Grade 0
#
Standard
Temp
Rated
♦ ♦
♦
—
—
♦
♦
—
V
—
♦
3.00
3.06
V
♦ ♦
2.74
2.80
2.82
2.88
V
♦ ♦
—
100
—
mV
—
60
—
mV
1.18
1.202
1.21
V
1.17
1.202
1.22
V
V
V
—
♦ ♦
♦ ♦
♦ —
— ♦
1
Typical values are measured at 25°C. Characterized, not tested
When IRQ or a pin interrupt is configured to detect rising edges, pulldown resistors are used in place of pullup resistors.
3 The specified resistor value is the actual value internal to the device. The pullup value may measure higher when measured
externally on the pin.
2
MC9S08SG32 Data Sheet, Rev. 8
298
Freescale Semiconductor
Appendix A Electrical Characteristics
4
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
5
All functional non-supply pins except RESET are internally clamped to VSS and VDD.
6
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
7
The RESET pin does not have a clamp diode to VDD. Do not drive this pin above VDD.
8
Maximum is highest voltage that POR is guaranteed.
9
Simulated, not tested.
10
Factory trimmed at VDD = 5.0 V, Temp = 25°C.
2
1.0
150˚C
25˚C
–40˚C
0.8
VOL (V)
VOL (V)
1.5
1
0.5
0
150˚C
25˚C
–40˚C
Max 1.5V@20mA
Max 0.8V@5mA
0.6
0.4
0.2
0
5
10
15
IOL (mA)
a) VDD = 5V, High Drive
20
25
0
0
2
4
6
IOL (mA)
b) VDD = 3V, High Drive
8
10
Figure A-1. Typical VOL vs IOL, High Drive Strength
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
299
Appendix A Electrical Characteristics
2
1.0
150˚C
25˚C
–40˚C
0.8
VOL (V)
VOL (V)
1.5
1
0.5
0
150˚C
25˚C
–40˚C
Max 1.5V@4mA
Max 0.8V@1mA
0.6
0.4
0.2
0
1
2
3
IOL (mA)
a) VDD = 5V, Low Drive
4
0
5
0
0.4
0.8
1.2
IOL (mA)
b) VDD = 3V, Low Drive
1.6
2.0
Figure A-2. Typical VOL vs IOL, Low Drive Strength
2
1.0
150˚C
25˚C
–40˚C
0.8
VDD – VOH (V)
VDD – VOH (V)
1.5
1
0.5
0
150˚C
25˚C
–40˚C
Max 1.5V@20mA
Max 0.8V@5mA
0.6
0.4
0.2
0
–5
–10
–15
–20
IOH (mA)
a) VDD = 5V, High Drive
–25
0
0
–2
–4
–6
–8
IOH (mA)
b) VDD = 3V, High Drive
–10
Figure A-3. Typical VDD – VOH vs IOH, High Drive Strength
MC9S08SG32 Data Sheet, Rev. 8
300
Freescale Semiconductor
Appendix A Electrical Characteristics
2
1.0
150˚C
25˚C
–40˚C
0.8
VDD – VOH (V)
VDD – VOH (V)
1.5
1
0.5
0
150˚C
25˚C
–40˚C
Max 1.5V@4mA
Max 0.8V@1mA
0.6
0.4
0.2
0
–1
–2
–3
IOH (mA)
a) VDD = 5V, Low Drive
–4
–5
0
0
–0.4
–0.8
–1.2
–1.6
IOH (mA)
b) VDD = 3V, Low Drive
–2.0
Figure A-4. Typical VDD – VOH vs IOH, Low Drive Strength
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
301
Appendix A Electrical Characteristics
A.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table A-7. Supply Current Characteristics
Temp Rated
C
1
C
P
2
C
C
3
C
Parameter
Symbol
3
Run supply current measured at
(CPU clock = 4 MHz, fBus = 2 MHz)
Run supply current3 measured at
(CPU clock = 16 MHz, fBus = 8 MHz)
RIDD
RIDD
4
Run supply current measured at
(CPU clock = 32 MHz, fBus = 16MHz)
RIDD
VDD
(V)
Typ1
Max2
Unit
5
1.4
3
mA
3
1.3
2.5
5
4.7
3
AEC
Grade 0
C
Standard
#
mA
♦
♦
♦
♦
7.5
mA
♦
♦
4.6
7
mA
5
8.9
10
mA
3
8.7
9.6
mA
♦
♦
♦
♦
♦
♦
Stop3 mode supply current
4
C
–40°C (C,V, and M suffix)
0.96
–
μA
P
25°C (All parts)
1.3
–
μA
P5
85°C (C suffix only)
16.9
35
μA
P5
105°C (V suffix only)
37
90
μA
P5
125°C (M suffix only)
84
150
μA
C
–40°C (C,V, and M suffix)
0.85
–
μA
P
25°C (All parts)
1.2
–
μA
P5
85°C (C suffix only)
14.8
30
μA
P5
105°C (V suffix only)
32.7
80
μA
P5
125°C (M suffix only)
75
130
μA
5
S3IDD
3
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
—
—
—
—
—
—
—
—
—
—
MC9S08SG32 Data Sheet, Rev. 8
302
Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-7. Supply Current Characteristics (continued)
C
Parameter
Symbol
VDD
(V)
Typ1
Max2
Unit
AEC
Grade 0
#
Standard
Temp Rated
Stop2 mode supply current
5
–40°C (C,M, and V suffix)
0.94
–
μA
P
25°C (All parts)
1.25
–
μA
P5
85°C (C suffix only)
13.4
30
μA
P5
105°C (V suffix only)
30
65
μA
P5
125°C (M suffix only)
65
120
μA
C
–40°C (C,M, and V suffix)
0.83
–
μA
P
25°C (All parts)
1.1
–
μA
P5
85°C (C suffix only)
11.5
25
μA
P5
105°C (V suffix only)
25
55
μA
P5
125°C (M suffix only)
57
100
μA
5
300
500
nA
3
300
500
nA
5
110
180
μA
3
90
160
μA
♦
♦
♦
♦
♦
♦
♦
♦
♦
5,3
5
8
μA
♦
RTC adder to stop2 or stop36
6
5
S2IDD
3
S23IDDR
C
TI
LVD adder to stop3 (LVDE = LVDSE = 1)
7
8
1
2
3
4
5
6
7
♦
♦
♦
♦
♦
C
C
C
S3IDDLVD
Adder to stop3 for oscillator enabled7
(EREFSTEN =1)
S3IDDOS
C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typical values are based on characterization data at 25°C. See Figure A-5 through Figure A-7 for typical curves across
temperature and voltage.
Max values in this column apply for the full operating temperature range of the device unless otherwise noted.
All modules except ADC active, ICS configured for FBELP, and does not include any dc loads on port pins
All modules except ADC active, ICS configured for FEI, and does not include any dc loads on port pins
Stop Currents are tested in production for 25 Con all parts. Tests at other temperatures depend upon the part number suffix
and maturity of the product. Freescale may eliminate a test insertion at a particular temperature from the production test flow
once sufficient data has been collected and is approved.
Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait
mode.
Values given under the following conditions: low range operation (RANGE = 0) with a 32.768kHz crystal and low power mode
(HGO = 0).
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
303
Appendix A Electrical Characteristics
12
FEI
FBELP
10
Run IDD (mA)
8
6
4
2
0
0 1 2
4
8
20
16
fbus (MHz)
Figure A-5. Typical Run IDD vs. Bus Frequency (VDD = 5V)
6
RUN
5
Run IDD (mA)
4
3
WAIT
2
1
0
–40
0
25
Temperature (˚C)
85
105
125
150
Figure A-6. Typical Run and Wait IDD vs. Temperature (VDD = 5V; fbus = 8MHz)
MC9S08SG32 Data Sheet, Rev. 8
304
Freescale Semiconductor
Appendix A Electrical Characteristics
STOP2
STOP3
STOP IDD ( A)
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
–40
0
25
Temperature (˚C)
85
105
125
150
Figure A-7. Typical Stop IDD vs. Temperature (VDD = 5V)
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
305
Appendix A Electrical Characteristics
A.8
External Oscillator (XOSC) Characteristics
Table A-8. Oscillator Electrical Specifications (Temperature Range = –40 to 125°C Ambient)
Symbol
Min
Typ1
Max
Unit
flo
32
—
38.4
kHz
fhi
1
—
5
MHz
High range (RANGE = 1, HGO = 1) FBELP mode
fhi-hgo
1
—
16
MHz
High range (RANGE = 1, HGO = 0) FBELP mode
fhi-lp
1
—
8
MHz
C
Rating
AEC Grade 0
#
Standard
Temp
Rated
♦
♦
♦
♦
♦
♦
♦
♦
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
1
2
C
High range (RANGE = 1) FEE or FBE mode
2
C1, C2
— Load capacitors
See crystal or resonator
manufacturer’s recommendation.
Feedback resistor
3
—
Low range (32 kHz to 100 kHz)
RF
—
10
—
MΩ
—
1
—
MΩ
Low range, low gain (RANGE = 0, HGO = 0)
—
0
—
kΩ
Low range, high gain (RANGE = 0, HGO = 1)
—
100
—
kΩ
—
0
—
kΩ
≥ 8 MHz
—
0
0
kΩ
4 MHz
—
0
10
kΩ
1 MHz
—
0
20
kΩ
t
CSTL-LP
—
200
—
ms
CSTL-HGO
—
400
—
ms
t
CSTH-LP
—
5
—
ms
CSTH-HGO
—
20
—
ms
0.03125
—
5
MHz
0
—
40
MHz
0
—
36
MHz
High range (1 MHz to 16 MHz)
♦ ♦
♦ ♦
Series resistor
High range, low gain (RANGE = 1, HGO = 0)
4
—
RS
High range, high gain (RANGE = 1, HGO = 1)
♦ ♦
♦ ♦
♦ ♦
♦ ♦
♦ ♦
♦ ♦
Crystal start-up time 3
Low range, low gain (RANGE = 0, HGO = 0)
5
T
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO =
t
0)4
High range, high gain (RANGE = 1, HGO = 1)4
t
♦
♦
♦
♦
♦
♦
♦
♦
Square wave input clock frequency (EREFS = 0,
ERCLKEN = 1)
FEE or FBE mode 2
6
T
FBELP mode
fextal
FBELP mode
♦ ♦
♦ —
— ♦
MC9S08SG32 Data Sheet, Rev. 8
306
Freescale Semiconductor
Appendix A Electrical Characteristics
1
Typical data was characterized at 5.0 V, 25°C or is recommended value.
The input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz.
3
Characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve specifications.
4
4 MHz crystal
2
EXTAL
MCU
XTAL
RF
C1
Crystal or Resonator
RS
C2
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
307
Appendix A Electrical Characteristics
A.9
Internal Clock Source (ICS) Characteristics
Table A-9. ICS Frequency Specifications (Temperature Range = –40 to 125°C Ambient)
Symbol
Min
Typical
Max
Unit
Standard
AEC Grade 0
Temp Rated
fint_ft
—
31.25
—
kHz
♦
♦
fint_ut
25
36
41.66
kHz
♦
♦
P Internal reference frequency — trimmed
fint_t
31.25
—
39.0625
kHz
4
D Internal reference startup time
tirefst
—
55
100
μs
♦
♦
♦
♦
5
DCO output frequency range —
— untrimmed1 value provided for reference:
fdco_ut = 1024 x fint_ut
fdco_ut
25.6
36.86
42.66
MHz
♦
♦
32
—
40
MHz
6
D DCO output frequency range — trimmed
fdco_t
32
—
36
MHz
♦
—
—
♦
#
C
Rating
1
Internal reference frequency — factory
P trimmed at VDD = 5 V and temperature =
25°C
2
T
3
Internal reference frequency —
untrimmed1
7
Resolution of trimmed DCO output
D frequency at fixed voltage and temperature Δfdco_res_t
(using FTRIM)
—
± 0.1
± 0.2
%fdco
♦
♦
8
Resolution of trimmed DCO output
D frequency at fixed voltage and temperature Δfdco_res_t
(not using FTRIM)
—
± 0.2
± 0.4
%fdco
♦
♦
—
%fdco
Δfdco_t
+ 0.5
– 1.0
± 1.5
♦
—
9
Total deviation of trimmed DCO output
P
frequency over voltage and temperature
—
+ 0.5
– 1.0
±3
%fdco
—
♦
10
Total deviation of trimmed DCO output
D frequency over fixed voltage and
temperature range of 0°C to 70 °C
Δfdco_t
—
± 0.5
±1
%fdco
♦
♦
11
D FLL acquisition time 2
tacquire
—
1
ms
♦
♦
12
D
CJitter
—
0.2
%fdco
♦
♦
DCO output clock long term jitter (over 2
ms interval) 3
0.02
1
TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
3
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
2
MC9S08SG32 Data Sheet, Rev. 8
308
Freescale Semiconductor
Deviation from Trimmed Frequency
Appendix A Electrical Characteristics
+2%
+1%
0
–1%
–2%
–40
0
25
Temperature (˚C)
85
105
125
150
Figure A-8. Typical Frequency Deviation vs Temperature (ICS Trimmed to 16MHz bus@25˚C, 5V, FEI)1
A.10
Analog Comparator (ACMP) Electricals
Table A-10. Analog Comparator Electrical Specifications
C
1
—
2
C/T
3
Rating
Symbol
Min
Typical
Max
Unit
VDD
2.7
—
5.5
V
Supply current (active)
IDDAC
—
20
35
μA
D
Analog input voltage
VAIN
VSS – 0.3
—
VDD
V
4
D
Analog input offset voltage
VAIO
—
20
40
mV
5
D
Analog Comparator hysteresis
VH
3.0
6.0
20.0
mV
6
D
Analog input leakage current
IALKG
—
—
1.0
μA
7
D
Analog Comparator initialization delay
tAINIT
—
—
1.0
μs
Supply voltage
AEC Grade 0
#
Standard
Temp Rated
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
1. Based on the average of several hundred units from a typical characterization lot.
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
309
Appendix A Electrical Characteristics
A.11
ADC Characteristics
Table A-11. ADC Operating Conditions
Characteristic
1
Supply voltage
2
Conditions
Absolute
Input Voltage
Symb
Min
Typ1
Max
Unit
VDDAD
2.7
—
5.5
V
♦ ♦
VADIN
VREFL
—
VREF
V
♦ ♦
3
Input
Capacitance
CADIN
—
4.5
5.5
pF
♦ ♦
4
Input
Resistance
RADIN
—
3
5
kΩ
♦ ♦
—
—
—
—
5
10
kΩ
♦ ♦
—
—
10
kΩ
♦ ♦
0.4
—
8.0
MHz
♦ ♦
0.4
—
4.0
MHz
♦ ♦
Analog Source
Resistance
5
10 bit mode
fADCK > 4MHz
fADCK < 4MHz
RAS
8 bit mode (all valid
fADCK)
6
1
H
Standard
#
AEC Grade 0
Temp
Rated
ADC
Conversion
Clock Freq.
High Speed (ADLPC=0)
Low Power (ADLPC=1)
fADCK
Comment
External to
MCU
Typical values assume VDDAD = VDD = 5.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
MC9S08SG32 Data Sheet, Rev. 8
310
Freescale Semiconductor
Appendix A Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
Pad
leakage
due to
input
protection
ZAS
RAS
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
RADIN
ADC SAR
ENGINE
+
VADIN
VAS
+
–
CAS
–
RADIN
INPUT PIN
INPUT PIN
RADIN
RADIN
INPUT PIN
CADIN
Figure A-9. ADC Input Impedance Equivalency Diagram
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
311
Appendix A Electrical Characteristics
Table A-12. ADC Characteristics
Characteristic
Conditions
ADLPC=1
ADLSMP=1
ADCO=1
ADLPC=1
ADLSMP=0
ADCO=1
C
Symb
Min
Typ1
Max
Unit
T
IDD +
IDDAD
—
133
—
μA
♦ ♦
ADC current
only
T
IDD +
IDDAD
—
218
—
μA
♦ ♦
ADC current
only
T
IDD +
IDDAD
—
327
—
μA
♦ ♦
ADC current
only
P
IDD +
IDDAD
—
0.58
2
1
mA
♦ ♦
ADC current
only
2
3.3
5
Standard
#
AEC Grade 0
Temp
Rated
Comment
1
Supply current
ADLPC=0
ADLSMP=1
ADCO=1
ADLPC=0
ADLSMP=0
ADCO=1
2
3
ADC
asynchronous
clock source
High speed (ADLPC=0)
Conversion
time (including
sample time)
Short sample
(ADLSMP=0)
Sample time
P
Low power (ADLPC=1)
D
Long sample
(ADLSMP=1)
fADACK
D
Long sample
(ADLSMP=1)
1.25
2
3.3
—
20
—
ADCK
cycles
tADC
Short sample
(ADLSMP=0)
4
MHz
—
40
—
—
3.5
—
ADCK
cycles
tADS
—
23.5
—
♦ ♦
♦ ♦
tADACK =
1/fADACK
♦ ♦
♦ ♦
♦ ♦
See ADC
Chapter for
conversion
time variances
♦ ♦
MC9S08SG32 Data Sheet, Rev. 8
312
Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-12. ADC Characteristics (continued)
Characteristic
Conditions
C
Symb
Min
Typ1
Max
—
±1
±2.5
Unit
AEC Grade 0
#
Standard
Temp
Rated
Comment
28-pin packages only
10-bit mode
Total
unadjusted
error (includes
quantization)
8-bit mode
P
2
ETUE
LSB
—
±0.5
±1
—
±.5
±3.5
♦ ♦
♦ ♦
20-pin packages
10-bit mode
5
P
8-bit mode
LSB2
ETUE
—
±0.7
±1.5
—
±.5
±3.5
♦
—
♦
—
16-pin and packages
10-bit mode
P
8-bit mode
Differential
Non-Linearity
6
10-bit mode
P
LSB2
ETUE
—
±0.7
±1.5
—
±0.5
±1.0
LSB2
DNL
8-bit mode
—
±0.3
±0.5
♦ ♦
♦ ♦
♦ ♦
♦ ♦
Monotonicity and No-Missing-Codes guaranteed
7
Integral
non-linearity
10-bit mode
—
T
8-bit mode
±0.5
±1.0
LSB2
INL
—
±0.3
±0.5
♦ ♦
♦ ♦
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
313
Appendix A Electrical Characteristics
Table A-12. ADC Characteristics (continued)
Characteristic
Conditions
C
Symb
P
EZS
Typ1
Max
Unit
—
±0.5
±1.5
LSB2
—
±0.5
±0.5
—
±1.5
±2.5
—
±0.5
±0.7
—
±1.5
±2.5
—
±0.5
±0.7
Min
AEC Grade 0
#
Standard
Temp
Rated
Comment
28-pin packages only
10-bit mode
Zero-scale
error
8-bit mode
♦ ♦
♦ ♦
20-pin packages
10-bit mode
8
P
EZS
8-bit mode
LSB2
♦
—
♦
—
16-pin packages
10-bit mode
8-bit mode
P
EZS
LSB2
♦ ♦
♦ ♦
MC9S08SG32 Data Sheet, Rev. 8
314
Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-12. ADC Characteristics (continued)
Characteristic
Conditions
C
Symb
Min
Typ1
Max
Unit
0
±0.5
±1
LSB2
♦ ♦
0
±0.5
±0.5
LSB2
♦ ♦
0
±1.0
±1.5
LSB2
♦
—
0
±0.5
±0.5
LSB2
♦
—
0
±1.0
±1.5
LSB2
♦ ♦
0
±0.5
±0.5
LSB2
♦ ♦
—
—
±0.5
LSB2
♦ ♦
—
—
±0.5
LSB2
♦ ♦
0
±0.2
±2.5
LSB2
♦ ♦
0
±0.1
±1
LSB2
♦ ♦
—
3.26
6
—
mV/°C
♦ ♦
—
3.63
8
—
mV/°C
♦ ♦
—
1.39
6
—
V
♦ ♦
Standard
#
AEC Grade 0
Temp
Rated
Comment
28-pin packages only
10-bit mode
T
Full-scale error
8-bit mode
EFS
20-pin packages
10-bit mode
T
8-bit mode
EFS
16-pin packages
10-bit mode
T
8-bit mode
Quantization
error
10-bit mode
D
8-bit mode
Input leakage
error
EQ
10-bit mode
D
8-bit mode
Temp sensor
slope
EFS
EIL
-40°C to 25°C
D
m
25°C to 125°C
Temp sensor
voltage
25°C
D
Pad leakage3
* RAS
VTEMP
25
1
Typical values assume VDD = 5.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 1 LSB = (V
N
REFH - VREFL)/2
3 Based on input pad leakage current. Refer to pad electricals.
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
315
Appendix A Electrical Characteristics
A.12
AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1
Control Timing
Table A-13. Control Timing
1
C
D
Rating
Bus frequency
(tcyc = 1/fBus)
-40 C to 125 C
Symbol
Min
Typ1
Max
Unit
AEC Grade 0
Num
Standard
Temp
Rated
fBus
dc
—
20
MHz
♦
—
dc
—
18
MHz
—
♦
700
1500
μs
♦
—
600
1500
μs
—
> 125 C
2
D
Internal low power
oscillator period
-40 C to 125 C
tLPO
3
D
External reset pulse width2
textrst
100
—
ns
4
D
Reset low drive3
trstdrv
66 x tcyc
—
ns
♦
♦ ♦
♦ ♦
5
D
tILIH, tIHIL
100
1.5 x tcyc
—
—
ns
♦ ♦
—
40
—
ns
♦ ♦
—
75
—
—
11
—
> 125 C
Pin interrupt pulse width
Asynchronous path2
Synchronous path4
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control
disabled (PTxSE = 0)
6
tRise, tFall
Slew rate control
enabled (PTxSE = 1)
♦ ♦
C
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)5
Slew rate control
disabled (PTxSE = 0)
tRise, tFall
Slew rate control
enabled (PTxSE = 1)
tRise, tFall
♦ ♦
ns
—
35
—
♦ ♦
1
Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3 When any reset is initiated, internal circuitry drives the reset pin low for about 66 cycles of t . After POR reset, the bus clock
cyc
frequency changes to the untrimmed DCO frequency (freset = (fdco_ut)/4) because TRIM is reset to 0x80 and FTRIM is reset
to 0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets trim stays at the pre-reset value.
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40°C to 125°C.
2
MC9S08SG32 Data Sheet, Rev. 8
316
Freescale Semiconductor
Appendix A Electrical Characteristics
textrst
RESET PIN
Figure A-10. Reset Timing
tIHIL
Pin Interrupts
Pin Interrupts
tILIH
Figure A-11. Pin Interrupt Timing
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
317
Appendix A Electrical Characteristics
A.12.2
TPM/MTIM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table A-14. TPM Input Timing
Symbol
Min
Max
Unit
Standard
AEC Grade 0
Temp
Rated
External clock frequency (1/tTCLK)
fTCLK
dc
fBus/4
MHz
♦
♦
—
External clock period
tTCLK
4
—
tcyc
♦
♦
3
—
External clock high time
tclkh
1.5
—
tcyc
♦
♦
4
—
External clock low time
tclkl
1.5
—
tcyc
♦
♦
5
—
Input capture pulse width
tICPW
1.5
—
tcyc
♦
♦
#
C
1
—
2
Rating
tTCLK
tclkh
TCLK
tclkl
Figure A-12. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure A-13. Timer Input Capture Pulse
MC9S08SG32 Data Sheet, Rev. 8
318
Freescale Semiconductor
Appendix A Electrical Characteristics
A.12.3
SPI
Table A-15 and Figure A-14 through Figure A-17 describe the timing requirements for the SPI system.
Table A-15. SPI Electrical Characteristic
C
1
D
2
3
4
5
6
7
D
D
D
D
D
D
Rating2
Symbol
Min
Max
Unit
Master
Slave
tSCK
tSCK
2
4
2048
—
tcyc
tcyc
Master
Slave
tLead
tLead
—
1/2
1/2
—
tSCK
tSCK
Master
Slave
tLag
tLag
—
1/2
1/2
—
tSCK
tSCK
Clock (SPSCK) high time
Master and Slave
tSCKH
1/2 tSCK – 25
—
ns
♦ ♦
Clock (SPSCK) low time
Master and Slave
tSCKL
1/2 tSCK – 25
—
ns
♦ ♦
Master
Slave
tSI(M)
tSI(S)
30
30
—
—
ns
ns
Master
Slave
tHI(M)
tHI(S)
30
30
—
—
ns
ns
Cycle time
Enable lead time
Enable lag time
Data setup time (inputs)
Data hold time (inputs)
♦ ♦
♦ ♦
♦ ♦
♦ ♦
D
Access time, slave3
tA
0
40
ns
♦ ♦
9
D
Disable time, slave4
tdis
—
40
ns
♦ ♦
10
D
Data setup time (outputs)
Master
Slave
tSO
tSO
—
—
25
25
ns
ns
Master
Slave
tHO
tHO
–10
–10
—
—
ns
ns
Master
Slave
fop
fop
fBus/2048
dc
55
fBus/4
MHz
D
D
Data hold time (outputs)
Operating frequency
12
2
♦ ♦
8
11
1
Standard
Num1
AEC Grade 0
Temp
Rated
♦ ♦
♦ ♦
♦ ♦
Refer to Figure A-14 through Figure A-17.
All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing
assumes slew rate control disabled and high drive strength enabled for SPI output pins.
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
319
Appendix A Electrical Characteristics
3
Time to data active from high-impedance state.
Hold time to high-impedance state.
5
Maximum baud rate must be limited to 5 MHz due to input filter characteristics.
4
SS1
(OUTPUT)
1
2
SCK
(CPOL = 0)
(OUTPUT)
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN2
BIT 6 . . . 1
10
MOSI
(OUTPUT)
3
5
LSB IN
10
MSB OUT2
BIT 6 . . . 1
11
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-14. SPI Master Timing (CPHA = 0)
MC9S08SG32 Data Sheet, Rev. 8
320
Freescale Semiconductor
Appendix A Electrical Characteristics
SS(1)
(OUTPUT)
1
2
3
SCK
(CPOL = 0)
(OUTPUT)
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN(2)
BIT 6 . . . 1
10
LSB IN
11
MOSI
(OUTPUT)
MSB OUT(2)
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-15. SPI Master Timing (CPHA = 1)
SS
(INPUT)
3
1
SCK
(CPOL = 0)
(INPUT)
5
4
2
SCK
(CPOL = 1)
(INPUT)
5
4
8
MISO
(OUTPUT)
MOSI
(INPUT)
11
10
SLAVE
6
9
MSB OUT
BIT 6 . . . 1
SLAVE LSB OUT
SEE
NOTE
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure A-16. SPI Slave Timing (CPHA = 0)
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
321
Appendix A Electrical Characteristics
SS
(INPUT)
1
3
2
SCK
(CPOL = 0)
(INPUT)
5
4
SCK
(CPOL = 1)
(INPUT)
5
4
10
MISO
(OUTPUT)
SEE
NOTE
8
MOSI
(INPUT)
SLAVE
11
MSB OUT
6
BIT 6 . . . 1
9
SLAVE LSB OUT
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure A-17. SPI Slave Timing (CPHA = 1)
MC9S08SG32 Data Sheet, Rev. 8
322
Freescale Semiconductor
Appendix A Electrical Characteristics
A.13
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the Flash
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see the Memory section.
Table A-16. Flash Characteristics
C
1
—
Characteristic
Symbol
Min
Typical
Max
Unit
Supply voltage for program/erase
Vprog/era
2.7
—
5.5
V
se
AEC Grade 0
#
Standard
Temp
Rated
♦
♦
♦
♦
♦
2
—
Supply voltage for read operation
VRead
2.7
—
5.5
V
3
—
Internal FCLK frequency1
fFCLK
150
—
200
kHz
4
—
Internal FCLK period (1/fFCLK)
tFcyc
5
—
6.67
μs
♦
♦
♦
5
—
Byte program time (random
location)2
tprog
9
tFcyc
♦
♦
6
—
Byte program time (burst mode)2
♦
♦
♦
♦
—
tBurst
4
tFcyc
time2
tPage
4000
tFcyc
tMass
20,000
tFcyc
7
—
Page erase
8
—
Mass erase time2
Program/erase endurance3
9
10
C
C
nFLPE
cycles
TL to TH = –40°C to +125°C
10,000
—
—
♦
TL to TH = –40°C to +150°C
10,000
—
—
—
T = 25°C
10,000
100,000
—
15
100
—
Data retention4
tD_ret
years
♦
♦
♦
♦
♦
1
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for
calculating approximate time to program and erase.
3 Typical endurance for Flash is based upon the intrinsic bit cell performance. For additional information on how Freescale
defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory.
4
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer
to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
2
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
323
Appendix A Electrical Characteristics
A.14
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the
MCU resides. Board design and layout, circuit topology choices, location and characteristics of external
components as well as MCU software operation all play a significant role in EMC performance. The
system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263,
AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
A.14.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell
method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed
with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test
software. The radiated emissions from the microcontroller are measured in a TEM cell in two package
orientations (North and East).
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal
to the reported emissions levels.
Table A-17. Radiated Emissions, Electric Field
Radiated emissions,
electric field
Symbol
VRE_TEM
Conditions
VDD = 5 V
TA = +25oC
package type
28 TSSOP
Frequency
fOSC/fBUS
Level1
(Max)
0.15 – 50 MHz
12
50 – 150 MHz
12
Unit
♦ ♦
dBμV
150 – 500 MHz
500 – 1000 MHz
4 MHz crystal
20 MHz bus
AEC Grade 0
Parameter
Standard
Temp
Rated
♦ ♦
6
♦ ♦
–8
♦ ♦
IEC Level2
N
—
♦ ♦
SAE Level3
2
—
♦ ♦
1
Data based on qualification test results.
IEC Level Maximums: N ≤ 12dBμV, L ≤ 24dBμV, I ≤ 36dBμV
3 SAE Level Maximums: 1 ≤ 10dBμV, 2 ≤ 20dBμV, 3 ≤ 30dBμV, 4 ≤ 40dBμV
2
MC9S08SG32 Data Sheet, Rev. 8
324
Freescale Semiconductor
Appendix B
Ordering Information and Mechanical Drawings
B.1
Ordering Information
This section contains ordering information for MC9S08SG32 and MC9S08SG16 devices.
Table B-1. Device Numbering System
Flash
MC9S08SG32
MC9S08SG16
RAM
1K
♦
♦
32K
16K
Available Packages2
Temp Rated
AEC Grade 0
Memory
Standard
Part Number1
28-Pin
20-Pin
16-Pin
♦
♦
28 TSSOP
20 TSSOP3
16 TSSOP
1
See Table 1-1 for a complete description of modules included on each device.
See Table B-2 for package information.
3 20-pin TSSOP package is not available on the AEC Grade 0 high-temperature rated devices.
2
Jennifer
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
325
Appendix B Ordering Information and Mechanical Drawings
B.1.1
Device Numbering Scheme
This device uses a smart numbering system. Refer to the following diagram to understand what each
element of the device number represents.
S
9
S08
SG n
E1
C
xx
R
Tape and Reel Suffix (optional)
- R = Tape and Reel
Status
- S = Auto Qualified
- MC = Fully Qualified
Package Designator
Two letter descriptor (refer to
Table B-2).
Main Memory Type
- 9 = Flash-based
Temperature Option
- C = –40 to 85 °C
- V = –40 to 105 °C
- M = –40 to 125 °C
- J = –40 to 140 °C
- W = –40 to 150 °C
Core
Family
- SG
Memory Size
- 32 Kbytes
- 16 Kbytes
Mask Set Identifier — this
field only appears in “Auto
Qualified” part numbers
- Alpha character references
wafer fab.
- Numeric character identifies
mask.
Figure B-1. MC9S08SG32 Device Numbering Scheme
B.2
Package Information and Mechanical Drawings
Table B-2 provides the available package types and their document numbers. The latest package
outline/mechanical drawings are available on the MC9S08SG32 Series Product Summary pages at
http://www.freescale.com.
To view the latest drawing, either:
• Click on the appropriate link in Table B-2, or
• Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate
document number (from Table B-2) in the “Enter Keyword” search box at the top of the page.
MC9S08SG32 Data Sheet, Rev. 8
326
Freescale Semiconductor
Appendix B Ordering Information and Mechanical Drawings
The following pages are mechanical specifications for MC9S08SG32 Series package options. See
Table B-2 for the document number for each package type.
is
Table B-2. Package Information
Pin Count
Type
Designator
Document No.
28
TSSOP
TL
98ARS23923W
20
TSSOP
TJ
98ASH70169A
16
TSSOP
TG
98ASH70247A
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
327
Appendix B Ordering Information and Mechanical Drawings
MC9S08SG32 Data Sheet, Rev. 8
328
Freescale Semiconductor
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