MC9S08SG8
MC9S08SG4
Data Sheet
Now Includes High-Temperature (up to 150 °C) Devices!
HCS08
Microcontrollers
MC9S08SG8
Rev. 8
1/2014
freescale.com
MC9S08SG8 Features
8-Bit HCS08 Central Processor Unit (CPU)
• 40 MHz HCS08 CPU (central processor unit)
• 36 MHz HCS08 CPU for temperatures greater
than 125 C
• HC08 instruction set with added BGND instruction
• Support for up to 32 interrupt/reset sources
On-Chip Memory
• Flash read/program/erase over full operating
voltage and temperature
• Random-access memory (RAM)
Power-Saving Modes
• Two very low power stop modes
• Reduced power wait mode
• Very low power real time interrupt for use in run,
wait, and stop
Clock Source Options
• Oscillator (XOSC) — Loop-control Pierce
oscillator; Crystal or ceramic resonator range of
31.25 kHz to 38.4 kHz or 1 MHz to 16MHz
• Internal Clock Source (ICS) — Internal clock
source module containing a frequency-locked
loop (FLL) controlled by internal or external
reference; precision trimming of internal reference
allows 0.2% resolution and 1.5% deviation over
temperature –40 to 125 C or 3% deviation for
temperature > 125 C and voltage; supports bus
frequencies from 2 MHz to 20MHz.
System Protection
• Watchdog computer operating properly (COP)
reset with option to run from dedicated 1-kHz
internal clock source or bus clock
• Low-voltage detection with reset or interrupt;
selectable trip points
• Illegal opcode detection with reset
• Illegal address detection with reset
• FLASH block protect
Development Support
• Single-wire background debug interface
• Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
• On-chip, in-circuit emulation (ICE) debug module
containing two comparators and nine trigger
modes. Eight deep FIFO for storing
change-of-flow address and event-only data.
Debug module supports both tag and force
breakpoints.
Peripherals
• ADC — 12-channel, 10-bit resolution, 2.5 s
conversion time, automatic compare function,
temperature sensor, internal bandgap reference
channel; runs in stop3
• ACMP — Analog comparator with selectable
interrupt on rising, falling, or either edge of
comparator output; compare option to fixed
internal bandgap reference voltage; output can be
optionally routed to TPM module; runs in stop3
• SCI — Full duplex non-return to zero (NRZ); LIN
master extended break generation; LIN slave
extended break detection; wake up on active edge
• SPI — Full-duplex or single-wire bidirectional;
Double-buffered transmit and receive; Master or
Slave mode; MSB-first or LSB-first shifting
• IIC — Up to 100 kbps with maximum bus loading;
Multi-master operation; Programmable slave
address; Interrupt driven byte-by-byte data
transfer; supports broadcast mode and 10-bit
addressing
• MTIM — 8-bit modulo counter with 8-bit prescaler
and overflow interrupt
• TPMx — Two 2-channel timer pwm modules
(TPM1, TPM2); Selectable input capture, output
compare, or buffered edge- or center-aligned
PWM on each channel
• RTC — (Real-time counter) 8-bit modulus counter
with binary or decimal based prescaler; External
clock source for precise time base, time-of-day,
calendar or task scheduling functions; Free
running on-chip low power oscillator (1 kHz) for
cyclic wake-up without external components, runs
in all MCU modes
Input/Output
• 16 general purpose I/O pins (GPIOs)
• 8 interrupt pins with selectable polarity
• Ganged output option for PTB[5:2] and PTC[3:0];
allows single write to change state of multiple pins
• Hysteresis and configurable pull up device on all
input pins; Configurable slew rate and drive
strength on all output pins.
Package Options
• 20-TSSOP (not available on high-temperature
rated devices)
• 16-TSSOP
• 8-SOIC (not available on high-temperature rated
devices)
MC9S08SG8 Data Sheet
Covers MC9S08SG8
MC9S08SG4
MC9S08SG8
Rev. 8
1/2014
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2006-2014. All rights reserved.
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
Number
Revision
Date
0
15 Dec 2006
Description of Changes
Initial alpha customer release version; Preliminary
1
June 2007
Samples Draft. Updated book with the latest TPM v3 module. Includes some
minor edits to the IIC module to update the Module Quick Start. Fixed the
SOPT1 bits 1 and 0 to be RESERVED for both READ and WRITE. Changed all
the Reset states of the Slew Rate Enable Registers (PTASE, PTBSE, and
PTCSE) bits from 1 to 0 due to silicon functional change.
2
11/2007
Market Launch. Updated the Electricals and Device Numbering scheme information.
12/2007
• Fixed typos: Chapter 7 heading corrected version to v2, and Figure 16-1. title
corrected to read ...”TPM Modules Highlighted.”
• Table A-3. Thermal Characteristics row 1, V and M entries were transposed. V
now refers to value -40 to 105C and M now refers to value -40 to 125C. Added
row 2, parameter classification of “D” and row 4 symbol of ”JA.”
• Table A-6. DC Characteristics, row 8 Input Hysteresis, corrected units from mV
to V.
4
3/2008
• SPI block corrected to be version 3 of the module.
• Temperature Sensor values corrected to reflect the ADC 5V in Section 9.1.4
Temperature Sensor and Table A-12. ADC Characteristics.
• Provided Maximum juncture temperature for C, V, and M Temperature ranges.
• Corrected Table A-6, row 10 separated to two pins: PTB6/SDA/XTAL, RESET.
• Corrected block diagrams User Flash and User RAM listing typos to be SG8
and SG4 instead of SH8 and SH4.
• Updated the Revision History for Revision Number 1 to include the information
on the Slew Rate Enable Register changes that occurred for that revision.
5
6/2008
• Added ICS over Temperature graph to Electricals appendix.
3
© Freescale Semiconductor, Inc., 2006-2014. All rights reserved.
This product incorporates SuperFlash Technology licensed from SST.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
6
Freescale Semiconductor
Revision
Number
6
7
8
Revision
Date
Description of Changes
7/2009
• Revised NV Register 0xFFAE address to have dashes instead of 0s.
• Revised NVOPT register in Table 4-4 and Figure 4-6 so that Reserved is indicated with em dashes (—).
• Changed ICS FLL deviation to 1.5% from 2%.
• Table A-9, Row 1and Table A-6 footnote 10: Removed temperature reference. •
Table A-9, Row 9: Changed Column C to “D” and Max to “1.5%”
• Removed section A.14.2.
• Updated Mechanical drawings to point to the Freescale web.
• Rebuilt book to ensure proper footers and pagination.
• Revised all "Reserved" vector space memory locations in Table 4-1 to read,
"Unused Vector Space (available for user program)."
7/2011
• Revised to include high-temperature (up to 150C) devices for 16-pin TSSOP
package.
• In Table 2-1, added TCLK to row 20 and Alt 3 column.
• Updated “How to Reach Us” information.
1/2014
Changes done in Chapter 3, “Modes of Operation”.
Updated Table 3-1
Updated PPDC column to “x” from “0” for the specification
STOPE=1,ENBDM=0,LVDE and LVDSE =both bits must be 1.
Changes done in Appendix A, “Electrical Characteristics”
• In Table A-6. DC Characteristics for column “Characteristic” moved “Reset”
from parameter “P” to “C”.
• In the Table A-6 added note 11 and 12 for parameter #18.
Note 11: Device functionality is guaranteed between the LVD threshold VLVD0
and VDD Min.When VDD is below the minimum operating voltage (VDD Min),
the analog parameters for the IO pins, ACMP and ADC, are not guaranteed to
meet data sheet performance parameters.
Note 12: In addition to LVD, it is recommended to also use the LVW feature. LVW
can trigger an interrupt and be used as an indicator to warn that the VDD is dropping,so that the software can take actions accordingly before the VDD drops
below VDD Min.
• Table A-13. Control Timing.
For the parameter “Internal low power oscillator period” changed the “Min”
value from “800” to “700”.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
7
Contents
Section Number
Title
Page
Chapter 1
Device Overview ...................................................................... 21
Chapter 2
Pins and Connections ............................................................. 25
Chapter 3
Modes of Operation ................................................................. 33
Chapter 4
Memory ..................................................................................... 39
Chapter 5
Resets, Interrupts, and General System Control.................. 61
Chapter 6
Parallel Input/Output Control.................................................. 75
Chapter 7
Central Processor Unit (S08CPUV2) ...................................... 91
Chapter 8
5-V Analog Comparator (S08ACMPV2)................................ 111
Chapter 9
Analog-to-Digital Converter (S08ADCV1)............................ 119
Chapter 10
Internal Clock Source (S08ICSV2)........................................ 147
Chapter 11
Inter-Integrated Circuit (S08IICV2) ....................................... 161
Chapter 12
Modulo Timer (S08MTIMV1).................................................. 179
Chapter 13
Real-Time Counter (S08RTCV1) ........................................... 189
Chapter 14
Serial Communications Interface (S08SCIV4)..................... 199
Chapter 15
Serial Peripheral Interface (S08SPIV3) ................................ 219
Chapter 16
Timer Pulse-Width Modulator (S08TPMV3) ......................... 235
Chapter 17
Development Support ........................................................... 261
Appendix A
Electrical Characteristics...................................................... 283
Appendix B
Ordering Information and Mechanical Drawings................ 313
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
9
MC9S08SG8 MCU Series Data Sheet, Rev. 8
10
Freescale Semiconductor
Contents
Section Number
Title
Page
Chapter 1
Device Overview
1.1
1.2
1.3
Devices in the MC9S08SG8 Series .................................................................................................21
MCU Block Diagram ......................................................................................................................22
System Clock Distribution ..............................................................................................................24
Chapter 2
Pins and Connections
2.1
2.2
Device Pin Assignment ...................................................................................................................25
Recommended System Connections ...............................................................................................27
2.2.1 Power ................................................................................................................................27
2.2.2 Oscillator (XOSC) ............................................................................................................28
2.2.3 RESET Pin ........................................................................................................................28
2.2.4 Background / Mode Select (BKGD/MS) ..........................................................................29
2.2.5 General-Purpose I/O and Peripheral Ports ........................................................................29
Chapter 3
Modes of Operation
3.1
3.2
3.3
3.4
3.5
3.6
Introduction .....................................................................................................................................33
Features ...........................................................................................................................................33
Run Mode ........................................................................................................................................33
Active Background Mode ...............................................................................................................33
Wait Mode .......................................................................................................................................34
Stop Modes ......................................................................................................................................34
3.6.1 Stop3 Mode .......................................................................................................................35
3.6.2 Stop2 Mode .......................................................................................................................36
3.6.3 On-Chip Peripheral Modules in Stop Modes ....................................................................36
Chapter 4
Memory
4.1
4.2
4.3
4.4
4.5
MC9S08SG8 Memory Map ............................................................................................................39
Reset and Interrupt Vector Assignments .........................................................................................40
Register Addresses and Bit Assignments ........................................................................................41
RAM ................................................................................................................................................48
FLASH ............................................................................................................................................48
4.5.1 Features .............................................................................................................................49
4.5.2 Program and Erase Times .................................................................................................49
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Section Number
4.6
4.7
Title
Page
4.5.3 Program and Erase Command Execution .........................................................................50
4.5.4 Burst Program Execution ..................................................................................................51
4.5.5 Access Errors ....................................................................................................................53
4.5.6 FLASH Block Protection ..................................................................................................53
4.5.7 Vector Redirection ............................................................................................................54
Security ............................................................................................................................................54
FLASH Registers and Control Bits .................................................................................................55
4.7.1 FLASH Clock Divider Register (FCDIV) ........................................................................56
4.7.2 FLASH Options Register (FOPT and NVOPT) ................................................................57
4.7.3 FLASH Configuration Register (FCNFG) .......................................................................58
4.7.4 FLASH Protection Register (FPROT and NVPROT) ......................................................58
4.7.5 FLASH Status Register (FSTAT) ......................................................................................59
4.7.6 FLASH Command Register (FCMD) ...............................................................................60
Chapter 5
Resets, Interrupts, and General System Control
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Introduction .....................................................................................................................................61
Features ...........................................................................................................................................61
MCU Reset ......................................................................................................................................61
Computer Operating Properly (COP) Watchdog .............................................................................62
Interrupts .........................................................................................................................................63
5.5.1 Interrupt Stack Frame .......................................................................................................64
5.5.2 Interrupt Vectors, Sources, and Local Masks ...................................................................65
Low-Voltage Detect (LVD) System ................................................................................................67
5.6.1 Power-On Reset Operation ...............................................................................................67
5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................67
5.6.3 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................67
Reset, Interrupt, and System Control Registers and Control Bits ...................................................67
5.7.1 System Reset Status Register (SRS) .................................................................................68
5.7.2 System Background Debug Force Reset Register (SBDFR) ............................................69
5.7.3 System Options Register 1 (SOPT1) ................................................................................70
5.7.4 System Options Register 2 (SOPT2) ................................................................................71
5.7.5 System Device Identification Register (SDIDH, SDIDL) ................................................72
5.7.6 System Power Management Status and Control 1 Register (SPMSC1) ...........................73
5.7.7 System Power Management Status and Control 2 Register (SPMSC2) ...........................74
Chapter 6
Parallel Input/Output Control
6.1
6.2
6.3
6.4
Port Data and Data Direction ..........................................................................................................75
Pull-up, Slew Rate, and Drive Strength ..........................................................................................76
Ganged Output ................................................................................................................................77
Pin Interrupts ...................................................................................................................................78
MC9S08SG8 MCU Series Data Sheet, Rev. 8
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Section Number
6.5
6.6
Title
Page
6.4.1 Edge Only Sensitivity .......................................................................................................78
6.4.2 Edge and Level Sensitivity ...............................................................................................78
6.4.3 Pull-up/Pull-down Resistors .............................................................................................79
6.4.4 Pin Interrupt Initialization .................................................................................................79
Pin Behavior in Stop Modes ............................................................................................................79
Parallel I/O and Pin Control Registers ............................................................................................79
6.6.1 Port A Registers ................................................................................................................80
6.6.2 Port B Registers ................................................................................................................84
6.6.3 Port C Registers ................................................................................................................88
Chapter 7
Central Processor Unit (S08CPUV2)
7.1
7.2
7.3
7.4
7.5
Introduction .....................................................................................................................................91
7.1.1 Features .............................................................................................................................91
Programmer’s Model and CPU Registers .......................................................................................92
7.2.1 Accumulator (A) ...............................................................................................................92
7.2.2 Index Register (H:X) ........................................................................................................92
7.2.3 Stack Pointer (SP) .............................................................................................................93
7.2.4 Program Counter (PC) ......................................................................................................93
7.2.5 Condition Code Register (CCR) .......................................................................................93
Addressing Modes ...........................................................................................................................94
7.3.1 Inherent Addressing Mode (INH) .....................................................................................95
7.3.2 Relative Addressing Mode (REL) ....................................................................................95
7.3.3 Immediate Addressing Mode (IMM) ................................................................................95
7.3.4 Direct Addressing Mode (DIR) ........................................................................................95
7.3.5 Extended Addressing Mode (EXT) ..................................................................................95
7.3.6 Indexed Addressing Mode ................................................................................................95
Special Operations ...........................................................................................................................96
7.4.1 Reset Sequence .................................................................................................................97
7.4.2 Interrupt Sequence ............................................................................................................97
7.4.3 Wait Mode Operation ........................................................................................................98
7.4.4 Stop Mode Operation ........................................................................................................98
7.4.5 BGND Instruction .............................................................................................................98
HCS08 Instruction Set Summary ....................................................................................................99
Chapter 8
5-V Analog Comparator (S08ACMPV2)
8.1
Introduction ...................................................................................................................................111
8.1.1 ACMP Configuration Information ..................................................................................111
8.1.2 ACMP in Stop3 Mode ....................................................................................................111
8.1.3 ACMP/TPM Configuration Information ........................................................................111
8.1.4 Features ...........................................................................................................................113
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
13
Section Number
8.2
8.3
8.4
Title
Page
8.1.5 Modes of Operation ........................................................................................................113
8.1.6 Block Diagram ................................................................................................................113
External Signal Description ..........................................................................................................115
Memory Map ................................................................................................................................115
8.3.1 Register Descriptions ......................................................................................................115
Functional Description ..................................................................................................................117
Chapter 9
Analog-to-Digital Converter (S08ADCV1)
9.1
9.2
9.3
9.4
Introduction ...................................................................................................................................119
9.1.1 Channel Assignments .....................................................................................................119
9.1.2 Alternate Clock ...............................................................................................................120
9.1.3 Hardware Trigger ............................................................................................................120
9.1.4 Temperature Sensor ........................................................................................................120
9.1.5 Features ...........................................................................................................................123
9.1.6 Block Diagram ................................................................................................................123
External Signal Description ..........................................................................................................124
9.2.1 Analog Power (VDDAD) ..................................................................................................125
9.2.2 Analog Ground (VSSAD) .................................................................................................125
9.2.3 Voltage Reference High (VREFH) ...................................................................................125
9.2.4 Voltage Reference Low (VREFL) ....................................................................................125
9.2.5 Analog Channel Inputs (ADx) ........................................................................................125
Register Definition ........................................................................................................................125
9.3.1 Status and Control Register 1 (ADCSC1) ......................................................................125
9.3.2 Status and Control Register 2 (ADCSC2) ......................................................................127
9.3.3 Data Result High Register (ADCRH) .............................................................................128
9.3.4 Data Result Low Register (ADCRL) ..............................................................................128
9.3.5 Compare Value High Register (ADCCVH) ....................................................................129
9.3.6 Compare Value Low Register (ADCCVL) .....................................................................129
9.3.7 Configuration Register (ADCCFG) ................................................................................129
9.3.8 Pin Control 1 Register (APCTL1) ..................................................................................131
9.3.9 Pin Control 2 Register (APCTL2) ..................................................................................132
9.3.10 Pin Control 3 Register (APCTL3) ..................................................................................133
Functional Description ..................................................................................................................134
9.4.1 Clock Select and Divide Control ....................................................................................134
9.4.2 Input Select and Pin Control ...........................................................................................135
9.4.3 Hardware Trigger ............................................................................................................135
9.4.4 Conversion Control .........................................................................................................135
9.4.5 Automatic Compare Function .........................................................................................138
9.4.6 MCU Wait Mode Operation ............................................................................................138
9.4.7 MCU Stop3 Mode Operation ..........................................................................................138
9.4.8 MCU Stop1 and Stop2 Mode Operation .........................................................................139
MC9S08SG8 MCU Series Data Sheet, Rev. 8
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Freescale Semiconductor
Section Number
9.5
9.6
Title
Page
Initialization Information ..............................................................................................................139
9.5.1 ADC Module Initialization Example .............................................................................139
Application Information ................................................................................................................141
9.6.1 External Pins and Routing ..............................................................................................141
9.6.2 Sources of Error ..............................................................................................................143
Chapter 10
Internal Clock Source (S08ICSV2)
10.1 Introduction ...................................................................................................................................147
10.1.1 Module Configuration .....................................................................................................147
10.1.2 Features ...........................................................................................................................149
10.1.3 Block Diagram ................................................................................................................149
10.1.4 Modes of Operation ........................................................................................................150
10.2 External Signal Description ..........................................................................................................151
10.3 Register Definition ........................................................................................................................151
10.3.1 ICS Control Register 1 (ICSC1) .....................................................................................152
10.3.2 ICS Control Register 2 (ICSC2) .....................................................................................153
10.3.3 ICS Trim Register (ICSTRM) .........................................................................................154
10.3.4 ICS Status and Control (ICSSC) .....................................................................................154
10.4 Functional Description ..................................................................................................................155
10.4.1 Operational Modes ..........................................................................................................155
10.4.2 Mode Switching ..............................................................................................................157
10.4.3 Bus Frequency Divider ...................................................................................................158
10.4.4 Low Power Bit Usage .....................................................................................................158
10.4.5 Internal Reference Clock ................................................................................................158
10.4.6 Optional External Reference Clock ................................................................................158
10.4.7 Fixed Frequency Clock ...................................................................................................159
Chapter 11
Inter-Integrated Circuit (S08IICV2)
11.1 Introduction ...................................................................................................................................161
11.1.1 Module Configuration .....................................................................................................161
11.1.2 Features ...........................................................................................................................163
11.1.3 Modes of Operation ........................................................................................................163
11.1.4 Block Diagram ................................................................................................................163
11.2 External Signal Description ..........................................................................................................164
11.2.1 SCL — Serial Clock Line ...............................................................................................164
11.2.2 SDA — Serial Data Line ................................................................................................164
11.3 Register Definition ........................................................................................................................164
11.3.1 IIC Address Register (IICA) ...........................................................................................165
11.3.2 IIC Frequency Divider Register (IICF) ..........................................................................165
11.3.3 IIC Control Register (IICC1) ..........................................................................................168
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
15
Section Number
11.4
11.5
11.6
11.7
Title
Page
11.3.4 IIC Status Register (IICS) ...............................................................................................168
11.3.5 IIC Data I/O Register (IICD) ..........................................................................................169
11.3.6 IIC Control Register 2 (IICC2) .......................................................................................170
Functional Description ..................................................................................................................171
11.4.1 IIC Protocol .....................................................................................................................171
11.4.2 10-bit Address .................................................................................................................174
11.4.3 General Call Address ......................................................................................................175
Resets ............................................................................................................................................175
Interrupts .......................................................................................................................................175
11.6.1 Byte Transfer Interrupt ....................................................................................................175
11.6.2 Address Detect Interrupt .................................................................................................176
11.6.3 Arbitration Lost Interrupt ................................................................................................176
Initialization/Application Information ..........................................................................................177
Chapter 12
Modulo Timer (S08MTIMV1)
12.1 Introduction ...................................................................................................................................179
12.1.1 MTIM Configuration Information ..................................................................................179
12.1.2 Features ...........................................................................................................................181
12.1.3 Modes of Operation ........................................................................................................181
12.1.4 Block Diagram ................................................................................................................182
12.2 External Signal Description ..........................................................................................................182
12.3 Register Definition ........................................................................................................................183
12.3.1 MTIM Status and Control Register (MTIMSC) .............................................................184
12.3.2 MTIM Clock Configuration Register (MTIMCLK) .......................................................185
12.3.3 MTIM Counter Register (MTIMCNT) ...........................................................................186
12.3.4 MTIM Modulo Register (MTIMMOD) ..........................................................................186
12.4 Functional Description ..................................................................................................................187
12.4.1 MTIM Operation Example .............................................................................................188
Chapter 13
Real-Time Counter (S08RTCV1)
13.1 Introduction ...................................................................................................................................189
13.1.1 Features ...........................................................................................................................191
13.1.2 Modes of Operation ........................................................................................................191
13.1.3 Block Diagram ................................................................................................................192
13.2 External Signal Description ..........................................................................................................192
13.3 Register Definition ........................................................................................................................192
13.3.1 RTC Status and Control Register (RTCSC) ....................................................................193
13.3.2 RTC Counter Register (RTCCNT) ..................................................................................194
13.3.3 RTC Modulo Register (RTCMOD) ................................................................................194
13.4 Functional Description ..................................................................................................................194
MC9S08SG8 MCU Series Data Sheet, Rev. 8
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Section Number
Title
Page
13.4.1 RTC Operation Example .................................................................................................195
13.5 Initialization/Application Information ..........................................................................................196
Chapter 14
Serial Communications Interface (S08SCIV4)
14.1 Introduction ...................................................................................................................................199
14.1.1 Features ...........................................................................................................................201
14.1.2 Modes of Operation ........................................................................................................201
14.1.3 Block Diagram ................................................................................................................202
14.2 Register Definition ........................................................................................................................204
14.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) ..............................................................204
14.2.2 SCI Control Register 1 (SCIC1) .....................................................................................205
14.2.3 SCI Control Register 2 (SCIC2) .....................................................................................206
14.2.4 SCI Status Register 1 (SCIS1) ........................................................................................207
14.2.5 SCI Status Register 2 (SCIS2) ........................................................................................209
14.2.6 SCI Control Register 3 (SCIC3) .....................................................................................210
14.2.7 SCI Data Register (SCID) ...............................................................................................211
14.3 Functional Description ..................................................................................................................211
14.3.1 Baud Rate Generation .....................................................................................................211
14.3.2 Transmitter Functional Description ................................................................................212
14.3.3 Receiver Functional Description ....................................................................................213
14.3.4 Interrupts and Status Flags ..............................................................................................215
14.3.5 Additional SCI Functions ...............................................................................................216
Chapter 15
Serial Peripheral Interface (S08SPIV3)
15.1 Introduction ...................................................................................................................................219
15.1.1 Features ...........................................................................................................................221
15.1.2 Block Diagrams ..............................................................................................................221
15.1.3 SPI Baud Rate Generation ..............................................................................................223
15.2 External Signal Description ..........................................................................................................224
15.2.1 SPSCK — SPI Serial Clock ............................................................................................224
15.2.2 MOSI — Master Data Out, Slave Data In ......................................................................224
15.2.3 MISO — Master Data In, Slave Data Out ......................................................................224
15.2.4 SS — Slave Select ..........................................................................................................224
15.3 Modes of Operation .......................................................................................................................225
15.3.1 SPI in Stop Modes ..........................................................................................................225
15.4 Register Definition ........................................................................................................................225
15.4.1 SPI Control Register 1 (SPIC1) ......................................................................................225
15.4.2 SPI Control Register 2 (SPIC2) ......................................................................................226
15.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................227
15.4.4 SPI Status Register (SPIS) ..............................................................................................228
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Section Number
Title
Page
15.4.5 SPI Data Register (SPID) ...............................................................................................229
15.5 Functional Description ..................................................................................................................230
15.5.1 SPI Clock Formats ..........................................................................................................230
15.5.2 SPI Interrupts ..................................................................................................................233
15.5.3 Mode Fault Detection .....................................................................................................233
Chapter 16
Timer Pulse-Width Modulator (S08TPMV3)
16.1 Introduction ...................................................................................................................................235
16.1.1 ACMP/TPM Configuration Information ........................................................................235
16.1.2 TPM Configuration Information .....................................................................................235
16.1.3 TPMV3 Differences from Previous Versions .................................................................236
16.1.4 Migrating from TPMV1 ..................................................................................................238
16.1.5 Features ...........................................................................................................................240
16.1.6 Modes of Operation ........................................................................................................240
16.1.7 Block Diagram ................................................................................................................241
16.2 Signal Description .........................................................................................................................243
16.2.1 Detailed Signal Descriptions ..........................................................................................243
16.3 Register Definition ........................................................................................................................247
16.3.1 TPM Status and Control Register (TPMxSC) ................................................................247
16.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................248
16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................249
16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................250
16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................251
16.4 Functional Description ..................................................................................................................253
16.4.1 Counter ............................................................................................................................253
16.4.2 Channel Mode Selection .................................................................................................255
16.5 Reset Overview .............................................................................................................................258
16.5.1 General ............................................................................................................................258
16.5.2 Description of Reset Operation .......................................................................................258
16.6 Interrupts .......................................................................................................................................258
16.6.1 General ............................................................................................................................258
16.6.2 Description of Interrupt Operation .................................................................................259
Chapter 17
Development Support
17.1 Introduction ...................................................................................................................................261
17.1.1 Forcing Active Background ............................................................................................261
17.1.2 Features ...........................................................................................................................262
17.2 Background Debug Controller (BDC) ..........................................................................................262
17.2.1 BKGD Pin Description ...................................................................................................263
17.2.2 Communication Details ..................................................................................................264
MC9S08SG8 MCU Series Data Sheet, Rev. 8
18
Freescale Semiconductor
Section Number
Title
Page
17.2.3 BDC Commands .............................................................................................................268
17.2.4 BDC Hardware Breakpoint .............................................................................................270
17.3 On-Chip Debug System (DBG) ....................................................................................................271
17.3.1 Comparators A and B .....................................................................................................271
17.3.2 Bus Capture Information and FIFO Operation ...............................................................271
17.3.3 Change-of-Flow Information ..........................................................................................272
17.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................272
17.3.5 Trigger Modes .................................................................................................................273
17.3.6 Hardware Breakpoints ....................................................................................................275
17.4 Register Definition ........................................................................................................................275
17.4.1 BDC Registers and Control Bits .....................................................................................275
17.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................277
17.4.3 DBG Registers and Control Bits .....................................................................................278
Appendix A
Electrical Characteristics
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9
A.10
A.11
A.12
Introduction ...................................................................................................................................283
Parameter Classification ................................................................................................................283
Absolute Maximum Ratings ..........................................................................................................283
Thermal Characteristics .................................................................................................................285
ESD Protection and Latch-Up Immunity ......................................................................................287
DC Characteristics .........................................................................................................................288
Supply Current Characteristics ......................................................................................................293
External Oscillator (XOSC) Characteristics .................................................................................297
Internal Clock Source (ICS) Characteristics .................................................................................299
Analog Comparator (ACMP) Electricals ......................................................................................301
ADC Characteristics ......................................................................................................................302
AC Characteristics .........................................................................................................................305
A.12.1 Control Timing ...............................................................................................................305
A.12.2 TPM/MTIM Module Timing ..........................................................................................307
A.12.3 SPI ...................................................................................................................................308
A.13 FLASH Specifications ...................................................................................................................311
A.14 EMC Performance .........................................................................................................................312
A.14.1 Radiated Emissions .........................................................................................................312
Appendix B
Ordering Information and Mechanical Drawings
B.1 Ordering Information ....................................................................................................................313
B.1.1 Device Numbering Scheme ............................................................................................313
B.2 Mechanical Drawings ....................................................................................................................314
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
19
Chapter 1
Device Overview
The MC9S08SG8 members of the low-cost, high-performance HCS08 family of 8-bit microcontroller
units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of
modules, memory sizes, memory types, and package types. The high-temperature devices have been
qualified to meet or exceed AEC Grade 0 requirements to allow them to operate up to 150 °C TA.
1.1
Devices in the MC9S08SG8 Series
Table 1-1 summarizes the feature set available in the MC9S08SG8 series of MCUs.
t
Table 1-1. MC9S08SG8 Features by MCU and Package
Feature
9S08SG8
9S08SG4
FLASH size (bytes)
8192
4096
RAM size (bytes)
512
256
Pin quantity
20
16
8
12
8
4
ACMP
ADC channels
8
12
8
4
yes
yes
yes 1
yes
yes
yes
yes
1
IIC
yes
MTIM
yes
Pin Interrupts
8
8
4
8
8
4
Pin I/O
16
12
4
16
12
4
SCI
yes
yes
no
yes
yes
no
SPI
yes
yes
no
yes
yes
no
2
2
1
2
2
1
RTC
TPM1 channels
TPM2 channels
XOSC
1
16
yes
DBG
ICS
20
yes
2
2
1
2
2
1
yes
yes
no
yes
yes
no
FBE and FEE modes are not available in 8-pin packages.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
21
Chapter 1 Device Overview
1.2
MCU Block Diagram
The block diagram in Figure 1-1 shows the structure of the MC9S08SG8 MCU.
HCS08 CORE
DEBUG MODULE (DBG)
BKGD/MS
8-BIT MODULO TIMER
MODULE (MTIM)
HCS08 SYSTEM CONTROL
SCL
IIC MODULE (IIC)
LVD
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER FLASH
(MC9S08SG8 = 8,192 BYTES)
(MC9S08SG4 = 4096 BYTES)
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI)
USER RAM
(MC9S08SG8 = 512 BYTES)
(MC9S08SG4 = 256 BYTES)
16-BIT TIMER/PWM
MODULE (TPM1)
REAL-TIME COUNTER (RTC)
16-BIT TIMER/PWM
MODULE (TPM2)
40-MHz INTERNAL CLOCK
SOURCE (ICS)
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
VOLTAGE
REGULATOR
VSS
VDDA
VSSA
VREFH
VREFL
SS
MISO
MOSI
SPSCK
PTA3/PAI3/SCL/ADP3
PTA1/PIA1/TPM2CH0/ADP1/ACMP–
PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+
SEE NOTE 1, 2
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
TCLK
TPM1CH0
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
PTB3/PIB3/MOSI/ADP7
PTB2/PIB2/SPSCK/ADP6
TPM1CH1
PTB1/PIB1/TxD/ADP5
PTB0/PIB0/RxD/ADP4
TCLK
TPM2CH0
TPM2CH1
XTAL
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
PTA2/PAI2/SDA/ADP2/ACMPO
RxD
TxD
SEE NOTE 1, 2
EXTAL
ANALOG COMPARATOR
(ACMP)
SEE NOTE 3
VDD
SDA
PORT A
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
COP
TCLK
PORT B
BDC
ACMPO
ACMP–
ACMP+
PORT C
CPU
RESET
PTC3/ADP11
PTC2/ADP10
PTC1/TPM1CH1/ADP9
PTC0/TPM1CH0/ADP8
ADP11-ADP0
NOTES
= Pin can be enabled as part of the ganged output drive feature.
NOTE 1: Port B not available on 8-pin packages
NOTE 2: Port C not available on 8-pin or 16-pin packages.
NOTE 3: VDDA/VREFH and VSSA/VREFL, are double bonded to VDD and VSS respectively.
Figure 1-1. MC9S08SG8 Block Diagram
MC9S08SG8 MCU Series Data Sheet, Rev. 8
22
Freescale Semiconductor
Chapter 1 Device Overview
Table 1-2 provides the functional version of the on-chip modules.
Table 1-2. Module Versions
Module
Version
Analog Comparator (5V)
(ACMP)
2
Analog-to-Digital Converter
(ADC)
1
Central Processor Unit
(CPU)
2
Inter-Integrated Circuit
(IIC)
2
Internal Clock Source
(ICS)
2
Serial Peripheral Interface
(SPI)
3
Serial Communications Interface
(SCI)
4
Modulo Timer
(MTIM)
1
Real-Time Counter
(RTC)
1
Timer Pulse Width Modulator
(TPM)
3
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
23
Chapter 1 Device Overview
1.3
System Clock Distribution
Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock
inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module
function.
The following defines the clocks used in this MCU:
• BUSCLK — The frequency of the bus is always half of ICSOUT.
• ICSOUT — Primary output of the ICS and is twice the bus frequency.
• ICSLCLK — Development tools can select this clock source to speed up BDC communications in
systems where the bus clock is configured to run at a very slow frequency.
• ICSERCLK — External reference clock can be selected as the RTC clock source and as the
alternate clock for the ADC module.
• ICSIRCLK — Internal reference clock can be selected as the RTC clock source.
• ICSFFCLK — Fixed frequency clock can be selected as clock source for the TPM1, TPM2 and
MTIM modules.
• LPOCLK — Independent 1-kHz clock source that can be selected as the clock source for the COP
and RTC modules.
• TCLK — External input clock source for TPM1, TPM2 and MTIM and is referenced as TPMCLK
in TPM chapters.
TCLK
1 kHZ
LPO
LPOCLK
COP
RTC
TPM1
TPM2
MTIM
SCI
SPI
ICSERCLK
ICSIRCLK
ICS
ICSFFCLK
2
ICSOUT
2
FFCLK*
SYNC*
BUSCLK
ICSLCLK
XOSC
CPU
EXTAL
BDC
XTAL
* The fixed frequency clock (FFCLK) is internally
synchronized to the bus clock and must not exceed one
half of the bus clock frequency.
ADC
IIC
ADC has min and max
frequency requirements.
See the ADC chapter
and electricals appendix
for details.
FLASH
FLASH has frequency
requirements for program
and erase operation. See
the electricals appendix
for details.
Figure 1-2. System Clock Distribution Diagram
MC9S08SG8 MCU Series Data Sheet, Rev. 8
24
Freescale Semiconductor
Chapter 2
Pins and Connections
This section describes signals that connect to package pins. It includes pinout diagrams, recommended
system connections, and detailed discussions of signals.
2.1
Device Pin Assignment
Figure 2-1 - Figure 2-3 shows the pin assignments for the MC9S08SG8 devices.
NOTE
20-pin TSSOP package and 8-pin SOIC package are not available for the
AEC Grade 0 high-temperature rated devices.
RESET
BKGD/MS
VDD
VSS
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
PTC3/ADP11
PTC2/ADP10
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+
PTA1/PIA1/TPM2CH0/ADP1/ACMPPTA2/PIA2/SDA/ADP2/ACMPO
PTA3/PIA3/SCL/ADP3
PTB0/PIB0/RxD/ADP4
PTB1/PIB1/TxD/ADP5
PTB2/PIB2/SPSCK/ADP6
PTB3/PIB3/MOSI/ADP7
PTC0/TPM1CH0/ADP8
PTC1/TPM1CH1/ADP9
Figure 2-1. 20-Pin TSSOP
RESET
BKGD/MS
VDD
VSS
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+
PTA1/PIA1/TPM2CH0/ADP1/ACMPPTA2/PIA2/SDA/ADP2/ACMPO
PTA3/PIA3/SCL/ADP3
PTB0/PIB0/RxD/ADP4
PTB1/PIB1/TxD/ADP5
PTB2/PIB2/SPSCK/ADP6
PTB3/PIB3/MOSI/ADP7
Figure 2-2. 16-Pin TSSOP
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
25
Chapter 2 Pins and Connections
RESET
1
8
PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+
BKGD/MS
2
7
PTA1/PIA1/TPM2CH0/ADP1/ACMP-
VDD
3
6
PTA2/PIA2/SDA/ADP2/ACMPO
VSS
4
5
PTA3/PIA3/SCL/ADP3
Figure 2-3. 8-Pin SOIC
MC9S08SG8 MCU Series Data Sheet, Rev. 8
26
Freescale Semiconductor
Chapter 2 Pins and Connections
2.2
Recommended System Connections
Figure 2-4 shows pin connections that are common to MC9S08SG8 application systems.
MC9S08SG8
BACKGROUND HEADER
VDD
BKGD/MS
VDD
PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+
PORT
A
4.7 k–10 k
PTA1/PIA1/TPM2CH0/ADP1/ACMPPTA2/PIA2/SDA/ADP2/ACMPO
PTA3/PIA3/SCL/ADP3
RESET
OPTIONAL
MANUAL
RESET
0.1 F
PTB0/PIB0/RxD/ADP4
PTB1/PIB1/TxD/ADP5
PTC0/TPM1CH0/ADP8
PTC1/TPM1CH1/ADP9
PTC2/ADP10
PTB2/PIB2/SPSCK/ADP6
PORT
C
PORT
B
PTB3/PIB3/MOSI/ADP7
PTB4/TPM2CH1/MISO
PTC3/ADP11
PTB5/TPM1CH1/SS
PTB6/SDA/XTAL
PTB7/SCL/EXTAL
SYSTEM
POWER
+
5V
VDD
CBLK +
10 F
CBY
0.1 F
VSS
RF
C1
X1
RS
C2
NOTE 1
NOTES:
1. External crystal circuit not required if using the internal clock option.
2. RESET pin can only be used to reset into user mode, you can not enter BDM using RESET
pin. BDM can be entered by holding MS low during POR or writing a 1 to BDFR in SBDFR
with MS low after issuing BDM command.
3. RC filter on RESET pin recommended for noisy environments.
Figure 2-4. Basic System Connections
2.2.1
Power
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all
I/O buffer circuitry, ACMP and ADC modules, and to an internal voltage regulator. The internal voltage
regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU.
Typically, application systems have two separate capacitors across the power pins. In this case, there
should be a bulk electrolytic capacitor, such as a 10-F tantalum capacitor, to provide bulk charge storage
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
27
Chapter 2 Pins and Connections
for the overall system and a 0.1-F ceramic bypass capacitor located as near to the MCU power pins as
practical to suppress high-frequency noise. Each pin must have a bypass capacitor for best noise
suppression.
2.2.2
Oscillator (XOSC)
Immediately after reset, the MCU uses an internally generated clock provided by the clock source
generator (ICS) module. For more information on the ICS, see Chapter 10, “Internal Clock Source
(S08ICSV2).”
The oscillator (XOSC) in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic
resonator. Rather than a crystal or ceramic resonator, an external oscillator can be connected to the EXTAL
input pin.
Refer to Figure 2-4 for the following discussion. RS (when used) and RF should be low-inductance
resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have
too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically
designed for high-frequency applications.
RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup; its value
is not generally critical. Typical systems use 1 M to 10 M. Higher values are sensitive to humidity and
lower values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific
crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin
capacitance when selecting C1 and C2. The crystal manufacturer typically specifies a load capacitance
which is the series combination of C1 and C2 (which are usually the same size). As a first-order
approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin
(EXTAL and XTAL).
2.2.3
RESET Pin
RESET is a dedicated pin with open-drain drive containing an internal pull-up device. Internal power-on
reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin is
normally connected to the standard 6-pin background debug connector so a development system can
directly reset the MCU system. If desired, a manual external reset can be added by supplying a simple
switch to ground (pull reset pin low to force a reset).
Whenever any reset is initiated (whether from an external signal or from an internal system), the RESET
pin is driven low for about 66 bus cycles. The reset circuitry decodes the cause of reset and records it by
setting a corresponding bit in the system reset status register (SRS).
NOTE
This pin does not contain a clamp diode to VDD and should not be driven
above VDD.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
28
Freescale Semiconductor
Chapter 2 Pins and Connections
The voltage measured on the internally pulled up RESET pin will not be
pulled to VDD. The internal gates connected to this pin are pulled to VDD. If
the RESET pin is required to drive to a VDD level an external pullup should
be used.
NOTE
In EMC-sensitive applications, an external RC filter is recommended on the
RESET. See Figure 2-4 for an example.
2.2.4
Background / Mode Select (BKGD/MS)
During a power-on-reset (POR) or background debug force reset (see Section 5.7.2, “System Background
Debug Force Reset Register (SBDFR),” for more information), the BKGD/MS pin functions as a mode
select pin. Immediately after any reset, the pin functions as the background pin and can be used for
background debug communication. The BKGD/MS pin contains an internal pullup device.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of the
internal reset after a POR or force BDC reset. If a debug system is connected to the 6-pin standard
background debug header, it can hold BKGD/MS low during a POR or immediately after issuing a
background debug force reset, which will force the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the maximum bus clock rate, so there must never be any significant capacitance
connected to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.2.5
General-Purpose I/O and Peripheral Ports
The MC9S08SG8 series of MCUs support up to 16 general-purpose I/O pins which are shared with
on-chip peripheral functions (timers, serial I/O, ADC, etc.).
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,
software can select one of two drive strengths and enable or disable slew rate control. When a port pin is
configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a
pull-up device. Immediately after reset, all of these pins are configured as high-impedance
general-purpose inputs with internal pull-up devices disabled.
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. For information about controlling these pins as general-purpose I/O
pins, see Chapter 6, “Parallel Input/Output Control.”
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
29
Chapter 2 Pins and Connections
The MC9S08SG8 devices contain a ganged output drive feature that allows a safe and reliable method of
allowing pins to be tied together externally to produce a higher output current drive. See Section 6.3,
“Ganged Output” for more information for configuring the port pins for ganged output drive.
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program should either enable on-chip pull-up
devices or change the direction of unused pins to outputs so they do not
float.
When using the 8-pin devices, the user must either enable on-chip pullup
devices or change the direction of non-bonded out port B and port C pins to
outputs so the pins do not float.
When using the 16-pin devices, the user must either enable on-chip pullup
devices or change the direction of non-bonded out port C pins to outputs so
the pins do not float.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
30
Freescale Semiconductor
Chapter 2 Pins and Connections
Table 2-1. Pin Availability by Package Pin-Count
Priority
Pin Number
20-pin
16-pin
8-pin
1
1
1
2
2
2
3
3
3
4
4
4
5
6
5
6
—
—
Port Pin
Highest
Alt 1
Alt 2
Alt 3
Alt 4
BKGD
VSS
PTB7
SCL1
PTB6
SDA1
EXTAL
XTAL
—
PTB5
TPM1CH1
SS
PTC03
8
8
—
PTB4
TPM2CH1
MISO
PTC03
9
—
—
PTC3
PTC03
ADP11
PTC2
3
—
2
PTC0
ADP10
2
ADP9
11
—
—
PTC1
TPM1CH1
PTC03
12
—
—
PTC0
TPM1CH02
PTC03
ADP8
3
ADP7
3
ADP6
13
9
—
PTB3
PIB3
MOSI
14
10
—
PTB2
PIB2
SPSCK
15
11
—
PTB1
PIB1
TxD
16
12
—
PTB0
PIB0
RxD
17
18
19
20
13
14
15
16
5
6
7
8
MS
VDD
7
—
Alt5
RESET
7
10
1
Lowest
PTA3
PTA2
PTA1
PTA0
PIA3
PIA2
PTC0
PTC0
ADP5
ADP4
1
ADP3
1
ADP2
SCL
SDA
ACMPO
PIA1
TPM2CH0
ADP1
ACMP–4
PIA0
TPM1CH02
ADP04
ACMP+4
TCLK
4
IIC pins can be repositioned using IICPS in SOPT2, default reset locations are on PTA2 and PTA3.
2
TPM1CHx pins can be repositioned using TPM1PS in SOPT2, default reset locations are on PTA0 and
PTB5.
3 This port pin is part of the ganged output feature. When pin is enabled for ganged output, it will have priority
over all digital modules. The output data, drive strength and slew-rate control of this port pin will follow the
configuration for the PTC0 pin, even in 16-pin packages where PTC0 doesn’t bond out. Ganged output not
available in 8-pin packages.
4 If ACMP and ADC are both enabled, both will have access to the pin.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
31
Chapter 2 Pins and Connections
MC9S08SG8 MCU Series Data Sheet, Rev. 8
32
Freescale Semiconductor
Chapter 3
Modes of Operation
3.1
Introduction
The operating modes of the MC9S08SG8 are described in this chapter. Entry into each mode, exit from
each mode, and functionality while in each of the modes are described.
3.2
•
•
•
3.3
Features
Active background mode for code development
Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation
is maintained
Stop modes — System clocks are stopped and voltage regulator is in standby
— Stop3 — All internal circuits are powered for fast recovery
— Stop2 — Partial power down of internal circuits, RAM content is retained
Run Mode
This is the normal operating mode for the MC9S08SG8. This mode is selected upon the MCU exiting reset
if the BKGD/MS pin is high. In this mode, the CPU executes code from internal memory with execution
beginning at the address fetched from memory at 0xFFFE–0xFFFF after reset.
3.4
Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for
analyzing MCU operation during software development.
Active background mode is entered in any of the following ways:
• When the BKGD/MS pin is low during POR or immediately after issuing a background debug
force reset (see Section 5.7.2, “System Background Debug Force Reset Register (SBDFR)”)
• When a BACKGROUND command is received through the BKGD/MS pin
• When a BGND instruction is executed
• When encountering a BDC breakpoint
• When encountering a DBG breakpoint
After entering active background mode, the CPU is held in a suspended state waiting for serial background
commands rather than executing instructions from the user application program.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
33
Chapter 3 Modes of Operation
Background commands are of two types:
• Non-intrusive commands, defined as commands that can be issued while the user program is
running. Non-intrusive commands can be issued through the BKGD/MS pin while the MCU is in
run mode; non-intrusive commands can also be executed when the MCU is in the active
background mode. Non-intrusive commands include:
— Memory access commands
— Memory-access-with-status commands
— BDC register access commands
— The BACKGROUND command
• Active background commands, which can only be executed while the MCU is in active background
mode. Active background commands include commands to:
— Read or write CPU registers
— Trace one user program instruction at a time
— Leave active background mode to return to the user application program (GO)
The active background mode is used to program a bootloader or user application program into the FLASH
program memory before the MCU is operated in run mode for the first time. When the MC9S08SG8 is
shipped from the Freescale Semiconductor factory, the FLASH program memory is erased by default
unless specifically noted so there is no program that could be executed in run mode until the FLASH
memory is initially programmed. The active background mode can also be used to erase and reprogram
the FLASH memory after it has been previously programmed.
For additional information about the active background mode, refer to the Development Support chapter.
3.5
Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the
wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and
resumes processing, beginning with the stacking operations leading to the interrupt service routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can
be used. Only the BACKGROUND command and memory-access-with-status commands are available
when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access,
but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND
command can be used to wake the MCU from wait mode and enter active background mode.
3.6
Stop Modes
One of two stop modes is entered upon execution of a STOP instruction when STOPE in SOPT1. In any
stop mode, the bus and CPU clocks are halted. The ICS module can be configured to leave the reference
clocks running. See Chapter 10, “Internal Clock Source (S08ICSV2),” for more information.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
34
Freescale Semiconductor
Chapter 3 Modes of Operation
Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various
conditions. The selected mode is entered following the execution of a STOP instruction.
Table 3-1. Stop Mode Selection
STOPE
ENBDM 1
0
x
1
LVDE
LVDSE
PPDC
Stop Mode
x
x
Stop modes disabled; illegal opcode reset if STOP instruction executed
1
x
x
Stop3 with BDM enabled 2
1
0
Both bits must be 1
x
Stop3 with voltage regulator active
1
0
Either bit a 0
0
Stop3
1
0
Either bit a 0
1
Stop2
1
ENBDM is located in the BDCSCR, which is only accessible through BDC commands, see Section 17.4.1.1, “BDC Status and
Control Register (BDCSCR)”.
2 When in Stop3 mode with BDM enabled, The S
IDD will be near RIDD levels because internal clocks are enabled.
3.6.1
Stop3 Mode
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time
counter (RTC), LVD system, ACMP, ADC, SCI, or any pin interrupts.
If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking
the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the
appropriate interrupt vector.
3.6.1.1
LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. For configuring the LVD system for interrupt or reset, refer to 5.6, “Low-Voltage Detect
(LVD) System”. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode.
For the ADC to operate in stop mode, the LVD must be enabled when entering stop3.
For the ACMP to operate in stop mode with compare to internal bandgap option, the LVD must be enabled
when entering stop3.
3.6.1.2
Active BDM Enabled in Stop Mode
Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This
register is described in Chapter 17, “Development Support.” If ENBDM is set when the CPU executes a
STOP instruction, the system clocks to the background debug logic remain active when the MCU enters
stop mode. Because of this, background debug communication remains possible. In addition, the voltage
regulator does not enter its low-power standby state but maintains full internal regulation.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
35
Chapter 3 Modes of Operation
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After entering background debug mode, all background
commands are available.
3.6.2
Stop2 Mode
Stop2 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most
of the internal circuitry of the MCU is powered off in stop2 with the exception of the RAM. Upon entering
stop2, all I/O pin control signals are latched so that the pins retain their states during stop2.
Exit from stop2 is performed by asserting the wake-up pin (RESET) on the MCU.
In addition, the real-time counter (RTC) can wake the MCU from stop2, if enabled.
Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR):
• All module control and status registers are reset
• The LVD reset function is enabled and the MCU remains in the reset state if VDD is below the LVD
trip point (low trip point selected due to POR)
• The CPU takes the reset vector
In addition to the above, upon waking up from stop2, the PPDF bit in SPMSC2 is set. This flag is used to
direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched
until a 1 is written to PPDACK in SPMSC2.
To maintain I/O states for pins that were configured as general-purpose I/O before entering stop2, the user
must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers
before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to
PPDACK, then the pins will switch to their reset states when PPDACK is written.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
3.6.3
On-Chip Peripheral Modules in Stop Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.2, “Stop2
Mode,” and Section 3.6.1, “Stop3 Mode,” for specific information on system behavior in stop modes.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
36
Freescale Semiconductor
Chapter 3 Modes of Operation
Table 3-2. Stop Mode Behavior
Mode
Peripheral
Stop2
Stop3
CPU
Off
Standby
RAM
Standby
Standby
FLASH
Off
Standby
Parallel Port Registers
Off
Standby
ADC
Off
Optionally On1
ACMP
Off
Optionally On2
BDM
Off3
Optionally On
ICS
Off
Optionally On4
IIC
Off
Standby
5
Optionally On
LVD/LVW
Off
MTIM
Off
Standby
RTC
Optionally On
Optionally On
SCI
Off
Standby
SPI
Off
Standby
TPM
Off
Standby
Standby
Optionally On6
Off
Optionally On7
States Held
States Held
Voltage Regulator
XOSC
I/O Pins
1
2
3
4
5
6
7
Requires the asynchronous ADC clock and LVD to be enabled, else in
standby.
Requires the LVD to be enabled when compare to internal bandgap reference
option is enabled.
If ENBDM is set when entering stop2, the MCU will actually enter stop3.
IRCLKEN and IREFSTEN set in ICSC1, else in standby.
If LVDSE is set when entering stop2, the MCU will actually enter stop3.
Voltage regulator will be on if BDM is enabled or if LVD is enabled when
entering stop3.
ERCLKEN and EREFSTEN set in ICSC2, else in standby. For high frequency
range (RANGE in ICSC2 set) requires the LVD to also be enabled in stop3.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
37
Chapter 3 Modes of Operation
MC9S08SG8 MCU Series Data Sheet, Rev. 8
38
Freescale Semiconductor
Chapter 4
Memory
4.1
MC9S08SG8 Memory Map
As shown in Figure 4-1, on-chip memory in the MC9S08SG8 series of MCUs consists of RAM, FLASH
program memory for nonvolatile data storage, and I/O and control/status registers. The registers are
divided into three groups:
• Direct-page registers (0x0000 through 0x007F)
• High-page registers (0x1800 through 0x185F)
• Nonvolatile registers (0xFFB0 through 0xFFBF)
0x0000
0x007F
0x0080
DIRECT PAGE REGISTERS
RAM
512 BYTES
0x027F
0x0280
0x17FF
0x1800
UNIMPLEMENTED
5504 BYTES
0x0000
0x007F
0x0080
0x017F
0x0180
0x027F
0x0280
0x17FF
0x1800
DIRECT PAGE REGISTERS
RAM
256 BYTES
RESERVED
256 BYTES
UNIMPLEMENTED
5504 BYTES
HIGH PAGE REGISTERS
HIGH PAGE REGISTERS
0x185F
0x1860
0x185F
0x1860
UNIMPLEMENTED
UNIMPLEMENTED
51,104 BYTES
51,104 BYTES
0xDFFF
0xE000
0xDFFF
0xE000
RESERVED
FLASH
8192 BYTES
0xEFFF
0xF000
4096 BYTES
FLASH
4096 BYTES
0xFFFF
0xFFFF
MC9S08SG8
MC9S08SG4
Figure 4-1. MC9S08SG8 Memory Map
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
39
Chapter 4 Memory
4.2
Reset and Interrupt Vector Assignments
Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table
are the labels used in the Freescale Semiconductor provided equate file for the MC9S08SG8.
Table 4-1. Reset and Interrupt Vectors
Address
(High/Low)
Vector
Vector Name
0xFFC0:0xFFC1
Unused Vector Space (available for user program)
—
0xFFC2:0xFFC3
ACMP
Vacmp
0xFFC4:0xFFC5
Unused Vector Space (available for user program)
—
0xFFC6:0xFFC7
Unused Vector Space (available for user program)
—
0xFFC8:0xFFC9
Unused Vector Space (available for user program)
—
0xFFCA:0xFFCB
MTIM Overflow
Vmtim
0xFFCC:0xFFCD
RTC
Vrtc
0xFFCE:0xFFCF
IIC
Viic
0xFFD0:0xFFD1
ADC Conversion
Vadc
0xFFD2:0xFFD3
Unused Vector Space (available for user program)
—
0xFFD4:0xFFD5
Port B Pin Interrupt
Vportb
0xFFD6:0xFFD7
Port A Pin Interrupt
Vporta
0xFFD8:0xFFD9
Unused Vector Space (available for user program)
—
0xFFDA:0xFFDB
SCI Transmit
Vscitx
0xFFDC:0xFFDD
SCI Receive
Vscirx
0xFFDE:0xFFDF
SCI Error
Vscierr
0xFFE0:0xFFE1
SPI
Vspi
0xFFE2:0xFFE3
TPM2 Overflow
Vtpm2ovf
0xFFE4:0xFFE5
TPM2 Channel 1
Vtpm2ch1
0xFFE6:0xFFE7
TPM2 Channel 0
Vtpm2ch0
0xFFE8:0xFFE9
TPM1 Overflow
Vtpm1ovf
0xFFEA:0xFFEB
Unused Vector Space (available for user program)
—
0xFFEC:0xFFED
Unused Vector Space (available for user program)
—
0xFFEE:0xFFEF
Unused Vector Space (available for user program)
—
0xFFF0:0xFFF1
Unused Vector Space (available for user program)
—
0xFFF2:0xFFF3
TPM1 Channel 1
Vtpm1ch1
0xFFF4:0xFFF5
TPM1 Channel 0
Vtpm1ch0
0xFFF6:0xFFF7
Unused Vector Space (available for user program)
—
0xFFF8:0xFFF9
Low Voltage Detect
Vlvd
0xFFFA:0xFFFB
Unused Vector Space (available for user program)
—
0xFFFC:0xFFFD
SWI
Vswi
0xFFFE:0xFFFF
Reset
Vreset
MC9S08SG8 MCU Series Data Sheet, Rev. 8
40
Freescale Semiconductor
Chapter 4 Memory
4.3
Register Addresses and Bit Assignments
The registers in the MC9S08SG8 are divided into these groups:
• Direct-page registers are located in the first 128 locations in the memory map; these are accessible
with efficient direct addressing mode instructions.
• High-page registers are used much less often, so they are located above 0x1800 in the memory
map. This leaves more room in the direct page for more frequently used registers and RAM.
• The nonvolatile register area consists of a block of 16 locations in FLASH memory at
0xFFB0–0xFFBF. Nonvolatile register locations include:
— NVPROT and NVOPT are loaded into working registers at reset
— An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to
secure memory
Because the nonvolatile register locations are FLASH memory, they must be erased and
programmed like other FLASH memory locations.
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation
instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all
user-accessible direct-page registers and control bits.
The direct page registers in Table 4-2 can use the more efficient direct addressing mode, which requires
only the lower byte of the address. Because of this, the lower byte of the address in column one is shown
in bold text. In Table 4-3 and Table 4-4, the whole address in column one is shown in bold. In Table 4-2,
Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart from the
bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0
indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit
locations that could read as 1s or 0s.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
41
Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 1 of 3)
Address
0x0000
Register
Name
PTAD
0x0001
PTADD
0x0002
PTBD
0x0003
PTBDD
0x0004
PTCD
0x0005
PTCDD
0x0006–
Reserved
0x000D
Bit 7
6
5
4
3
2
1
Bit 0
0
0
—
—
PTAD3
PTAD2
PTAD1
PTAD0
0
0
—
—
PTADD3
PTADD2
PTADD1
PTADD0
PTBD7
PTBD6
PTBD5
PTBD4
PTBD3
PTBD2
PTBD1
PTBD0
PTBDD7
PTBDD6
PTBDD5
PTBDD4
PTBDD3
PTBDD2
PTBDD1
PTBDD0
0
0
0
0
PTCD3
PTCD2
PTCD1
PTCD0
0
0
0
0
PTCDD3
PTCDD2
PTCDD1
PTCDD0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x000E
ACMPSC
ACME
ACBGS
ACF
ACIE
ACO
ACOPE
ACMOD1
ACMOD0
0x000F
Reserved
—
—
—
—
—
—
—
—
0x0010
ADCSC1
COCO
AIEN
ADCO
0x0011
ADCSC2
ADACT
ADTRG
ACFE
ACFGT
—
—
—
—
0x0012
ADCRH
0
0
0
0
0
0
ADR9
ADR8
0x0013
ADCRL
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
0x0014
ADCVH
0
0
0
0
0
0
ADCV9
ADCV8
0x0015
ADCVL
ADCV7
ADCV6
ADCV5
ADCV4
ADCV3
ADCV2
ADCV1
ADCV0
0x0016
ADCFG
ADLPC
0x0017
APCTL1
ADPC7
0x0018
APCTL2
0x0019–
Reserved
0x001B
ADCH
ADIV
ADPC6
ADLSMP
ADPC5
MODE
ADICLK
ADPC4
ADPC3
ADPC2
ADPC1
ADPC0
0
0
0
0
ADPC11
ADPC10
ADPC9
ADPC8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TOF
TOIE
TRST
TSTP
0
0
0
0
0
0
0x001C
MTIMSC
0x001D
MTIMCLK
0x001E
MTIMCNT
CNT
0x001F
MTIMMOD
MOD
0x0020
TPM1SC
TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
0x0021
TPM1CNTH
Bit 15
14
13
12
11
10
9
Bit 8
0x0022
TPM1CNTL
Bit 7
6
5
4
3
2
1
Bit 0
0x0023
TPM1MODH
Bit 15
14
13
12
11
10
9
Bit 8
0x0024
TPM1MODL
Bit 7
6
5
4
3
2
1
Bit 0
0x0025
TPM1C0SC
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
0
0
0x0026
TPM1C0VH
Bit 15
14
13
12
11
10
9
Bit 8
0x0027
TPM1C0VL
Bit 7
6
5
4
3
2
1
Bit 0
0x0028
TPM1C1SC
CH1F
CH1IE
MS1B
MS1A
ELS1B
ELS1A
0
0
0x0029
TPM1C1VH
Bit 15
14
13
12
11
10
9
Bit 8
0x002A
TPM1C1VL
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LBKDIE
RXEDGIE
0
SBR12
SBR11
SBR10
SBR9
SBR8
0x002B–
Reserved
0x0037
0x0038
SCIBDH
CLKS
PS
MC9S08SG8 MCU Series Data Sheet, Rev. 8
42
Freescale Semiconductor
Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 2 of 3)
Address
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
0x0039
SCIBDL
0x003A
SCIC1
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
0x003B
SCIC2
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0x003C
SCIS1
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
0x003D
SCIS2
LBKDIF
RXEDGIF
0
RXINV
RWUID
BRK13
LBKDE
RAF
0x003E
SCIC3
R8
T8
TXDIR
TXINV
ORIE
NEIE
FEIE
PEIE
0x003F
SCID
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IREFS
IRCLKEN
IREFSTEN
EREFS
ERCLKEN EREFSTEN
0x0040–
Reserved
0x0047
0x0048
ICSC1
CLKS
0x0049
ICSC2
BDIV
0x004A
ICSTRM
0x004B
ICSSC
0x004C–
Reserved
0x004F
RDIV
RANGE
HGO
LP
TRIM
0
0
0
IREFST
—
—
—
—
—
—
—
—
CLKST
—
—
—
—
OSCINIT
FTRIM
—
—
—
—
0x0050
SPIC1
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0x0051
SPIC2
0
0
0
MODFEN
BIDIROE
0
SPISWAI
SPC0
0x0052
SPIBR
0
SPPR2
SPPR1
SPPR0
0
SPR2
SPR1
SPR0
0x0053
SPIS
SPRF
0
SPTEF
MODF
0
0
0
0
0x0054
Reserved
0x0055
SPID
0x0056–
Reserved
0x0057
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AD7
AD6
AD5
AD4
AD3
AD2
AD1
0
0x0058
IICA
0x0059
IICF
0x005A
IICC1
IICEN
IICIE
MST
TX
TXAK
RSTA
0
0
0x005B
IICS
TCF
IAAS
BUSY
ARBL
0
SRW
IICIF
RXAK
0x005C
IICD
0x005D
IICC2
0x005E–
Reserved
0x005F
MULT
ICR
DATA
GCAEN
ADEXT
0
0
0
AD10
AD9
AD8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x0060
TPM2SC
TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
0x0061
TPM2CNTH
Bit 15
14
13
12
11
10
9
Bit 8
0x0062
TPM2CNTL
Bit 7
6
5
4
3
2
1
Bit 0
0x0063
TPM2MODH
Bit 15
14
13
12
11
10
9
Bit 8
0x0064
TPM2MODL
Bit 7
6
5
4
3
2
1
Bit 0
0x0065
TPM2C0SC
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
0
0
0x0066
TPM2C0VH
Bit 15
14
13
12
11
10
9
Bit 8
0x0067
TPM2C0VL
Bit 7
6
5
4
3
2
1
Bit 0
0x0068
TPM2C1SC
CH1F
CH1IE
MS1B
MS1A
ELS1B
ELS1A
0
0
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
43
Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 3 of 3)
Address
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
TPM2C1VH
Bit 15
14
13
12
11
10
9
Bit 8
0x006A
TPM2C1VL
Bit 7
6
5
4
3
2
1
Bit 0
0x006B
Reserved
—
—
—
—
—
—
—
—
0x006C
RTCSC
0x006D
RTCCNT
0x006E
RTCMOD
—
—
—
—
0x0069
0x006F Reserved
0x007F
RTIF
RTCLKS
RTIE
RTCPS
RTCCNT
RTCMOD
—
—
—
—
—
—
—
—
—
—
—
—
MC9S08SG8 MCU Series Data Sheet, Rev. 8
44
Freescale Semiconductor
Chapter 4 Memory
High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers
so they have been located outside the direct addressable memory space, starting at 0x1800.
Table 4-3. High-Page Register Summary (Sheet 1 of 2)
Address
Register Name
0x1800
SRS
0x1801
SBDFR
0x1802
SOPT1
0x1803
SOPT2
0x1804 –
0x1805
Bit 7
6
5
4
3
2
1
POR
PIN
COP
ILOP
ILAD
0
LVD
0
0
0
0
0
0
0
0
BDFR
STOPE
0
0
IICPS
0
0
COPT
Bit 0
COPCLKS
COPW
0
ACIC
0
0
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1806
SDIDH
1
—
—
—
ID11
ID10
ID9
ID8
0x1807
SDIDL
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0x1808
Reserved
—
—
—
—
—
—
—
—
0x1809
SPMSC1
LVWF
LVWACK
LVWIE
LVDRE
LVDSE
LVDE
0
BGBE
0x180A
SPMSC2
0
0
LVDV
LVWV
PPDF
PPDACK
—
PPDC
0x180B–
0x180F
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1810
DBGCAH
Bit 15
14
13
12
11
10
9
Bit 8
0x1811
DBGCAL
Bit 7
6
5
4
3
2
1
Bit 0
0x1812
DBGCBH
Bit 15
14
13
12
11
10
9
Bit 8
0x1813
DBGCBL
Bit 7
6
5
4
3
2
1
Bit 0
0x1814
DBGFH
Bit 15
14
13
12
11
10
9
Bit 8
0x1815
DBGFL
Bit 7
6
5
4
3
2
1
Bit 0
0x1816
DBGC
DBGEN
ARM
TAG
BRKEN
RWA
RWAEN
RWB
RWBEN
0x1817
DBGT
TRGSEL
BEGIN
0
0
TRG3
TRG2
TRG1
TRG0
0x1818
DBGS
AF
BF
ARMF
0
CNT3
CNT2
CNT1
CNT0
0x1819–
0x181F
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1820
FCDIV
DIVLD
PRDIV8
0x1821
FOPT
KEYEN
FNORED
0
0
0
0
0x1822
Reserved
—
—
—
—
—
—
—
0x1823
FCNFG
0
0
KEYACC
0
0
0
0
0x1824
FPROT
0x1825
FSTAT
0x1826
FCMD
0x1827–
0x183F
Reserved
—
—
—
—
—
—
0x1840
PTAPE
0
0
0x1841
PTASE
0
0x1842
PTADS
0x1843
0x1844
T1CH1PS T1CH0PS
DIV
SEC
FPS
FCBEF
FCCF
FPVIOL
—
0
FPDIS
FACCERR
0
FBLANK
0
0
—
—
—
—
—
—
—
—
—
—
—
—
PTAPE3
PTAPE2
PTAPE1
PTAPE0
0
—
—
PTASE3
PTASE2
PTASE1
PTASE0
0
0
—
—
PTADS3
PTADS2
PTADS1
PTADS0
Reserved
—
—
—
—
—
—
—
—
PTASC
0
0
0
0
PTAIF
PTAACK
PTAIE
PTAMOD
FCMD
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
45
Chapter 4 Memory
Table 4-3. High-Page Register Summary (Sheet 2 of 2)
Address
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
0x1845
PTAPS
0
0
0
0
PTAPS3
PTAPS2
PTAPS1
PTAPS0
0x1846
PTAES
0
0
0
0
PTAES3
PTAES2
PTAES1
PTAES0
0x1847
Reserved
—
—
—
—
—
—
—
—
0x1848
PTBPE
PTBPE7
PTBPE6
PTBPE5
PTBPE4
PTBPE3
PTBPE2
PTBPE1
PTBPE0
0x1849
PTBSE
PTBSE7
PTBSE6
PTBSE5
PTBSE4
PTBSE3
PTBSE2
PTBSE1
PTBSE0
0x184A
PTBDS
PTBDS7
PTBDS6
PTBDS5
PTBDS4
PTBDS3
PTBDS2
PTBDS1
PTBDS0
0x184B
Reserved
—
—
—
—
—
—
—
—
0x184C
PTBSC
0
0
0
0
PTBIF
PTBACK
PTBIE
PTBMOD
0x184D
PTBPS
0
0
0
0
PTBPS3
PTBPS2
PTBPS1
PTBPS0
0x184E
PTBES
0
0
0
0
PTBES3
PTBES2
PTBES1
PTBES0
0x184F
Reserved
—
—
—
—
—
—
—
—
0x1850
PTCPE
0
0
0
0
PTCPE3
PTCPE2
PTCPE1
PTCPE0
0x1851
PTCSE
0
0
0
0
PTCSE3
PTCSE2
PTCSE1
PTCSE0
0x1852
PTCDS
0
0
0
0
PTCDS3
PTCDS2
PTCDS1
PTCDS0
0x1853
GNGC
GNGPS7
GNGPS6
GNGPS5
GNGPS4
GNGPS3
GNGPS2
GNGPS1
GNGEN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1854–
0x185F
Reserved
MC9S08SG8 MCU Series Data Sheet, Rev. 8
46
Freescale Semiconductor
Chapter 4 Memory
Nonvolatile FLASH registers, shown in Table 4-4, are located in the FLASH memory. These registers
include an 8-byte backdoor key, NVBACKKEY, which can be used to gain access to secure memory
resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of
the FLASH memory are transferred into corresponding FPROT and FOPT working registers in the
high-page registers to control security and block protection options.
Table 4-4. Nonvolatile Register Summary
Address
Register Name
0xFFAE
Reserved for
storage of FTRIM
0xFFAF
Reserved for
storage of ICSTRM
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
FTRIM
—
—
—
—
—
—
TRIM
0xFFB0 – NVBACKKEY
0xFFB7
0xFFB8 – Reserved
0xFFBC
0xFFBD
NVPROT
0xFFBE
Reserved
0xFFBF
NVOPT
8-Byte Comparison Key
—
—
—
—
—
—
—
—
—
—
FPS
FPDIS
—
—
—
—
—
—
KEYEN
FNORED
—
—
—
—
—
—
SEC
Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily
disengage memory security. This key mechanism can be accessed only through user code running in secure
memory. (A security key cannot be entered directly through background debug commands.) This security
key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the
only way to disengage security is by mass erasing the FLASH if needed (normally through the background
debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset,
program the security bits (SEC) to the unsecured state (1:0).
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
47
Chapter 4 Memory
4.4
RAM
The MC9S08SG8 includes static RAM. The locations in RAM below 0x0100 can be accessed using the
more efficient direct addressing mode, and any single bit in this area can be accessed with the bit
manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed
program variables in this area of RAM is preferred.
The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on the
contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage
does not drop below the minimum value for RAM retention (VRAM).
For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the
MC9S08SG8, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct page
RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include
the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the
highest address of the RAM in the Freescale Semiconductor-provided equate file).
LDHX
TXS
#RamLast+1
;point one past RAM
;SP 59){
Minutes++;
Seconds = 0;
}
/* 60 minutes in an hour */
if (Minutes > 59){
Hours++;
Minutes = 0;
}
/* 24 hours in a day */
if (Hours > 23){
Days ++;
Hours = 0;
}
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
197
Real-Time Counter (S08RTCV1)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
198
Freescale Semiconductor
Chapter 14
Serial Communications Interface (S08SCIV4)
14.1
Introduction
Figure 14-1 shows the MC9S08SG8 block diagram with the SCI module highlighted.
MC9S08SG8 MCU Series Data Sheet, Rev.8
Freescale Semiconductor
199
Chapter 14 Serial Communications Interface (S08SCIV4)
HCS08 CORE
DEBUG MODULE (DBG)
BKGD/MS
8-BIT MODULO TIMER
MODULE (MTIM)
HCS08 SYSTEM CONTROL
SCL
LVD
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER FLASH
(MC9S08SG8 = 8,192 BYTES)
(MC9S08SG4 = 4096 BYTES)
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI)
USER RAM
(MC9S08SG8 = 512 BYTES)
(MC9S08SG4 = 256 BYTES)
16-BIT TIMER/PWM
MODULE (TPM1)
REAL-TIME COUNTER (RTC)
16-BIT TIMER/PWM
MODULE (TPM2)
40-MHz INTERNAL CLOCK
SOURCE (ICS)
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
VOLTAGE
REGULATOR
VSS
VDDA
VSSA
VREFH
VREFL
SS
MISO
MOSI
SPSCK
PTA3/PAI3/SCL/ADP3
PTA1/PIA1/TPM2CH0/ADP1/ACMP–
PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+
SEE NOTE 1, 2
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
TCLK
TPM1CH0
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
PTB3/PIB3/MOSI/ADP7
PTB2/PIB2/SPSCK/ADP6
TPM1CH1
PTB1/PIB1/TxD/ADP5
PTB0/PIB0/RxD/ADP4
TCLK
TPM2CH0
TPM2CH1
XTAL
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
PTA2/PAI2/SDA/ADP2/ACMPO
RxD
TxD
SEE NOTE 1, 2
EXTAL
ANALOG COMPARATOR
(ACMP)
SEE NOTE 3
VDD
SDA
PORT A
IIC MODULE (IIC)
PORT B
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
COP
TCLK
ACMPO
ACMP–
ACMP+
PORT C
BDC
CPU
RESET
PTC3/ADP11
PTC2/ADP10
PTC1/TPM1CH1/ADP9
PTC0/TPM1CH0/ADP8
ADP11-ADP0
NOTES
= Pin can be enabled as part of the ganged output drive feature.
NOTE 1: Port B not available on 8-pin packages
NOTE 2: Port C not available on 8-pin or 16-pin packages.
NOTE 3: VDDA/VREFH and VSSA/VREFL, are double bonded to VDD and VSS respectively.
Figure 14-1. MC9S08SG8 Block Diagram with SCI Module Highlighted
MC9S08SG8 MCU Series Data Sheet, Rev.8
200
Freescale Semiconductor
Serial Communications Interface (S08SCIV4)
14.1.1
Features
Features of SCI module include:
• Full-duplex, standard non-return-to-zero (NRZ) format
• Double-buffered transmitter and receiver with separate enables
• Programmable baud rates (13-bit modulo divider)
• Interrupt-driven or polled operation:
— Transmit data register empty and transmission complete
— Receive data register full
— Receive overrun, parity error, framing error, and noise error
— Idle receiver detect
— Active edge on receive pin
— Break detect supporting LIN
• Hardware parity generation and checking
• Programmable 8-bit or 9-bit character length
• Receiver wakeup by idle-line or address-mark
• Optional 13-bit break character generation / 11-bit break character detection
• Selectable transmitter output polarity
14.1.2
Modes of Operation
See Section 14.3, “Functional Description,” For details concerning SCI operation in these modes:
• 8- and 9-bit data modes
• Stop mode operation
• Loop mode
• Single-wire mode
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
201
Serial Communications Interface (S08SCIV4)
14.1.3
Block Diagram
Figure 14-2 shows the transmitter portion of the SCI.
INTERNAL BUS
(WRITE-ONLY)
LOOPS
SCID – Tx BUFFER
RSRC
LOOP
CONTROL
STOP
M
START
11-BIT TRANSMIT SHIFT REGISTER
8
7
6
5
4
3
2
1
0
TO TxD PIN
L
LSB
H
1 BAUD
RATE CLOCK
TO RECEIVE
DATA IN
SHIFT DIRECTION
PT
BREAK (ALL 0s)
PARITY
GENERATION
PREAMBLE (ALL 1s)
PE
SHIFT ENABLE
T8
LOAD FROM SCID
TXINV
SCI CONTROLS TxD
TE
SBK
TRANSMIT CONTROL
TXDIR
TxD DIRECTION
TO TxD
PIN LOGIC
BRK13
TDRE
TIE
TC
Tx INTERRUPT
REQUEST
TCIE
Figure 14-2. SCI Transmitter Block Diagram
MC9S08SG8 MCU Series Data Sheet, Rev. 8
202
Freescale Semiconductor
Serial Communications Interface (S08SCIV4)
Figure 14-3 shows the receiver portion of the SCI.
INTERNAL BUS
(READ-ONLY)
16 BAUD
RATE CLOCK
DIVIDE
BY 16
SCID – Rx BUFFER
LBKDE
H
DATA RECOVERY
WAKE
ILT
8
7
6
5
4
3
2
1
START
FROM RxD PIN
RXINV
M
LSB
RSRC
11-BIT RECEIVE SHIFT REGISTER
MSB
SINGLE-WIRE
LOOP CONTROL
ALL 1s
LOOPS
STOP
FROM
TRANSMITTER
0
L
SHIFT DIRECTION
WAKEUP
LOGIC
RWU
RWUID
ACTIVE EDGE
DETECT
RDRF
RIE
IDLE
ILIE
LBKDIF
Rx INTERRUPT
REQUEST
LBKDIE
RXEDGIF
RXEDGIE
OR
ORIE
FE
FEIE
NF
ERROR INTERRUPT
REQUEST
NEIE
PE
PT
PARITY
CHECKING
PF
PEIE
Figure 14-3. SCI Receiver Block Diagram
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
203
Serial Communications Interface (S08SCIV4)
14.2
Register Definition
The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for
transmit/receive data.
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all SCI registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
14.2.1
SCI Baud Rate Registers (SCIBDH, SCIBDL)
This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud
rate setting [SBR12:SBR0], first write to SCIBDH to buffer the high half of the new value and then write
to SCIBDL. The working value in SCIBDH does not change until SCIBDL is written.
SCIBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first
time the receiver or transmitter is enabled (RE or TE bits in SCIC2 are written to 1).
7
6
5
LBKDIE
RXEDGIE
0
0
R
4
3
2
1
0
SBR12
SBR11
SBR10
SBR9
SBR8
0
0
0
0
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 14-4. SCI Baud Rate Register (SCIBDH)
Table 14-1. SCIBDH Field Descriptions
Field
7
LBKDIE
Description
LIN Break Detect Interrupt Enable (for LBKDIF)
0 Hardware interrupts from LBKDIF disabled (use polling).
1 Hardware interrupt requested when LBKDIF flag is 1.
6
RXEDGIE
RxD Input Active Edge Interrupt Enable (for RXEDGIF)
0 Hardware interrupts from RXEDGIF disabled (use polling).
1 Hardware interrupt requested when RXEDGIF flag is 1.
4:0
SBR[12:8]
Baud Rate Modulo Divisor — The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the
modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to
reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16BR). See also BR bits in
Table 14-2.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
204
Freescale Semiconductor
Serial Communications Interface (S08SCIV4)
7
6
5
4
3
2
1
0
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
0
0
0
0
0
1
0
0
R
W
Reset
Figure 14-5. SCI Baud Rate Register (SCIBDL)
Table 14-2. SCIBDL Field Descriptions
Field
7:0
SBR[7:0]
14.2.2
Description
Baud Rate Modulo Divisor — These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the
modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to
reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16BR). See also BR bits in
Table 14-1.
SCI Control Register 1 (SCIC1)
This read/write register is used to control various optional features of the SCI system.
7
6
5
4
3
2
1
0
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-6. SCI Control Register 1 (SCIC1)
Table 14-3. SCIC1 Field Descriptions
Field
Description
7
LOOPS
Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS = 1,
the transmitter output is internally connected to the receiver input.
0 Normal operation — RxD and TxD use separate pins.
1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See
RSRC bit.) RxD pin is not used by SCI.
6
SCISWAI
SCI Stops in Wait Mode
0 SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes up the CPU.
1 SCI clocks freeze while CPU is in wait mode.
5
RSRC
4
M
Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When
LOOPS = 1, the receiver input is internally connected to the TxD pin and RSRC determines whether this
connection is also connected to the transmitter output.
0 Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins.
1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input.
9-Bit or 8-Bit Mode Select
0 Normal — start + 8 data bits (LSB first) + stop.
1 Receiver and transmitter use 9-bit data characters
start + 8 data bits (LSB first) + 9th data bit + stop.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
205
Serial Communications Interface (S08SCIV4)
Table 14-3. SCIC1 Field Descriptions (continued)
Field
3
WAKE
Description
Receiver Wakeup Method Select — Refer to Section 14.3.3.2, “Receiver Wakeup Operation” for more
information.
0 Idle-line wakeup.
1 Address-mark wakeup.
2
ILT
Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character
do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. Refer to
Section 14.3.3.2.1, “Idle-Line Wakeup” for more information.
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
1
PE
Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most significant
bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit.
0 No hardware parity generation or checking.
1 Parity enabled.
0
PT
Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total
number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in
the data character, including the parity bit, is even.
0 Even parity.
1 Odd parity.
14.2.3
SCI Control Register 2 (SCIC2)
This register can be read or written at any time.
7
6
5
4
3
2
1
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-7. SCI Control Register 2 (SCIC2)
Table 14-4. SCIC2 Field Descriptions
Field
7
TIE
6
TCIE
Description
Transmit Interrupt Enable (for TDRE)
0 Hardware interrupts from TDRE disabled (use polling).
1 Hardware interrupt requested when TDRE flag is 1.
Transmission Complete Interrupt Enable (for TC)
0 Hardware interrupts from TC disabled (use polling).
1 Hardware interrupt requested when TC flag is 1.
5
RIE
Receiver Interrupt Enable (for RDRF)
0 Hardware interrupts from RDRF disabled (use polling).
1 Hardware interrupt requested when RDRF flag is 1.
4
ILIE
Idle Line Interrupt Enable (for IDLE)
0 Hardware interrupts from IDLE disabled (use polling).
1 Hardware interrupt requested when IDLE flag is 1.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
206
Freescale Semiconductor
Serial Communications Interface (S08SCIV4)
Table 14-4. SCIC2 Field Descriptions (continued)
Field
Description
3
TE
Transmitter Enable
0 Transmitter off.
1 Transmitter on.
TE must be 1 in order to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output
for the SCI system.
When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of
traffic on the single SCI communication line (TxD pin).
TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is in progress.
Refer to Section 14.3.2.1, “Send Break and Queued Idle” for more details.
When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued
break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin.
2
RE
Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If
LOOPS = 1 the RxD pin reverts to being a general-purpose I/O pin even if RE = 1.
0 Receiver off.
1 Receiver on.
1
RWU
Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it
waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle
line between messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character
(WAKE = 1, address-mark wakeup). Application software sets RWU and (normally) a selected hardware
condition automatically clears RWU. Refer to Section 14.3.3.2, “Receiver Wakeup Operation” for more details.
0 Normal SCI receiver operation.
1 SCI receiver in standby waiting for wakeup condition.
0
SBK
Send Break — Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional
break characters of 10 or 11 (13 or 14 if BRK13 = 1) bit times of logic 0 are queued as long as SBK = 1.
Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a
second break character may be queued before software clears SBK. Refer to Section 14.3.2.1, “Send Break and
Queued Idle” for more details.
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
14.2.4
SCI Status Register 1 (SCIS1)
This register has eight read-only status flags. Writes have no effect. Special software sequences (which do
not involve writing to this register) are used to clear these status flags.
R
7
6
5
4
3
2
1
0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
1
1
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 14-8. SCI Status Register 1 (SCIS1)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
207
Serial Communications Interface (S08SCIV4)
Table 14-5. SCIS1 Field Descriptions
Field
Description
7
TDRE
Transmit Data Register Empty Flag — TDRE is set out of reset and when a transmit data value transfers from
the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read
SCIS1 with TDRE = 1 and then write to the SCI data register (SCID).
0 Transmit data register (buffer) full.
1 Transmit data register (buffer) empty.
6
TC
Transmission Complete Flag — TC is set out of reset and when TDRE = 1 and no data, preamble, or break
character is being transmitted.
0 Transmitter active (sending data, a preamble, or a break).
1 Transmitter idle (transmission activity complete).
TC is cleared automatically by reading SCIS1 with TC = 1 and then doing one of the following three things:
• Write to the SCI data register (SCID) to transmit new data
• Queue a preamble by changing TE from 0 to 1
• Queue a break character by writing 1 to SBK in SCIC2
5
RDRF
Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into
the receive data register (SCID). To clear RDRF, read SCIS1 with RDRF = 1 and then read the SCI data register
(SCID).
0 Receive data register empty.
1 Receive data register full.
4
IDLE
Idle Line Flag — IDLE is set when the SCI receive line becomes idle for a full character time after a period of
activity. When ILT = 0, the receiver starts counting idle bit times after the start bit. So if the receive character is
all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times
depending on the M control bit) needed for the receiver to detect an idle line. When ILT = 1, the receiver doesn’t
start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at the end of the
previous character do not count toward the full character time of logic high needed for the receiver to detect an
idle line.
To clear IDLE, read SCIS1 with IDLE = 1 and then read the SCI data register (SCID). After IDLE has been
cleared, it cannot become set again until after a new character has been received and RDRF has been set. IDLE
will get set only once even if the receive line remains idle for an extended period.
0 No idle line detected.
1 Idle line was detected.
3
OR
Receiver Overrun Flag — OR is set when a new serial character is ready to be transferred to the receive data
register (buffer), but the previously received character has not been read from SCID yet. In this case, the new
character (and all associated error information) is lost because there is no room to move it into SCID. To clear
OR, read SCIS1 with OR = 1 and then read the SCI data register (SCID).
0 No overrun.
1 Receive overrun (new SCI data lost).
2
NF
Noise Flag — The advanced sampling technique used in the receiver takes seven samples during the start bit
and three samples in each data bit and the stop bit. If any of these samples disagrees with the rest of the samples
within any bit time in the frame, the flag NF will be set at the same time as the flag RDRF gets set for the character.
To clear NF, read SCIS1 and then read the SCI data register (SCID).
0 No noise detected.
1 Noise detected in the received character in SCID.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
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Freescale Semiconductor
Serial Communications Interface (S08SCIV4)
Table 14-5. SCIS1 Field Descriptions (continued)
Field
Description
1
FE
Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop
bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read
SCIS1 with FE = 1 and then read the SCI data register (SCID).
0 No framing error detected. This does not guarantee the framing is correct.
1 Framing error.
0
PF
Parity Error Flag — PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in
the received character does not agree with the expected parity value. To clear PF, read SCIS1 and then read the
SCI data register (SCID).
0 No parity error.
1 Parity error.
14.2.5
SCI Status Register 2 (SCIS2)
This register has one read-only status flag.
7
6
LBKDIF
RXEDGIF
0
0
R
5
4
3
2
1
RXINV
RWUID
BRK13
LBKDE
0
0
0
0
0
0
RAF
W
Reset
0
0
= Unimplemented or Reserved
Figure 14-9. SCI Status Register 2 (SCIS2)
Table 14-6. SCIS2 Field Descriptions
Field
Description
7
LBKDIF
LIN Break Detect Interrupt Flag — LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break
character is detected. LBKDIF is cleared by writing a “1” to it.
0 No LIN break character has been detected.
1 LIN break character has been detected.
6
RXEDGIF
RxD Pin Active Edge Interrupt Flag — RXEDGIF is set when an active edge (falling if RXINV = 0, rising if
RXINV=1) on the RxD pin occurs. RXEDGIF is cleared by writing a “1” to it.
0 No active edge on the receive pin has occurred.
1 An active edge on the receive pin has occurred.
4
RXINV1
Receive Data Inversion — Setting this bit reverses the polarity of the received data input.
0 Receive data not inverted
1 Receive data inverted
3
RWUID
Receive Wake Up Idle Detect— RWUID controls whether the idle character that wakes up the receiver sets the
IDLE bit.
0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
2
BRK13
Break Character Generation Length — BRK13 is used to select a longer transmitted break character length.
Detection of a framing error is not affected by the state of this bit.
0 Break character is transmitted with length of 10 bit times (11 if M = 1)
1 Break character is transmitted with length of 13 bit times (14 if M = 1)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
209
Serial Communications Interface (S08SCIV4)
Table 14-6. SCIS2 Field Descriptions (continued)
1
Field
Description
1
LBKDE
LIN Break Detection Enable— LBKDE is used to select a longer break character detection length. While LBKDE
is set, framing error (FE) and receive data register full (RDRF) flags are prevented from setting.
0 Break character is detected at length of 10 bit times (11 if M = 1).
1 Break character is detected at length of 11 bit times (12 if M = 1).
0
RAF
Receiver Active Flag — RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is
cleared automatically when the receiver detects an idle line. This status flag can be used to check whether an
SCI character is being received before instructing the MCU to go to stop mode.
0 SCI receiver idle waiting for a start bit.
1 SCI receiver active (RxD input not idle).
Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle.
When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold by
one bit time. Under the worst case timing conditions allowed in LIN, it is possible that a 0x00 data
character can appear to be 10.26 bit times long at a slave which is running 14% faster than the master. This
would trigger normal break detection circuitry which is designed to detect a 10 bit break symbol. When
the LBKDE bit is set, framing errors are inhibited and the break detection threshold changes from 10 bits
to 11 bits, preventing false detection of a 0x00 data character as a LIN break symbol.
14.2.6
SCI Control Register 3 (SCIC3)
7
R
6
5
4
3
2
1
0
T8
TXDIR
TXINV
ORIE
NEIE
FEIE
PEIE
0
0
0
0
0
0
0
R8
W
Reset
0
= Unimplemented or Reserved
Figure 14-10. SCI Control Register 3 (SCIC3)
Table 14-7. SCIC3 Field Descriptions
Field
Description
7
R8
Ninth Data Bit for Receiver — When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a ninth
receive data bit to the left of the MSB of the buffered data in the SCID register. When reading 9-bit data, read R8
before reading SCID because reading SCID completes automatic flag clearing sequences which could allow R8
and SCID to be overwritten with new data.
6
T8
Ninth Data Bit for Transmitter — When the SCI is configured for 9-bit data (M = 1), T8 may be thought of as a
ninth transmit data bit to the left of the MSB of the data in the SCID register. When writing 9-bit data, the entire
9-bit value is transferred to the SCI shift register after SCID is written so T8 should be written (if it needs to change
from its previous value) before SCID is written. If T8 does not need to change in the new value (such as when it
is used to generate mark or space parity), it need not be written each time SCID is written.
5
TXDIR
TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation
(LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin.
0 TxD pin is an input in single-wire mode.
1 TxD pin is an output in single-wire mode.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
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Freescale Semiconductor
Serial Communications Interface (S08SCIV4)
Table 14-7. SCIC3 Field Descriptions (continued)
Field
4
TXINV1
1
Description
Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output.
0 Transmit data not inverted
1 Transmit data inverted
3
ORIE
Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests.
0 OR interrupts disabled (use polling).
1 Hardware interrupt requested when OR = 1.
2
NEIE
Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests.
0 NF interrupts disabled (use polling).
1 Hardware interrupt requested when NF = 1.
1
FEIE
Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt
requests.
0 FE interrupts disabled (use polling).
1 Hardware interrupt requested when FE = 1.
0
PEIE
Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt
requests.
0 PF interrupts disabled (use polling).
1 Hardware interrupt requested when PF = 1.
Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.
14.2.7
SCI Data Register (SCID)
This register is actually two separate registers. Reads return the contents of the read-only receive data
buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also
involved in the automatic flag clearing mechanisms for the SCI status flags.
7
6
5
4
3
2
1
0
R
R7
R6
R5
R4
R3
R2
R1
R0
W
T7
T6
T5
T4
T3
T2
T1
T0
0
0
0
0
0
0
0
0
Reset
Figure 14-11. SCI Data Register (SCID)
14.3
Functional Description
The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote
devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block.
The transmitter and receiver operate independently, although they use the same baud rate generator.
During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and
processes received data. The following describes each of the blocks of the SCI.
14.3.1
Baud Rate Generation
As shown in Figure 14-12, the clock source for the SCI baud rate generator is the bus-rate clock.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
211
Serial Communications Interface (S08SCIV4)
MODULO DIVIDE BY
(1 THROUGH 8191)
BUSCLK
SBR12:SBR0
BAUD RATE GENERATOR
OFF IF [SBR12:SBR0] = 0
DIVIDE BY
16
Tx BAUD RATE
Rx SAMPLING CLOCK
(16 BAUD RATE)
BAUD RATE =
BUSCLK
[SBR12:SBR0] 16
Figure 14-12. SCI Baud Rate Generation
SCI communications require the transmitter and receiver (which typically derive baud rates from
independent clock sources) to use the same baud rate. Allowed tolerance on this baud frequency depends
on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is
performed.
The MCU resynchronizes to bit boundaries on every high-to-low transition, but in the worst case, there are
no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is
accumulated for the whole character time. For a Freescale Semiconductor SCI system whose bus
frequency is driven by a crystal, the allowed baud rate mismatch is about ±4.5 percent for 8-bit data format
and about ±4 percent for 9-bit data format. Although baud rate modulo divider settings do not always
produce baud rates that exactly match standard rates, it is normally possible to get within a few percent,
which is acceptable for reliable communications.
14.3.2
Transmitter Functional Description
This section describes the overall block diagram for the SCI transmitter, as well as specialized functions
for sending break and idle characters. The transmitter block diagram is shown in Figure 14-2.
The transmitter output (TxD) idle state defaults to logic high (TXINV = 0 following reset). The transmitter
output is inverted by setting TXINV = 1. The transmitter is enabled by setting the TE bit in SCIC2. This
queues a preamble character that is one full character frame of the idle state. The transmitter then remains
idle until data is available in the transmit data buffer. Programs store data into the transmit data buffer by
writing to the SCI data register (SCID).
The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long
depending on the setting in the M control bit. For the remainder of this section, we will assume M = 0,
selecting the normal 8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits,
and a stop bit. When the transmit shift register is available for a new SCI character, the value waiting in
the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the
transmit data register empty (TDRE) status flag is set to indicate another character may be written to the
transmit data buffer at SCID.
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the
transmitter sets the transmit complete flag and enters an idle mode, with TxD high, waiting for more
characters to transmit.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
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Freescale Semiconductor
Serial Communications Interface (S08SCIV4)
Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity
that is in progress must first be completed. This includes data characters in progress, queued idle
characters, and queued break characters.
14.3.2.1
Send Break and Queued Idle
The SBK control bit in SCIC2 is used to send break characters which were originally used to gain the
attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times
including the start and stop bits). A longer break of 13 bit times can be enabled by setting BRK13 = 1.
Normally, a program would wait for TDRE to become set to indicate the last character of a message has
moved to the transmit shifter, then write 1 and then write 0 to the SBK bit. This action queues a break
character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into
the shifter (synchronized to the baud rate clock), an additional break character is queued. If the receiving
device is another Freescale Semiconductor SCI, the break characters will be received as 0s in all eight data
bits and a framing error (FE = 1) occurs.
When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake
up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last
character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This
action queues an idle character to be sent as soon as the shifter is available. As long as the character in the
shifter does not finish while TE = 0, the SCI transmitter never actually releases control of the TxD pin. If
there is a possibility of the shifter finishing while TE = 0, set the general-purpose I/O controls so the pin
that is shared with TxD is an output driving a logic 1. This ensures that the TxD line will look like a normal
idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE.
The length of the break character is affected by the BRK13 and M bits as shown below.
Table 14-8. Break Character Length
14.3.3
BRK13
M
Break Character Length
0
0
10 bit times
0
1
11 bit times
1
0
13 bit times
1
1
14 bit times
Receiver Functional Description
In this section, the receiver block diagram (Figure 14-3) is used as a guide for the overall receiver
functional description. Next, the data sampling technique used to reconstruct receiver data is described in
more detail. Finally, two variations of the receiver wakeup function are explained.
The receiver input is inverted by setting RXINV = 1. The receiver is enabled by setting the RE bit in
SCIC2. Character frames consist of a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop bit
of logic 1. For information about 9-bit data mode, refer to Section 14.3.5.1, “8- and 9-Bit Data Modes.”
For the remainder of this discussion, we assume the SCI is configured for normal 8-bit data mode.
After receiving the stop bit into the receive shifter, and provided the receive data register is not already
full, the data character is transferred to the receive data register and the receive data register full (RDRF)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
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Serial Communications Interface (S08SCIV4)
status flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the
overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the
program has one full character time after RDRF is set before the data in the receive data buffer must be
read to avoid a receiver overrun.
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive
data register by reading SCID. The RDRF flag is cleared automatically by a 2-step sequence which is
normally satisfied in the course of the user’s program that handles receive data. Refer to Section 14.3.4,
“Interrupts and Status Flags” for more details about flag clearing.
14.3.3.1
Data Sampling Technique
The SCI receiver uses a 16 baud rate clock for sampling. The receiver starts by taking logic level samples
at 16 times the baud rate to search for a falling edge on the RxD serial data input pin. A falling edge is
defined as a logic 0 sample after three consecutive logic 1 samples. The 16 baud rate clock is used to
divide the bit time into 16 segments labeled RT1 through RT16. When a falling edge is located, three more
samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at
least two of these three samples are 0, the receiver assumes it is synchronized to a receive character.
The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to
determine the logic level for that bit. The logic level is interpreted to be that of the majority of the samples
taken during the bit time. In the case of the start bit, the bit is assumed to be 0 if at least two of the samples
at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s. If any
sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic
level for that bit, the noise flag (NF) will be set when the received character is transferred to the receive
data buffer.
The falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample
clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise
or mismatched baud rates. It does not improve worst case analysis because some characters do not have
any extra falling edges anywhere in the character frame.
In the case of a framing error, provided the received character was not a break character, the sampling logic
that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected
almost immediately.
In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing
error flag is cleared. The receive shift register continues to function, but a complete character cannot
transfer to the receive data buffer if FE is still set.
14.3.3.2
Receiver Wakeup Operation
Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the characters in a
message that is intended for a different SCI receiver. In such a system, all receivers evaluate the first
character(s) of each message, and as soon as they determine the message is intended for a different
receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIC2. When RWU bit is set, the
status flags associated with the receiver (with the exception of the idle bit, IDLE, when RWUID bit is set)
are inhibited from setting, thus eliminating the software overhead for handling the unimportant message
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Serial Communications Interface (S08SCIV4)
characters. At the end of a message, or at the beginning of the next message, all receivers automatically
force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next message.
14.3.3.2.1
Idle-Line Wakeup
When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared
automatically when the receiver detects a full character time of the idle-line level. The M control bit selects
8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character
time (10 or 11 bit times because of the start and stop bits).
When RWU is one and RWUID is zero, the idle condition that wakes up the receiver does not set the IDLE
flag. The receiver wakes up and waits for the first data character of the next message which will set the
RDRF flag and generate an interrupt if enabled. When RWUID is one, any idle condition sets the IDLE
flag and generates an interrupt if enabled, regardless of whether RWU is zero or one.
The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle
bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward
the full character time of idle. When ILT = 1, the idle bit counter does not start until after a stop bit time,
so the idle detection is not affected by the data in the last character of the previous message.
14.3.3.2.2
Address-Mark Wakeup
When WAKE = 1, the receiver is configured for address-mark wakeup. In this mode, RWU is cleared
automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth
bit in M = 0 mode and ninth bit in M = 1 mode).
Address-mark wakeup allows messages to contain idle characters but requires that the MSB be reserved
for use in address frames. The logic 1 MSB of an address frame clears the RWU bit before the stop bit is
received and sets the RDRF flag. In this case the character with the MSB set is received even though the
receiver was sleeping during most of this character time.
14.3.4
Interrupts and Status Flags
The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the
cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events.
Another interrupt vector is associated with the receiver for RDRF, IDLE, RXEDGIF and LBKDIF events,
and a third vector is used for OR, NF, FE, and PF error conditions. Each of these ten interrupt sources can
be separately masked by local interrupt enable masks. The flags can still be polled by software when the
local masks are cleared to disable generation of hardware interrupt requests.
The SCI transmitter has two status flags that optionally can generate hardware interrupt requests. Transmit
data register empty (TDRE) indicates when there is room in the transmit data buffer to write another
transmit character to SCID. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be
requested whenever TDRE = 1. Transmit complete (TC) indicates that the transmitter is finished
transmitting all data, preamble, and break characters and is idle with TxD at the inactive level. This flag is
often used in systems with modems to determine when it is safe to turn off the modem. If the transmit
complete interrupt enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1.
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Serial Communications Interface (S08SCIV4)
Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status flags if
the corresponding TIE or TCIE local interrupt masks are 0s.
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive
data register by reading SCID. The RDRF flag is cleared by reading SCIS1 while RDRF = 1 and then
reading SCID.
When polling is used, this sequence is naturally satisfied in the normal course of the user program. If
hardware interrupts are used, SCIS1 must be read in the interrupt service routine (ISR). Normally, this is
done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied.
The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD line remains
idle for an extended period of time. IDLE is cleared by reading SCIS1 while IDLE = 1 and then reading
SCID. After IDLE has been cleared, it cannot become set again until the receiver has received at least one
new character and has set RDRF.
If the associated error was detected in the received character that caused RDRF to be set, the error flags
— noise flag (NF), framing error (FE), and parity error flag (PF) — get set at the same time as RDRF.
These flags are not set in overrun cases.
If RDRF was already set when a new character is ready to be transferred from the receive shifter to the
receive data buffer, the overrun (OR) flag gets set instead the data along with any associated NF, FE, or PF
condition is lost.
At any time, an active edge on the RxD serial data input pin causes the RXEDGIF flag to set. The
RXEDGIF flag is cleared by writing a “1” to it. This function does depend on the receiver being enabled
(RE = 1).
14.3.5
Additional SCI Functions
The following sections describe additional SCI functions.
14.3.5.1
8- and 9-Bit Data Modes
The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the
M control bit in SCIC1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data
register. For the transmit data buffer, this bit is stored in T8 in SCIC3. For the receiver, the ninth bit is held
in R8 in SCIC3.
For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCID.
If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character,
it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the
transmit shifter, the value in T8 is copied at the same time data is transferred from SCID to the shifter.
9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the
ninth bit. Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In
custom protocols, the ninth bit can also serve as a software-controlled marker.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
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14.3.5.2
Stop Mode Operation
During all stop modes, clocks to the SCI module are halted.
In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these
two stop modes. No SCI module registers are affected in stop3 mode.
The receive input active edge detect circuit is still active in stop3 mode, but not in stop2. . An active edge
on the receive input brings the CPU out of stop3 mode if the interrupt is not masked (RXEDGIE = 1).
Note, because the clocks are halted, the SCI module will resume operation upon exit from stop (only in
stop3 mode). Software should ensure stop mode is not entered while there is a character being transmitted
out of or received into the SCI module.
14.3.5.3
Loop Mode
When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or
single-wire mode (RSRC = 1). Loop mode is sometimes used to check software, independent of
connections in the external system, to help isolate system problems. In this mode, the transmitter output is
internally connected to the receiver input and the RxD pin is not used by the SCI, so it reverts to a
general-purpose port I/O pin.
14.3.5.4
Single-Wire Operation
When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or
single-wire mode (RSRC = 1). Single-wire mode is used to implement a half-duplex serial connection.
The receiver is internally connected to the transmitter output and to the TxD pin. The RxD pin is not used
and reverts to a general-purpose port I/O pin.
In single-wire mode, the TXDIR bit in SCIC3 controls the direction of serial data on the TxD pin. When
TXDIR = 0, the TxD pin is an input to the SCI receiver and the transmitter is temporarily disconnected
from the TxD pin so an external device can send serial data to the receiver. When TXDIR = 1, the TxD pin
is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the
transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
217
Serial Communications Interface (S08SCIV4)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
218
Freescale Semiconductor
Chapter 15
Serial Peripheral Interface (S08SPIV3)
15.1
Introduction
The serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial communication
between the MCU and peripheral devices. These peripheral devices can include other microcontrollers,
analog-to-digital converters, shift registers, sensors, memories, etc.
The SPI runs at a baud rate up to the bus clock divided by two. Software can poll the status flags, or SPI
operation can be interrupt driven.
Figure 15-1 shows the MC9S08SG8 block diagram with the SPI module highlighted.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
219
Chapter 15 Serial Peripheral Interface (S08SPIV3)
HCS08 CORE
DEBUG MODULE (DBG)
BKGD/MS
8-BIT MODULO TIMER
MODULE (MTIM)
HCS08 SYSTEM CONTROL
SCL
LVD
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER FLASH
(MC9S08SG8 = 8,192 BYTES)
(MC9S08SG4 = 4096 BYTES)
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI)
USER RAM
(MC9S08SG8 = 512 BYTES)
(MC9S08SG4 = 256 BYTES)
16-BIT TIMER/PWM
MODULE (TPM1)
REAL-TIME COUNTER (RTC)
16-BIT TIMER/PWM
MODULE (TPM2)
40-MHz INTERNAL CLOCK
SOURCE (ICS)
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
VOLTAGE
REGULATOR
VSS
VDDA
VSSA
VREFH
VREFL
SS
MISO
MOSI
SPSCK
PTA3/PAI3/SCL/ADP3
PTA1/PIA1/TPM2CH0/ADP1/ACMP–
PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+
SEE NOTE 1, 2
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
TCLK
TPM1CH0
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
PTB3/PIB3/MOSI/ADP7
PTB2/PIB2/SPSCK/ADP6
TPM1CH1
PTB1/PIB1/TxD/ADP5
PTB0/PIB0/RxD/ADP4
TCLK
TPM2CH0
TPM2CH1
XTAL
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
PTA2/PAI2/SDA/ADP2/ACMPO
RxD
TxD
SEE NOTE 1, 2
EXTAL
ANALOG COMPARATOR
(ACMP)
SEE NOTE 3
VDD
SDA
PORT A
IIC MODULE (IIC)
PORT B
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
COP
TCLK
ACMPO
ACMP–
ACMP+
PORT C
BDC
CPU
RESET
PTC3/ADP11
PTC2/ADP10
PTC1/TPM1CH1/ADP9
PTC0/TPM1CH0/ADP8
ADP11-ADP0
NOTES
= Pin can be enabled as part of the ganged output drive feature.
NOTE 1: Port B not available on 8-pin packages
NOTE 2: Port C not available on 8-pin or 16-pin packages.
NOTE 3: VDDA/VREFH and VSSA/VREFL, are double bonded to VDD and VSS respectively.
Figure 15-1. MC9S08SG8 Block Diagram with SPI Module Highlighted
MC9S08SG8 MCU Series Data Sheet, Rev. 8
220
Freescale Semiconductor
Serial Peripheral Interface (S08SPIV3)
15.1.1
Features
Features of the SPI module include:
• Master or slave mode operation
• Full-duplex or single-wire bidirectional option
• Programmable transmit bit rate
• Double-buffered transmit and receive
• Serial clock phase and polarity options
• Slave select output
• Selectable MSB-first or LSB-first shifting
15.1.2
Block Diagrams
This section includes block diagrams showing SPI system connections, the internal organization of the SPI
module, and the SPI clock dividers that control the master mode bit rate.
15.1.2.1
SPI System Block Diagram
Figure 15-2 shows the SPI modules of two MCUs connected in a master-slave arrangement. The master
device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the
slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively
exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock
output from the master and an input to the slave. The slave device must be selected by a low level on the
slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave
select output.
SLAVE
MASTER
MOSI
MOSI
SPI SHIFTER
7
6
5
4
3
2
SPI SHIFTER
1
0
MISO
SPSCK
CLOCK
GENERATOR
SS
MISO
7
6
5
4
3
2
1
0
SPSCK
SS
Figure 15-2. SPI System Connections
MC9S08SG8 MCU Series Data Sheet, Rev.8
Freescale Semiconductor
221
Serial Peripheral Interface (S08SPIV3)
The most common uses of the SPI system include connecting simple shift registers for adding input or
output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although
Figure 15-2 shows a system where data is exchanged between two MCUs, many practical systems involve
simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a
slave to the master MCU.
15.1.2.2
SPI Module Block Diagram
Figure 15-3 is a block diagram of the SPI module. The central element of the SPI is the SPI shift register.
Data is written to the double-buffered transmitter (write to SPID) and gets transferred to the SPI shift
register at the start of a data transfer. After shifting in a byte of data, the data is transferred into the
double-buffered receiver where it can be read (read from SPID). Pin multiplexing logic controls
connections between MCU pins and the SPI module.
When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the shifter output is
routed to MOSI, and the shifter input is routed from the MISO pin.
When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter
output is routed to MISO, and the shifter input is routed from the MOSI pin.
In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all
MOSI pins together. Peripheral devices often use slightly different names for these pins.
MC9S08SG8 MCU Series Data Sheet, Rev.8
222
Freescale Semiconductor
Serial Peripheral Interface (S08SPIV3)
PIN CONTROL
M
SPE
MOSI
(MOMI)
S
Tx BUFFER (WRITE SPID)
ENABLE
SPI SYSTEM
M
SHIFT
OUT
SPI SHIFT REGISTER
SHIFT
IN
MISO
(SISO)
S
SPC0
Rx BUFFER (READ SPID)
BIDIROE
SHIFT
DIRECTION
LSBFE
SHIFT
CLOCK
Rx BUFFER
FULL
Tx BUFFER
EMPTY
MASTER CLOCK
BUS RATE
CLOCK
SPIBR
CLOCK GENERATOR
MSTR
CLOCK
LOGIC
SLAVE CLOCK
MASTER/SLAVE
M
SPSCK
S
MASTER/
SLAVE
MODE SELECT
MODFEN
SSOE
MODE FAULT
DETECTION
SPRF
SS
SPTEF
SPTIE
MODF
SPIE
SPI
INTERRUPT
REQUEST
Figure 15-3. SPI Module Block Diagram
15.1.3
SPI Baud Rate Generation
As shown in Figure 15-4, the clock source for the SPI baud rate generator is the bus clock. The three
prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate
select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256
to get the internal SPI master mode bit-rate clock.
MC9S08SG8 MCU Series Data Sheet, Rev.8
Freescale Semiconductor
223
Serial Peripheral Interface (S08SPIV3)
BUS CLOCK
PRESCALER
CLOCK RATE DIVIDER
DIVIDE BY
1, 2, 3, 4, 5, 6, 7, or 8
DIVIDE BY
2, 4, 8, 16, 32, 64, 128, or 256
SPPR2:SPPR1:SPPR0
SPR2:SPR1:SPR0
MASTER
SPI
BIT RATE
Figure 15-4. SPI Baud Rate Generation
15.2
External Signal Description
The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control
bits. When the SPI is disabled (SPE = 0), these four pins revert to being general-purpose port I/O pins that
are not controlled by the SPI.
15.2.1
SPSCK — SPI Serial Clock
When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master,
this pin is the serial clock output.
15.2.2
MOSI — Master Data Out, Slave Data In
When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this
pin is the serial data output. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data
input. If SPC0 = 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes
the bidirectional data I/O pin (MOMI). Also, the bidirectional mode output enable bit determines whether
the pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and slave mode is
selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin.
15.2.3
MISO — Master Data In, Slave Data Out
When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this
pin is the serial data input. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data
output. If SPC0 = 1 to select single-wire bidirectional mode, and slave mode is selected, this pin becomes
the bidirectional data I/O pin (SISO) and the bidirectional mode output enable bit determines whether the
pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and master mode is selected,
this pin is not used by the SPI and reverts to being a general-purpose port I/O pin.
15.2.4
SS — Slave Select
When the SPI is enabled as a slave, this pin is the low-true slave select input. When the SPI is enabled as
a master and mode fault enable is off (MODFEN = 0), this pin is not used by the SPI and reverts to being
a general-purpose port I/O pin. When the SPI is enabled as a master and MODFEN = 1, the slave select
output enable bit determines whether this pin acts as the mode fault input (SSOE = 0) or as the slave select
output (SSOE = 1).
MC9S08SG8 MCU Series Data Sheet, Rev.8
224
Freescale Semiconductor
Serial Peripheral Interface (S08SPIV3)
15.3
Modes of Operation
15.3.1
SPI in Stop Modes
The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction.
During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1
or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are
halted. No registers are affected. If stop3 is exited with a reset, the SPI will be put into its reset state. If
stop3 is exited with an interrupt, the SPI continues from the state it was in when stop3 was entered.
15.4
Register Definition
The SPI has five 8-bit registers to select SPI options, control baud rate, report SPI status, and for
transmit/receive data.
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all SPI registers. This section refers to registers and control bits only by their names, and
a Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
15.4.1
SPI Control Register 1 (SPIC1)
This read/write register includes the SPI enable control, interrupt enables, and configuration options.
7
6
5
4
3
2
1
0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0
0
0
0
0
1
0
0
R
W
Reset
Figure 15-5. SPI Control Register 1 (SPIC1)
Table 15-1. SPIC1 Field Descriptions
Field
Description
7
SPIE
SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF)
and mode fault (MODF) events.
0 Interrupts from SPRF and MODF inhibited (use polling)
1 When SPRF or MODF is 1, request a hardware interrupt
6
SPE
SPI System Enable — Disabling the SPI halts any transfer that is in progress, clears data buffers, and initializes
internal state machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty.
0 SPI system inactive
1 SPI system enabled
5
SPTIE
SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF).
0 Interrupts from SPTEF inhibited (use polling)
1 When SPTEF is 1, hardware interrupt requested
MC9S08SG8 MCU Series Data Sheet, Rev.8
Freescale Semiconductor
225
Serial Peripheral Interface (S08SPIV3)
Table 15-1. SPIC1 Field Descriptions (continued)
Field
Description
4
MSTR
Master/Slave Mode Select
0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device
3
CPOL
Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a
slave SPI device. Refer to Section 15.5.1, “SPI Clock Formats” for more details.
0 Active-high SPI clock (idles low)
1 Active-low SPI clock (idles high)
2
CPHA
Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral
devices. Refer to Section 15.5.1, “SPI Clock Formats” for more details.
0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer
1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer
1
SSOE
Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in
SPCR2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in Table 15-2.
0
LSBFE
LSB First (Shifter Direction)
0 SPI serial data transfers start with most significant bit
1 SPI serial data transfers start with least significant bit
Table 15-2. SS Pin Function
MODFEN
SSOE
Master Mode
Slave Mode
0
0
General-purpose I/O (not SPI)
Slave select input
0
1
General-purpose I/O (not SPI)
Slave select input
1
0
SS input for mode fault
Slave select input
1
1
Automatic SS output
Slave select input
NOTE
Ensure that the SPI should not be disabled (SPE=0) at the same time as a bit change to the CPHA bit. These
changes should be performed as separate operations or unexpected behavior may occur.
15.4.2
SPI Control Register 2 (SPIC2)
This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not
implemented and always read 0.
R
7
6
5
0
0
0
4
3
MODFEN
BIDIROE
0
0
2
1
0
SPISWAI
SPC0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 15-6. SPI Control Register 2 (SPIC2)
MC9S08SG8 MCU Series Data Sheet, Rev.8
226
Freescale Semiconductor
Serial Peripheral Interface (S08SPIV3)
Table 15-3. SPIC2 Register Field Descriptions
Field
Description
4
MODFEN
Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or
effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to
Table 15-2 for more details).
0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
3
BIDIROE
Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1,
BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin.
Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO
(SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect.
0 Output driver disabled so SPI data I/O pin acts as an input
1 SPI I/O pin enabled as an output
1
SPISWAI
SPI Stop in Wait Mode
0 SPI clocks continue to operate in wait mode
1 SPI clocks stop when the MCU enters wait mode
0
SPC0
15.4.3
SPI Pin Control 0 — The SPC0 bit chooses single-wire bidirectional mode. If MSTR = 0 (slave mode), the SPI
uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR = 1 (master mode), the SPI uses the MOSI
(MOMI) pin for bidirectional SPI data transfers. When SPC0 = 1, BIDIROE is used to enable or disable the output
driver for the single bidirectional SPI I/O pin.
0 SPI uses separate pins for data input and data output
1 SPI configured for single-wire bidirectional operation
SPI Baud Rate Register (SPIBR)
This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
7
R
6
5
4
3
SPPR2
SPPR1
SPPR0
0
0
0
0
2
1
0
SPR2
SPR1
SPR0
0
0
0
0
W
Reset
0
0
= Unimplemented or Reserved
Figure 15-7. SPI Baud Rate Register (SPIBR)
Table 15-4. SPIBR Register Field Descriptions
Field
Description
6:4
SPPR[2:0]
SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler
as shown in Table 15-5. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler
drives the input of the SPI baud rate divider (see Figure 15-4).
2:0
SPR[2:0]
SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in
Table 15-6. The input to this divider comes from the SPI baud rate prescaler (see Figure 15-4). The output of this
divider is the SPI bit rate clock for master mode.
MC9S08SG8 MCU Series Data Sheet, Rev.8
Freescale Semiconductor
227
Serial Peripheral Interface (S08SPIV3)
Table 15-5. SPI Baud Rate Prescaler Divisor
SPPR2:SPPR1:SPPR0
Prescaler Divisor
0:0:0
1
0:0:1
2
0:1:0
3
0:1:1
4
1:0:0
5
1:0:1
6
1:1:0
7
1:1:1
8
Table 15-6. SPI Baud Rate Divisor
15.4.4
SPR2:SPR1:SPR0
Rate Divisor
0:0:0
2
0:0:1
4
0:1:0
8
0:1:1
16
1:0:0
32
1:0:1
64
1:1:0
128
1:1:1
256
SPI Status Register (SPIS)
This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0.
Writes have no meaning or effect.
R
7
6
5
4
3
2
1
0
SPRF
0
SPTEF
MODF
0
0
0
0
0
0
1
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 15-8. SPI Status Register (SPIS)
MC9S08SG8 MCU Series Data Sheet, Rev.8
228
Freescale Semiconductor
Serial Peripheral Interface (S08SPIV3)
Table 15-7. SPIS Register Field Descriptions
Field
Description
7
SPRF
SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may
be read from the SPI data register (SPID). SPRF is cleared by reading SPRF while it is set, then reading the SPI
data register.
0 No data available in the receive data buffer
1 Data available in the receive data buffer
5
SPTEF
SPI Transmit Buffer Empty Flag — This bit is set when there is room in the transmit data buffer. It is cleared by
reading SPIS with SPTEF set, followed by writing a data value to the transmit buffer at SPID. SPIS must be read
with SPTEF = 1 before writing data to SPID or the SPID write will be ignored. SPTEF generates an SPTEF CPU
interrupt request if the SPTIE bit in the SPIC1 is also set. SPTEF is automatically set when a data byte transfers
from the transmit buffer into the transmit shift register. For an idle SPI (no data in the transmit buffer or the shift
register and no transfer in progress), data written to SPID is transferred to the shifter almost immediately so
SPTEF is set within two bus cycles allowing a second 8-bit data value to be queued into the transmit buffer. After
completion of the transfer of the value in the shift register, the queued value from the transmit buffer will
automatically move to the shifter and SPTEF will be set to indicate there is room for new data in the transmit
buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set and no data moves from the
buffer to the shifter.
0 SPI transmit buffer not empty
1 SPI transmit buffer empty
4
MODF
Master Mode Fault Flag — MODF is set if the SPI is configured as a master and the slave select input goes low,
indicating some other SPI device is also configured as a master. The SS pin acts as a mode fault error input only
when MSTR = 1, MODFEN = 1, and SSOE = 0; otherwise, MODF will never be set. MODF is cleared by reading
MODF while it is 1, then writing to SPI control register 1 (SPIC1).
0 No mode fault error
1 Mode fault error detected
15.4.5
SPI Data Register (SPID)
7
6
5
4
3
2
1
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 15-9. SPI Data Register (SPID)
Reads of this register return the data read from the receive data buffer. Writes to this register write data to
the transmit data buffer. When the SPI is configured as a master, writing data to the transmit data buffer
initiates an SPI transfer.
Data should not be written to the transmit data buffer unless the SPI transmit buffer empty flag (SPTEF)
is set, indicating there is room in the transmit buffer to queue a new transmit byte.
Data may be read from SPID any time after SPRF is set and before another transfer is finished. Failure to
read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition
and the data from the new transfer is lost.
MC9S08SG8 MCU Series Data Sheet, Rev.8
Freescale Semiconductor
229
Serial Peripheral Interface (S08SPIV3)
15.5
Functional Description
An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then
writing a byte of data to the SPI data register (SPID) in the master SPI device. When the SPI shift register
is available, this byte of data is moved from the transmit data buffer to the shifter, SPTEF is set to indicate
there is room in the buffer to queue another transmit character if desired, and the SPI serial transfer starts.
During the SPI transfer, data is sampled (read) on the MISO pin at one SPSCK edge and shifted, changing
the bit value on the MOSI pin, one-half SPSCK cycle later. After eight SPSCK cycles, the data that was
in the shift register of the master has been shifted out the MOSI pin to the slave while eight bits of data
were shifted in the MISO pin into the master’s shift register. At the end of this transfer, the received data
byte is moved from the shifter into the receive data buffer and SPRF is set to indicate the data can be read
by reading SPID. If another byte of data is waiting in the transmit buffer at the end of a transfer, it is moved
into the shifter, SPTEF is set, and a new transfer is started.
Normally, SPI data is transferred most significant bit (MSB) first. If the least significant bit first enable
(LSBFE) bit is set, SPI data is shifted LSB first.
When the SPI is configured as a slave, its SS pin must be driven low before a transfer starts and SS must
stay low throughout the transfer. If a clock format where CPHA = 0 is selected, SS must be driven to a
logic 1 between successive transfers. If CPHA = 1, SS may remain low between successive transfers. See
Section 15.5.1, “SPI Clock Formats” for more details.
Because the transmitter and receiver are double buffered, a second byte, in addition to the byte currently
being shifted out, can be queued into the transmit data buffer, and a previously received character can be
in the receive data buffer while a new character is being shifted in. The SPTEF flag indicates when the
transmit buffer has room for a new character. The SPRF flag indicates when a received character is
available in the receive data buffer. The received character must be read out of the receive buffer (read
SPID) before the next transfer is finished or a receive overrun error results.
In the case of a receive overrun, the new data is lost because the receive buffer still held the previous
character and was not ready to accept the new data. There is no indication for such an overrun condition
so the application system designer must ensure that previous data has been read from the receive buffer
before a new transfer is initiated.
15.5.1
SPI Clock Formats
To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI
system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock
formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses
between two different clock phase relationships between the clock and data.
Figure 15-10 shows the clock formats when CPHA = 1. At the top of the figure, the eight bit times are
shown for reference with bit 1 starting at the first SPSCK edge and bit 8 ending one-half SPSCK cycle
after the sixteenth SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits
depending on the setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these
waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform
applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the
MC9S08SG8 MCU Series Data Sheet, Rev.8
230
Freescale Semiconductor
Serial Peripheral Interface (S08SPIV3)
MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS
OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The
master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back
high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input
of a slave.
BIT TIME #
(REFERENCE)
1
2
...
6
7
8
BIT 7
BIT 0
BIT 6
BIT 1
...
...
BIT 2
BIT 5
BIT 1
BIT 6
BIT 0
BIT 7
SPSCK
(CPOL = 0)
SPSCK
(CPOL = 1)
SAMPLE IN
(MISO OR MOSI)
MOSI
(MASTER OUT)
MSB FIRST
LSB FIRST
MISO
(SLAVE OUT)
SS OUT
(MASTER)
SS IN
(SLAVE)
Figure 15-10. SPI Clock Formats (CPHA = 1)
When CPHA = 1, the slave begins to drive its MISO output when SS goes to active low, but the data is not
defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto
the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the
master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the
third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled,
and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the
master and slave, respectively. When CHPA = 1, the slave’s SS input is not required to go to its inactive
high level between transfers.
Figure 15-11 shows the clock formats when CPHA = 0. At the top of the figure, the eight bit times are
shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last
SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting
MC9S08SG8 MCU Series Data Sheet, Rev.8
Freescale Semiconductor
231
Serial Peripheral Interface (S08SPIV3)
in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a
specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input
of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a
master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies
to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes
to active low at the start of the first bit time of the transfer and goes back high one-half SPSCK cycle after
the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a
slave.
BIT TIME #
(REFERENCE)
1
2
BIT 7
BIT 0
BIT 6
BIT 1
...
6
7
8
BIT 2
BIT 5
BIT 1
BIT 6
BIT 0
BIT 7
SPSCK
(CPOL = 0)
SPSCK
(CPOL = 1)
SAMPLE IN
(MISO OR MOSI)
MOSI
(MASTER OUT)
MSB FIRST
LSB FIRST
...
...
MISO
(SLAVE OUT)
SS OUT
(MASTER)
SS IN
(SLAVE)
Figure 15-11. SPI Clock Formats (CPHA = 0)
When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB
depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the
slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK
edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the
second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and
slave, respectively. When CPHA = 0, the slave’s SS input must go to its inactive high level between
transfers.
MC9S08SG8 MCU Series Data Sheet, Rev.8
232
Freescale Semiconductor
Serial Peripheral Interface (S08SPIV3)
15.5.2
SPI Interrupts
There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system.
The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode
fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI
transmit buffer empty flag (SPTEF). When one of the flag bits is set, and the associated interrupt mask bit
is set, a hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared, software can
poll the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) should
check the flag bits to determine what event caused the interrupt. The service routine should also clear the
flag bit(s) before returning from the ISR (usually near the beginning of the ISR).
15.5.3
Mode Fault Detection
A mode fault occurs and the mode fault flag (MODF) becomes set when a master SPI device detects an
error on the SS pin (provided the SS pin is configured as the mode fault input signal). The SS pin is
configured to be the mode fault input signal when MSTR = 1, mode fault enable is set (MODFEN = 1),
and slave select output enable is clear (SSOE = 0).
The mode fault detection feature can be used in a system where more than one SPI device might become
a master at the same time. The error is detected when a master’s SS pin is low, indicating that some other
SPI device is trying to address this master as if it were a slave. This could indicate a harmful output driver
conflict, so the mode fault logic is designed to disable all SPI output drivers when such an error is detected.
When a mode fault is detected, MODF is set and MSTR is cleared to change the SPI configuration back
to slave mode. The output drivers on the SPSCK, MOSI, and MISO (if not bidirectional mode) are
disabled.
MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPIC1). User
software should verify the error condition has been corrected before changing the SPI back to master
mode.
MC9S08SG8 MCU Series Data Sheet, Rev.8
Freescale Semiconductor
233
Serial Peripheral Interface (S08SPIV3)
MC9S08SG8 MCU Series Data Sheet, Rev.8
234
Freescale Semiconductor
Chapter 16
Timer Pulse-Width Modulator (S08TPMV3)
16.1
Introduction
The TPM uses one input/output (I/O) pin per channel, TPMxCHn where x is the TPM number (for
example, 1 or 2) and n is the channel number (for example, 0–1). The TPM shares its I/O pins with
general-purpose I/O port pins (refer to the Pins and Connections chapter for more information).
All MC9S08SG8 MCUs have two TPM modules. The number of channels available depends on the pin
quantity of the package, as shown in Table 16-1:
Table 16-1. MC9S08SG8 Features by MCU and Package
Feature
1
MC9S08SG8/4
Pin quantity
20
16
8
TPM1 channels
2
2
11
TPM2 channels
2
2
11
The 8-pin device does not have TPM1CH1 or TPM2CH1
bonded out, but those timer channels are available to the
user to use as software compares.
Figure 16-1 shows the MC9S08SG8 block diagram with the TPM modules highlighted.
16.1.1
ACMP/TPM Configuration Information
The ACMP module can be configured to connect the output of the analog comparator to TPM1 input
capture channel 0 by setting ACIC in SOPT2. With ACIC set, the TPM1CH0 pin is not available externally
regardless of the configuration of the TPM1 module for channel 0.
16.1.2
TPM Configuration Information
The external clock for the TPM modules, TPMCLK, is selected by setting CLKS[B:A] = 1:1 in TPMxSC,
which selects the TCLK pin input. The TCLK input on PTA5 can be enabled as external clock inputs to
both TPM modules and MTIM simultaneously.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
235
Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)
HCS08 CORE
DEBUG MODULE (DBG)
BKGD/MS
8-BIT MODULO TIMER
MODULE (MTIM)
HCS08 SYSTEM CONTROL
SCL
IIC MODULE (IIC)
LVD
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER FLASH
(MC9S08SG8 = 8,192 BYTES)
(MC9S08SG4 = 4096 BYTES)
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI)
USER RAM
(MC9S08SG8 = 512 BYTES)
(MC9S08SG4 = 256 BYTES)
16-BIT TIMER/PWM
MODULE (TPM1)
REAL-TIME COUNTER (RTC)
16-BIT TIMER/PWM
MODULE (TPM2)
40-MHz INTERNAL CLOCK
SOURCE (ICS)
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
VOLTAGE
REGULATOR
VSS
VDDA
VSSA
VREFH
VREFL
SS
MISO
MOSI
SPSCK
PTA3/PAI3/SCL/ADP3
PTA1/PIA1/TPM2CH0/ADP1/ACMP–
PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+
SEE NOTE 1, 2
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
TCLK
TPM1CH0
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
PTB3/PIB3/MOSI/ADP7
PTB2/PIB2/SPSCK/ADP6
TPM1CH1
PTB1/PIB1/TxD/ADP5
PTB0/PIB0/RxD/ADP4
TCLK
TPM2CH0
TPM2CH1
XTAL
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
PTA2/PAI2/SDA/ADP2/ACMPO
RxD
TxD
SEE NOTE 1, 2
EXTAL
ANALOG COMPARATOR
(ACMP)
SEE NOTE 3
VDD
SDA
PORT A
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
COP
TCLK
PORT B
BDC
ACMPO
ACMP–
ACMP+
PORT C
CPU
RESET
PTC3/ADP11
PTC2/ADP10
PTC1/TPM1CH1/ADP9
PTC0/TPM1CH0/ADP8
ADP11-ADP0
NOTES
= Pin can be enabled as part of the ganged output drive feature.
NOTE 1: Port B not available on 8-pin packages
NOTE 2: Port C not available on 8-pin or 16-pin packages.
NOTE 3: VDDA/VREFH and VSSA/VREFL, are double bonded to VDD and VSS respectively.
Figure 16-1. MC9S08SG8 Block Diagram with TPM Modules Highlighted
16.1.3
TPMV3 Differences from Previous Versions
The TPMV3 is the latest version of the Timer/PWM module that addresses errata found in previous
versions. The following section outlines the differences between TPMV3 and TPMV2 modules, and any
considerations that should be taken when porting code.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
236
Freescale Semiconductor
Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)
Table 16-2. TPMV2 and TPMV3 Porting Considerations
Action
TPMV3
TPMV2
Write to TPMxCnTH:L registers1
Any write to TPMxCNTH or TPMxCNTL registers
Clears the TPM counter
(TPMxCNTH:L) and the
prescaler counter.
Clears the TPM counter
(TPMxCNTH:L) only.
Read of TPMxCNTH:L registers1
In BDM mode, any read of TPMxCNTH:L registers
Returns the value of the TPM If only one byte of the
counter that is frozen.
TPMxCNTH:L registers was
read before the BDM mode
became active, returns the
latched value of TPMxCNTH:L
from the read buffer (instead of
the frozen TPM counter value).
In BDM mode, a write to TPMxSC, TPMxCNTH or TPMxCNTL Clears this read coherency
mechanism.
Does not clear this read
coherency mechanism.
Read of TPMxCnVH:L registers2
In BDM mode, any read of TPMxCnVH:L registers
Returns the value of the
TPMxCnVH:L register.
If only one byte of the
TPMxCnVH:L registers was
read before the BDM mode
became active, returns the
latched value of TPMxCNTH:L
from the read buffer (instead of
the value in the TPMxCnVH:L
registers).
In BDM mode, a write to TPMxCnSC
Clears this read coherency
mechanism.
Does not clear this read
coherency mechanism.
In Input Capture mode, writes to TPMxCnVH:L registers3
Not allowed.
Allowed.
In Output Compare mode, when (CLKSB:CLKSA not = 0:0),
writes to TPMxCnVH:L registers3
Update the TPMxCnVH:L
registers with the value of
their write buffer at the next
change of the TPM counter
(end of the prescaler
counting) after the second
byte is written.
Always update these registers
when their second byte is
written.
Write to TPMxCnVH:L registers
In Edge-Aligned PWM mode when (CLKSB:CLKSA not = 00), Update the TPMxCnVH:L
writes to TPMxCnVH:L registers
registers with the value of
their write buffer after both
bytes were written and when
the TPM counter changes
from (TPMxMODH:L - 1) to
(TPMxMODH:L).
Note: If the TPM counter is a
free-running counter, then
this update is made when the
TPM counter changes from
0xFFFE to 0xFFFF.
Update after both bytes are
written and when the TPM
counter changes from
TPMxMODH:L to 0x0000.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
237
Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)
Table 16-2. TPMV2 and TPMV3 Porting Considerations (continued)
Action
TPMV3
In Center-Aligned PWM mode when (CLKSB:CLKSA not =
00), writes to TPMxCnVH:L registers4
TPMV2
Update the TPMxCnVH:L
registers with the value of
their write buffer after both
bytes are written and when
the TPM counter changes
from (TPMxMODH:L - 1) to
(TPMxMODH:L).
Note: If the TPM counter is a
free-running counter, then
this update is made when the
TPM counter changes from
0xFFFE to 0xFFFF.
Update after both bytes are
written and when the TPM
counter changes from
TPMxMODH:L to
(TPMxMODH:L - 1).
Produces 100% duty cycle.
Produces 0% duty cycle.
Produces a near 100% duty
cycle.
Produces 0% duty cycle.
TPMxCnVH:L is changed from 0x0000 to a non-zero value7
Waits for the start of a new
PWM period to begin using
the new duty cycle setting.
Changes the channel output at
the middle of the current PWM
period (when the count
reaches 0x0000).
TPMxCnVH:L is changed from a non-zero value to 0x00008
Finishes the current PWM
period using the old duty
cycle setting.
Finishes the current PWM
period using the new duty
cycle setting.
Clears the write coherency
mechanism of
TPMxMODH:L registers.
Does not clear the write
coherency mechanism.
Center-Aligned PWM
When TPMxCnVH:L = TPMxMODH:L5
When TPMxCnVH:L = (TPMxMODH:L -
1)6
Write to TPMxMODH:L registers in BDM mode
In BDM mode, a write to TPMxSC register
1
2
3
4
5
6
7
8
For more information, refer to Section 16.3.2, “TPM-Counter Registers (TPMxCNTH:TPMxCNTL) .” [SE110-TPM case 7]
For more information, refer to Section 16.3.5, “TPM Channel Value Registers (TPMxCnVH:TPMxCnVL).”
For more information, refer to Section 16.4.2.1, “Input Capture Mode .”
For more information, refer to Section 16.4.2.4, “Center-Aligned PWM Mode.”
For more information, refer to Section 16.4.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 1]
For more information, refer to Section 16.4.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 2]
For more information, refer to Section 16.4.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 3 and 5]
For more information, refer to Section 16.4.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 4]
16.1.4
Migrating from TPMV1
In addition to Section 16.1.3, “TPMV3 Differences from Previous Versions,” keep in mind the following
considerations when migrating from a device that uses TPMV1.
• You can write to the Channel Value register (TPMxCnV) when the timer is not in input capture
mode for TPMV2, not TPMV3.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
238
Freescale Semiconductor
Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)
•
•
In edge- or center- aligned modes, the Channel Value register (TPMxCnV) registers only update
when the timer changes from TPMMOD-1 to TPMMOD, or in the case of a free running timer
from 0xFFFE to 0xFFFF.
Also, when configuring the TPM modules, it is best to write to TPMxSC before TPMxCnV as a
write to TPMxSC resets the coherency mechanism on the TPMxCnV registers.
Table 16-3. Migrating to TPMV3 Considerations
When...
Writing to the Channel Value Register (TPMxCnV)
register...
Action / Best Practice
Timer must be in Input Capture mode.
Updating the Channel Value Register (TPMxCnV) Only occurs when the timer changes from
register in edge-aligned or center-aligned modes... TPMMOD-1 to TPMMOD (or in the case of a free
running timer, from 0xFFFE to 0xFFFF).
Reseting the coherency mechanism for the
Channel Value Register (TPMxCnV) register...
Write to TPMxSC.
Configuring the TPM modules...
Write first to TPMxSC and then to TPMxCnV
register.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
239
Timer/PWM Module (S08TPMV3)
16.1.5
Features
The TPM includes these distinctive features:
• One to eight channels:
— Each channel may be input capture, output compare, or edge-aligned PWM
— Rising-Edge, falling-edge, or any-edge input capture trigger
— Set, clear, or toggle output compare action
— Selectable polarity on PWM outputs
• Module may be configured for buffered, center-aligned pulse-width-modulation (CPWM) on all
channels
• Timer clock source selectable as prescaled bus clock, fixed system clock, or an external clock pin
— Prescale taps for divide-by 1, 2, 4, 8, 16, 32, 64, or 128
— Fixed system clock source are synchronized to the bus clock by an on-chip synchronization
circuit
— External clock pin may be shared with any timer channel pin or a separated input pin
• 16-bit free-running or modulo up/down count operation
• Timer system enable
• One interrupt per channel plus terminal count interrupt
16.1.6
Modes of Operation
In general, TPM channels may be independently configured to operate in input capture, output compare,
or edge-aligned PWM modes. A control bit allows the whole TPM (all channels) to switch to
center-aligned PWM mode. When center-aligned PWM mode is selected, input capture, output compare,
and edge-aligned PWM functions are not available on any channels of this TPM module.
When the microcontroller is in active BDM background or BDM foreground mode, the TPM temporarily
suspends all counting until the microcontroller returns to normal user operating mode. During stop mode,
all system clocks, including the main oscillator, are stopped; therefore, the TPM is effectively disabled
until clocks resume. During wait mode, the TPM continues to operate normally. Provided the TPM does
not need to produce a real time reference or provide the interrupt source(s) needed to wake the MCU from
wait mode, the user can save power by disabling TPM functions before entering wait mode.
• Input capture mode
When a selected edge event occurs on the associated MCU pin, the current value of the 16-bit timer
counter is captured into the channel value register and an interrupt flag bit is set. Rising edges,
falling edges, any edge, or no edge (disable channel) may be selected as the active edge which
triggers the input capture.
• Output compare mode
When the value in the timer counter register matches the channel value register, an interrupt flag
bit is set, and a selected output action is forced on the associated MCU pin. The output compare
action may be selected to force the pin to zero, force the pin to one, toggle the pin, or ignore the
pin (used for software timing functions).
MC9S08SG8 MCU Series Data Sheet, Rev. 8
240
Freescale Semiconductor
Timer/PWM Module (S08TPMV3)
•
•
Edge-aligned PWM mode
The value of a 16-bit modulo register plus 1 sets the period of the PWM output signal. The channel
value register sets the duty cycle of the PWM output signal. The user may also choose the polarity
of the PWM output signal. Interrupts are available at the end of the period and at the duty-cycle
transition point. This type of PWM signal is called edge-aligned because the leading edges of all
PWM signals are aligned with the beginning of the period, which is the same for all channels within
a TPM.
Center-aligned PWM mode
Twice the value of a 16-bit modulo register sets the period of the PWM output, and the
channel-value register sets the half-duty-cycle duration. The timer counter counts up until it
reaches the modulo value and then counts down until it reaches zero. As the count matches the
channel value register while counting down, the PWM output becomes active. When the count
matches the channel value register while counting up, the PWM output becomes inactive. This type
of PWM signal is called center-aligned because the centers of the active duty cycle periods for all
channels are aligned with a count value of zero. This type of PWM is required for types of motors
used in small appliances.
This is a high-level description only. Detailed descriptions of operating modes are in later sections.
16.1.7
Block Diagram
The TPM uses one input/output (I/O) pin per channel, TPMxCHn (timer channel n) where n is the channel
number (1-8). The TPM shares its I/O pins with general purpose I/O port pins (refer to I/O pin descriptions
in full-chip specification for the specific chip implementation).
Figure 16-2 shows the TPM structure. The central component of the TPM is the 16-bit counter that can
operate as a free-running counter or a modulo up/down counter. The TPM counter (when operating in
normal up-counting mode) provides the timing reference for the input capture, output compare, and
edge-aligned PWM functions. The timer counter modulo registers, TPMxMODH:TPMxMODL, control
the modulo value of the counter (the values 0x0000 or 0xFFFF effectively make the counter free running).
Software can read the counter value at any time without affecting the counting sequence. Any write to
either half of the TPMxCNT counter resets the counter, regardless of the data value written.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
241
Timer/PWM Module (S08TPMV3)
BUS CLOCK
FIXED SYSTEM CLOCK
SYNC
EXTERNAL CLOCK
CLOCK SOURCE
SELECT
OFF, BUS, FIXED
SYSTEM CLOCK, EXT
PRESCALE AND SELECT
³1, 2, 4, 8, 16, 32, 64,
or ³128
CLKSB:CLKSA
PS2:PS1:PS0
CPWMS
16-BIT COUNTER
TOF
COUNTER RESET
TOIE
INTERRUPT
LOGIC
16-BIT COMPARATOR
TPMxMODH:TPMxMODL
ELS0B
CHANNEL 0
ELS0A
PORT
LOGIC
TPMxCH0
16-BIT COMPARATOR
CH0F
TPMxC0VH:TPMxC0VL
INTERNAL BUS
16-BIT LATCH
CHANNEL 1
MS0B
MS0A
ELS1B
ELS1A
CH0IE
INTERRUPT
LOGIC
PORT
LOGIC
TPMxCH1
16-BIT COMPARATOR
CH1F
TPMxC1VH:TPMxC1VL
16-BIT LATCH
MS1B
CH1IE
MS1A
INTERRUPT
LOGIC
Up to 8 channels
ELS7B
CHANNEL 7
ELS7A
PORT
LOGIC
TPMxCH7
16-BIT COMPARATOR
CH7F
TPMxC7VH:TPMxC7VL
16-BIT LATCH
MS7B
MS7A
CH7IE
INTERRUPT
LOGIC
Figure 16-2. TPM Block Diagram
MC9S08SG8 MCU Series Data Sheet, Rev. 8
242
Freescale Semiconductor
Timer/PWM Module (S08TPMV3)
The TPM channels are programmable independently as input capture, output compare, or edge-aligned
PWM channels. Alternately, the TPM can be configured to produce CPWM outputs on all channels. When
the TPM is configured for CPWMs, the counter operates as an up/down counter; input capture, output
compare, and EPWM functions are not practical.
If a channel is configured as input capture, an internal pullup device may be enabled for that channel. The
details of how a module interacts with pin controls depends upon the chip implementation because the I/O
pins and associated general purpose I/O controls are not part of the module. Refer to the discussion of the
I/O port logic in a full-chip specification.
Because center-aligned PWMs are usually used to drive 3-phase AC-induction motors and brushless DC
motors, they are typically used in sets of three or six channels.
16.2
Signal Description
Table 16-4 shows the user-accessible signals for the TPM. The number of channels may be varied from
one to eight. When an external clock is included, it can be shared with the same pin as any TPM channel;
however, it could be connected to a separate input pin. Refer to the I/O pin descriptions in full-chip
specification for the specific chip implementation.
Table 16-4. Signal Properties
Name
Function
EXTCLK1
2
TPMxCHn
External clock source which may be selected to drive the TPM counter.
I/O pin associated with TPM channel n
1
When preset, this signal can share any channel pin; however depending upon full-chip
implementation, this signal could be connected to a separate external pin.
2 n=channel number (1 to 8)
Refer to documentation for the full-chip for details about reset states, port connections, and whether there
is any pullup device on these pins.
TPM channel pins can be associated with general purpose I/O pins and have passive pullup devices which
can be enabled with a control bit when the TPM or general purpose I/O controls have configured the
associated pin as an input. When no TPM function is enabled to use a corresponding pin, the pin reverts
to being controlled by general purpose I/O controls, including the port-data and data-direction registers.
Immediately after reset, no TPM functions are enabled, so all associated pins revert to general purpose I/O
control.
16.2.1
Detailed Signal Descriptions
This section describes each user-accessible pin signal in detail. Although Table 16-4 grouped all channel
pins together, any TPM pin can be shared with the external clock source signal. Since I/O pin logic is not
part of the TPM, refer to full-chip documentation for a specific derivative for more details about the
interaction of TPM pin functions and general purpose I/O controls including port data, data direction, and
pullup controls.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
243
Timer/PWM Module (S08TPMV3)
16.2.1.1
EXTCLK — External Clock Source
Control bits in the timer status and control register allow the user to select nothing (timer disable), the
bus-rate clock (the normal default source), a crystal-related clock, or an external clock as the clock which
drives the TPM prescaler and subsequently the 16-bit TPM counter. The external clock source is
synchronized in the TPM. The bus clock clocks the synchronizer; the frequency of the external source must
be no more than one-fourth the frequency of the bus-rate clock, to meet Nyquist criteria and allowing for
jitter.
The external clock signal shares the same pin as a channel I/O pin, so the channel pin will not be usable
for channel I/O function when selected as the external clock source. It is the user’s responsibility to avoid
such settings. If this pin is used as an external clock source (CLKSB:CLKSA = 1:1), the channel can still
be used in output compare mode as a software timer (ELSnB:ELSnA = 0:0).
16.2.1.2
TPMxCHn — TPM Channel n I/O Pin(s)
Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the
channel configuration. The TPM pins share with general purpose I/O pins, where each pin has a port data
register bit, and a data direction control bit, and the port has optional passive pullups which may be enabled
whenever a port pin is acting as an input.
The TPM channel does not control the I/O pin when (ELSnB:ELSnA = 0:0) or when (CLKSB:CLKSA =
0:0) so it normally reverts to general purpose I/O control. When CPWMS = 1 (and ELSnB:ELSnA not =
0:0), all channels within the TPM are configured for center-aligned PWM and the TPMxCHn pins are all
controlled by the TPM system. When CPWMS=0, the MSnB:MSnA control bits determine whether the
channel is configured for input capture, output compare, or edge-aligned PWM.
When a channel is configured for input capture (CPWMS=0, MSnB:MSnA = 0:0 and ELSnB:ELSnA not
= 0:0), the TPMxCHn pin is forced to act as an edge-sensitive input to the TPM. ELSnB:ELSnA control
bits determine what polarity edge or edges will trigger input-capture events. A synchronizer based on the
bus clock is used to synchronize input edges to the bus clock. This implies the minimum pulse width—that
can be reliably detected—on an input capture pin is four bus clock periods (with ideal clock pulses as near
as two bus clocks can be detected). TPM uses this pin as an input capture input to override the port data
and data direction controls for the same pin.
When a channel is configured for output compare (CPWMS=0, MSnB:MSnA = 0:1 and ELSnB:ELSnA
not = 0:0), the associated data direction control is overridden, the TPMxCHn pin is considered an output
controlled by the TPM, and the ELSnB:ELSnA control bits determine how the pin is controlled. The
remaining three combinations of ELSnB:ELSnA determine whether the TPMxCHn pin is toggled, cleared,
or set each time the 16-bit channel value register matches the timer counter.
When the output compare toggle mode is initially selected, the previous value on the pin is driven out until
the next output compare event—then the pin is toggled.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
244
Freescale Semiconductor
Timer/PWM Module (S08TPMV3)
When a channel is configured for edge-aligned PWM (CPWMS=0, MSnB=1 and ELSnB:ELSnA not =
0:0), the data direction is overridden, the TPMxCHn pin is forced to be an output controlled by the TPM,
and ELSnA controls the polarity of the PWM output signal on the pin. When ELSnB:ELSnA=1:0, the
TPMxCHn pin is forced high at the start of each new period (TPMxCNT=0x0000), and the pin is forced
low when the channel value register matches the timer counter. When ELSnA=1, the TPMxCHn pin is
forced low at the start of each new period (TPMxCNT=0x0000), and the pin is forced high when the
channel value register matches the timer counter.
TPMxMODH:TPMxMODL = 0x0008
TPMxMODH:TPMxMODL = 0x0005
TPMxCNTH:TPMxCNTL...
0
1
2
3
4
5
6
7
8
0
1
2
...
2
...
TPMxCHn
CHnF BIT
TOF BIT
Figure 16-3. High-True Pulse of an Edge-Aligned PWM
TPMxMODH:TPMxMODL = 0x0008
TPMxMODH:TPMxMODL = 0x0005
TPMxCNTH:TPMxCNTL...
0
1
2
3
4
5
6
7
8
0
1
TPMxCHn
CHnF BIT
TOF BIT
Figure 16-4. Low-True Pulse of an Edge-Aligned PWM
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
245
Timer/PWM Module (S08TPMV3)
When the TPM is configured for center-aligned PWM (and ELSnB:ELSnA not = 0:0), the data direction
for all channels in this TPM are overridden, the TPMxCHn pins are forced to be outputs controlled by the
TPM, and the ELSnA bits control the polarity of each TPMxCHn output. If ELSnB:ELSnA=1:0, the
corresponding TPMxCHn pin is cleared when the timer counter is counting up, and the channel value
register matches the timer counter; the TPMxCHn pin is set when the timer counter is counting down, and
the channel value register matches the timer counter. If ELSnA=1, the corresponding TPMxCHn pin is set
when the timer counter is counting up and the channel value register matches the timer counter; the
TPMxCHn pin is cleared when the timer counter is counting down and the channel value register matches
the timer counter.
TPMxMODH:TPMxMODL = 0x0008
TPMxMODH:TPMxMODL = 0x0005
TPMxCNTH:TPMxCNTL ...
7
8
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
8
7
6
5
...
7
8
7
6
5
...
TPMxCHn
CHnF BIT
TOF BIT
Figure 16-5. High-True Pulse of a Center-Aligned PWM
TPMxMODH:TPMxMODL = 0x0008
TPMxMODH:TPMxMODL = 0x0005
TPMxCNTH:TPMxCNTL ...
7
8
7
6
5
4
3
2
1
0
1
2
3
4
5
6
TPMxCHn
CHnF BIT
TOF BIT
Figure 16-6. Low-True Pulse of a Center-Aligned PWM
MC9S08SG8 MCU Series Data Sheet, Rev. 8
246
Freescale Semiconductor
Timer/PWM Module (S08TPMV3)
16.3
Register Definition
This section consists of register descriptions in address order.
16.3.1
TPM Status and Control Register (TPMxSC)
TPMxSC contains the overflow status flag and control bits used to configure the interrupt enable, TPM
configuration, clock source, and prescale factor. These controls relate to all channels within this timer
module.
7
R
TOF
W
0
Reset
0
6
5
4
3
2
1
0
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
0
0
0
0
0
0
0
Figure 16-7. TPM Status and Control Register (TPMxSC)
Table 16-5. TPMxSC Field Descriptions
Field
Description
7
TOF
Timer overflow flag. This read/write flag is set when the TPM counter resets to 0x0000 after reaching the modulo
value programmed in the TPM counter modulo registers. Clear TOF by reading the TPM status and control
register when TOF is set and then writing a logic 0 to TOF. If another TPM overflow occurs before the clearing
sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed
for the earlier TOF. This is done so a TOF interrupt request cannot be lost during the clearing sequence for a
previous TOF. Reset clears TOF. Writing a logic 1 to TOF has no effect.
0 TPM counter has not reached modulo value or overflow
1 TPM counter has overflowed
6
TOIE
Timer overflow interrupt enable. This read/write bit enables TPM overflow interrupts. If TOIE is set, an interrupt is
generated when TOF equals one. Reset clears TOIE.
0 TOF interrupts inhibited (use for software polling)
1 TOF interrupts enabled
5
CPWMS
Center-aligned PWM select. When present, this read/write bit selects CPWM operating mode. By default, the TPM
operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting
CPWMS reconfigures the TPM to operate in up/down counting mode for CPWM functions. Reset clears CPWMS.
0 All channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the
MSnB:MSnA control bits in each channel’s status and control register.
1 All channels operate in center-aligned PWM mode.
4–3
Clock source selects. As shown in Table 16-6, this 2-bit field is used to disable the TPM system or select one of
CLKS[B:A] three clock sources to drive the counter prescaler. The fixed system clock source is only meaningful in systems
with a PLL-based system clock. When there is no PLL, the fixed-system clock source is the same as the bus rate
clock. The external source is synchronized to the bus clock by TPM module, and the fixed system clock source
(when a PLL is present) is synchronized to the bus clock by an on-chip synchronization circuit. When a PLL is
present but not enabled, the fixed-system clock source is the same as the bus-rate clock.
2–0
PS[2:0]
Prescale factor select. This 3-bit field selects one of 8 division factors for the TPM clock input as shown in
Table 16-7. This prescaler is located after any clock source synchronization or clock source selection so it affects
the clock source selected to drive the TPM system. The new prescale factor will affect the clock source on the
next system clock cycle after the new value is updated into the register bits.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
247
Timer/PWM Module (S08TPMV3)
Table 16-6. TPM-Clock-Source Selection
CLKSB:CLKSA
TPM Clock Source to Prescaler Input
00
No clock selected (TPM counter disable)
01
Bus rate clock
10
Fixed system clock
11
External source
Table 16-7. Prescale Factor Selection
16.3.2
PS2:PS1:PS0
TPM Clock Source Divided-by
000
1
001
2
010
4
011
8
100
16
101
32
110
64
111
128
TPM-Counter Registers (TPMxCNTH:TPMxCNTL)
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where
they remain latched until the other half is read. This allows coherent 16-bit reads in either big-endian or
little-endian order which makes this more friendly to various compiler implementations. The coherency
mechanism is automatically restarted by an MCU reset or any write to the timer status/control register
(TPMxSC).
Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the
TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data
involved in the write.
R
7
6
5
4
3
2
1
0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
W
Reset
Any write to TPMxCNTH clears the 16-bit counter
0
0
0
0
0
0
Figure 16-8. TPM Counter Register High (TPMxCNTH)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
248
Freescale Semiconductor
Timer/PWM Module (S08TPMV3)
R
7
6
5
4
3
2
1
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
W
Reset
Any write to TPMxCNTL clears the 16-bit counter
0
0
0
0
0
0
Figure 16-9. TPM Counter Register Low (TPMxCNTL)
When BDM is active, the timer counter is frozen (this is the value that will be read by user); the coherency
mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became
active, even if one or both counter halves are read while BDM is active. This assures that if the user was
in the middle of reading a 16-bit register when BDM became active, it will read the appropriate value from
the other half of the 16-bit value after returning to normal execution.
In BDM mode, writing any value to TPMxSC, TPMxCNTH or TPMxCNTL registers resets the read
coherency mechanism of the TPMxCNTH:L registers, regardless of the data involved in the write.
16.3.3
TPM Counter Modulo Registers (TPMxMODH:TPMxMODL)
The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock, and
the overflow flag (TOF) becomes set. Writing to TPMxMODH or TPMxMODL inhibits the TOF bit and
overflow interrupts until the other byte is written. Reset sets the TPM counter modulo registers to 0x0000
which results in a free running timer counter (modulo disabled).
Writing to either byte (TPMxMODH or TPMxMODL) latches the value into a buffer and the registers are
updated with the value of their write buffer according to the value of CLKSB:CLKSA bits, so:
• If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written
• If (CLKSB:CLKSA not = 0:0), then the registers are updated after both bytes were written, and the
TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If
the TPM counter is a free-running counter, the update is made when the TPM counter changes from
0xFFFE to 0xFFFF
The latching mechanism may be manually reset by writing to the TPMxSC address (whether BDM is
active or not).
When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC register)
such that the buffer latches remain in the state they were in when the BDM became active, even if one or
both halves of the modulo register are written while BDM is active. Any write to the modulo registers
bypasses the buffer latches and directly writes to the modulo register while BDM is active.
7
6
5
4
3
2
1
0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
R
W
Reset
Figure 16-10. TPM Counter Modulo Register High (TPMxMODH)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
249
Timer/PWM Module (S08TPMV3)
7
6
5
4
3
2
1
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
R
W
Reset
Reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first
counter overflow will occur.
16.3.4
TPM Channel n Status and Control Register (TPMxCnSC)
TPMxCnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt
enable, channel configuration, and pin function.
7
R
6
5
4
3
2
CHnIE
MSnB
MSnA
ELSnB
ELSnA
0
0
0
0
0
CHnF
W
0
Reset
0
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 16-12. TPM Channel n Status and Control Register (TPMxCnSC)
Table 16-8. TPMxCnSC Field Descriptions
Field
Description
7
CHnF
Channel n flag. When channel n is an input-capture channel, this read/write bit is set when an active edge occurs
on the channel n pin. When channel n is an output compare or edge-aligned/center-aligned PWM channel, CHnF
is set when the value in the TPM counter registers matches the value in the TPM channel n value registers. When
channel n is an edge-aligned/center-aligned PWM channel and the duty cycle is set to 0% or 100%, CHnF will not
be set even when the value in the TPM counter registers matches the value in the TPM channel n value registers.
A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF by
reading TPMxCnSC while CHnF is set and then writing a logic 0 to CHnF. If another interrupt request occurs
before the clearing sequence is complete, the sequence is reset so CHnF remains set after the clear sequence
completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost due to clearing a previous
CHnF.
Reset clears the CHnF bit. Writing a logic 1 to CHnF has no effect.
0 No input capture or output compare event occurred on channel n
1 Input capture or output compare event on channel n
6
CHnIE
Channel n interrupt enable. This read/write bit enables interrupts from channel n. Reset clears CHnIE.
0 Channel n interrupt requests disabled (use for software polling)
1 Channel n interrupt requests enabled
5
MSnB
Mode select B for TPM channel n. When CPWMS=0, MSnB=1 configures TPM channel n for edge-aligned PWM
mode. Refer to the summary of channel mode and setup controls in Table 16-9.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
250
Freescale Semiconductor
Timer/PWM Module (S08TPMV3)
Table 16-8. TPMxCnSC Field Descriptions (continued)
Field
Description
4
MSnA
Mode select A for TPM channel n. When CPWMS=0 and MSnB=0, MSnA configures TPM channel n for
input-capture mode or output compare mode. Refer to Table 16-9 for a summary of channel mode and setup
controls.
Note: If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger.
3–2
ELSnB
ELSnA
Edge/level select bits. Depending upon the operating mode for the timer channel as set by CPWMS:MSnB:MSnA
and shown in Table 16-9, these bits select the polarity of the input edge that triggers an input capture event, select
the level that will be driven in response to an output compare match, or select the polarity of the PWM output.
Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general purpose I/O pin not related to any timer
functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin
available as a general purpose I/O pin when the associated timer channel is set up as a software timer that does
not require the use of a pin.
Table 16-9. Mode, Edge, and Level Selection
CPWMS
MSnB:MSnA
ELSnB:ELSnA
X
XX
00
Pin not used for TPM - revert to general
purpose I/O or other peripheral control
0
00
01
Input capture
01
1X
Mode
XX
Capture on falling edge
only
11
Capture on rising or
falling edge
01
Output compare
Toggle output on
compare
10
Clear output on
compare
11
Set output on compare
10
Edge-aligned
PWM
10
High-true pulses (clear
output on compare)
Low-true pulses (set
output on compare)
Center-aligned
PWM
X1
16.3.5
Capture on rising edge
only
10
X1
1
Configuration
High-true pulses (clear
output on compare-up)
Low-true pulses (set
output on compare-up)
TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel registers are cleared by
reset.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
251
Timer/PWM Module (S08TPMV3)
7
6
5
4
3
2
1
0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
R
W
Reset
Figure 16-13. TPM Channel Value Register High (TPMxCnVH)
7
6
5
4
3
2
1
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 16-14. TPM Channel Value Register Low (TPMxCnVL)
In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes
into a buffer where they remain latched until the other half is read. This latching mechanism also resets
(becomes unlatched) when the TPMxCnSC register is written (whether BDM mode is active or not). Any
write to the channel registers will be ignored during the input capture mode.
When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxCnSC register)
such that the buffer latches remain in the state they were in when the BDM became active, even if one or
both halves of the channel register are read while BDM is active. This assures that if the user was in the
middle of reading a 16-bit register when BDM became active, it will read the appropriate value from the
other half of the 16-bit value after returning to normal execution. The value read from the TPMxCnVH
and TPMxCnVL registers in BDM mode is the value of these registers and not the value of their read
buffer.
In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value
into a buffer. After both bytes are written, they are transferred as a coherent 16-bit value into the
timer-channel registers according to the value of CLKSB:CLKSA bits and the selected mode, so:
• If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written.
• If (CLKSB:CLKSA not = 0:0 and in output compare mode) then the registers are updated after the
second byte is written and on the next change of the TPM counter (end of the prescaler counting).
• If (CLKSB:CLKSA not = 0:0 and in EPWM or CPWM modes), then the registers are updated after
the both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1)
to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter then the update is
made when the TPM counter changes from 0xFFFE to 0xFFFF.
The latching mechanism may be manually reset by writing to the TPMxCnSC register (whether BDM
mode is active or not). This latching mechanism allows coherent 16-bit writes in either big-endian or
little-endian order which is friendly to various compiler implementations.
When BDM is active, the coherency mechanism is frozen such that the buffer latches remain in the state
they were in when the BDM became active even if one or both halves of the channel register are written
while BDM is active. Any write to the channel registers bypasses the buffer latches and directly write to
the channel register while BDM is active. The values written to the channel register while BDM is active
MC9S08SG8 MCU Series Data Sheet, Rev. 8
252
Freescale Semiconductor
Timer/PWM Module (S08TPMV3)
are used for PWM & output compare operation once normal execution resumes. Writes to the channel
registers while BDM is active do not interfere with partial completion of a coherency sequence. After the
coherency mechanism has been fully exercised, the channel registers are updated using the buffered values
written (while BDM was not active) by the user.
16.4
Functional Description
All TPM functions are associated with a central 16-bit counter which allows flexible selection of the clock
source and prescale factor. There is also a 16-bit modulo register associated with the main counter.
The CPWMS control bit chooses between center-aligned PWM operation for all channels in the TPM
(CPWMS=1) or general purpose timing functions (CPWMS=0) where each channel can independently be
configured to operate in input capture, output compare, or edge-aligned PWM mode. The CPWMS control
bit is located in the main TPM status and control register because it affects all channels within the TPM
and influences the way the main counter operates. (In CPWM mode, the counter changes to an up/down
mode rather than the up-counting mode used for general purpose timer functions.)
The following sections describe the main counter and each of the timer operating modes (input capture,
output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and
interrupt activity depend upon the operating mode, these topics will be covered in the associated mode
explanation sections.
16.4.1
Counter
All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section
discusses selection of the clock source, end-of-count overflow, up-counting vs. up/down counting, and
manual counter reset.
16.4.1.1
Counter Clock Source
The 2-bit field, CLKSB:CLKSA, in the timer status and control register (TPMxSC) selects one of three
possible clock sources or OFF (which effectively disables the TPM). See Table 16-6. After any MCU reset,
CLKSB:CLKSA=0:0 so no clock source is selected, and the TPM is in a very low power state. These
control bits may be read or written at any time and disabling the timer (writing 00 to the CLKSB:CLKSA
field) does not affect the values in the counter or other timer registers.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
253
Timer/PWM Module (S08TPMV3)
Table 16-10. TPM Clock Source Selection
CLKSB:CLKSA
TPM Clock Source to Prescaler Input
00
No clock selected (TPM counter disabled)
01
Bus rate clock
10
Fixed system clock
11
External source
The bus rate clock is the main system bus clock for the MCU. This clock source requires no
synchronization because it is the clock that is used for all internal MCU activities including operation of
the CPU and buses.
In MCUs that have no PLL or the PLL is not engaged, the fixed system clock source is the same as the
bus-rate-clock source, and it does not go through a synchronizer. When a PLL is present and engaged, a
synchronizer is required between the crystal divided-by two clock source and the timer counter so counter
transitions will be properly aligned to bus-clock transitions. A synchronizer will be used at chip level to
synchronize the crystal-related source clock to the bus clock.
The external clock source may be connected to any TPM channel pin. This clock source always has to pass
through a synchronizer to assure that counter transitions are properly aligned to bus clock transitions. The
bus-rate clock drives the synchronizer; therefore, to meet Nyquist criteria even with jitter, the frequency
of the external clock source must not be faster than the bus rate divided-by four. With ideal clocks the
external clock can be as fast as bus clock divided by four.
When the external clock source shares the TPM channel pin, this pin should not be used for other channel
timing functions. For example, it would be ambiguous to configure channel 0 for input capture when the
TPM channel 0 pin was also being used as the timer external clock source. (It is the user’s responsibility
to avoid such settings.) The TPM channel could still be used in output compare mode for software timing
functions (pin controls set not to affect the TPM channel pin).
16.4.1.2
Counter Overflow and Modulo Reset
An interrupt flag and enable are associated with the 16-bit main counter. The flag (TOF) is a
software-accessible indication that the timer counter has overflowed. The enable signal selects between
software polling (TOIE=0) where no hardware interrupt is generated, or interrupt-driven operation
(TOIE=1) where a static hardware interrupt is generated whenever the TOF flag is equal to one.
The conditions causing TOF to become set depend on whether the TPM is configured for center-aligned
PWM (CPWMS=1). In the simplest mode, there is no modulus limit and the TPM is not in CPWMS=1
mode. In this case, the 16-bit timer counter counts from 0x0000 through 0xFFFF and overflows to 0x0000
on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus
limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When
the TPM is in center-aligned PWM mode (CPWMS=1), the TOF flag gets set as the counter changes
direction at the end of the count value set in the modulus register (that is, at the transition from the value
set in the modulus register to the next lower count value). This corresponds to the end of a PWM period
(the 0x0000 count value corresponds to the center of a period).
MC9S08SG8 MCU Series Data Sheet, Rev. 8
254
Freescale Semiconductor
Timer/PWM Module (S08TPMV3)
16.4.1.3
Counting Modes
The main timer counter has two counting modes. When center-aligned PWM is selected (CPWMS=1), the
counter operates in up/down counting mode. Otherwise, the counter operates as a simple up counter. As
an up counter, the timer counter counts from 0x0000 through its terminal count and then continues with
0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL.
When center-aligned PWM operation is specified, the counter counts up from 0x0000 through its terminal
count and then down to 0x0000 where it changes back to up counting. Both 0x0000 and the terminal count
value are normal length counts (one timer clock period long). In this mode, the timer overflow flag (TOF)
becomes set at the end of the terminal-count period (as the count changes to the next lower count value).
16.4.1.4
Manual Counter Reset
The main timer counter can be manually reset at any time by writing any value to either half of
TPMxCNTH or TPMxCNTL. Resetting the counter in this manner also resets the coherency mechanism
in case only half of the counter was read before resetting the count.
16.4.2
Channel Mode Selection
Provided CPWMS=0, the MSnB and MSnA control bits in the channel n status and control registers
determine the basic mode of operation for the corresponding channel. Choices include input capture,
output compare, and edge-aligned PWM.
16.4.2.1
Input Capture Mode
With the input-capture function, the TPM can capture the time at which an external event occurs. When
an active edge occurs on the pin of an input-capture channel, the TPM latches the contents of the TPM
counter into the channel-value registers (TPMxCnVH:TPMxCnVL). Rising edges, falling edges, or any
edge may be chosen as the active edge that triggers an input capture.
In input capture mode, the TPMxCnVH and TPMxCnVL registers are read only.
When either half of the 16-bit capture register is read, the other half is latched into a buffer to support
coherent 16-bit accesses in big-endian or little-endian order. The coherency sequence can be manually
reset by writing to the channel status/control register (TPMxCnSC).
An input capture event sets a flag bit (CHnF) which may optionally generate a CPU interrupt request.
While in BDM, the input capture function works as configured by the user. When an external event occurs,
the TPM latches the contents of the TPM counter (which is frozen because of the BDM mode) into the
channel value registers and sets the flag bit.
16.4.2.2
Output Compare Mode
With the output-compare function, the TPM can generate timed pulses with programmable position,
polarity, duration, and frequency. When the counter reaches the value in the channel-value registers of an
output-compare channel, the TPM can set, clear, or toggle the channel pin.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
255
Timer/PWM Module (S08TPMV3)
In output compare mode, values are transferred to the corresponding timer channel registers only after both
8-bit halves of a 16-bit register have been written and according to the value of CLKSB:CLKSA bits, so:
• If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written
• If (CLKSB:CLKSA not = 0:0), the registers are updated at the next change of the TPM counter
(end of the prescaler counting) after the second byte is written.
The coherency sequence can be manually reset by writing to the channel status/control register
(TPMxCnSC).
An output compare event sets a flag bit (CHnF) which may optionally generate a CPU-interrupt request.
16.4.2.3
Edge-Aligned PWM Mode
This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS=0) and can
be used when other channels in the same TPM are configured for input capture or output compare
functions. The period of this PWM signal is determined by the value of the modulus register
(TPMxMODH:TPMxMODL) plus 1. The duty cycle is determined by the setting in the timer channel
register (TPMxCnVH:TPMxCnVL). The polarity of this PWM signal is determined by the setting in the
ELSnA control bit. 0% and 100% duty cycle cases are possible.
The output compare value in the TPM channel registers determines the pulse width (duty cycle) of the
PWM signal (Figure 16-15). The time between the modulus overflow and the output compare is the pulse
width. If ELSnA=0, the counter overflow forces the PWM signal high, and the output compare forces the
PWM signal low. If ELSnA=1, the counter overflow forces the PWM signal low, and the output compare
forces the PWM signal high.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
TPMxCHn
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 16-15. PWM Period and Pulse Width (ELSnA=0)
When the channel value register is set to 0x0000, the duty cycle is 0%. 100% duty cycle can be achieved
by setting the timer-channel register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus
setting. This implies that the modulus setting must be less than 0xFFFF in order to get 100% duty cycle.
Because the TPM may be used in an 8-bit MCU, the settings in the timer channel registers are buffered to
ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers
TPMxCnVH and TPMxCnVL, actually write to buffer registers. In edge-aligned PWM mode, values are
transferred to the corresponding timer-channel registers according to the value of CLKSB:CLKSA bits, so:
• If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written
• If (CLKSB:CLKSA not = 0:0), the registers are updated after the both bytes were written, and the
TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If
MC9S08SG8 MCU Series Data Sheet, Rev. 8
256
Freescale Semiconductor
Timer/PWM Module (S08TPMV3)
the TPM counter is a free-running counter then the update is made when the TPM counter changes
from 0xFFFE to 0xFFFF.
16.4.2.4
Center-Aligned PWM Mode
This type of PWM output uses the up/down counting mode of the timer counter (CPWMS=1). The output
compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal
while the period is determined by the value in TPMxMODH:TPMxMODL. TPMxMODH:TPMxMODL
should be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous
results. ELSnA will determine the polarity of the CPWM output.
pulse width = 2 x (TPMxCnVH:TPMxCnVL)
period = 2 x (TPMxMODH:TPMxMODL); TPMxMODH:TPMxMODL=0x0001-0x7FFF
If the channel-value register TPMxCnVH:TPMxCnVL is zero or negative (bit 15 set), the duty cycle will
be 0%. If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the (non-zero)
modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This
implies the usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if you
do not need to generate 100% duty cycle). This is not a significant limitation. The resulting period would
be much longer than required for normal applications.
TPMxMODH:TPMxMODL=0x0000 is a special case that should not be used with center-aligned PWM
mode. When CPWMS=0, this case corresponds to the counter running free from 0x0000 through 0xFFFF,
but when CPWMS=1 the counter needs a valid match to the modulus register somewhere other than at
0x0000 in order to change directions from up-counting to down-counting.
The output compare value in the TPM channel registers (times 2) determines the pulse width (duty cycle)
of the CPWM signal (Figure 16-16). If ELSnA=0, a compare occurred while counting up forces the
CPWM output signal low and a compare occurred while counting down forces the output high. The
counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then counts down
until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL.
COUNT= 0
OUTPUT
COUNT=
COMPARE
TPMxMODH:TPMxMODL (COUNT DOWN)
OUTPUT
COMPARE
(COUNT UP)
COUNT=
TPMxMODH:TPMxMODL
TPMxCHn
PULSE WIDTH
2 x TPMxCnVH:TPMxCnVL
PERIOD
2 x TPMxMODH:TPMxMODL
Figure 16-16. CPWM Period and Pulse Width (ELSnA=0)
Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin
transitions are lined up at the same system clock edge. This type of PWM is also required for some types
of motor drives.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
257
Timer/PWM Module (S08TPMV3)
Input capture, output compare, and edge-aligned PWM functions do not make sense when the counter is
operating in up/down counting mode so this implies that all active channels within a TPM must be used in
CPWM mode when CPWMS=1.
The TPM may be used in an 8-bit MCU. The settings in the timer channel registers are buffered to ensure
coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers
TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers.
In center-aligned PWM mode, the TPMxCnVH:L registers are updated with the value of their write buffer
according to the value of CLKSB:CLKSA bits, so:
• If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written
• If (CLKSB:CLKSA not = 0:0), the registers are updated after the both bytes were written, and the
TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If
the TPM counter is a free-running counter, the update is made when the TPM counter changes from
0xFFFE to 0xFFFF.
When TPMxCNTH:TPMxCNTL=TPMxMODH:TPMxMODL, the TPM can optionally generate a TOF
interrupt (at the end of this count).
Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the
coherency mechanism for the modulo registers. Writing to TPMxCnSC cancels any values written to the
channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL.
16.5
16.5.1
Reset Overview
General
The TPM is reset whenever any MCU reset occurs.
16.5.2
Description of Reset Operation
Reset clears the TPMxSC register which disables clocks to the TPM and disables timer overflow interrupts
(TOIE=0). CPWMS, MSnB, MSnA, ELSnB, and ELSnA are all cleared which configures all TPM
channels for input-capture operation with the associated pins disconnected from I/O pin logic (so all MCU
pins related to the TPM revert to general purpose I/O pins).
16.6
16.6.1
Interrupts
General
The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel.
The meaning of channel interrupts depends on each channel’s mode of operation. If the channel is
configured for input capture, the interrupt flag is set each time the selected input capture edge is
recognized. If the channel is configured for output compare or PWM modes, the interrupt flag is set each
time the main timer counter matches the value in the 16-bit channel value register.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
258
Freescale Semiconductor
Timer/PWM Module (S08TPMV3)
All TPM interrupts are listed in Table 16-11 which shows the interrupt name, the name of any local enable
that can block the interrupt request from leaving the TPM and getting recognized by the separate interrupt
processing logic.
Table 16-11. Interrupt Summary
Interrupt
Local
Enable
Source
Description
TOF
TOIE
Counter overflow
Set each time the timer counter reaches its terminal
count (at transition to next count value which is
usually 0x0000)
CHnF
CHnIE
Channel event
An input capture or output compare event took
place on channel n
The TPM module will provide a high-true interrupt signal. Vectors and priorities are determined at chip
integration time in the interrupt module so refer to the user’s guide for the interrupt module or to the chip’s
complete documentation for details.
16.6.2
Description of Interrupt Operation
For each interrupt source in the TPM, a flag bit is set upon recognition of the interrupt condition such as
timer overflow, channel-input capture, or output-compare events. This flag may be read (polled) by
software to determine that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set
to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will generate
whenever the associated interrupt flag equals one. The user’s software must perform a sequence of steps
to clear the interrupt flag before returning from the interrupt-service routine.
TPM interrupt flags are cleared by a two-step process including a read of the flag bit while it is set (1)
followed by a write of zero (0) to the bit. If a new event is detected between these two steps, the sequence
is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new
event.
16.6.2.1
Timer Overflow Interrupt (TOF) Description
The meaning and details of operation for TOF interrupts varies slightly depending upon the mode of
operation of the TPM system (general purpose timing functions versus center-aligned PWM operation).
The flag is cleared by the two step sequence described above.
16.6.2.1.1
Normal Case
Normally TOF is set when the timer counter changes from 0xFFFF to 0x0000. When the TPM is not
configured for center-aligned PWM (CPWMS=0), TOF gets set when the timer counter changes from the
terminal count (the value in the modulo register) to 0x0000. This case corresponds to the normal meaning
of counter overflow.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
259
Timer/PWM Module (S08TPMV3)
16.6.2.1.2
Center-Aligned PWM Case
When CPWMS=1, TOF gets set when the timer counter changes direction from up-counting to
down-counting at the end of the terminal count (the value in the modulo register). In this case the TOF
corresponds to the end of a PWM period.
16.6.2.2
Channel Event Interrupt Description
The meaning of channel interrupts depends on the channel’s current mode (input-capture, output-compare,
edge-aligned PWM, or center-aligned PWM).
16.6.2.2.1
Input Capture Events
When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select no edge
(off), rising edges, falling edges or any edge as the edge which triggers an input capture event. When the
selected edge is detected, the interrupt flag is set. The flag is cleared by the two-step sequence described
in Section 16.6.2, “Description of Interrupt Operation.”
16.6.2.2.2
Output Compare Events
When a channel is configured as an output compare channel, the interrupt flag is set each time the main
timer counter matches the 16-bit value in the channel value register. The flag is cleared by the two-step
sequence described Section 16.6.2, “Description of Interrupt Operation.”
16.6.2.2.3
PWM End-of-Duty-Cycle Events
For channels configured for PWM operation there are two possibilities. When the channel is configured
for edge-aligned PWM, the channel flag gets set when the timer counter matches the channel value register
which marks the end of the active duty cycle period. When the channel is configured for center-aligned
PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM
case, the channel flag is set at the start and at the end of the active duty cycle period which are the times
when the timer counter matches the channel value register. The flag is cleared by the two-step sequence
described Section 16.6.2, “Description of Interrupt Operation.”
MC9S08SG8 MCU Series Data Sheet, Rev. 8
260
Freescale Semiconductor
Chapter 17
Development Support
17.1
Introduction
Development support systems in the HCS08 include the background debug controller (BDC) and the
on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that
provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories. The
BDC is also the primary debug interface for development and allows non-intrusive access to memory data
and traditional debug features such as CPU register modify, breakpoints, and single instruction trace
commands.
In the HCS08 Family, address and data bus signals are not available on external pins (not even in test
modes). Debug is done through commands fed into the target MCU via the single-wire background debug
interface. The debug module provides a means to selectively trigger and capture bus information so an
external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis
without having external access to the address and data signals.
17.1.1
Forcing Active Background
The method for forcing active background mode depends on the specific HCS08 derivative. For the
MC9S08SG8, you can force active background after a power-on reset by holding the BKGD pin low as
the device exits the reset condition. You can also force active background by driving BKGD low
immediately after a serial background command that writes a one to the BDFR bit in the SBDFR register.
Other causes of reset including an external pin reset or an internally generated error reset ignore the state
of the BKGD pin and reset into normal user mode. If no debug pod is connected to the BKGD pin, the
MCU will always reset into normal operating mode.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
261
17.1.2
Features
Features of the BDC module include:
• Single pin for mode selection and background communications
• BDC registers are not located in the memory map
• SYNC command to determine target communications rate
• Non-intrusive commands for memory access
• Active background mode commands for CPU register access
• GO and TRACE1 commands
• BACKGROUND command can wake CPU from stop or wait modes
• One hardware address breakpoint built into BDC
• Oscillator runs in stop mode, if BDC enabled
• COP watchdog disabled while in active background mode
Features of the ICE system include:
• Two trigger comparators: Two address + read/write (R/W) or one full address + data + R/W
• Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information:
— Change-of-flow addresses or
— Event-only data
• Two types of breakpoints:
— Tag breakpoints for instruction opcodes
— Force breakpoints for any address access
• Nine trigger modes:
— Basic: A-only, A OR B
— Sequence: A then B
— Full: A AND B data, A AND NOT B data
— Event (store data): Event-only B, A then event-only B
— Range: Inside range (A address B), outside range (address < A or address > B)
17.2
Background Debug Controller (BDC)
All MCUs in the HCS08 Family contain a single-wire background debug interface that supports in-circuit
programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike
debug interfaces on earlier 8-bit MCUs, this system does not interfere with normal application resources.
It does not use any user memory or locations in the memory map and does not share any on-chip
peripherals.
BDC commands are divided into two groups:
• Active background mode commands require that the target MCU is in active background mode (the
user program is not running). Active background mode commands allow the CPU registers to be
read or written, and allow the user to trace one user instruction at a time, or GO to the user program
from active background mode.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
262
Freescale Semiconductor
•
Non-intrusive commands can be executed at any time even while the user’s program is running.
Non-intrusive commands allow a user to read or write MCU memory locations or access status and
control registers within the background debug controller.
Typically, a relatively simple interface pod is used to translate commands from a host computer into
commands for the custom serial interface to the single-wire background debug system. Depending on the
development tool vendor, this interface pod may use a standard RS-232 serial port, a parallel printer port,
or some other type of communications such as a universal serial bus (USB) to communicate between the
host PC and the pod. The pod typically connects to the target system with ground, the BKGD pin, RESET,
and sometimes VDD. An open-drain connection to reset allows the host to force a target system reset,
which is useful to regain control of a lost target system or to control startup of a target system before the
on-chip nonvolatile memory has been programmed. Sometimes VDD can be used to allow the pod to use
power from the target system to avoid the need for a separate power supply. However, if the pod is powered
separately, it can be connected to a running target system without forcing a target system reset or otherwise
disturbing the running application program.
BKGD 1
2 GND
NO CONNECT 3
4 RESET
NO CONNECT 5
6 VDD
Figure 17-1. BDM Tool Connector
17.2.1
BKGD Pin Description
BKGD is the single-wire background debug interface pin. The primary function of this pin is for
bidirectional serial communication of active background mode commands and data. During reset, this pin
is used to select between starting in active background mode or starting the user’s application program.
This pin is also used to request a timed sync response pulse to allow a host development tool to determine
the correct clock frequency for background debug serial communications.
BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of
microcontrollers. This protocol assumes the host knows the communication clock rate that is determined
by the target BDC clock rate. All communication is initiated and controlled by the host that drives a
high-to-low edge to signal the beginning of each bit time. Commands and data are sent most significant
bit first (MSB first). For a detailed description of the communications protocol, refer to Section 17.2.2,
“Communication Details.”
If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC
command may be sent to the target MCU to request a timed sync response signal from which the host can
determine the correct communication speed.
BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required.
Unlike typical open-drain pins, the external RC time constant on this pin, which is influenced by external
capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively
driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts.
Refer to Section 17.2.2, “Communication Details,” for more detail.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
263
When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD
chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU
into active background mode after reset. The specific conditions for forcing active background depend
upon the HCS08 derivative (refer to the introduction to this Development Support section). It is not
necessary to reset the target MCU to communicate with it through the background debug interface.
17.2.2
Communication Details
The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to
indicate the start of each bit time. The external controller provides this falling edge whether data is
transmitted or received.
BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data
is transferred MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if
512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress
when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU
system.
The custom serial protocol requires the debug pod to know the target BDC communication clock speed.
The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the
BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source.
The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams
show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but
asynchronous to the external host. The internal BDC clock signal is shown for reference in counting
cycles.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
264
Freescale Semiconductor
Figure 17-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU.
The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge
to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target
senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin
during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD
pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal
during this period.
BDC CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
10 CYCLES
SYNCHRONIZATION
UNCERTAINTY
EARLIEST START
OF NEXT BIT
TARGET SENSES BIT LEVEL
PERCEIVED START
OF BIT TIME
Figure 17-2. BDC Host-to-Target Serial Bit Timing
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
265
Figure 17-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long
enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive
before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the
bit time. The host should sample the bit level about 10 cycles after it started the bit time.
BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
TARGET MCU
SPEEDUP PULSE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
PERCEIVED START
OF BIT TIME
R-C RISE
BKGD PIN
10 CYCLES
10 CYCLES
EARLIEST START
OF NEXT BIT
HOST SAMPLES BKGD PIN
Figure 17-3. BDC Target-to-Host Serial Bit Timing (Logic 1)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
266
Freescale Semiconductor
Figure 17-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the
target HCS08 finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low
for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit
level about 10 cycles after starting the bit time.
BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
HIGH-IMPEDANCE
SPEEDUP
PULSE
TARGET MCU
DRIVE AND
SPEED-UP PULSE
PERCEIVED START
OF BIT TIME
BKGD PIN
10 CYCLES
10 CYCLES
EARLIEST START
OF NEXT BIT
HOST SAMPLES BKGD PIN
Figure 17-4. BDM Target-to-Host Serial Bit Timing (Logic 0)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
267
17.2.3
BDC Commands
BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All
commands and data are sent MSB-first using a custom BDC communications protocol. Active background
mode commands require that the target MCU is currently in the active background mode while
non-intrusive commands may be issued at any time whether the target MCU is in active background mode
or running a user application program.
Table 17-1 shows all HCS08 BDC commands, a shorthand description of their coding structure, and the
meaning of each command.
Coding Structure Nomenclature
This nomenclature is used in Table 17-1 to describe the coding structure of the BDC commands.
Commands begin with an 8-bit hexadecimal command code in the host-to-target
direction (most significant bit first)
/ = separates parts of the command
d = delay 16 target BDC clock cycles
AAAA = a 16-bit address in the host-to-target direction
RD = 8 bits of read data in the target-to-host direction
WD = 8 bits of write data in the host-to-target direction
RD16 = 16 bits of read data in the target-to-host direction
WD16 = 16 bits of write data in the host-to-target direction
SS = the contents of BDCSCR in the target-to-host direction (STATUS)
CC = 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL)
RBKP = 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint
register)
WBKP = 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
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Freescale Semiconductor
Table 17-1. BDC Command Summary
Command
Mnemonic
1
Active BDM/
Non-intrusive
Coding
Structure
Description
SYNC
Non-intrusive
n/a1
Request a timed reference pulse to determine
target BDC communication speed
ACK_ENABLE
Non-intrusive
D5/d
Enable acknowledge protocol. Refer to
Freescale document order no. HCS08RMv1/D.
ACK_DISABLE
Non-intrusive
D6/d
Disable acknowledge protocol. Refer to
Freescale document order no. HCS08RMv1/D.
BACKGROUND
Non-intrusive
90/d
Enter active background mode if enabled
(ignore if ENBDM bit equals 0)
READ_STATUS
Non-intrusive
E4/SS
Read BDC status from BDCSCR
WRITE_CONTROL
Non-intrusive
C4/CC
Write BDC controls in BDCSCR
READ_BYTE
Non-intrusive
E0/AAAA/d/RD
Read a byte from target memory
READ_BYTE_WS
Non-intrusive
E1/AAAA/d/SS/RD
Read a byte and report status
READ_LAST
Non-intrusive
E8/SS/RD
Re-read byte from address just read and report
status
WRITE_BYTE
Non-intrusive
C0/AAAA/WD/d
Write a byte to target memory
WRITE_BYTE_WS
Non-intrusive
C1/AAAA/WD/d/SS
Write a byte and report status
READ_BKPT
Non-intrusive
E2/RBKP
Read BDCBKPT breakpoint register
WRITE_BKPT
Non-intrusive
C2/WBKP
Write BDCBKPT breakpoint register
GO
Active BDM
08/d
Go to execute the user application program
starting at the address currently in the PC
TRACE1
Active BDM
10/d
Trace 1 user instruction at the address in the
PC, then return to active background mode
TAGGO
Active BDM
18/d
Same as GO but enable external tagging
(HCS08 devices have no external tagging pin)
READ_A
Active BDM
68/d/RD
Read accumulator (A)
READ_CCR
Active BDM
69/d/RD
Read condition code register (CCR)
READ_PC
Active BDM
6B/d/RD16
Read program counter (PC)
READ_HX
Active BDM
6C/d/RD16
Read H and X register pair (H:X)
READ_SP
Active BDM
6F/d/RD16
Read stack pointer (SP)
READ_NEXT
Active BDM
70/d/RD
Increment H:X by one then read memory byte
located at H:X
READ_NEXT_WS
Active BDM
71/d/SS/RD
Increment H:X by one then read memory byte
located at H:X. Report status and data.
WRITE_A
Active BDM
48/WD/d
Write accumulator (A)
WRITE_CCR
Active BDM
49/WD/d
Write condition code register (CCR)
WRITE_PC
Active BDM
4B/WD16/d
Write program counter (PC)
WRITE_HX
Active BDM
4C/WD16/d
Write H and X register pair (H:X)
WRITE_SP
Active BDM
4F/WD16/d
Write stack pointer (SP)
WRITE_NEXT
Active BDM
50/WD/d
Increment H:X by one, then write memory byte
located at H:X
WRITE_NEXT_WS
Active BDM
51/WD/d/SS
Increment H:X by one, then write memory byte
located at H:X. Also report status.
The SYNC command is a special operation that does not have a command code.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
269
The SYNC command is unlike other BDC commands because the host does not necessarily know the
correct communications speed to use for BDC communications until after it has analyzed the response to
the SYNC command.
To issue a SYNC command, the host:
• Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest
clock is normally the reference oscillator/64 or the self-clocked rate/64.)
• Drives BKGD high for a brief speedup pulse to get a fast rise time (This speedup pulse is typically
one cycle of the fastest clock in the system.)
• Removes all drive to the BKGD pin so it reverts to high impedance
• Monitors the BKGD pin for the sync response pulse
The target, upon detecting the SYNC request from the host (which is a much longer low time than would
ever occur during normal BDC communications):
• Waits for BKGD to return to a logic high
• Delays 16 cycles to allow the host to stop driving the high speedup pulse
• Drives BKGD low for 128 BDC clock cycles
• Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD
• Removes all drive to the BKGD pin so it reverts to high impedance
The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for
subsequent BDC communications. Typically, the host can determine the correct communication speed
within a few percent of the actual target speed and the communication protocol can easily tolerate speed
errors of several percent.
17.2.4
BDC Hardware Breakpoint
The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a
16-bit match value in the BDCBKPT register. This breakpoint can generate a forced breakpoint or a tagged
breakpoint. A forced breakpoint causes the CPU to enter active background mode at the first instruction
boundary following any access to the breakpoint address. The tagged breakpoint causes the instruction
opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather
than executing that instruction if and when it reaches the end of the instruction queue. This implies that
tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can
be set at any address.
The breakpoint enable (BKPTEN) control bit in the BDC status and control register (BDCSCR) is used to
enable the breakpoint logic (BKPTEN = 1). When BKPTEN = 0, its default value after reset, the
breakpoint logic is disabled and no BDC breakpoints are requested regardless of the values in other BDC
breakpoint registers and control bits. The force/tag select (FTS) control bit in BDCSCR is used to select
forced (FTS = 1) or tagged (FTS = 0) type breakpoints.
The on-chip debug module (DBG) includes circuitry for two additional hardware breakpoints that are more
flexible than the simple breakpoint in the BDC module.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
270
Freescale Semiconductor
17.3
On-Chip Debug System (DBG)
Because HCS08 devices do not have external address and data buses, the most important functions of an
in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage
FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture
bus information and what information to capture. The system relies on the single-wire background debug
system to access debug control registers and to read results out of the eight stage FIFO.
The debug module includes control and status registers that are accessible in the user’s memory map.
These registers are located in the high register space to avoid using valuable direct page memory space.
Most of the debug module’s functions are used during development, and user programs rarely access any
of the control and status registers for the debug module. The one exception is that the debug system can
provide the means to implement a form of ROM patching. This topic is discussed in greater detail in
Section 17.3.6, “Hardware Breakpoints.”
17.3.1
Comparators A and B
Two 16-bit comparators (A and B) can optionally be qualified with the R/W signal and an opcode tracking
circuit. Separate control bits allow you to ignore R/W for each comparator. The opcode tracking circuitry
optionally allows you to specify that a trigger will occur only if the opcode at the specified address is
actually executed as opposed to only being read from memory into the instruction queue. The comparators
are also capable of magnitude comparisons to support the inside range and outside range trigger modes.
Comparators are disabled temporarily during all BDC accesses.
The A comparator is always associated with the 16-bit CPU address. The B comparator compares to the
CPU address or the 8-bit CPU data bus, depending on the trigger mode selected. Because the CPU data
bus is separated into a read data bus and a write data bus, the RWAEN and RWA control bits have an
additional purpose, in full address plus data comparisons they are used to decide which of these buses to
use in the comparator B data bus comparisons. If RWAEN = 1 (enabled) and RWA = 0 (write), the CPU’s
write data bus is used. Otherwise, the CPU’s read data bus is used.
The currently selected trigger mode determines what the debugger logic does when a comparator detects
a qualified match condition. A match can cause:
• Generation of a breakpoint to the CPU
• Storage of data bus values into the FIFO
• Starting to store change-of-flow addresses into the FIFO (begin type trace)
• Stopping the storage of change-of-flow addresses into the FIFO (end type trace)
17.3.2
Bus Capture Information and FIFO Operation
The usual way to use the FIFO is to setup the trigger mode and other control options, then arm the
debugger. When the FIFO has filled or the debugger has stopped storing data into the FIFO, you would
read the information out of it in the order it was stored into the FIFO. Status bits indicate the number of
words of valid information that are in the FIFO as data is stored into it. If a trace run is manually halted by
writing 0 to ARM before the FIFO is full (CNT = 1:0:0:0), the information is shifted by one position and
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
271
the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry
in the FIFO.
In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In
these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading
DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information
is available at the FIFO data port. In the event-only trigger modes (see Section 17.3.5, “Trigger Modes”),
8-bit data information is stored into the FIFO. In these cases, the high-order half of the FIFO (DBGFH) is
not used and data is read out of the FIFO by simply reading DBGFL. Each time DBGFL is read, the FIFO
is shifted so the next data value is available through the FIFO data port at DBGFL.
In trigger modes where the FIFO is storing change-of-flow addresses, there is a delay between CPU
addresses and the input side of the FIFO. Because of this delay, if the trigger event itself is a
change-of-flow address or a change-of-flow address appears during the next two bus cycles after a trigger
event starts the FIFO, it will not be saved into the FIFO. In the case of an end-trace, if the trigger event is
a change-of-flow, it will be saved as the last change-of-flow entry for that debug run.
The FIFO can also be used to generate a profile of executed instruction addresses when the debugger is
not armed. When ARM = 0, reading DBGFL causes the address of the most-recently fetched opcode to be
saved in the FIFO. To use the profiling feature, a host debugger would read addresses out of the FIFO by
reading DBGFH then DBGFL at regular periodic intervals. The first eight values would be discarded
because they correspond to the eight DBGFL reads needed to initially fill the FIFO. Additional periodic
reads of DBGFH and DBGFL return delayed information about executed instructions so the host debugger
can develop a profile of executed instruction addresses.
17.3.3
Change-of-Flow Information
To minimize the amount of information stored in the FIFO, only information related to instructions that
cause a change to the normal sequential execution of instructions is stored. With knowledge of the source
and object code program stored in the target system, an external debugger system can reconstruct the path
of execution through many instructions from the change-of-flow information stored in the FIFO.
For conditional branch instructions where the branch is taken (branch condition was true), the source
address is stored (the address of the conditional branch opcode). Because BRA and BRN instructions are
not conditional, these events do not cause change-of-flow information to be stored in the FIFO.
Indirect JMP and JSR instructions use the current contents of the H:X index register pair to determine the
destination address, so the debug system stores the run-time destination address for any indirect JMP or
JSR. For interrupts, RTI, or RTS, the destination address is stored in the FIFO as change-of-flow
information.
17.3.4
Tag vs. Force Breakpoints and Triggers
Tagging is a term that refers to identifying an instruction opcode as it is fetched into the instruction queue,
but not taking any other action until and unless that instruction is actually executed by the CPU. This
distinction is important because any change-of-flow from a jump, branch, subroutine call, or interrupt
causes some instructions that have been fetched into the instruction queue to be thrown away without being
executed.
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Freescale Semiconductor
A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint
request. The usual action in response to a breakpoint is to go to active background mode rather than
continuing to the next instruction in the user application program.
The tag vs. force terminology is used in two contexts within the debug module. The first context refers to
breakpoint requests from the debug module to the CPU. The second refers to match signals from the
comparators to the debugger control logic. When a tag-type break request is sent to the CPU, a signal is
entered into the instruction queue along with the opcode so that if/when this opcode ever executes, the
CPU will effectively replace the tagged opcode with a BGND opcode so the CPU goes to active
background mode rather than executing the tagged instruction. When the TRGSEL control bit in the DBGT
register is set to select tag-type operation, the output from comparator A or B is qualified by a block of
logic in the debug module that tracks opcodes and only produces a trigger to the debugger if the opcode at
the compare address is actually executed. There is separate opcode tracking logic for each comparator so
more than one compare event can be tracked through the instruction queue at a time.
17.3.5
Trigger Modes
The trigger mode controls the overall behavior of a debug run. The 4-bit TRG field in the DBGT register
selects one of nine trigger modes. When TRGSEL = 1 in the DBGT register, the output of the comparator
must propagate through an opcode tracking circuit before triggering FIFO actions. The BEGIN bit in
DBGT chooses whether the FIFO begins storing data when the qualified trigger is detected (begin trace),
or the FIFO stores data in a circular fashion from the time it is armed until the qualified trigger is detected
(end trigger).
A debug run is started by writing a 1 to the ARM bit in the DBGC register, which sets the ARMF flag and
clears the AF and BF flags and the CNT bits in DBGS. A begin-trace debug run ends when the FIFO gets
full. An end-trace run ends when the selected trigger event occurs. Any debug run can be stopped manually
by writing a 0 to ARM or DBGEN in DBGC.
In all trigger modes except event-only modes, the FIFO stores change-of-flow addresses. In event-only
trigger modes, the FIFO stores data in the low-order eight bits of the FIFO.
The BEGIN control bit is ignored in event-only trigger modes and all such debug runs are begin type
traces. When TRGSEL = 1 to select opcode fetch triggers, it is not necessary to use R/W in comparisons
because opcode tags would only apply to opcode fetches that are always read cycles. It would also be
unusual to specify TRGSEL = 1 while using a full mode trigger because the opcode value is normally
known at a particular address.
The following trigger mode descriptions only state the primary comparator conditions that lead to a trigger.
Either comparator can usually be further qualified with R/W by setting RWAEN (RWBEN) and the
corresponding RWA (RWB) value to be matched against R/W. The signal from the comparator with
optional R/W qualification is used to request a CPU breakpoint if BRKEN = 1 and TAG determines
whether the CPU request will be a tag request or a force request.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
273
A-Only — Trigger when the address matches the value in comparator A
A OR B — Trigger when the address matches either the value in comparator A or the value in
comparator B
A Then B — Trigger when the address matches the value in comparator B but only after the address for
another cycle matched the value in comparator A. There can be any number of cycles after the A match
and before the B match.
A AND B Data (Full Mode) — This is called a full mode because address, data, and R/W (optionally)
must match within the same bus cycle to cause a trigger event. Comparator A checks address, the low byte
of comparator B checks data, and R/W is checked against RWA if RWAEN = 1. The high-order half of
comparator B is not used.
In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you
do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the
CPU breakpoint is issued when the comparator A address matches.
A AND NOT B Data (Full Mode) — Address must match comparator A, data must not match the low
half of comparator B, and R/W must match RWA if RWAEN = 1. All three conditions must be met within
the same bus cycle to cause a trigger.
In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you
do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the
CPU breakpoint is issued when the comparator A address matches.
Event-Only B (Store Data) — Trigger events occur each time the address matches the value in
comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the
FIFO becomes full.
A Then Event-Only B (Store Data) — After the address has matched the value in comparator A, a trigger
event occurs each time the address matches the value in comparator B. Trigger events cause the data to be
captured into the FIFO. The debug run ends when the FIFO becomes full.
Inside Range (A Address B) — A trigger occurs when the address is greater than or equal to the value
in comparator A and less than or equal to the value in comparator B at the same time.
Outside Range (Address < A or Address > B) — A trigger occurs when the address is either less than
the value in comparator A or greater than the value in comparator B.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
274
Freescale Semiconductor
17.3.6
Hardware Breakpoints
The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions
described in Section 17.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the
CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a
force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction
queue. If a tagged opcode reaches the end of the pipe, the CPU executes a BGND instruction to go to active
background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to
finish the current instruction and then go to active background mode.
If the background mode has not been enabled (ENBDM = 1) by a serial WRITE_CONTROL command
through the BKGD pin, the CPU will execute an SWI instruction instead of going to active background
mode.
17.4
Register Definition
This section contains the descriptions of the BDC and DBG registers and control bits.
Refer to the high-page register summary in the device overview chapter of this data sheet for the absolute
address assignments for all DBG registers. This section refers to registers and control bits only by their
names. A Freescale-provided equate or header file is used to translate these names into the appropriate
absolute addresses.
17.4.1
BDC Registers and Control Bits
The BDC has two registers:
• The BDC status and control register (BDCSCR) is an 8-bit register containing control and status
bits for the background debug controller.
• The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address.
These registers are accessed with dedicated serial BDC commands and are not located in the memory
space of the target MCU (so they do not have addresses and cannot be accessed by user programs).
Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written
at any time. For example, the ENBDM control bit may not be written while the MCU is in active
background mode. (This prevents the ambiguous condition of the control bit forbidding active background
mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS,
WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial
BDC command. The clock switch (CLKSW) control bit may be read or written at any time.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
275
17.4.1.1
BDC Status and Control Register (BDCSCR)
This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL)
but is not accessible to user programs because it is not located in the normal memory map of the MCU.
7
R
6
5
4
3
BKPTEN
FTS
CLKSW
BDMACT
ENBDM
2
1
0
WS
WSF
DVF
W
Normal
Reset
0
0
0
0
0
0
0
0
Reset in
Active BDM:
1
1
0
0
1
0
0
0
= Unimplemented or Reserved
Figure 17-5. BDC Status and Control Register (BDCSCR)
Table 17-2. BDCSCR Register Field Descriptions
Field
Description
7
ENBDM
Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly
after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal
reset clears it.
0 BDM cannot be made active (non-intrusive commands still allowed)
1 BDM can be made active to allow active background mode commands
6
BDMACT
Background Mode Active Status — This is a read-only status bit.
0 BDM not active (user application program running)
1 BDM active and waiting for serial commands
5
BKPTEN
BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select)
control bit and BDCBKPT match register are ignored.
0 BDC breakpoint disabled
1 BDC breakpoint enabled
4
FTS
Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the
BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register
causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue,
the CPU enters active background mode rather than executing the tagged opcode.
0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that
instruction
1 Breakpoint match forces active background mode at next instruction boundary (address need not be an
opcode)
3
CLKSW
Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC clock
source.
0 Alternate BDC clock source
1 MCU bus clock
MC9S08SG8 MCU Series Data Sheet, Rev. 8
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Freescale Semiconductor
Table 17-2. BDCSCR Register Field Descriptions (continued)
Field
Description
2
WS
Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function.
However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active
background mode where all BDC commands work. Whenever the host forces the target MCU into active
background mode, the host should issue a READ_STATUS command to check that BDMACT = 1 before
attempting other BDC commands.
0 Target CPU is running user application code or in active background mode (was not in wait or stop mode when
background became active)
1 Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or stop to
active background mode
1
WSF
Wait or Stop Failure Status — This status bit is set if a memory access command failed due to the target CPU
executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a
BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command
that failed, then return to the user program. (Typically, the host would restore CPU registers and stack values and
re-execute the wait or stop instruction.)
0 Memory access did not conflict with a wait or stop instruction
1 Memory access command failed because the CPU entered wait or stop mode
0
DVF
Data Valid Failure Status — This status bit is not used in the MC9S08SG8 because it does not have any slow
access memory.
0 Memory access did not conflict with a slow memory access
1 Memory access command failed because CPU was not finished with a slow memory access
17.4.1.2
BDC Breakpoint Match Register (BDCBKPT)
This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS
control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC
commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is
not accessible to user programs because it is not located in the normal memory map of the MCU.
Breakpoints are normally set while the target MCU is in active background mode before running the user
application program. For additional information about setup and use of the hardware breakpoint logic in
the BDC, refer to Section 17.2.4, “BDC Hardware Breakpoint.”
17.4.2
System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial background mode command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
277
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
BDFR1
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
1
BDFR is writable only through serial background mode debug commands, not from user programs.
Figure 17-6. System Background Debug Force Reset Register (SBDFR)
Table 17-3. SBDFR Register Field Description
Field
Description
0
BDFR
Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.
17.4.3
DBG Registers and Control Bits
The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control
and status registers. These registers are located in the high register space of the normal memory map so
they are accessible to normal application programs. These registers are rarely if ever accessed by normal
user application programs with the possible exception of a ROM patching mechanism that uses the
breakpoint logic.
17.4.3.1
Debug Comparator A High Register (DBGCAH)
This register contains compare value bits for the high-order eight bits of comparator A. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.2
Debug Comparator A Low Register (DBGCAL)
This register contains compare value bits for the low-order eight bits of comparator A. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.3
Debug Comparator B High Register (DBGCBH)
This register contains compare value bits for the high-order eight bits of comparator B. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.4
Debug Comparator B Low Register (DBGCBL)
This register contains compare value bits for the low-order eight bits of comparator B. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
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Freescale Semiconductor
17.4.3.5
Debug FIFO High Register (DBGFH)
This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have
no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte
of each FIFO word, so this register is not used and will read 0x00.
Reading DBGFH does not cause the FIFO to shift to the next word. When reading 16-bit words out of the
FIFO, read DBGFH before reading DBGFL because reading DBGFL causes the FIFO to advance to the
next word of information.
17.4.3.6
Debug FIFO Low Register (DBGFL)
This register provides read-only access to the low-order eight bits of the FIFO. Writes to this register have
no meaning or effect.
Reading DBGFL causes the FIFO to shift to the next available word of information. When the debug
module is operating in event-only modes, only 8-bit data is stored into the FIFO (high-order half of each
FIFO word is unused). When reading 8-bit words out of the FIFO, simply read DBGFL repeatedly to get
successive bytes of data from the FIFO. It isn’t necessary to read DBGFH in this case.
Do not attempt to read data from the FIFO while it is still armed (after arming but before the FIFO is filled
or ARMF is cleared) because the FIFO is prevented from advancing during reads of DBGFL. This can
interfere with normal sequencing of reads from the FIFO.
Reading DBGFL while the debugger is not armed causes the address of the most-recently fetched opcode
to be stored to the last location in the FIFO. By reading DBGFH then DBGFL periodically, external host
software can develop a profile of program execution. After eight reads from the FIFO, the ninth read will
return the information that was stored as a result of the first read. To use the profiling feature, read the FIFO
eight times without using the data to prime the sequence and then begin using the data to get a delayed
picture of what addresses were being executed. The information stored into the FIFO on reads of DBGFL
(while the FIFO is not armed) is the address of the most-recently fetched opcode.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
279
17.4.3.7
Debug Control Register (DBGC)
This register can be read or written at any time.
7
6
5
4
3
2
1
0
DBGEN
ARM
TAG
BRKEN
RWA
RWAEN
RWB
RWBEN
0
0
0
0
0
0
0
0
R
W
Reset
Figure 17-7. Debug Control Register (DBGC)
Table 17-4. DBGC Register Field Descriptions
Field
Description
7
DBGEN
Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
0 DBG disabled
1 DBG enabled
6
ARM
Arm Control — Controls whether the debugger is comparing and storing information in the FIFO. A write is used
to set this bit (and ARMF) and completion of a debug run automatically clears it. Any debug run can be manually
stopped by writing 0 to ARM or to DBGEN.
0 Debugger not armed
1 Debugger armed
5
TAG
Tag/Force Select — Controls whether break requests to the CPU will be tag or force type requests. If
BRKEN = 0, this bit has no meaning or effect.
0 CPU breaks requested as force type requests
1 CPU breaks requested as tag type requests
4
BRKEN
Break Enable — Controls whether a trigger event will generate a break request to the CPU. Trigger events can
cause information to be stored in the FIFO without generating a break request to the CPU. For an end trace, CPU
break requests are issued to the CPU when the comparator(s) and R/W meet the trigger requirements. For a
begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL does not affect the timing of
CPU break requests.
0 CPU break requests not enabled
1 Triggers cause a break request to the CPU
3
RWA
R/W Comparison Value for Comparator A — When RWAEN = 1, this bit determines whether a read or a write
access qualifies comparator A. When RWAEN = 0, RWA and the R/W signal do not affect comparator A.
0 Comparator A can only match on a write cycle
1 Comparator A can only match on a read cycle
2
RWAEN
Enable R/W for Comparator A — Controls whether the level of R/W is considered for a comparator A match.
0 R/W is not used in comparison A
1 R/W is used in comparison A
1
RWB
R/W Comparison Value for Comparator B — When RWBEN = 1, this bit determines whether a read or a write
access qualifies comparator B. When RWBEN = 0, RWB and the R/W signal do not affect comparator B.
0 Comparator B can match only on a write cycle
1 Comparator B can match only on a read cycle
0
RWBEN
Enable R/W for Comparator B — Controls whether the level of R/W is considered for a comparator B match.
0 R/W is not used in comparison B
1 R/W is used in comparison B
MC9S08SG8 MCU Series Data Sheet, Rev. 8
280
Freescale Semiconductor
17.4.3.8
Debug Trigger Register (DBGT)
This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired
to 0s.
7
6
TRGSEL
BEGIN
0
0
R
5
4
0
0
3
2
1
0
TRG3
TRG2
TRG1
TRG0
0
0
0
0
W
Reset
0
0
= Unimplemented or Reserved
Figure 17-8. Debug Trigger Register (DBGT)
Table 17-5. DBGT Register Field Descriptions
Field
Description
7
TRGSEL
Trigger Type — Controls whether the match outputs from comparators A and B are qualified with the opcode
tracking logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate
through the opcode tracking logic and a trigger event is only signalled to the FIFO logic if the opcode at the match
address is actually executed.
0 Trigger on access to compare address (force)
1 Trigger if opcode at compare address is executed (tag)
6
BEGIN
Begin/End Trigger Select — Controls whether the FIFO starts filling at a trigger or fills in a circular manner until
a trigger ends the capture of information. In event-only trigger modes, this bit is ignored and all debug runs are
assumed to be begin traces.
0 Data stored in FIFO until trigger (end trace)
1 Trigger initiates data storage (begin trace)
3:0
TRG[3:0]
Select Trigger Mode — Selects one of nine triggering modes, as described below.
0000 A-only
0001 A OR B
0010 A Then B
0011 Event-only B (store data)
0100 A then event-only B (store data)
0101 A AND B data (full mode)
0110 A AND NOT B data (full mode)
0111 Inside range: A address B
1000 Outside range: address < A or address > B
1001 – 1111 (No trigger)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
281
17.4.3.9
Debug Status Register (DBGS)
This is a read-only status register.
R
7
6
5
4
3
2
1
0
AF
BF
ARMF
0
CNT3
CNT2
CNT1
CNT0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 17-9. Debug Status Register (DBGS)
Table 17-6. DBGS Register Field Descriptions
Field
Description
7
AF
Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A
condition was met since arming.
0 Comparator A has not matched
1 Comparator A match
6
BF
Trigger Match B Flag — BF is cleared at the start of a debug run and indicates whether a trigger match B
condition was met since arming.
0 Comparator B has not matched
1 Comparator B match
5
ARMF
Arm Flag — While DBGEN = 1, this status bit is a read-only image of ARM in DBGC. This bit is set by writing 1
to the ARM control bit in DBGC (while DBGEN = 1) and is automatically cleared at the end of a debug run. A
debug run is completed when the FIFO is full (begin trace) or when a trigger event is detected (end trace). A
debug run can also be ended manually by writing 0 to ARM or DBGEN in DBGC.
0 Debugger not armed
1 Debugger armed
3:0
CNT[3:0]
FIFO Valid Count — These bits are cleared at the start of a debug run and indicate the number of words of valid
data in the FIFO at the end of a debug run. The value in CNT does not decrement as data is read out of the FIFO.
The external debug host is responsible for keeping track of the count as information is read out of the FIFO.
0000 Number of valid words in FIFO = No valid data
0001 Number of valid words in FIFO = 1
0010 Number of valid words in FIFO = 2
0011 Number of valid words in FIFO = 3
0100 Number of valid words in FIFO = 4
0101 Number of valid words in FIFO = 5
0110 Number of valid words in FIFO = 6
0111 Number of valid words in FIFO = 7
1000 Number of valid words in FIFO = 8
MC9S08SG8 MCU Series Data Sheet, Rev. 8
282
Freescale Semiconductor
Appendix A
Electrical Characteristics
A.1
Introduction
This section contains electrical and timing specifications for the MC9S08SG8 Series of microcontrollers
available at the time of publication.
The MC9S08SG8 Series includes both:
• Standard (STD) – devices that are standard-temperature rated.
• AEC Grade 0 – devices that are high-temperature rated.
A.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table A-1. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
A.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table A-2 may affect device reliability or cause
permanent damage to the device. For functional operating conditions, refer to the remaining tables in this
section.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
283
Appendix A Electrical Characteristics
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable
pull-up resistor associated with the pin is enabled.
Table A-2. Absolute Maximum Ratings
Temp Rated1
Rating
Symbol
Value
Unit
Standard
AEC
Grade 0
Supply voltage
VDD
–0.3 to +5.8
V
x
x
Maximum current into VDD
IDD
120
mA
x
x
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
x
x
Instantaneous maximum current
Single pin limit (applies to all port pins)2, 3, 4
ID
25
mA
x
x
Tstg
–55 to 150
C
x
x
Storage temperature range
1
Electrical characteristics only apply to the temperature rated devices marked with x.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values.
3 All functional non-supply pins are internally clamped to V
SS and VDD.
4 Power supply must maintain regulation within operating V
DD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or
if the clock rate is very low (which would reduce overall power consumption).
2
MC9S08SG8 MCU Series Data Sheet, Rev. 8
284
Freescale Semiconductor
Appendix A Electrical Characteristics
A.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the
MCU design. To take PI/O into account in power calculations, determine the difference between actual pin
voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high
pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table A-3. Thermal Characteristics
Temp Rated1
Num
C
1
—
Rating
Symbol
Value
Operating temperature range
(packaged)
V
M
–40 to 85
–40 to 125
4
x
x
C
TJ
95
x
V
115
x
M
135
x
W
155
Thermal resistance
Single-layer board
x
Airflow at
200 ft/min
Natural
Convection
131
153
16-pin TSSOP
115
135
20-pin TSSOP
95
115
Airflow at
200 ft/min
Natural
Convection
95
102
16-pin TSSOP
86
94
20-pin TSSOP
69
76
8-pin NB SOIC
D
x
–40 to 150
2,3
3
AEC
Grade 0
x
Maximum junction temperature
C
D
C
–40 to 105
TA
W
D
Standar
d
TL to TH
C
2
Unit
JA
resistance2,3
Thermal
Four-layer board
8-pin NB SOIC
JA
x
C/W
x
x
x
x
C/W
x
x
x
1
Electrical characteristics only apply to the temperature rated devices marked with x.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature,
ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
3 Junction to Ambient Natural Convection
2
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
285
Appendix A Electrical Characteristics
The average chip-junction temperature (TJ) in C can be obtained from:
TJ = TA + (PD JA)
Eqn. A-1
where:
TA = Ambient temperature, C
JA = Package thermal resistance, junction-to-ambient, C/W
PD = Pint PI/O
Pint = IDD VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K (TJ + 273C)
Eqn. A-2
Solving Equation A-1 and Equation A-2 for K gives:
K = PD (TA + 273C) + JA (PD)2
Eqn. A-3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation A-1 and Equation A-2 iteratively for any value of TA.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
286
Freescale Semiconductor
Appendix A Electrical Characteristics
A.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the human body
model (HBM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-4. ESD and Latch-up Test Conditions
Model
Human
Body
Latch-up
Description
Symbol
Value
Unit
Series resistance
R1
1500
Storage capacitance
C
100
pF
Number of pulses per pin
—
3
Minimum input voltage limit
– 2.5
V
Maximum input voltage limit
7.5
V
Table A-5. ESD and Latch-Up Protection Characteristics
No.
1
Rating1
Symbol
Min
Max
Unit
1
Human body model (HBM)
VHBM
2000
—
V
2
Charge device model (CDM)
VCDM
500
—
V
3
Latch-up current at TA = 125C
ILAT
100
—
mA
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
287
Appendix A Electrical Characteristics
A.6
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table A-6. DC Characteristics
Temp Rated2
Num C
1
2
3
4
5
Characteristic
— Operating voltage
Symbol
Condition
Min
Typ1
Max
Unit
VDD
—
2.7
—
5.5
V
AEC
Stand
Grade
ard
0
x
x
C
All I/O pins,
5 V, ILoad = –4 mA
VDD – 1.5
—
—
x
x
P
low-drive strength
5 V, ILoad = –2 mA
VDD – 0.8
—
—
x
x
C Output high
VOH
C voltage
P
All I/O pins,
C
high-drive strength
C
Max total IOH for
all ports
Output high
current
IOHT
3 V, ILoad = –1 mA
VDD – 0.8
—
—
x
x
5 V, ILoad = –20 mA
VDD – 1.5
—
—
x
x
5 V, ILoad = –10 mA
VDD – 0.8
—
—
x
x
3 V, ILoad = –5 mA
VDD – 0.8
—
—
x
x
VOUT < VDD
0
—
–100
–50
V
mA
x
x
C
All I/O pins
5 V, ILoad = 4 mA
—
—
1.5
x
x
P
low-drive strength
5 V, ILoad = 2 mA
—
—
0.8
x
x
C Output low
VOL
C voltage
P
All I/O pins
C
high-drive strength
C
Output low
current
Max total IOL for
all ports
IOLT
3 V, ILoad = 1 mA
—
—
0.8
x
x
5 V, ILoad = 20 mA
—
—
1.5
V
x
x
5 V, ILoad = 10 mA
—
—
0.8
x
x
3 V, ILoad = 5 mA
—
—
0.8
x
x
VOUT > VSS
0
—
100
mA
x
50
6
7
8
9
P Input high voltage; all digital inputs
VIH
C
P Input low voltage; all digital inputs
VIL
C
C Input hysteresis
Vhys
P Input leakage current (per pin)
IIn
P
Hi-Z (off-state) leakage current (per
pin)
input/output port pins
10
PTB6/SDA/XTAL, RESET
input/output port pins
IOZ
5V
0.65 x VDD
—
—
3V
0.7 x VDD
—
—
5V
—
—
0.35 x VDD
3V
—
—
0.35 x VDD
0.06 x VDD
VIn = VDD or VSS
temperature > 125 C
—
x
V
x
x
x
V
x
x
x
x
x
x
x
x
V
0.1
1
—
2
A
x
x
VIn = VDD or VSS,
—
0.1
1
A
x
VIn = VDD or VSS
—
0.2
2
A
x
VIn = VDD or VSS
temperature > 125 C
—
0.2
2
A
MC9S08SG8 MCU Series Data Sheet, Rev. 8
288
x
Freescale Semiconductor
x
Appendix A Electrical Characteristics
Table A-6. DC Characteristics (continued)
Temp Rated2
Num C
Min
Typ1
Max
Unit
17
37
52
k
x
x
17
37
52
k
x
x
VIN > VDD
0
—
2
mA
x
x
VIN < VSS
0
—
–0.2
mA
x
x
Total MCU limit,
includes
VIN > VDD
0
—
25
mA
x
x
sum of all stressed
pins
VIN < VSS
0
—
–5
mA
x
x
Characteristic
Symbol
Condition
AEC
Stand
Grade
ard
0
Pullup or Pulldown3 resistors; when
enabled
11
I/O pins RPU,RPD
P
4
C
D
RESET
RPU
DC injection current 5, 6, 7, 8
Single pin limit
IIC
12
13
D Input Capacitance, all pins
CIn
—
—
8
pF
x
x
14
D RAM retention voltage
VRAM
—
0.6
1.0
V
x
x
15
D POR re-arm voltage9
VPOR
0.9
1.4
2.0
V
x
x
tPOR
10
—
—
s
x
x
VLVD1
3.9
3.88
4.0
4.0
4.1
4.12
4.0
3.98
4.1
4.1
4.2
4.22
2.48
2.54
2.56
2.62
2.64
2.70
4.5
4.48
4.6
4.6
4.7
4.72
10
16
D POR re-arm time
17
Low-voltage
detection
P
threshold —
high range
18
19
20
21
22
VDD falling
VDD rising
Low-voltage detection threshold —
11 12
P low range ,
VDD falling
VDD rising
Low-voltage
warning
P
threshold —
high range 1
VDD falling
Low-voltage
warning
P
threshold —
high range 0
VDD falling
VLVD0
VLVW3
VDD rising
VLVW2
Low-voltage warning threshold —
low range 0
P
VDD falling
VDD rising
4.6
4.58
4.7
4.7
4.8
4.82
4.2
4.18
4.3
4.3
4.4
4.42
V
x
x
x
V
x
x
x
x
x
x
V
x
x
x
x
V
4.3
4.28
4.4
4.4
4.5
4.52
VLVW1
2.84
2.90
2.92
2.98
3.00
3.06
V
x
x
x
x
VLVW0
2.66
2.72
2.74
2.80
2.82
2.88
V
x
x
x
x
VDD rising
Low-voltage warning threshold
low range 1
P
VDD falling
VDD rising
.
x
x
x
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
289
Appendix A Electrical Characteristics
Table A-6. DC Characteristics (continued)
Temp Rated2
Num C
Characteristic
Low-voltage inhibit reset/recover
hysteresis
23
T
24
P Bandgap Voltage Reference13
Symbol
Vhys
VBG
Condition
Min
Typ1
Max
5V
—
100
—
3V
—
60
—
1.18
1.20
1.21
V
1.17
1.20
1.22
V
Unit
mV
AEC
Stand
Grade
ard
0
x
x
x
x
x
1
x
Typical values are measured at 25C. Characterized, not tested.
Electrical characteristics only apply to the temperature rated devices marked with x.
3
When a pin interrupt is configured to detect rising edges, pulldown resistors are used in place of pullup resistors.
4
The specified resistor value is the actual value internal to the device. The pullup value may measure higher when measured externally on
the pin.
5 Power supply must maintain regulation within operating V
DD range during instantaneous and operating maximum current conditions. If
positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply
going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk
when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall
power consumption).
6 All functional non-supply pins are internally clamped to V
SS and VDD.
7 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance
values for positive and negative clamp voltages, then use the larger of the two values.
8 The RESET pin does not have a clamp diode to V . Do not drive this pin above V .
DD
DD
9 Maximum is highest voltage that POR will occur.
10 Simulated, not tested
11 Device functionality is guaranteed between the LVD threshold VLVD0 and VDD Min.When VDD is below the minimum operating voltage
(VDD Min), the analog parameters for the IO pins, ACMP and ADC, are not guaranteed to meet data sheet performance parameters.
12 In addition to LVD, it is recommended to also use the LVW feature. LVW can trigger an interrupt and be used as an indicator to warn that the
VDD is dropping,so that the software can take actions accordingly before the VDD drops below VDD Min
13 Factory trimmed at V
DD = 5.0 V
2
MC9S08SG8 MCU Series Data Sheet, Rev. 8
290
Freescale Semiconductor
Appendix A Electrical Characteristics
2
1.0
150°C
25°C
–40°C
0.8
VOL (V)
VOL (V)
1.5
1
0.5
0
150°C
25°C
–40°C
Max 1.5V@20mA
Max 0.8V@5mA
0.6
0.4
0.2
0
5
10
15
IOL (mA)
a) VDD = 5V, High Drive
20
0
25
0
2
4
6
IOL (mA)
b) VDD = 3V, High Drive
8
10
Figure A-1. Typical VOL vs IOL, High Drive Strength
2
1.0
150°C
25°C
–40°C
0.8
VOL (V)
VOL (V)
1.5
1
0.5
0
150°C
25°C
–40°C
Max 1.5V@4mA
Max 0.8V@1mA
0.6
0.4
0.2
0
1
2
3
IOL (mA)
a) VDD = 5V, Low Drive
4
5
0
0
0.4
0.8
1.2
IOL (mA)
b) VDD = 3V, Low Drive
1.6
2.0
Figure A-2. Typical VOL vs IOL, Low Drive Strength
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
291
Appendix A Electrical Characteristics
1.0
2
150°C
25°C
–40°C
0.8
VDD – VOH (V)
VDD – VOH (V)
1.5
1
0.5
0
150°C
25°C
–40°C
Max 1.5V@ –20mA
Max 0.8V@ –5mA
0.6
0.4
0.2
0
–5
–10
–15
–20
IOH (mA)
a) VDD = 5V, High Drive
0
–25
0
–2
–4
–6
–8
IOH (mA)
b) VDD = 3V, High Drive
–10
Figure A-3. Typical VDD – VOH vs IOH, High Drive Strength
2
1.0
150°C
25°C
–40°C
0.8
VDD – VOH (V)
VDD – VOH (V)
1.5
1
0.5
0
150°C
25°C
–40°C
Max 1.5V@ –4mA
Max 0.8V@ –1mA
0.6
0.4
0.2
0
–1
–2
–3
IOH (mA)
a) VDD = 5V, Low Drive
–4
–5
0
0
–0.4
–0.8
–1.2
–1.6
IOH (mA)
b) VDD = 3V, Low Drive
–2.0
Figure A-4. Typical VDD – VOH vs IOH, Low Drive Strength
MC9S08SG8 MCU Series Data Sheet, Rev. 8
292
Freescale Semiconductor
Appendix A Electrical Characteristics
A.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table A-7. Supply Current Characteristics
Temp Rated3
Num
C
C
1
C
P
2
C
C
3
C
Parameter
Symbol
4
Run supply current measured at
(CPU clock = 4 MHz, fBus = 2
MHz)
3
Run supply current measured at
(CPU clock = 16 MHz, fBus = 8
MHz)
RIDD
RIDD
5
Run supply current measured at
(CPU clock = 32 MHz, fBus = 16
MHz)
RIDD
VDD
(V)
Typ1
5
1.1
Max2
Unit
1.5
3
1
1.5
5
3.9
5
3
3.9
5
5
7.25
7.7
3
7.15
7.6
mA
mA
mA
Standard
AEC
Grade 0
x
x
x
x
x
x
x
x
x
x
x
x
Stop3 mode supply current
4
C
–40 C (C & M suffix )
1.1
—
x
P
25 C (All parts)
1.5
—
x
P6
85 C (C suffix only )
9.0
26
P6
105 C (V suffix only)
20.6
60
x
P6
125 C (M suffix only)
45.2
130
x
C
–40 C (C & M suffix )
1.0
—
x
C
25 C (All parts)
1.4
—
x
C
85 C (C suffix only )
7.8
19
C
105 C (V suffix only)
18.2
45
x
C
125 C (M suffix only)
40.1
95
x
5
S3IDD
3
A
A
x
x
Stop2 mode supply current
5
C
–40 C (C & M suffix )
1.1
—
x
P
25 C (All parts)
1.4
—
x
P6
85 C (C suffix only )
6.8
22
P6
105 C (V suffix only)
15.2
50
x
P6
125 C (M suffix only)
32.7
99
x
C
–40 C (C & M suffix )
1.0
—
x
C
25 C (All parts)
1.3
—
x
C
85 C (C suffix only )
5.8
16
C
105 C (V suffix only)
13.1
36
x
C
125 C (M suffix only)
28.3
76
x
5
S2IDD
3
A
A
x
x
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
293
Appendix A Electrical Characteristics
Table A-7. Supply Current Characteristics (continued)
Temp Rated3
Num
6
C
C
Parameter
Symbol
RTC adder to stop2 or stop37
S23IDDR
TI
1
2
3
4
5
6
7
8
7
C
LVD adder to stop3 (LVDE = LVDSE
= 1)
S3IDDLVD
8
C
Adder to stop3 for oscillator
enabled8
(EREFSTEN =1)
S3IDDOS
C
VDD
(V)
Typ1
5
300
500
nA
x
3
300
500
nA
x
5
110
180
A
x
3
90
160
A
x
5,
3
5
8
A
Max2
Unit
Standard
AEC
Grade 0
x
x
Typical values are based on characterization data at 25C. See Figure A-5 through Figure A-7 for typical curves across
voltage/temperature.
Max values in this column apply for the full operating temperature range of the device unless otherwise noted.
Electrical characteristics only apply to the temperature rated devices marked with x.
All modules except ADC active, ICS configured for FBE, and does not include any dc loads on port pins.
All modules except ADC active, ICS configured for FEI, and does not include any dc loads on port pins.
Stop currents are tested in production for 25C on all parts. Tests at other temperatures depend upon the part number suffix
and maturity of the product. Freescale may eliminate a test insertion at a particular temperature from the production test flow
once sufficient data has been collected and is approved.
Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode.
Values given under the following conditions: low range operation (RANGE = 0) with a 32.768kHz crystal and low power mode
(HGO = 0).
10
FEI
FBELP
Run IDD (mA)
8
6
4
2
0
0 1 2
4
8
16
20
fbus (MHz)
Figure A-5. Typical Run IDD vs. Bus Frequency (VDD = 5V)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
294
Freescale Semiconductor
Appendix A Electrical Characteristics
5
Run IDD (mA)
4
3
2
1
0
–40
0
25
Temperature (°C)
85
105
125
150
Figure A-6. Typical Run IDD vs. Temperature (VDD = 5V; fbus = 8MHz)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
295
Appendix A Electrical Characteristics
100
STOP2
STOP3
90
80
70
60
50
STOP IDD (µA)
40
30
20
10
0
–40
0
25
Temperature (°C)
85
105
125
150
Figure A-7. Typical Stop IDD vs. Temperature (VDD = 5V)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
296
Freescale Semiconductor
Appendix A Electrical Characteristics
A.8
External Oscillator (XOSC) Characteristics
Table A-8. Oscillator Electrical Specifications (Temperature Range = –40 to 125C Ambient)
Temp Rated2
Nu
m
C
Rating
Symbol
Min
Typ
1
Max
Uni
t
Standard
AEC
Grade 0
Oscillator crystal or resonator (EREFS = 1,
ERCLKEN = 1)
Low range (RANGE = 0)
1
2
flo
32
—
38.4
kHz
x
x
fhi
1
—
5
MHz
x
x
High range (RANGE = 1, HGO = 1) FBELP
mode
fhi-hgo
1
—
16
MHz
x
x
High range (RANGE = 1, HGO = 0) FBELP
mode
fhi-lp
1
—
8
MHz
x
x
High range (RANGE = 1) FEE or FBE mode
C
—
3
Load capacitors
See crystal or resonator manufacturer’s
recommendation.
C1, C2
Feedback resistor
3
—
RF
Low range (32 kHz to 100 kHz)
x
x
x
x
x
x
x
x
x
x
—
10
—
—
1
—
—
0
—
—
100
—
—
0
—
8 MHz
—
0
0
x
x
MHz
—
0
10
x
x
MHz
—
0
20
x
x
—
200
—
x
x
CSTL-LP
—
400
—
x
x
CSTL-HGO
t
—
5
—
x
x
CSTH-LP
t
CSTH-HGO
—
20
—
x
x
fextal
0.03125
—
5
MHz
x
0
0
—
—
40
36
MHz
x
High range (1 MHz to 16 MHz)
M
Series resistor
Low range, low gain (RANGE = 0, HGO =
0)
Low range, high gain (RANGE = 0, HGO =
1)
4
— 0)
High range, low gain (RANGE = 1, HGO =
RS
k
High range, high gain (RANGE = 1, HGO
= 1)
Crystal start-up time
4
Low range, low gain (RANGE = 0, HGO =
t
0)
Low range, high gain (RANGE = 0, HGO = t
5
T
1)
High range, low gain (RANGE = 1, HGO =
0)5
High range, high gain (RANGE = 1, HGO
= 1)4
ms
Square wave input clock frequency (EREFS = 0,
ERCLKEN = 1)
6
T
FEE or FBE mode 2
FBELP mode
1
x
Typical data was characterized at 5.0 V, 25C or is recommended value.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
297
Appendix A Electrical Characteristics
2
Electrical characteristics only apply to the temperature rated devices marked with x.
The input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz.
4
This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve
specifications.
5
4 MHz crystal
3
MCU
EXTAL
XTAL
RF
C1
Crystal or Resonator
RS
C2
MC9S08SG8 MCU Series Data Sheet, Rev. 8
298
Freescale Semiconductor
Appendix A Electrical Characteristics
A.9
Internal Clock Source (ICS) Characteristics
Table A-9. ICS Frequency Specifications (Temperature Range = –40 to 125C Ambient)
Temp Rated1
Nu
m
C
1
Internal reference frequency - factory
P trimmed
at VDD = 5 V
2
P
3
P
4
D Internal reference startup time
5
DCO output frequency range untrimmed1
—
value provided for reference: fdco_ut =
1024 fint_ut
6
D
DCO output frequency range trimmed
fdco_t
7
Resolution of trimmed DCO output
D frequency at fixed voltage and
temperature (using FTRIM)
8
Resolution of trimmed DCO output
D frequency at fixed voltage and
temperature (not using FTRIM)
9
Total deviation from actual trimmed
P DCO output frequency over voltage
and temperature
fdco_t
10
Total deviation of trimmed DCO output
D frequency over fixed voltage and
temperature range of 0C to 70 C
fdco_t
11
D FLL acquisition time 3
tacquire
12
D
Rating
Symbol
Min
Typ
Max
Unit
Standard
AEC
Grade 0
fint_ft
—
31.25
—
kHz
x
x
Internal reference frequency untrimmed2
fint_ut
25
36
41.66
kHz
x
x
Internal reference frequency - user
trimmed
fint_t
31.25
—
39.0625
kHz
x
x
tirefst
—
55
100
s
x
x
fdco_ut
25.6
36.86
42.66
MHz
x
x
32
—
40
MHz
x
32
—
36
MHz
fdco_res_t
—
0.1
0.2
%fdco
x
x
fdco_res_t
—
0.2
0.4
%fdco
x
x
—
+ 0.5
– 1.0
1.5
%fdco
x
—
+ 0.5
– 1.0
3
%fdco
—
0.5
1
%fdco
x
x
1
ms
x
x
0.2
%fdco
x
x
DCO output clock long term jitter (over
2mS interval) 4
CJitter
—
0.02
x
x
1
Electrical characteristics only apply to the temperature rated devices marked with x.
TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).
3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used
as the reference, this specification assumes it is already running.
4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
BUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter
percentage for a given interval.
2
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
299
Deviation from Trimmed Frequency
Appendix A Electrical Characteristics
+2%
+1%
0
–1%
–2%
–40
0
25
Temperature (°C)
85
105
125
150
Figure A-8. Typical Frequency Deviation vs Temperature (ICS Trimmed to 16MHz bus@25°C, 5V, FEI)1
1. Based on the average of several hundred units from a typical characterization lot.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
300
Freescale Semiconductor
Appendix A Electrical Characteristics
A.10
Analog Comparator (ACMP) Electricals
Table A-10. Analog Comparator Electrical Specifications
Temp Rated1
Num
1
C
Rating
Symbol
Min
Typ
Max
Unit
Standard
AEC Grade
0
VDD
2.7
—
5.5
V
x
x
Supply current (active)
IDDAC
—
20
35
A
x
x
D
Analog input voltage
VAIN
VSS – 0.3
—
VDD
V
x
x
4
D
Analog input offset voltage
VAIO
20
40
mV
x
x
5
D
Analog Comparator hysteresis
6
D
7
D
1
—
Supply voltage
2
D
3
VH
3.0
6.0
20.0
mV
x
x
Analog input leakage current
IALKG
—
—
1.0
A
x
x
Analog Comparator
initialization delay
tAINIT
—
—
1.0
s
x
x
Electrical characteristics only apply to the temperature rated devices marked with x.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
301
Appendix A Electrical Characteristics
A.11
ADC Characteristics
Table A-11. ADC Operating Conditions
Temp Rated2
Characteristic
Supply voltage
Conditions
Min
Typ1
Max
Unit
Standard
AEC
Grade 0
VDDAD
2.7
—
5.5
V
x
x
Input Voltage
VADIN
VREFL
—
VREFH
V
x
x
Input
Capacitance
CADIN
—
4.5
5.5
pF
x
x
Input
Resistance
RADIN
—
3
5
k
x
x
—
—
—
—
5
10
x
x
8 bit mode (all valid
fADCK)
—
—
10
x
x
High Speed
(ADLPC=0)
0.4
—
8.0
x
x
0.4
—
4.0
x
x
Analog Source
Resistance
ADC
Conversion
Clock Freq.
Absolute
Symb
10 bit mode
fADCK > 4MHz
fADCK < 4MHz
Low Power
(ADLPC=1)
RAS
fADCK
Comment
External to
MCU
k
MHz
1
Typical values assume VDDAD = VDD = 5.0V, Temp = 25C, fADCK=1.0MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2 Electrical characteristics only apply to the temperature rated devices marked with x.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
302
Freescale Semiconductor
Appendix A Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
+
VADIN
VAS
–
CAS
+
–
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure A-9. ADC Input Impedance Equivalency Diagram
Table A-12. ADC Characteristics
Temp Rated2
Characteristic
Conditions
C
Symb
Min
Typ1
Max
Unit
IDD +
IDDAD
—
133
—
Comment
Stand
ard
AEC
Grade
0
A
x
x
ADC
current
only
Supply current
ADLPC=1
ADLSMP=1
ADCO=1
T
Supply current
ADLPC=1
ADLSMP=0
ADCO=1
T
IDD +
IDDAD
—
218
—
A
x
x
ADC
current
only
Supply current
ADLPC=0
ADLSMP=1
ADCO=1
T
IDD +
IDDAD
—
327
—
A
x
x
ADC
current
only
Supply current
ADLPC=0
ADLSMP=0
ADCO=1
P
IDD +
IDDAD
—
0.582
1
mA
x
x
ADC
current
only
2
3.3
5
x
x
ADC
asynchronous
clock source
High speed
(ADLPC=0)
P
Low power
(ADLPC=1)
MHz
fADACK
1.25
2
3.3
x
x
tADACK =
1/fADACK
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
303
Appendix A Electrical Characteristics
Table A-12. ADC Characteristics (continued)
Temp Rated2
Characteristic
Conversion
time (including
sample time)
Conditions
C
Symb
D
tADC
Short sample
(ADLSMP=0)
Long sample
(ADLSMP=1)
Short sample
(ADLSMP=0)
Sample time
D
Long sample
(ADLSMP=1)
Total
unadjusted
error (Includes
quantization)
P
ETUE
10 bit mode
Differential
Non-Linearity
P
Typ1
Max
—
20
—
—
40
—
—
3.5
—
Stand
ard
AEC
Grade
0
x
x
x
x
x
x
x
x
ADCK
cycles
—
23.5
—
—
1.5
3.5
LSB2
x
x
—
0.7
1.5
LSB3
x
x
—
0.5
1.0
x
x
—
0.3
0.5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
DNL
8 bit mode
Unit
ADCK
cycles
tADS
10 bit mode
8 bit mode
Min
LSB3
Comment
See ADC
Chapter
for
conversion
time
variances
Monotonicity and No-Missing-Codes guaranteed
Integral
non-linearity
10 bit mode
Zero-scale
error
10 bit mode
Full-scale error
(VADIN = VDD)
10 bit mode
Quantization
error
Input leakage
error
Temp sensor
slope
Temp sensor
voltage
T
8 bit mode
P
8 bit mode
T
8 bit mode
EZS
EFS
10 bit mode
D
8 bit mode
EQ
10 bit mode
D
8 bit mode
EIL
–40C to 25C
D
D
0.5
1.0
—
0.3
0.5
—
1.5
2.5
—
0.5
0.7
0
1.0
1.5
0
0.5
0.5
—
—
0.5
—
—
0.5
0
0.2
2.5
0
0.1
1
—
3.266
—
m
25C to 125C
25C
—
INL
VTEMP
LSB3
LSB3
LSB3
LSB3
LSB3
Pad
leakage3 *
RAS
mV/C
—
3.638
—
—
1.396
—
V
25
1
Typical values assume VDD = 5.0 V, Temp = 25C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 Electrical characteristics only apply to the temperature rated devices marked with x.
3 Based on input pad leakage current. Refer to pad electricals.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
304
Freescale Semiconductor
Appendix A Electrical Characteristics
A.12
AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1
Control Timing
Table A-13. Control Timing
Temp
Rated2
Num
C
1
D
Rating
Bus frequency (tcyc = 1/fBus)
–40 C to 125 C
Symbol
Min
Typ1
fBus
dc
—
>125 C
2
D
Internal low power oscillator period
–40 C to 125 C
Max
20
Unit
MHz
Sta
ndar
d
x
18
tLPO
>125 C
700
1500
600
1500
AE
C
Gra
de 0
x
s
x
x
3
D
External reset pulse width3
textrst
100
—
ns
x
x
4
D
Reset low drive4
trstdrv
66 x tcyc
—
ns
x
x
8
D
Pin interrupt pulse width
Asynchronous path2
Synchronous path5
tILIH, tIHIL
100
1.5 x tcyc
—
—
ns
x
x
—
—
40
75
—
—
ns
x
x
—
—
11
35
—
—
ns
x
x
9
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
C
1
Typical values are based on characterization data at VDD = 5.0V, 25C unless otherwise stated.
Electrical characteristics only apply to the temperature rated devices marked with x.
3 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
4 When any reset is initiated, internal circuitry drives the reset pin low for about 66 cycles of t
cyc. After POR reset the bus clock
frequency changes to the untrimmed DCO frequency (freset = (fdco_ut)/4) because TRIM is reset to 0x80 and FTRIM is reset to
0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets trim stays at the pre-reset value.
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40C to 125C.
2
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
305
Appendix A Electrical Characteristics
textrst
RESET PIN
Figure A-10. Reset Timing
tIHIL
IRQ/Pin Interrupts
IRQ/Pin Interrupts
tILIH
Figure A-11. IRQ/Pin Interrupt Timing
MC9S08SG8 MCU Series Data Sheet, Rev. 8
306
Freescale Semiconductor
Appendix A Electrical Characteristics
A.12.2
TPM/MTIM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table A-14. TPM Input Timing
Temp Rated1
Num
1
C
Rating
Symbol
Min
Max
Unit
Standard
AEC
Grade 0
1
—
External clock frequency (1/tTCLK)
fTCLK
dc
fBus/4
MHz
x
x
2
—
External clock period
tTCLK
4
—
tcyc
x
x
3
—
External clock high time
tclkh
1.5
—
tcyc
x
x
4
—
External clock low time
tclkl
1.5
—
tcyc
x
x
5
—
Input capture pulse width
tICPW
1.5
—
tcyc
x
x
Electrical characteristics only apply to the temperature rated devices marked with x.
tTCLK
tclkh
TCLK
tclkl
Figure A-12. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure A-13. Timer Input Capture Pulse
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
307
Appendix A Electrical Characteristics
A.12.3
SPI
Table A-15 and Figure A-14 through Figure A-17 describe the timing requirements for the SPI system.
Table A-15. SPI Electrical Characteristic
Temp Rated3
Num1
Rating2
C
Symbol
Min
Max
Unit
Standard
AEC Grade
0
Cycle time
1
D
Master
Slave
tSCK
tSCK
2
4
2048
tcyc
tcyc
x
x
—
Master
Slave
tLead
tLead
—
1/2
1/2
—
tSCK
tSCK
x
x
Master
Slave
tLag
tLag
—
1/2
1/2
—
tSCK
tSCK
x
x
x
x
x
x
Enable lead time
2
D
3
D
4
D
Clock (SPSCK) high time
Master and Slave
tSCKH
1/2 tSCK – 25
—
ns
5
D
Clock (SPSCK) low time
Master and Slave
tSCKL
1/2 tSCK – 25
—
ns
6
D
Master
Slave
tSI(M)
tSI(S)
30
30
—
—
ns
ns
x
x
7
D
Master
Slave
tHI(M)
tHI(S)
30
30
—
—
ns
ns
x
x
8
D
Access time, slave4
tA
0
40
ns
x
x
9
D
Disable time, slave5
tdis
—
40
ns
x
x
10
D
Data setup time (outputs)
Master
Slave
tSO
tSO
25
25
—
—
ns
ns
x
x
11
D
Master
Slave
tHO
tHO
–10
–10
—
—
ns
ns
x
x
12
D
Master
Slave
fop
fop
fBus/2048
dc
56
fBus/4
MHz
x
x
Enable lag time
Data setup time (inputs)
Data hold time (inputs)
Data hold time (outputs)
Operating frequency
1
2
3
4
5
6
Refer to Figure A-14 through Figure A-17.
All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew
rate control disabled and high drive strength enabled for SPI output pins.
Electrical characteristics only apply to the temperature rated devices marked with x.
Time to data active from high-impedance state.
Hold time to high-impedance state.
Maximum baud rate must be limited to 5 MHz due to input filter characteristics.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
308
Freescale Semiconductor
Appendix A Electrical Characteristics
SS1
(OUTPUT)
3
1
2
SCK
(CPOL = 0)
(OUTPUT)
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN2
BIT 6 . . . 1
10
MOSI
(OUTPUT)
LSB IN
11
10
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-14. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
3
2
SCK
(CPOL = 0)
(OUTPUT)
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN(2)
LSB IN
11
10
MOSI
(OUTPUT)
BIT 6 . . . 1
MSB OUT(2)
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-15. SPI Master Timing (CPHA = 1)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
309
Appendix A Electrical Characteristics
SS
(INPUT)
3
1
SCK
(CPOL = 0)
(INPUT)
5
4
2
SCK
(CPOL = 1)
(INPUT)
5
4
8
MISO
(OUTPUT)
11
10
BIT 6 . . . 1
MSB OUT
SLAVE
SEE
NOTE
SLAVE LSB OUT
7
6
MOSI
(INPUT)
9
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure A-16. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
3
1
2
SCK
(CPOL = 0)
(INPUT)
5
4
SCK
(CPOL = 1)
(INPUT)
5
4
10
MISO
(OUTPUT)
SEE
NOTE
8
MOSI
(INPUT)
SLAVE
11
MSB OUT
6
BIT 6 . . . 1
9
SLAVE LSB OUT
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure A-17. SPI Slave Timing (CPHA = 1)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
310
Freescale Semiconductor
Appendix A Electrical Characteristics
A.13
FLASH Specifications
This section provides details about program/erase times and program-erase endurance for the FLASH
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see the Memory section.
Table A-16. FLASH Characteristics
Temp Rated1
Nu
m
C
1
—
Supply voltage for
program/erase
2
—
3
Unit
Stand
ard
AEC
Grade
0
V
x
x
V
x
x
200
kHz
x
x
6.67
s
x
x
9
tFcyc
x
x
tBurst
4
tFcyc
x
x
Page erase time2
tPage
4000
tFcyc
x
x
time2
tMass
20,000
tFcyc
x
x
Symbol
Min
Vprog/erase
2.7
5.5
Supply voltage for read
operation
VRead
2.7
5.5
—
Internal FCLK frequency2
fFCLK
150
—
Internal FCLK period (1/fFCLK)
tFcyc
5
5
—
Byte program time (random
location)3
tprog
6
—
Byte program time (burst
mode)2
7
—
—
8
Characteristic
Mass erase
Typical
Max
endurance4
9
C
Program/erase
TL to TH = –40C to +125C
TL to TH = –40C to +150C
T = 25C
10
C
Data retention5
nFLPE
tD_ret
10,000
10,000
10,000
—
—
100,000
—
—
—
cycles
x
—
x
—
x
x
15
100
—
years
x
x
1
Electrical characteristics only apply to the temperature rated devices marked with x.
The frequency of this clock is controlled by a software setting.
3 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for
calculating approximate time to program and erase.
4 Typical endurance for FLASH is based on the intrinsic bit cell performance. For additional information on how Freescale defines
typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory.
5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to
25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to
Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
2
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
311
Appendix A Electrical Characteristics
A.14
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the
MCU resides. Board design and layout, circuit topology choices, location and characteristics of external
components as well as MCU software operation all play a significant role in EMC performance. The
system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263,
AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
A.14.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell
method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed
with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test
software. The radiated emissions from the microcontroller are measured in a TEM cell in two package
orientations (North and East).
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal
to the reported emissions levels.
Table A-17. Radiated Emissions, Electric Field
Temp Rated1
Parameter
Radiated
emissions,
electric field
1
Symbol
VRE_TEM
Conditions
VDD = 5 V
TA = +25oC
package type
16-TSSOP
Frequency
fOSC/fBUS
Level
(Max)
0.15 – 50 MHz
0
50 – 150 MHz
0
150 – 500 MHz
500 – 1000 MHz
4 MHz
crystal
16 MHzbus
Unit
Standa
AEC
rd
Grade 0
x
x
x
x
–6
x
x
–9
x
x
dBV
IEC Level
N
—
x
x
SAE Level
1
—
x
x
Electrical characteristics only apply to the temperature rated devices marked with x.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
312
Freescale Semiconductor
Appendix B
Ordering Information and Mechanical Drawings
B.1
Ordering Information
This section contains ordering information for MC9S08SG8 and MC9S08SG4 devices.
Table B-1. Device Numbering System
Temp Rated2
Memory
Device
Number1
FLASH
RAM
Standard
S9S08SG8
8K
512
x
S9S08SG4
4K
256
x
S9S08SG8
8K
512
x
S9S08SG4
4K
256
x
Available Packages3
AEC Grade 0
20-Pin
16-Pin
8-Pin
20 TSSOP
16 TSSOP
8 NB SOIC
—
16 TSSOP
—
1
See Table 1-1 for a complete description of modules included on each device.
Apply to the temperature rated devices marked with x only.
3 See Table B-2 for package information.
2
B.1.1
Device Numbering Scheme
S
9
S08
SG 8
E2
C
TJ
R
Status
- S = Auto Qualified
Tape and Reel Suffix (optional)
Package Designator
Two letter descriptor
(refer to Table B-2).
Main Memory Type
- 9 = Flash-based
Temperature Option
- C = -40 to 85 C
- V = -40 to 105 C
- M = -40 to 125 C
- W = -40 to 150 C
Core
SG Family
Memory Size
Mask Set Identifier
- 8 Kbytes
- 4 Kbytes
- Alpha character references
wafer fab.
- Numeric character identifies
mask.
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor
313
Appendix B Ordering Information and Mechanical Drawings
B.2
Mechanical Drawings
The following pages are mechanical specifications for MC9S08SG8 package options. See Table B-2 for
the document number for each package type.
Table B-2. Package Information
Pin
Count
Type
Designator
Document No.
20
TSSOP
TJ
98ASH70169A
16
TSSOP
TG
98ASH70247A
8
NB SOIC
SC
98ASB42564B
MC9S08SG8 MCU Series Data Sheet, Rev. 8
314
Freescale Semiconductor
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