S9S12G48F1CLCR

厂商：
NXP(恩智浦)
封装：
LQFP32
描述：
IC MCU 16BIT 48KB FLASH 32LQFP

数据手册：

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S9S12G48F1CLCR 数据手册

MC9S12G Family Reference Manual and Data Sheet S12 Microcontrollers MC9S12GRMV1 Rev.1.28 December 7, 2020 nxp.com To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: nxp.com/ A full list of family members and options is included in the appendices. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 2 The following revision history table summarizes changes contained in this document. Revision History Date Revision Level Nov, 2012 1.19 • Corrected order of chapters Jan, 2013 1.20 • Updated Appendix A, “Electrical Characteristics” (Reason: Added AEC Grade 0 spec) • Updated Appendix C, “Ordering and Shipping Information” (Reason: Added temperature option W) Jan, 2013 1.21 • Separated description of 8-channel timer • Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals) Jan, 2013 1.22 • Updated Chapter 1, “Device Overview MC9S12G-Family” (Reason: added KGD option for the S12GA192 and the S12GA240) • Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals) • Updated Appendix C, “Ordering and Shipping Information” (Reason: Added KGD information) • Added Appendix D, “Package and Die Information” (Reason: Added KGD information) Feb, 2013 1.23 • Updated Appendix C, “Ordering and Shipping Information” (Reason: Removed KGD information) Jul, 2014 1.24 • Updated Chapter 1, “Device Overview MC9S12G-Family” (Reason: Spec update) • Fixed wordingFixed typos and formatting, improved wording • Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals) • Updated Chapter 17, “Digital Analog Converter (DAC_8B5V)” (Reason: Spec update) Aug, 2014 1.25 • Fixed issues with hidden text throughout the document Jun, 2017 1.26 • Updated Chapter 1, “Device Overview MC9S12G-Family (added mask set information to Table 1-5) Oct, 2017 1.27 • Updated Appendix A, “Electrical Characteristics (updated Table A-45 and Table A-46) Dec, 2020 1.28 • Updated Appendix A, “Electrical Characteristics (added Table A-14) Description This document contains information for all constituent modules, with the exception of the CPU. For CPU information please refer to CPU12-1 in the CPU12 & CPU12X Reference Manual MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 3 MC9S12G Family Reference Manual Rev.1.28 4 NXP Semiconductors Chapter 1 Device Overview MC9S12G-Family. . . . . . . . . . . . . . . . . . . . . . 29 Chapter 2 Port Integration Module (S12GPIMV1) . . . . . . . . . . . . . . . . . . 149 Chapter 3 5V Analog Comparator (ACMPV1) . . . . . . . . . . . . . . . . . . . . . 249 Chapter 4 Reference Voltage Attenuator (RVAV1) . . . . . . . . . . . . . . . . . 255 Chapter 5 S12G Memory Map Controller (S12GMMCV1) . . . . . . . . . . . . 259 Chapter 6 Interrupt Module (S12SINTV1). . . . . . . . . . . . . . . . . . . . . . . . . 273 Chapter 7 Background Debug Module (S12SBDMV1) . . . . . . . . . . . . . . 281 Chapter 8 S12S Debug Module (S12SDBGV2) . . . . . . . . . . . . . . . . . . . . 305 Chapter 9 Security (S12XS9SECV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 Chapter 10 S12 Clock, Reset and Power Management Unit (S12CPMU) 353 Chapter 11 Analog-to-Digital Converter (ADC10B8CV2) . . . . . . . . . . . . . 405 Chapter 12 Analog-to-Digital Converter (ADC12B8CV2) . . . . . . . . . . . . . 429 Chapter 13 Analog-to-Digital Converter (ADC10B12CV2) . . . . . . . . . . . . 455 Chapter 14 Analog-to-Digital Converter (ADC12B12CV2) . . . . . . . . . . . . 481 Chapter 15 Analog-to-Digital Converter (ADC10B16CV2) . . . . . . . . . . . . 507 Chapter 16 Analog-to-Digital Converter (ADC12B16CV2) . . . . . . . . . . . . 533 Chapter 17 Digital Analog Converter (DAC_8B5V) . . . . . . . . . . . . . . . . . . 559 Chapter 18 Scalable Controller Area Network (S12MSCANV3) . . . . . . . . 569 Chapter 19 Pulse-Width Modulator (S12PWM8B8CV2) . . . . . . . . . . . . . . 623 Chapter 20 Serial Communication Interface (S12SCIV5) . . . . . . . . . . . . . 653 Chapter 21 Serial Peripheral Interface (S12SPIV5) . . . . . . . . . . . . . . . . . . 691 Chapter 22 Timer Module (TIM16B6CV3) . . . . . . . . . . . . . . . . . . . . . . . . . . 719 Chapter 23 Timer Module (TIM16B8CV3) . . . . . . . . . . . . . . . . . . . . . . . . . . 737 Chapter 24 16 KByte Flash Module (S12FTMRG16K1V1). . . . . . . . . . . . . 765 Chapter 25 32 KByte Flash Module (S12FTMRG32K1V1). . . . . . . . . . . . . 813 Chapter 26 48 KByte Flash Module (S12FTMRG48K1V1). . . . . . . . . . . . . 865 Chapter 27 64 KByte Flash Module (S12FTMRG64K1V1). . . . . . . . . . . . . 917 Chapter 28 96 KByte Flash Module (S12FTMRG96K1V1). . . . . . . . . . . . . 969 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 5 Chapter 29 128 KByte Flash Module (S12FTMRG128K1V1). . . . . . . . . . 1021 Chapter 30 192 KByte Flash Module (S12FTMRG192K2V1). . . . . . . . . . 1073 Chapter 31 240 KByte Flash Module (S12FTMRG240K2V1). . . . . . . . . . 1125 Appendix A Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177 Appendix B Detailed Register Address Map. . . . . . . . . . . . . . . . . . . . . . . 1233 Appendix C Ordering and Shipping Information . . . . . . . . . . . . . . . . . . . 1253 Appendix D Package and Die Information . . . . . . . . . . . . . . . . . . . . . . . . 1255 MC9S12G Family Reference Manual Rev.1.28 6 NXP Semiconductors Chapter 1 Device Overview MC9S12G-Family 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.2.1 MC9S12G-Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.2.2 Chip-Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.3.1 S12 16-Bit Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.3.2 On-Chip Flash with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.3.3 On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.3.4 Port Integration Module (PIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.3.5 Main External Oscillator (XOSCLCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.3.6 Internal RC Oscillator (IRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.3.7 Internal Phase-Locked Loop (IPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.3.8 System Integrity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.3.9 Timer (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.3.10 Pulse Width Modulation Module (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.3.11 Controller Area Network Module (MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.3.12 Serial Communication Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.3.13 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.3.14 Analog-to-Digital Converter Module (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.3.15 Reference Voltage Attenuator (RVA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.3.16 Digital-to-Analog Converter Module (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.3.17 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.3.18 On-Chip Voltage Regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.3.19 Background Debug (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.3.20 Debugger (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Key Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Family Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 1.6.1 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Signal Description and Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.7.1 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.7.2 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 1.7.3 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 1.8.1 S12GN16 and S12GN32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 1.8.2 S12GNA16 and S12GNA32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1.8.3 S12GN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.8.4 S12G48 and S12G64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.8.5 S12GA48 and S12GA64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 1.8.6 S12G96 and S12G128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 1.8.7 S12GA96 and S12GA128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 1.8.8 S12G192 and S12G240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 1.8.9 S12GA192 and S12GA240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 9 1.9 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 1.10 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 1.10.1 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 1.10.2 Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 1.11 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 1.12 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 1.12.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 1.12.2 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 1.12.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 1.13 COP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 1.14 Autonomous Clock (ACLK) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 1.15 ADC External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 1.16 ADC Special Conversion Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 1.17 ADC Result Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 1.18 ADC VRH/VRL Signal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 1.19 BDM Clock Source Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Chapter 2 Port Integration Module (S12GPIMV1) 2.1 2.2 2.3 2.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 2.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 2.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 2.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 2.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 PIM Routing - External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 2.2.1 Package Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 2.2.2 Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 2.2.3 Signals and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 PIM Routing - Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 2.3.1 Pin BKGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 2.3.2 Pins PA7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 2.3.3 Pins PB7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 2.3.4 Pins PC7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 2.3.5 Pins PD7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 2.3.6 Pins PE1-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 2.3.7 Pins PT7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 2.3.8 Pins PS7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 2.3.9 Pins PM3-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 2.3.10 Pins PP7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 2.3.11 Pins PJ7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 2.3.12 Pins AD15-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 PIM Ports - Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 2.4.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 2.4.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 2.4.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 MC9S12G Family Reference Manual Rev.1.28 10 NXP Semiconductors 2.5 2.6 PIM Ports - Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 2.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 2.5.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 2.5.3 Pin Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 2.5.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 2.6.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 2.6.2 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 2.6.3 Enabling IRQ edge-sensitive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 2.6.4 ADC External Triggers ETRIG3-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 2.6.5 Emulation of Smaller Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Chapter 3 5V Analog Comparator (ACMPV1) 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 3.6.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 3.6.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Chapter 4 Reference Voltage Attenuator (RVAV1) 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 4.6.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 4.6.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Chapter 5 S12G Memory Map Controller (S12GMMCV1) 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 5.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 5.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 5.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 5.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 5.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 11 5.2 5.3 5.4 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 5.4.1 MCU Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 5.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 5.4.3 Unimplemented and Reserved Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 5.4.4 Prioritization of Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 5.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Chapter 6 Interrupt Module (S12SINTV1) 6.1 6.2 6.3 6.4 6.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 6.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 6.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 6.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 6.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 6.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 6.4.1 S12S Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 6.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 6.4.3 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 6.4.4 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 6.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 6.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 6.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Chapter 7 Background Debug Module (S12SBDMV1) 7.1 7.2 7.3 7.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 7.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 7.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 7.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 MC9S12G Family Reference Manual Rev.1.28 12 NXP Semiconductors 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.4.10 7.4.11 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Chapter 8 S12S Debug Module (S12SDBGV2) 8.1 8.2 8.3 8.4 8.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 8.1.1 Glossary Of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 8.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 8.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 8.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 8.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 8.4.1 S12SDBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 8.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 8.4.3 Match Modes (Forced or Tagged) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 8.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 8.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 8.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 8.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 8.5.1 State Machine scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 8.5.2 Scenario 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 8.5.3 Scenario 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 8.5.4 Scenario 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 8.5.5 Scenario 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 8.5.6 Scenario 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 8.5.7 Scenario 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 8.5.8 Scenario 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 8.5.9 Scenario 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 8.5.10 Scenario 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 8.5.11 Scenario 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 13 Chapter 9 Security (S12XS9SECV2) 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 9.1.3 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 9.1.4 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 9.1.5 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 9.1.6 Reprogramming the Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 9.1.7 Complete Memory Erase (Special Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Chapter 10 S12 Clock, Reset and Power Management Unit (S12CPMU) 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 10.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 10.1.3 S12CPMU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 10.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 10.2.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 10.2.2 EXTAL and XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 10.2.3 VDDR — Regulator Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 10.2.4 VSS — Ground Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 10.2.5 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 10.2.6 VDDX, VSSX— Pad Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 10.2.7 VDD — Internal Regulator Output Supply (Core Logic) . . . . . . . . . . . . . . . . . . . . . . . 361 10.2.8 VDDF — Internal Regulator Output Supply (NVM Logic) . . . . . . . . . . . . . . . . . . . . . 361 10.2.9 API_EXTCLK — API external clock output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 10.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 10.4.1 Phase Locked Loop with Internal Filter (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 10.4.2 Startup from Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 10.4.3 Stop Mode using PLLCLK as Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 10.4.4 Full Stop Mode using Oscillator Clock as Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . 391 10.4.5 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 10.4.6 System Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 10.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 10.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 10.5.2 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 10.5.3 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 10.5.4 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 10.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 10.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 MC9S12G Family Reference Manual Rev.1.28 14 NXP Semiconductors 10.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 10.7.1 General Initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 10.7.2 Application information for COP and API usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 Chapter 11 Analog-to-Digital Converter (ADC10B8CV2) 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 11.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 11.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 11.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 11.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 11.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 11.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 11.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 11.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 Chapter 12 Analog-to-Digital Converter (ADC12B8CV2) 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 12.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 12.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 12.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 12.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 12.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 12.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 12.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 Chapter 13 Analog-to-Digital Converter (ADC10B12CV2) 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 15 13.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 13.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 13.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 13.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 13.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 13.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 Chapter 14 Analog-to-Digital Converter (ADC12B12CV2) 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 14.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 14.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 14.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 14.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 14.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 14.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 14.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 Chapter 15 Analog-to-Digital Converter (ADC10B16CV2) 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 15.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 15.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 15.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 15.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 15.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 15.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 15.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 MC9S12G Family Reference Manual Rev.1.28 16 NXP Semiconductors Chapter 16 Analog-to-Digital Converter (ADC12B16CV2) 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 16.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 16.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 16.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 16.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 16.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 16.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 16.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 Chapter 17 Digital Analog Converter (DAC_8B5V) 17.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 17.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 17.2.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 17.2.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 17.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 17.3.1 DACU Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 17.3.2 AMP Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 17.3.3 AMPP Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 17.3.4 AMPM Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 17.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 17.4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 17.4.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 17.5.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 17.5.2 Mode “Off” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 17.5.3 Mode “Operational Amplifier” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 17.5.4 Mode “Unbuffered DAC” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 17.5.5 Mode “Unbuffered DAC with Operational Amplifier” . . . . . . . . . . . . . . . . . . . . . . . . . 566 17.5.6 Mode “Buffered DAC” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 17.5.7 Analog output voltage calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 Chapter 18 Scalable Controller Area Network (S12MSCANV3) 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 17 18.2 18.3 18.4 18.5 18.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 18.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 18.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 18.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 18.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 18.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 18.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 18.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 18.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 18.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 18.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 18.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 18.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 18.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 18.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 18.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 18.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 Chapter 19 Pulse-Width Modulator (S12PWM8B8CV2) 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 19.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 19.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 19.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 19.2.1 PWM7 - PWM0 — PWM Channel 7 - 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 19.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 19.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 19.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 19.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 19.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 Chapter 20 Serial Communication Interface (S12SCIV5) 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 MC9S12G Family Reference Manual Rev.1.28 18 NXP Semiconductors 20.2 20.3 20.4 20.5 20.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 20.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 20.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 20.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 20.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 20.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 20.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 20.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 20.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 20.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 20.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 20.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 20.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 20.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 20.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 20.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 20.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 20.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 20.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 20.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 Chapter 21 Serial Peripheral Interface (S12SPIV5) 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 21.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 21.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 21.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 21.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 21.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 21.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 21.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 21.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 21.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 21.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 21.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 21.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 21.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 21.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 19 21.4.4 21.4.5 21.4.6 21.4.7 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 Chapter 22 Timer Module (TIM16B6CV3) 22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 22.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 22.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 22.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 22.2.1 IOC5 - IOC0 — Input Capture and Output Compare Channel 5-0 . . . . . . . . . . . . . . . . 721 22.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 22.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 22.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 22.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 22.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 22.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 22.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 22.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 22.6.1 Channel [5:0] Interrupt (C[5:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 22.6.2 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 Chapter 23 Timer Module (TIM16B8CV3) 23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 23.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 23.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 23.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 23.2.1 IOC7 — Input Capture and Output Compare Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . 741 23.2.2 IOC6 - IOC0 — Input Capture and Output Compare Channel 6-0 . . . . . . . . . . . . . . . . 741 23.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 23.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 23.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 23.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760 23.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760 23.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760 23.4.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 23.4.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 23.4.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 MC9S12G Family Reference Manual Rev.1.28 20 NXP Semiconductors 23.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 23.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 23.6.1 Channel [7:0] Interrupt (C[7:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 23.6.2 Pulse Accumulator Input Interrupt (PAOVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 23.6.3 Pulse Accumulator Overflow Interrupt (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 23.6.4 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 Chapter 24 16 KByte Flash Module (S12FTMRG16K1V1) 24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 24.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 24.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 24.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 24.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 24.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 24.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 24.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 24.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 24.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 24.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 24.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 24.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 24.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 794 24.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 24.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809 24.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 24.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 24.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 24.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 24.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 811 24.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 812 24.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812 Chapter 25 32 KByte Flash Module (S12FTMRG32K1V1) 25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813 25.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 25.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 25.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815 25.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 25.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 25.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 25.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 25.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 21 25.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 25.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 25.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 25.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 25.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 845 25.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 25.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 25.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 25.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 25.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 25.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 25.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 862 25.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 863 25.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863 Chapter 26 48 KByte Flash Module (S12FTMRG48K1V1) 26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 26.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 26.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 26.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 26.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 26.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869 26.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869 26.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873 26.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892 26.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892 26.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892 26.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 26.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 26.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 898 26.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899 26.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913 26.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914 26.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914 26.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914 26.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914 26.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 915 26.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 916 26.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916 Chapter 27 64 KByte Flash Module (S12FTMRG64K1V1) 27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917 MC9S12G Family Reference Manual Rev.1.28 22 NXP Semiconductors 27.2 27.3 27.4 27.5 27.6 27.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918 27.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918 27.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921 27.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921 27.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943 27.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943 27.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943 27.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944 27.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944 27.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 949 27.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 27.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964 27.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 27.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 27.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 27.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 966 27.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 967 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967 Chapter 28 96 KByte Flash Module (S12FTMRG96K1V1) 28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 28.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970 28.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970 28.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 28.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972 28.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973 28.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973 28.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976 28.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995 28.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995 28.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995 28.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996 28.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996 28.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . 1001 28.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002 28.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 28.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 28.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 28.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 28.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 23 28.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1018 28.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 1019 28.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019 Chapter 29 128 KByte Flash Module (S12FTMRG128K1V1) 29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021 29.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 29.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 29.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023 29.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024 29.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025 29.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025 29.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029 29.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047 29.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047 29.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047 29.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048 29.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048 29.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . 1053 29.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054 29.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068 29.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 29.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 29.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 29.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 29.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1070 29.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 1071 29.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071 Chapter 30 192 KByte Flash Module (S12FTMRG192K2V1) 30.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073 30.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 30.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 30.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075 30.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076 30.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077 30.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077 30.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081 30.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099 30.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099 30.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099 30.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100 MC9S12G Family Reference Manual Rev.1.28 24 NXP Semiconductors 30.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . 30.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 30.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 30.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100 1105 1106 1119 1120 1120 1121 1121 1122 1122 1122 Chapter 31 240 KByte Flash Module (S12FTMRG240K2V1) 31.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . 31.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 31.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 31.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125 1126 1126 1127 1128 1129 1129 1133 1151 1151 1151 1152 1152 1157 1158 1171 1172 1172 1173 1173 1174 1174 1174 Appendix A Electrical Characteristics A.1 General A.1.1 A.1.2 A.1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 25 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 A.13 A.14 A.15 A.16 A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183 I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187 Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191 A.3.1 Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196 A.4.1 ADC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196 A.4.2 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197 A.4.3 ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198 A.4.4 ADC Temperature Sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 ACMP Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210 NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211 A.7.1 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211 A.7.2 NVM Reliability Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217 A.8.1 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217 A.8.2 Electrical Characteristics for the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219 Electrical Characteristics for the IRC1M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219 Electrical Characteristics for the Oscillator (XOSCLCP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221 Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222 Electrical Specification for Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223 Chip Power-up and Voltage Drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227 A.15.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227 A.15.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229 ADC Conversion Result Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231 Appendix B Detailed Register Address Map B.1 Detailed Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233 Appendix C Ordering and Shipping Information C.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253 Appendix D Package and Die Information D.1 100 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256 D.2 64 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259 MC9S12G Family Reference Manual Rev.1.28 26 NXP Semiconductors D.3 D.4 D.5 D.6 D.7 48 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262 48 QFN Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264 32 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267 20 TSSOP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270 KGD Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 27 MC9S12G Family Reference Manual Rev.1.28 28 NXP Semiconductors Chapter 1 Device Overview MC9S12G-Family Revision History Version Number Revision Date Rev 0.27 1-Apr-2011 Rev 0.28 11-May-2011 • Rev 0.29 10-Jan-2011 • Corrected Figure 1-4 Rev 0.30 10-Feb-2012 • Updated Table 1-5(added mask set 1N75C) • Typos and formatting Rev 0.31 15-Mar-2012 • • • • • • • Rev 0.32 07-May-2012 • Updated Section 1.19, “BDM Clock Source Connectivity” • Typos and formatting Rev 0.33 27-Sep-2012 • Corrected Figure 1-4 • Corrected Figure 1-5 • Corrected Figure 1-6 Rev 0.34 25-Jan-2013 Added KGD option for the S12GA192 and the S12GA240 • Updated Table 1-1 • Corrected Table 1-2 • Corrected Table 1-6 Description of Changes • Typos and formatting Updated Table 1-1 (added S12GSA devices) Updated Figure 1-1 Updated Table 1-5 (added S12GA devices) Added Section 1.8.2, “S12GNA16 and S12GNA32” Added Section 1.8.5, “S12GA48 and S12GA64” Added Section 1.8.7, “S12GA96 and S12GA128” Typos and formatting Rev 0.35 02-Jul-2014 • Corrected Table 1-2 Rev 0.36 14-Jun-2017 • Extended Table 1-5 1.1 Introduction The MC9S12G-Family is an optimized, automotive, 16-bit microcontroller product line focused on low-cost, high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS-Family. The MC9S12G-Family is targeted at generic automotive applications requiring CAN or LIN/J2602 communication. Typical examples of these applications include body controllers, occupant detection, door modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes. The MC9S12G-Family uses many of the same features found on the MC9S12XS- and MC9S12P-Family, including error correction code (ECC) on flash memory, a fast analog-to-digital converter (ADC) and a frequency modulated phase locked loop (IPLL) that improves the EMC performance. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 29 Device Overview MC9S12G-Family The MC9S12G-Family is optimized for lower program memory sizes down to 16k. In order to simplify customer use it features an EEPROM with a small 4 bytes erase sector size. The MC9S12G-Family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of NXP’s existing 8-bit and 16-bit MCU families. Like the MC9S12XS-Family, the MC9S12G-Family run 16-bit wide accesses without wait states for all peripherals and memories. The MC9S12G-Family is available in 100-pin LQFP, 64-pin LQFP, 48-pin LQFP/QFN, 32-pin LQFP and 20-pin TSSOP package options and aims to maximize the amount of functionality especially for the lower pin count packages. In addition to the I/O ports available in each module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait modes. 1.2 Features This section describes the key features of the MC9S12G-Family. 1.2.1 MC9S12G-Family Comparison Table 1-1 provides a summary of different members of the MC9S12G-Family and their features. This information is intended to provide an understanding of the range of functionality offered by this microcontroller family. S12G128 S12GA128 S12G192 S12GA192 S12G240 S12GA240 48 64 64 96 96 128 128 192 192 240 240 EEPROM [kBytes] 0.5 0.5 1 1 1.5 1.5 1.5 2 2 3 3 4 4 4 4 4 4 RAM [kBytes] 1 1 2 2 4 4 4 4 4 8 8 8 8 11 11 11 11 MSCAN — — — — — 1 1 1 1 1 1 1 1 1 1 1 1 SCI 1 1 1 1 2 2 2 2 2 3 3 3 3 3 3 3 3 SPI 1 1 1 1 2 2 2 2 2 3 3 3 3 3 3 3 3 16-Bit Timer channels 6 6 6 6 6 6 6 6 6 8 8 8 8 8 8 8 8 8-Bit PWM channels 6 6 6 6 6 6 6 6 6 8 8 8 8 8 8 8 8 10-Bit ADC channels 8 — 8 — 12 12 — 12 — 12 — 12 — 16 — 16 — 12-Bit ADC channels — 8 — 8 — — 12 — 12 — 12 — 12 — 16 — 16 Temperature Sensor — — — — — — — — — — — — — — Yes — Yes RVA — — — — — — — — — — — — — — YES — YES 8-Bit DAC — — — — — — — — — — — — — — 2 — 2 S12G96 48 CPU S12GA64 48 S12G64 32 S12GA48 32 S12G48 16 S12GN48 16 S12GN32 Flash memory [kBytes] Feature S12GN16 S12GA96 S12GNA32 S12GNA16 Table 1-1. MC9S12G-Family Overview1 CPU12V1 MC9S12G Family Reference Manual Rev.1.28 30 NXP Semiconductors Device Overview MC9S12G-Family S12GN16 S12GNA16 S12GN32 S12GNA32 S12GN48 S12G48 S12GA48 S12G64 S12GA64 S12G96 S12GA96 S12G128 S12GA128 S12G192 S12GA192 S12G240 S12GA240 Table 1-1. MC9S12G-Family Overview1 1 1 1 1 1 1 1 1 1 — — — — — — — — PLL Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes External osc Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Internal 1 MHz RC oscillator Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 20-pin TSSOP Yes — Yes — — — — — — — — — — — — — — 32-pin LQFP Yes — Yes — Yes Yes — Yes — — — — — — — — — 48-pin LQFP Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 48-pin QFN Yes Yes Yes Yes — — — — — — — — — — — — — 64-pin LQFP — — — — Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 100-pin LQFP — — — — — — — — — Yes Yes Yes Yes Yes Yes Yes Yes KGD — — — — — — — — — — — — — — Yes — Yes Feature ACMP (analog comparator) Supply voltage 3.13 V – 5.5 V Execution speed 1 Static – 25 MHz Not all peripherals are available in all package types Table 1-2shows the maximum number of peripherals or peripheral channels per package type. Not all peripherals are available at the same time. The maximum number of peripherals is also limited by the device chosen as per Table 1-1. Table 1-2. Maximum Peripheral Availability per Package Peripheral MSCAN 20 TSSOP 32 LQFP 48 QFN 48 LQFP 64 LQFP 100 LQFP KGD (Die) — Yes — Yes Yes Yes Yes SCI0 Yes Yes Yes Yes Yes Yes Yes SCI1 — Yes Yes Yes Yes Yes Yes SCI2 — — — Yes Yes Yes Yes SPI0 Yes Yes Yes Yes Yes Yes Yes SPI1 — — — Yes Yes Yes Yes SPI2 — — — — Yes Yes Yes 4=0…3 6=0…5 6=0…5 8=0…7 8=0…7 8=0…7 8=0…7 8-Bit PWM Channels 4 = 0 … 3 6 = 0 … 5 6 = 0 … 5 8=0…7 8=0…7 8=0…7 8=0…7 Timer Channels ADC channels 6 = 0 … 5 8 = 0 … 7 8 = 0 … 7 12 = 0 … 11 16 = 0 … 15 16 = 0 … 15 16 = 0 … 15 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 31 Device Overview MC9S12G-Family Table 1-2. Maximum Peripheral Availability per Package Peripheral 1.2.2 20 TSSOP 32 LQFP 48 QFN 48 LQFP 64 LQFP 100 LQFP KGD (Die) DAC0 — — — Yes Yes Yes Yes DAC1 — — — Yes Yes Yes Yes ACMP Yes Yes Yes Yes Yes — — Total GPIO 14 26 40 40 54 86 86 Chip-Level Features On-chip modules available within the family include the following features: • S12 CPU core • Up to 240 Kbyte on-chip flash with ECC • Up to 4 Kbyte EEPROM with ECC • Up to 11 Kbyte on-chip SRAM • Phase locked loop (IPLL) frequency multiplier with internal filter • 4–16 MHz amplitude controlled Pierce oscillator • 1 MHz internal RC oscillator • Timer module (TIM) supporting up to eight channels that provide a range of 16-bit input capture, output compare, counter, and pulse accumulator functions • Pulse width modulation (PWM) module with up to eight x 8-bit channels • Up to 16-channel, 10 or 12-bit resolution successive approximation analog-to-digital converter (ADC) • Up to two 8-bit digital-to-analog converters (DAC) • Up to one 5V analog comparator (ACMP) • Up to three serial peripheral interface (SPI) modules • Up to three serial communication interface (SCI) modules supporting LIN communications • Up to one multi-scalable controller area network (MSCAN) module (supporting CAN protocol 2.0A/B) • On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages • Autonomous periodic interrupt (API) • Precision fixed voltage reference for ADC conversions • Optional reference voltage attenuator module to increase ADC accuracy 1.3 Module Features The following sections provide more details of the modules implemented on the MC9S12G-Family family. MC9S12G Family Reference Manual Rev.1.28 32 NXP Semiconductors Device Overview MC9S12G-Family 1.3.1 S12 16-Bit Central Processor Unit (CPU) S12 CPU is a high-speed 16-bit processing unit: • Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution • Includes many single-byte instructions. This allows much more efficient use of ROM space. • Extensive set of indexed addressing capabilities, including: — Using the stack pointer as an indexing register in all indexed operations — Using the program counter as an indexing register in all but auto increment/decrement mode — Accumulator offsets using A, B, or D accumulators — Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8) 1.3.2 On-Chip Flash with ECC On-chip flash memory on the MC9S12G-Family family features the following: • Up to 240 Kbyte of program flash memory — 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction and double fault detection — Erase sector size 512 bytes — Automated program and erase algorithm — User margin level setting for reads — Protection scheme to prevent accidental program or erase • Up to 4 Kbyte EEPROM — 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction and double fault detection — Erase sector size 4 bytes — Automated program and erase algorithm — User margin level setting for reads 1.3.3 • 1.3.4 • • • • On-Chip SRAM Up to 11 Kbytes of general-purpose RAM Port Integration Module (PIM) Data registers and data direction registers for ports A, B, C, D, E, T, S, M, P, J and AD when used as general-purpose I/O Control registers to enable/disable pull devices and select pullups/pulldowns on ports T, S, M, P, J and AD on per-pin basis Single control register to enable/disable pull devices on ports A, B, C, D and E, on per-port basis and on BKGD pin Control registers to enable/disable open-drain (wired-or) mode on ports S and M MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 33 Device Overview MC9S12G-Family • • • • • • • 1.3.5 • 1.3.6 • 1.3.7 • Interrupt flag register for pin interrupts on ports P, J and AD Control register to configure IRQ pin operation Routing register to support programmable signal redirection in 20 TSSOP only Routing register to support programmable signal redirection in 100 LQFP package only Package code register preset by factory related to package in use, writable once after reset. Also includes bit to reprogram routing of API_EXTCLK in all packages. Control register for free-running clock outputs Main External Oscillator (XOSCLCP) Loop control Pierce oscillator using a 4 MHz to 16 MHz crystal — Current gain control on amplitude output — Signal with low harmonic distortion — Low power — Good noise immunity — Eliminates need for external current limiting resistor — Transconductance sized for optimum start-up margin for typical crystals — Oscillator pins can be shared w/ GPIO functionality Internal RC Oscillator (IRC) Trimmable internal reference clock. — Frequency: 1 MHz — Trimmed accuracy over –40°C to +125°C ambient temperature range: 1.0% for temperature option C and V (see Table A-4) 1.3% for temperature option M (see Table A-4) Internal Phase-Locked Loop (IPLL) Phase-locked-loop clock frequency multiplier — No external components required — Reference divider and multiplier allow large variety of clock rates — Automatic bandwidth control mode for low-jitter operation — Automatic frequency lock detector — Configurable option to spread spectrum for reduced EMC radiation (frequency modulation) — Reference clock sources: – External 4–16 MHz resonator/crystal (XOSCLCP) – Internal 1 MHz RC oscillator (IRC) MC9S12G Family Reference Manual Rev.1.28 34 NXP Semiconductors Device Overview MC9S12G-Family 1.3.8 • • • • • • • System Integrity Support Power-on reset (POR) System reset generation Illegal address detection with reset Low-voltage detection with interrupt or reset Real time interrupt (RTI) Computer operating properly (COP) watchdog — Configurable as window COP for enhanced failure detection — Initialized out of reset using option bits located in flash memory Clock monitor supervising the correct function of the oscillator 1.3.9 • • • Timer (TIM) Up to eight x 16-bit channels for input capture or output compare 16-bit free-running counter with 7-bit precision prescaler In case of eight channel timer Version an additional 16-bit pulse accumulator is available 1.3.10 • Up to eight channel x 8-bit or up to four channel x 16-bit pulse width modulator — Programmable period and duty cycle per channel — Center-aligned or left-aligned outputs — Programmable clock select logic with a wide range of frequencies 1.3.11 • • • • • • • Pulse Width Modulation Module (PWM) Controller Area Network Module (MSCAN) 1 Mbit per second, CAN 2.0 A, B software compatible — Standard and extended data frames — 0–8 bytes data length — Programmable bit rate up to 1 Mbps Five receive buffers with FIFO storage scheme Three transmit buffers with internal prioritization Flexible identifier acceptance filter programmable as: — 2 x 32-bit — 4 x 16-bit — 8 x 8-bit Wakeup with integrated low pass filter option Loop back for self test Listen-only mode to monitor CAN bus MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 35 Device Overview MC9S12G-Family • • Bus-off recovery by software intervention or automatically 16-bit time stamp of transmitted/received messages 1.3.12 • • • • • • • • • Up to three SCI modules Full-duplex or single-wire operation Standard mark/space non-return-to-zero (NRZ) format Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths 13-bit baud rate selection Programmable character length Programmable polarity for transmitter and receiver Active edge receive wakeup Break detect and transmit collision detect supporting LIN 1.3, 2.0, 2.1 and SAE J2602 1.3.13 • • • • • • • Serial Communication Interface Module (SCI) Serial Peripheral Interface Module (SPI) Up to three SPI modules Configurable 8- or 16-bit data size Full-duplex or single-wire bidirectional Double-buffered transmit and receive Master or slave mode MSB-first or LSB-first shifting Serial clock phase and polarity options 1.3.14 Analog-to-Digital Converter Module (ADC) Up to 16-channel, 10-bit/12-bit1 analog-to-digital converter — 3 us conversion time — 8-/101-bit resolution — Left or right justified result data — Wakeup from low power modes on analog comparison > or GPO PB1 • 100 LQFP: The API_EXTCLK signal is mapped to this pin when used with the external clock function. If the Autonomous Periodic Interrupt clock is enabled and routed here the I/O state is forced to output. • Signal priority: 100 LQFP: API_EXTCLK > GPO PB0 • 100 LQFP: The ECLK signal is mapped to this pin when used with the external clock function. The enabled ECLK signal forces the I/O state to an output. • Signal priority: 100 LQFP: ECLK > GPO 2.3.4 Pins PC7-0 • NOTE When using AMPM1, AMPP1 or DACU1 please refer to section 2.6.1, “Initialization”. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 163 Port Integration Module (S12GPIMV1) • When routing of ADC channels to PC4-PC0 is selected (PRR1[PRR1AN]=1) the related bit in the ADC Digital Input Enable Register (ATDDIEN) must be set to 1 to activate the digital input function on those pins not used as ADC inputs. If the external trigger source is one of the ADC channels, the digital input buffer of this channel is automatically enabled. Table 2-8. Port C Pins PC7-0 PC7 • 100 LQFP: The unbuffered analog output signal DACU1 of the DAC1 module is mapped to this pin if the DAC is operating in “unbuffered DAC” mode. If this pin is used with the DAC then the digital I/O function and pull device are disabled. • Signal priority: 100 LQFP: DACU1 > GPO PC6 • 100 LQFP: The non-inverting analog input signal AMPP1 of the DAC1 module is mapped to this pin if the DAC is operating in “unbuffered DAC with operational amplifier” or “operational amplifier only” mode. If this pin is used with the DAC then the digital input buffer is disabled. • Signal priority: 100 LQFP: GPO PC5 • 100 LQFP: The inverting analog input signal AMPM1 of the DAC1 module is mapped to this pin if the DAC is operating in “unbuffered DAC with operational amplifier” or “operational amplifier only” mode. If this pin is used with the DAC then the digital input buffer is disabled. • Signal priority: 100 LQFP: GPO PC4-PC2 • 100 LQFP: If routing is active (PRR1[PRR1AN]=1) the ADC analog input channel signals AN15-13 and their related digital trigger inputs are mapped to these pins. The routed ADC function has no effect on the output state. Refer to NOTE/2-163 for input buffer control. • Signal priority: 100 LQFP: GPO PC1-PC0 • 100 LQFP: If routing is active (PRR1[PRR1AN]=1) the ADC analog input channel signals AN11-10 and their related digital trigger inputs are mapped to these pins. The routed ADC function has no effect on the output state. Refer to NOTE/2-163 for input buffer control. • Signal priority: 100 LQFP: GPO MC9S12G Family Reference Manual Rev.1.28 164 NXP Semiconductors Port Integration Module (S12GPIMV1) 2.3.5 Pins PD7-0 Table 2-9. Port D Pins PD7-0 PD7-PD0 2.3.6 • These pins feature general-purpose I/O functionality only. Pins PE1-0 Table 2-10. Port E Pins PE1-0 PE1 • If the CPMU OSC function is active this pin is used as XTAL signal and the pulldown device is disabled. • 20 TSSOP: The SCI0 TXD signal is mapped to this pin when used with the SCI function. If the SCI0 TXD signal is enabled and routed here the I/O state will depend on the SCI0 configuration. • 20 TSSOP: The TIM channel 3 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. • 20 TSSOP: The PWM channel 1 signal is mapped to this pin when used with the PWM function. The enabled PWM channel forces the I/O state to be an output. • 20 TSSOP: The ADC ETRIG1 signal is mapped to this pin when used with the ADC function. The enabled external trigger function has no effect on the I/O state. Refer to Section 2.6.4, “ADC External Triggers ETRIG3-0”. • Signal priority: 20 TSSOP: XTAL > TXD0 > IOC3 > PWM1 > GPO Others: XTAL > GPO PE0 • If the CPMU OSC function is active this pin is used as EXTAL signal and the pulldown device is disabled. • 20 TSSOP: The SCI0 RXD signal is mapped to this pin when used with the SCI function. If the SCI0 RXD signal is enabled and routed here the I/O state will be forced to input. • 20 TSSOP: The TIM channel 2 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. • 20 TSSOP: The PWM channel 0 signal is mapped to this pin when used with the PWM function. The enabled PWM channel forces the I/O state to be an output. • 20 TSSOP: The ADC ETRIG0 signal is mapped to this pin when used with the ADC function. The enabled external trigger function has no effect on the I/O state. Refer to Section 2.6.4, “ADC External Triggers ETRIG3-0”. • Signal priority: 20 TSSOP: EXTAL > RXD0 > IOC2 > PWM0 > GPO Others: EXTAL > GPO 2.3.7 Pins PT7-0 Table 2-11. Port T Pins PT7-0 PT7-PT6 • 64/100 LQFP: The TIM channels 7 and 6 signal are mapped to these pins when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. • Signal priority: 64/100 LQFP: IOC7-6 > GPO PT5 • 48/64/100 LQFP: The TIM channel 5 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. If the ACMP timer link is enabled this pin is disconnected from the timer input so that it can still be used as general-purpose I/O or as timer output. The use case for the ACMP timer link requires the timer input capture function to be enabled. • Signal priority: 48/64/100 LQFP: IOC5 > GPO MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 165 Port Integration Module (S12GPIMV1) Table 2-11. Port T Pins PT7-0 (continued) PT4 • 48/64/100 LQFP: The TIM channel 4 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. • Signal priority: 48/64/100 LQFP: IOC4 > GPO PT3-PT2 • Except 20 TSSOP: The TIM channels 3 and 2 signal are mapped to these pins when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. • Signal priority: Except 20 TSSOP: IOC3-2 > GPO PT1 • Except 100 LQFP: The IRQ signal is mapped to this pin when used with the IRQ interrupt function. If enabled (IRQCR[IRQEN]=1) the I/O state of the pin is forced to be an input. • The TIM channel 1 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. • Signal priority: 100 LQFP: IOC1 > GPO Others: IRQ > IOC1 > GPO PT0 • Except 100 LQFP: The XIRQ signal is mapped to this pin when used with the XIRQ interrupt function.The interrupt is enabled by clearing the X mask bit in the CPU Condition Code register. The I/O state of the pin is forced to input level upon the first clearing of the X bit and held in this state even if the bit is set again. A STOP or WAIT recovery with the X bit set (refer to CPU12/CPU12X Reference Manual) is not available. • The TIM channel 0 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. • Signal priority: 100 LQFP: IOC0 > GPO Others: XIRQ > IOC0 > GPO MC9S12G Family Reference Manual Rev.1.28 166 NXP Semiconductors Port Integration Module (S12GPIMV1) 2.3.8 Pins PS7-0 Table 2-12. Port S Pins PS7-0 PS7 • The SPI0 SS signal is mapped to this pin when used with the SPI function. Depending on the configuration of the enabled SPI0 the I/O state is forced to be input or output. • 20 TSSOP: The SCI0 TXD signal is mapped to this pin when used with the SCI function. If the SCI0 TXD signal is enabled and routed here the I/O state will depend on the SCI0 configuration. • 20 TSSOP: The PWM channel 3 signal is mapped to this pin when used with the PWM function. If the PWM channel is enabled and routed here the I/O state is forced to output.The enabled PWM channel forces the I/O state to be an output. • 32 LQFP: The PWM channel 5 signal is mapped to this pin when used with the PWM function. The enabled PWM channel forces the I/O state to be an output. • 64/48/32/20 LQFP: The ECLK signal is mapped to this pin when used with the external clock function. If the ECLK output is enabled the I/O state will be forced to output. • The API_EXTCLK signal is mapped to this pin when used with the external clock function. If the Autonomous Periodic Interrupt clock is enabled and routed here the I/O state is forced to output. • 20 TSSOP: The ADC ETRIG3 signal is mapped to this pin if PWM channel 3 is routed here. The enabled external trigger function has no effect on the I/O state. Refer to Section 2.6.4, “ADC External Triggers ETRIG3-0”. • Signal priority: 20 TSSOP: SS0 > TXD0 > PWM3 > ECLK > API_EXTCLK > GPO 32 LQFP: SS0 > PWM5 > ECLK > API_EXTCLK > GPO 48/64 LQFP: SS0 > ECLK > API_EXTCLK > GPO 100 LQFP: SS0 > API_EXTCLK > GPO PS6 • The SPI0 SCK signal is mapped to this pin when used with the SPI function. Depending on the configuration of the enabled SPI0 the I/O state is forced to be input or output. • 20 TSSOP: The TIM channel 3 signal is mapped to this pin when used with the timer function. If the TIM output compare signal is enabled and routed here the I/O state will be forced to output. • 32 LQFP: The TIM channel 5 signal is mapped to this pin when used with the timer function. If the TIM output compare signal is enabled and routed here the I/O state will be forced to output. If the ACMP timer link is enabled this pin is disconnected from the timer input so that it can still be used as general-purpose I/O or as timer output. The use case for the ACMP timer link requires the timer input capture function to be enabled. • Signal priority: 20 TSSOP: SCK0 > IOC3 > GPO 32 LQFP: SCK0 > IOC5 > GPO Others: SCK0 > GPO PS5 • The SPI0 MOSI signal is mapped to this pin when used with the SPI function. Depending on the configuration of the enabled SPI0 the I/O state is forced to be input or output. • 20 TSSOP: The TIM channel 2 signal is mapped to this pin when used with the timer function. If the TIM output compare signal is enabled and routed here the I/O state will be forced to output. • 32 LQFP: The TIM channel 4 signal is mapped to this pin when used with the timer function. If the TIM output compare signal is enabled and routed here the I/O state will be forced to output. • Signal priority: 20 TSSOP: MOSI0 > IOC2 > GPO 32 LQFP: MOSI0 > IOC4 > GPO Others: MOSI0 > GPO MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 167 Port Integration Module (S12GPIMV1) Table 2-12. Port S Pins PS7-0 (continued) PS4 • The SPI0 MISO signal is mapped to this pin when used with the SPI function. Depending on the configuration of the enabled SPI0 the I/O state is forced to be input or output. • 20 TSSOP: The SCI0 RXD signal is mapped to this pin when used with the SCI function. If the SCI0 RXD signal is enabled and routed here the I/O state will be forced to input. • 20 TSSOP: The PWM channel 2 signal is mapped to this pin when used with the PWM function. If the PWM channel is enabled and routed here the I/O state is forced to output. • 32 LQFP: The PWM channel 4 signal is mapped to this pin when used with the PWM function. The enabled PWM channel forces the I/O state to be an output. • 20 TSSOP: The ADC ETRIG2 signal is mapped to this pin if PWM channel 2 is routed here. The enabled external trigger function has no effect on the I/O state. Refer to Section 2.6.4, “ADC External Triggers ETRIG3-0”. • Signal priority: 20 TSSOP: MISO0 > RXD0 > PWM2 > GPO 32 LQFP: MISO0 > PWM4 > GPO Others: MISO0 > GPO PS3 • Except 20 TSSOP and 32 LQFP: The SCI1 TXD signal is mapped to this pin when used with the SCI function. If the SCI1 TXD signal is enabled the I/O state will depend on the SCI1 configuration. • Signal priority: 48/64/100 LQFP: TXD1 > GPO PS2 • Except 20 TSSOP and 32 LQFP: The SCI1 RXD signal is mapped to this pin when used with the SCI function. If the SCI1 RXD signal is enabled the I/O state will be forced to be input. • Signal priority: 20 TSSOP and 32 LQFP: GPO Others: RXD1 > GPO PS1 • Except 20 TSSOP: The SCI0 TXD signal is mapped to this pin when used with the SCI function. If the SCI0 TXD signal is enabled the I/O state will depend on the SCI0 configuration. • Signal priority: Except 20 TSSOP: TXD0 > GPO PS0 • Except 20 TSSOP: The SCI0 RXD signal is mapped to this pin when used with the SCI function. If the SCI0 RXD signal is enabled the I/O state will be forced to be input. • Signal priority: 20 TSSOP: GPO Others: RXD0 > GPO MC9S12G Family Reference Manual Rev.1.28 168 NXP Semiconductors Port Integration Module (S12GPIMV1) 2.3.9 Pins PM3-0 Table 2-13. Port M Pins PM3-0 PM3 • 64/100 LQFP: The SCI2 TXD signal is mapped to this pin when used with the SCI function. If the SCI2 TXD signal is enabled the I/O state will depend on the SCI2 configuration. • Signal priority: 64/100 LQFP: TXD2 > GPO PM2 • 64/100 LQFP: The SCI2 RXD signal is mapped to this pin when used with the SCI function. If the SCI2 RXD signal is enabled the I/O state will be forced to be input. • Signal priority: 64/100 LQFP: RXD2 > GPO PM1 • Except 20 TSSOP: The TXCAN signal is mapped to this pin when used with the CAN function. The enabled CAN forces the I/O state to be an output. • 32 LQFP: The SCI1 TXD signal is mapped to this pin when used with the SCI function. If the SCI1 TXD signal is enabled the I/O state will depend on the SCI1 configuration. • 48 LQFP: The SCI2 TXD signal is mapped to this pin when used with the SCI function. If the SCI2 TXD signal is enabled the I/O state will depend on the SCI2 configuration. • Signal priority: 32 LQFP: TXCAN > TXD1 > GPO 48 LQFP: TXCAN > TXD2 > GPO 64/100 LQFP: TXCAN > GPO PM0 • Except 20 TSSOP: The RXCAN signal is mapped to this pin when used with the CAN function. The enabled CAN forces the I/O state to be an input. If CAN is active the selection of a pulldown device on the RXCAN input has no effect. • 32 LQFP: The SCI1 RXD signal is mapped to this pin when used with the SCI function. The enabled SCI1 RXD signal forces the I/O state to an input. • 48 LQFP: The SCI2 RXD signal is mapped to this pin when used with the SCI function. The enabled SCI2 RXD signal forces the I/O state to an input. • Signal priority: 32 LQFP: RXCAN > RXD1 > GPO 48 LQFP: RXCAN > RXD2 > GPO 64/100 LQFP: RXCAN > GPO 2.3.10 Pins PP7-0 Table 2-14. Port P Pins PP7-0 PP7-PP6 • 64/100 LQFP: The PWM channels 7 and 6 signal are mapped to these pins when used with the PWM function. The enabled PWM channel forces the I/O state to be an output. • 64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: 64/100 LQFP: PWM > GPO PP5-PP4 • 48/64/100 LQFP: The PWM channels 5 and 4 signal are mapped to these pins when used with the PWM function. The enabled PWM channel forces the I/O state to be an output. • 48/64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: 48/64/100 LQFP: PWM > GPO MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 169 Port Integration Module (S12GPIMV1) Table 2-14. Port P Pins PP7-0 (continued) PP3-PP2 • Except 20 TSSOP: The PWM channels 3 and 2 signal are mapped to these pins when used with the PWM function. The enabled PWM channel forces the I/O state to be an output. • Except 20 TSSOP: The ADC ETRIG 3 and 2 signal are mapped to these pins when used with the ADC function. The enabled external trigger function has no effect on the I/O state. Refer to Section 2.6.4, “ADC External Triggers ETRIG3-0”. • Except 20 TSSOP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: Except 20 TSSOP: PWM > GPO PP1 • Except 20 TSSOP: The PWM channel 1 signal is mapped to this pin when used with the PWM function. The enabled PWM channel forces the I/O state to be an output. • Except 100 LQFP and 20 TSSOP: The ECLKX2 signal is mapped to this pin when used with the external clock function. The enabled ECLKX2 forces the I/O state to an output. • Except 20 TSSOP: The ADC ETRIG1 signal is mapped to this pin when used with the ADC function. The enabled external trigger function has no effect on the I/O state. Refer to Section 2.6.4, “ADC External Triggers ETRIG3-0”. • Except 20 TSSOP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: Except 100 LQFP and 20 TSSOP: PWM1 > ECLKX2 > GPO 100 LQFP: PWM1 > GPO PP0 • Except 20 TSSOP: The PWM channel 0 signal is mapped to this pin when used with the PWM function. The enabled PWM channel forces the I/O state to be an output. • Except 100 LQFP and 20 TSSOP: The API_EXTCLK signal is mapped to this pin when used with the external clock function. If the Autonomous Periodic Interrupt clock is enabled and routed here the I/O state is forced to output. • Except 20 TSSOP: The ADC ETRIG0 signal is mapped to this pin when used with the ADC function. The enabled external trigger function has no effect on the I/O state. Refer to Section 2.6.4, “ADC External Triggers ETRIG3-0”. • Except 20 TSSOP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: Except 100 LQFP and 20 TSSOP: PWM0 > API_EXTCLK > GPO 100 LQFP: PWM0 > GPO MC9S12G Family Reference Manual Rev.1.28 170 NXP Semiconductors Port Integration Module (S12GPIMV1) 2.3.11 Pins PJ7-0 Table 2-15. Port J Pins PJ7-0 PJ7 • 64/100 LQFP: The SPI2 SS signal is mapped to this pin when used with the SPI function. Depending on the configuration of the enabled SPI2 the I/O state is forced to be input or output. • 64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: 64/100 LQFP: SS2 > GPO PJ6 • 64/100 LQFP: The SPI2 SCK signal is mapped to this pin when used with the SPI function. Depending on the configuration of the enabled SPI2 the I/O state is forced to be input or output. • 64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: 64/100 LQFP: SCK2 > GPO PJ5 • 64/100 LQFP: The SPI2 MOSI signal is mapped to this pin when used with the SPI function. Depending on the configuration of the enabled SPI2 the I/O state is forced to be input or output. • 64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: 64/100 LQFP: MOSI2 > GPO PJ4 • 64/100 LQFP: The SPI2 MISO signal is mapped to this pin when used with the SPI function.Depending on the configuration of the enabled SPI2 the I/O state is forced to be input or output. • 64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: 64/100 LQFP: MISO2 > GPO PJ3 • Except 20 TSSOP and 32 LQFP: The SPI1 SS signal is mapped to this pin when used with the SPI function. Depending on the configuration of the enabled SPI1 the I/O state is forced to be input or output. • 48 LQFP: The PWM channel 7 signal is mapped to this pin when used with the PWM function. The enabled PWM channel forces the I/O state to be an output. • Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: 48 LQFP: SS1 > PWM7 > GPO 64/100 LQFP: SS1 > GPO PJ2 • Except 20 TSSOP and 32 LQFP: The SPI1 SCK signal is mapped to this pin when used with the SPI function. Depending on the configuration of the enabled SPI1 the I/O state is forced to be input or output. • 48 LQFP: The TIM channel 7 signal is mapped to this pin when used with the TIM function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output. • Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: 48 LQFP: SCK1 > IOC7 > GPO 64/100 LQFP: SCK1 > GPO MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 171 Port Integration Module (S12GPIMV1) Table 2-15. Port J Pins PJ7-0 (continued) PJ1 • Except 20 TSSOP and 32 LQFP: The SPI1 MOSI signal is mapped to this pin when used with the SPI function. Depending on the configuration of the enabled SPI1 the I/O state is forced to be input or output. • 48 LQFP: The TIM channel 6 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output. • Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: 48 LQFP: MOSI1 > IOC6 > GPO 64/100 LQFP: MOSI1 > GPO PJ0 • Except 20 TSSOP and 32 LQFP: The SPI1 MISO signal is mapped to this pin when used with the SPI function. Depending on the configuration of the enabled SPI1 the I/O state is forced to be input or output. • 48 LQFP: The PWM channel 6 signal is mapped to this pin when used with the PWM function. The enabled PWM channel forces the I/O state to be an output. • Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: 48 LQFP: MISO1 > PWM6 > GPO 64/100 LQFP: MISO1 > GPO 2.3.12 Pins AD15-0 NOTE The following sources contribute to enable the input buffers on port AD: • Digital input enable register bits set for each individual pin in ADC • External trigger function of ADC enabled on ADC channel • ADC channels routed to port C freeing up pins • Digital input enable register set bit in and ACMP Taking the availability of the different sources on each pin into account the following logic equation must be true to activate the digital input buffer for general-purpose input use: IBEx = ( (ATDDIENH/L[IENx]=1) OR (ATDCTL1[ETRIGSEL]=0 AND ATDCTL2[ETRIGE]=1) OR (PRR1[PRR1AN]=1) ) AND (ACDIEN=1) Eqn. 2-1 MC9S12G Family Reference Manual Rev.1.28 172 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-16. Port AD Pins AD15-8 PAD15 • 64/100 LQFP: The unbuffered analog output signal DACU0 of the DAC0 module is mapped to this pin if the DAC is operating in “unbuffered DAC” mode. If this pin is used with the DAC then the digital I/O function and pull device are disabled. • 64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN15 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • 64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: 64/100 LQFP: DACU0 > GPO PAD14 • 64/100 LQFP: The non-inverting analog input signal AMPP0 of the DAC0 module is mapped to this pin if the DAC is operating in “unbuffered DAC with operational amplifier” or “operational amplifier only” mode. If this pin is used with the DAC then the digital input buffer is disabled. • 64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN14 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • 64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: 64/100 LQFP: GPO PAD13 • 64/100 LQFP: The inverting analog input signal AMPM0 of the DAC0 module is mapped to this pin if the DAC is operating in “unbuffered DAC with operational amplifier” or “operational amplifier only” mode. If this pin is used with the DAC then the digital input buffer is disabled. • 64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN13 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • 64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: 64/100 LQFP: GPO PAD12 • 64/100 LQFP: The ADC analog input channel signal AN12 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • 64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: 64/100 LQFP: GPO MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 173 Port Integration Module (S12GPIMV1) Table 2-16. Port AD Pins AD15-8 PAD11 • 64/100 LQFP: The buffered analog output signal AMP0 of the DAC0 module is mapped to this pin if the DAC is operating in “buffered DAC”, “unbuffered DAC with operational amplifier” or “operational amplifier only” mode. If this pin is used with the DAC then the digital I/O function and pull device are disabled. • 48 LQFP: The buffered analog output signal AMP0 of the DAC0 module is mapped to this pin if the DAC is operating in “buffered DAC”, “unbuffered DAC with operational amplifier”1 or “operational amplifier only” mode. If this pin is used with the DAC then the digital I/O function and pull device are disabled. • 48 LQFP: The unbuffered analog output signal DACU0 of the DAC0 module is mapped to this pin if the DAC is operating in “unbuffered DAC” mode. If this pin is used with the DAC then the digital output function and pull device are disabled. • 48/64 LQFP: The inverting input signal ACMPM of the analog comparator is mapped to this pin when used with the ACMP function. The ACMP function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • 48/64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN11 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • 48/64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: 48 LQFP: AMP0 > DACU0 > GPO 64/100 LQFP: AMP0 > GPO PAD10 • 100 LQFP: The buffered analog output signal AMP1 of the DAC1 module is mapped to this pin if the DAC is operating in “buffered DAC”, “unbuffered DAC with operational amplifier” or “operational amplifier only” mode. If this pin is used with the DAC then the digital I/O function and pull device are disabled. • 48/64 LQFP: The buffered analog output signal AMP1 of the DAC1 module is mapped to this pin if the DAC is operating in “buffered DAC”, “unbuffered DAC with operational amplifier”1 or “operational amplifier only” mode. If this pin is used with the DAC then the digital output function and pull device are disabled. • 48/64 LQFP: The unbuffered analog output signal DACU1 of the DAC1 module is mapped to this pin if the DAC is operating in “unbuffered DAC” mode. If this pin is used with the DAC then the digital output function and pull device are disabled. • 48/64 LQFP: The non-inverting input signal ACMPP of the analog comparator is mapped to this pin when used with the ACMP function. The ACMP function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • 48/64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN10 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • 48/64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: 48/64 LQFP: AMP1 > DACU1 > GPO 100 LQFP: AMP1 > GPO MC9S12G Family Reference Manual Rev.1.28 174 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-16. Port AD Pins AD15-8 PAD9 • 48/64 LQFP: The ACMPO signal of the analog comparator is mapped to this pin when used with the ACMP function. If the ACMP output is enabled (ACMPC[ACOPE]=1) the I/O state will be forced to output. • 48/64/100 LQFP: The ADC analog input channel signal AN9 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • 48/64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: 48 LQFP: ACMPO > GPO 64/100 LQFP: GPO PAD8 • 48/64/100 LQFP: The ADC analog input channel signal AN8 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • 48/64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: 48/64/100 LQFP: GPO 1 AMP output takes precedence over DACU output on shared pin. Table 2-17. Port AD Pins AD7-0 PAD7 • 32 LQFP: The inverting input signal ACMPM of the analog comparator is mapped to this pin when used with the ACMP function. The ACMP function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • Except 20 TSSOP: The ADC analog input channel signal AN7 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • Except 20 TSSOP: Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: Except 20 TSSOP: GPO PAD6 • 32 LQFP: The non-inverting input signal ACMPP of the analog comparator is mapped to this pin when used with the ACMP function. The ACMP function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • Except 20 TSSOP: The ADC analog input channel signal AN6 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • Except 20 TSSOP: Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: Except 20 TSSOP: GPO MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 175 Port Integration Module (S12GPIMV1) Table 2-17. Port AD Pins AD7-0 (continued) PAD5 • 32 LQFP: The ACMPO signal of the analog comparator is mapped to this pin when used with the ACMP function. If the ACMP output is enabled (ACMPC[ACOPE]=1) the I/O state will be forced to output. • 20 TSSOP: The inverting input signal ACMPM of the analog comparator is mapped to this pin when used with the ACMP function. The ACMP function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • The ADC analog input channel signal AN5 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • 20 TSSOP: The SCI0 TXD signal is mapped to this pin. If the SCI0 TXD signal is enabled the I/O state will depend on the SCI0 configuration. • 20 TSSOP: The TIM channel 3 signal is mapped to this pin. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. • 20 TSSOP: The PWM channel 3 signal is mapped to this pin. If the PWM channel is enabled and routed here the I/O state is forced to output. • 20 TSSOP: The ADC ETRIG3 signal is mapped to this pin if PWM channel 3 is routed here. The enabled external trigger function has no effect on the I/O state. Refer to Section 2.6.4, “ADC External Triggers ETRIG3-0”. • Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: 32 LQFP: ACMPO > GPO 20 TSSOP: TXD0 > IOC3 > PWM3 > GPO Others: GPO PAD4 • 20 TSSOP: The non-inverting input signal ACMPP of the analog comparator is mapped to this pin when used with the ACMP function. The ACMP function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • The ADC analog input channel signal AN4 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • 20 TSSOP: The SCI0 RXD signal is mapped to this pin. If the SCI0 RXD signal is enabled and routed here the I/O state will be forced to input. • 20 TSSOP: The TIM channel 2 signal is mapped to this pin. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. • 20 TSSOP: The PWM channel 2 signal is mapped to this pin. If the PWM channel is enabled and routed here the I/O state is forced to output. • 20 TSSOP: The ADC ETRIG2 signal is mapped to this pin if PWM channel 2 is routed here. The enabled external trigger function has no effect on the I/O state. Refer to Section 2.6.4, “ADC External Triggers ETRIG3-0”. • Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: 20 TSSOP: RXD0 > IOC2 > PWM2 > GPO Others: GPO MC9S12G Family Reference Manual Rev.1.28 176 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-17. Port AD Pins AD7-0 (continued) PAD3 • 20 TSSOP: The ACMPO signal of the analog comparator is mapped to this pin when used with the ACMP function. If the ACMP output is enabled (ACMPC[ACOPE]=1) the I/O state will be forced to output. • The ADC analog input channel signal AN3 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: 20 TSSOP: ACMPO > GPO Others: GPO PAD2-PAD0 • The ADC analog input channel signals AN2-0 and their related digital trigger inputs are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: GPO MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 177 Port Integration Module (S12GPIMV1) 2.4 PIM Ports - Memory Map and Register Definition This section provides a detailed description of all PIM registers. 2.4.1 Memory Map Table 2-18 shows the memory maps of all groups (for definitions see Table 2-2). Addresses 0x0000 to 0x0007 are only implemented in group G1 otherwise reserved. Table 2-18. Block Memory Map (0x0000-0x027F) Port (A) (B) (C) (D) E (A) (B) (C) (D) E Global Address Register Access Reset Value Section/Page 0x0000 PORTA—Port A Data Register1 R/W 0x00 2.4.3.1/2-197 0x0001 PORTB—Port B Data Register1 R/W 0x00 2.4.3.2/2-197 0x0002 DDRA—Port A Data Direction Register1 R/W 0x00 2.4.3.3/2-198 0x0003 DDRB—Port B Data Direction Register1 R/W 0x00 2.4.3.4/2-199 0x0004 PORTC—Port C Data Register1 R/W 0x00 2.4.3.5/2-199 0x0005 PORTD—Port D Data Register1 R/W 0x00 2.4.3.6/2-200 0x0006 DDRC—Port C Data Direction Register1 R/W 0x00 2.4.3.7/2-201 0x0007 DDRD—Port D Data Direction Register1 R/W 0x00 2.4.3.8/2-201 0x0008 PORTE—Port E Data Register R/W 0x00 0x0009 DDRE—Port E Data Direction Register R/W 0x00 0x000A : 0x000B Non-PIM address range2 - - - 0x000C PUCR—Pull Control Register R/W 0x50 2.4.3.11/2-203 0x000D Reserved R 0x00 0x000E : 0x001B Non-PIM address range2 - - - 0x001C ECLKCTL—ECLK Control Register R/W 0xC0 2.4.3.12/2-205 0x001D Reserved R 0x00 0x001E IRQCR—IRQ Control Register R/W 0x00 0x001F Reserved R 0x00 - - 0x0020 : 0x023F Non-PIM address range2 2.4.3.13/2-205 - MC9S12G Family Reference Manual Rev.1.28 178 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-18. Block Memory Map (0x0000-0x027F) (continued) Port Global Address T 0x0240 S M P Register Access Reset Value Section/Page PTT—Port T Data Register R/W 0x00 2.4.3.15/2-207 0x0241 PTIT—Port T Input Register R 3 2.4.3.16/2-207 0x0242 DDRT—Port T Data Direction Register R/W 0x00 2.4.3.17/2-208 0x0243 Reserved R 0x00 0x0244 PERT—Port T Pull Device Enable Register R/W 0x00 2.4.3.18/2-209 0x0245 PPST—Port T Polarity Select Register R/W 0x00 2.4.3.19/2-210 0x0246 Reserved R 0x00 0x0247 Reserved R 0x00 0x0248 PTS—Port S Data Register R/W 0x00 2.4.3.20/2-210 0x0249 PTIS—Port S Input Register R 3 2.4.3.21/2-211 0x024A DDRS—Port S Data Direction Register R/W 0x00 2.4.3.22/2-211 0x024B Reserved R 0x00 0x024C PERS—Port S Pull Device Enable Register R/W 0xFF 2.4.3.23/2-212 0x024D PPSS—Port S Polarity Select Register R/W 0x00 2.4.3.24/2-212 0x024E WOMS—Port S Wired-Or Mode Register R/W 0x00 2.4.3.25/2-213 0x024F PRR0—Pin Routing Register 04 R/W 0x00 2.4.3.26/2-213 0x0250 PTM—Port M Data Register R/W 0x00 2.4.3.27/2-215 0x0251 PTIM—Port M Input Register R 3 2.4.3.29/2-216 0x0252 DDRM—Port M Data Direction Register R/W 0x00 2.4.3.29/2-216 0x0253 Reserved R 0x00 0x0254 PERM—Port M Pull Device Enable Register R/W 0x00 2.4.3.30/2-217 0x0255 PPSM—Port M Polarity Select Register R/W 0x00 2.4.3.31/2-218 0x0256 WOMM—Port M Wired-Or Mode Register R/W 0x00 2.4.3.32/2-218 0x0257 PKGCR—Package Code Register R/W 5 2.4.3.33/2-219 0x0258 PTP—Port P Data Register R/W 0x00 2.4.3.34/2-220 0x0259 PTIP—Port P Input Register R 3 2.4.3.35/2-221 0x025A DDRP—Port P Data Direction Register R/W 0x00 2.4.3.36/2-222 0x025B Reserved R 0x00 0x025C PERP—Port P Pull Device Enable Register R/W 0x00 2.4.3.37/2-222 0x025D PPSP—Port P Polarity Select Register R/W 0x00 2.4.3.38/2-223 0x025E PIEP—Port P Interrupt Enable Register R/W 0x00 2.4.3.39/2-224 0x025F PIFP—Port P Interrupt Flag Register R/W 0x00 2.4.3.40/2-224 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 179 Port Integration Module (S12GPIMV1) Table 2-18. Block Memory Map (0x0000-0x027F) (continued) Port Global Address 0x0260 Register Reserved for ACMP available in group G2 and G3 0x0261 J AD Access Reset Value Section/Page R(/W) 0x00 (ACMP) R(/W) 0x00 (ACMP) R 0x00 0x0262 : 0x0266 Reserved 0x0268 PTJ—Port J Data Register R/W 0x00 2.4.3.42/2-226 0x0269 PTIJ—Port J Input Register R 3 2.4.3.43/2-227 0x026A DDRJ—Port J Data Direction Register R/W 0x00 2.4.3.44/2-227 0x026B Reserved R 0x00 0x026C PERJ—Port J Pull Device Enable Register R/W 0xFF (G1,G2) 0x0F (G3) 2.4.3.45/2-228 0x026D PPSJ—Port J Polarity Select Register R/W 0x00 2.4.3.46/2-229 0x026E PIEJ—Port J Interrupt Enable Register R/W 0x00 2.4.3.47/2-229 0x026F PIFJ—Port J Interrupt Flag Register R/W 0x00 2.4.3.48/2-230 0x0270 PT0AD—Port AD Data Register R/W 0x00 2.4.3.49/2-231 0x0271 PT1AD—Port AD Data Register R/W 0x00 2.4.3.50/2-231 0x0272 PTI0AD—Port AD Input Register R 3 2.4.3.51/2-232 0x0273 PTI1AD—Port AD Input Register R 3 2.4.3.54/2-233 0x0274 DDR0AD—Port AD Data Direction Register R/W 0x00 2.4.3.53/2-233 0x0275 DDR1AD—Port AD Data Direction Register R/W 0x00 2.4.3.54/2-233 0x0276 Reserved for RVACTL on G(A)240 and G(A)192 only R(/W) 0x00 (RVA) 0x0277 PRR1—Pin Routing Register 16 R/W 0x00 2.4.3.56/2-234 0x0278 PER0AD—Port AD Pull Device Enable Register R/W 0x00 2.4.3.57/2-235 0x0279 PER1AD—Port AD Pull Device Enable Register R/W 0x00 2.4.3.58/2-236 0x027A PPS0AD—Port AD Polarity Select Register R/W 0x00 2.4.3.59/2-236 0x027B PPS1AD—Port AD Polarity Select Register R/W 0x00 2.4.3.60/2-237 0x027C PIE0AD—Port AD Interrupt Enable Register R/W 0x00 2.4.3.61/2-238 0x027D PIE1AD—Port AD Interrupt Enable Register R/W 0x00 2.4.3.62/2-238 0x027E PIF0AD—Port AD Interrupt Flag Register R/W 0x00 2.4.3.63/2-239 0x027F PIF1AD—Port AD Interrupt Flag Register R/W 0x00 2.4.3.64/2-240 1 Available in group G1 only. In any other case this address is reserved. Refer to device memory map to determine related module. 3 Read always returns logic level on pins. 4 Routing takes only effect if the PKGCR is set to 20 TSSOP. 2 MC9S12G Family Reference Manual Rev.1.28 180 NXP Semiconductors Port Integration Module (S12GPIMV1) 5 6 Preset by factory. Routing register only available on G(A)240 and G(A)192 only. Takes only effect if the PKGCR is set to 100 LQFP. 2.4.2 Register Map The following tables show the individual register maps of groups G1 (Table 2-19), G2 (Table 2-20) and G3 (Table 2-21). NOTE To maintain SW compatibility write data to unimplemented register bits must be zero. 2.4.2.1 Block Register Map (G1) Table 2-19. Block Register Map (G1) Global Address Register Name 0x0000 PORTA W 0x0001 PORTB W 0x0002 DDRA R R R W 0x0003 DDRB W 0x0004 PORTC W 0x0005 PORTD 0x0006 DDRC R R R W R W 0x0007 DDRD R 0x0008 PORTE R 0x0009 DDRE Bit 7 6 5 4 3 2 1 Bit 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 PE1 PE0 0 0 0 0 0 0 DDRE1 DDRE0 W R W = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 181 Port Integration Module (S12GPIMV1) Table 2-19. Block Register Map (G1) (continued) Global Address Register Name 0x000A–0x000B Non-PIM Address Range Bit 7 0x000D Reserved W R R R W 0x001E IRQCR W R R R W 0 BKPUE 0 0 0 1 Bit 0 PDPEE PUPDE PUPCE PUPBE PUPAE 0 0 0 0 0 Non-PIM Address Range NECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 0 0 0 0 0 0 0 0 IRQE IRQEN 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Non-PIM Address Range W W 0x0241 PTIT W R R R W 0x0243 Reserved W 0x0244 PERT W 0x0245 PPST 2 R 0x0240 PTT 0x0242 DDRT 0 W W 0x0020–0x023F Non-PIM Address Range 3 R 0x001D Reserved 0x001F Reserved 4 Non-PIM Address Range W W 0x001C ECLKCTL 5 R 0x000C PUCR 0x000E–0x001B Non-PIM Address Range 6 R R R W PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 0 0 0 0 0 0 0 0 PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.28 182 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-19. Block Register Map (G1) (continued) Global Address Register Name 0x0246 Reserved R W 0x0248 PTS W 0x024A DDRS R R R R W W 0x024C PERS W R R R W 0x024E WOMS W 0x024F PRR0 W 0x0250 PTM R R R W 0x0252 DDRM W 0x0254 PERM 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 0 0 0 0 0 0 0 0 PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 PRR0P3 PRR0P2 PRR0T31 PRR0T30 PRR0T21 PRR0T20 PRR0S1 PRR0S0 0 0 0 0 PTM3 PTM2 PTM1 PTM0 0 0 0 0 PTIM3 PTIM2 PTIM1 PTIM0 0 0 0 0 DDRM3 DDRM2 DDRM1 DDRM0 0 0 0 0 0 0 0 0 0 0 0 0 PERM3 PERM2 PERM1 PERM0 W 0x0251 PTIM 0x0253 Reserved 5 W 0x024B Reserved 0x024D PPSS 6 W 0x0247 Reserved 0x0249 PTIS Bit 7 R R R W R W = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 183 Port Integration Module (S12GPIMV1) Table 2-19. Block Register Map (G1) (continued) Global Address Register Name 0x0255 PPSM R W 0x0257 PKGCR W R R R W 0x0259 PTIP W 0x025A DDRP W 0x025B Reserved R R R W 0x025D PPSP W 0x025F PIFP R R R W R W 0x0260–0x0267 Reserved W 0x0268 PTJ W 0x0269 PTIJ 0x026A DDRJ 5 4 3 2 1 Bit 0 0 0 0 0 PPSM3 PPSM2 PPSM1 PPSM0 0 0 0 0 WOMM3 WOMM2 WOMM1 WOMM0 0 0 0 0 PKGCR2 PKGCR1 PKGCR0 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 0 0 0 0 0 0 0 0 PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 0 0 0 0 0 0 0 0 PTJ7 PTJ6 PTJ5 PTJ4 PTJ3 PTJ2 PTJ1 PTJ0 PTIJ7 PTIJ6 PTIJ5 PTIJ4 PTIJ3 PTIJ2 PTIJ1 PTIJ0 DDRJ7 DDRJ6 DDRJ5 DDRJ4 DDRJ3 DDRJ2 DDRJ1 DDRJ0 APICLKS7 W 0x025C PERP 0x025E PIEP 6 W 0x0256 WOMM 0x0258 PTP Bit 7 R R R W R W = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.28 184 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-19. Block Register Map (G1) (continued) Global Address Register Name 0x026B Reserved Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 PERJ7 PERJ6 PERJ5 PERJ4 PERJ3 PERJ2 PERJ1 PERJ0 PPSJ7 PPSJ6 PPSJ5 PPSJ4 PPSJ3 PPSJ2 PPSJ1 PPSJ0 PIEJ7 PIEJ6 PIEJ5 PIEJ4 PIEJ3 PIEJ2 PIEJ1 PIEJ0 PIFJ7 PIFJ6 PIFJ5 PIFJ4 PIFJ3 PIFJ2 PIFJ1 PIFJ0 PT0AD7 PT0AD6 PT0AD5 PT0AD4 PT0AD3 PT0AD2 PT0AD1 PT0AD0 PT1AD7 PT1AD6 PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0 R PTI0AD7 PTI0AD6 PTI0AD5 PTI0AD4 PTI0AD3 PTI0AD2 PTI0AD1 PTI0AD0 PTI1AD6 PTI1AD5 PTI1AD4 PTI1AD3 PTI1AD2 PTI1AD1 PTI1AD0 R W 0x026C PERJ W 0x026D PPSJ W 0x026E PIEJ R R R W 0x026F PIFJ W 0x0270 PT0AD W 0x0271 PT1AD R R R W 0x0272 PTI0AD W 0x0273 PTI1AD W 0x0274 DDR0AD 0x0275 DDR1AD R PTI1AD7 R W R W 0x0276 Reserved W 0x0277 PRR1 W 0x0278 PER0AD 0x0279 PER1AD DDR0AD7 DDR0AD6 DDR0AD5 DDR0AD4 DDR0AD3 DDR0AD2 DDR0AD1 DDR0AD0 DDR1AD7 DDR1AD6 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0 R R R W R W Reserved for RVACTL on G(A)240 and G(A)192 0 0 0 0 0 0 0 PRR1AN PER0AD7 PER0AD6 PER0AD5 PER0AD4 PER0AD3 PER0AD2 PER0AD1 PER0AD0 PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 185 Port Integration Module (S12GPIMV1) Table 2-19. Block Register Map (G1) (continued) Global Address Register Name 0x027A PPS0AD R W 0x027B PPS1AD R W 0x027C PIE0AD W R 0x027D PIE1AD R W 0x027E PIF0AD R W 0x027F PIF1AD W R Bit 7 6 5 4 3 2 1 Bit 0 PPS0AD7 PPS0AD6 PPS0AD5 PPS0AD4 PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0 PPS1AD7 PPS1AD6 PPS1AD5 PPS1AD4 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0 PIE0AD7 PIE0AD6 PIE0AD5 PIE0AD4 PIE0AD3 PIE0AD2 PIE0AD1 PIE0AD0 PIE1AD7 PIE1AD6 PIE1AD5 PIE1AD4 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0 PIF0AD7 PIF0AD6 PIF0AD5 PIF0AD4 PIF0AD3 PIF0AD2 PIF0AD1 PIF0AD0 PIF1AD7 PIF1AD6 PIF1AD5 PIF1AD4 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0 = Unimplemented or Reserved 2.4.2.2 Block Register Map (G2) Table 2-20. Block Register Map (G2) Global Address Register Name 0x0000–0x0007 Reserved 0x0008 PORTE 0x0009 DDRE 0x000A–0x000B Non-PIM Address Range 0x000C PUCR 0x000D Reserved R Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PE1 PE0 0 0 0 0 0 0 DDRE1 DDRE0 W R W R W R Non-PIM Address Range W R 0 W R 0 BKPUE 0 0 0 PDPEE 0 0 0 0 0 0 0 0 0 W = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.28 186 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-20. Block Register Map (G2) (continued) Global Address Register Name 0x000E–0x001B Non-PIM Address Range 0x001C ECLKCTL 0x001D Reserved 0x001E IRQCR 0x001F Reserved 0x0020–0x023F Non-PIM Address Range 0x0240 PTT 0x0241 PTIT 0x0242 DDRT Bit 7 4 3 2 1 Bit 0 Non-PIM Address Range W R W R NECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 0 0 0 0 0 0 0 0 IRQE IRQEN 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W R W R W R Non-PIM Address Range W R W R PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 0 0 0 0 0 0 0 0 PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 W R W W 0x0244 PERT W R R R W 0x0246 Reserved W 0x0247 Reserved W 0x0248 PTS 5 R 0x0243 Reserved 0x0245 PPST 6 R R R W = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 187 Port Integration Module (S12GPIMV1) Table 2-20. Block Register Map (G2) (continued) Global Address Register Name 0x0249 PTIS R W 0x024B Reserved W 0x024D PPSS R R R W R W 0x024E WOMS W 0x024F PRR0 W 0x0250 PTM R R R W 0x0252 DDRM W R R R W 0x0255 PPSM W 0x0257 PKGCR 4 3 2 1 Bit 0 PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 0 0 0 0 0 0 0 0 PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 PRR0P3 PRR0P2 PRR0T31 PRR0T30 PRR0T21 PRR0T20 PRR0S1 PRR0S0 0 0 0 0 PTM3 PTM2 PTM1 PTM0 0 0 0 0 PTIM3 PTIM2 PTIM1 PTIM0 0 0 0 0 DDRM3 DDRM2 DDRM1 DDRM0 0 0 0 0 0 0 0 0 0 0 0 0 PERM3 PERM2 PERM1 PERM0 0 0 0 0 PPSM3 PPSM2 PPSM1 PPSM0 0 0 0 0 WOMM3 WOMM2 WOMM1 WOMM0 0 0 0 PKGCR2 PKGCR1 PKGCR0 W 0x0254 PERM 0x0256 WOMM 5 W 0x0251 PTIM 0x0253 Reserved 6 W 0x024A DDRS 0x024C PERS Bit 7 R R R W R W APICLKS7 0 = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.28 188 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-20. Block Register Map (G2) (continued) Global Address Register Name 0x0258 PTP R W 0x0259 PTIP W 0x025A DDRP W 0x025B Reserved R R R W 0x025D PPSP W R R R W 0x025F PIFP W 0x0260–0x0261 Reserved W 0x0262–0x0266 Reserved 0x0267 Reserved R R 4 3 2 1 Bit 0 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 0 0 0 0 0 0 0 0 PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 0 Reserved for ACMP 0 0 0 0 0 0 0 Reserved Reserved 0 0 0 0 0 PTJ7 PTJ6 PTJ5 PTJ4 PTJ3 PTJ2 PTJ1 PTJ0 PTIJ7 PTIJ6 PTIJ5 PTIJ4 PTIJ3 PTIJ2 PTIJ1 PTIJ0 DDRJ7 DDRJ6 DDRJ5 DDRJ4 DDRJ3 DDRJ2 DDRJ1 DDRJ0 0 0 0 0 0 0 0 0 W R W W 0x0269 PTIJ W 0x026B Reserved 5 R 0x0268 PTJ 0x026A DDRJ 6 W 0x025C PERP 0x025E PIEP Bit 7 R R R W R Reserved W = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 189 Port Integration Module (S12GPIMV1) Table 2-20. Block Register Map (G2) (continued) Global Address Register Name 0x026C PERJ Bit 7 6 5 4 3 2 1 Bit 0 PERJ7 PERJ6 PERJ5 PERJ4 PERJ3 PERJ2 PERJ1 PERJ0 PPSJ7 PPSJ6 PPSJ5 PPSJ4 PPSJ3 PPSJ2 PPSJ1 PPSJ0 PIEJ7 PIEJ6 PIEJ5 PIEJ4 PIEJ3 PIEJ2 PIEJ1 PIEJ0 PIFJ7 PIFJ6 PIFJ5 PIFJ4 PIFJ3 PIFJ2 PIFJ1 PIFJ0 PT0AD7 PT0AD6 PT0AD5 PT0AD4 PT0AD3 PT0AD2 PT0AD1 PT0AD0 PT1AD7 PT1AD6 PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0 R PTI0AD7 PTI0AD6 PTI0AD5 PTI0AD4 PTI0AD3 PTI0AD2 PTI0AD1 PTI0AD0 PTI1AD6 PTI1AD5 PTI1AD4 PTI1AD3 PTI1AD2 PTI1AD1 PTI1AD0 R W 0x026D PPSJ W 0x026E PIEJ W 0x026F PIFJ R R R W 0x0270 PT0AD W 0x0271 PT1AD W 0x0272 PTI0AD R R W 0x0273 PTI1AD W 0x0274 DDR0AD W 0x0275 DDR1AD 0x0276 Reserved R PTI1AD7 R R W R W 0x0278 PER0AD W 0x027A PPS0AD DDR1AD7 DDR1AD6 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0x0277 Reserved 0x0279 PER1AD DDR0AD7 DDR0AD6 DDR0AD5 DDR0AD4 DDR0AD3 DDR0AD2 DDR0AD1 DDR0AD0 R R R W R W PER0AD7 PER0AD6 PER0AD5 PER0AD4 PER0AD3 PER0AD2 PER0AD1 PER0AD0 PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 PPS0AD7 PPS0AD6 PPS0AD5 PPS0AD4 PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0 = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.28 190 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-20. Block Register Map (G2) (continued) Global Address Register Name 0x027B PPS1AD R W 0x027C PIE0AD R W 0x027D PIE1AD W R 0x027E PIF0AD R W 0x027F PIF1AD R W Bit 7 6 5 4 3 2 1 Bit 0 PPS1AD7 PPS1AD6 PPS1AD5 PPS1AD4 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0 PIE0AD7 PIE0AD6 PIE0AD5 PIE0AD4 PIE0AD3 PIE0AD2 PIE0AD1 PIE0AD0 PIE1AD7 PIE1AD6 PIE1AD5 PIE1AD4 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0 PIF0AD7 PIF0AD6 PIF0AD5 PIF0AD4 PIF0AD3 PIF0AD2 PIF0AD1 PIF0AD0 PIF1AD7 PIF1AD6 PIF1AD5 PIF1AD4 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0 = Unimplemented or Reserved 2.4.2.3 Block Register Map (G3) Table 2-21. Block Register Map (G3) Global Address Register Name 0x0000–0x0007 Reserved 0x0008 PORTE 0x0009 DDRE 0x000A–0x000B Non-PIM Address Range 0x000C PUCR 0x000D Reserved R Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PE1 PE0 0 0 0 0 0 0 DDRE1 DDRE0 W R W R W R Non-PIM Address Range W R 0 W R 0 BKPUE 0 0 0 PDPEE 0 0 0 0 0 0 0 0 0 W = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 191 Port Integration Module (S12GPIMV1) Table 2-21. Block Register Map (G3) (continued) Global Address Register Name 0x000E–0x001B Non-PIM Address Range Bit 7 0x001D Reserved W 0x0020–0x023F Non-PIM Address Range 0x0240 PTT 0x0241 PTIT 0x0242 DDRT R R R W R W 2 1 Bit 0 NECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 0 0 0 0 0 0 0 0 IRQE IRQEN 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Non-PIM Address Range W R 0 0 0 0 0 0 0 0 0 0 0 0 0 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 0 0 0 0 0 0 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 W R W R W W 0x0244 PERT W R R R W 0x0246 Reserved W 0x0247 Reserved W 0x0248 PTS 3 R 0x0243 Reserved 0x0245 PPST 4 Non-PIM Address Range W W 0x001F Reserved 5 R 0x001C ECLKCTL 0x001E IRQCR 6 R R R W = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.28 192 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-21. Block Register Map (G3) (continued) Global Address Register Name 0x0249 PTIS R W 0x024B Reserved W R R R W 0x024D PPSS W 0x024E WOMS W 0x024F PRR0 R R R W 0x0250 PTM W 0x0251 PTIM W 0x0252 DDRM 0x0253 Reserved R R R R 4 3 2 1 Bit 0 PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 0 0 0 0 0 0 0 0 PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 PRR0P3 PRR0P2 PRR0T31 PRR0T30 PRR0T21 PRR0T20 PRR0S1 PRR0S0 0 0 0 0 0 0 PTM1 PTM0 0 0 0 0 0 0 PTIM1 PTIM0 0 0 0 0 0 0 DDRM1 DDRM0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERM1 PERM0 0 0 0 0 0 0 PPSM1 PPSM0 0 0 0 0 0 0 WOMM1 WOMM0 0 0 0 0 PKGCR1 PKGCR0 W W 0x0255 PPSM W 0x0257 PKGCR 5 W 0x0254 PERM 0x0256 WOMM 6 W 0x024A DDRS 0x024C PERS Bit 7 R R R W R W APICLKS7 PKGCR2 = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 193 Port Integration Module (S12GPIMV1) Table 2-21. Block Register Map (G3) (continued) Global Address Register Name 0x0258 PTP R W 0x025A DDRP W R R R W 0x025D PPSP W R R R W 0x0260–0x0261 Reserved W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 Bit 0 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 0 0 0 0 0 0 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 0 0 0 0 PTJ3 PTJ2 PTJ1 PTJ0 PTIJ3 PTIJ2 PTIJ1 PTIJ0 DDRJ3 DDRJ2 DDRJ1 DDRJ0 0 0 0 0 PERJ3 PERJ2 PERJ1 PERJ0 R R Reserved for ACMP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0x0268 PTJ W 0x0269 PTIJ W 0x026A DDRJ 0 W 0x025F PIFP 0x0262–0x0267 Reserved 0 5 W 0x025C PERP 0x025E PIEP 6 W 0x0259 PTIP 0x025B Reserved Bit 7 R R R W 0x026B Reserved R W 0x026C PERJ W R = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.28 194 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-21. Block Register Map (G3) (continued) Global Address Register Name 0x026D PPSJ W 0x026E PIEJ W 0x026F PIFJ 0x0270 PT0AD R R R R 0x0272 PTI0AD W R R 0x0273 PTI1AD W 0x0274 DDR0AD W 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PT1AD7 PT1AD6 PT1AD5 0 0 R PTI1AD7 R R W 0x0276 Reserved W 0x0277 Reserved W R R 0x0278 PER0AD W 0x0279 PER1AD W 0x027B PPS1AD 5 3 2 1 Bit 0 PPSJ3 PPSJ2 PPSJ1 PPSJ0 PIEJ3 PIEJ2 PIEJ1 PIEJ0 PIFJ3 PIFJ2 PIFJ1 PIFJ0 PT0AD3 PT0AD2 PT0AD1 PT0AD0 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0 0 0 PTI0AD3 PTI0AD2 PTI0AD1 PTI0AD0 PTI1AD6 PTI1AD5 PTI1AD4 PTI1AD3 PTI1AD2 PTI1AD1 PTI1AD0 0 0 0 W W 0x027A PPS0AD 6 W 0x0271 PT1AD 0x0275 DDR1AD Bit 7 R R R 0 DDR1AD7 DDR1AD6 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W PER0AD3 PER0AD2 PER0AD1 PER0AD0 PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 0 0 0 0 PPS1AD7 PPS1AD6 PPS1AD5 PPS1AD4 W R DDR0AD3 DDR0AD2 DDR0AD1 DDR0AD0 PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0 = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 195 Port Integration Module (S12GPIMV1) Table 2-21. Block Register Map (G3) (continued) Global Address Register Name 0x027C PIE0AD R W 0x027D PIE1AD W R 0x027E PIF0AD R W 0x027F PIF1AD W R Bit 7 6 5 4 0 0 0 0 PIE1AD7 PIE1AD6 PIE1AD5 PIE1AD4 0 0 0 0 PIF1AD7 PIF1AD6 PIF1AD5 PIF1AD4 3 2 1 Bit 0 PIE0AD3 PIE0AD2 PIE0AD1 PIE0AD0 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0 PIF0AD3 PIF0AD2 PIF0AD1 PIF0AD0 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0 = Unimplemented or Reserved 2.4.3 Register Descriptions This section describes the details of all configuration registers. Every register has the same functionality in all groups if not specified separately. Refer to the register figures for reserved locations. If not stated differently, writing to reserved bits has not effect and read returns zero. • • • NOTE All register read accesses are synchronous to internal clocks General-purpose data output availability depends on prioritization; input data registers always reflect the pin status independent of the use Pull-device availability, pull-device polarity, wired-or mode, key-wakeup functionality are independent of the prioritization unless noted differently in section Section 2.3, “PIM Routing - Functional description”. MC9S12G Family Reference Manual Rev.1.28 196 NXP Semiconductors Port Integration Module (S12GPIMV1) 2.4.3.1 Port A Data Register (PORTA) Access: User read/write1 Address 0x0000 (G1) R W Reset 7 6 5 4 3 2 1 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 0 0 0 0 0 0 0 0 Address 0x0000 (G2, G3) R Access: User read only 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 2-2. Port A Data Register (PORTA) 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime Table 2-22. PORTA Register Field Descriptions Field Description 7-0 PA Port A general-purpose input/output data—Data Register The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. 2.4.3.2 Port B Data Register (PORTB) Access: User read/write1 Address 0x0001 (G1) R W Reset 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 0 0 0 0 0 0 0 0 Address 0x0001 (G2, G3) R Access: User read only 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 2-3. Port B Data Register (PORTB) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 197 Port Integration Module (S12GPIMV1) 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime Table 2-23. PORTB Register Field Descriptions Field Description 7-0 PB Port B general-purpose input/output data—Data Register The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. 2.4.3.3 Port A Data Direction Register (DDRA) Access: User read/write1 Address 0x0002 (G1) R W Reset 7 6 5 4 3 2 1 0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 0 Address 0x0002 (G2, G3) R Access: User read only 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 2-4. Port A Data Direction Register (DDRA) 1 Read: Anytime Write: Anytime Table 2-24. DDRA Register Field Descriptions Field 7-0 DDRA Description Port A Data Direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input MC9S12G Family Reference Manual Rev.1.28 198 NXP Semiconductors Port Integration Module (S12GPIMV1) 2.4.3.4 Port B Data Direction Register (DDRB) Access: User read/write1 Address 0x0003 (G1) R W Reset 7 6 5 4 3 2 1 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 Address 0x0003 (G2, G3) R Access: User read only 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 2-5. Port B Data Direction Register (DDRB) 1 Read: Anytime Write: Anytime Table 2-25. DDRB Register Field Descriptions Field 7-0 DDRB Description Port B Data Direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.4.3.5 Port C Data Register (PORTC) Access: User read/write1 Address 0x0004 (G1) R W Reset 7 6 5 4 3 2 1 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0 0 0 0 0 0 0 0 Address 0x0004 (G2, G3) R Access: User read only 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 2-6. Port C Data Register (PORTC) 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 199 Port Integration Module (S12GPIMV1) Table 2-26. PORTC Register Field Descriptions Field Description 7-0 PC Port C general-purpose input/output data—Data Register The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. 2.4.3.6 Port D Data Register (PORTD) Access: User read/write1 Address 0x0005 (G1) R W Reset 7 6 5 4 3 2 1 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 0 0 0 0 0 0 0 0 Address 0x0005 (G2, G3) R Access: User read only 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 2-7. Port D Data Register (PORTD) 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime Table 2-27. PORTD Register Field Descriptions Field Description 7-0 PD Port D general-purpose input/output data—Data Register The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. MC9S12G Family Reference Manual Rev.1.28 200 NXP Semiconductors Port Integration Module (S12GPIMV1) 2.4.3.7 Port C Data Direction Register (DDRC) Access: User read/write1 Address 0x0006 (G1) R W Reset 7 6 5 4 3 2 1 0 DDRC7 DDRC6 DDRC5 DDRA4 DDRC3 DDRC2 DDRC1 DDRC0 0 0 0 0 0 0 0 0 Address 0x0006 (G2, G3) R Access: User read only 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 2-8. Port C Data Direction Register (DDRC) 1 Read: Anytime Write: Anytime Table 2-28. DDRC Register Field Descriptions Field 7-0 DDRC Description Port C Data Direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.4.3.8 Port D Data Direction Register (DDRD) Access: User read/write1 Address 0x0007 (G1) R W Reset 7 6 5 4 3 2 1 0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 Address 0x0007 (G2, G3) R Access: User read only 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 2-9. Port D Data Direction Register (DDRD) 1 Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 201 Port Integration Module (S12GPIMV1) Table 2-29. DDRD Register Field Descriptions Field 7-0 DDRD Description Port D Data Direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.4.3.9 Port E Data Register (PORTE) Access: User read/write1 Address 0x0008 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 PE1 PE0 0 0 Figure 2-10. Port E Data Register (PORTE) 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime Table 2-30. PORTE Register Field Descriptions Field 1-0 PE Description Port E general-purpose input/output data—Data Register When not used with an alternative signal, this pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit is driven to the pin. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. 2.4.3.10 Port E Data Direction Register (DDRE) Access: User read/write1 Address 0x0009 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DDRE1 DDRE0 0 0 Figure 2-11. Port E Data Direction Register (DDRE) 1 Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.28 202 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-31. DDRE Register Field Descriptions Field 1-0 DDRE Description Port E Data Direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.4.3.11 Ports A, B, C, D, E, BKGD pin Pull Control Register (PUCR) Access: User read/write1 Address 0x000C (G1) 7 R 6 0 0 BKPUE W Reset 5 0 1 0 4 3 2 1 0 PDPEE PUPDE PUPCE PUPBE PUPAE 1 0 0 0 0 Address 0x000C (G2, G3) 7 R 6 0 5 0 BKPUE W Reset Access: User read/write 0 1 0 4 PDPEE 1 3 2 1 0 0 0 0 0 0 0 0 0 Figure 2-12. Ports A, B, C, D, E, BKGD pin Pullup Control Register (PUCR) 1 Read:Anytime in normal mode. Write:Anytime, except BKPUE, which is writable in special mode only. Table 2-32. PUCR Register Field Descriptions Field Description 6 BKPUE BKGD pin Pullup Enable—Enable pullup device on pin This bit configures whether a pullup device is activated, if the pin is used as input. If a pin is used as output this bit has no effect. Out of reset the pullup device is enabled. 1 Pullup device enabled 0 Pullup device disabled 4 PDPEE Port E Pulldown Enable—Enable pulldown devices on all port input pins This bit configures whether a pulldown device is activated on all associated port input pins. If a pin is used as output or used with the CPMU OSC function this bit has no effect. Out of reset the pulldown devices are enabled. 1 Pulldown devices enabled 0 Pulldown devices disabled 3 PUPDE Port D Pullup Enable—Enable pullup devices on all port input pins This bit configures whether a pullup device is activated on all associated port input pins. If a pin is used as output this bit has no effect. 1 Pullup devices enabled 0 Pullup devices disabled MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 203 Port Integration Module (S12GPIMV1) Table 2-32. PUCR Register Field Descriptions (continued) Field 2 PUPCE Description Port C Pullup Enable—Enable pullup devices on all port input pins This bit configures whether a pullup device is activated on all associated port input pins. If a pin is used as output this bit has no effect. 1 Pullup devices enabled 0 Pullup devices disabled 1 PUPBE Port B Pullup Enable—Enable pullup devices on all port input pins This bit configures whether a pullup device is activated on all associated port input pins. If a pin is used as output this bit has no effect. 1 Pullup devices enabled 0 Pullup devices disabled 0 PUPAE Port A Pullup Enable—Enable pullup devices on all port input pins This bit configures whether a pullup device is activated on all associated port input pins. If a pin is used as output this bit has no effect. 1 Pullup devices enabled 0 Pullup devices disabled MC9S12G Family Reference Manual Rev.1.28 204 NXP Semiconductors Port Integration Module (S12GPIMV1) 2.4.3.12 ECLK Control Register (ECLKCTL) Access: User read/write1 Address 0x001C R W 7 6 5 4 3 2 1 0 NECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 1 1 0 0 0 0 0 0 Reset: Figure 2-13. ECLK Control Register (ECLKCTL) 1 Read: Anytime Write: Anytime Table 2-33. ECLKCTL Register Field Descriptions Field Description 7 NECLK No ECLK—Disable ECLK output This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the internal bus clock. 1 ECLK disabled 0 ECLK enabled 6 NCLKX2 No ECLKX2—Disable ECLKX2 output This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the internal bus clock. 1 ECLKX2 disabled 0 ECLKX2 enabled 5 DIV16 Free-running ECLK predivider—Divide by 16 This bit enables a divide-by-16 stage on the selected EDIV rate. 1 Divider enabled: ECLK rate = EDIV rate divided by 16 0 Divider disabled: ECLK rate = EDIV rate 4-0 EDIV Free-running ECLK Divider—Configure ECLK rate These bits determine the rate of the free-running clock on the ECLK pin. 00000 ECLK rate = bus clock rate 00001 ECLK rate = bus clock rate divided by 2 00010 ECLK rate = bus clock rate divided by 3,... 11111 ECLK rate = bus clock rate divided by 32 2.4.3.13 IRQ Control Register (IRQCR) Access: User read/write1 Address 0x001E R W Reset 7 6 IRQE IRQEN 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 2-14. IRQ Control Register (IRQCR) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 205 Port Integration Module (S12GPIMV1) 1 Read: Anytime Write: IRQE: Once in normal mode, anytime in special mode IRQEN: Anytime Table 2-34. IRQCR Register Field Descriptions Field 7 IRQE Description IRQ select edge sensitive only— 1 IRQ pin configured to respond only to falling edges. Falling edges on the IRQ pin are detected anytime when IRQE=1 and will be cleared only upon a reset or the servicing of the IRQ interrupt. 0 IRQ pin configured for low level recognition 6 IRQEN IRQ enable— 1 IRQ pin is connected to interrupt logic 0 IRQ pin is disconnected from interrupt logic NOTE If the input is driven to active level (IRQ=0) a write access to set either IRQCR[IRQEN] and IRQCR[IRQE] to 1 simultaneously or to set IRQCR[IRQEN] to 1 when IRQCR[IRQE]=1 causes an IRQ interrupt to be generated if the I-bit is cleared. Refer to Section 2.6.3, “Enabling IRQ edge-sensitive mode”. 2.4.3.14 Reserved Register Access: User read/write1 Address 0x001F R W Reset 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved x x x x x x x x Figure 2-15. Reserved Register 1 Read: Anytime Write: Only in special mode These reserved registers are designed for factory test purposes only and are not intended for general user access. Writing to these registers when in special mode can alter the module’s functionality. MC9S12G Family Reference Manual Rev.1.28 206 NXP Semiconductors Port Integration Module (S12GPIMV1) 2.4.3.15 Port T Data Register (PTT) Access: User read/write1 Address 0x0240 (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x0240 (G3) R 7 6 0 0 0 0 W Reset 5 4 3 2 1 0 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 0 0 0 0 0 0 Figure 2-16. Port T Data Register (PTT) 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime Table 2-35. PTT Register Field Descriptions Field Description 7-0 PTT Port T general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. 2.4.3.16 Port T Input Register (PTIT) Access: User read only1 Address 0x0241 (G1, G2) R 7 6 5 4 3 2 1 0 PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 0 0 0 0 0 0 0 0 W Reset Access: User read only1 Address 0x0241 (G3) R 7 6 5 4 3 2 1 0 0 0 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 0 0 0 0 0 0 0 0 W Reset Figure 2-17. Port T Input Register (PTIT) 1 Read: Anytime Write:Never MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 207 Port Integration Module (S12GPIMV1) Table 2-36. PTIT Register Field Descriptions Field Description 7-0 PTIT Port T input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. 2.4.3.17 Port T Data Direction Register (DDRT) Access: User read/write1 Address 0x0242 (G1, G2) R W Reset 7 6 5 4 3 2 1 0 DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x0242 (G3) R 7 6 0 0 0 0 W Reset 5 4 3 2 1 0 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 0 0 0 0 0 0 Figure 2-18. Port T Data Direction Register (DDRT) 1 Read: Anytime Write: Anytime Table 2-37. DDRT Register Field Descriptions Field 7-0 DDRT Description Port T data direction— This bit determines whether the pin is a general-purpose input or output. 1 Associated pin configured as output 0 Associated pin configured as input MC9S12G Family Reference Manual Rev.1.28 208 NXP Semiconductors Port Integration Module (S12GPIMV1) 2.4.3.18 Port T Pull Device Enable Register (PERT) Access: User read/write1 Address 0x0244 (G1, G2) R W 7 6 5 4 3 2 1 0 PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 0 0 0 0 0 0 0 0 Reset Access: User read/write1 Address 0x0244 (G3) R 7 6 0 0 0 0 W Reset 5 4 3 2 1 0 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 0 0 0 0 0 0 Figure 2-19. Port T Pull Device Enable Register (PERT) 1 Read: Anytime Write: Anytime Table 2-38. PERT Register Field Descriptions Field Description 7-2 PERT Port T pull device enable—Enable pull device on input pin This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has no effect. The polarity is selected by the related polarity select register bit. 1 Pull device enabled 0 Pull device disabled 1 PERT Port T pull device enable—Enable pull device on input pin This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related polarity select register bit. If this pin is used as IRQ only a pullup device can be enabled. 1 Pull device enabled 0 Pull device disabled 0 PERT Port T pull device enable—Enable pull device on input pin This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related polarity select register bit. If this pin is used as XIRQ only a pullup device can be enabled. 1 Pull device enabled 0 Pull device disabled MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 209 Port Integration Module (S12GPIMV1) 2.4.3.19 Port T Polarity Select Register (PPST) Access: User read/write1 Address 0x0245 (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x0245 (G3) R 7 6 0 0 0 0 W Reset 5 4 3 2 1 0 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0 0 0 0 0 0 Figure 2-20. Port T Polarity Select Register (PPST) 1 Read: Anytime Write: Anytime Table 2-39. PPST Register Field Descriptions Field 7-0 PPST Description Port T pull device select—Configure pull device polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. 1 Pulldown device selected 0 Pullup device selected 2.4.3.20 Port S Data Register (PTS) Access: User read/write1 Address 0x0248 R W 7 6 5 4 3 2 1 0 PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 0 0 0 0 0 0 0 0 Figure 2-21. Port S Data Register (PTS) 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime MC9S12G Family Reference Manual Rev.1.28 210 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-40. PTS Register Field Descriptions Field Description 7-0 PTS Port S general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. 2.4.3.21 Port S Input Register (PTIS) Access: User read only1 Address 0x0249 R 7 6 5 4 3 2 1 0 PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 0 0 0 0 0 0 0 0 W Reset Figure 2-22. Port S Input Register (PTIS) 1 Read: Anytime Write:Never Table 2-41. PTIS Register Field Descriptions Field Description 7-0 PTIS Port S input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. 2.4.3.22 Port S Data Direction Register (DDRS) Access: User read/write1 Address 0x024A R W Reset 7 6 5 4 3 2 1 0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 0 0 0 0 0 0 0 0 Figure 2-23. Port S Data Direction Register (DDRS) 1 Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 211 Port Integration Module (S12GPIMV1) Table 2-42. DDRS Register Field Descriptions Field 7-0 DDRS Description Port S data direction— This bit determines whether the associated pin is a general-purpose input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.4.3.23 Port S Pull Device Enable Register (PERS) Access: User read/write1 Address 0x024C R W Reset 7 6 5 4 3 2 1 0 PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 1 1 1 1 1 1 1 1 Figure 2-24. Port S Pull Device Enable Register (PERS) 1 Read: Anytime Write: Anytime Table 2-43. PERS Register Field Descriptions Field Description 7-0 PERS Port S pull device enable—Enable pull device on input pin or wired-or output pin This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related polarity select register bit. If a pin is used as output this bit has only effect if used in wired-or mode with a pullup device. 1 Pull device enabled 0 Pull device disabled 2.4.3.24 Port S Polarity Select Register (PPSS) Access: User read/write1 Address 0x024D R W Reset 7 6 5 4 3 2 1 0 PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 0 0 0 0 0 0 0 0 Figure 2-25. Port S Polarity Select Register (PPSS) 1 Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.28 212 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-44. PPSS Register Field Descriptions Field 7-0 PPSS Description Port S pull device select—Configure pull device polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. 1 Pulldown device selected 0 Pullup device selected 2.4.3.25 Port S Wired-Or Mode Register (WOMS) Access: User read/write1 Address 0x024E R W Reset 7 6 5 4 3 2 1 0 WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 0 0 0 0 0 0 0 0 Figure 2-26. Port S Wired-Or Mode Register (WOMS) 1 Read: Anytime Write: Anytime Table 2-45. WOMS Register Field Descriptions Field Description 7-0 WOMS Port S wired-or mode—Enable open-drain functionality on output pin This bit configures an output pin as wired-or (open-drain) or push-pull. In wired-or mode a logic “0” is driven active-low while a logic “1” remains undriven. This allows a multipoint connection of several serial modules. The bit has no influence on pins used as input. 1 Output buffer operates as open-drain output. 0 Output buffer operates as push-pull output. 2.4.3.26 Pin Routing Register 0 (PRR0) NOTE Routing takes only effect if PKGCR is set to select the 20 TSSOP package. Access: User read/write1 Address 0x024F R W Reset 7 6 5 4 3 2 1 0 PRR0P3 PRR0P2 PRR0T31 PRR0T30 PRR0T21 PRR0T20 PRR0S1 PRR0S0 0 0 0 0 0 0 0 0 Figure 2-27. Pin Routing Register (PRR0) 1 Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 213 Port Integration Module (S12GPIMV1) Table 2-46. PRR0 Register Field Descriptions Field Description 7 PRR0P3 Pin Routing Register PWM3 —Select alternative routing of PWM3 output, ETRIG3 input This bit programs the routing of the PWM3 channel and the ETRIG3 input to a different external pin in 20 TSSOP. See Table 2-47 for more details. 6 PRR0P2 Pin Routing Register PWM2 —Select alternative routing of PWM2 output, ETRIG2 input This bit programs the routing of the PWM2 channel and the ETRIG2 input to a different external pin in 20 TSSOP. See Table 2-48 for more details. 5 Pin Routing Register IOC3 —Select alternative routing of IOC3 output and input PRR0T31 Those two bits program the routing of the timer IOC3 channel to different external pins in 20 TSSOP. See Table 2-49 for more details. 4 PRR0T30 3 Pin Routing Register IOC2 —Select alternative routing of IOC2 output and input PRR0T21 Those two bits program the routing of the timer IOC2 channel to different external pins in 20 TSSOP. See Table 2-50 for more details. 2 PRR0T20 1 PRR0S1 0 PRR0S0 Pin Routing Register Serial Module —Select alternative routing of SCI0 pins Those bits program the routing of the SCI0 module pins to different external pins in 20 TSSOP. See Table 2-51 for more details. Table 2-47. PWM3/ETRIG3 Routing Options PRR0P3 PWM3/ETRIG3 Associated Pin 0 PS7 - PWM3, ETRIG3 1 PAD5 - PWM3, ETRIG3 Table 2-48. PWM2/ETRIG2 Routing Options PRR0P2 PWM2/ETRIG2 Associated Pin 0 PS4 - PWM2, ETRIG2 1 PAD4 - PWM2, ETRIG2 Table 2-49. IOC3 Routing Options PRR0T31 PRR0T30 IOC3 Associated Pin 0 0 PS6 - IOC3 0 1 PE1 - IOC3 1 0 PAD5 - IOC3 1 1 Reserved MC9S12G Family Reference Manual Rev.1.28 214 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-50. IOC2 Routing Options PRR0T21 PRR0T20 IOC2 Associated Pin 0 0 PS5 - IOC2 0 1 PE0 - IOC2 1 0 PAD4 - IOC2 1 1 Reserved Table 2-51. SCI0 Routing Options 2.4.3.27 PRR0S1 PRR0S0 SCI0 Associated Pin 0 0 PE0 - RXD, PE1 - TXD 0 1 PS4 - RXD, PS7 - TXD 1 0 PAD4 - RXD, PAD5 - TXD 1 1 Reserved Port M Data Register (PTM) Access: User read/write1 Address 0x0250 (G1, G2) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PTM3 PTM2 PTM1 PTM0 0 0 0 0 Access: User read/write1 Address 0x0250 (G3) R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 PTM1 PTM0 0 0 Figure 2-28. Port M Data Register (PTM) 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime Table 2-52. PTM Register Field Descriptions Field Description 3-0 PTM Port M general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 215 Port Integration Module (S12GPIMV1) 2.4.3.28 Port M Input Register (PTIM) Access: User read only1 Address 0x0251 (G1, G2) R 7 6 5 4 3 2 1 0 0 0 0 0 PTIM3 PTIM2 PTIM1 PTIM0 0 0 0 0 0 0 0 0 W Reset Access: User read only1 Address 0x0251 (G3) R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 PTIM1 PTIM0 0 0 0 0 0 0 0 0 W Reset Figure 2-29. Port M Input Register (PTIM) 1 Read: Anytime Write:Never Table 2-53. PTIM Register Field Descriptions Field Description 3-0 PTIM Port M input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. 2.4.3.29 Port M Data Direction Register (DDRM) Access: User read/write1 Address 0x0252 (G1, G2) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 DDRM3 DDRM2 DDRM1 DDRM0 0 0 0 0 Access: User read/write1 Address 0x0252 (G3) R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DDRM1 DDRM0 0 0 Figure 2-30. Port M Data Direction Register (DDRM) 1 Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.28 216 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-54. DDRM Register Field Descriptions Field 3-0 DDRM Description Port M data direction— This bit determines whether the associated pin is a general-purpose input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.4.3.30 Port M Pull Device Enable Register (PERM) Access: User read/write1 Address 0x0254 (G1, G2) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PERM3 PERM2 PERM1 PERM0 0 0 0 0 Access: User read/write1 Address 0x0254 (G3) R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 PERM1 PERM0 0 0 Figure 2-31. Port M Pull Device Enable Register (PERM) 1 Read: Anytime Write: Anytime Table 2-55. PERM Register Field Descriptions Field Description 3-1 PERM Port M pull device enable—Enable pull device on input pin or wired-or output pin This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related polarity select register bit. If a pin is used as output this bit has only effect if used in wired-or mode with a pullup device. 1 Pull device enabled 0 Pull device disabled 0 PERM Port M pull device enable—Enable pull device on input pin or wired-or output pin This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related polarity select register bit. If a pin is used as output this bit has only effect if used in wired-or mode with a pullup device. If CAN is active the selection of a pulldown device on the RXCAN input will have no effect. 1 Pull device enabled 0 Pull device disabled MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 217 Port Integration Module (S12GPIMV1) 2.4.3.31 Port M Polarity Select Register (PPSM) Access: User read/write1 Address 0x0255 (G1, G2) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PPSM3 PPSM2 PPSM1 PPSM0 0 0 0 0 Access: User read/write1 Address 0x0255 (G3) R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 PPSM1 PPSM0 0 0 Figure 2-32. Port M Polarity Select Register (PPSM) 1 Read: Anytime Write: Anytime Table 2-56. PPSM Register Field Descriptions Field 3-0 PPSM Description Port M pull device select—Configure pull device polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. 1 Pulldown device selected 0 Pullup device selected 2.4.3.32 Port M Wired-Or Mode Register (WOMM) Access: User read/write1 Address 0x0256 (G1, G2) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 WOMM3 WOMM2 WOMM1 WOMM0 0 0 0 0 Access: User read/write1 Address 0x0256 (G3) R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 WOMM1 WOMM0 0 0 Figure 2-33. Port M Wired-Or Mode Register (WOMM) 1 Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.28 218 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-57. WOMM Register Field Descriptions Field Description 3-0 WOMM Port M wired-or mode—Enable open-drain functionality on output pin This bit configures an output pin as wired-or (open-drain) or push-pull. In wired-or mode a logic “0” is driven active-low while a logic “1” remains undriven. This allows a multipoint connection of several serial modules. The bit has no influence on pins used as input. 1 Output buffer operates as open-drain output. 0 Output buffer operates as push-pull output. 2.4.3.33 Package Code Register (PKGCR) Access: User read/write1 Address 0x0257 7 R W Reset APICLKS7 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 PKGCR2 PKGCR1 PKGCR0 F F F After deassert of system reset the values are automatically loaded from the Flash memory. See device specification for details. Figure 2-34. Package Code Register (PKGCR) 1 Read: Anytime Write: APICLKS7: Anytime PKGCR2-0: Once in normal mode, anytime in special mode Table 2-58. PKGCR Register Field Descriptions Field Description 7 Pin Routing Register API_EXTCLK —Select PS7 as API_EXTCLK output APICLKS7 When set to 1 the API_EXTCLK output will be routed to PS7. The default pin will be disconnected in all packages except 20 TSSOP, which has no default location for API_EXTCLK. See Table 2-59 for more details. 2-0 PKGCR Package Code Register —Select package in use Those bits are preset by factory and reflect the package in use. See Table 2-60 for code definition. The bits can be modified once after reset to allow software development for a different package. In any other application it is recommended to re-write the actual package code once after reset to lock the register from inadvertent changes during operation. Writing reserved codes or codes of larger packages than the given device is offered in are illegal. In these cases the code will be converted to PKGCR[2:0]=0b111 and select the maximum available package option for the given device. Codes writes of smaller packages than the given device is offered in are not restricted. Depending on the package selection the input buffers of non-bonded pins are disabled to avoid shoot-through current. Also a predefined signal routing will take effect. Refer also to Section 2.6.5, “Emulation of Smaller Packages”. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 219 Port Integration Module (S12GPIMV1) Table 2-59. API_EXTCLK Routing Options APICLKS7 API_EXTCLK Associated Pin 0 PB1 (100 LQFP) PP0 (64/48/32 LQFP) N.C. (20TSSOP) 1 PS7 Table 2-60. Package Options 1 2.4.3.34 PKGCR2 PKGCR1 PKGCR0 Selected Package 1 1 1 Reserved1 1 1 0 100 LQFP 1 0 1 Reserved 1 0 0 64 LQFP 0 1 1 48 LQFP 0 1 0 Reserved 0 0 1 32 LQFP 0 0 0 20 TSSOP Reading this value indicates an illegal code write or uninitialized factory programming. Port P Data Register (PTP) Access: User read/write1 Address 0x0258 (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x0258 (G3) R 7 6 0 0 0 0 W Reset 5 4 3 2 1 0 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 0 0 0 0 0 0 Figure 2-35. Port P Data Register (PTP) 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime MC9S12G Family Reference Manual Rev.1.28 220 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-61. PTP Register Field Descriptions Field Description 7-0 PTP Port P general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. 2.4.3.35 Port P Input Register (PTIP) Access: User read only1 Address 0x0259 (G1, G2) R 7 6 5 4 3 2 1 0 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 0 0 0 0 0 0 0 0 W Reset Access: User read only1 Address 0x0259 (G3) R 7 6 5 4 3 2 1 0 0 0 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 0 0 0 0 0 0 0 0 W Reset Figure 2-36. Port P Input Register (PTIP) 1 Read: Anytime Write:Never Table 2-62. PTIP Register Field Descriptions Field Description 7-0 PTIP Port P input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 221 Port Integration Module (S12GPIMV1) 2.4.3.36 Port P Data Direction Register (DDRP) Access: User read/write1 Address 0x025A (G1, G2) R W Reset 7 6 5 4 3 2 1 0 DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x025A (G3) R 7 6 0 0 0 0 W Reset 5 4 3 2 1 0 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 0 0 0 0 0 0 Figure 2-37. Port P Data Direction Register (DDRP) 1 Read: Anytime Write: Anytime Table 2-63. DDRP Register Field Descriptions Field 7-0 DDRP Description Port P data direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.4.3.37 Port P Pull Device Enable Register (PERP) Access: User read/write1 Address 0x025C (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x025C (G3) R 7 6 0 0 0 0 W Reset 5 4 3 2 1 0 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 0 0 0 0 0 0 Figure 2-38. Port P Pull Device Enable Register (PERP) 1 Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.28 222 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-64. PERP Register Field Descriptions Field Description 7-0 PERP Port P pull device enable—Enable pull device on input pin This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has no effect. The polarity is selected by the related polarity select register bit. 1 Pull device enabled 0 Pull device disabled 2.4.3.38 Port P Polarity Select Register (PPSP) Access: User read/write1 Address 0x025D (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x025D (G3) R 7 6 0 0 0 0 W Reset 5 4 3 2 1 0 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 0 0 0 0 0 0 Figure 2-39. Port P Polarity Select Register (PPSP) 1 Read: Anytime Write: Anytime Table 2-65. PPSP Register Field Descriptions Field 7-0 PPSP Description Port P pull device select—Configure pull device and pin interrupt edge polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. This bit also selects the polarity of the active pin interrupt edge. 1 Pulldown device selected; rising edge selected 0 Pullup device selected; falling edge selected MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 223 Port Integration Module (S12GPIMV1) 2.4.3.39 Port P Interrupt Enable Register (PIEP) Read: Anytime Access: User read/write1 Address 0x025E (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x025E (G3) R 7 6 0 0 0 0 W Reset 5 4 3 2 1 0 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 0 0 0 0 0 0 Figure 2-40. Port P Interrupt Enable Register (PIEP) 1 Read: Anytime Write: Anytime Table 2-66. PIEP Register Field Descriptions Field Description 7-0 PIEP Port P interrupt enable— This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if the pin is operating in input or output mode when in use with the general-purpose or related peripheral function. 1 Interrupt is enabled 0 Interrupt is disabled (interrupt flag masked) 2.4.3.40 Port P Interrupt Flag Register (PIFP) Access: User read/write1 Address 0x025F (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x025F (G3) R 7 6 0 0 0 0 W Reset 5 4 3 2 1 0 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 0 0 0 0 0 0 Figure 2-41. Port P Interrupt Flag Register (PIFP) MC9S12G Family Reference Manual Rev.1.28 224 NXP Semiconductors Port Integration Module (S12GPIMV1) 1 Read: Anytime Write: Anytime, write 1 to clear Table 2-67. PIFP Register Field Descriptions Field Description 7-0 PIFP Port P interrupt flag— This flag asserts after a valid active edge was detected on the related pin (see Section 2.5.4.2, “Pin Interrupts and Wakeup”). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the associated interrupt enable bit is set. Writing a logic “1” to the corresponding bit field clears the flag. 1 Active edge on the associated bit has occurred 0 No active edge occurred MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 225 Port Integration Module (S12GPIMV1) 2.4.3.41 Reserved Registers NOTE Addresses 0x0260-0x0261 are reserved for ACMP registers in G2 and G3 only. Refer to ACMP section “ACMP Control Register (ACMPC)” and “ACMP Status Register (ACMPS)”. 2.4.3.42 Port J Data Register (PTJ) Access: User read/write1 Address 0x0268 (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PTJ7 PTJ6 PTJ5 PTJ4 PTJ3 PTJ2 PTJ1 PTJ0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x0268 (G3) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PTJ3 PTJ2 PTJ1 PTJ0 0 0 0 0 Figure 2-42. Port J Data Register (PTJ) 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime Table 2-68. PTJ Register Field Descriptions Field Description 7-0 PTJ Port J general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. MC9S12G Family Reference Manual Rev.1.28 226 NXP Semiconductors Port Integration Module (S12GPIMV1) 2.4.3.43 Port J Input Register (PTIJ) Access: User read only1 Address 0x0269 (G1, G2) R 7 6 5 4 3 2 1 0 PTIJ7 PTIJ6 PTIJ5 PTIJ4 PTIJ3 PTIJ2 PTIJ1 PTIJ0 0 0 0 0 0 0 0 0 W Reset Access: User read only1 Address 0x0269 (G3) R 7 6 5 4 3 2 1 0 0 0 0 0 PTIJ3 PTIJ2 PTIJ1 PTIJ0 0 0 0 0 0 0 0 0 W Reset Figure 2-43. Port J Input Register (PTIJ) 1 Read: Anytime Write:Never Table 2-69. PTIJ Register Field Descriptions Field Description 7-0 PTIJ Port J input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. 2.4.3.44 Port J Data Direction Register (DDRJ) Access: User read/write1 Address 0x026A (G1, G2) R W Reset 7 6 5 4 3 2 1 0 DDRJ7 DDRJ6 DDRJ5 DDRJ4 DDRJ3 DDRJ2 DDRJ1 DDRJ0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x026A (G3) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 DDRJ3 DDRJ2 DDRJ1 DDRJ0 0 0 0 0 Figure 2-44. Port J Data Direction Register (DDRJ) 1 Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 227 Port Integration Module (S12GPIMV1) Table 2-70. DDRJ Register Field Descriptions Field 7-0 DDRJ Description Port J data direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.4.3.45 Port J Pull Device Enable Register (PERJ) Access: User read/write1 Address 0x026C (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PERJ7 PERJ6 PERJ5 PERJ4 PERJ3 PERJ2 PERJ1 PERJ0 1 1 1 1 1 1 1 1 Access: User read/write1 Address 0x026C (G3) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PERJ3 PERJ2 PERJ1 PERJ0 1 1 1 1 Figure 2-45. Port J Pull Device Enable Register (PERJ) 1 Read: Anytime Write: Anytime Table 2-71. PERJ Register Field Descriptions Field Description 7-0 PERJ Port J pull device enable—Enable pull device on input pin This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has no effect. The polarity is selected by the related polarity select register bit. 1 Pull device enabled 0 Pull device disabled MC9S12G Family Reference Manual Rev.1.28 228 NXP Semiconductors Port Integration Module (S12GPIMV1) 2.4.3.46 Port J Polarity Select Register (PPSJ) Access: User read/write1 Address 0x026D (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PPSJ7 PPSJ6 PPSJ5 PPSJ4 PPSJ3 PPSJ2 PPSJ1 PPSJ0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x026D (G3) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PPSJ3 PPSJ2 PPSJ1 PPSJ0 0 0 0 0 Figure 2-46. Port J Polarity Select Register (PPSJ) 1 Read: Anytime Write: Anytime Table 2-72. PPSJ Register Field Descriptions Field 7-0 PPSJ Description Port J pull device select—Configure pull device and pin interrupt edge polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. This bit also selects the polarity of the active pin interrupt edge. 1 Pulldown device selected; rising edge selected 0 Pullup device selected; falling edge selected 2.4.3.47 Port J Interrupt Enable Register (PIEJ) Read: Anytime Access: User read/write1 Address 0x026E (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PIEJ7 PIEJ6 PIEJ5 PIEJ4 PIEJ3 PIEJ2 PIEJ1 PIEJ0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x026E (G3) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PIEJ3 PIEJ2 PIEJ1 PIEJ0 0 0 0 0 Figure 2-47. Port J Interrupt Enable Register (PIEJ) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 229 Port Integration Module (S12GPIMV1) 1 Read: Anytime Write: Anytime Table 2-73. PIEJ Register Field Descriptions Field Description 7-0 PIEJ Port J interrupt enable— This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if the pin is operating in input or output mode when in use with the general-purpose or related peripheral function. 1 Interrupt is enabled 0 Interrupt is disabled (interrupt flag masked) 2.4.3.48 Port J Interrupt Flag Register (PIFJ) Access: User read/write1 Address 0x026F (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PIFJ7 PIFJ6 PIFJ5 PIFJ4 PIFJ3 PIFJ2 PIFJ1 PIFJ0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x026F (G3) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PIFJ3 PIFJ2 PIFJ1 PIFJ0 0 0 0 0 Figure 2-48. Port J Interrupt Flag Register (PIFJ) 1 Read: Anytime Write: Anytime, write 1 to clear Table 2-74. PIFJ Register Field Descriptions Field Description 7-0 PIFJ Port J interrupt flag— This flag asserts after a valid active edge was detected on the related pin (see Section 2.5.4.2, “Pin Interrupts and Wakeup”). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the associated interrupt enable bit is set. Writing a logic “1” to the corresponding bit field clears the flag. 1 Active edge on the associated bit has occurred 0 No active edge occurred MC9S12G Family Reference Manual Rev.1.28 230 NXP Semiconductors Port Integration Module (S12GPIMV1) 2.4.3.49 Port AD Data Register (PT0AD) Access: User read/write1 Address 0x0270 (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PT0AD7 PT0AD6 PT0AD5 PT0AD4 PT0AD3 PT0AD2 PT0AD1 PT0AD0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x0270 (G3) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PT0AD3 PT0AD2 PT0AD1 PT0AD0 0 0 0 0 Figure 2-49. Port AD Data Register (PT0AD) 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime Table 2-75. PT0AD Register Field Descriptions Field Description 7-0 PT0AD Port AD general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read if the digital input buffers are enabled (Section 2.3.12, “Pins AD15-0”). 2.4.3.50 Port AD Data Register (PT1AD) Access: User read/write1 Address 0x0271 R W Reset 7 6 5 4 3 2 1 0 PT1AD7 PT1AD6 PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0 0 0 0 0 0 0 0 0 Figure 2-50. Port AD Data Register (PT1AD) 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 231 Port Integration Module (S12GPIMV1) Table 2-76. PT1AD Register Field Descriptions Field Description 7-0 PT1AD Port AD general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read if the digital input buffers are enabled (Section 2.3.12, “Pins AD15-0”). 2.4.3.51 Port AD Input Register (PTI0AD) Access: User read only1 Address 0x0272 (G1, G2) R 7 6 5 4 3 2 1 0 PTI0AD7 PTI0AD6 PTI0AD5 PTI0AD4 PTI0AD3 PTI0AD2 PTI0AD1 PTI0AD0 0 0 0 0 0 0 0 0 W Reset Access: User read only1 Address 0x0272 (G3) R 7 6 5 4 3 2 1 0 0 0 0 0 PTI0AD3 PTI0AD2 PTI0AD1 PTI0AD0 0 0 0 0 0 0 0 0 W Reset Figure 2-51. Port AD Input Register (PTI0AD) 1 Read: Anytime Write: Never Table 2-77. PTI0AD Register Field Descriptions Field Description 7-0 PTI0AD Port AD input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. 2.4.3.52 Port AD Input Register (PTI1AD) Access: User read only1 Address 0x0273 R 7 6 5 4 3 2 1 0 PTI1AD7 PTI1AD6 PTI1AD5 PTI1AD4 PTI1AD3 PTI1AD2 PTI1AD1 PTI1AD0 0 0 0 0 0 0 0 0 W Reset Figure 2-52. Port AD Input Register (PTI1AD) 1 Read: Anytime Write: Never MC9S12G Family Reference Manual Rev.1.28 232 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-78. PTI1AD Register Field Descriptions Field Description 7-0 PTI1AD Port AD input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. 2.4.3.53 Port AD Data Direction Register (DDR0AD) Access: User read/write1 Address 0x0274 (G1, G2) R W 7 6 5 4 3 2 1 0 DDR0AD7 DDR0AD6 DDR0AD5 DDR0AD4 DDR0AD3 DDR0AD2 DDR0AD1 DDR0AD0 0 0 0 0 0 0 0 0 Reset Access: User read/write1 Address 0x0274 (G3) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 DDR0AD3 DDR0AD2 DDR0AD1 DDR0AD0 0 0 0 0 Figure 2-53. Port AD Data Direction Register (DDR0AD) 1 Read: Anytime Write: Anytime Table 2-79. DDR0AD Register Field Descriptions Field Description 7-0 DDR0AD Port AD data direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.4.3.54 Port AD Data Direction Register (DDR1AD) Access: User read/write1 Address 0x0275 R W Reset 7 6 5 4 3 2 1 0 DDR1AD7 DDR1AD6 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0 0 0 0 0 0 0 0 0 Figure 2-54. Port AD Data Direction Register (DDR1AD) 1 Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 233 Port Integration Module (S12GPIMV1) Table 2-80. DDR1AD Register Field Descriptions Field 7-0 DDR1AD Description Port AD data direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.4.3.55 Reserved Register NOTE Address 0x0276 is reserved for RVA on G(A)240 and G(A)192 only. Refer to RVA section “RVA Control Register (RVACTL)”. 2.4.3.56 Pin Routing Register 1 (PRR1) NOTE Routing takes only effect if PKGCR is set to select the 100 LQFP package. Access: User read/write1 Address 0x0277 (G(A)240 and G(A)192 only) R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Address 0x0277 (non G(A)240 and G(A)192) R 0 PRR1AN 0 Access: User read/write 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 2-55. Pin Routing Register (PRR1) 1 Read: Anytime Write: Anytime Table 2-81. PRR1 Register Field Descriptions Field Description 0 PRR1AN Pin Routing Register ADC channels — Select alternative routing for AN15/14/13/11/10 pins to port C This bit programs the routing of the specific ADC channels to alternative external pins in 100 LQFP. See Table 2-82. The routing affects the analog signals and digital input trigger paths to the ADC. Refer to the related pin descriptions in Section 2.3.4, “Pins PC7-0” and Section 2.3.12, “Pins AD15-0”. 1 AN inputs on port C 0 AN inputs on port AD MC9S12G Family Reference Manual Rev.1.28 234 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-82. AN Routing Options PRR1AN 2.4.3.57 Associated Pins 0 AN10 - PAD10 AN11 - PAD11 AN13 - PAD13 AN14 - PAD14 AN15 - PAD15 1 AN10 - PC0 AN11 - PC1 AN13 - PC2 AN14 - PC3 AN15 - PC4 Port AD Pull Enable Register (PER0AD) Access: User read/write1 Address 0x0278 (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PER0AD7 PER0AD6 PER0AD5 PER0AD4 PER0AD3 PER0AD2 PER0AD1 PER0AD0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x0278 (G3) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PER0AD3 PER0AD2 PER0AD1 PER0AD0 0 0 0 0 Figure 2-56. Port AD Pullup Enable Register (PER0AD) 1 Read: Anytime Write: Anytime Table 2-83. PER0AD Register Field Descriptions Field Description 7-0 PER0AD Port AD pull enable—Enable pull device on input pin This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has no effect. The polarity is selected by the related polarity select register bit. 1 Pull device enabled 0 Pull device disabled MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 235 Port Integration Module (S12GPIMV1) 2.4.3.58 Port AD Pull Enable Register (PER1AD) Access: User read/write1 Address 0x0279 R W Reset 7 6 5 4 3 2 1 0 PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 0 0 0 0 0 0 0 0 Figure 2-57. Port AD Pullup Enable Register (PER1AD) 1 Read: Anytime Write: Anytime Table 2-84. PER1AD Register Field Descriptions Field Description 7-0 PER1AD Port AD pull enable—Enable pull device on input pin This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has no effect. The polarity is selected by the related polarity select register bit. 1 Pull device enabled 0 Pull device disabled 2.4.3.59 Port AD Polarity Select Register (PPS0AD) Access: User read/write1 Address 0x027A (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PPS0AD7 PPS0AD6 PPS0AD5 PPS0AD4 PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x027A (G3) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0 0 0 0 0 Figure 2-58. Port AD Polarity Select Register (PPS0AD) 1 Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.28 236 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-85. PPS0AD Register Field Descriptions Field 7-0 PPS0AD Description Port AD pull device select—Configure pull device and pin interrupt edge polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. This bit also selects the polarity of the active pin interrupt edge. 1 Pulldown device selected; rising edge selected 0 Pullup device selected; falling edge selected 2.4.3.60 Port AD Polarity Select Register (PPS1AD) Access: User read/write1 Address 0x027B R W Reset 7 6 5 4 3 2 1 0 PPS1AD7 PPS1AD6 PPS1AD5 PPS1AD4 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0 0 0 0 0 0 0 0 0 Figure 2-59. Port AD Polarity Select Register (PPS1AD) 1 Read: Anytime Write: Anytime Table 2-86. PPS1AD Register Field Descriptions Field 7-0 PPS1AD Description Port AD pull device select—Configure pull device and pin interrupt edge polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. This bit also selects the polarity of the active pin interrupt edge. 1 Pulldown device selected; rising edge selected 0 Pullup device selected; falling edge selected MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 237 Port Integration Module (S12GPIMV1) 2.4.3.61 Port AD Interrupt Enable Register (PIE0AD) Read: Anytime Access: User read/write1 Address 0x027C (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PIE0AD7 PIE0AD6 PIE0AD5 PIE0AD4 PIE0AD3 PIE0AD2 PIE0AD1 PIE0AD0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x027C (G3) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PIE0AD3 PIE0AD2 PIE0AD1 PIE0AD0 0 0 0 0 Figure 2-60. Port AD Interrupt Enable Register (PIE0AD) 1 Read: Anytime Write: Anytime Table 2-87. PIE0AD Register Field Descriptions Field Description 7-0 PIE0AD Port AD interrupt enable— This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if the pin is operating in input or output mode when in use with the general-purpose or related peripheral function. 1 Interrupt is enabled 0 Interrupt is disabled (interrupt flag masked) 2.4.3.62 Port AD Interrupt Enable Register (PIE1AD) Read: Anytime Access: User read/write1 Address 0x027D R W Reset 7 6 5 4 3 2 1 0 PIE1AD7 PIE1AD6 PIE1AD5 PIE1AD4 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0 0 0 0 0 0 0 0 0 Figure 2-61. Port AD Interrupt Enable Register (PIE1AD) 1 Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.28 238 NXP Semiconductors Port Integration Module (S12GPIMV1) Table 2-88. PIE1AD Register Field Descriptions Field Description 7-0 PIE1AD Port AD interrupt enable— This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if the pin is operating in input or output mode when in use with the general-purpose or related peripheral function. 1 Interrupt is enabled 0 Interrupt is disabled (interrupt flag masked) 2.4.3.63 Port AD Interrupt Flag Register (PIF0AD) Access: User read/write1 Address 0x027E (G1, G2) R W Reset 7 6 5 4 3 2 1 0 PIF0AD7 PIF0AD6 PIF0AD5 PIF0AD4 PIF0AD3 PIF0AD2 PIF0AD1 PIF0AD0 0 0 0 0 0 0 0 0 Access: User read/write1 Address 0x027E (G3) R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PIF0AD3 PIF0AD2 PIF0AD1 PIF0AD0 0 0 0 0 Figure 2-62. Port AD Interrupt Flag Register (PIF0AD) 1 Read: Anytime Write: Anytime, write 1 to clear Table 2-89. PIF0AD Register Field Descriptions Field Description 7-0 PIF0AD Port AD interrupt flag— This flag asserts after a valid active edge was detected on the related pin (see Section 2.5.4.2, “Pin Interrupts and Wakeup”). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the associated interrupt enable bit is set. Writing a logic “1” to the corresponding bit field clears the flag. 1 Active edge on the associated bit has occurred 0 No active edge occurred MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 239 Port Integration Module (S12GPIMV1) 2.4.3.64 Port AD Interrupt Flag Register (PIF1AD) Access: User read/write1 Address 0x027F R W Reset 7 6 5 4 3 2 1 0 PIF1AD7 PIF1AD6 PIF1AD5 PIF1AD4 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0 0 0 0 0 0 0 0 0 Figure 2-63. Port AD Interrupt Flag Register (PIF1AD) 1 Read: Anytime Write: Anytime Table 2-90. PIF1AD Register Field Descriptions Field Description 7-0 PIF1AD Port AD interrupt flag— This flag asserts after a valid active edge was detected on the related pin (see Section 2.5.4.2, “Pin Interrupts and Wakeup”). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the associated interrupt enable bit is set. Writing a logic “1” to the corresponding bit field clears the flag. 1 Active edge on the associated bit has occurred 0 No active edge occurred MC9S12G Family Reference Manual Rev.1.28 240 NXP Semiconductors Port Integration Module (S12GPIMV1) 2.5 PIM Ports - Functional Description 2.5.1 General Each pin except BKGD can act as general-purpose I/O. In addition most pins can act as an output or input of a peripheral module. 2.5.2 Registers A set of configuration registers is common to all ports with exception of the ADC port (Table 2-91). All registers can be written at any time, however a specific configuration might not become active. Example: Selecting a pullup device. This device does not become active while the port is used as a push-pull output. Table 2-91. Register availability per port1 Port 1 2.5.2.1 Data (Portx, PTx) Input (PTIx) Data Direction (DDRx) Pull Enable (PERx) Polarity Select (PPSx) WiredOr Mode (WOMx) Interrupt Enable (PIEx) Interrupt Flag (PIFx) A yes - yes - - - - B yes - yes - - - - C yes - yes - - - - D yes - yes - - - - E yes - yes - - - - T yes yes yes yes yes - - - yes S yes yes yes yes yes yes - - M yes yes yes yes yes yes - - P yes yes yes yes yes - yes yes J yes yes yes yes yes - yes yes AD yes yes yes yes yes - yes yes Each cell represents one register with individual configuration bits Data Register (PORTx, PTx) This register holds the value driven out to the pin if the pin is used as a general-purpose I/O. Writing to this register has only an effect on the pin if the pin is used as general-purpose output. When reading this address, the buffered state of the pin is returned if the associated data direction register bit is set to 0. If the data direction register bits are set to 1, the contents of the data register is returned. This is independent of any other configuration (Figure 2-64). 2.5.2.2 Input Register (PTIx) This register is read-only and always returns the buffered state of the pin (Figure 2-64). MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 241 Port Integration Module (S12GPIMV1) 2.5.2.3 Data Direction Register (DDRx) This register defines whether the pin is used as an general-purpose input or an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-64). Independent of the pin usage with a peripheral module this register determines the source of data when reading the associated data register address (2.5.2.1/2-241). NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on port data or port input registers, when changing the data direction register. PTI 0 1 PT 0 PIN 1 DDR 0 1 Module data out output enable module enable Figure 2-64. Illustration of I/O pin functionality 2.5.2.4 Pull Device Enable Register (PERx) This register turns on a pullup or pulldown device on the related pins determined by the associated polarity select register (2.5.2.5/2-242). The pull device becomes active only if the pin is used as an input or as a wired-or output. Some peripheral module only allow certain configurations of pull devices to become active. Refer to Section 2.3, “PIM Routing - Functional description”. 2.5.2.5 Pin Polarity Select Register (PPSx) This register selects either a pullup or pulldown device if enabled. It becomes only active if the pin is used as an input. A pullup device can be activated if the pin is used as a wired-or output. MC9S12G Family Reference Manual Rev.1.28 242 NXP Semiconductors Port Integration Module (S12GPIMV1) 2.5.2.6 Wired-Or Mode Register (WOMx) If the pin is used as an output this register turns off the active-high drive. This allows wired-or type connections of outputs. 2.5.2.7 Interrupt Enable Register (PIEx) If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable the interrupt. 2.5.2.8 Interrupt Flag Register (PIFx) If the pin is used as an interrupt input this register holds the interrupt flag after a valid pin event. 2.5.2.9 Pin Routing Register (PRRx) This register allows software re-configuration of the pinouts for specific peripherals in the 20 TSSOP package only. 2.5.2.10 Package Code Register (PKGCR) This register determines the package in use. Pre programmed by factory. 2.5.3 Pin Configuration Summary The following table summarizes the effect of the various configuration bits, that is data direction (DDR), output level (IO), pull enable (PE), pull select (PS) on the pin function and pull device 1. The configuration bit PS is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pullup or pulldown device if PE is active. 1. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 243 Port Integration Module (S12GPIMV1) Table 2-92. Pin Configuration Summary DDR IO PE PS1 IE2 0 x 0 x 0 Input3 0 3 0 x 1 0 Function Pull Device Interrupt Disabled Disabled Input Pullup Disabled Pulldown Disabled 0 x 1 1 0 Input3 0 x 0 0 1 Input3 Disabled Falling edge 0 x 0 1 1 Input3 Disabled Rising edge 1 Input3 Pullup Falling edge 3 0 x 1 0 0 x 1 1 1 Input Pulldown Rising edge 1 0 x x 0 Output, drive to 0 Disabled Disabled 1 1 x x 0 Output, drive to 1 Disabled Disabled 1 0 x 0 1 Output, drive to 0 Disabled Falling edge 1 1 x 1 1 Output, drive to 1 Disabled Rising edge 1 Always “0” on port A, B, C, D, BKGD. Always “1” on port E Applicable only on port P, J and AD. 3 Port AD: Assuming digital input buffer enabled in ADC module (ATDDIEN) and ACMP module (ACDIEN) 2 2.5.4 Interrupts This section describes the interrupts generated by the PIM and their individual sources. Vector addresses and interrupt priorities are defined at MCU level. Table 2-93. PIM Interrupt Sources Module Interrupt Sources 2.5.4.1 Local Enable XIRQ None IRQ IRQCR[IRQEN] Port P pin interrupt PIEP[PIEP7-PIEP0] Port J pin interrupt PIEJ[PIEJ7-PIEJ0] Port AD pin interrupt PIE0AD[PIE0AD7-PIE0AD0] PIE1AD[PIE1AD7-PIE1AD0] XIRQ, IRQ Interrupts The XIRQ pin allows requesting non-maskable interrupts after reset initialization. During reset, the X bit in the condition code register is set and any interrupts are masked until software enables them. The IRQ pin allows requesting asynchronous interrupts. The interrupt input is disabled out of reset. To enable the interrupt the IRQCR[IRQEN] bit must be set and the I bit cleared in the condition code register. The interrupt can be configured for level-sensitive or falling-edge-sensitive triggering. If IRQCR[IRQEN] is cleared while an interrupt is pending, the request will deassert. MC9S12G Family Reference Manual Rev.1.28 244 NXP Semiconductors Port Integration Module (S12GPIMV1) Both interrupts are capable to wake-up the device from stop mode. Means for glitch filtering are not provided on these pins. 2.5.4.2 Pin Interrupts and Wakeup Ports P, J and AD offer pin interrupt capability. The related interrupt enable (PIE) as well as the sensitivity to rising or falling edges (PPS) can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs. An interrupt is generated when a port interrupt flag (PIF) and its corresponding port interrupt enable (PIE) are both set. The pin interrupt feature is also capable to wake up the CPU when it is in stop or wait mode. A digital filter on each pin prevents short pulses from generating an interrupt. A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level. Else the sampling logic is restarted. In run and wait mode the filters are continuously clocked by the bus clock. Pulses with a duration of tPULSE < nP_MASK/fbus are assuredly filtered out while pulses with a duration of tPULSE > nP_PASS/fbus guarantee a pin interrupt. In stop mode the clock is generated by an RC-oscillator. The minimum pulse length varies over process conditions, temperature and voltage (Figure 2-65). Pulses with a duration of tPULSE < tP_MASK are assuredly filtered out while pulses with a duration of tPULSE > tP_PASS guarantee a wakeup event. Please refer to the appendix table “Pin Interrupt Characteristics” for pulse length limits. To maximize current saving the RC oscillator is active only if the following condition is true on any individual pin: Sample count VACMPM) before the initialization delay has passed, a flag will be set immediately after this. Similarly the flag will also be set when disabling the ACMP, then re-enabling it with the inputs changing to produce an opposite result to the hold state before the end of the initialization delay. By setting the ACMPC[ACICE] bit the gated comparator output can be connected to the synchronized timer input capture channel 5 (see Figure 3-1). This feature can be used to generate time stamps and timer interrupts on ACMP events. The comparator output signal synchronized to the bus clock is used to read the comparator output status (ACMPS[ACO]) and to set the interrupt flag (ACMPS[ACIF]). The condition causing the interrupt flag (ACMPS[ACIF]) to assert is selected with register bits ACMPC[ACMOD1:ACMOD0]. This includes any edge configuration, that is rising, or falling, or rising and falling (toggle) edges of the comparator output. Also flag setting can be disabled. An interrupt will be generated if the interrupt enable bit (ACMPC[ACIE]) and the interrupt flag (ACMPS[ACIF]) are both set. ACMPS[ACIF] is cleared by writing a 1. The raw comparator output signal ACMPO can be driven out on an external pin by setting the ACMPC[ACOPE] bit. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 253 5V Analog Comparator (ACMPV1) MC9S12G Family Reference Manual Rev.1.28 254 NXP Semiconductors Chapter 4 Reference Voltage Attenuator (RVAV1) Revision History Rev. No. (Item No.) Date (Submitted By) V00.05 09 Jun 2010 • Added appendix title in note to reference reduced ADC clock • Orthographical corrections aligned to Freescale Publications Style Guide V00.06 01 Jul 2010 • Aligned to S12 register guidelines V01.00 18 Oct 2010 • Initial version 4.1 Sections Affected Substantial Change(s) Introduction The reference voltage attenuator (RVA) provides a circuit for reduction of the ADC reference voltage difference VRH-VSSA to gain more ADC resolution. 4.2 Features The RVA has the following features: • Attenuation of ADC reference voltage with low long-term drift 4.3 Block Diagram The block diagram of the RVA module is shown below. Refer to device overview section “ADC VRH/VRL Signal Connection” for connection of RVA to pins and ADC module. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 255 Reference Voltage Attenuator (RVAV1) STOP VRH RVAON RVA R VRH_INT 5R to ADC VRL_INT 4R VSSA Figure 4-1. RVA Module Block Diagram 4.4 External Signals The RVA has two external input signals, VRH and VSSA. 4.5 Modes of Operation 1. Attenuation Mode The RVA is attenuating the reference voltage when enabled by the register control bit and the MCU not being in STOP mode. 2. Bypass Mode The RVA is in bypass mode either when disabled or during STOP mode. In these cases the resistor ladder of the RVA is disconnected for power saving. MC9S12G Family Reference Manual Rev.1.28 256 NXP Semiconductors Reference Voltage Attenuator (RVAV1) 4.6 Memory Map and Register Definition 4.6.1 Register Map Table 4-1 shows the RVA register map. Table 4-1. RVA Register Map Global Address Register Name 0x0276 RVACTL Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 R W Bit 0 RVAON = Unimplemented or Reserved 4.6.2 4.6.2.1 Register Descriptions RVA Control Register (RVACTL) Access: User read/write1 Address 0x0276 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 RVAON 0 Figure 4-2. RVA Control Register (RVACTL) 1 Read: Anytime Write: Anytime Table 4-2. RVACTL Register Field Descriptions Field 0 RVAON Description RVA On — This bit turns on the reference voltage attenuation. 0 RVA in bypass mode 1 RVA in attenuation mode MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 257 Reference Voltage Attenuator (RVAV1) 4.7 Functional Description The RVA is a prescaler for the ADC reference voltage. If the attenuation is turned off the resistive divider is disconnected from VSSA, VRH_INT is connected to VRH and VRL_INT is connected to VSSA. In this mode the attenuation is bypassed and the resistive divider does not draw current. If the attenuation is turned on the resistive divider is connected to VSSA, VRH_INT and VRL_INT are connected to intermediate voltage levels: VRH_INT = 0.9 * (VRH - VSSA) + VSSA Eqn. 4-1 VRL_INT = 0.4 * (VRH - VSSA) + VSSA Eqn. 4-2 The attenuated reference voltage difference (VRH_INT - VRL_INT) equals 50% of the input reference voltage difference (VRH - VSSA). With reference voltage attenuation the resolution of the ADC is improved by a factor of 2. NOTE In attenuation mode the maximum ADC clock is reduced. Please refer to the conditions in appendix A “ATD Accuracy”, table “ATD Conversion Performance 5V range, RVA enabled”. MC9S12G Family Reference Manual Rev.1.28 258 NXP Semiconductors Chapter 5 S12G Memory Map Controller (S12GMMCV1) Table 5-1. Revision History Table Rev. No. Date (Item No.) (Submitted By) 01.02 5.1 20-May 2010 Sections Affected Substantial Change(s) Updates for S12VR48 and S12VR64 Introduction The S12GMMC module controls the access to all internal memories and peripherals for the CPU12 and S12SBDM module. It regulates access priorities and determines the address mapping of the on-chip resources. Figure 5-1 shows a block diagram of the S12GMMC module. 5.1.1 Glossary Table 5-2. Glossary Of Terms Term Definition Local Addresses Address within the CPU12’s Local Address Map (Figure 5-11) Global Address Address within the Global Address Map (Figure 5-11) Aligned Bus Access Bus access to an even address. Misaligned Bus Access Bus access to an odd address. NS Normal Single-Chip Mode SS Special Single-Chip Mode Unimplemented Address Ranges Address ranges which are not mapped to any on-chip resource. NVM Non-volatile Memory; Flash or EEPROM IFR NVM Information Row. Refer to FTMRG Block Guide 5.1.2 Overview The S12GMMC connects the CPU12’s and the S12SBDM’s bus interfaces to the MCU’s on-chip resources (memories and peripherals). It arbitrates the bus accesses and determines all of the MCU’s memory maps. Furthermore, the S12GMMC is responsible for constraining memory accesses on secured devices and for selecting the MCU’s functional mode. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 259 S12G Memory Map Controller (S12GMMCV1) 5.1.3 Features The main features of this block are: • Paging capability to support a global 256 KByte memory address space • Bus arbitration between the masters CPU12, S12SBDM to different resources. • MCU operation mode control • MCU security control • Generation of system reset when CPU12 accesses an unimplemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes 5.1.4 Modes of Operation The S12GMMC selects the MCU’s functional mode. It also determines the devices behavior in secured and unsecured state. 5.1.4.1 Functional Modes Two functional modes are implemented on devices of the S12G product family: • Normal Single Chip (NS) The mode used for running applications. • Special Single Chip Mode (SS) A debug mode which causes the device to enter BDM Active Mode after each reset. Peripherals may also provide special debug features in this mode. 5.1.4.2 Security S12G devices can be secured to prohibit external access to the on-chip flash. The S12GMMC module determines the access permissions to the on-chip memories in secured and unsecured state. 5.1.5 Block Diagram Figure 5-1 shows a block diagram of the S12GMMC. MC9S12G Family Reference Manual Rev.1.28 260 NXP Semiconductors S12G Memory Map Controller (S12GMMCV1) CPU BDM MMC Address Decoder & Priority DBG Target Bus Controller EEPROM Flash RAM Peripherals Figure 5-1. S12GMMC Block Diagram 5.2 External Signal Description The S12GMMC uses two external pins to determine the devices operating mode: RESET and MODC (Figure 5-3) See Device User Guide (DUG) for the mapping of these signals to device pins. Table 5-3. External System Pins Associated With S12GMMC Pin Name Pin Functions RESET (See Section Device Overview) RESET MODC (See Section Device Overview) MODC 5.3 5.3.1 Description The RESET pin is used the select the MCU’s operating mode. The MODC pin is captured at the rising edge of the RESET pin. The captured value determines the MCU’s operating mode. Memory Map and Registers Module Memory Map A summary of the registers associated with the S12GMMC block is shown in Figure 5-2. Detailed descriptions of the registers and bits are given in the subsections that follow. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 261 S12G Memory Map Controller (S12GMMCV1) Address Register Name 0x000A Reserved Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIX3 PIX2 PIX1 PIX0 0 0 0 0 0 0 0 0 R W 0x000B MODE R MODC W 0x0010 Reserved R W 0x0011 DIRECT R W 0x0012 Reserved R W 0x0013 MMCCTL1 R W 0x0014 Reserved R NVMRES W 0x0015 PPAGE R W 0x00160x0017 Reserved R W = Unimplemented or Reserved Figure 5-2. MMC Register Summary 5.3.2 Register Descriptions This section consists of the S12GMMC control register descriptions in address order. 5.3.2.1 Mode Register (MODE) Address: 0x000B 7 R W Reset MODC MODC1 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1. External signal (see Table 5-3). = Unimplemented or Reserved Figure 5-3. Mode Register (MODE) MC9S12G Family Reference Manual Rev.1.28 262 NXP Semiconductors S12G Memory Map Controller (S12GMMCV1) Read: Anytime. Write: Only if a transition is allowed (see Figure 5-4). The MODC bit of the MODE register is used to select the MCU’s operating mode. Table 5-4. MODE Field Descriptions Field Description 7 MODC Mode Select Bit — This bit controls the current operating mode during RESET high (inactive). The external mode pin MODC determines the operating mode during RESET low (active). The state of the pin is registered into the respective register bit after the RESET signal goes inactive (see Figure 5-4). Write restrictions exist to disallow transitions between certain modes. Figure 5-4 illustrates all allowed mode changes. Attempting non authorized transitions will not change the MODE bit, but it will block further writes to the register bit except in special modes. Write accesses to the MODE register are blocked when the device is secured. RESET 1 0 Normal Single-Chip (NS) 1 Special Single-Chip (SS) 1 0 Figure 5-4. Mode Transition Diagram when MCU is Unsecured 5.3.2.2 Direct Page Register (DIRECT) Address: 0x0011 R W Reset 7 6 5 4 3 2 1 0 DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 0 0 0 0 0 0 0 0 Figure 5-5. Direct Register (DIRECT) Read: Anytime Write: anytime in special SS, write-once in NS. This register determines the position of the 256 Byte direct page within the memory map.It is valid for both global and local mapping scheme. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 263 S12G Memory Map Controller (S12GMMCV1) Table 5-5. DIRECT Field Descriptions Field Description 7–0 DP[15:8] Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct addressing mode. These register bits form bits [15:8] of the local address (see Figure 5-6). Bit15 Bit8 Bit0 Bit7 DP [15:8] CPU Address [15:0] Figure 5-6. DIRECT Address Mapping Example 5-1. This example demonstrates usage of the Direct Addressing Mode MOVB #$04,DIRECT LDY GO 18 none (Previous enable tagging and go to user program.) This command will be deprecated and should not be used anymore. Opcode will be executed as a GO command. 1 If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands. 2 When the firmware command READ_NEXT or WRITE_NEXT is used to access the BDM address space the BDM resources are accessed rather than user code. Writing BDM firmware is not possible. 3 System stop disables the ACK function and ignored commands will not have an ACK-pulse (e.g., CPU in stop or wait mode). The GO_UNTIL command will not get an Acknowledge if CPU executes the wait or stop instruction before the “UNTIL” condition (BDM active again) is reached (see Section 7.4.7, “Serial Interface Hardware Handshake Protocol” last note). 7.4.5 BDM Command Structure Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word, depending on the command. All the read commands return 16 bits of data despite the byte or word implication in the command name. 8-bit reads return 16-bits of data, only one byte of which contains valid data. If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 291 Background Debug Module (S12SBDMV1) 16-bit misaligned reads and writes are generally not allowed. If attempted by BDM hardware command, the BDM ignores the least significant bit of the address and assumes an even address from the remaining bits. For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait 150 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a free cycle before stealing a cycle. For BDM firmware read commands, the external host should wait at least 48 bus clock cycles after sending the command opcode and before attempting to obtain the read data. The 48 cycle wait allows enough time for the requested data to be made available in the BDM shift register, ready to be shifted out. For BDM firmware write commands, the external host must wait 36 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The external host should wait for at least for 76 bus clock cycles after a TRACE1 or GO command before starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM firmware lookup table and resume execution of the user code. Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup table. NOTE If the bus rate of the target processor is unknown or could be changing, it is recommended that the ACK (acknowledge function) is used to indicate when an operation is complete. When using ACK, the delay times are automated. Figure 7-6 represents the BDM command structure. The command blocks illustrate a series of eight bit times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is 8  16 target clock cycles.1 1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 7.4.6, “BDM Serial Interface” and Section 7.3.2.1, “BDM Status Register (BDMSTS)” for information on how serial clock rate is selected. MC9S12G Family Reference Manual Rev.1.28 292 NXP Semiconductors Background Debug Module (S12SBDMV1) 8 Bits AT ~16 TC/Bit 16 Bits AT ~16 TC/Bit Command Address Hardware Read 150-BC Delay 16 Bits AT ~16 TC/Bit Data Next Command 150-BC Delay Hardware Write Command Address Data Next Command 48-BC DELAY Firmware Read Command Next Command Data 36-BC DELAY Firmware Write Command Data Next Command 76-BC Delay GO, TRACE Command Next Command BC = Bus Clock Cycles TC = Target Clock Cycles Figure 7-6. BDM Command Structure 7.4.6 BDM Serial Interface The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDM. The BDM serial interface is timed based on the VCO clock (please refer to the CPMU Block Guide for more details), which gets divided by 8. This clock will be referred to as the target clock in the following explanation. The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per bit. The interface times out if 512 clock cycles occur between falling edges from the host. The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases. The timing for host-to-target is shown in Figure 7-7 and that of target-to-host in Figure 7-8 and Figure 7-9. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Since the host and target are operating from separate clocks, it can take the target system up to one full clock cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 293 Background Debug Module (S12SBDMV1) earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 7-7 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1 transmission. Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals. BDM Clock (Target MCU) Host Transmit 1 Host Transmit 0 Perceived Start of Bit Time Target Senses Bit 10 Cycles Synchronization Uncertainty Earliest Start of Next Bit Figure 7-7. BDM Host-to-Target Serial Bit Timing The receive cases are more complicated. Figure 7-8 shows the host receiving a logic 1 from the target system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time. MC9S12G Family Reference Manual Rev.1.28 294 NXP Semiconductors Background Debug Module (S12SBDMV1) BDM Clock (Target MCU) Host Drive to BKGD Pin Target System Speedup Pulse Perceived Start of Bit Time High-Impedance High-Impedance High-Impedance R-C Rise BKGD Pin 10 Cycles 10 Cycles Host Samples BKGD Pin Earliest Start of Next Bit Figure 7-8. BDM Target-to-Host Serial Bit Timing (Logic 1) Figure 7-9 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host initiates the bit time but the target finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time. BDM Clock (Target MCU) Host Drive to BKGD Pin High-Impedance Speedup Pulse Target System Drive and Speedup Pulse Perceived Start of Bit Time BKGD Pin 10 Cycles 10 Cycles Host Samples BKGD Pin Earliest Start of Next Bit Figure 7-9. BDM Target-to-Host Serial Bit Timing (Logic 0) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 295 Background Debug Module (S12SBDMV1) 7.4.7 Serial Interface Hardware Handshake Protocol BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM clock source can be modified when changing the settings for the VCO frequency (CPMUSYNR), it is very helpful to provide a handshake protocol in which the host could determine when an issued command is executed by the CPU. The BDM clock frequency is always VCO frequency divided by 8. The alternative is to always wait the amount of time equal to the appropriate number of cycles at the slowest possible rate the clock could be running. This sub-section will describe the hardware handshake protocol. The hardware handshake protocol signals to the host controller when an issued command was successfully executed by the target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the BKGD pin. This pulse is generated by the target MCU when a command, issued by the host, has been successfully executed (see Figure 7-10). This pulse is referred to as the ACK pulse. After the ACK pulse has finished: the host can start the bit retrieval if the last issued command was a read command, or start a new command if the last command was a write command or a control command (BACKGROUND, GO, GO_UNTIL or TRACE1). The ACK pulse is not issued earlier than 32 serial clock cycles after the BDM command was issued. The end of the BDM command is assumed to be the 16th tick of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse. Note also that, there is no upper limit for the delay between the command and the related ACK pulse, since the command execution depends upon the CPU bus, which in some cases could be very slow due to long accesses taking place.This protocol allows a great flexibility for the POD designers, since it does not rely on any accurate time measurement or short response time to any event in the serial communication. BDM Clock (Target MCU) Target Transmits ACK Pulse High-Impedance 32 Cycles 16 Cycles High-Impedance Speedup Pulse Minimum Delay From the BDM Command BKGD Pin Earliest Start of Next Bit 16th Tick of the Last Command Bit Figure 7-10. Target Acknowledge Pulse (ACK) NOTE If the ACK pulse was issued by the target, the host assumes the previous command was executed. If the CPU enters wait or stop prior to executing a hardware command, the ACK pulse will not be issued meaning that the BDM command was not executed. After entering wait or stop mode, the BDM command is no longer pending. MC9S12G Family Reference Manual Rev.1.28 296 NXP Semiconductors Background Debug Module (S12SBDMV1) Figure 7-11 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed (free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data, the BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved. After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the form of a word and the host needs to determine which is the appropriate byte based on whether the address was odd or even. Target BKGD Pin READ_BYTE Host Byte Address Host (2) Bytes are Retrieved New BDM Command Host Target Target BDM Issues the ACK Pulse (out of scale) BDM Decodes the Command BDM Executes the READ_BYTE Command Figure 7-11. Handshake Protocol at Command Level Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK handshake pulse is initiated by the target MCU by issuing a negative edge in the BKGD pin. The hardware handshake protocol in Figure 7-10 specifies the timing when the BKGD pin is being driven, so the host should follow this timing constraint in order to avoid the risk of an electrical conflict in the BKGD pin. NOTE The only place the BKGD pin can have an electrical conflict is when one side is driving low and the other side is issuing a speedup pulse (high). Other “highs” are pulled rather than driven. However, at low rates the time of the speedup pulse can become lengthy and so the potential conflict time becomes longer as well. The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not acknowledge by an ACK pulse, the host needs to abort the pending command first in order to be able to issue a new BDM command. When the CPU enters wait or stop while the host issues a hardware command (e.g., WRITE_BYTE), the target discards the incoming command due to the wait or stop being detected. Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be issued in this case. After a certain time the host (not aware of stop or wait) should decide to abort any possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol provides a mechanism in which a command, and its corresponding ACK, can be aborted. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 297 Background Debug Module (S12SBDMV1) NOTE The ACK pulse does not provide a time out. This means for the GO_UNTIL command that it can not be distinguished if a stop or wait has been executed (command discarded and ACK not issued) or if the “UNTIL” condition (BDM active) is just not reached yet. Hence in any case where the ACK pulse of a command is not issued the possible pending command should be aborted before issuing a new command. See the handshake abort procedure described in Section 7.4.8, “Hardware Handshake Abort Procedure”. 7.4.8 Hardware Handshake Abort Procedure The abort procedure is based on the SYNC command. In order to abort a command, which had not issued the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a speedup pulse. By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol, see Section 7.4.9, “SYNC — Request Timed Reference Pulse”, and assumes that the pending command and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been completed the host is free to issue new BDM commands. For BDM firmware READ or WRITE commands it can not be guaranteed that the pending command is aborted when issuing a SYNC before the corresponding ACK pulse. There is a short latency time from the time the READ or WRITE access begins until it is finished and the corresponding ACK pulse is issued. The latency time depends on the firmware READ or WRITE command that is issued and on the selected bus clock rate. When the SYNC command starts during this latency time the READ or WRITE command will not be aborted, but the corresponding ACK pulse will be aborted. A pending GO, TRACE1 or GO_UNTIL command can not be aborted. Only the corresponding ACK pulse can be aborted by the SYNC command. Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command. The ACK is actually aborted when a negative edge is perceived by the target in the BKGD pin. The short abort pulse should have at least 4 clock cycles keeping the BKGD pin low, in order to allow the negative edge to be detected by the target. In this case, the target will not execute the SYNC protocol but the pending command will be aborted along with the ACK pulse. The potential problem with this abort procedure is when there is a conflict between the ACK pulse and the short abort pulse. In this case, the target may not perceive the abort pulse. The worst case is when the pending command is a read command (i.e., READ_BYTE). If the abort pulse is not perceived by the target the host will attempt to send a new command after the abort pulse was issued, while the target expects the host to retrieve the accessed memory byte. In this case, host and target will run out of synchronism. However, if the command to be aborted is not a read command the short abort pulse could be used. After a command is aborted the target assumes the next negative edge, after the abort pulse, is the first bit of a new BDM command. NOTE The details about the short abort pulse are being provided only as a reference for the reader to better understand the BDM internal behavior. It is not recommended that this procedure be used in a real application. MC9S12G Family Reference Manual Rev.1.28 298 NXP Semiconductors Background Debug Module (S12SBDMV1) Since the host knows the target serial clock frequency, the SYNC command (used to abort a command) does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to assure the SYNC pulse will not be misinterpreted by the target. See Section 7.4.9, “SYNC — Request Timed Reference Pulse”. Figure 7-12 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE command. Note that, after the command is aborted a new command could be issued by the host computer. READ_BYTE CMD is Aborted by the SYNC Request (Out of Scale) BKGD Pin READ_BYTE Host Memory Address SYNC Response From the Target (Out of Scale) READ_STATUS Target Host BDM Decode and Starts to Execute the READ_BYTE Command Target New BDM Command Host Target New BDM Command Figure 7-12. ACK Abort Procedure at the Command Level NOTE Figure 7-12 does not represent the signals in a true timing scale Figure 7-13 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode. Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not a probable situation, the protocol does not prevent this conflict from happening. At Least 128 Cycles BDM Clock (Target MCU) Target MCU Drives to BKGD Pin Host Drives SYNC To BKGD Pin ACK Pulse High-Impedance Host and Target Drive to BKGD Pin Electrical Conflict Speedup Pulse Host SYNC Request Pulse BKGD Pin 16 Cycles Figure 7-13. ACK Pulse and SYNC Request Conflict MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 299 Background Debug Module (S12SBDMV1) NOTE This information is being provided so that the MCU integrator will be aware that such a conflict could occur. The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE BDM commands. This provides backwards compatibility with the existing POD devices which are not able to execute the hardware handshake protocol. It also allows for new POD devices, that support the hardware handshake protocol, to freely communicate with the target device. If desired, without the need for waiting for the ACK pulse. The commands are described as follows: • ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the ACK pulse as a response. • ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst case delay time at the appropriate places in the protocol. The default state of the BDM after reset is hardware handshake protocol disabled. All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See Section 7.4.3, “BDM Hardware Commands” and Section 7.4.4, “Standard BDM Firmware Commands” for more information on the BDM commands. The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued. In this case, the ACK_ENABLE command is ignored by the target since it is not recognized as a valid command. The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO command will issue an ACK pulse when the CPU exits from background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO_UNTIL command is equivalent to a GO command with exception that the ACK pulse, in this case, is issued when the CPU enters into background mode. This command is an alternative to the GO command and should be used when the host wants to trace if a breakpoint match occurs and causes the CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters BDM, which could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related to this command could be aborted using the SYNC command. The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode after one instruction of the application program is executed. The ACK pulse related to this command could be aborted using the SYNC command. MC9S12G Family Reference Manual Rev.1.28 300 NXP Semiconductors Background Debug Module (S12SBDMV1) 7.4.9 SYNC — Request Timed Reference Pulse The SYNC command is unlike other BDM commands because the host does not necessarily know the correct communication speed to use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host should perform the following steps: 1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication frequency (The lowest serial communication frequency is determined by the settings for the VCO clock (CPMUSYNR). The BDM clock frequency is always VCO clock frequency divided by 8.) 2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host clock.) 3. Remove all drive to the BKGD pin so it reverts to high impedance. 4. Listen to the BKGD pin for the sync response pulse. Upon detecting the SYNC request from the host, the target performs the following steps: 1. Discards any incomplete command received or bit retrieved. 2. Waits for BKGD to return to a logic one. 3. Delays 16 cycles to allow the host to stop driving the high speedup pulse. 4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency. 5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD. 6. Removes all drive to the BKGD pin so it reverts to high impedance. The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication. After the SYNC response, the target will consider the next negative edge (issued by the host) as the start of a new BDM command or the start of new SYNC request. Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the same as in a regular SYNC command. Note that one of the possible causes for a command to not be acknowledged by the target is a host-target synchronization problem. In this case, the command may not have been understood by the target and so an ACK response pulse will not be issued. 7.4.10 Instruction Tracing When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM firmware and executes a single instruction in the user code. Once this has occurred, the CPU is forced to return to the standard BDM firmware and the BDM is active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 301 Background Debug Module (S12SBDMV1) If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. Once back in standard BDM firmware execution, the program counter points to the first instruction in the interrupt service routine. Be aware when tracing through the user code that the execution of the user code is done step by step but all peripherals are free running. Hence possible timing relations between CPU code execution and occurrence of events of other peripherals no longer exist. Do not trace the CPU instruction BGND used for soft breakpoints. Tracing over the BGND instruction will result in a return address pointing to BDM firmware address space. When tracing through user code which contains stop or wait instructions the following will happen when the stop or wait instruction is traced: The CPU enters stop or wait mode and the TRACE1 command can not be finished before leaving the low power mode. This is the case because BDM active mode can not be entered after CPU executed the stop instruction. However all BDM hardware commands except the BACKGROUND command are operational after tracing a stop or wait instruction and still being in stop or wait mode. If system stop mode is entered (all bus masters are in stop mode) no BDM command is operational. As soon as stop or wait mode is exited the CPU enters BDM active mode and the saved PC value points to the entry of the corresponding interrupt service routine. In case the handshake feature is enabled the corresponding ACK pulse of the TRACE1 command will be discarded when tracing a stop or wait instruction. Hence there is no ACK pulse when BDM active mode is entered as part of the TRACE1 command after CPU exited from stop or wait mode. All valid commands sent during CPU being in stop or wait mode or after CPU exited from stop or wait mode will have an ACK pulse. The handshake feature becomes disabled only when system stop mode has been reached. Hence after a system stop mode the handshake feature must be enabled again by sending the ACK_ENABLE command. 7.4.11 Serial Communication Time Out The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any time-out limit. Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting memory or the operating mode of the MCU. This is referred to as a soft-reset. If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. The data is not available for retrieval after the time-out has occurred. This is the expected behavior if the handshake protocol is not enabled. In order to allow the data to be retrieved even with a large clock frequency mismatch (between BDM and CPU) when the hardware MC9S12G Family Reference Manual Rev.1.28 302 NXP Semiconductors Background Debug Module (S12SBDMV1) handshake protocol is enabled, the time out between a read command and the data retrieval is disabled. Therefore, the host could wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued read command. However, once the handshake pulse (ACK pulse) is issued, the time-out feature is re-activated, meaning that the target will time out after 512 clock cycles. Therefore, the host needs to retrieve the data within a 512 serial clock cycles time frame after the ACK pulse had been issued. After that period, the read command is discarded and the data is no longer available for retrieval. Any negative edge in the BKGD pin after the time-out period is considered to be a new command or a SYNC request. Note that whenever a partially issued command, or partially retrieved data, has occurred the time out in the serial communication is active. This means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative edges and the command being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received command or data retrieved to be disregarded. The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 303 Background Debug Module (S12SBDMV1) MC9S12G Family Reference Manual Rev.1.28 304 NXP Semiconductors Chapter 8 S12S Debug Module (S12SDBGV2) Table 8-1. Revision History Revision Number Revision Date Sections Affected 02.08 09.MAY.2008 General 02.09 29.MAY.2008 8.4.5.4 Added note for end aligned, PurePC, rollover case. 02.10 27.SEP.2012 General Changed cross reference formats 8.1 Summary of Changes Spelling corrections. Revision history format changed. Introduction The S12SDBG module provides an on-chip trace buffer with flexible triggering capability to allow non-intrusive debug of application software. The S12SDBG module is optimized for S12SCPU debugging. Typically the S12SDBG module is used in conjunction with the S12SBDM module, whereby the user configures the S12SDBG module for a debugging session over the BDM interface. Once configured the S12SDBG module is armed and the device leaves BDM returning control to the user program, which is then monitored by the S12SDBG module. Alternatively the S12SDBG module can be configured over a serial interface using SWI routines. 8.1.1 Glossary Of Terms COF: Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt BDM: Background Debug Mode S12SBDM: Background Debug Module DUG: Device User Guide, describing the features of the device into which the DBG is integrated WORD: 16-bit data entity Data Line: 20-bit data entity CPU: S12SCPU module DBG: S12SDBG module POR: Power On Reset MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 305 S12S Debug Module (S12SDBGV2) Tag: Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the execution stage a tag hit occurs. 8.1.2 Overview The comparators monitor the bus activity of the CPU module. A match can initiate a state sequencer transition. On a transition to the Final State, bus tracing is triggered and/or a breakpoint can be generated. Independent of comparator matches a transition to Final State with associated tracing and breakpoint can be triggered immediately by writing to the TRIG control bit. The trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads. Tracing is disabled when the MCU system is secured. 8.1.3 • • • • • • Features Three comparators (A, B and C) — Comparators A compares the full address bus and full 16-bit data bus — Comparator A features a data bus mask register — Comparators B and C compare the full address bus only — Each comparator features selection of read or write access cycles — Comparator B allows selection of byte or word access cycles — Comparator matches can initiate state sequencer transitions Three comparator modes — Simple address/data comparator match mode — Inside address range mode, Addmin  Address Addmax — Outside address range match mode, Address Addminor Address  Addmax Two types of matches — Tagged — This matches just before a specific instruction begins execution — Force — This is valid on the first instruction boundary after a match occurs Two types of breakpoints — CPU breakpoint entering BDM on breakpoint (BDM) — CPU breakpoint executing SWI on breakpoint (SWI) Trigger mode independent of comparators — TRIG Immediate software trigger Four trace modes — Normal: change of flow (COF) PC information is stored (see Section 8.4.5.2.1, “Normal Mode) for change of flow definition. — Loop1: same as Normal but inhibits consecutive duplicate source address entries — Detail: address and data for all cycles except free cycles and opcode fetches are stored — Compressed Pure PC: all program counter addresses are stored MC9S12G Family Reference Manual Rev.1.28 306 NXP Semiconductors S12S Debug Module (S12SDBGV2) • 4-stage state sequencer for trace buffer control — Tracing session trigger linked to Final State of state sequencer — Begin and End alignment of tracing to trigger 8.1.4 Modes of Operation The DBG module can be used in all MCU functional modes. During BDM hardware accesses and whilst the BDM module is active, CPU monitoring is disabled. When the CPU enters active BDM Mode through a BACKGROUND command, the DBG module, if already armed, remains armed. The DBG module tracing is disabled if the MCU is secure, however, breakpoints can still be generated. Table 8-2. Mode Dependent Restriction Summary BDM Enable BDM Active MCU Secure Comparator Matches Enabled Breakpoints Possible Tagging Possible Tracing Possible x x 1 Yes Yes Yes No 0 0 0 Yes Only SWI Yes Yes 0 1 0 1 0 0 Yes Yes Yes Yes 1 1 0 No No No No 8.1.5 Active BDM not possible when not enabled Block Diagram TAGS TAGHITS BREAKPOINT REQUESTS TO CPU COMPARATOR A COMPARATOR B COMPARATOR C COMPARATOR MATCH CONTROL CPU BUS BUS INTERFACE SECURE MATCH0 MATCH1 TAG & MATCH CONTROL LOGIC TRANSITION STATE STATE SEQUENCER STATE MATCH2 TRACE CONTROL TRIGGER TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS) Figure 8-1. Debug Module Block Diagram MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 307 S12S Debug Module (S12SDBGV2) 8.2 External Signal Description There are no external signals associated with this module. 8.3 8.3.1 Memory Map and Registers Module Memory Map A summary of the registers associated with the DBG sub-block is shown in Figure 8-2. Detailed descriptions of the registers and bits are given in the subsections that follow. Address Name 0x0020 DBGC1 R W 0x0021 DBGSR 0x0022 2 3 4 Bit 7 6 5 ARM 0 TRIG 0 R W 1TBF 0 DBGTCR R W 0 0x0023 DBGC2 R W 0 0x0024 DBGTBH R W 0x0025 DBGTBL R W 0x0026 DBGCNT R 1 TBF W 0 0x0027 DBGSCRX 0 0 0 0 0x0027 DBGMFR R W R W 0 0 0 SZE SZ SZE SZ 0 0 0 0x0028 0x0028 0x0028 R W R DBGBCTL W R DBGCCTL W DBGACTL 4 3 BDM DBGBRK 0 0 0 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SC3 SC2 SC1 SC0 0 0 MC2 MC1 MC0 TAG BRK RW RWE NDB COMPE TAG BRK RW RWE TAG BRK RW RWE 0 0 0 0 0 TSOURCE 2 1 0 SSF2 Bit 0 COMRV SSF1 SSF0 0 TRCMOD TALIGN ABCM CNT 0x0029 DBGXAH R W 0x002A DBGXAM R W Bit 15 14 13 12 11 0x002B DBGXAL R W Bit 7 6 5 4 3 0 0 COMPE COMPE Bit 17 Bit 16 10 9 Bit 8 2 1 Bit 0 Figure 8-2. Quick Reference to DBG Registers MC9S12G Family Reference Manual Rev.1.28 308 NXP Semiconductors S12S Debug Module (S12SDBGV2) Address Name 0x002C DBGADH 0x002D 0x002E 2 3 4 6 5 4 3 2 1 Bit 0 R W Bit 15 14 13 12 11 10 9 Bit 8 DBGADL R W Bit 7 6 5 4 3 2 1 Bit 0 DBGADHM R W Bit 15 14 13 12 11 10 9 Bit 8 1 Bit 0 R Bit 7 6 5 4 3 2 W This bit is visible at DBGCNT[7] and DBGSR[7] This represents the contents if the Comparator A control register is blended into this address. This represents the contents if the Comparator B control register is blended into this address This represents the contents if the Comparator C control register is blended into this address 0x002F 1 Bit 7 DBGADLM Figure 8-2. Quick Reference to DBG Registers 8.3.2 Register Descriptions This section consists of the DBG control and trace buffer register descriptions in address order. Each comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F in the DBG module register address map. When ARM is set in DBGC1, the only bits in the DBG module registers that can be written are ARM, TRIG, and COMRV[1:0]. 8.3.2.1 Debug Control Register 1 (DBGC1) Address: 0x0020 7 R W Reset ARM 0 6 5 0 0 TRIG 0 0 4 3 BDM DBGBRK 0 0 2 1 0 0 0 COMRV 0 0 = Unimplemented or Reserved Figure 8-3. Debug Control Register (DBGC1) Read: Anytime Write: Bits 7, 1, 0 anytime Bit 6 can be written anytime but always reads back as 0. Bits 4:3 anytime DBG is not armed. NOTE When disarming the DBG by clearing ARM with software, the contents of bits[4:3] are not affected by the write, since up until the write operation, ARM = 1 preventing these bits from being written. These bits must be cleared using a second write if required. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 309 S12S Debug Module (S12SDBGV2) Table 8-3. DBGC1 Field Descriptions Field Description 7 ARM Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by user software and is automatically cleared on completion of a debug session, or if a breakpoint is generated with tracing not enabled. On setting this bit the state sequencer enters State1. 0 Debugger disarmed 1 Debugger armed 6 TRIG Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of state sequencer status. When tracing is complete a forced breakpoint may be generated depending upon DBGBRK and BDM bit settings. This bit always reads back a 0. Writing a 0 to this bit has no effect. If the DBGTCR_TSOURCE bit is clear no tracing is carried out. If tracing has already commenced using BEGIN trigger alignment, it continues until the end of the tracing session as defined by the TALIGN bit, thus TRIG has no affect. In secure mode tracing is disabled and writing to this bit cannot initiate a tracing session. The session is ended by setting TRIG and ARM simultaneously. 0 Do not trigger until the state sequencer enters the Final State. 1 Trigger immediately 4 BDM Background Debug Mode Enable — This bit determines if a breakpoint causes the system to enter Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled by the ENBDM bit in the BDM module, then breakpoints default to SWI. 0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint. 1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI 3 DBGBRK S12SDBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint on reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated on completion of the tracing session. If tracing is not enabled, the breakpoint is generated immediately. 0 No Breakpoint generated 1 Breakpoint generated 1–0 COMRV Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the 8-byte window of the S12SDBG module address map, located between 0x0028 to 0x002F. Furthermore these bits determine which register is visible at the address 0x0027. See Table 8-4. Table 8-4. COMRV Encoding 8.3.2.2 COMRV Visible Comparator Visible Register at 0x0027 00 Comparator A DBGSCR1 01 Comparator B DBGSCR2 10 Comparator C DBGSCR3 11 None DBGMFR Debug Status Register (DBGSR) MC9S12G Family Reference Manual Rev.1.28 310 NXP Semiconductors S12S Debug Module (S12SDBGV2) Address: 0x0021 R 7 6 5 4 3 2 1 0 TBF 0 0 0 0 SSF2 SSF1 SSF0 — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset POR = Unimplemented or Reserved Figure 8-4. Debug Status Register (DBGSR) Read: Anytime Write: Never Table 8-5. DBGSR Field Descriptions Field Description 7 TBF Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no affect on this bit This bit is also visible at DBGCNT[7] 2–0 SSF[2:0] State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During a debug session on each transition to a new state these bits are updated. If the debug session is ended by software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer before disarming. If a debug session is ended by an internal event, then the state sequencer returns to state0 and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 8-6. Table 8-6. SSF[2:0] — State Sequence Flag Bit Encoding 8.3.2.3 SSF[2:0] Current State 000 State0 (disarmed) 001 State1 010 State2 011 State3 100 Final State 101,110,111 Reserved Debug Trace Control Register (DBGTCR) Address: 0x0022 7 R 0 W Reset 0 6 TSOURCE 0 5 4 0 0 0 0 3 2 TRCMOD 0 1 0 0 0 0 TALIGN 0 Figure 8-5. Debug Trace Control Register (DBGTCR) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 311 S12S Debug Module (S12SDBGV2) Read: Anytime Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed. Table 8-7. DBGTCR Field Descriptions Field Description 6 TSOURCE Trace Source Control Bit — The TSOURCE bit enables a tracing session given a trigger condition. If the MCU system is secured, this bit cannot be set and tracing is inhibited. This bit must be set to read the trace buffer. 0 Debug session without tracing requested 1 Debug session with tracing requested 3–2 TRCMOD Trace Mode Bits — See Section 8.4.5.2, “Trace Modes for detailed Trace Mode descriptions. In Normal Mode, change of flow information is stored. In Loop1 Mode, change of flow information is stored but redundant entries into trace memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. In Compressed Pure PC mode the program counter value for each instruction executed is stored. See Table 8-8. 0 TALIGN Trigger Align Bit — This bit controls whether the trigger is aligned to the beginning or end of a tracing session. 0 Trigger at end of stored data 1 Trigger before storing data Table 8-8. TRCMOD Trace Mode Bit Encoding 8.3.2.4 TRCMOD Description 00 Normal 01 Loop1 10 Detail 11 Compressed Pure PC Debug Control Register2 (DBGC2) Address: 0x0023 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 1 ABCM W Reset 0 0 0 = Unimplemented or Reserved Figure 8-6. Debug Control Register2 (DBGC2) Read: Anytime Write: Anytime the module is disarmed. This register configures the comparators for range matching. Table 8-9. DBGC2 Field Descriptions Field 1–0 ABCM[1:0] Description A and B Comparator Match Control — These bits determine the A and B comparator match mapping as described in Table 8-10. MC9S12G Family Reference Manual Rev.1.28 312 NXP Semiconductors S12S Debug Module (S12SDBGV2) Table 8-10. ABCM Encoding 1 ABCM Description 00 Match0 mapped to comparator A match: Match1 mapped to comparator B match. 01 Match 0 mapped to comparator A/B inside range: Match1 disabled. 10 Match 0 mapped to comparator A/B outside range: Match1 disabled. 11 Reserved1 Currently defaults to Comparator A, Comparator B disabled 8.3.2.5 Debug Trace Buffer Register (DBGTBH:DBGTBL) Address: 0x0024, 0x0025 15 R W 14 13 12 11 10 9 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 8 7 6 5 4 3 2 1 0 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR X X X X X X X X X X X X X X X X Other Resets — — — — — — — — — — — — — — — — Figure 8-7. Debug Trace Buffer Register (DBGTB) Read: Only when unlocked AND unsecured AND not armed AND TSOURCE set. Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer contents. Table 8-11. DBGTB Field Descriptions Field Description 15–0 Bit[15:0] Trace Buffer Data Bits — The Trace Buffer Register is a window through which the 20-bit wide data lines of the Trace Buffer may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer which points to the next address to be read. When the ARM bit is set the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when the module is disarmed. The DBGTB register can be read only as an aligned word, any byte reads or misaligned access of these registers return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. Similarly reads while the debugger is armed or with the TSOURCE bit clear, return 0 and do not affect the trace buffer pointer. The POR state is undefined. Other resets do not affect the trace buffer contents. 8.3.2.6 Debug Count Register (DBGCNT) Address: 0x0026 R 7 6 TBF 0 — 0 — 0 5 4 3 2 1 0 — 0 — 0 — 0 CNT W Reset POR — 0 — 0 — 0 = Unimplemented or Reserved Figure 8-8. Debug Count Register (DBGCNT) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 313 S12S Debug Module (S12SDBGV2) Read: Anytime Write: Never Table 8-12. DBGCNT Field Descriptions Field Description 7 TBF Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no affect on this bit This bit is also visible at DBGSR[7] 5–0 CNT[5:0] Count Value — The CNT bits indicate the number of valid data 20-bit data lines stored in the Trace Buffer. Table 8-13 shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer. When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The DBGCNT register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace buffer. Table 8-13. CNT Decoding Table 8.3.2.7 TBF CNT[5:0] Description 0 000000 No data valid 0 000001 000010 000100 000110 .. 111111 1 line valid 2 lines valid 4 lines valid 6 lines valid .. 63 lines valid 1 000000 64 lines valid; if using Begin trigger alignment, ARM bit will be cleared and the tracing session ends. 1 000001 .. .. 111110 64 lines valid, oldest data has been overwritten by most recent data Debug State Control Registers There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the next state for the state sequencer following a match. The three debug state control registers are located at the same address in the register address map (0x0027). Each register can be accessed using the COMRV bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register (DBGMFR). Table 8-14. State Control Register Access Encoding COMRV Visible State Control Register 00 DBGSCR1 MC9S12G Family Reference Manual Rev.1.28 314 NXP Semiconductors S12S Debug Module (S12SDBGV2) Table 8-14. State Control Register Access Encoding 8.3.2.7.1 COMRV Visible State Control Register 01 DBGSCR2 10 DBGSCR3 11 DBGMFR Debug State Control Register 1 (DBGSCR1) Address: 0x0027 R 7 6 5 4 0 0 0 0 0 0 0 W Reset 0 3 2 1 0 SC3 SC2 SC1 SC0 0 0 0 0 = Unimplemented or Reserved Figure 8-9. Debug State Control Register 1 (DBGSCR1) Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the targeted next state whilst in State1. The matches refer to the match channels of the comparator match control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1, “Debug Comparator Control Register (DBGXCTL). Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 8-15. DBGSCR1 Field Descriptions Field 3–0 SC[3:0] Description These bits select the targeted next state whilst in State1, based upon the match event. Table 8-16. State1 Sequencer Next State Selection SC[3:0] Description (Unspecified matches have no effect) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Any match to Final State Match1 to State3 Match2 to State2 Match1 to State2 Match0 to State2....... Match1 to State3 Match1 to State3.........Match0 to Final State Match0 to State2....... Match2 to State3 Either Match0 or Match1 to State2 Reserved Match0 to State3 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 315 S12S Debug Module (S12SDBGV2) Table 8-16. State1 Sequencer Next State Selection SC[3:0] Description (Unspecified matches have no effect) 1010 1011 1100 1101 1110 1111 Reserved Reserved Reserved Either Match0 or Match2 to Final State........Match1 to State2 Reserved Reserved The priorities described in Table 8-36 dictate that in the case of simultaneous matches, a match leading to final state has priority followed by the match on the lower channel number (0,1,2). Thus with SC[3:0]=1101 a simultaneous match0/match1 transitions to final state. 8.3.2.7.2 Debug State Control Register 2 (DBGSCR2) Address: 0x0027 R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 SC3 SC2 SC1 SC0 0 0 0 0 = Unimplemented or Reserved Figure 8-10. Debug State Control Register 2 (DBGSCR2) Read: If COMRV[1:0] = 01 Write: If COMRV[1:0] = 01 and DBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the targeted next state whilst in State2. The matches refer to the match channels of the comparator match control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1, “Debug Comparator Control Register (DBGXCTL). Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 8-17. DBGSCR2 Field Descriptions Field 3–0 SC[3:0] Description These bits select the targeted next state whilst in State2, based upon the match event. Table 8-18. State2 —Sequencer Next State Selection SC[3:0] Description (Unspecified matches have no effect) 0000 0001 0010 0011 0100 Match0 to State1....... Match2 to State3. Match1 to State3 Match2 to State3 Match1 to State3....... Match0 Final State Match1 to State1....... Match2 to State3. MC9S12G Family Reference Manual Rev.1.28 316 NXP Semiconductors S12S Debug Module (S12SDBGV2) Table 8-18. State2 —Sequencer Next State Selection SC[3:0] Description (Unspecified matches have no effect) 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Match2 to Final State Match2 to State1..... Match0 to Final State Either Match0 or Match1 to Final State Reserved Reserved Reserved Reserved Either Match0 or Match1 to Final State........Match2 to State3 Reserved Reserved Either Match0 or Match1 to Final State........Match2 to State1 The priorities described in Table 8-36 dictate that in the case of simultaneous matches, a match leading to final state has priority followed by the match on the lower channel number (0,1,2). 8.3.2.7.3 Debug State Control Register 3 (DBGSCR3) Address: 0x0027 R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 SC3 SC2 SC1 SC0 0 0 0 0 = Unimplemented or Reserved Figure 8-11. Debug State Control Register 3 (DBGSCR3) Read: If COMRV[1:0] = 10 Write: If COMRV[1:0] = 10 and DBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the targeted next state whilst in State3. The matches refer to the match channels of the comparator match control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1, “Debug Comparator Control Register (DBGXCTL). Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 8-19. DBGSCR3 Field Descriptions Field 3–0 SC[3:0] Description These bits select the targeted next state whilst in State3, based upon the match event. Table 8-20. State3 — Sequencer Next State Selection SC[3:0] Description (Unspecified matches have no effect) 0000 Match0 to State1 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 317 S12S Debug Module (S12SDBGV2) Table 8-20. State3 — Sequencer Next State Selection SC[3:0] Description (Unspecified matches have no effect) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Match2 to State2........ Match1 to Final State Match0 to Final State....... Match1 to State1 Match1 to Final State....... Match2 to State1 Match1 to State2 Match1 to Final State Match2 to State2........ Match0 to Final State Match0 to Final State Reserved Reserved Either Match1 or Match2 to State1....... Match0 to Final State Reserved Reserved Either Match1 or Match2 to Final State....... Match0 to State1 Match0 to State2....... Match2 to Final State Reserved The priorities described in Table 8-36 dictate that in the case of simultaneous matches, a match leading to final state has priority followed by the match on the lower channel number (0,1,2). 8.3.2.7.4 Debug Match Flag Register (DBGMFR) Address: 0x0027 R 7 6 5 4 3 2 1 0 0 0 0 0 0 MC2 MC1 MC0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 8-12. Debug Match Flag Register (DBGMFR) Read: If COMRV[1:0] = 11 Write: Never DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features 3 flag bits each mapped directly to a channel. Should a match occur on the channel during the debug session, then the corresponding flag is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag is set, further comparator matches on the same channel in the same session have no affect on that flag. 8.3.2.8 Comparator Register Descriptions Each comparator has a bank of registers that are visible through an 8-byte window in the DBG module register address map. Comparator A consists of 8 register bytes (3 address bus compare registers, two data bus compare registers, two data bus mask registers and a control register). Comparator B consists of four MC9S12G Family Reference Manual Rev.1.28 318 NXP Semiconductors S12S Debug Module (S12SDBGV2) register bytes (three address bus compare registers and a control register). Comparator C consists of four register bytes (three address bus compare registers and a control register). Each set of comparator registers can be accessed using the COMRV bits in the DBGC1 register. Unimplemented registers (e.g. Comparator B data bus and data bus masking) read as zero and cannot be written. The control register for comparator B differs from those of comparators A and C. Table 8-21. Comparator Register Layout 0x0028 CONTROL Read/Write Comparators A,B and C 0x0029 ADDRESS HIGH Read/Write Comparators A,B and C 0x002A ADDRESS MEDIUM Read/Write Comparators A,B and C 0x002B ADDRESS LOW Read/Write Comparators A,B and C 0x002C DATA HIGH COMPARATOR Read/Write Comparator A only 0x002D DATA LOW COMPARATOR Read/Write Comparator A only 0x002E DATA HIGH MASK Read/Write Comparator A only 0x002F DATA LOW MASK Read/Write Comparator A only 8.3.2.8.1 Debug Comparator Control Register (DBGXCTL) The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in the 8-byte window of the DBG module register address map. Address: 0x0028 R W Reset 7 6 5 4 3 2 1 0 SZE SZ TAG BRK RW RWE NDB COMPE 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 8-13. Debug Comparator Control Register DBGACTL (Comparator A) Address: 0x0028 7 R W Reset 6 5 4 3 2 SZE SZ TAG BRK RW RWE 0 0 0 0 0 0 1 0 0 0 COMPE 0 = Unimplemented or Reserved Figure 8-14. Debug Comparator Control Register DBGBCTL (Comparator B) Address: 0x0028 R 7 6 0 0 0 0 W Reset 5 4 3 2 TAG BRK RW RWE 0 0 0 0 1 0 0 0 COMPE 0 = Unimplemented or Reserved Figure 8-15. Debug Comparator Control Register DBGCCTL (Comparator C) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 319 S12S Debug Module (S12SDBGV2) Read: DBGACTL if COMRV[1:0] = 00 DBGBCTL if COMRV[1:0] = 01 DBGCCTL if COMRV[1:0] = 10 Write: DBGACTL if COMRV[1:0] = 00 and DBG not armed DBGBCTL if COMRV[1:0] = 01 and DBG not armed DBGCCTL if COMRV[1:0] = 10 and DBG not armed Table 8-22. DBGXCTL Field Descriptions Field Description 7 SZE (Comparators A and B) Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the associated comparator. This bit is ignored if the TAG bit in the same register is set. 0 Word/Byte access size is not used in comparison 1 Word/Byte access size is used in comparison 6 SZ (Comparators A and B) Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set. 0 Word access size is compared 1 Byte access size is compared 5 TAG Tag Select— This bit controls whether the comparator match has immediate effect, causing an immediate state sequencer transition or tag the opcode at the matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue. 0 Allow state sequencer transition immediately on match 1 On match, tag the opcode. If the opcode is about to be executed allow a state sequencer transition 4 BRK Break— This bit controls whether a comparator match terminates a debug session immediately, independent of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled using the DBGC1 bit DBGBRK. 0 The debug session termination is dependent upon the state sequencer and trigger conditions. 1 A match on this channel terminates the debug session immediately; breakpoints if active are generated, tracing, if active, is terminated and the module disarmed. 3 RW Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated comparator. The RW bit is not used if RWE = 0. This bit is ignored if the TAG bit in the same register is set. 0 Write cycle is matched1Read cycle is matched 2 RWE Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated comparator.This bit is ignored if the TAG bit in the same register is set 0 Read/Write is not used in comparison 1 Read/Write is used in comparison 1 Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator NDB register value or when the data bus differs from the register value. This bit is ignored if the TAG bit in the same (Comparator A) register is set. This bit is only available for comparator A. 0 Match on data bus equivalence to comparator register contents 1 Match on data bus difference to comparator register contents 0 COMPE Determines if comparator is enabled 0 The comparator is not enabled 1 The comparator is enabled Table 8-23 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if the corresponding TAG bit is set since the match occurs based on the tagged opcode reaching the execution stage of the instruction queue. MC9S12G Family Reference Manual Rev.1.28 320 NXP Semiconductors S12S Debug Module (S12SDBGV2) Table 8-23. Read or Write Comparison Logic Table 8.3.2.8.2 RWE Bit RW Bit RW Signal Comment 0 x 0 RW not used in comparison 0 x 1 RW not used in comparison 1 0 0 Write data bus 1 0 1 No match 1 1 0 No match 1 1 1 Read data bus Debug Comparator Address High Register (DBGXAH) Address: 0x0029 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 1 0 Bit 17 Bit 16 0 0 = Unimplemented or Reserved Figure 8-16. Debug Comparator Address High Register (DBGXAH) The DBGC1_COMRV bits determine which comparator address registers are visible in the 8-byte window from 0x0028 to 0x002F as shown in Section Table 8-24., “Comparator Address Register Visibility Table 8-24. Comparator Address Register Visibility COMRV Visible Comparator 00 DBGAAH, DBGAAM, DBGAAL 01 DBGBAH, DBGBAM, DBGBAL 10 DBGCAH, DBGCAM, DBGCAL 11 None Read: Anytime. See Table 8-24 for visible register encoding. Write: If DBG not armed. See Table 8-24 for visible register encoding. Table 8-25. DBGXAH Field Descriptions Field Description 1–0 Bit[17:16] Comparator Address High Compare Bits — The Comparator address high compare bits control whether the selected comparator compares the address bus bits [17:16] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 321 S12S Debug Module (S12SDBGV2) 8.3.2.8.3 Debug Comparator Address Mid Register (DBGXAM) Address: 0x002A R W Reset 7 6 5 4 3 2 1 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 8-17. Debug Comparator Address Mid Register (DBGXAM) Read: Anytime. See Table 8-24 for visible register encoding. Write: If DBG not armed. See Table 8-24 for visible register encoding. Table 8-26. DBGXAM Field Descriptions Field 7–0 Bit[15:8] Description Comparator Address Mid Compare Bits — The Comparator address mid compare bits control whether the selected comparator compares the address bus bits [15:8] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one 8.3.2.8.4 Debug Comparator Address Low Register (DBGXAL) Address: 0x002B R W Reset 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 8-18. Debug Comparator Address Low Register (DBGXAL) Read: Anytime. See Table 8-24 for visible register encoding. Write: If DBG not armed. See Table 8-24 for visible register encoding. Table 8-27. DBGXAL Field Descriptions Field 7–0 Bits[7:0] Description Comparator Address Low Compare Bits — The Comparator address low compare bits control whether the selected comparator compares the address bus bits [7:0] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC9S12G Family Reference Manual Rev.1.28 322 NXP Semiconductors S12S Debug Module (S12SDBGV2) 8.3.2.8.5 Debug Comparator Data High Register (DBGADH) Address: 0x002C R W Reset 7 6 5 4 3 2 1 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 8-19. Debug Comparator Data High Register (DBGADH) Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. Table 8-28. DBGADH Field Descriptions Field Description 7–0 Bits[15:8] Comparator Data High Compare Bits— The Comparator data high compare bits control whether the selected comparator compares the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. This register is available only for comparator A. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear. 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one 8.3.2.8.6 Debug Comparator Data Low Register (DBGADL) Address: 0x002D R W Reset 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 8-20. Debug Comparator Data Low Register (DBGADL) Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. Table 8-29. DBGADL Field Descriptions Field Description 7–0 Bits[7:0] Comparator Data Low Compare Bits — The Comparator data low compare bits control whether the selected comparator compares the data bus bits [7:0] to a logic one or logic zero. The comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. This register is available only for comparator A. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 323 S12S Debug Module (S12SDBGV2) 8.3.2.8.7 Debug Comparator Data High Mask Register (DBGADHM) Address: 0x002E R W Reset 7 6 5 4 3 2 1 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 8-21. Debug Comparator Data High Mask Register (DBGADHM) Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. Table 8-30. DBGADHM Field Descriptions Field Description 7–0 Bits[15:8] Comparator Data High Mask Bits — The Comparator data high mask bits control whether the selected comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear 0 Do not compare corresponding data bit Any value of corresponding data bit allows match. 1 Compare corresponding data bit 8.3.2.8.8 Debug Comparator Data Low Mask Register (DBGADLM) Address: 0x002F R W Reset 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 8-22. Debug Comparator Data Low Mask Register (DBGADLM) Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. Table 8-31. DBGADLM Field Descriptions Field 7–0 Bits[7:0] 8.4 Description Comparator Data Low Mask Bits — The Comparator data low mask bits control whether the selected comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear 0 Do not compare corresponding data bit. Any value of corresponding data bit allows match 1 Compare corresponding data bit Functional Description This section provides a complete functional description of the DBG module. If the part is in secure mode, the DBG module can generate breakpoints but tracing is not possible. MC9S12G Family Reference Manual Rev.1.28 324 NXP Semiconductors S12S Debug Module (S12SDBGV2) 8.4.1 S12SDBG Operation Arming the DBG module by setting ARM in DBGC1 allows triggering the state sequencer, storing of data in the trace buffer and generation of breakpoints to the CPU. The DBG module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer. The comparators monitor the bus activity of the CPU. All comparators can be configured to monitor address bus activity. Comparator A can also be configured to monitor databus activity and mask out individual data bus bits during a compare. Comparators can be configured to use R/W and word/byte access qualification in the comparison. A match with a comparator register value can initiate a state sequencer transition to another state (see Figure 8-24). Either forced or tagged matches are possible. Using a forced match, a state sequencer transition can occur immediately on a successful match of system busses and comparator registers. Whilst tagging, at a comparator match, the instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction queue can a state sequencer transition occur. In the case of a transition to Final State, bus tracing is triggered and/or a breakpoint can be generated. A state sequencer transition to final state (with associated breakpoint, if enabled) can be initiated by writing to the TRIG bit in the DBGC1 control register. The trace buffer is visible through a 2-byte window in the register address map and must be read out using standard 16-bit word reads. TAGS TAGHITS BREAKPOINT REQUESTS TO CPU COMPARATOR A COMPARATOR B COMPARATOR C COMPARATOR MATCH CONTROL CPU BUS BUS INTERFACE SECURE MATCH0 MATCH1 TAG & MATCH CONTROL LOGIC TRANSITION STATE STATE SEQUENCER STATE MATCH2 TRACE CONTROL TRIGGER TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS) Figure 8-23. DBG Overview 8.4.2 Comparator Modes The DBG contains three comparators, A, B and C. Each comparator compares the system address bus with the address stored in DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparator A also compares the data buses to the data stored in DBGADH, DBGADL and allows masking of individual data bus bits. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 325 S12S Debug Module (S12SDBGV2) All comparators are disabled in BDM and during BDM accesses. The comparator match control logic (see Figure 8-23) configures comparators to monitor the buses for an exact address or an address range, whereby either an access inside or outside the specified range generates a match condition. The comparator configuration is controlled by the control register contents and the range control by the DBGC2 contents. A match can initiate a transition to another state sequencer state (see Section 8.4.4, “State Sequence Control”). The comparator control register also allows the type of access to be included in the comparison through the use of the RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled for the associated comparator and the RW bit selects either a read or write access for a valid match. Similarly the SZE and SZ bits allow the size of access (word or byte) to be considered in the compare. Only comparators A and B feature SZE and SZ. The TAG bit in each comparator control register is used to determine the match condition. By setting TAG, the comparator qualifies a match with the output of opcode tracking logic and a state sequencer transition occurs when the tagged instruction reaches the CPU execution stage. Whilst tagging the RW, RWE, SZE, and SZ bits and the comparator data registers are ignored; the comparator address register must be loaded with the exact opcode address. If the TAG bit is clear (forced type match) a comparator match is generated when the selected address appears on the system address bus. If the selected address is an opcode address, the match is generated when the opcode is fetched from the memory, which precedes the instruction execution by an indefinite number of cycles due to instruction pipelining. For a comparator match of an opcode at an odd address when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an opcode at odd address (n), the comparator register must contain address (n–1). Once a successful comparator match has occurred, the condition that caused the original match is not verified again on subsequent matches. Thus if a particular data value is verified at a given address, this address may not still contain that data value when a subsequent match occurs. Match[0, 1, 2] map directly to Comparators [A, B, C] respectively, except in range modes (see Section 8.3.2.4, “Debug Control Register2 (DBGC2)). Comparator channel priority rules are described in the priority section (Section 8.4.3.4, “Channel Priorities). 8.4.2.1 Single Address Comparator Match With range comparisons disabled, the match condition is an exact equivalence of address bus with the value stored in the comparator address registers. Further qualification of the type of access (R/W, word/byte) and databus contents is possible, depending on comparator channel. 8.4.2.1.1 Comparator C Comparator C offers only address and direction (R/W) comparison. The exact address is compared, thus with the comparator address register loaded with address (n) a word access of address (n–1) also accesses (n) but does not cause a match. MC9S12G Family Reference Manual Rev.1.28 326 NXP Semiconductors S12S Debug Module (S12SDBGV2) Table 8-32. Comparator C Access Considerations Condition For Valid Match 1 Comp C Address RWE RW Examples 0 X LDAA ADDR[n] STAA #$BYTE ADDR[n] ADDR[n] 1 0 STAA #$BYTE ADDR[n] ADDR[n] 1 1 LDAA #$BYTE ADDR[n] Read and write accesses of ADDR[n] ADDR[n] 1 Write accesses of ADDR[n] Read accesses of ADDR[n] A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain the exact address from the code. 8.4.2.1.2 Comparator B Comparator B offers address, direction (R/W) and access size (word/byte) comparison. If the SZE bit is set the access size (word or byte) is compared with the SZ bit value such that only the specified size of access causes a match. Thus if configured for a byte access of a particular address, a word access covering the same address does not lead to match. Assuming the access direction is not qualified (RWE=0), for simplicity, the size access considerations are shown in Table 8-33. Table 8-33. Comparator B Access Size Considerations Condition For Valid Match 1 Comp B Address RWE SZE SZ8 Examples Word and byte accesses of ADDR[n] ADDR[n]1 0 0 X MOVB #$BYTE ADDR[n] MOVW #$WORD ADDR[n] Word accesses of ADDR[n] only ADDR[n] 0 1 0 MOVW #$WORD ADDR[n] LDD ADDR[n] Byte accesses of ADDR[n] only ADDR[n] 0 1 1 MOVB #$BYTE ADDR[n] LDAB ADDR[n] A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain the exact address from the code. Access direction can also be used to qualify a match for Comparator B in the same way as described for Comparator C in Table 8-32. 8.4.2.1.3 Comparator A Comparator A offers address, direction (R/W), access size (word/byte) and data bus comparison. Table 8-34 lists access considerations with data bus comparison. On word accesses the data byte of the lower address is mapped to DBGADH. Access direction can also be used to qualify a match for Comparator A in the same way as described for Comparator C in Table 8-32. Table 8-34. Comparator A Matches When Accessing ADDR[n] SZE SZ DBGADHM, DBGADLM 0 X $0000 Access DH=DBGADH, DL=DBGADL Byte Word Comment No databus comparison MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 327 S12S Debug Module (S12SDBGV2) SZE SZ DBGADHM, DBGADLM Access DH=DBGADH, DL=DBGADL 0 X $FF00 Byte, data(ADDR[n])=DH Word, data(ADDR[n])=DH, data(ADDR[n+1])=X Comment Match data( ADDR[n]) 0 X $00FF Word, data(ADDR[n])=X, data(ADDR[n+1])=DL Match data( ADDR[n+1]) 0 X $00FF Byte, data(ADDR[n])=X, data(ADDR[n+1])=DL Possible unintended match 0 X $FFFF Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL Match data( ADDR[n], ADDR[n+1]) 0 X $FFFF Byte, data(ADDR[n])=DH, data(ADDR[n+1])=DL Possible unintended match 1 0 $0000 Word No databus comparison 1 0 $00FF Word, data(ADDR[n])=X, data(ADDR[n+1])=DL Match only data at ADDR[n+1] 1 0 $FF00 Word, data(ADDR[n])=DH, data(ADDR[n+1])=X Match only data at ADDR[n] 1 0 $FFFF Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL Match data at ADDR[n] & ADDR[n+1] 1 1 $0000 Byte No databus comparison 1 1 $FF00 Byte, data(ADDR[n])=DH Match data at ADDR[n] 8.4.2.1.4 Comparator A Data Bus Comparison NDB Dependency Comparator A features an NDB control bit, which allows data bus comparators to be configured to either trigger on equivalence or trigger on difference. This allows monitoring of a difference in the contents of an address location from an expected value. When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by clearing the corresponding mask bit (DBGADHM/DBGADLM) so that it is ignored in the comparison. A match occurs when all data bus bits with corresponding mask bits set are equivalent. If all mask register bits are clear, then a match is based on the address bus only, the data bus is ignored. When matching on a difference, mask bits can be cleared to ignore bit positions. A match occurs when any data bus bit with corresponding mask bit set is different. Clearing all mask bits, causes all bits to be ignored and prevents a match because no difference can be detected. In this case address bus equivalence does not cause a match. Table 8-35. NDB and MASK bit dependency 8.4.2.2 NDB DBGADHM[n] / DBGADLM[n] Comment 0 0 Do not compare data bus bit. 0 1 Compare data bus bit. Match on equivalence. 1 0 Do not compare data bus bit. 1 1 Compare data bus bit. Match on difference. Range Comparisons Using the AB comparator pair for a range comparison, the data bus can also be used for qualification by using the comparator A data registers. Furthermore the DBGACTL RW and RWE bits can be used to qualify the range comparison on either a read or a write access. The corresponding DBGBCTL bits are ignored. The SZE and SZ control bits are ignored in range mode. The comparator A TAG bit is used to tag MC9S12G Family Reference Manual Rev.1.28 328 NXP Semiconductors S12S Debug Module (S12SDBGV2) range comparisons. The comparator B TAG bit is ignored in range modes. In order for a range comparison using comparators A and B, both COMPEA and COMPEB must be set; to disable range comparisons both must be cleared. The comparator A BRK bit is used to for the AB range, the comparator B BRK bit is ignored in range mode. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries. 8.4.2.2.1 Inside Range (CompA_Addr  address  CompB_Addr) In the Inside Range comparator mode, comparator pair A and B can be configured for range comparisons. This configuration depends upon the control register (DBGC2). The match condition requires that a valid match for both comparators happens on the same bus cycle. A match condition on only one comparator is not valid. An aligned word access which straddles the range boundary is valid only if the aligned address is inside the range. 8.4.2.2.2 Outside Range (address < CompA_Addr or address > CompB_Addr) In the Outside Range comparator mode, comparator pair A and B can be configured for range comparisons. A single match condition on either of the comparators is recognized as valid. An aligned word access which straddles the range boundary is valid only if the aligned address is outside the range. Outside range mode in combination with tagging can be used to detect if the opcode fetches are from an unexpected range. In forced match mode the outside range match would typically be activated at any interrupt vector fetch or register access. This can be avoided by setting the upper range limit to $3FFFF or lower range limit to $00000 respectively. 8.4.3 Match Modes (Forced or Tagged) Match modes are used as qualifiers for a state sequencer change of state. The Comparator control register TAG bits select the match mode. The modes are described in the following sections. 8.4.3.1 Forced Match When configured for forced matching, a comparator channel match can immediately initiate a transition to the next state sequencer state whereby the corresponding flags in DBGSR are set. The state control register for the current state determines the next state. Forced matches are typically generated 2-3 bus cycles after the final matching address bus cycle, independent of comparator RWE/RW settings. Furthermore since opcode fetches occur several cycles before the opcode execution a forced match of an opcode address typically precedes a tagged match at the same address. 8.4.3.2 Tagged Match If a CPU taghit occurs a transition to another state sequencer state is initiated and the corresponding DBGSR flags are set. For a comparator related taghit to occur, the DBG must first attach tags to instructions as they are fetched from memory. When the tagged instruction reaches the execution stage of the instruction queue a taghit is generated by the CPU. This can initiate a state sequencer transition. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 329 S12S Debug Module (S12SDBGV2) 8.4.3.3 Immediate Trigger Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing to the TRIG bit in DBGC1. If configured for begin aligned tracing, this triggers the state sequencer into the Final State, if configured for end alignment, setting the TRIG bit disarms the module, ending the session and issues a forced breakpoint request to the CPU. It is possible to set both TRIG and ARM simultaneously to generate an immediate trigger, independent of the current state of ARM. 8.4.3.4 Channel Priorities In case of simultaneous matches the priority is resolved according to Table 8-36. The lower priority is suppressed. It is thus possible to miss a lower priority match if it occurs simultaneously with a higher priority. The priorities described in Table 8-36 dictate that in the case of simultaneous matches, the match pointing to final state has highest priority followed by the lower channel number (0,1,2). Table 8-36. Channel Priorities Priority Source Highest Lowest 8.4.4 Action TRIG Enter Final State Channel pointing to Final State Transition to next state as defined by state control registers Match0 (force or tag hit) Transition to next state as defined by state control registers Match1 (force or tag hit) Transition to next state as defined by state control registers Match2 (force or tag hit) Transition to next state as defined by state control registers State Sequence Control ARM = 0 State 0 (Disarmed) ARM = 1 State1 State2 ARM = 0 Session Complete (Disarm) Final State State3 ARM = 0 Figure 8-24. State Sequencer Diagram The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the trace buffer. Once the DBG module has been armed by setting the ARM bit in the DBGC1 register, then state1 of the state sequencer is entered. Further transitions between the states are then controlled by the state control registers and channel matches. From Final State the only permitted transition is back to the MC9S12G Family Reference Manual Rev.1.28 330 NXP Semiconductors S12S Debug Module (S12SDBGV2) disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state. Alternatively writing to the TRIG bit in DBGSC1, provides an immediate trigger independent of comparator matches. Independent of the state sequencer, each comparator channel can be individually configured to generate an immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers. Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer transition can be initiated by a match on other channels. If a debug session is ended by a match on a channel the state sequencer transitions through Final State for a clock cycle to state0. This is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and the debug module is disarmed. 8.4.4.1 Final State On entering Final State a trigger may be issued to the trace buffer according to the trace alignment control as defined by the TALIGN bit (see Section 8.3.2.3, “Debug Trace Control Register (DBGTCR)”). If the TSOURCE bit in DBGTCR is clear then the trace buffer is disabled and the transition to Final State can only generate a breakpoint request. In this case or upon completion of a tracing session when tracing is enabled, the ARM bit in the DBGC1 register is cleared, returning the module to the disarmed state0. If tracing is enabled a breakpoint request can occur at the end of the tracing session. If neither tracing nor breakpoints are enabled then when the final state is reached it returns automatically to state0 and the debug module is disarmed. 8.4.5 Trace Buffer Operation The trace buffer is a 64 lines deep by 20-bits wide RAM array. The DBG module stores trace information in the RAM array in a circular buffer format. The system accesses the RAM array through a register window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 20-bit trace buffer line is read, an internal pointer into the RAM increments so that the next read receives fresh information. Data is stored in the format shown in Table 8-37 and Table 8-40. After each store the counter register DBGCNT is incremented. Tracing of CPU activity is disabled when the BDM is active. Reading the trace buffer whilst the DBG is armed returns invalid data and the trace buffer pointer is not incremented. 8.4.5.1 Trace Trigger Alignment Using the TALIGN bit (see Section 8.3.2.3, “Debug Trace Control Register (DBGTCR)) it is possible to align the trigger with the end or the beginning of a tracing session. If end alignment is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered; the transition to Final State signals the end of the tracing session. Tracing with Begin-Trigger starts at the opcode of the trigger. Using end alignment or when the tracing is initiated by writing to the TRIG bit whilst configured for begin alignment, tracing starts in the second cycle after the DBGC1 write cycle. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 331 S12S Debug Module (S12SDBGV2) 8.4.5.1.1 Storing with Begin Trigger Alignment Storing with begin alignment, data is not stored in the Trace Buffer until the Final State is entered. Once the trigger condition is met the DBG module remains armed until 64 lines are stored in the Trace Buffer. If the trigger is at the address of the change-of-flow instruction the change of flow associated with the trigger is stored in the Trace Buffer. Using begin alignment together with tagging, if the tagged instruction is about to be executed then the trace is started. Upon completion of the tracing session the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 8.4.5.1.2 Storing with End Trigger Alignment Storing with end alignment, data is stored in the Trace Buffer until the Final State is entered, at which point the DBG module becomes disarmed and no more data is stored. If the trigger is at the address of a change of flow instruction, the trigger event is not stored in the Trace Buffer. If all trace buffer lines have been used before a trigger event occurrs then the trace continues at the first line, overwriting the oldest entries. 8.4.5.2 Trace Modes Four trace modes are available. The mode is selected using the TRCMOD bits in the DBGTCR register. Tracing is enabled using the TSOURCE bit in the DBGTCR register. The modes are described in the following subsections. 8.4.5.2.1 Normal Mode In Normal Mode, change of flow (COF) program counter (PC) addresses are stored. COF addresses are defined as follows: • Source address of taken conditional branches (long, short, bit-conditional, and loop primitives) • Destination address of indexed JMP, JSR, and CALL instruction • Destination address of RTI, RTS, and RTC instructions • Vector address of interrupts, except for BDM vectors LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as change of flow and are not stored in the trace buffer. Stored information includes the full 18-bit address bus and information bits, which contains a source/destination bit to indicate whether the stored address was a source address or destination address. NOTE When a COF instruction with destination address is executed, the destination address is stored to the trace buffer on instruction completion, indicating the COF has taken place. If an interrupt occurs simultaneously then the next instruction carried out is actually from the interrupt service routine. The instruction at the destination address of the original program flow gets executed after the interrupt service routine. MC9S12G Family Reference Manual Rev.1.28 332 NXP Semiconductors S12S Debug Module (S12SDBGV2) In the following example an IRQ interrupt occurs during execution of the indexed JMP at address MARK1. The BRN at the destination (SUB_1) is not executed until after the IRQ service routine but the destination address is entered into the trace buffer to indicate that the indexed JMP COF has taken place. MARK1 MARK2 LDX JMP NOP #SUB_1 0,X SUB_1 BRN * ADDR1 NOP DBNE A,PART5 IRQ_ISR MARK1 IRQ_ISR SUB_1 ADDR1 8.4.5.2.2 LDAB STAB RTI #$F0 VAR_C1 ; IRQ interrupt occurs during execution of this ; ; JMP Destination address TRACE BUFFER ENTRY 1 ; RTI Destination address TRACE BUFFER ENTRY 3 ; ; Source address TRACE BUFFER ENTRY 4 ; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2 ; The execution flow taking into account the IRQ is as follows LDX JMP LDAB STAB RTI BRN NOP DBNE #SUB_1 0,X #$F0 VAR_C1 ; ; ; * A,PART5 ; ; Loop1 Mode Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it however allows the filtering out of redundant information. The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate information from a looping construct such as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the DBG module writes this value into a background register. This prevents consecutive duplicate address entries in the Trace Buffer resulting from repeated branches. Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the DBG module is designed to help find. 8.4.5.2.3 Detail Mode In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This mode is intended to supply additional information on indexed, indirect addressing modes where storing only the destination address would not provide all information required for a user to determine where the code is in error. This mode also features information bit storage to the trace buffer, for each address byte MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 333 S12S Debug Module (S12SDBGV2) storage. The information bits indicate the size of access (word or byte) and the type of access (read or write). When tracing in Detail Mode, all cycles are traced except those when the CPU is either in a free or opcode fetch cycle. 8.4.5.2.4 Compressed Pure PC Mode In Compressed Pure PC Mode, the PC addresses of all executed opcodes, including illegal opcodes are stored. A compressed storage format is used to increase the effective depth of the trace buffer. This is achieved by storing the lower order bits each time and using 2 information bits to indicate if a 64 byte boundary has been crossed, in which case the full PC is stored. Each Trace Buffer row consists of 2 information bits and 18 PC address bits NOTE: When tracing is terminated using forced breakpoints, latency in breakpoint generation means that opcodes following the opcode causing the breakpoint can be stored to the trace buffer. The number of opcodes is dependent on program flow. This can be avoided by using tagged breakpoints. 8.4.5.3 Trace Buffer Organization (Normal, Loop1, Detail modes) ADRH, ADRM, ADRL denote address high, middle and low byte respectively. The numerical suffix refers to the tracing count. The information format for Loop1 and Normal modes is identical. In Detail mode, the address and data for each entry are stored on consecutive lines, thus the maximum number of entries is 32. In this case DBGCNT bits are incremented twice, once for the address line and once for the data line, on each trace buffer entry. In Detail mode CINF comprises of R/W and size access information (CRW and CSZ respectively). Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (DATAL) and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to trace buffer byte1 and the byte at the higher address is stored to byte0. Table 8-37. Trace Buffer Organization (Normal,Loop1,Detail modes) Mode Entry Number Entry 1 8-bits 8-bits Field 2 Field 1 Field 0 CINF1,ADRH1 ADRM1 ADRL1 0 DATAH1 DATAL1 CINF2,ADRH2 ADRM2 ADRL2 0 DATAH2 DATAL2 Entry 1 PCH1 PCM1 PCL1 Entry 2 PCH2 PCM2 PCL2 Detail Mode Entry 2 Normal/Loop1 Modes 4-bits MC9S12G Family Reference Manual Rev.1.28 334 NXP Semiconductors S12S Debug Module (S12SDBGV2) 8.4.5.3.1 Information Bit Organization The format of the bits is dependent upon the active trace mode as described below. Field2 Bits in Detail Mode Bit 3 Bit 2 CSZ CRW Bit 1 Bit 0 ADDR[17] ADDR[16] Figure 8-25. Field2 Bits in Detail Mode In Detail Mode the CSZ and CRW bits indicate the type of access being made by the CPU. Table 8-38. Field Descriptions Bit Description 3 CSZ Access Type Indicator— This bit indicates if the access was a byte or word size when tracing in Detail Mode 0 Word Access 1 Byte Access 2 CRW Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access when tracing in Detail Mode. 0 Write Access 1 Read Access 1 ADDR[17] Address Bus bit 17— Corresponds to system address bus bit 17. 0 ADDR[16] Address Bus bit 16— Corresponds to system address bus bit 16. Field2 Bits in Normal and Loop1 Modes Bit 3 Bit 2 Bit 1 Bit 0 CSD CVA PC17 PC16 Figure 8-26. Information Bits PCH Table 8-39. PCH Field Descriptions Bit Description 3 CSD Source Destination Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a source or destination address. This bit has no meaning in Compressed Pure PC mode. 0 Source Address 1 Destination Address 2 CVA Vector Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a vector address. Vector addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set. This bit has no meaning in Compressed Pure PC mode. 0 Non-Vector Destination Address 1 Vector Destination Address 1 PC17 Program Counter bit 17— In Normal and Loop1 mode this bit corresponds to program counter bit 17. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 335 S12S Debug Module (S12SDBGV2) Table 8-39. PCH Field Descriptions (continued) Bit Description 0 PC16 Program Counter bit 16— In Normal and Loop1 mode this bit corresponds to program counter bit 16. 8.4.5.4 Trace Buffer Organization (Compressed Pure PC mode) Table 8-40. Trace Buffer Organization Example (Compressed PurePC mode) 2-bits Line Number Field 3 Mode Compressed Pure PC Mode 6-bits 6-bits 6-bits Field 2 Field 1 Field 0 Line 1 00 Line 2 11 PC4 PC1 (Initial 18-bit PC Base Address) PC3 PC2 Line 3 01 0 0 PC5 Line 4 00 Line 5 10 Line 6 00 PC6 (New 18-bit PC Base Address) 0 PC8 PC7 PC9 (New 18-bit PC Base Address) NOTE Configured for end aligned triggering in compressed PurePC mode, then after rollover it is possible that the oldest base address is overwritten. In this case all entries between the pointer and the next base address have lost their base address following rollover. For example in Table 8-40 if one line of rollover has occurred, Line 1, PC1, is overwritten with a new entry. Thus the entries on Lines 2 and 3 have lost their base address. For reconstruction of program flow the first base address following the pointer must be used, in the example, Line 4. The pointer points to the oldest entry, Line 2. Field3 Bits in Compressed Pure PC Modes Table 8-41. Compressed Pure PC Mode Field 3 Information Bit Encoding INF1 INF0 0 0 TRACE BUFFER ROW CONTENT Base PC address TB[17:0] contains a full PC[17:0] value 0 1 Trace Buffer[5:0] contain incremental PC relative to base address zero value 1 0 Trace Buffer[11:0] contain next 2 incremental PCs relative to base address zero value 1 1 Trace Buffer[17:0] contain next 3 incremental PCs relative to base address zero value Each time that PC[17:6] differs from the previous base PC[17:6], then a new base address is stored. The base address zero value is the lowest address in the 64 address range The first line of the trace buffer always gets a base PC address, this applies also on rollover. MC9S12G Family Reference Manual Rev.1.28 336 NXP Semiconductors S12S Debug Module (S12SDBGV2) 8.4.5.5 Reading Data from Trace Buffer The data stored in the Trace Buffer can be read provided the DBG module is not armed, is configured for tracing (TSOURCE bit is set) and the system not secured. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by a single aligned word write to DBGTB when the module is disarmed. The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. The Trace Buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of valid lines can be determined. DBGCNT does not decrement as data is read. Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the pointer points to the oldest data entry, thus if no rollover has occurred, the pointer points to line0, otherwise it points to the line with the oldest entry. In compressed Pure PC mode on rollover the line with the oldest data entry may also contain newer data entries in fields 0 and 1. Thus if rollover is indicated by the TBF bit, the line status must be decoded using the INF bits in field3 of that line. If both INF bits are clear then the line contains only entries from before the last rollover. If INF0=1 then field 0 contains post rollover data but fields 1 and 2 contain pre rollover data. If INF1=1 then fields 0 and 1 contain post rollover data but field 2 contains pre rollover data. The pointer is initialized by each aligned write to DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. The least significant word of line is read out first. This corresponds to the fields 1 and 0 of Table 8-37. The next word read returns field 2 in the least significant bits [3:0] and “0” for bits [15:4]. Reading the Trace Buffer while the DBG module is armed returns invalid data and no shifting of the RAM pointer occurs. 8.4.5.6 Trace Buffer Reset State The Trace Buffer contents and DBGCNT bits are not initialized by a system reset. Thus should a system reset occur, the trace session information from immediately before the reset occurred can be read out and the number of valid lines in the trace buffer is indicated by DBGCNT. The internal pointer to the current trace buffer address is initialized by unlocking the trace buffer and points to the oldest valid data even if a reset occurred during the tracing session. To read the trace buffer after a reset, TSOURCE must be set, otherwise the trace buffer reads as all zeroes. Generally debugging occurrences of system resets is best handled using end trigger alignment since the reset may occur before the trace trigger, which in the begin trigger alignment case means no information would be stored in the trace buffer. The Trace Buffer contents and DBGCNT bits are undefined following a POR. NOTE An external pin RESET that occurs simultaneous to a trace buffer entry can, in very seldom cases, lead to either that entry being corrupted or the first entry of the session being corrupted. In such cases the other contents of the trace buffer still contain valid tracing information. The case occurs when the reset assertion coincides with the trace buffer entry clock edge. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 337 S12S Debug Module (S12SDBGV2) 8.4.6 Tagging A tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue a tag hit occurs and can initiate a state sequencer transition. Each comparator control register features a TAG bit, which controls whether the comparator match causes a state sequencer transition immediately or tags the opcode at the matched address. If a comparator is enabled for tagged comparisons, the address stored in the comparator match address registers must be an opcode address. Using Begin trigger together with tagging, if the tagged instruction is about to be executed then the transition to the next state sequencer state occurs. If the transition is to the Final State, tracing is started. Only upon completion of the tracing session can a breakpoint be generated. Using End alignment, when the tagged instruction is about to be executed and the next transition is to Final State then a breakpoint is generated immediately, before the tagged instruction is carried out. R/W monitoring, access size (SZ) monitoring and data bus monitoring are not useful if tagging is selected, since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on the type of access. Thus these bits are ignored if tagging is selected. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries. Tagging is disabled when the BDM becomes active. 8.4.7 Breakpoints It is possible to generate breakpoints from channel transitions to final state or using software to write to the TRIG bit in the DBGC1 register. 8.4.7.1 Breakpoints From Comparator Channels Breakpoints can be generated when the state sequencer transitions to the Final State. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue. If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 8-42). If no tracing session is selected, breakpoints are requested immediately. If the BRK bit is set, then the associated breakpoint is generated immediately independent of tracing trigger alignment. Table 8-42. Breakpoint Setup For CPU Breakpoints BRK TALIGN DBGBRK Breakpoint Alignment 0 0 0 Fill Trace Buffer until trigger then disarm (no breakpoints) 0 0 1 Fill Trace Buffer until trigger, then breakpoint request occurs 0 1 0 Start Trace Buffer at trigger (no breakpoints) MC9S12G Family Reference Manual Rev.1.28 338 NXP Semiconductors S12S Debug Module (S12SDBGV2) Table 8-42. Breakpoint Setup For CPU Breakpoints 0 1 1 Start Trace Buffer at trigger A breakpoint request occurs when Trace Buffer is full 1 x 1 Terminate tracing and generate breakpoint immediately on trigger 1 x 0 Terminate tracing immediately on trigger 8.4.7.2 Breakpoints Generated Via The TRIG Bit If a TRIG triggers occur, the Final State is entered whereby tracing trigger alignment is defined by the TALIGN bit. If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 8-42). If no tracing session is selected, breakpoints are requested immediately. TRIG breakpoints are possible with a single write to DBGC1, setting ARM and TRIG simultaneously. 8.4.7.3 Breakpoint Priorities If a TRIG trigger occurs after Begin aligned tracing has already started, then the TRIG no longer has an effect. When the associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent comparator channel match, it has no effect, since tracing has already started. If a forced SWI breakpoint coincides with a BGND in user code with BDM enabled, then the BDM is activated by the BGND and the breakpoint to SWI is suppressed. 8.4.7.3.1 DBG Breakpoint Priorities And BDM Interfacing Breakpoint operation is dependent on the state of the BDM module. If the BDM module is active, the CPU is executing out of BDM firmware, thus comparator matches and associated breakpoints are disabled. In addition, while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active, the breakpoint gives priority to BDM requests over SWI requests if the breakpoint happens to coincide with a SWI instruction in user code. On returning from BDM, the SWI from user code gets executed. Table 8-43. Breakpoint Mapping Summary DBGBRK BDM Bit (DBGC1[4]) BDM Enabled BDM Active Breakpoint Mapping 0 X X X No Breakpoint 1 0 X 0 Breakpoint to SWI X X 1 1 No Breakpoint 1 1 0 X Breakpoint to SWI 1 1 1 0 Breakpoint to BDM BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU actually executes the BDM firmware code, checks the ENABLE and returns if ENABLE is not set. If not serviced by the monitor then the breakpoint is re-asserted when the BDM returns to normal CPU flow. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 339 S12S Debug Module (S12SDBGV2) If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code could coincide with a DBG breakpoint. The CPU ensures that BDM requests have a higher priority than SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid a repeated breakpoint at the same address. Should a tagged or forced breakpoint coincide with a BGND in user code, then the instruction that follows the BGND instruction is the first instruction executed when normal program execution resumes. NOTE When program control returns from a tagged breakpoint using an RTI or BDM GO command without program counter modification it returns to the instruction whose tag generated the breakpoint. To avoid a repeated breakpoint at the same location reconfigure the DBG module in the SWI routine, if configured for an SWI breakpoint, or over the BDM interface by executing a TRACE command before the GO to increment the program flow past the tagged instruction. 8.5 8.5.1 Application Information State Machine scenarios Defining the state control registers as SCR1,SCR2, SCR3 and M0,M1,M2 as matches on channels 0,1,2 respectively. SCR encoding supported by S12SDBGV1 are shown in black. SCR encoding supported only in S12SDBGV2 are shown in red. For backwards compatibility the new scenarios use a 4th bit in each SCR register. Thus the existing encoding for SCRx[2:0] is not changed. 8.5.2 Scenario 1 A trigger is generated if a given sequence of 3 code events is executed. Figure 8-27. Scenario 1 SCR2=0010 SCR1=0011 State1 M1 State2 SCR3=0111 M2 State3 M0 Final State Scenario 1 is possible with S12SDBGV1 SCR encoding MC9S12G Family Reference Manual Rev.1.28 340 NXP Semiconductors S12S Debug Module (S12SDBGV2) 8.5.3 Scenario 2 A trigger is generated if a given sequence of 2 code events is executed. Figure 8-28. Scenario 2a SCR2=0101 SCR1=0011 State1 M1 M2 State2 Final State A trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into a range (COMPA,COMPB configured for range mode). M1 is disabled in range modes. Figure 8-29. Scenario 2b SCR2=0101 SCR1=0111 State1 M01 M2 State2 Final State A trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry into a range (COMPA,COMPB configured for range mode) Figure 8-30. Scenario 2c SCR2=0011 SCR1=0010 State1 M2 M0 State2 Final State All 3 scenarios 2a,2b,2c are possible with the S12SDBGV1 SCR encoding 8.5.4 Scenario 3 A trigger is generated immediately when one of up to 3 given events occurs Figure 8-31. Scenario 3 SCR1=0000 State1 M012 Final State Scenario 3 is possible with S12SDBGV1 SCR encoding 8.5.5 Scenario 4 Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B and event B must be followed by event A. 2 consecutive occurrences of event A without an intermediate MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 341 S12S Debug Module (S12SDBGV2) event B cause a trigger. Similarly 2 consecutive occurrences of event B without an intermediate event A cause a trigger. This is possible by using CompA and CompC to match on the same address as shown. Figure 8-32. Scenario 4a SCR1=0100 State1 M1 SCR3=0001 State 3 M0 M2 State2 M0 M1 M1 SCR2=0011 Final State This scenario is currently not possible using 2 comparators only. S12SDBGV2 makes it possible with 2 comparators, State 3 allowing a M0 to return to state 2, whilst a M2 leads to final state as shown. Figure 8-33. Scenario 4b (with 2 comparators) SCR1=0110 State1 M2 SCR3=1110 State 3 M0 M0 State2 M01 M2 M2 SCR2=1100 M1 disabled in range mode Final State The advantage of using only 2 channels is that now range comparisons can be included (channel0) This however violates the S12SDBGV1 specification, which states that a match leading to final state always has priority in case of a simultaneous match, whilst priority is also given to the lowest channel number. For S12SDBG the corresponding CPU priority decoder is removed to support this, such that on simultaneous taghits, taghits pointing to final state have highest priority. If no taghit points to final state then the lowest channel number has priority. Thus with the above encoding from State3, the CPU and DBG would break on a simultaneous M0/M2. MC9S12G Family Reference Manual Rev.1.28 342 NXP Semiconductors S12S Debug Module (S12SDBGV2) 8.5.6 Scenario 5 Trigger if following event A, event C precedes event B. i.e. the expected execution flow is A->B->C. Figure 8-34. Scenario 5 SCR2=0110 SCR1=0011 M1 State1 M0 State2 Final State M2 Scenario 5 is possible with the S12SDBGV1 SCR encoding 8.5.7 Scenario 6 Trigger if event A occurs twice in succession before any of 2 other events (BC) occurs. This scenario is not possible using the S12SDBGV1 SCR encoding. S12SDBGV2 includes additions shown in red. The change in SCR1 encoding also has the advantage that a State1->State3 transition using M0 is now possible. This is advantageous because range and data bus comparisons use channel0 only. Figure 8-35. Scenario 6 SCR3=1010 SCR1=1001 State1 M0 State3 M0 Final State M12 8.5.8 Scenario 7 Trigger when a series of 3 events is executed out of order. Specifying the event order as M1,M2,M0 to run in loops (120120120). Any deviation from that order should trigger. This scenario is not possible using the S12SDBGV1 SCR encoding because OR possibilities are very limited in the channel encoding. By adding OR forks as shown in red this scenario is possible. Figure 8-36. Scenario 7 M01 SCR2=1100 SCR1=1101 State1 M1 State2 SCR3=1101 M2 State3 M12 Final State M0 M02 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 343 S12S Debug Module (S12SDBGV2) On simultaneous matches the lowest channel number has priority so with this configuration the forking from State1 has the peculiar effect that a simultaneous match0/match1 transitions to final state but a simultaneous match2/match1transitions to state2. 8.5.9 Scenario 8 Trigger when a routine/event at M2 follows either M1 or M0. Figure 8-37. Scenario 8a SCR2=0101 SCR1=0111 M01 State1 M2 State2 Final State Trigger when an event M2 is followed by either event M0 or event M1 Figure 8-38. Scenario 8b SCR2=0111 SCR1=0010 State1 M2 State2 M01 Final State Scenario 8a and 8b are possible with the S12SDBGV1 and S12SDBGV2 SCR encoding 8.5.10 Scenario 9 Trigger when a routine/event at A (M2) does not follow either B or C (M1 or M0) before they are executed again. This cannot be realized with theS12SDBGV1 SCR encoding due to OR limitations. By changing the SCR2 encoding as shown in red this scenario becomes possible. Figure 8-39. Scenario 9 SCR2=1111 SCR1=0111 State1 M01 State2 M01 Final State M2 8.5.11 Scenario 10 Trigger if an event M0 occurs following up to two successive M2 events without the resetting event M1. As shown up to 2 consecutive M2 events are allowed, whereby a reset to State1 is possible after either one or two M2 events. If an event M0 occurs following the second M2, before M1 resets to State1 then a trigger MC9S12G Family Reference Manual Rev.1.28 344 NXP Semiconductors S12S Debug Module (S12SDBGV2) is generated. Configuring CompA and CompC the same, it is possible to generate a breakpoint on the third consecutive occurrence of event M0 without a reset M1. Figure 8-40. Scenario 10a SCR1=0010 State1 M1 M2 SCR2=0100 SCR3=0010 M2 State2 M0 State3 Final State M1 Figure 8-41. Scenario 10b M0 SCR2=0011 SCR1=0010 State1 M2 State2 SCR3=0000 M1 State3 Final State M0 Scenario 10b shows the case that after M2 then M1 must occur before M0. Starting from a particular point in code, event M2 must always be followed by M1 before M0. If after any M2, event M0 occurs before M1 then a trigger is generated. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 345 S12S Debug Module (S12SDBGV2) MC9S12G Family Reference Manual Rev.1.28 346 NXP Semiconductors Chapter 9 Security (S12XS9SECV2) Table 9-1. Revision History Revision Number Revision Date 02.00 27 Aug 2004 reviewed and updated for S12XD architecture 02.01 21 Feb 2007 added S12XE, S12XF and S12XS architectures 02.02 19 Apr 2007 corrected statement about Backdoor key access via BDM on XE, XF, XS 9.1 Sections Affected Description of Changes Introduction This specification describes the function of the security mechanism in the MC9S12G-Family (9SEC). NOTE No security feature is absolutely secure. However, NXP’s strategy is to make reading or copying the FLASH and/or EEPROM difficult for unauthorized users. 9.1.1 Features The user must be reminded that part of the security must lie with the application code. An extreme example would be application code that dumps the contents of the internal memory. This would defeat the purpose of security. At the same time, the user may also wish to put a backdoor in the application program. An example of this is the user downloads a security key through the SCI, which allows access to a programming routine that updates parameters stored in another section of the Flash memory. The security features of the MC9S12G-Family (in secure mode) are: • Protect the content of non-volatile memories (Flash, EEPROM) • Execution of NVM commands is restricted • Disable access to internal memory via background debug module (BDM) 9.1.2 Modes of Operation Table 9-2 gives an overview over availability of security relevant features in unsecure and secure modes. Table 9-2. Feature Availability in Unsecure and Secure Modes on S12XS Unsecure Mode Flash Array Access NS SS ✔ ✔ NX ES Secure Mode EX ST NS SS ✔ ✔ NX ES EX ST MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 347 Security (S12XS9SECV2) Table 9-2. Feature Availability in Unsecure and Secure Modes on S12XS Unsecure Mode 1 2 9.1.3 NS SS EEPROM Array Access ✔ NVM Commands NX ES Secure Mode EX ST NS SS ✔ ✔ ✔ ✔1 ✔ ✔1 ✔1 BDM ✔ ✔ — ✔2 DBG Module Trace ✔ ✔ — — NX ES EX ST Restricted NVM command set only. Please refer to the NVM wrapper block guides for detailed information. BDM hardware commands restricted to peripheral registers only. Securing the Microcontroller Once the user has programmed the Flash and EEPROM, the chip can be secured by programming the security bits located in the options/security byte in the Flash memory array. These non-volatile bits will keep the device secured through reset and power-down. The options/security byte is located at address 0xFF0F (= global address 0x7F_FF0F) in the Flash memory array. This byte can be erased and programmed like any other Flash location. Two bits of this byte are used for security (SEC[1:0]). On devices which have a memory page window, the Flash options/security byte is also available at address 0xBF0F by selecting page 0x3F with the PPAGE register. The contents of this byte are copied into the Flash security register (FSEC) during a reset sequence. 0xFF0F 7 6 5 4 3 2 1 0 KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0 Figure 9-1. Flash Options/Security Byte The meaning of the bits KEYEN[1:0] is shown in Table 9-3. Please refer to Section 9.1.5.1, “Unsecuring the MCU Using the Backdoor Key Access” for more information. Table 9-3. Backdoor Key Access Enable Bits KEYEN[1:0] Backdoor Key Access Enabled 00 0 (disabled) 01 0 (disabled) 10 1 (enabled) 11 0 (disabled) The meaning of the security bits SEC[1:0] is shown in Table 9-4. For security reasons, the state of device security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’. MC9S12G Family Reference Manual Rev.1.28 348 NXP Semiconductors Security (S12XS9SECV2) Table 9-4. Security Bits SEC[1:0] Security State 00 1 (secured) 01 1 (secured) 10 0 (unsecured) 11 1 (secured) NOTE Please refer to the Flash block guide for actual security configuration (in section “Flash Module Security”). 9.1.4 Operation of the Secured Microcontroller By securing the device, unauthorized access to the EEPROM and Flash memory contents can be prevented. However, it must be understood that the security of the EEPROM and Flash memory contents also depends on the design of the application program. For example, if the application has the capability of downloading code through a serial port and then executing that code (e.g. an application containing bootloader code), then this capability could potentially be used to read the EEPROM and Flash memory contents even when the microcontroller is in the secure state. In this example, the security of the application could be enhanced by requiring a challenge/response authentication before any code can be downloaded. Secured operation has the following effects on the microcontroller: 9.1.4.1 • • • Background debug module (BDM) operation is completely disabled. Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for details. Tracing code execution using the DBG module is disabled. 9.1.4.2 • • • • Normal Single Chip Mode (NS) Special Single Chip Mode (SS) BDM firmware commands are disabled. BDM hardware commands are restricted to the register space. Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for details. Tracing code execution using the DBG module is disabled. Special single chip mode means BDM is active after reset. The availability of BDM firmware commands depends on the security state of the device. The BDM secure firmware first performs a blank check of both the Flash memory and the EEPROM. If the blank check succeeds, security will be temporarily turned off and the state of the security bits in the appropriate Flash memory location can be changed If the blank check fails, security will remain active, only the BDM hardware commands will be enabled, and the accessible memory space is restricted to the peripheral register area. This will allow the BDM to be used MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 349 Security (S12XS9SECV2) to erase the EEPROM and Flash memory without giving access to their contents. After erasing both Flash memory and EEPROM, another reset into special single chip mode will cause the blank check to succeed and the options/security byte can be programmed to “unsecured” state via BDM. While the BDM is executing the blank check, the BDM interface is completely blocked, which means that all BDM commands are temporarily blocked. 9.1.5 Unsecuring the Microcontroller Unsecuring the microcontroller can be done by three different methods: 1. Backdoor key access 2. Reprogramming the security bits 3. Complete memory erase (special modes) 9.1.5.1 Unsecuring the MCU Using the Backdoor Key Access In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method. This method requires that: • The backdoor key at 0xFF00–0xFF07 (= global addresses 0x3_FF00–0x3_FF07) has been programmed to a valid value. • The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’. • In single chip mode, the application program programmed into the microcontroller must be designed to have the capability to write to the backdoor key locations. The backdoor key values themselves would not normally be stored within the application data, which means the application program would have to be designed to receive the backdoor key values from an external source (e.g. through a serial port). The backdoor key access method allows debugging of a secured microcontroller without having to erase the Flash. This is particularly useful for failure analysis. NOTE No word of the backdoor key is allowed to have the value 0x0000 or 0xFFFF. 9.1.6 Reprogramming the Security Bits In normal single chip mode (NS), security can also be disabled by erasing and reprogramming the security bits within Flash options/security byte to the unsecured value. Because the erase operation will erase the entire sector from 0xFE00–0xFFFF (0x7F_FE00–0x7F_FFFF), the backdoor key and the interrupt vectors will also be erased; this method is not recommended for normal single chip mode. The application software can only erase and program the Flash options/security byte if the Flash sector containing the Flash options/security byte is not protected (see Flash protection). Thus Flash protection is a useful means of preventing this method. The microcontroller will enter the unsecured state after the next reset following the programming of the security bits to the unsecured value. MC9S12G Family Reference Manual Rev.1.28 350 NXP Semiconductors Security (S12XS9SECV2) This method requires that: • The application software previously programmed into the microcontroller has been designed to have the capability to erase and program the Flash options/security byte, or security is first disabled using the backdoor key method, allowing BDM to be used to issue commands to erase and program the Flash options/security byte. • The Flash sector containing the Flash options/security byte is not protected. 9.1.7 Complete Memory Erase (Special Modes) The microcontroller can be unsecured in special modes by erasing the entire EEPROM and Flash memory contents. When a secure microcontroller is reset into special single chip mode (SS), the BDM firmware verifies whether the EEPROM and Flash memory are erased. If any EEPROM or Flash memory address is not erased, only BDM hardware commands are enabled. BDM hardware commands can then be used to write to the EEPROM and Flash registers to mass erase the EEPROM and all Flash memory blocks. When next reset into special single chip mode, the BDM firmware will again verify whether all EEPROM and Flash memory are erased, and this being the case, will enable all BDM commands, allowing the Flash options/security byte to be programmed to the unsecured value. The security bits SEC[1:0] in the Flash security register will indicate the unsecure state following the next reset. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 351 Security (S12XS9SECV2) MC9S12G Family Reference Manual Rev.1.28 352 NXP Semiconductors Chapter 10 S12 Clock, Reset and Power Management Unit (S12CPMU) Revision History Version Revision Effective Number Date Date Author Description of Changes V04.03 29 Jan 10 29 Jan 10 Added Note in section 10.3.2.16/10-380 to precise description of API behavior after feature enable for the first time-out period. V04.04 03 Mar 10 03 Mar 10 Corrected typos. V04.05 23. Mar 10 23 Mar 10 Corrected typos. V04.06 13 Apr 10 13 Apr 10 Corrected typo in Table 10-6 V04.07 28 Apr 10 28 Apr 10 Major rework fixing typos, figures and tables and improved description of Adaptive Oscillator Filter. V04.08 03 May 10 03 Mail 10 Improved pin description in Section 10.2, “Signal Description V04.09 22 Jun 10 22 Jun 10 Changed IP-Name from OSCLCP to XOSCLCP, added OSCCLK_LCP clock name intoFigure 10-1 and Figure 10-2 updated description of Section 10.2.2, “EXTAL and XTAL. V04.10 01 Jul 10 01 Jul 10 Added TC trimming to feature list V04.11 23 Aug 10 23 Aug 10 Removed feature of adaptive oscillator filter. Register bits 6 and 4to 0in the CPMUOSC register are marked reserved and do not alter. V04.12 27 April 12 27 April 12 V04.13 10.1 6 Mar 13 6 Mar 13 Corrected wording for API interrupt flag Changed notation of IRC trim values for 0x00000 to 0b00000 Table 10-19. correction: substituted fACLK by ACLK Clock Period Introduction This specification describes the function of the Clock, Reset and Power Management Unit (S12CPMU). • The Pierce oscillator (XOSCLCP) provides a robust, low-noise and low-power external clock source. It is designed for optimal start-up margin with typical quartz crystals and ceramic resonators. • The Voltage regulator (IVREG) operates from the range 3.13V to 5.5V. It provides all the required chip internal voltages and voltage monitors. • The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 353 S12 Clock, Reset and Power Management Unit (S12CPMU) • The Internal Reference Clock (IRC1M) provides a1MHz clock. 10.1.1 Features The Pierce Oscillator (XOSCLCP) contains circuitry to dynamically control current gain in the output amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity. • Supports quartz crystals or ceramic resonators from 4MHz to 16MHz. • High noise immunity due to input hysteresis and spike filtering. • Low RF emissions with peak-to-peak swing limited dynamically • Transconductance (gm) sized for optimum start-up margin for typical crystals • Dynamic gain control eliminates the need for external current limiting resistor • Integrated resistor eliminates the need for external bias resistor. • Low power consumption: Operates from internal 1.8V (nominal) supply, Amplitude control limits power The Voltage Regulator (IVREG) has the following features: • Input voltage range from 3.13V to 5.5V • Low-voltage detect (LVD) with low-voltage interrupt (LVI) • Power-on reset (POR) • Low-voltage reset (LVR) The Phase Locked Loop (PLL) has the following features: • highly accurate and phase locked frequency multiplier • Configurable internal filter for best stability and lock time. • Frequency modulation for defined jitter and reduced emission • Automatic frequency lock detector • Interrupt request on entry or exit from locked condition • Reference clock either external (crystal) or internal square wave (1MHz IRC1M) based. • PLL stability is sufficient for LIN communication, even if using IRC1M as reference clock The Internal Reference Clock (IRC1M) has the following features: • Frequency trimming (A factory trim value for 1MHz is loaded from Flash Memory into the IRCTRIM register after reset, which can be overwritten by application if required) • Temperature Coefficient (TC) trimming. (A factory trim value is loaded from Flash Memory into the IRCTRIM register to turned off TC trimming after reset. Application can trim the TC if required by overwriting the IRCTRIM register). • Other features of the S12CPMU include • Clock monitor to detect loss of crystal MC9S12G Family Reference Manual Rev.1.28 354 NXP Semiconductors S12 Clock, Reset and Power Management Unit (S12CPMU) • • • Autonomous periodical interrupt (API) Bus Clock Generator — Clock switch to select either PLLCLK or external crystal/resonator based Bus Clock — PLLCLK divider to adjust system speed System Reset generation from the following possible sources: — Power-on reset (POR) — Low-voltage reset (LVR) — Illegal address access — COP time out — Loss of oscillation (clock monitor fail) — External pin RESET 10.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the S12CPMU. 10.1.2.1 Run Mode The voltage regulator is in Full Performance Mode (FPM). The Phase Locked Loop (PLL) is on. The Internal Reference Clock (IRC1M) is on. The API is available. • PLL Engaged Internal (PEI) — This is the default mode after System Reset and Power-On Reset. — The Bus Clock is based on the PLLCLK. — After reset the PLL is configured for 50 MHz VCOCLK operation Post divider is 0x03, so PLLCLK is VCOCLK divided by 4, that is 12.5MHz and Bus Clock is 6.25MHz. The PLL can be re-configured for other bus frequencies. — The reference clock for the PLL (REFCLK) is based on internal reference clock IRC1M • PLL Engaged External (PEE) — The Bus Clock is based n the PLLCLK. — This mode can be entered from default mode PEI by performing the following steps: – Configure the PLL for desired bus frequency. – Program the reference divider (REFDIV[3:0] bits) to divide down oscillator frequency if necessary. – Enable the external oscillator (OSCE bit) – Wait for oscillator to start up (UPOSC=1) and PLL to lock (LOCK=1). • PLL Bypassed External (PBE) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 355 S12 Clock, Reset and Power Management Unit (S12CPMU) — The Bus Clock is based on the Oscillator Clock (OSCCLK). — The PLLCLK is always on to qualify the external oscillator clock. Therefore it is necessary to make sure a valid PLL configuration is used for the selected oscillator frequency. — This mode can be entered from default mode PEI by performing the following steps: – Make sure the PLL configuration is valid for the selected oscillator frequency. – Enable the external oscillator (OSCE bit) – Wait for oscillator to start up (UPOSC=1) – Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0). — The PLLCLK is on and used to qualify the external oscillator clock. 10.1.2.2 Wait Mode For S12CPMU Wait Mode is the same as Run Mode. 10.1.2.3 Stop Mode This mode is entered by executing the CPU STOP instruction. The voltage regulator is in Reduced Power Mode (RPM). The API is available. The Phase Locked Loop (PLL) is off. The Internal Reference Clock (IRC1M) is off. Core Clock, Bus Clock and BDM Clock are stopped. Depending on the setting of the PSTP and the OSCE bit, Stop Mode can be differentiated between Full Stop Mode (PSTP = 0 or OSCE=0) and Pseudo Stop Mode (PSTP = 1 and OSCE=1). In addition, the behavior of the COP in each mode will change based on the clocking method selected by COPOSCSEL[1:0]. • Full Stop Mode (PSTP = 0 or OSCE=0) External oscillator (XOSCLCP) is disabled. — If COPOSCSEL1=0: The COP and RTI counters halt during Full Stop Mode. After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK (PLLSEL=1). COP and RTI are running on IRCCLK (COPOSCSEL0=0, RTIOSCSEL=0). — If COPOSCSEL1=1: During Full Stop Mode the COP is running on ACLK (trimmable internal RC-Oscillator clock) and the RTI counter halts. After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK (PLLSEL=1). The COP runs on ACLK and RTI is running on IRCCLK (COPOSCSEL0=0, RTIOSCSEL=0). MC9S12G Family Reference Manual Rev.1.28 356 NXP Semiconductors S12 Clock, Reset and Power Management Unit (S12CPMU) • Pseudo Stop Mode (PSTP = 1 and OSCE=1) External oscillator (XOSCLCP) continues to run. — If COPOSCSEL1=0: If the respective enable bits are set (PCE=1 and PRE=1) the COP and RTI will continue to run with a clock derived from the oscillator clock. The clock configuration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged. — If COPOSCSEL1=1: If the respective enable bit for the RTI is set (PRE=1) the RTI will continue to run with a clock derived from the oscillator clock. The COP will continue to run on ACLK. The clock configuration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged. NOTE When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator tUPOSC before entering Pseudo Stop Mode. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 357 S12 Clock, Reset and Power Management Unit (S12CPMU) 10.1.3 S12CPMU Block Diagram Illegal Address Access MMC VDD, VDDF (core supplies) Low Voltage Detect VDDA VDDR VSS ILAF LVDS Low Voltage Interrupt LVIE Low Voltage Detect VDDX VDDX VSSX Voltage Regulator 3.13 to 5.5V VDDA VSSA LVRF Power-On Detect S12CPMU PORF RESET Clock Monitor External Loop OSCCLK_LCP EXTAL Controlled Pierce Oscillator XTAL (XOSCLCP) 4MHz-16MHz REFDIV[3:0] IRCTRIM[9:0] Reference Divider OSCE UPOSC Internal Reference Clock (IRC1M) Power-On Reset Reset Generator monitor fail PSTP COP time out System Reset UPOSC=0 sets PLLSEL bit Oscillator status Interrupt OSCIE OSCCLK CAN_OSCCLK (to MSCAN) & PLLSEL POSTDIV[4:0] ECLK2X (Core Clock) Post Divider 1,2,.,32 divide by 4 PLLCLK ECLK divide by 2 (Bus Clock) IRCCLK (to LCD) VCOFRQ[1:0] divide by 8 VCOCLK Lock detect REFCLK FBCLK Phase locked Loop with internal Filter (PLL) BDM Clock REFFRQ[1:0] LOCK LOCKIE Divide by 2*(SYNDIV+1) COPOSCSEL1 UPOSC ACLK IRCCLK OSCCLK SYNDIV[5:0] Bus Clock RC Osc. ACLK APICLK COP time out COPCLK COP to Reset Watchdog Generator IRCCLK COPOSCSEL0 UPOSC=0 clears PCE CPMUCOP OSCCLK PLL Lock Interrupt Autonomous API_EXTCLK Periodic Interrupt (API) APIE RTIE API Interrupt RTI Interrupt Real Time RTICLK Interrupt (RTI) RTIOSCSEL PRE CPMURTI Figure 10-1. Block diagram of S12CPMU MC9S12G Family Reference Manual Rev.1.28 358 NXP Semiconductors S12 Clock, Reset and Power Management Unit (S12CPMU) Figure 10-2 shows a block diagram of the XOSCLCP. OSCCLK_LCP monitor fail Clock Monitor Peak Detector Gain Control VDD = 1.8 V VSS Rf Quartz Crystals EXTAL or Ceramic Resonators XTAL C1 C2 VSS VSS Figure 10-2. XOSCLCP Block Diagram 10.2 Signal Description This section lists and describes the signals that connect off chip. 10.2.1 RESET Pin RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered. 10.2.2 EXTAL and XTAL These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. If XOSCLCP is enabled, the MCU internal OSCCLK_LCP is derived from the EXTAL input frequency. If OSCE=0, the EXTAL pin is pulled down by an internal resistor of approximately 200 k and the XTAL pin is pulled down by an internal resistor of approximately 700 k. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 359 S12 Clock, Reset and Power Management Unit (S12CPMU) NOTE NXP recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. The loop controlled circuit (XOSCLCP) is not suited for overtone resonators and crystals. 10.2.3 VDDR — Regulator Power Input Pin Pin VDDR is the power input of IVREG. All currents sourced into the regulator loads flow through this pin. An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDR and VSS can smooth ripple on VDDR. 10.2.4 VSS — Ground Pin VSS must be grounded. 10.2.5 VDDA, VSSA — Regulator Reference Supply Pins Pins VDDA and VSSA are used to supply the analog parts of the regulator. Internal precision reference circuits are supplied from these signals. An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDA and VSSA can improve the quality of this supply. 10.2.6 VDDX, VSSX— Pad Supply Pins This supply domain is monitored by the Low Voltage Reset circuit. An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDX and VSSX can improve the quality of this supply. NOTE Depending on the device package following device supply pins are maybe combined into one pin: VDDR, VDDX and VDDA. Depending on the device package following device supply pins are maybe combined into one pin: VSS, VSSX and VSSA. Please refer to the device Reference Manual for information if device supply pins are combined into one supply pin for certain packages and which supply pins are combined together. An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between the combined supply pin pair can improve the quality of this supply. MC9S12G Family Reference Manual Rev.1.28 360 NXP Semiconductors S12 Clock, Reset and Power Management Unit (S12CPMU) 10.2.7 VDD — Internal Regulator Output Supply (Core Logic) Node VDD is a device internal supply output of the voltage regulator that provides the power supply for the core logic. This supply domain is monitored by the Low Voltage Reset circuit. 10.2.8 VDDF — Internal Regulator Output Supply (NVM Logic) Node VDDF is a device internal supply output of the voltage regulator that provides the power supply for the NVM logic. This supply domain is monitored by the Low Voltage Reset circuit 10.2.9 API_EXTCLK — API external clock output pin This pin provides the signal selected via APIES and is enabled with APIEA bit. See device specification to which pin it connects. 10.3 Memory Map and Registers This section provides a detailed description of all registers accessible in the S12CPMU. 10.3.1 Module Memory Map The S12CPMU registers are shown in Figure 10-3. Addres s Name 0x0034 CPMU SYNR 0x0035 CPMU REFDIV 0x0036 CPMU POSTDIV 0x0037 CPMUFLG 0x0038 CPMUINT 0x0039 CPMUCLKS 0x003A CPMUPLL Bit 7 R W R W R 6 5 4 VCOFRQ[1:0] REFFRQ[1:0] 3 W R 0 0 0 0 RTIF PORF LVRF 0 0 W R W R W RTIE PLLSEL PSTP 0 0 1 Bit 0 SYNDIV[5:0] 0 REFDIV[3:0] POSTDIV[4:0] W R 2 LOCKIF LOCKIE 0 COP OSCSEL1 FM1 FM0 LOCK ILAF OSCIF UPOSC 0 0 PRE PCE RTI OSCSEL COP OSCSEL0 0 0 0 0 OSCIE 0 = Unimplemented or Reserved Figure 10-3. CPMU Register Summary MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 361 S12 Clock, Reset and Power Management Unit (S12CPMU) Addres s Name 0x003B CPMURTI 0x003C CPMUCOP R W R W Bit 7 6 5 4 3 2 1 Bit 0 RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 WCOP RSBCK 0 0 0 CR2 CR1 CR0 WRTMASK 0x003D RESERVEDCP R MUTEST0 W 0 0 0 0 0 0 0 0 0x003E RESERVEDCP R MUTEST1 W 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDS LVIE LVIF 0 0 APIES APIEA APIFE APIE APIF ACLKTR5 ACLKTR4 ACLKTR3 0 0 APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0 RESERVEDCP R MUTEST3 W 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 0x003F CPMU ARMCOP 0x02F0 RESERVED 0x02F1 CPMU LVCTL W 0x02F2 CPMU APICTL W 0x02F3 CPMUACLKTR 0x02F4 CPMUAPIRH 0x02F5 CPMUAPIRL 0x02F6 0x02F7 RESERVED 0x02F8 CPMU IRCTRIMH 0x02F9 CPMU IRCTRIML 0x02FA CPMUOSC W R R R W R W R W APICLK ACLKTR2 ACLKTR1 ACLKTR0 W R 0 TCTRIM[4:0] W R IRCTRIM[9:8] IRCTRIM[7:0] W R OSCE Reserved OSCPINS_ EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved W 0x02FB 0x02FC CPMUPROT R W RESERVEDCP R MUTEST2 W PROT 0 = Unimplemented or Reserved Figure 10-3. CPMU Register Summary MC9S12G Family Reference Manual Rev.1.28 362 NXP Semiconductors S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2 Register Descriptions This section describes all the S12CPMU registers and their individual bits. Address order is as listed in Figure 10-3. 10.3.2.1 S12CPMU Synthesizer Register (CPMUSYNR) The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency range. 0x0034 7 R W Reset 6 5 4 3 VCOFRQ[1:0] 0 2 1 0 0 0 0 SYNDIV[5:0] 1 0 1 1 Figure 10-4. S12CPMU Synthesizer Register (CPMUSYNR) Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect. NOTE Writing to this register clears the LOCK and UPOSC status bits. If PLL has locked (LOCK=1) f VCO = 2  f REF   SYNDIV + 1  NOTE fVCO must be within the specified VCO frequency lock range. Bus frequency fbus must not exceed the specified maximum. The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK frequency as shown in Table 10-1. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufficient stability). Table 10-1. VCO Clock Frequency Selection VCOCLK Frequency Ranges VCOFRQ[1:0] 32MHz TIMxxx - Correct reference: Figure 23-25 -> Figure 23-30 - Add description, “a counter overflow when TTOV[7] is set”, to be the condition of channel 7 override event. - Phrase the description of OC7M to make it more explicit -single source generate different channel guide 23.1 Introduction The basic scalable timer consists of a 16-bit, software-programmable counter driven by a flexible programmable prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from microseconds to many seconds. This timer could contain up to 8 input capture/output compare channels with one pulse accumulator available only on channel 7. The input capture function is used to detect a selected transition edge and record the time. The output compare function is used for generating output signals or for timer software delays. The 16-bit pulse accumulator is used to operate as a simple event counter or a gated time accumulator. The pulse accumulator shares timer channel 7 when the channel is available and when in event mode. A full access for the counter registers or the input capture/output compare registers should take place in one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word. 23.1.1 Features The TIM16B8CV3 includes these distinctive features: • Up to 8 channels available. (refer to device specification for exact number) • All channels have same input capture/output compare functionality. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 737 Timer Module (TIM16B8CV3) • • • Clock prescaling. 16-bit counter. 16-bit pulse accumulator on channel 7 . 23.1.2 Modes of Operation Stop: Timer is off because clocks are stopped. Freeze: Timer counter keeps on running, unless TSFRZ in TSCR1 is set to 1. Wait: Counters keeps on running, unless TSWAI in TSCR1 is set to 1. Normal: Timer counter keep on running, unless TEN in TSCR1 is cleared to 0. 23.1.3 Block Diagrams MC9S12G Family Reference Manual Rev.1.28 738 NXP Semiconductors Timer Module (TIM16B8CV3) Bus clock Prescaler 16-bit Counter Channel 0 Input capture Output compare Channel 1 Input capture Output compare Channel 2 Input capture Output compare Timer overflow interrupt Timer channel 0 interrupt Channel 3 Input capture Output compare Registers Channel 4 Input capture Output compare Channel 5 Input capture Output compare Timer channel 7 interrupt PA overflow interrupt PA input interrupt Channel 6 Input capture Output compare IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 Channel 7 16-bit Pulse accumulator Input capture Output compare IOC7 Maximum possible channels, scalable from 0 to 7. Pulse Accumulator is available only if channel 7 exists. Figure 23-1. TIM16B8CV3 Block Diagram MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 739 Timer Module (TIM16B8CV3) TIMCLK(Timer clock) Clock select (PAMOD) PACLK PACLK / 256 Prescaled clock (PCLK) 4:1 MUX PACLK / 65536 Intermodule Bus CLK1 CLK0 Edge detector IOC7 Interrupt PACNT MUX Divide by 64 M clock Figure 23-2. 16-Bit Pulse Accumulator Block Diagram 16-bit Main Timer IOCn Edge detector Set CnF Interrupt TCn Input Capture Reg. Figure 23-3. Interrupt Flag Setting MC9S12G Family Reference Manual Rev.1.28 740 NXP Semiconductors Timer Module (TIM16B8CV3) PULSE ACCUMULATOR PAD CHANNEL 7 OUTPUT COMPARE OCPD TEN TIOS7 Figure 23-4. Channel 7 Output Compare/Pulse Accumulator Logic 23.2 External Signal Description The TIM16B8CV3 module has a selected number of external pins. Refer to device specification for exact number. 23.2.1 IOC7 — Input Capture and Output Compare Channel 7 This pin serves as input capture or output compare for channel 7 . This can also be configured as pulse accumulator input. 23.2.2 IOC6 - IOC0 — Input Capture and Output Compare Channel 6-0 Those pins serve as input capture or output compare for TIM16B8CV3 channel . NOTE For the description of interrupts see Section 23.6, “Interrupts”. 23.3 Memory Map and Register Definition This section provides a detailed description of all memory and registers. 23.3.1 Module Memory Map The memory map for the TIM16B8CV3 module is given below in Figure 23-5. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the TIM16B8CV3 module and the address offset for each register. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 741 Timer Module (TIM16B8CV3) 23.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Only bits related to implemented channels are valid. Register Name 0x0000 TIOS 0x0010–0x001F TCxH–TCxL1 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0x0020 PACTL R W R W 0x0001 CFORC 0x0002 OC7M 0x0003 OC7D 0x0004 TCNTH 0x0005 TCNTL 0x0006 TSCR1 0x0007 TTOV 0x0008 TCTL1 0x0009 TCTL2 0x000A TCTL3 0x000B TCTL4 0x000C TIE 0x000D TSCR2 0x000E TFLG1 0x000F TFLG2 Bit 7 6 5 4 3 2 1 Bit 0 IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 0 FOC7 0 FOC6 0 FOC5 0 FOC4 0 FOC3 0 FOC2 0 FOC1 0 FOC0 OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 TEN TSWAI TSFRZ TFFCA PRNT 0 0 0 TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A C7I C6I C5I C4I C3I C2I C1I C0I 0 0 0 TCRE PR2 PR1 PR0 C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI TOI C7F TOF 0 Figure 23-5. TIM16B8CV3 Register Summary (Sheet 1 of 2) MC9S12G Family Reference Manual Rev.1.28 742 NXP Semiconductors Timer Module (TIM16B8CV3) Register Name Bit 7 0x0021 PAFLG 0x0022 PACNTH 0x0023 PACNTL 0x0024–0x002B Reserved 0x002C OCPD 0x002D Reserved 0x002E PTPSR 5 4 R 0 0 0 0 W R PACNT15 PACNT14 PACNT13 PACNT12 W R PACNT7 PACNT6 PACNT5 PACNT4 W R W R OCPD7 OCPD6 OCPD5 OCPD4 W R R W R W 0x002F Reserved 6 PTPS7 PTPS6 PTPS5 3 2 1 Bit 0 0 0 PAOVF PAIF PACNT11 PACNT10 PACNT9 PACNT8 PACNT3 PACNT2 PACNT1 PACNT0 OCPD3 OCPD2 OCPD1 OCPD0 PTPS3 PTPS2 PTPS1 PTPS0 PTPS4 Figure 23-5. TIM16B8CV3 Register Summary (Sheet 2 of 2) 1 The register is available only if corresponding channel exists. 23.3.2.1 Timer Input Capture/Output Compare Select (TIOS) Module Base + 0x0000 R W Reset 7 6 5 4 3 2 1 0 IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 0 0 0 0 0 0 0 0 Figure 23-6. Timer Input Capture/Output Compare Select (TIOS) Read: Anytime Write: Anytime Table 23-2. TIOS Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field 7:0 IOS[7:0] Description Input Capture or Output Compare Channel Configuration 0 The corresponding implemented channel acts as an input capture. 1 The corresponding implemented channel acts as an output compare. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 743 Timer Module (TIM16B8CV3) 23.3.2.2 Timer Compare Force Register (CFORC) Module Base + 0x0001 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 0 0 0 0 0 0 0 0 Reset Figure 23-7. Timer Compare Force Register (CFORC) Read: Anytime but will always return 0x0000 (1 state is transient) Write: Anytime Table 23-3. CFORC Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description 7:0 FOC[7:0] Note: Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare “x” to occur immediately. The action taken is the same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not get set. A channel 7 event, which can be a counter overflow when TTOV[7] is set or a successful output compare on channel 7, overrides any channel 6:0 compares. If forced output compare on any channel occurs at the same time as the successful output compare then forced output compare action will take precedence and interrupt flag won’t get set. 23.3.2.3 Output Compare 7 Mask Register (OC7M) Module Base + 0x0002 R W Reset 7 6 5 4 3 2 1 0 OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 0 0 0 0 0 0 0 0 Figure 23-8. Output Compare 7 Mask Register (OC7M) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.28 744 NXP Semiconductors Timer Module (TIM16B8CV3) Table 23-4. OC7M Field Descriptions Field Description 7:0 OC7M[7:0] Output Compare 7 Mask — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a successful output compare on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set, the output compare action reflects the corresponding OC7D bit. 0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on a channel 7 event, even if the corresponding pin is setup for output compare. 1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a channel 7 event. Note: The corresponding channel must also be setup for output compare (IOSx = 1 and OCPDx = 0) for data to be transferred from the output compare 7 data register to the timer port. 23.3.2.4 1 Output Compare 7 Data Register (OC7D) . Module Base + 0x0003 R W Reset 7 6 5 4 3 2 1 0 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 0 0 0 0 0 0 0 0 Figure 23-9. Output Compare 7 Data Register (OC7D) Read: Anytime Write: Anytime Table 23-5. OC7D Field Descriptions Field Description 7:0 OC7D[7:0] Output Compare 7 Data — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a successful output compare on channel 7, can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register. 23.3.2.5 Timer Count Register (TCNT) Module Base + 0x0004 R W Reset 15 14 13 12 11 10 9 9 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 0 0 0 0 0 0 0 0 Figure 23-10. Timer Count Register High (TCNTH) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 745 Timer Module (TIM16B8CV3) Module Base + 0x0005 R W Reset 7 6 5 4 3 2 1 0 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 0 0 0 0 0 0 0 0 Figure 23-11. Timer Count Register Low (TCNTL) The 16-bit main timer is an up counter. A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. Read: Anytime Write: Has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1). The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock. 23.3.2.6 Timer System Control Register 1 (TSCR1) Module Base + 0x0006 R W Reset 7 6 5 4 3 TEN TSWAI TSFRZ TFFCA PRNT 0 0 0 0 0 2 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 23-12. Timer System Control Register 1 (TSCR1) Read: Anytime Write: Anytime Table 23-6. TSCR1 Field Descriptions Field 7 TEN 6 TSWAI Description Timer Enable 0 Disables the main timer, including the counter. Can be used for reducing power consumption. 1 Allows the timer to function normally. If for any reason the timer is not active, there is no 64 clock for the pulse accumulator because the 64 is generated by the timer prescaler. Timer Module Stops While in Wait 0 Allows the timer module to continue running during wait. 1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait. TSWAI also affects pulse accumulator. MC9S12G Family Reference Manual Rev.1.28 746 NXP Semiconductors Timer Module (TIM16B8CV3) Table 23-6. TSCR1 Field Descriptions (continued) Field Description 5 TSFRZ Timer Stops While in Freeze Mode 0 Allows the timer counter to continue running while in freeze mode. 1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation. TSFRZ does not stop the pulse accumulator. 4 TFFCA Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally. 1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT register (0x0004, 0x0005) clears the TOF flag. Any access to the PACNT registers (0x0022, 0x0023) clears the PAOVF and PAIF flags in the PAFLG register (0x0021) if channel 7 exists. This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses. 3 PRNT Precision Timer 0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler selection. 1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and all bits. This bit is writable only once out of reset. 23.3.2.7 Timer Toggle On Overflow Register 1 (TTOV) Module Base + 0x0007 R W Reset 7 6 5 4 3 2 1 0 TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 0 0 0 0 0 0 0 0 Figure 23-13. Timer Toggle On Overflow Register 1 (TTOV) Read: Anytime Write: Anytime Table 23-7. TTOV Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description 7:0 TOV[7:0] Toggle On Overflow Bits — TOVx toggles output compare pin on overflow. This feature only takes effect when in output compare mode. When set, it takes precedence over forced output compare but not channel 7 override events. 0 Toggle output compare pin on overflow feature disabled. 1 Toggle output compare pin on overflow feature enabled. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 747 Timer Module (TIM16B8CV3) 23.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2) Module Base + 0x0008 R W Reset 7 6 5 4 3 2 1 0 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 0 0 0 0 0 0 0 0 Figure 23-14. Timer Control Register 1 (TCTL1) Module Base + 0x0009 R W Reset 7 6 5 4 3 2 1 0 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 0 0 0 0 0 0 0 0 Figure 23-15. Timer Control Register 2 (TCTL2) Read: Anytime Write: Anytime Table 23-8. TCTL1/TCTL2 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero Field Description 7:0 OMx Output Mode — These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: To enable output action by OMx bits on timer port, the corresponding bit in OC7M should be cleared. For an output line to be driven by an OCx the OCPDx must be cleared. 7:0 OLx Output Level — These eightpairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: To enable output action by OLx bits on timer port, the corresponding bit in OC7M should be cleared. For an output line to be driven by an OCx the OCPDx must be cleared. Table 23-9. Compare Result Output Action OMx OLx Action 0 0 No output compare action on the timer output signal 0 1 Toggle OCx output line 1 0 Clear OCx output line to zero 1 1 Set OCx output line to one MC9S12G Family Reference Manual Rev.1.28 748 NXP Semiconductors Timer Module (TIM16B8CV3) Note: To enable output action using the OM7 and OL7 bits on the timer port,the corresponding bit OC7M7 in the OC7M register must also be cleared. The settings for these bits can be seen inTable 23-10. Table 23-10. The OC7 and OCx event priority OC7M7=0 OC7M7=1 OC7Mx=1 TC7=TCx OC7Mx=0 TC7>TCx TC7=TCx IOCx=OC7Dx IOCx=OC7Dx IOC7=OM7/O +OMx/OLx L7 IOC7=OM7/O L7 OC7Mx=1 TC7>TCx TC7=TCx IOCx=OMx/OLx IOC7=OM7/OL7 OC7Mx=0 TC7>TCx IOCx=OC7Dx IOCx=OC7Dx IOC7=OC7D7 +OMx/OLx IOC7=OC7D7 TC7=TCx TC7>TCx IOCx=OMx/OLx IOC7=OC7D7 Note: in Table 23-10, the IOS7 and IOSx should be set to 1 IOSx is the register TIOS bit x, OC7Mx is the register OC7M bit x, TCx is timer Input Capture/Output Compare register, IOCx is channel x, OMx/OLx is the register TCTL1/TCTL2, OC7Dx is the register OC7D bit x. IOCx = OC7Dx+ OMx/OLx, means that both OC7 event and OCx event will change channel x value. 23.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4) Module Base + 0x000A R W Reset 7 6 5 4 3 2 1 0 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 0 0 0 0 0 0 0 0 Figure 23-16. Timer Control Register 3 (TCTL3) Module Base + 0x000B R W Reset 7 6 5 4 3 2 1 0 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A 0 0 0 0 0 0 0 0 Figure 23-17. Timer Control Register 4 (TCTL4) Read: Anytime MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 749 Timer Module (TIM16B8CV3) Write: Anytime. Table 23-11. TCTL3/TCTL4 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field 7:0 EDGnB EDGnA Description Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector circuits. Table 23-12. Edge Detector Circuit Configuration EDGnB EDGnA Configuration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge (rising or falling) 23.3.2.10 Timer Interrupt Enable Register (TIE) Module Base + 0x000C R W Reset 7 6 5 4 3 2 1 0 C7I C6I C5I C4I C3I C2I C1I C0I 0 0 0 0 0 0 0 0 Figure 23-18. Timer Interrupt Enable Register (TIE) Read: Anytime Write: Anytime. Table 23-13. TIE Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero Field Description 7:0 C7I:C0I Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled to cause a interrupt. MC9S12G Family Reference Manual Rev.1.28 750 NXP Semiconductors Timer Module (TIM16B8CV3) 23.3.2.11 Timer System Control Register 2 (TSCR2) Module Base + 0x000D 7 R W Reset TOI 0 6 5 4 0 0 0 0 0 0 3 2 1 0 TCRE PR2 PR1 PR0 0 0 0 0 = Unimplemented or Reserved Figure 23-19. Timer System Control Register 2 (TSCR2) Read: Anytime Write: Anytime. Table 23-14. TSCR2 Field Descriptions Field 7 TOI Description Timer Overflow Interrupt Enable 0 Interrupt inhibited. 1 Hardware interrupt requested when TOF flag set. 3 TCRE Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7 event. This mode of operation is similar to an up-counting modulus counter. 0 Counter reset inhibited and counter free runs. 1 Counter reset by a successful output compare 7. Note: If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1, TOF will never be set when TCNT is reset from 0xFFFF to 0x0000. Note: TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler counter width" + "1 Bus Clock", for a more detail explanation please refer to Section 23.4.3, “Output Compare Note: This bit and feature is available only when channel 7 exists. If channel 7 doesn’t exist, this bit is reserved. Writing to reserved bit has no effect. Read from reserved bit return a zero. 2:0 PR[2:0] Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the Bus Clock as shown in Table 23-15. Table 23-15. Timer Clock Selection PR2 PR1 PR0 Timer Clock 0 0 0 Bus Clock / 1 0 0 1 Bus Clock / 2 0 1 0 Bus Clock / 4 0 1 1 Bus Clock / 8 1 0 0 Bus Clock / 16 1 0 1 Bus Clock / 32 1 1 0 Bus Clock / 64 1 1 1 Bus Clock / 128 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 751 Timer Module (TIM16B8CV3) NOTE The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. 23.3.2.12 Main Timer Interrupt Flag 1 (TFLG1) Module Base + 0x000E R W Reset 7 6 5 4 3 2 1 0 C7F C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 0 Figure 23-20. Main Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit. Table 23-16. TRLG1 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description 7:0 C[7:0]F Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN or PAEN is set to one. Note: When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel (0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared. 23.3.2.13 Main Timer Interrupt Flag 2 (TFLG2) Module Base + 0x000F 7 R W Reset TOF 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 23-21. Main Timer Interrupt Flag 2 (TFLG2) TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit to one while TEN bit of TSCR1 or PAEN bit of PACTL is set to one. Read: Anytime Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared). MC9S12G Family Reference Manual Rev.1.28 752 NXP Semiconductors Timer Module (TIM16B8CV3) Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set. Table 23-17. TRLG2 Field Descriptions Field Description 7 TOF Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 or PAEN bit of PACTL is set to one (See also TCRE control bit explanation) . 23.3.2.14 Timer Input Capture/Output Compare Registers High and Low 0– 7(TCxH and TCxL) Module Base + 0x0010 = TC0H 0x0012 = TC1H 0x0014=TC2H 0x0016=TC3H R W 0x0018=TC4H 0x001A=TC5H 0x001C=TC6H 0x001E=TC7H 15 14 13 12 11 10 9 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Reset Figure 23-22. Timer Input Capture/Output Compare Register x High (TCxH) Module Base + 0x0011 = TC0L 0x0013 = TC1L 0x0015 =TC2L 0x0017=TC3L R W 0x0019 =TC4L 0x001B=TC5L 0x001D=TC6L 0x001F=TC7L 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Reset Figure 23-23. Timer Input Capture/Output Compare Register x Low (TCxL) 1 This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes. Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. Read: Anytime Write: Anytime for output compare function.Writes to these registers have no meaning or effect during input capture. All timer input capture/output compare registers are reset to 0x0000. NOTE Read/Write access in byte mode for high byte should take place before low byte otherwise it will give a different result. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 753 Timer Module (TIM16B8CV3) 23.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL) Module Base + 0x0020 7 R 0 W Reset 0 6 5 4 3 2 1 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 23-24. 16-Bit Pulse Accumulator Control Register (PACTL) Read: Any time Write: Any time When PAEN is set, the Pulse Accumulator counter is enabled. The Pulse Accumulator counter shares the input pin with IOC7. Table 23-18. PACTL Field Descriptions Field 6 PAEN Description Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse accumulator can function unless pulse accumulator is disabled. 0 16-Bit Pulse Accumulator system disabled. 1 Pulse Accumulator system enabled. 5 PAMOD Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See Table 23-19. 0 Event counter mode. 1 Gated time accumulation mode. 4 PEDGE Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). For PAMOD bit = 0 (event counter mode). See Table 23-19. 0 Falling edges on IOC7 pin cause the count to be increased. 1 Rising edges on IOC7 pin cause the count to be increased. For PAMOD bit = 1 (gated time accumulation mode). 0 IOC7 input pin high enables M (Bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling edge on IOC7 sets the PAIF flag. 1 IOC7 input pin low enables M (Bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge on IOC7 sets the PAIF flag. 3:2 CLK[1:0] Clock Select Bits — Refer to Table 23-20. 1 PAOVI 0 PAI Pulse Accumulator Overflow Interrupt Enable 0 Interrupt inhibited. 1 Interrupt requested if PAOVF is set. Pulse Accumulator Input Interrupt Enable 0 Interrupt inhibited. 1 Interrupt requested if PAIF is set. MC9S12G Family Reference Manual Rev.1.28 754 NXP Semiconductors Timer Module (TIM16B8CV3) Table 23-19. Pin Action PAMOD PEDGE Pin Action 0 0 Falling edge 0 1 Rising edge 1 0 Div. by 64 clock enabled with pin high level 1 1 Div. by 64 clock enabled with pin low level NOTE If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 because the 64 clock is generated by the timer prescaler. Table 23-20. Timer Clock Selection CLK1 CLK0 Timer Clock 0 0 Use timer prescaler clock as timer counter clock 0 1 Use PACLK as input to timer counter clock 1 0 Use PACLK/256 as timer counter clock frequency 1 1 Use PACLK/65536 as timer counter clock frequency For the description of PACLK please refer Figure 23-30. If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input clock to the timer counter. The change from one selected clock to the other happens immediately after these bits are written. 23.3.2.16 Pulse Accumulator Flag Register (PAFLG) 1 . Module Base + 0x0021 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 PAOVF PAIF 0 0 Unimplemented or Reserved Figure 23-25. Pulse Accumulator Flag Register (PAFLG) Read: Anytime Write: Anytime When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags in the PAFLG register. Timer module or Pulse Accumulator must stay enabled (TEN=1 or PAEN=1) while clearing these bits. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 755 Timer Module (TIM16B8CV3) Table 23-21. PAFLG Field Descriptions Field Description 1 PAOVF Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of PACTL register is set to one. 0 PAIF Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.In event mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at the IOC7 input pin triggers PAIF. Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of PACTL register is set to one. Any access to the PACNT register will clear all the flags in this register when TFFCA bit in register TSCR(0x0006) is set. 23.3.2.17 Pulse Accumulators Count Registers (PACNT) Module Base + 0x0022 R W Reset 15 14 13 12 11 10 9 0 PACNT15 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8 0 0 0 0 0 0 0 0 Figure 23-26. Pulse Accumulator Count Register High (PACNTH) 1 . Module Base + 0x0023 R W Reset 7 6 5 4 3 2 1 0 PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 0 0 0 0 0 0 0 0 Figure 23-27. Pulse Accumulator Count Register Low (PACNTL) Read: Anytime Write: Anytime These registers contain the number of active input edges on its input pin since the last reset. When PACNT overflows from 0xFFFF to 0x0000, the Interrupt flag PAOVF in PAFLG (0x0021) is set. Full count register access should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. NOTE Reading the pulse accumulator counter registers immediately after an active edge on the pulse accumulator input pin may miss the last count because the input has to be synchronized with the Bus clock first. MC9S12G Family Reference Manual Rev.1.28 756 NXP Semiconductors Timer Module (TIM16B8CV3) 23.3.2.18 Output Compare Pin Disconnect Register(OCPD) Module Base + 0x002C R W Reset 7 6 5 4 3 2 1 0 OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 0 0 0 0 0 0 0 0 Figure 23-28. Output Compare Pin Disconnect Register (OCPD) Read: Anytime Write: Anytime All bits reset to zero. Table 23-22. OCPD Field Description Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description 7:0 OCPD[7:0] Output Compare Pin Disconnect Bits 0 Enables the timer channel port. Output Compare action will occur on the channel pin. These bits do not affect the input capture or pulse accumulator functions. 1 Disables the timer channel port. Output Compare action will not occur on the channel pin, but the output compare flag still become set. 23.3.2.19 Precision Timer Prescaler Select Register (PTPSR) Module Base + 0x002E R W Reset 7 6 5 4 3 2 1 0 PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 0 0 0 0 0 0 0 0 Figure 23-29. Precision Timer Prescaler Select Register (PTPSR) Read: Anytime Write: Anytime All bits reset to zero. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 757 Timer Module (TIM16B8CV3) ... Table 23-23. PTPSR Field Descriptions Field Description 7:0 PTPS[7:0] Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1. Table 23-24 shows some selection examples in this case. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. The Prescaler can be calculated as follows depending on logical value of the PTPS[7:0] and PRNT bit: PRNT = 1 : Prescaler = PTPS[7:0] + 1 Table 23-24. Precision Timer Prescaler Selection Examples when PRNT = 1 PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Prescale Factor 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 3 0 0 0 0 0 0 1 1 4 - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 1 0 0 1 1 20 0 0 0 1 0 1 0 0 21 0 0 0 1 0 1 0 1 22 - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 0 253 1 1 1 1 1 1 0 1 254 1 1 1 1 1 1 1 0 255 1 1 1 1 1 1 1 1 256 23.4 Functional Description This section provides a complete functional description of the timer TIM16B8CV3 block. Please refer to the detailed timer block diagram in Figure 23-30 as necessary. MC9S12G Family Reference Manual Rev.1.28 758 NXP Semiconductors Timer Module (TIM16B8CV3) PTPSR[7:0] PRE-PRESCALER MUX PRNT tim source Clock CLK[1:0] PACLK PACLK/256 PACLK/65536 PR[2:1:0] channel 7 output compare 1 MUX 0 PRESCALER TCRE CxI TCNT(hi):TCNT(lo) CxF CLEAR COUNTER 16-BIT COUNTER TOF INTERRUPT LOGIC TOI TE TOF CHANNEL 0 16-BIT COMPARATOR C0F C0F OM:OL0 TC0 EDG0A TOV0 EDGE DETECT EDG0B CH. 0 CAPTURE IOC0 PIN LOGIC CH. 0COMPARE IOC0 PIN IOC0 CHANNEL 1 16-BIT COMPARATOR C1F C1F OM:OL1 TC1 EDG1A EDGE DETECT EDG1B CH. 1 CAPTURE IOC1 PIN LOGIC CH. 1 COMPARE TOV1 IOC1 PIN IOC1 CHANNEL2 CHANNEL7 16-BIT COMPARATOR C7F C7F TC7 OM:OL7 EDG7A EDG7B PAOVF TOV7 EDGE DETECT IOC7 PACNT(hi):PACNT(lo) PACLK/65536 CH.7 CAPTURE IOC7 PIN PA INPUT LOGIC CH. 7 COMPARE IOC7 PIN PEDGE MUX 16-BIT COUNTER PAEN EDGE DETECT PACLK PACLK/256 INTERRUPT REQUEST PAMOD INTERRUPT LOGIC PEDGE PAOVI PAI PAOVF PAIF TEN PAIF DIVIDE-BY-64 tim source clock PAOVF PAOVI Maximum possible channels, scalable from 0 to 7. Pulse Accumulator is available only if channel 7 exists. Figure 23-30. Detailed Timer Block Diagram MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 759 Timer Module (TIM16B8CV3) 23.4.1 Prescaler The prescaler divides the Bus clock by 1, 2, 4, 8, 16, 32, 64 or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2). The prescaler divides the Bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system control register 2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32, 64 and 128 when the PRNT bit in TSCR1 is disabled. By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this case, it is possible to set additional prescaler settings for the main timer counter in the present timer by using PTPSR[7:0] bits of PTPSR register generating divide by 1, 2, 3, 4,....20, 21, 22, 23,......255, or 256. 23.4.2 Input Capture Clearing the I/O (input/output) select bit, IOSx, configures channel x as an input capture channel. The input capture function captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel registers, TCx. The minimum pulse width for the input capture input is greater than two Bus clocks. An input capture on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests. Timer module or Pulse Accumulator must stay enabled (TEN bit of TSCR1 or PAEN bit of PACTL register must be set to one) while clearing CxF (writing one to CxF). 23.4.3 Output Compare Setting the I/O select bit, IOSx, configures channel x when available as an output compare channel. The output compare function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the timer counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin if the corresponding OCPDx bit is set to zero. An output compare on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests. Timer module or Pulse Accumulator must stay enabled (TEN bit of TSCR1 or PAEN bit of PACTL register must be set to one) while clearing CxF (writing one to CxF). The output mode and level bits, OMx and OLx, select set, clear, toggle on output compare. Clearing both OMx and OLx results in no output compare action on the output compare channel pin. Setting a force output compare bit, FOCx, causes an output compare on channel x. A forced output compare does not set the channel flag. A channel 7 event, which can be a counter overflow when TTOV[7] is set or a successful output compare on channel 7, overrides output compares on all other output compare channels. The output compare 7 mask register masks the bits in the output compare 7 data register. The timer counter reset enable bit, TCRE, enables channel 7 output compares to reset the timer counter. A channel 7 output compare can reset the timer counter even if the IOC7 pin is being used as the pulse accumulator input. MC9S12G Family Reference Manual Rev.1.28 760 NXP Semiconductors Timer Module (TIM16B8CV3) Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin. When TCRE is set and TC7 is not equal to 0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it will last only one Bus cycle then reset to 0. Note: in Figure 23-31,if PR[2:0] is equal to 0, one prescaler counter equal to one Bus clock Figure 23-31. The TCNT cycle diagram under TCRE=1 condition prescaler counter TC7 0 1 Bus clock 1 TC7-1 TC7 0 TC7 event TC7 event 23.4.3.1 ----- OC Channel Initialization The internal register whose output drives OCx can be programmed before the timer drives OCx. The desired state can be programmed to this internal register by writing a one to CFORCx bit with TIOSx, OCPDx and TEN bits set to one. Set OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=1 and OCPDx=1 Clear OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=0 and OCPDx=1 Setting OCPDx to zero allows the internal register to drive the programmed state to OCx. This allows a glitch free switch over of port from general purpose I/O to timer output once the OCPDx bit is set to zero. 23.4.4 Pulse Accumulator The pulse accumulator (PACNT) is a 16-bit counter that can operate in two modes: Event counter mode — Counting edges of selected polarity on the pulse accumulator input pin, PAI. Gated time accumulation mode — Counting pulses from a divide-by-64 clock. The PAMOD bit selects the mode of operation. The minimum pulse width for the PAI input is greater than two Bus clocks. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 761 Timer Module (TIM16B8CV3) 23.4.5 Event Counter Mode Clearing the PAMOD bit configures the PACNT for event counter operation. An active edge on the IOC7 pin increments the pulse accumulator counter. The PEDGE bit selects falling edges or rising edges to increment the count. NOTE The PACNT input and timer channel 7 use the same pin IOC7. To use the IOC7, disconnect it from the output logic by clearing the channel 7 output mode and output level bits, OM7 and OL7. Also clear the channel 7 output compare 7 mask bit, OC7M7. The Pulse Accumulator counter register reflect the number of active input edges on the PACNT input pin since the last reset. The PAOVF bit is set when the accumulator rolls over from 0xFFFF to 0x0000. The pulse accumulator overflow interrupt enable bit, PAOVI, enables the PAOVF flag to generate interrupt requests. NOTE The pulse accumulator counter can operate in event counter mode even when the timer enable bit, TEN, is clear. 23.4.6 Gated Time Accumulation Mode Setting the PAMOD bit configures the pulse accumulator for gated time accumulation operation. An active level on the PACNT input pin enables a divided-by-64 clock to drive the pulse accumulator. The PEDGE bit selects low levels or high levels to enable the divided-by-64 clock. The trailing edge of the active level at the IOC7 pin sets the PAIF. The PAI bit enables the PAIF flag to generate interrupt requests. The pulse accumulator counter register reflect the number of pulses from the divided-by-64 clock since the last reset. NOTE The timer prescaler generates the divided-by-64 clock. If the timer is not active, there is no divided-by-64 clock. 23.5 Resets The reset state of each individual bit is listed within Section 23.3, “Memory Map and Register Definition” which details the registers and their bit fields 23.6 Interrupts This section describes interrupts originated by the TIM16B8CV3 block. Table 23-25 lists the interrupts generated by the TIM16B8CV3 to communicate with the MCU. MC9S12G Family Reference Manual Rev.1.28 762 NXP Semiconductors Timer Module (TIM16B8CV3) Table 23-25. TIM16B8CV3 Interrupts Interrupt Offset Vector Priority Source Description C[7:0]F — — — Timer Channel 7–0 Active high timer channel interrupts 7–0 PAOVI — — — Pulse Accumulator Input Active high pulse accumulator input interrupt PAOVF — — — Pulse Accumulator Overflow Pulse accumulator overflow interrupt TOF — — — Timer Overflow Timer Overflow interrupt The TIM16B8CV3 could use up to 11 interrupt vectors. The interrupt vector offsets and interrupt numbers are chip dependent. 23.6.1 Channel [7:0] Interrupt (C[7:0]F) This active high outputs will be asserted by the module to request a timer channel 7 – 0 interrupt. The TIM block only generates the interrupt and does not service it. Only bits related to implemented channels are valid. 23.6.2 Pulse Accumulator Input Interrupt (PAOVI) This active high output will be asserted by the module to request a timer pulse accumulator input interrupt. The TIM block only generates the interrupt and does not service it. 23.6.3 Pulse Accumulator Overflow Interrupt (PAOVF) This active high output will be asserted by the module to request a timer pulse accumulator overflow interrupt. The TIM block only generates the interrupt and does not service it. 23.6.4 Timer Overflow Interrupt (TOF) This active high output will be asserted by the module to request a timer overflow interrupt. The TIM block only generates the interrupt and does not service it. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 763 Timer Module (TIM16B8CV3) MC9S12G Family Reference Manual Rev.1.28 764 NXP Semiconductors Chapter 24 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-1. Revision History Revision Number Revision Date V01.04 Sections Affected Description of Changes 17 Jun 2010 24.4.6.1/24-795 24.4.6.2/24-796 24.4.6.3/24-796 24.4.6.14/24-806 Clarify Erase Verify Commands Descriptions related to the bits MGSTAT[1:0] of the register FSTAT. V01.05 20 Aug 2010 24.4.6.2/24-796 24.4.6.12/24-803 24.4.6.13/24-805 Updated description of the commands RD1BLK, MLOADU and MLOADF V01.06 31 Jan 2011 24.3.2.9/24-781 Updated description of protection on Section 24.3.2.9 24.1 Introduction The FTMRG16K1 module implements the following: • 16Kbytes of P-Flash (Program Flash) memory • 512 bytes of EEPROM memory The Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory contents. The user interface to the memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is written to with the command, global address, data, and any required command parameters. The memory controller must complete the execution of a command before the FCCOB register can be written to with a new command. CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 765 It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory. Simultaneous P-Flash and EEPROM operations are discussed in Section 24.4.5. Both P-Flash and EEPROM memories are implemented with Error Correction Codes (ECC) that can resolve single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read by half-phrase, only one single bit fault in an aligned 4 byte half-phrase containing the byte or word accessed will be corrected. 24.1.1 Glossary Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. EEPROM Memory — The EEPROM memory constitutes the nonvolatile memory store for data. EEPROM Sector — The EEPROM sector is the smallest portion of the EEPROM memory that can be erased. The EEPROM sector consists of 4 bytes. NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters required for Flash command execution. Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double bit fault detection within each double word. P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications. P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased. Each P-Flash sector contains 512 bytes. Program IFR — Nonvolatile information register located in the P-Flash block that contains the Version ID, and the Program Once field. 24.1.2 24.1.2.1 • • • Features P-Flash Features 16 Kbytes of P-Flash memory composed of one 16 Kbyte Flash block divided into 32 sectors of 512 bytes Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 766 16 KByte Flash Module (S12FTMRG16K1V1) • • • Fast sector erase and phrase program operation Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 24.1.2.2 • • • • • • 512 bytes of EEPROM memory composed of one 512 byte Flash block divided into 128 sectors of 4 bytes Single bit fault correction and double bit fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Protection scheme to prevent accidental program or erase of EEPROM memory Ability to program up to four words in a burst sequence 24.1.2.3 • • • EEPROM Features Other Flash Module Features No external high-voltage power supply required for Flash memory program and erase operations Interrupt generation on Flash command completion and Flash error detection Security mechanism to prevent unauthorized access to the Flash memory 24.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 24-1. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 767 16 KByte Flash Module (S12FTMRG16K1V1) Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 4Kx39 sector 0 sector 1 Protection sector 31 Security Bus Clock Clock Divider FCLK Memory Controller CPU EEPROM 256x22 sector 0 sector 1 sector 127 Figure 24-1. FTMRG16K1 Block Diagram 24.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual Rev.1.28 768 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) 24.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed. If such action is attempted the write operation will not change the register value. Writing to the Flash registers is allowed when the Flash is not busy executing commands (CCIF = 1) and during initialization right after reset, despite the value of flag CCIF in that case (refer to Section 24.6 for a complete description of the reset sequence). . Table 24-2. FTMRG Memory Map Global Address (in Bytes) 0x0_0000 - 0x0_03FF 1 Size (Bytes) 1,024 Description Register Space 0x0_0400 – 0x0_05FF 512 EEPROM Memory 0x0_0600 – 0x0_07FF 512 FTMRG reserved area 0x0_4000 – 0x0_7FFF 16,284 NVMRES1=1 : NVM Resource area (see Figure 24-3) 0x3_8000 – 0x3_BFFF 16,384 FTMRG reserved area 0x3_C000 – 0x3_FFFF 16,384 P-Flash Memory See NVMRES description in Section 24.4.3 24.3.1 Module Memory Map The S12 architecture places the P-Flash memory between global addresses 0x3_C000 and 0x3_FFFF as shown in Table 24-3.The P-Flash memory map is shown in Figure 24-2. Table 24-3. P-Flash Memory Addressing Global Address Size (Bytes) 0x3_C000 – 0x3_FFFF 16 K Description P-Flash Block Contains Flash Configuration Field (see Table 24-4) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 769 16 KByte Flash Module (S12FTMRG16K1V1) The FPROT register, described in Section 24.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. Two separate memory regions, one growing downward from global address 0x3_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection. The Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 24-4. Table 24-4. Flash Configuration Field 1 Global Address Size (Bytes) 0x3_FF00-0x3_FF07 8 Backdoor Comparison Key Refer to Section 24.4.6.11, “Verify Backdoor Access Key Command,” and Section 24.5.1, “Unsecuring the MCU using Backdoor Key Access” 0x3_FF08-0x3_FF0B1 4 Reserved 0x3_FF0C1 1 P-Flash Protection byte. Refer to Section 24.3.2.9, “P-Flash Protection Register (FPROT)” 0x3_FF0D1 1 EEPROM Protection byte. Refer to Section 24.3.2.10, “EEPROM Protection Register (EEPROT)” 0x3_FF0E1 1 Flash Nonvolatile byte Refer to Section 24.3.2.16, “Flash Option Register (FOPT)” 0x3_FF0F1 1 Flash Security byte Refer to Section 24.3.2.2, “Flash Security Register (FSEC)” Description 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B reserved field should be programmed to 0xFF. P-Flash START = 0x3_C000 Protection Movable End 0x3_E000 Protection Fixed End Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 P-Flash END = 0x3_FFFF Flash Configuration Field 16 bytes (0x3_FF00 - 0x3_FF0F) Figure 24-2. P-Flash Memory Map MC9S12G Family Reference Manual Rev.1.28 770 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-5. Program IFR Fields 1 Global Address Size (Bytes) 0x0_4000 – 0x0_4007 8 Reserved 0x0_4008 – 0x0_40B5 174 Reserved 0x0_40B6 – 0x0_40B7 2 Version ID1 0x0_40B8 – 0x0_40BF 8 Reserved 0x0_40C0 – 0x0_40FF 64 Program Once Field Refer to Section 24.4.6.6, “Program Once Command” Field Description Used to track firmware patch versions, see Section 24.4.2 Table 24-6. Memory Controller Resource Fields (NVMRES1=1) Global Address Size (Bytes) 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 24-5) 0x0_4100 – 0x0_41FF 256 Reserved. 0x0_4200 – 0x0_57FF 1 Description Reserved 0x0_5800 – 0x0_59FF 512 Reserved 0x0_5A00 – 0x0_5FFF 1,536 Reserved 0x0_6000 – 0x0_6BFF 3,072 Reserved 0x0_6C00 – 0x0_7FFF 5,120 Reserved NVMRES - See Section 24.4.3 for NVMRES (NVM Resource) detail. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 771 16 KByte Flash Module (S12FTMRG16K1V1) 0x0_4000 P-Flash IFR 1 Kbyte (NVMRES=1) 0x0_4400 Reserved 5k bytes RAM Start = 0x0_5800 RAM End = 0x0_59FF Reserved 512 bytes Reserved 4608 bytes 0x0_6C00 Reserved 5120 bytes 0x0_7FFF Figure 24-3. Memory Controller Resource Memory Map (NVMRES=1) 24.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 24.3). A summary of the Flash module registers is given in Figure 24-4 with detailed descriptions in the following subsections. Address & Name 0x0000 FCLKDIV 0x0001 FSEC 0x0002 FCCOBIX 7 R 6 5 4 3 2 1 0 FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0 FDIVLD W R W R W Figure 24-4. FTMRG16K1 Register Summary MC9S12G Family Reference Manual Rev.1.28 772 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) Address & Name 0x0003 FRSV0 0x0004 FCNFG 0x0005 FERCNFG 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 EEPROT 0x000A FCCOBHI 0x000B FCCOBLO 0x000C FRSV1 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 FDFD FSFD 0 0 0 0 0 DFDIE SFDIE ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0 0 0 0 0 DFDIF SFDIF FPHDIS FPHS1 FPHS0 RNV2 RNV1 RNV0 DPS4 DPS3 DPS2 DPS1 DPS0 W R W R CCIE 0 IGNSF W R W R 0 CCIF 0 0 W R W R W R W R W R FPOPEN RNV6 0 0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 DPOPEN W R W R W R W R W Figure 24-4. FTMRG16K1 Register Summary (continued) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 773 16 KByte Flash Module (S12FTMRG16K1V1) Address & Name 0x0011 FRSV5 0x0012 FRSV6 0x0013 FRSV7 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W = Unimplemented or Reserved Figure 24-4. FTMRG16K1 Register Summary (continued) 24.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Offset Module Base + 0x0000 7 R 6 FDIVLD W Reset 0 5 4 3 FDIVLCK 0 2 1 0 0 0 0 FDIV[5:0] 0 0 0 = Unimplemented or Reserved Figure 24-5. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). Table 24-7. FCLKDIV Field Descriptions Field 7 FDIVLD Description Clock Divider Loaded 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset MC9S12G Family Reference Manual Rev.1.28 774 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-7. FCLKDIV Field Descriptions (continued) Field Description 6 FDIVLCK Clock Divider Locked 0 FDIV field is open for writing 1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in normal mode. 5–0 FDIV[5:0] Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events during Flash program and erase algorithms. Table 24-8 shows recommended values for FDIV[5:0] based on the BUSCLK frequency. Please refer to Section 24.4.4, “Flash Command Operations,” for more information. Table 24-8. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) 1 2 24.3.2.2 MIN1 MAX2 1.0 1.6 1.6 FDIV[5:0] BUSCLK Frequency (MHz) FDIV[5:0] MIN1 MAX2 0x00 16.6 17.6 0x10 2.6 0x01 17.6 18.6 0x11 2.6 3.6 0x02 18.6 19.6 0x12 3.6 4.6 0x03 19.6 20.6 0x13 4.6 5.6 0x04 20.6 21.6 0x14 5.6 6.6 0x05 21.6 22.6 0x15 6.6 7.6 0x06 22.6 23.6 0x16 7.6 8.6 0x07 23.6 24.6 0x17 8.6 9.6 0x08 24.6 25.6 0x18 9.6 10.6 0x09 10.6 11.6 0x0A 11.6 12.6 0x0B 12.6 13.6 0x0C 13.6 14.6 0x0D 14.6 15.6 0x0E 15.6 16.6 0x0F BUSCLK is Greater Than this value. BUSCLK is Less Than or Equal to this value. Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 775 16 KByte Flash Module (S12FTMRG16K1V1) Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 24-6. Flash Security Register (FSEC) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FSEC register are readable but not writable. During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the Flash configuration field at global address 0x3_FF0F located in P-Flash memory (see Table 24-4) as indicated by reset condition F in Figure 24-6. If a double bit fault is detected while reading the P-Flash phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set to leave the Flash module in a secured state with backdoor key access disabled. Table 24-9. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the KEYEN[1:0] Flash module as shown in Table 24-10. 5–2 RNV[5:2] Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements. 1–0 SEC[1:0] Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 24-11. If the Flash module is unsecured using backdoor key access, the SEC bits are forced to 10. Table 24-10. Flash KEYEN States 1 KEYEN[1:0] Status of Backdoor Key Access 00 DISABLED 01 DISABLED1 10 ENABLED 11 DISABLED Preferred KEYEN state to disable backdoor key access. Table 24-11. Flash Security States 1 SEC[1:0] Status of Security 00 SECURED 01 SECURED1 10 UNSECURED 11 SECURED Preferred SEC state to set MCU to secured state. MC9S12G Family Reference Manual Rev.1.28 776 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) The security function in the Flash module is described in Section 24.5. 24.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations. Offset Module Base + 0x0002 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 CCOBIX[2:0] W Reset 1 0 0 0 = Unimplemented or Reserved Figure 24-7. FCCOB Index Register (FCCOBIX) CCOBIX bits are readable and writable while remaining bits read 0 and are not writable. Table 24-12. FCCOBIX Field Descriptions Field Description 2–0 CCOBIX[1:0] Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to. See 24.3.2.11 Flash Common Command Object Register (FCCOB),” for more details. 24.3.2.4 Flash Reserved0 Register (FRSV0) This Flash register is reserved for factory testing. Offset Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 24-8. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. 24.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 777 16 KByte Flash Module (S12FTMRG16K1V1) Offset Module Base + 0x0004 7 R W Reset CCIE 0 6 5 0 0 0 0 4 IGNSF 0 3 2 0 0 0 0 1 0 FDFD FSFD 0 0 = Unimplemented or Reserved Figure 24-9. Flash Configuration Register (FCNFG) CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not writable. Table 24-13. FCNFG Field Descriptions Field Description 7 CCIE Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command has completed. 0 Command complete interrupt disabled 1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 24.3.2.7) 4 IGNSF Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see Section 24.3.2.8). 0 All single bit faults detected during array reads are reported 1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated 1 FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. 0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected 1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see Section 24.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG register is set (see Section 24.3.2.6) 0 FSFD Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. 0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected 1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 24.3.2.7) and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see Section 24.3.2.6) 24.3.2.6 Flash Error Configuration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. MC9S12G Family Reference Manual Rev.1.28 778 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) Offset Module Base + 0x0005 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDIE SFDIE 0 0 = Unimplemented or Reserved Figure 24-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. Table 24-14. FERCNFG Field Descriptions Field Description 1 DFDIE Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation. 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set (see Section 24.3.2.8) 0 SFDIE Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault is detected during a Flash block read operation. 0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 24.3.2.8) 1 An interrupt will be requested whenever the SFDIF flag is set (see Section 24.3.2.8) 24.3.2.7 Flash Status Register (FSTAT) The FSTAT register reports the operational status of the Flash module. Offset Module Base + 0x0006 7 R W Reset CCIF 1 6 0 0 5 4 ACCERR FPVIOL 0 0 3 2 MGBUSY RSVD 0 0 1 0 MGSTAT[1:0] 01 01 = Unimplemented or Reserved Figure 24-11. Flash Status Register (FSTAT) 1 Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 24.6). CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 779 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation. 0 Flash command in progress 1 Flash command has completed 5 ACCERR Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory caused by either a violation of the command write sequence (see Section 24.4.4.2) or issuing an illegal Flash command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR. 0 No access error detected 1 Access error detected 4 FPVIOL Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of P-Flash or EEPROM memory during a command write sequence. The FPVIOL bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected 1 Protection violation detected 3 MGBUSY 2 RSVD Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller. 0 Memory Controller is idle 1 Memory Controller is busy executing a Flash command (CCIF = 0) Reserved Bit — This bit is reserved and always reads 0. 1–0 Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See Section 24.4.6, “Flash Command Description,” and Section 24.6, “Initialization” for details. 24.3.2.8 Flash Error Status Register (FERSTAT) The FERSTAT register reflects the error status of internal Flash operations. Offset Module Base + 0x0007 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDIF SFDIF 0 0 = Unimplemented or Reserved Figure 24-12. Flash Error Status Register (FERSTAT) All flags in the FERSTAT register are readable and only writable to clear the flag. MC9S12G Family Reference Manual Rev.1.28 780 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The DFDIF flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.2 0 No double bit fault detected 1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command running 0 SFDIF Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF. 0 No single bit fault detected 1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted while command running 1 The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either single fault or double fault but never both). A simultaneous access collision (Flash array read operation returning invalid data attempted while command running) is indicated when both SFDIF and DFDIF flags are high. 2 There is a one cycle delay in storing the ECC DFDIF and SFDIF fault flags in this register. At least one NOP is required after a flash memory read before checking FERSTAT for the occurrence of ECC errors. 24.3.2.9 P-Flash Protection Register (FPROT) The FPROT register defines which P-Flash sectors are protected against program and erase operations. Offset Module Base + 0x0008 7 R W Reset FPOPEN F1 6 5 RNV6 F1 4 FPHDIS F1 3 2 FPHS[1:0] F1 1 0 RNV[2:0] F1 F1 F1 F1 = Unimplemented or Reserved Figure 24-13. Flash Protection Register (FPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected region can only be increased. While the RNV[2:0] bits are writable, they should be left in an erased state. During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte in the Flash configuration field at global address 0x3_FF0C located in P-Flash memory (see Table 24-4) as indicated by reset condition ‘F’ in Figure 24-13. To change the P-Flash protection that will be loaded during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 781 16 KByte Flash Module (S12FTMRG16K1V1) Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. Table 24-17. FPROT Field Descriptions Field Description 7 FPOPEN Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or erase operations as shown in Table 24-18 for the P-Flash block. 0 When FPOPEN is clear, the FPHDIS bit defines an unprotected address range as specified by the FPHS bits 1 When FPOPEN is set, the FPHDIS bit enables protection for the address range specified by the FPHS bits 6 RNV[6] Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements. 5 FPHDIS Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory ending with global address 0x3_FFFF. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 4–3 FPHS[1:0] Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area in P-Flash memory as shown inTable 24-19. The FPHS bits can only be written to while the FPHDIS bit is set. 2–0 RNV[2:0] Reserved Nonvolatile Bits — These RNV bits should remain in the erased state. Table 24-18. P-Flash Protection Function 1 Function1 FPOPEN FPHDIS 1 1 No P-Flash Protection 1 0 Protected High Range 0 1 Full P-Flash Memory Protected 0 0 Unprotected High Range For range sizes, refer to Table 24-19. Table 24-19. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 00 0x3_F800–0x3_FFFF 2 Kbytes 01 0x3_F000–0x3_FFFF 4 Kbytes 10 0x3_E000–0x3_FFFF 8 Kbytes 11 0x3_C000–0x3_FFFF 16 Kbytes Although the protection scheme is loaded from the Flash memory at global address 0x3_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12G Family Reference Manual Rev.1.28 782 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) 24.3.2.10 EEPROM Protection Register (EEPROT) The EEPROT register defines which EEPROM sectors are protected against program and erase operations. Offset Module Base + 0x0009 7 R W Reset DPOPEN F1 6 5 0 0 0 0 4 3 2 1 0 F1 F1 DPS[4:0] F1 F1 F1 = Unimplemented or Reserved Figure 24-14. EEPROM Protection Register (EEPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the EEPROT register are writable with the restriction that protection can be added but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1 (protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is irrelevant. During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in P-Flash memory (see Table 24-4) as indicated by reset condition F in Table 24-21. To change the EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase containing the EEPROM protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the EEPROM memory fully protected. Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. Block erase of the EEPROM memory is not possible if any of the EEPROM sectors are protected. Table 24-20. EEPROT Field Descriptions Field Description 7 DPOPEN EEPROM Protection Control 0 Enables EEPROM memory protection from program and erase with protected address range defined by DPS bits 1 Disables EEPROM memory protection from program and erase 4–0 DPS[4:0] EEPROM Protection Size — The DPS[4:0] bits determine the size of the protected area in the EEPROM memory as shown inTable 24-21 . MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 783 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-21. EEPROM Protection Address Range DPS[4:0] Global Address Range Protected Size 00000 0x0_0400 – 0x0_041F 32 bytes 00001 0x0_0400 – 0x0_043F 64 bytes 00010 0x0_0400 – 0x0_045F 96 bytes 00011 0x0_0400 – 0x0_047F 128 bytes 00100 0x0_0400 – 0x0_049F 160 bytes 00101 0x0_0400 – 0x0_04BF 192 bytes The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increasing of one. . . . 01111 - to - 11111 0x0_0400 – 0x0_05FF 512 bytes 24.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. Offset Module Base + 0x000A 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[15:8] W Reset 3 0 0 0 0 Figure 24-15. Flash Common Command Object High Register (FCCOBHI) Offset Module Base + 0x000B 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[7:0] W Reset 3 0 0 0 0 Figure 24-16. Flash Common Command Object Low Register (FCCOBLO) 24.3.2.11.1 FCCOB - NVM Command Mode NVM command mode uses the indexed FCCOB register to provide a command code and its relevant parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates MC9S12G Family Reference Manual Rev.1.28 784 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes (as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array. The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 24-22. The return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller. Writes to the unimplemented parameter fields (CCOBIX = 110 and CCOBIX = 111) are ignored with reads from these fields returning 0x0000. Table 24-22 shows the generic Flash command format. The high byte of the first word in the CCOB array contains the command code, followed by the parameters for this specific Flash command. For details on the FCCOB settings required by each command, see the Flash command descriptions in Section 24.4.6. Table 24-22. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] 000 001 010 011 100 101 Byte FCCOB Parameter Fields (NVM Command Mode) HI FCMD[7:0] defining Flash command LO 6’h0, Global address [17:16] HI Global address [15:8] LO Global address [7:0] HI Data 0 [15:8] LO Data 0 [7:0] HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 24.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing. Offset Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 24-17. Flash Reserved1 Register (FRSV1) All bits in the FRSV1 register read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 785 16 KByte Flash Module (S12FTMRG16K1V1) 24.3.2.13 Flash Reserved2 Register (FRSV2) This Flash register is reserved for factory testing. Offset Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 24-18. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. 24.3.2.14 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. Offset Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 24-19. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 24.3.2.15 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing. Offset Module Base + 0x000F R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 24-20. Flash Reserved4 Register (FRSV4) All bits in the FRSV4 register read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.28 786 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) 24.3.2.16 Flash Option Register (FOPT) The FOPT register is the Flash option register. Offset Module Base + 0x0010 7 6 5 4 R 3 2 1 0 F1 F1 F1 F1 NV[7:0] W Reset F1 F1 F1 F1 = Unimplemented or Reserved Figure 24-21. Flash Option Register (FOPT) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FOPT register are readable but are not writable. During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global address 0x3_FF0E located in P-Flash memory (see Table 24-4) as indicated by reset condition F in Figure 24-21. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. Table 24-23. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits. 24.3.2.17 Flash Reserved5 Register (FRSV5) This Flash register is reserved for factory testing. Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 24-22. Flash Reserved5 Register (FRSV5) All bits in the FRSV5 register read 0 and are not writable. 24.3.2.18 Flash Reserved6 Register (FRSV6) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 787 16 KByte Flash Module (S12FTMRG16K1V1) Offset Module Base + 0x0012 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 24-23. Flash Reserved6 Register (FRSV6) All bits in the FRSV6 register read 0 and are not writable. 24.3.2.19 Flash Reserved7 Register (FRSV7) This Flash register is reserved for factory testing. Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 24-24. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.28 788 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) 24.4 Functional Description 24.4.1 Modes of Operation The FTMRG16K1 module provides the modes of operation normal and special . The operating mode is determined by module-level inputs and affects the FCLKDIV, FCNFG, and EEPROT registers (see Table 24-25). 24.4.2 IFR Version ID Word The version ID word is stored in the IFR at address 0x0_40B6. The contents of the word are defined in Table 24-24. Table 24-24. IFR Version ID Fields • [15:4] [3:0] Reserved VERNUM VERNUM: Version number. The first version is number 0b_0001 with both 0b_0000 and 0b_1111 meaning ‘none’. 24.4.3 Internal NVM resource (NVMRES) IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown in Table 24-5. The NVMRES global address map is shown in Table 24-6. 24.4.4 Flash Command Operations Flash command operations are used to modify Flash memory contents. The next sections describe: • How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from BUSCLK for Flash program and erase command operations • The command write sequence used to set Flash command parameters and launch execution • Valid Flash commands available for execution, according to MCU functional mode and MCU security state. 24.4.4.1 Writing the FCLKDIV Register Prior to issuing any Flash program or erase command after a reset, the user is required to write the FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz. Table 24-8 shows recommended values for the FDIV field based on BUSCLK frequency. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 789 16 KByte Flash Module (S12FTMRG16K1V1) NOTE Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash memory due to overstress. Setting FDIV too low can result in incomplete programming or erasure of the Flash memory cells. When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written, any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set. 24.4.4.2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see Section 24.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence. If CCIF is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the FCCOB register are ignored. 24.4.4.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 24.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag will remain clear until the Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 24-25. MC9S12G Family Reference Manual Rev.1.28 790 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no yes FCCOB Availability Check CCIF Set? Read: FSTAT register yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load. Write to FCCOB register to load required command parameter. More Parameters? yes no Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 24-25. Generic Flash Command Write Sequence Flowchart MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 791 16 KByte Flash Module (S12FTMRG16K1V1) 24.4.4.3 Valid Flash Module Commands Table 24-25 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 24-25. Flash Commands by Mode and Security State Unsecured FCMD Command Secured NS1 SS2 NS3 SS4 0x01 Erase Verify All Blocks     0x02 Erase Verify Block     0x03 Erase Verify P-Flash Section    0x04 Read Once    0x06 Program P-Flash    0x07 Program Once    0x08 Erase All Blocks 0x09 Erase Flash Block    0x0A Erase P-Flash Sector    0x0B Unsecure Flash 0x0C Verify Backdoor Access Key  0x0D Set User Margin Level  0x0E Set Field Margin Level 0x10 Erase Verify EEPROM Section    0x11 Program EEPROM    0x12 Erase EEPROM Sector            1 Unsecured Normal Single Chip mode Unsecured Special Single Chip mode. 3 Secured Normal Single Chip mode. 4 Secured Special Single Chip mode. 2 24.4.4.4 P-Flash Commands Table 24-26 summarizes the valid P-Flash commands along with the effects of the commands on the P-Flash block and other resources within the Flash module. Table 24-26. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks Function on P-Flash Memory Verify that all P-Flash (and EEPROM) blocks are erased. MC9S12G Family Reference Manual Rev.1.28 792 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-26. P-Flash Commands FCMD Command 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a P-Flash (or EEPROM) block. An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. 0x0A Erase P-Flash Sector 0x0B Unsecure Flash 0x0C Verify Backdoor Access Key Supports a method of releasing MCU security by verifying a set of security keys. 0x0D Set User Margin Level Specifies a user margin read level for all P-Flash blocks. 0x0E Set Field Margin Level Specifies a field margin read level for all P-Flash blocks (special modes only). 24.4.4.5 Function on P-Flash Memory Verify that a P-Flash block is erased. Verify that a given number of words starting at the address provided are erased. Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block that was previously programmed using the Program Once command. Program a phrase in a P-Flash block. Erase all bytes in a P-Flash sector. Supports a method of releasing MCU security by erasing all P-Flash (and EEPROM) blocks and verifying that all P-Flash (and EEPROM) blocks are erased. EEPROM Commands Table 24-27 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. Table 24-27. EEPROM Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block Function on EEPROM Memory Verify that all EEPROM (and P-Flash) blocks are erased. Verify that the EEPROM block is erased. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 793 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-27. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block. An erase of the full EEPROM block is only possible when DPOPEN bit in the EEPROT register is set prior to launching the command. 0x0B Unsecure Flash 0x0D Set User Margin Level Specifies a user margin read level for the EEPROM block. 0x0E Set Field Margin Level Specifies a field margin read level for the EEPROM block (special modes only). 0x10 Erase Verify EEPROM Section Verify that a given number of words starting at the address provided are erased. 0x11 Program EEPROM Program up to four words in the EEPROM block. 0x12 Erase EEPROM Sector Erase all bytes in a sector of the EEPROM block. 24.4.5 Supports a method of releasing MCU security by erasing all EEPROM (and P-Flash) blocks and verifying that all EEPROM (and P-Flash) blocks are erased. Allowed Simultaneous P-Flash and EEPROM Operations Only the operations marked ‘OK’ in Table 24-28 are permitted to be run simultaneously on the Program Flash and EEPROM blocks. Some operations cannot be executed simultaneously because certain hardware resources are shared by the two memories. The priority has been placed on permitting Program Flash reads while program and erase operations execute on the EEPROM, providing read (P-Flash) while write (EEPROM) functionality. Table 24-28. Allowed P-Flash and EEPROM Simultaneous Operations EEPROM Program Flash Read Read Margin Read1 Program Sector Erase OK OK OK Mass Erase2 Margin Read1 Program Sector Erase Mass Erase2 OK 1 A ‘Margin Read’ is any read after executing the margin setting commands ‘Set User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified. See the Note on margin settings in Section 24.4.6.12 and Section 24.4.6.13. 2 The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ MC9S12G Family Reference Manual Rev.1.28 794 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) 24.4.6 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence. The ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be processed by the Memory Controller: • Starting any command write sequence that programs or erases Flash memory before initializing the FCLKDIV register • Writing an invalid command as part of the command write sequence • For additional possible errors, refer to the error handling table provided for each command If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation will return invalid data if both flags SFDIF and DFDIF are set. If the SFDIF or DFDIF flags were not previously set when the invalid read operation occurred, both the SFDIF and DFDIF flags will be set. If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting any command write sequence (see Section 24.3.2.7). CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. 24.4.6.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and EEPROM blocks have been erased. Table 24-29. Erase Verify All Blocks Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x01 Not required Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks operation has completed. If all blocks are not erased, it means blank check failed, both MGSTAT bits will be set. Table 24-30. Erase Verify All Blocks Command Error Handling Register Error Bit ACCERR FPVIOL FSTAT 1 Error Condition Set if CCOBIX[2:0] != 000 at command launch None MGSTAT1 Set if any errors have been encountered during the read1or if blank check failed . MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. As found in the memory map for FTMRG32K1. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 795 16 KByte Flash Module (S12FTMRG16K1V1) 24.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0] bits determine which block must be verified. Table 24-31. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. See Table 24-32 Table 24-32. Flash block selection code description Selection code[1:0] Flash block to be verified 00 EEPROM 01 Invalid (ACCERR) 10 Invalid (ACCERR) 11 P-Flash Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that the selected P-Flash or EEPROM block is erased. The CCIF flag will set after the Erase Verify Block operation has completed.If the block is not erased, it means blank check failed, both MGSTAT bits will be set. Table 24-33. Erase Verify Block Command Error Handling Register Error Bit ACCERR FSTAT 1 2 FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if an invalid FlashBlockSelectionCode[1:0] is supplied1 None MGSTAT1 Set if any errors have been encountered during the read2 or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read2 or if blank check failed. As defined by the memory map for FTMRG32K1. As found in the memory map for FTMRG32K1. 24.4.6.3 Erase Verify P-Flash Section Command The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. MC9S12G Family Reference Manual Rev.1.28 796 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-34. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. Table 24-35. Erase Verify P-Flash Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 24-25) ACCERR Set if an invalid global address [17:0] is supplied see Table 24-3)1 Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT Set if the requested section crosses a the P-Flash address boundary FPVIOL 1 2 None MGSTAT1 Set if any errors have been encountered during the read2 or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read2 or if blank check failed. As defined by the memory map for FTMRG32K1. As found in the memory map for FTMRG32K1. 24.4.6.4 Read Once Command The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of P-Flash. The Read Once field is programmed using the Program Once command described in Section 24.4.6.6. The Read Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 24-36. Read Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x04 Not Required 001 Read Once phrase index (0x0000 - 0x0007) 010 Read Once word 0 value 011 Read Once word 1 value 100 Read Once word 2 value MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 797 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-36. Read Once Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 101 Read Once word 3 value Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. 8 Table 24-37. Read Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if an invalid phrase index is supplied FSTAT 24.4.6.5 Set if command not available in current mode (see Table 24-25) FPVIOL None MGSTAT1 Set if any errors have been encountered during the read MGSTAT0 Set if any non-correctable errors have been encountered during the read Program P-Flash Command The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an embedded algorithm. CAUTION A P-Flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash phrase is not allowed. Table 24-38. Program P-Flash Command FCCOB Requirements CCOBIX[2:0] 000 1 FCCOB Parameters 0x06 Global address [17:16] to identify P-Flash block 001 Global address [15:0] of phrase location to be programmed1 010 Word 0 program value 011 Word 1 program value 100 Word 2 program value 101 Word 3 program value Global address [2:0] must be 000 Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. The CCIF flag will set after the Program P-Flash operation has completed. MC9S12G Family Reference Manual Rev.1.28 798 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-39. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid global address [17:0] is supplied see Table 24-3)1 Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 1 Set if command not available in current mode (see Table 24-25) Set if the global address [17:0] points to a protected area MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation As defined by the memory map for FTMRG32K1. 24.4.6.6 Program Once Command The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in P-Flash. The Program Once reserved field can be read using the Read Once command as described in Section 24.4.6.4. The Program Once command must only be issued once since the nonvolatile information register in P-Flash cannot be erased. The Program Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 24-40. Program Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x07 Not Required 001 Program Once phrase index (0x0000 - 0x0007) 010 Program Once word 0 value 011 Program Once word 1 value 100 Program Once word 2 value 101 Program Once word 3 value Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with read back. The CCIF flag will remain clear, setting only after the Program Once operation has completed. The reserved nonvolatile information register accessed by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 799 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-41. Program Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed1 FSTAT FPVIOL 1 Set if command not available in current mode (see Table 24-25) None MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will be allowed to execute again on that same phrase. 24.4.6.7 Erase All Blocks Command The Erase All Blocks operation will erase the entire P-Flash and EEPROM memory space. Table 24-42. Erase All Blocks Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x08 Not required Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All Blocks operation has completed. Table 24-43. Erase All Blocks Command Error Handling Register Error Bit ACCERR FSTAT 1 FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 24-25) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation1 MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation1 As found in the memory map for FTMRG32K1. 24.4.6.8 Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or EEPROM block. MC9S12G Family Reference Manual Rev.1.28 800 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-44. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 24-45. Erase Flash Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 24-25) ACCERR Set if the supplied P-Flash address is not phrase-aligned or if the EEPROM address is not word-aligned FSTAT FPVIOL 1 2 Set if an invalid global address [17:16] is supplied1 Set if an area of the selected Flash block is protected MGSTAT1 Set if any errors have been encountered during the verify operation2 MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation2 As defined by the memory map for FTMRG32K1. As found in the memory map for FTMRG32K1. 24.4.6.9 Erase P-Flash Sector Command The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector. Table 24-46. Erase P-Flash Sector Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x0A Global address [17:16] to identify P-Flash block to be erased Global address [15:0] anywhere within the sector to be erased. Refer to Section 24.1.2.1 for the P-Flash sector size. Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 801 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-47. Erase P-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if an invalid global address [17:16] is supplied see Table 24-3)1 Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 1 Set if command not available in current mode (see Table 24-25) Set if the selected P-Flash sector is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation As defined by the memory map for FTMRG32K1. 24.4.6.10 Unsecure Flash Command The Unsecure Flash command will erase the entire P-Flash and EEPROM memory space and, if the erase is successful, will release security. Table 24-48. Unsecure Flash Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x0B Not required Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire P-Flash and EEPROM memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. If the erase verify is not successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security state. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag is set after the Unsecure Flash operation has completed. Table 24-49. Unsecure Flash Command Error Handling Register Error Bit ACCERR FSTAT 1 FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 24-25) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation1 MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation1 As found in the memory map for FTMRG32K1. MC9S12G Family Reference Manual Rev.1.28 802 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) 24.4.6.11 Verify Backdoor Access Key Command The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 24-10). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see Table 24-4). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 24-50. Verify Backdoor Access Key Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0C Not required 001 Key 0 010 Key 1 011 Key 2 100 Key 3 Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash configuration field with Key 0 compared to 0x3_FF00, etc. If the backdoor keys match, security will be released. If the backdoor keys do not match, security is not released and all future attempts to execute the Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is set after the Verify Backdoor Access Key operation has completed. Table 24-51. Verify Backdoor Access Key Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 100 at command launch Set if an incorrect backdoor key is supplied ACCERR FSTAT Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see Section 24.3.2.2) Set if the backdoor key has mismatched since the last reset FPVIOL None MGSTAT1 None MGSTAT0 None 24.4.6.12 Set User Margin Level Command The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P-Flash or EEPROM block. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 803 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-52. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0D 001 Flash block selection code [1:0]. Table 24-32 See Margin level setting. Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply user margin levels to the P-Flash block only. Valid margin level settings for the Set User Margin Level command are defined in Table 24-53. Table 24-53. Valid Set User Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state Table 24-54. Set User Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR FSTAT Set if command not available in current mode (see Table 24-25) Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 24-32 ) Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None MC9S12G Family Reference Manual Rev.1.28 804 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) NOTE User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. 24.4.6.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of the P-Flash or EEPROM block. Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the Table 24-55. Set Field Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0E 001 Flash block selection code [1:0]. Table 24-32 See Margin level setting. field margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM field margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash field margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply field margin levels to the P-Flash block only. Valid margin level settings for the Set Field Margin Level command are defined in Table 24-56. Table 24-56. Valid Set Field Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 0x0003 Field Margin-1 Level1 0x0004 Field Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 805 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-57. Set Field Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR FSTAT 1 Set if command not available in current mode (see Table 24-25) Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 24-32 )1 Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None As defined by the memory map for FTMRG32K1. CAUTION Field margin levels must only be used during verify of the initial factory programming. NOTE Field margin levels can be used to check that Flash memory contents have adequate margin for data retention at the normal level setting. If unexpected results are encountered when checking Flash memory contents at field margin levels, the Flash memory contents should be erased and reprogrammed. 24.4.6.14 Erase Verify EEPROM Section Command The Erase Verify EEPROM Section command will verify that a section of code in the EEPROM is erased. The Erase Verify EEPROM Section command defines the starting point of the data to be verified and the number of words. Table 24-58. Erase Verify EEPROM Section Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x10 Global address [17:16] to identify the EEPROM block 001 Global address [15:0] of the first word to be verified 010 Number of words to be verified Upon clearing CCIF to launch the Erase Verify EEPROM Section command, the Memory Controller will verify the selected section of EEPROM memory is erased. The CCIF flag will set after the Erase Verify EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12G Family Reference Manual Rev.1.28 806 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-59. Erase Verify EEPROM Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 24-25) ACCERR Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested section breaches the end of the EEPROM block FPVIOL None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. 24.4.6.15 Program EEPROM Command The Program EEPROM operation programs one to four previously erased words in the EEPROM block. The Program EEPROM operation will confirm that the targeted location(s) were successfully programmed upon completion. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Table 24-60. Program EEPROM Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x11 Global address [17:16] to identify the EEPROM block 001 Global address [15:0] of word to be programmed 010 Word 0 program value 011 Word 1 program value, if desired 100 Word 2 program value, if desired 101 Word 3 program value, if desired Upon clearing CCIF to launch the Program EEPROM command, the user-supplied words will be transferred to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program EEPROM command launch determines how many words will be programmed in the EEPROM block. The CCIF flag is set when the operation has completed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 807 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-61. Program EEPROM Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] < 010 at command launch Set if CCOBIX[2:0] > 101 at command launch ACCERR Set if command not available in current mode (see Table 24-25) Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested group of words breaches the end of the EEPROM block FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 24.4.6.16 Erase EEPROM Sector Command The Erase EEPROM Sector operation will erase all addresses in a sector of the EEPROM block. Table 24-62. Erase EEPROM Sector Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x12 Global address [17:16] to identify EEPROM block Global address [15:0] anywhere within the sector to be erased. See Section 24.1.2.2 for EEPROM sector size. Upon clearing CCIF to launch the Erase EEPROM Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase EEPROM Sector operation has completed. Table 24-63. Erase EEPROM Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if command not available in current mode (see Table 24-25) Set if an invalid global address [17:0] is suppliedsee Table 24-3) Set if a misaligned word address is supplied (global address [0] != 0) FSTAT FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation MC9S12G Family Reference Manual Rev.1.28 808 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) 24.4.7 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 24-64. Flash Interrupt Sources Interrupt Source Global (CCR) Mask Interrupt Flag Local Enable CCIF (FSTAT register) CCIE (FCNFG register) I Bit ECC Double Bit Fault on Flash Read DFDIF (FERSTAT register) DFDIE (FERCNFG register) I Bit ECC Single Bit Fault on Flash Read SFDIF (FERSTAT register) SFDIE (FERCNFG register) I Bit Flash Command Complete NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 24.4.7.1 Description of Flash Interrupt Operation The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed description of the register bits involved, refer to Section 24.3.2.5, “Flash Configuration Register (FCNFG)”, Section 24.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 24.3.2.7, “Flash Status Register (FSTAT)”, and Section 24.3.2.8, “Flash Error Status Register (FERSTAT)”. The logic used for generating the Flash module interrupts is shown in Figure 24-26. CCIE CCIF DFDIE DFDIF Flash Command Interrupt Request Flash Error Interrupt Request SFDIE SFDIF Figure 24-26. Flash Module Interrupts Implementation MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 809 16 KByte Flash Module (S12FTMRG16K1V1) 24.4.8 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 24.4.7, “Interrupts”). 24.4.9 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. 24.5 Security The Flash module provides security information to the MCU. The Flash security state is defined by the SEC bits of the FSEC register (see Table 24-11). During reset, the Flash module initializes the FSEC register using data read from the security byte of the Flash configuration field at global address 0x3_FF0F. The security state out of reset can be permanently changed by programming the security byte assuming that the MCU is starting from a mode where the necessary P-Flash erase and program commands are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset. The following subsections describe these security-related subjects: • Unsecuring the MCU using Backdoor Key Access • Unsecuring the MCU in Special Single Chip Mode using BDM • Mode and Security Effects on Flash Command Availability 24.5.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x3_FF00-0x3_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 24.3.2.2), the Verify Backdoor Access Key command (see Section 24.4.6.11) allows the user to present four prospective keys for comparison to the keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC register (see Table 24-11) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash memory and EEPROM memory will not be available for read access and will return invalid data. MC9S12G Family Reference Manual Rev.1.28 810 NXP Semiconductors 16 KByte Flash Module (S12FTMRG16K1V1) The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 24.3.2.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 24.4.6.11 2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10 The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method to re-enable the Verify Backdoor Access Key command. The security as defined in the Flash security byte (0x3_FF0F) is not changed by using the Verify Backdoor Access Key command sequence. The backdoor keys stored in addresses 0x3_FF00-0x3_FF07 are unaffected by the Verify Backdoor Access Key command sequence. The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection register, FPROT. After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is unsecured, the sector containing the Flash security byte can be erased and the Flash security byte can be reprogrammed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x3_FF00-0x3_FF07 in the Flash configuration field. 24.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM A secured MCU can be unsecured in special single chip mode by using the following method to erase the P-Flash and EEPROM memory: 1. Reset the MCU into special single chip mode 2. Delay while the BDM executes the Erase Verify All Blocks command write sequence to check if the P-Flash and EEPROM memories are erased 3. Send BDM commands to disable protection in the P-Flash and EEPROM memory 4. Execute the Erase All Blocks command write sequence to erase the P-Flash and EEPROM memory. Alternatively the Unsecure Flash command can be executed, if so the steps 5 and 6 below are skeeped. 5. After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into special single chip mode 6. Delay while the BDM executes the Erase Verify All Blocks command write sequence to verify that the P-Flash and EEPROM memory are erased If the P-Flash and EEPROM memory are verified as erased, the MCU will be unsecured. All BDM commands will now be enabled and the Flash security byte may be programmed to the unsecure state by continuing with the following steps: 7. Send BDM commands to execute the Program P-Flash command write sequence to program the Flash security byte to the unsecured state MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 811 16 KByte Flash Module (S12FTMRG16K1V1) 8. Reset the MCU 24.5.3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 24-25. 24.6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the Flash Block Configuration Parameters, the FPROT and EEPROT protection registers, and the FOPT and FSEC registers. The initialization routine reverts to built-in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence. If a double bit fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set. CCIF is cleared throughout the initialization sequence. The Flash module holds off all CPU access for a portion of the initialization sequence. Flash reads are allowed once the hold is removed. Completion of the initialization sequence is marked by setting CCIF high which enables user commands. If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12G Family Reference Manual Rev.1.28 812 NXP Semiconductors Chapter 25 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-1. Revision History Revision Number Revision Date V01.04 Sections Affected Description of Changes 17 Jun 2010 25.4.6.1/25-846 25.4.6.2/25-847 25.4.6.3/25-847 25.4.6.14/25-857 Clarify Erase Verify Commands Descriptions related to the bits MGSTAT[1:0] of the register FSTAT. V01.05 20 Aug 2010 25.4.6.2/25-847 25.4.6.12/25-854 25.4.6.13/25-856 Updated description of the commands RD1BLK, MLOADU and MLOADF V01.06 31 Jan 2011 25.3.2.9/25-829 Updated description of protection on Section 25.3.2.9 25.1 Introduction The FTMRG32K1 module implements the following: • 32Kbytes of P-Flash (Program Flash) memory • 1 Kbytes of EEPROM memory The Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory contents. The user interface to the memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is written to with the command, global address, data, and any required command parameters. The memory controller must complete the execution of a command before the FCCOB register can be written to with a new command. CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 813 It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory. Simultaneous P-Flash and EEPROM operations are discussed in Section 25.4.5. Both P-Flash and EEPROM memories are implemented with Error Correction Codes (ECC) that can resolve single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read by half-phrase, only one single bit fault in an aligned 4 byte half-phrase containing the byte or word accessed will be corrected. 25.1.1 Glossary Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. EEPROM Memory — The EEPROM memory constitutes the nonvolatile memory store for data. EEPROM Sector — The EEPROM sector is the smallest portion of the EEPROM memory that can be erased. The EEPROM sector consists of 4 bytes. NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters required for Flash command execution. Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double bit fault detection within each double word. P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications. P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased. Each P-Flash sector contains 512 bytes. Program IFR — Nonvolatile information register located in the P-Flash block that contains the Version ID, and the Program Once field. 25.1.2 25.1.2.1 • • • Features P-Flash Features 32 Kbytes of P-Flash memory composed of one 32 Kbyte Flash block divided into 64 sectors of 512 bytes Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 814 32 KByte Flash Module (S12FTMRG32K1V1) • • • Fast sector erase and phrase program operation Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 25.1.2.2 • • • • • • 1 Kbyte of EEPROM memory composed of one 1 Kbyte Flash block divided into 256 sectors of 4 bytes Single bit fault correction and double bit fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Protection scheme to prevent accidental program or erase of EEPROM memory Ability to program up to four words in a burst sequence 25.1.2.3 • • • EEPROM Features Other Flash Module Features No external high-voltage power supply required for Flash memory program and erase operations Interrupt generation on Flash command completion and Flash error detection Security mechanism to prevent unauthorized access to the Flash memory 25.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 25-1. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 815 32 KByte Flash Module (S12FTMRG32K1V1) Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 8Kx39 sector 0 sector 1 Protection sector 63 Security Bus Clock Clock Divider FCLK Memory Controller CPU EEPROM 512x22 sector 0 sector 1 sector 255 Figure 25-1. FTMRG32K1 Block Diagram 25.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual Rev.1.28 816 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) 25.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed. If such action is attempted the write operation will not change the register value. Writing to the Flash registers is allowed when the Flash is not busy executing commands (CCIF = 1) and during initialization right after reset, despite the value of flag CCIF in that case (refer to Section 25.6 for a complete description of the reset sequence). . Table 25-2. FTMRG Memory Map Global Address (in Bytes) 0x0_0000 - 0x0_03FF 1 Size (Bytes) 1,024 Description Register Space 0x0_0400 – 0x0_07FF 1,024 EEPROM Memory 0x0_4000 – 0x0_7FFF 16,284 NVMRES1=1 : NVM Resource area (see Figure 25-3) 0x3_8000 – 0x3_FFFF 32,768 P-Flash Memory See NVMRES description in Section 25.4.3 25.3.1 Module Memory Map The S12 architecture places the P-Flash memory between global addresses 0x3_8000 and 0x3_FFFF as shown in Table 25-3.The P-Flash memory map is shown in Figure 25-2. Table 25-3. P-Flash Memory Addressing Global Address Size (Bytes) 0x3_8000 – 0x3_FFFF 32 K Description P-Flash Block Contains Flash Configuration Field (see Table 25-4) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 817 32 KByte Flash Module (S12FTMRG32K1V1) The FPROT register, described in Section 25.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. Three separate memory regions, one growing upward from global address 0x3_8000 in the Flash memory (called the lower region), one growing downward from global address 0x3_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection. The Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 25-4. Table 25-4. Flash Configuration Field 1 Global Address Size (Bytes) 0x3_FF00-0x3_FF07 8 Backdoor Comparison Key Refer to Section 25.4.6.11, “Verify Backdoor Access Key Command,” and Section 25.5.1, “Unsecuring the MCU using Backdoor Key Access” 0x3_FF08-0x3_FF0B1 4 Reserved 0x3_FF0C1 1 P-Flash Protection byte. Refer to Section 25.3.2.9, “P-Flash Protection Register (FPROT)” 0x3_FF0D1 1 EEPROM Protection byte. Refer to Section 25.3.2.10, “EEPROM Protection Register (EEPROT)” 0x3_FF0E1 1 Flash Nonvolatile byte Refer to Section 25.3.2.16, “Flash Option Register (FOPT)” 0x3_FF0F1 1 Flash Security byte Refer to Section 25.3.2.2, “Flash Security Register (FSEC)” Description 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B reserved field should be programmed to 0xFF. MC9S12G Family Reference Manual Rev.1.28 818 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) P-Flash START = 0x3_8000 0x3_8400 0x3_8800 0x3_9000 Protection Fixed End Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x3_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) Protection Movable End 0x3_C000 Protection Fixed End 0x3_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 P-Flash END = 0x3_FFFF Flash Configuration Field 16 bytes (0x3_FF00 - 0x3_FF0F) Figure 25-2. P-Flash Memory Map Table 25-5. Program IFR Fields 1 Global Address Size (Bytes) 0x0_4000 – 0x0_4007 8 Reserved 0x0_4008 – 0x0_40B5 174 Reserved 0x0_40B6 – 0x0_40B7 2 Version ID1 0x0_40B8 – 0x0_40BF 8 Reserved 0x0_40C0 – 0x0_40FF 64 Program Once Field Refer to Section 25.4.6.6, “Program Once Command” Field Description Used to track firmware patch versions, see Section 25.4.2 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 819 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-6. Memory Controller Resource Fields (NVMRES1=1) Global Address Size (Bytes) 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 25-5) 0x0_4100 – 0x0_41FF 256 Reserved. 0x0_4200 – 0x0_57FF 1 Description Reserved 0x0_5800 – 0x0_59FF 512 Reserved 0x0_5A00 – 0x0_5FFF 1,536 Reserved 0x0_6000 – 0x0_6BFF 3,072 Reserved 0x0_6C00 – 0x0_7FFF 5,120 Reserved NVMRES - See Section 25.4.3 for NVMRES (NVM Resource) detail. 0x0_4000 0x0_4400 RAM Start = 0x0_5800 RAM End = 0x0_59FF P-Flash IFR 1 Kbyte (NVMRES=1) Reserved 5k bytes Reserved 512 bytes Reserved 4608 bytes 0x0_6C00 Reserved 5120 bytes 0x0_7FFF Figure 25-3. Memory Controller Resource Memory Map (NVMRES=1) 25.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 25.3). MC9S12G Family Reference Manual Rev.1.28 820 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) A summary of the Flash module registers is given in Figure 25-4 with detailed descriptions in the following subsections. Address & Name 0x0000 FCLKDIV 0x0001 FSEC 0x0002 FCCOBIX 0x0003 FRSV0 0x0004 FCNFG 0x0005 FERCNFG 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 EEPROT 0x000A FCCOBHI 0x000B FCCOBLO 0x000C FRSV1 7 R 6 5 4 3 2 1 0 FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0 0 0 0 0 0 0 0 0 0 0 0 0 FDFD FSFD 0 0 0 0 0 DFDIE SFDIE ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0 0 0 0 0 DFDIF SFDIF FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 DPS4 DPS3 DPS2 DPS1 DPS0 FDIVLD W R W R W R W R W R CCIE 0 IGNSF W R W R CCIF 0 0 0 W R W R W R W R W R FPOPEN RNV6 0 0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0 0 0 0 0 0 0 0 DPOPEN W Figure 25-4. FTMRG32K1 Register Summary MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 821 32 KByte Flash Module (S12FTMRG32K1V1) Address & Name 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT 0x0011 FRSV5 0x0012 FRSV6 0x0013 FRSV7 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W R W R W R W R W = Unimplemented or Reserved Figure 25-4. FTMRG32K1 Register Summary (continued) 25.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Offset Module Base + 0x0000 7 R FDIVLD W Reset 0 6 5 4 3 FDIVLCK 0 2 1 0 0 0 0 FDIV[5:0] 0 0 0 = Unimplemented or Reserved Figure 25-5. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. MC9S12G Family Reference Manual Rev.1.28 822 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). Table 25-7. FCLKDIV Field Descriptions Field 7 FDIVLD Description Clock Divider Loaded 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset 6 FDIVLCK Clock Divider Locked 0 FDIV field is open for writing 1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in normal mode. 5–0 FDIV[5:0] Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events during Flash program and erase algorithms. Table 25-8 shows recommended values for FDIV[5:0] based on the BUSCLK frequency. Please refer to Section 25.4.4, “Flash Command Operations,” for more information. Table 25-8. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) 1 2 MIN1 MAX2 1.0 1.6 1.6 FDIV[5:0] BUSCLK Frequency (MHz) FDIV[5:0] MIN1 MAX2 0x00 16.6 17.6 0x10 2.6 0x01 17.6 18.6 0x11 2.6 3.6 0x02 18.6 19.6 0x12 3.6 4.6 0x03 19.6 20.6 0x13 4.6 5.6 0x04 20.6 21.6 0x14 5.6 6.6 0x05 21.6 22.6 0x15 6.6 7.6 0x06 22.6 23.6 0x16 7.6 8.6 0x07 23.6 24.6 0x17 8.6 9.6 0x08 24.6 25.6 0x18 9.6 10.6 0x09 10.6 11.6 0x0A 11.6 12.6 0x0B 12.6 13.6 0x0C 13.6 14.6 0x0D 14.6 15.6 0x0E 15.6 16.6 0x0F BUSCLK is Greater Than this value. BUSCLK is Less Than or Equal to this value. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 823 32 KByte Flash Module (S12FTMRG32K1V1) 25.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 25-6. Flash Security Register (FSEC) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FSEC register are readable but not writable. During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the Flash configuration field at global address 0x3_FF0F located in P-Flash memory (see Table 25-4) as indicated by reset condition F in Figure 25-6. If a double bit fault is detected while reading the P-Flash phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set to leave the Flash module in a secured state with backdoor key access disabled. Table 25-9. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the KEYEN[1:0] Flash module as shown in Table 25-10. 5–2 RNV[5:2] Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements. 1–0 SEC[1:0] Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 25-11. If the Flash module is unsecured using backdoor key access, the SEC bits are forced to 10. Table 25-10. Flash KEYEN States 1 KEYEN[1:0] Status of Backdoor Key Access 00 DISABLED 01 DISABLED1 10 ENABLED 11 DISABLED Preferred KEYEN state to disable backdoor key access. MC9S12G Family Reference Manual Rev.1.28 824 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-11. Flash Security States 1 SEC[1:0] Status of Security 00 SECURED 01 SECURED1 10 UNSECURED 11 SECURED Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 25.5. 25.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations. Offset Module Base + 0x0002 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 CCOBIX[2:0] W Reset 1 0 0 0 = Unimplemented or Reserved Figure 25-7. FCCOB Index Register (FCCOBIX) CCOBIX bits are readable and writable while remaining bits read 0 and are not writable. Table 25-12. FCCOBIX Field Descriptions Field Description 2–0 CCOBIX[1:0] Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to. See 25.3.2.11 Flash Common Command Object Register (FCCOB),” for more details. 25.3.2.4 Flash Reserved0 Register (FRSV0) This Flash register is reserved for factory testing. Offset Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 25-8. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 825 32 KByte Flash Module (S12FTMRG32K1V1) 25.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU. Offset Module Base + 0x0004 7 R W Reset CCIE 0 6 5 0 0 0 0 4 IGNSF 0 3 2 0 0 0 0 1 0 FDFD FSFD 0 0 = Unimplemented or Reserved Figure 25-9. Flash Configuration Register (FCNFG) CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not writable. Table 25-13. FCNFG Field Descriptions Field Description 7 CCIE Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command has completed. 0 Command complete interrupt disabled 1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 25.3.2.7) 4 IGNSF Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see Section 25.3.2.8). 0 All single bit faults detected during array reads are reported 1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated 1 FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. 0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected 1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see Section 25.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG register is set (see Section 25.3.2.6) 0 FSFD Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. 0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected 1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 25.3.2.7) and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see Section 25.3.2.6) 25.3.2.6 Flash Error Configuration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. MC9S12G Family Reference Manual Rev.1.28 826 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) Offset Module Base + 0x0005 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDIE SFDIE 0 0 = Unimplemented or Reserved Figure 25-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. Table 25-14. FERCNFG Field Descriptions Field Description 1 DFDIE Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation. 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set (see Section 25.3.2.8) 0 SFDIE Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault is detected during a Flash block read operation. 0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 25.3.2.8) 1 An interrupt will be requested whenever the SFDIF flag is set (see Section 25.3.2.8) 25.3.2.7 Flash Status Register (FSTAT) The FSTAT register reports the operational status of the Flash module. Offset Module Base + 0x0006 7 R W Reset CCIF 1 6 0 0 5 4 ACCERR FPVIOL 0 0 3 2 MGBUSY RSVD 0 0 1 0 MGSTAT[1:0] 01 01 = Unimplemented or Reserved Figure 25-11. Flash Status Register (FSTAT) 1 Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 25.6). CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 827 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation. 0 Flash command in progress 1 Flash command has completed 5 ACCERR Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory caused by either a violation of the command write sequence (see Section 25.4.4.2) or issuing an illegal Flash command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR. 0 No access error detected 1 Access error detected 4 FPVIOL Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of P-Flash or EEPROM memory during a command write sequence. The FPVIOL bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected 1 Protection violation detected 3 MGBUSY 2 RSVD Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller. 0 Memory Controller is idle 1 Memory Controller is busy executing a Flash command (CCIF = 0) Reserved Bit — This bit is reserved and always reads 0. 1–0 Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See Section 25.4.6, “Flash Command Description,” and Section 25.6, “Initialization” for details. 25.3.2.8 Flash Error Status Register (FERSTAT) The FERSTAT register reflects the error status of internal Flash operations. Offset Module Base + 0x0007 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDIF SFDIF 0 0 = Unimplemented or Reserved Figure 25-12. Flash Error Status Register (FERSTAT) All flags in the FERSTAT register are readable and only writable to clear the flag. MC9S12G Family Reference Manual Rev.1.28 828 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The DFDIF flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.2 0 No double bit fault detected 1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command running 0 SFDIF Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF. 0 No single bit fault detected 1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted while command running 1 The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either single fault or double fault but never both). A simultaneous access collision (Flash array read operation returning invalid data attempted while command running) is indicated when both SFDIF and DFDIF flags are high. 2 There is a one cycle delay in storing the ECC DFDIF and SFDIF fault flags in this register. At least one NOP is required after a flash memory read before checking FERSTAT for the occurrence of ECC errors. 25.3.2.9 P-Flash Protection Register (FPROT) The FPROT register defines which P-Flash sectors are protected against program and erase operations. Offset Module Base + 0x0008 7 R W Reset FPOPEN F1 6 5 RNV6 F1 4 FPHDIS F1 3 FPHS[1:0] F1 2 1 FPLDIS F1 F1 0 FPLS[1:0] F1 F1 = Unimplemented or Reserved Figure 25-13. Flash Protection Register (FPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected region can only be increased (see Section 25.3.2.9.1, “P-Flash Protection Restrictions,” and Table 25-21). During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte in the Flash configuration field at global address 0x3_FF0C located in P-Flash memory (see Table 25-4) as indicated by reset condition ‘F’ in Figure 25-13. To change the P-Flash protection that will be loaded during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 829 32 KByte Flash Module (S12FTMRG32K1V1) Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. Table 25-17. FPROT Field Descriptions Field Description 7 FPOPEN Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or erase operations as shown in Table 25-18 for the P-Flash block. 0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits 1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits 6 RNV[6] Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements. 5 FPHDIS Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory ending with global address 0x3_FFFF. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 4–3 FPHS[1:0] Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area in P-Flash memory as shown inTable 25-19. The FPHS bits can only be written to while the FPHDIS bit is set. 2 FPLDIS Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory beginning with global address 0x3_8000. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 1–0 FPLS[1:0] Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area in P-Flash memory as shown in Table 25-20. The FPLS bits can only be written to while the FPLDIS bit is set. Table 25-18. P-Flash Protection Function 1 Function1 FPOPEN FPHDIS FPLDIS 1 1 1 No P-Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P-Flash Memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges For range sizes, refer to Table 25-19 and Table 25-20. MC9S12G Family Reference Manual Rev.1.28 830 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-19. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 00 0x3_F800–0x3_FFFF 2 Kbytes 01 0x3_F000–0x3_FFFF 4 Kbytes 10 0x3_E000–0x3_FFFF 8 Kbytes 11 0x3_C000–0x3_FFFF 16 Kbytes Table 25-20. P-Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 00 0x3_8000–0x3_83FF 1 Kbyte 01 0x3_8000–0x3_87FF 2 Kbytes 10 0x3_8000–0x3_8FFF 4 Kbytes 11 0x3_8000–0x3_9FFF 8 Kbytes All possible P-Flash protection scenarios are shown in Figure 25-14 . Although the protection scheme is loaded from the Flash memory at global address 0x3_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 831 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 Scenario FLASH START FPLS[1:0] 0x3_FFFF FPHS[1:0] 0x3_8000 FPOPEN = 0 0x3_8000 FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 32 KByte Flash Module (S12FTMRG32K1V1) 0x3_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 25-14. P-Flash Protection Scenarios MC9S12G Family Reference Manual Rev.1.28 832 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) 25.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 25-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 25-21. P-Flash Protection Scenario Transitions To Protection Scenario1 From Protection Scenario 0 1 2 3 0 X X X X X 1 X 4 X X X X X X X X X X 6 X 7 1 X 6 7 X 3 5 5 X X 2 4 X X X X X X Allowed transitions marked with X, see Figure 25-14 for a definition of the scenarios. 25.3.2.10 EEPROM Protection Register (EEPROT) The EEPROT register defines which EEPROM sectors are protected against program and erase operations. Offset Module Base + 0x0009 7 R W Reset DPOPEN F1 6 5 0 0 0 0 4 3 2 1 0 F1 F1 DPS[4:0] F1 F1 F1 = Unimplemented or Reserved Figure 25-15. EEPROM Protection Register (EEPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the EEPROT register are writable with the restriction that protection can be added but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1 (protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is irrelevant. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 833 32 KByte Flash Module (S12FTMRG32K1V1) During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in P-Flash memory (see Table 25-4) as indicated by reset condition F in Table 25-23. To change the EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase containing the EEPROM protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the EEPROM memory fully protected. Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. Block erase of the EEPROM memory is not possible if any of the EEPROM sectors are protected. Table 25-22. EEPROT Field Descriptions Field Description 7 DPOPEN EEPROM Protection Control 0 Enables EEPROM memory protection from program and erase with protected address range defined by DPS bits 1 Disables EEPROM memory protection from program and erase 4–0 DPS[4:0] EEPROM Protection Size — The DPS[4:0] bits determine the size of the protected area in the EEPROM memory as shown inTable 25-23 . Table 25-23. EEPROM Protection Address Range DPS[4:0] Global Address Range Protected Size 00000 0x0_0400 – 0x0_041F 32 bytes 00001 0x0_0400 – 0x0_043F 64 bytes 00010 0x0_0400 – 0x0_045F 96 bytes 00011 0x0_0400 – 0x0_047F 128 bytes 00100 0x0_0400 – 0x0_049F 160 bytes 00101 0x0_0400 – 0x0_04BF 192 bytes The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increasing of one. . . . 11111 - to - 11111 0x0_0400 – 0x0_07FF 1,024 bytes MC9S12G Family Reference Manual Rev.1.28 834 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) 25.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. Offset Module Base + 0x000A 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[15:8] W Reset 3 0 0 0 0 Figure 25-16. Flash Common Command Object High Register (FCCOBHI) Offset Module Base + 0x000B 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[7:0] W Reset 3 0 0 0 0 Figure 25-17. Flash Common Command Object Low Register (FCCOBLO) 25.3.2.11.1 FCCOB - NVM Command Mode NVM command mode uses the indexed FCCOB register to provide a command code and its relevant parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes (as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array. The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 25-24. The return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller. Writes to the unimplemented parameter fields (CCOBIX = 110 and CCOBIX = 111) are ignored with reads from these fields returning 0x0000. Table 25-24 shows the generic Flash command format. The high byte of the first word in the CCOB array contains the command code, followed by the parameters for this specific Flash command. For details on the FCCOB settings required by each command, see the Flash command descriptions in Section 25.4.6. Table 25-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] 000 001 Byte FCCOB Parameter Fields (NVM Command Mode) HI FCMD[7:0] defining Flash command LO 6’h0, Global address [17:16] HI Global address [15:8] LO Global address [7:0] MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 835 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] 010 011 100 101 Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 0 [15:8] LO Data 0 [7:0] HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 25.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing. Offset Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 25-18. Flash Reserved1 Register (FRSV1) All bits in the FRSV1 register read 0 and are not writable. 25.3.2.13 Flash Reserved2 Register (FRSV2) This Flash register is reserved for factory testing. Offset Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 25-19. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. 25.3.2.14 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.28 836 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) Offset Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 25-20. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 25.3.2.15 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing. Offset Module Base + 0x000F R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 25-21. Flash Reserved4 Register (FRSV4) All bits in the FRSV4 register read 0 and are not writable. 25.3.2.16 Flash Option Register (FOPT) The FOPT register is the Flash option register. Offset Module Base + 0x0010 7 6 5 4 R 3 2 1 0 F1 F1 F1 F1 NV[7:0] W Reset F1 F1 F1 F1 = Unimplemented or Reserved Figure 25-22. Flash Option Register (FOPT) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FOPT register are readable but are not writable. During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global address 0x3_FF0E located in P-Flash memory (see Table 25-4) as indicated by reset condition F in Figure 25-22. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 837 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-25. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits. 25.3.2.17 Flash Reserved5 Register (FRSV5) This Flash register is reserved for factory testing. Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 25-23. Flash Reserved5 Register (FRSV5) All bits in the FRSV5 register read 0 and are not writable. 25.3.2.18 Flash Reserved6 Register (FRSV6) This Flash register is reserved for factory testing. Offset Module Base + 0x0012 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 25-24. Flash Reserved6 Register (FRSV6) All bits in the FRSV6 register read 0 and are not writable. 25.3.2.19 Flash Reserved7 Register (FRSV7) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.28 838 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 25-25. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. 25.4 25.4.1 Functional Description Modes of Operation The FTMRG32K1 module provides the modes of operation normal and special . The operating mode is determined by module-level inputs and affects the FCLKDIV, FCNFG, and EEPROT registers (see Table 25-27). 25.4.2 IFR Version ID Word The version ID word is stored in the IFR at address 0x0_40B6. The contents of the word are defined in Table 25-26. Table 25-26. IFR Version ID Fields [15:4] [3:0] Reserved VERNUM MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 839 32 KByte Flash Module (S12FTMRG32K1V1) • VERNUM: Version number. The first version is number 0b_0001 with both 0b_0000 and 0b_1111 meaning ‘none’. 25.4.3 Internal NVM resource (NVMRES) IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown in Table 25-5. The NVMRES global address map is shown in Table 25-6. 25.4.4 Flash Command Operations Flash command operations are used to modify Flash memory contents. The next sections describe: • How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from BUSCLK for Flash program and erase command operations • The command write sequence used to set Flash command parameters and launch execution • Valid Flash commands available for execution, according to MCU functional mode and MCU security state. 25.4.4.1 Writing the FCLKDIV Register Prior to issuing any Flash program or erase command after a reset, the user is required to write the FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz. Table 25-8 shows recommended values for the FDIV field based on BUSCLK frequency. NOTE Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash memory due to overstress. Setting FDIV too low can result in incomplete programming or erasure of the Flash memory cells. When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written, any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set. 25.4.4.2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see Section 25.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence. If CCIF is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the FCCOB register are ignored. MC9S12G Family Reference Manual Rev.1.28 840 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) 25.4.4.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 25.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag will remain clear until the Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 25-26. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 841 32 KByte Flash Module (S12FTMRG32K1V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no Read: FSTAT register yes FCCOB Availability Check CCIF Set? yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load. Write to FCCOB register to load required command parameter. More Parameters? yes no Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 25-26. Generic Flash Command Write Sequence Flowchart MC9S12G Family Reference Manual Rev.1.28 842 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) 25.4.4.3 Valid Flash Module Commands Table 25-27 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 25-27. Flash Commands by Mode and Security State Unsecured FCMD Command Secured NS1 SS2 NS3 SS4 0x01 Erase Verify All Blocks     0x02 Erase Verify Block     0x03 Erase Verify P-Flash Section    0x04 Read Once    0x06 Program P-Flash    0x07 Program Once    0x08 Erase All Blocks 0x09 Erase Flash Block    0x0A Erase P-Flash Sector    0x0B Unsecure Flash 0x0C Verify Backdoor Access Key  0x0D Set User Margin Level  0x0E Set Field Margin Level 0x10 Erase Verify EEPROM Section    0x11 Program EEPROM    0x12 Erase EEPROM Sector            1 Unsecured Normal Single Chip mode Unsecured Special Single Chip mode. 3 Secured Normal Single Chip mode. 4 Secured Special Single Chip mode. 2 25.4.4.4 P-Flash Commands Table 25-28 summarizes the valid P-Flash commands along with the effects of the commands on the P-Flash block and other resources within the Flash module. Table 25-28. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks Function on P-Flash Memory Verify that all P-Flash (and EEPROM) blocks are erased. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 843 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-28. P-Flash Commands FCMD Command 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a P-Flash (or EEPROM) block. An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. 0x0A Erase P-Flash Sector 0x0B Unsecure Flash 0x0C Verify Backdoor Access Key Supports a method of releasing MCU security by verifying a set of security keys. 0x0D Set User Margin Level Specifies a user margin read level for all P-Flash blocks. 0x0E Set Field Margin Level Specifies a field margin read level for all P-Flash blocks (special modes only). 25.4.4.5 Function on P-Flash Memory Verify that a P-Flash block is erased. Verify that a given number of words starting at the address provided are erased. Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block that was previously programmed using the Program Once command. Program a phrase in a P-Flash block. Erase all bytes in a P-Flash sector. Supports a method of releasing MCU security by erasing all P-Flash (and EEPROM) blocks and verifying that all P-Flash (and EEPROM) blocks are erased. EEPROM Commands Table 25-29 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. Table 25-29. EEPROM Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block Function on EEPROM Memory Verify that all EEPROM (and P-Flash) blocks are erased. Verify that the EEPROM block is erased. MC9S12G Family Reference Manual Rev.1.28 844 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-29. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block. An erase of the full EEPROM block is only possible when DPOPEN bit in the EEPROT register is set prior to launching the command. 0x0B Unsecure Flash 0x0D Set User Margin Level Specifies a user margin read level for the EEPROM block. 0x0E Set Field Margin Level Specifies a field margin read level for the EEPROM block (special modes only). 0x10 Erase Verify EEPROM Section Verify that a given number of words starting at the address provided are erased. 0x11 Program EEPROM Program up to four words in the EEPROM block. 0x12 Erase EEPROM Sector Erase all bytes in a sector of the EEPROM block. 25.4.5 Supports a method of releasing MCU security by erasing all EEPROM (and P-Flash) blocks and verifying that all EEPROM (and P-Flash) blocks are erased. Allowed Simultaneous P-Flash and EEPROM Operations Only the operations marked ‘OK’ in Table 25-30 are permitted to be run simultaneously on the Program Flash and EEPROM blocks. Some operations cannot be executed simultaneously because certain hardware resources are shared by the two memories. The priority has been placed on permitting Program Flash reads while program and erase operations execute on the EEPROM, providing read (P-Flash) while write (EEPROM) functionality. Table 25-30. Allowed P-Flash and EEPROM Simultaneous Operations EEPROM Program Flash Read Read Margin Read1 Program Sector Erase OK OK OK Mass Erase2 Margin Read1 Program Sector Erase Mass Erase2 OK 1 A ‘Margin Read’ is any read after executing the margin setting commands ‘Set User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified. See the Note on margin settings in Section 25.4.6.12 and Section 25.4.6.13. 2 The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 845 32 KByte Flash Module (S12FTMRG32K1V1) 25.4.6 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence. The ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be processed by the Memory Controller: • Starting any command write sequence that programs or erases Flash memory before initializing the FCLKDIV register • Writing an invalid command as part of the command write sequence • For additional possible errors, refer to the error handling table provided for each command If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation will return invalid data if both flags SFDIF and DFDIF are set. If the SFDIF or DFDIF flags were not previously set when the invalid read operation occurred, both the SFDIF and DFDIF flags will be set. If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting any command write sequence (see Section 25.3.2.7). CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. 25.4.6.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and EEPROM blocks have been erased. Table 25-31. Erase Verify All Blocks Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x01 Not required Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks operation has completed. If all blocks are not erased, it means blank check failed, both MGSTAT bits will be set. Table 25-32. Erase Verify All Blocks Command Error Handling Register Error Bit ACCERR FPVIOL FSTAT 1 Error Condition Set if CCOBIX[2:0] != 000 at command launch None MGSTAT1 Set if any errors have been encountered during the read1or if blank check failed . MGSTAT0 Set if any non-correctable errors have been encountered during the read1 or if blank check failed. As found in the memory map for FTMRG32K1. MC9S12G Family Reference Manual Rev.1.28 846 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) 25.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0] bits determine which block must be verified. Table 25-33. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. See Table 25-34 Table 25-34. Flash block selection code description Selection code[1:0] Flash block to be verified 00 EEPROM 01 Invalid (ACCERR) 10 Invalid (ACCERR) 11 P-Flash Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that the selected P-Flash or EEPROM block is erased. The CCIF flag will set after the Erase Verify Block operation has completed.If the block is not erased, it means blank check failed, both MGSTAT bits will be set. Table 25-35. Erase Verify Block Command Error Handling Register Error Bit ACCERR FSTAT 25.4.6.3 FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if an invalid FlashBlockSelectionCode[1:0] is supplied None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. Erase Verify P-Flash Section Command The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 847 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-36. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. Table 25-37. Erase Verify P-Flash Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 25-27) ACCERR Set if an invalid global address [17:0] is supplied see Table 25-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT Set if the requested section crosses a the P-Flash address boundary FPVIOL 25.4.6.4 None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. Read Once Command The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of P-Flash. The Read Once field is programmed using the Program Once command described in Section 25.4.6.6. The Read Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 25-38. Read Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x04 Not Required 001 Read Once phrase index (0x0000 - 0x0007) 010 Read Once word 0 value 011 Read Once word 1 value 100 Read Once word 2 value 101 Read Once word 3 value MC9S12G Family Reference Manual Rev.1.28 848 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. 8 Table 25-39. Read Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if an invalid phrase index is supplied FSTAT 25.4.6.5 Set if command not available in current mode (see Table 25-27) FPVIOL None MGSTAT1 Set if any errors have been encountered during the read MGSTAT0 Set if any non-correctable errors have been encountered during the read Program P-Flash Command The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an embedded algorithm. CAUTION A P-Flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash phrase is not allowed. Table 25-40. Program P-Flash Command FCCOB Requirements CCOBIX[2:0] 000 1 FCCOB Parameters 0x06 Global address [17:16] to identify P-Flash block 001 Global address [15:0] of phrase location to be programmed1 010 Word 0 program value 011 Word 1 program value 100 Word 2 program value 101 Word 3 program value Global address [2:0] must be 000 Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. The CCIF flag will set after the Program P-Flash operation has completed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 849 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-41. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid global address [17:0] is supplied see Table 25-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 25.4.6.6 Set if command not available in current mode (see Table 25-27) Set if the global address [17:0] points to a protected area MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Program Once Command The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in P-Flash. The Program Once reserved field can be read using the Read Once command as described in Section 25.4.6.4. The Program Once command must only be issued once since the nonvolatile information register in P-Flash cannot be erased. The Program Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 25-42. Program Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x07 Not Required 001 Program Once phrase index (0x0000 - 0x0007) 010 Program Once word 0 value 011 Program Once word 1 value 100 Program Once word 2 value 101 Program Once word 3 value Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with read back. The CCIF flag will remain clear, setting only after the Program Once operation has completed. The reserved nonvolatile information register accessed by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. MC9S12G Family Reference Manual Rev.1.28 850 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-43. Program Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed1 FSTAT FPVIOL 1 Set if command not available in current mode (see Table 25-27) None MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will be allowed to execute again on that same phrase. 25.4.6.7 Erase All Blocks Command The Erase All Blocks operation will erase the entire P-Flash and EEPROM memory space. Table 25-44. Erase All Blocks Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x08 Not required Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All Blocks operation has completed. Table 25-45. Erase All Blocks Command Error Handling Register Error Bit ACCERR FSTAT 1 FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 25-27) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation1 MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation As found in the memory map for FTMRG32K1. 25.4.6.8 Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or EEPROM block. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 851 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-46. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 25-47. Erase Flash Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 25-27) ACCERR Set if the supplied P-Flash address is not phrase-aligned or if the EEPROM address is not word-aligned FSTAT FPVIOL 25.4.6.9 Set if an invalid global address [17:16] is supplied Set if an area of the selected Flash block is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Erase P-Flash Sector Command The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector. Table 25-48. Erase P-Flash Sector Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x0A Global address [17:16] to identify P-Flash block to be erased Global address [15:0] anywhere within the sector to be erased. Refer to Section 25.1.2.1 for the P-Flash sector size. Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed. MC9S12G Family Reference Manual Rev.1.28 852 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-49. Erase P-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if an invalid global address [17:16] is supplied see Table 25-3)1 Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 1 Set if command not available in current mode (see Table 25-27) Set if the selected P-Flash sector is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation As defined by the memory map for FTMRG32K1. 25.4.6.10 Unsecure Flash Command The Unsecure Flash command will erase the entire P-Flash and EEPROM memory space and, if the erase is successful, will release security. Table 25-50. Unsecure Flash Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x0B Not required Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire P-Flash and EEPROM memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. If the erase verify is not successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security state. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag is set after the Unsecure Flash operation has completed. Table 25-51. Unsecure Flash Command Error Handling Register Error Bit ACCERR FSTAT FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 25-27) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 25.4.6.11 Verify Backdoor Access Key Command The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 25-10). The Verify Backdoor Access Key command releases security if MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 853 32 KByte Flash Module (S12FTMRG32K1V1) user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see Table 25-4). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 25-52. Verify Backdoor Access Key Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0C Not required 001 Key 0 010 Key 1 011 Key 2 100 Key 3 Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash configuration field with Key 0 compared to 0x3_FF00, etc. If the backdoor keys match, security will be released. If the backdoor keys do not match, security is not released and all future attempts to execute the Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is set after the Verify Backdoor Access Key operation has completed. Table 25-53. Verify Backdoor Access Key Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 100 at command launch Set if an incorrect backdoor key is supplied ACCERR FSTAT Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see Section 25.3.2.2) Set if the backdoor key has mismatched since the last reset FPVIOL None MGSTAT1 None MGSTAT0 None 25.4.6.12 Set User Margin Level Command The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P-Flash or EEPROM block. Table 25-54. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x0D Flash block selection code [1:0]. Table 25-34 See MC9S12G Family Reference Manual Rev.1.28 854 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-54. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 001 Margin level setting. Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply user margin levels to the P-Flash block only. Valid margin level settings for the Set User Margin Level command are defined in Table 25-55. Table 25-55. Valid Set User Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state Table 25-56. Set User Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR FSTAT Set if command not available in current mode (see Table 25-27) Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 25-34 ) Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 855 32 KByte Flash Module (S12FTMRG32K1V1) NOTE User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. 25.4.6.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of the P-Flash or EEPROM block. Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the Table 25-57. Set Field Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0E 001 Flash block selection code [1:0]. Table 25-34 See Margin level setting. field margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM field margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash field margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply field margin levels to the P-Flash block only. Valid margin level settings for the Set Field Margin Level command are defined in Table 25-58. Table 25-58. Valid Set Field Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 0x0003 Field Margin-1 Level1 0x0004 Field Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state MC9S12G Family Reference Manual Rev.1.28 856 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-59. Set Field Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR FSTAT Set if command not available in current mode (see Table 25-27) Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 25-34 ) Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None CAUTION Field margin levels must only be used during verify of the initial factory programming. NOTE Field margin levels can be used to check that Flash memory contents have adequate margin for data retention at the normal level setting. If unexpected results are encountered when checking Flash memory contents at field margin levels, the Flash memory contents should be erased and reprogrammed. 25.4.6.14 Erase Verify EEPROM Section Command The Erase Verify EEPROM Section command will verify that a section of code in the EEPROM is erased. The Erase Verify EEPROM Section command defines the starting point of the data to be verified and the number of words. Table 25-60. Erase Verify EEPROM Section Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x10 Global address [17:16] to identify the EEPROM block 001 Global address [15:0] of the first word to be verified 010 Number of words to be verified Upon clearing CCIF to launch the Erase Verify EEPROM Section command, the Memory Controller will verify the selected section of EEPROM memory is erased. The CCIF flag will set after the Erase Verify EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 857 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-61. Erase Verify EEPROM Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 25-27) ACCERR Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested section breaches the end of the EEPROM block FPVIOL None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. 25.4.6.15 Program EEPROM Command The Program EEPROM operation programs one to four previously erased words in the EEPROM block. The Program EEPROM operation will confirm that the targeted location(s) were successfully programmed upon completion. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Table 25-62. Program EEPROM Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x11 Global address [17:16] to identify the EEPROM block 001 Global address [15:0] of word to be programmed 010 Word 0 program value 011 Word 1 program value, if desired 100 Word 2 program value, if desired 101 Word 3 program value, if desired Upon clearing CCIF to launch the Program EEPROM command, the user-supplied words will be transferred to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program EEPROM command launch determines how many words will be programmed in the EEPROM block. The CCIF flag is set when the operation has completed. MC9S12G Family Reference Manual Rev.1.28 858 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-63. Program EEPROM Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] < 010 at command launch Set if CCOBIX[2:0] > 101 at command launch ACCERR Set if command not available in current mode (see Table 25-27) Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested group of words breaches the end of the EEPROM block FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 25.4.6.16 Erase EEPROM Sector Command The Erase EEPROM Sector operation will erase all addresses in a sector of the EEPROM block. Table 25-64. Erase EEPROM Sector Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x12 Global address [17:16] to identify EEPROM block Global address [15:0] anywhere within the sector to be erased. See Section 25.1.2.2 for EEPROM sector size. Upon clearing CCIF to launch the Erase EEPROM Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase EEPROM Sector operation has completed. Table 25-65. Erase EEPROM Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if command not available in current mode (see Table 25-27) Set if an invalid global address [17:0] is suppliedsee Table 25-3) Set if a misaligned word address is supplied (global address [0] != 0) FSTAT FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 859 32 KByte Flash Module (S12FTMRG32K1V1) 25.4.7 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 25-66. Flash Interrupt Sources Interrupt Source Global (CCR) Mask Interrupt Flag Local Enable CCIF (FSTAT register) CCIE (FCNFG register) I Bit ECC Double Bit Fault on Flash Read DFDIF (FERSTAT register) DFDIE (FERCNFG register) I Bit ECC Single Bit Fault on Flash Read SFDIF (FERSTAT register) SFDIE (FERCNFG register) I Bit Flash Command Complete NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 25.4.7.1 Description of Flash Interrupt Operation The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed description of the register bits involved, refer to Section 25.3.2.5, “Flash Configuration Register (FCNFG)”, Section 25.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 25.3.2.7, “Flash Status Register (FSTAT)”, and Section 25.3.2.8, “Flash Error Status Register (FERSTAT)”. The logic used for generating the Flash module interrupts is shown in Figure 25-27. CCIE CCIF DFDIE DFDIF Flash Command Interrupt Request Flash Error Interrupt Request SFDIE SFDIF Figure 25-27. Flash Module Interrupts Implementation MC9S12G Family Reference Manual Rev.1.28 860 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) 25.4.8 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 25.4.7, “Interrupts”). 25.4.9 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. 25.5 Security The Flash module provides security information to the MCU. The Flash security state is defined by the SEC bits of the FSEC register (see Table 25-11). During reset, the Flash module initializes the FSEC register using data read from the security byte of the Flash configuration field at global address 0x3_FF0F. The security state out of reset can be permanently changed by programming the security byte assuming that the MCU is starting from a mode where the necessary P-Flash erase and program commands are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset. The following subsections describe these security-related subjects: • Unsecuring the MCU using Backdoor Key Access • Unsecuring the MCU in Special Single Chip Mode using BDM • Mode and Security Effects on Flash Command Availability 25.5.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x3_FF00-0x3_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 25.3.2.2), the Verify Backdoor Access Key command (see Section 25.4.6.11) allows the user to present four prospective keys for comparison to the keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC register (see Table 25-11) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash memory and EEPROM memory will not be available for read access and will return invalid data. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 861 32 KByte Flash Module (S12FTMRG32K1V1) The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 25.3.2.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 25.4.6.11 2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10 The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method to re-enable the Verify Backdoor Access Key command. The security as defined in the Flash security byte (0x3_FF0F) is not changed by using the Verify Backdoor Access Key command sequence. The backdoor keys stored in addresses 0x3_FF00-0x3_FF07 are unaffected by the Verify Backdoor Access Key command sequence. The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection register, FPROT. After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is unsecured, the sector containing the Flash security byte can be erased and the Flash security byte can be reprogrammed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x3_FF00-0x3_FF07 in the Flash configuration field. 25.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM A secured MCU can be unsecured in special single chip mode by using the following method to erase the P-Flash and EEPROM memory: 1. Reset the MCU into special single chip mode 2. Delay while the BDM executes the Erase Verify All Blocks command write sequence to check if the P-Flash and EEPROM memories are erased 3. Send BDM commands to disable protection in the P-Flash and EEPROM memory 4. Execute the Erase All Blocks command write sequence to erase the P-Flash and EEPROM memory. Alternatively the Unsecure Flash command can be executed, if so the steps 5 and 6 below are skeeped. 5. After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into special single chip mode 6. Delay while the BDM executes the Erase Verify All Blocks command write sequence to verify that the P-Flash and EEPROM memory are erased If the P-Flash and EEPROM memory are verified as erased, the MCU will be unsecured. All BDM commands will now be enabled and the Flash security byte may be programmed to the unsecure state by continuing with the following steps: 7. Send BDM commands to execute the Program P-Flash command write sequence to program the Flash security byte to the unsecured state MC9S12G Family Reference Manual Rev.1.28 862 NXP Semiconductors 32 KByte Flash Module (S12FTMRG32K1V1) 8. Reset the MCU 25.5.3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 25-27. 25.6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the Flash Block Configuration Parameters, the FPROT and EEPROT protection registers, and the FOPT and FSEC registers. The initialization routine reverts to built-in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence. If a double bit fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set. CCIF is cleared throughout the initialization sequence. The Flash module holds off all CPU access for a portion of the initialization sequence. Flash reads are allowed once the hold is removed. Completion of the initialization sequence is marked by setting CCIF high which enables user commands. If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 863 32 KByte Flash Module (S12FTMRG32K1V1) MC9S12G Family Reference Manual Rev.1.28 864 NXP Semiconductors Chapter 26 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-1. Revision History Revision Number Revision Date V01.04 Sections Affected Description of Changes 17 Jun 2010 26.4.6.1/26-899 26.4.6.2/26-900 26.4.6.3/26-900 26.4.6.14/26-910 Clarify Erase Verify Commands Descriptions related to the bits MGSTAT[1:0] of the register FSTAT. V01.05 20 Aug 2010 26.4.6.2/26-900 26.4.6.12/26-907 26.4.6.13/26-909 Updated description of the commands RD1BLK, MLOADU and MLOADF V01.06 31 Jan 2011 26.3.2.9/26-882 Updated description of protection on Section 26.3.2.9 26.1 Introduction The FTMRG48K1 module implements the following: • 48Kbytes of P-Flash (Program Flash) memory • 1,536bytes of EEPROM memory The Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory contents. The user interface to the memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is written to with the command, global address, data, and any required command parameters. The memory controller must complete the execution of a command before the FCCOB register can be written to with a new command. CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 865 It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory. Simultaneous P-Flash and EEPROM operations are discussed in Section 26.4.5. Both P-Flash and EEPROM memories are implemented with Error Correction Codes (ECC) that can resolve single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read by half-phrase, only one single bit fault in an aligned 4 byte half-phrase containing the byte or word accessed will be corrected. 26.1.1 Glossary Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. EEPROM Memory — The EEPROM memory constitutes the nonvolatile memory store for data. EEPROM Sector — The EEPROM sector is the smallest portion of the EEPROM memory that can be erased. The EEPROM sector consists of 4 bytes. NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters required for Flash command execution. Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double bit fault detection within each double word. P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications. P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased. Each P-Flash sector contains 512 bytes. Program IFR — Nonvolatile information register located in the P-Flash block that contains the Version ID, and the Program Once field. 26.1.2 26.1.2.1 • • • Features P-Flash Features 48 Kbytes of P-Flash memory composed of one 48 Kbyte Flash block divided into 96 sectors of 512 bytes Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 866 48 KByte Flash Module (S12FTMRG48K1V1) • • • Fast sector erase and phrase program operation Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 26.1.2.2 • • • • • • 1.5Kbytes of EEPROM memory composed of one 1.5Kbyte Flash block divided into 384 sectors of 4 bytes Single bit fault correction and double bit fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Protection scheme to prevent accidental program or erase of EEPROM memory Ability to program up to four words in a burst sequence 26.1.2.3 • • • EEPROM Features Other Flash Module Features No external high-voltage power supply required for Flash memory program and erase operations Interrupt generation on Flash command completion and Flash error detection Security mechanism to prevent unauthorized access to the Flash memory MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 867 48 KByte Flash Module (S12FTMRG48K1V1) 26.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 26-1. Figure 26-1. FTMRG48K1 Block Diagram Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 12Kx39 sector 0 sector 1 Protection sector 95 Security Bus Clock Clock Divider FCLK Memory Controller CPU EEPROM 768x22 sector 0 sector 1 sector 383 26.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual Rev.1.28 868 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) 26.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed. If such action is attempted the write operation will not change the register value. Writing to the Flash registers is allowed when the Flash is not busy executing commands (CCIF = 1) and during initialization right after reset, despite the value of flag CCIF in that case (refer to Section 26.6 for a complete description of the reset sequence). . Table 26-2. FTMRG Memory Map Global Address (in Bytes) 0x0_0000 - 0x0_03FF 1 Size (Bytes) 1,024 Description Register Space 0x0_0400 – 0x0_09FF 1,536 EEPROM Memory 0x0_0A00 – 0x0_0BFF 512 0x0_4000 – 0x0_7FFF 16,284 NVMRES1=1 : NVM Resource area (see Figure 26-3) 0x3_0000 – 0x3_3FFF 16,384 FTMRG reserved area 0x3_4000 – 0x3_FFFF 49,152 P-Flash Memory FTMRG reserved area See NVMRES description in Section 26.4.3 26.3.1 Module Memory Map The S12 architecture places the P-Flash memory between global addresses 0x3_4000 and 0x3_FFFF as shown in Table 26-3 .The P-Flash memory map is shown in Figure 26-2. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 869 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-3. P-Flash Memory Addressing Global Address Size (Bytes) 0x3_4000 – 0x3_FFFF 48 K Description P-Flash Block Contains Flash Configuration Field (see Table 26-4). The FPROT register, described in Section 26.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. The Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 26-4. MC9S12G Family Reference Manual Rev.1.28 870 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-4. Flash Configuration Field 1 Global Address Size (Bytes) 0x3_FF00-0x3_FF07 8 Backdoor Comparison Key Refer to Section 26.4.6.11, “Verify Backdoor Access Key Command,” and Section 26.5.1, “Unsecuring the MCU using Backdoor Key Access” 0x3_FF08-0x3_FF0B1 4 Reserved 0x3_FF0C1 1 P-Flash Protection byte. Refer to Section 26.3.2.9, “P-Flash Protection Register (FPROT)” 0x3_FF0D1 1 EEPROM Protection byte. Refer to Section 26.3.2.10, “EEPROM Protection Register (EEPROT)” 0x3_FF0E1 1 Flash Nonvolatile byte Refer to Section 26.3.2.16, “Flash Option Register (FOPT)” 0x3_FF0F1 1 Flash Security byte Refer to Section 26.3.2.2, “Flash Security Register (FSEC)” Description 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B reserved field should be programmed to 0xFF. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 871 48 KByte Flash Module (S12FTMRG48K1V1) Figure 26-2. P-Flash Memory Map P-Flash START = 0x3_4000 Flash Protected/Unprotected Region 16 Kbytes 0x3_8000 0x3_8400 0x3_8800 0x3_9000 Protection Fixed End Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x3_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) Protection Movable End 0x3_C000 Protection Fixed End 0x3_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 P-Flash END = 0x3_FFFF Flash Configuration Field 16 bytes (0x3_FF00 - 0x3_FF0F) Table 26-5. Program IFR Fields 1 Global Address Size (Bytes) 0x0_4000 – 0x0_4007 8 Reserved 0x0_4008 – 0x0_40B5 174 Reserved 0x0_40B6 – 0x0_40B7 2 Version ID1 0x0_40B8 – 0x0_40BF 8 Reserved 0x0_40C0 – 0x0_40FF 64 Program Once Field Refer to Section 26.4.6.6, “Program Once Command” Field Description Used to track firmware patch versions, see Section 26.4.2 MC9S12G Family Reference Manual Rev.1.28 872 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-6. Memory Controller Resource Fields (NVMRES1=1) Global Address Size (Bytes) 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 26-5) 0x0_4100 – 0x0_41FF 256 Reserved. 0x0_4200 – 0x0_57FF 1 Description Reserved 0x0_5800 – 0x0_59FF 512 Reserved 0x0_5A00 – 0x0_5FFF 1,536 Reserved 0x0_6000 – 0x0_6BFF 3,072 Reserved 0x0_6C00 – 0x0_7FFF 5,120 Reserved NVMRES - See Section 26.4.3 for NVMRES (NVM Resource) detail. 0x0_4000 0x0_4400 RAM Start = 0x0_5800 RAM End = 0x0_59FF P-Flash IFR 1 Kbyte (NVMRES=1) Reserved 5k bytes Reserved 512 bytes Reserved 4608 bytes 0x0_6C00 Reserved 5120 bytes 0x0_7FFF Figure 26-3. Memory Controller Resource Memory Map (NVMRES=1) 26.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 26.3). MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 873 48 KByte Flash Module (S12FTMRG48K1V1) A summary of the Flash module registers is given in Figure 26-4 with detailed descriptions in the following subsections. Address & Name 0x0000 FCLKDIV 0x0001 FSEC 0x0002 FCCOBIX 0x0003 FRSV0 0x0004 FCNFG 0x0005 FERCNFG 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 EEPROT 0x000A FCCOBHI 0x000B FCCOBLO 0x000C FRSV1 7 R 6 5 4 3 2 1 0 FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0 0 0 0 0 0 0 0 0 0 0 0 0 FDFD FSFD 0 0 0 0 0 DFDIE SFDIE ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0 0 0 0 0 DFDIF SFDIF FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 DPS5 DPS4 DPS3 DPS2 DPS1 DPS0 FDIVLD W R W R W R W R W R CCIE 0 IGNSF W R W R CCIF 0 0 0 W R W R W R W R W R FPOPEN DPOPEN RNV6 0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0 0 0 0 0 0 0 0 W Figure 26-4. FTMRG48K1 Register Summary MC9S12G Family Reference Manual Rev.1.28 874 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) Address & Name 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT 0x0011 FRSV5 0x0012 FRSV6 0x0013 FRSV7 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W R W R W R W R W = Unimplemented or Reserved Figure 26-4. FTMRG48K1 Register Summary (continued) 26.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Offset Module Base + 0x0000 7 R FDIVLD W Reset 0 6 5 4 3 FDIVLCK 0 2 1 0 0 0 0 FDIV[5:0] 0 0 0 = Unimplemented or Reserved Figure 26-5. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 875 48 KByte Flash Module (S12FTMRG48K1V1) CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). Table 26-7. FCLKDIV Field Descriptions Field 7 FDIVLD Description Clock Divider Loaded 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset 6 FDIVLCK Clock Divider Locked 0 FDIV field is open for writing 1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in normal mode. 5–0 FDIV[5:0] Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events during Flash program and erase algorithms. Table 26-8 shows recommended values for FDIV[5:0] based on the BUSCLK frequency. Please refer to Section 26.4.4, “Flash Command Operations,” for more information. Table 26-8. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) 1 2 MIN1 MAX2 1.0 1.6 1.6 FDIV[5:0] BUSCLK Frequency (MHz) FDIV[5:0] MIN1 MAX2 0x00 16.6 17.6 0x10 2.6 0x01 17.6 18.6 0x11 2.6 3.6 0x02 18.6 19.6 0x12 3.6 4.6 0x03 19.6 20.6 0x13 4.6 5.6 0x04 20.6 21.6 0x14 5.6 6.6 0x05 21.6 22.6 0x15 6.6 7.6 0x06 22.6 23.6 0x16 7.6 8.6 0x07 23.6 24.6 0x17 8.6 9.6 0x08 24.6 25.6 0x18 9.6 10.6 0x09 10.6 11.6 0x0A 11.6 12.6 0x0B 12.6 13.6 0x0C 13.6 14.6 0x0D 14.6 15.6 0x0E 15.6 16.6 0x0F BUSCLK is Greater Than this value. BUSCLK is Less Than or Equal to this value. MC9S12G Family Reference Manual Rev.1.28 876 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) 26.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 26-6. Flash Security Register (FSEC) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FSEC register are readable but not writable. During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the Flash configuration field at global address 0x3_FF0F located in P-Flash memory (see Table 26-4) as indicated by reset condition F in Figure 26-6. If a double bit fault is detected while reading the P-Flash phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set to leave the Flash module in a secured state with backdoor key access disabled. Table 26-9. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the KEYEN[1:0] Flash module as shown in Table 26-10. 5–2 RNV[5:2] Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements. 1–0 SEC[1:0] Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 26-11. If the Flash module is unsecured using backdoor key access, the SEC bits are forced to 10. Table 26-10. Flash KEYEN States 1 KEYEN[1:0] Status of Backdoor Key Access 00 DISABLED 01 DISABLED1 10 ENABLED 11 DISABLED Preferred KEYEN state to disable backdoor key access. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 877 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-11. Flash Security States 1 SEC[1:0] Status of Security 00 SECURED 01 SECURED1 10 UNSECURED 11 SECURED Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 26.5. 26.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations. Offset Module Base + 0x0002 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 CCOBIX[2:0] W Reset 1 0 0 0 = Unimplemented or Reserved Figure 26-7. FCCOB Index Register (FCCOBIX) CCOBIX bits are readable and writable while remaining bits read 0 and are not writable. Table 26-12. FCCOBIX Field Descriptions Field Description 2–0 CCOBIX[1:0] Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to. See 26.3.2.11 Flash Common Command Object Register (FCCOB),” for more details. 26.3.2.4 Flash Reserved0 Register (FRSV0) This Flash register is reserved for factory testing. Offset Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 26-8. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.28 878 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) 26.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU. Offset Module Base + 0x0004 7 R W Reset CCIE 0 6 5 0 0 0 0 4 IGNSF 0 3 2 0 0 0 0 1 0 FDFD FSFD 0 0 = Unimplemented or Reserved Figure 26-9. Flash Configuration Register (FCNFG) CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not writable. Table 26-13. FCNFG Field Descriptions Field Description 7 CCIE Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command has completed. 0 Command complete interrupt disabled 1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 26.3.2.7) 4 IGNSF Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see Section 26.3.2.8). 0 All single bit faults detected during array reads are reported 1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated 1 FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. 0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected 1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see Section 26.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG register is set (see Section 26.3.2.6) 0 FSFD Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. 0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected 1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 26.3.2.7) and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see Section 26.3.2.6) 26.3.2.6 Flash Error Configuration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 879 48 KByte Flash Module (S12FTMRG48K1V1) Offset Module Base + 0x0005 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDIE SFDIE 0 0 = Unimplemented or Reserved Figure 26-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. Table 26-14. FERCNFG Field Descriptions Field Description 1 DFDIE Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation. 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set (see Section 26.3.2.8) 0 SFDIE Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault is detected during a Flash block read operation. 0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 26.3.2.8) 1 An interrupt will be requested whenever the SFDIF flag is set (see Section 26.3.2.8) 26.3.2.7 Flash Status Register (FSTAT) The FSTAT register reports the operational status of the Flash module. Offset Module Base + 0x0006 7 R W Reset CCIF 1 6 0 0 5 4 ACCERR FPVIOL 0 0 3 2 MGBUSY RSVD 0 0 1 0 MGSTAT[1:0] 01 01 = Unimplemented or Reserved Figure 26-11. Flash Status Register (FSTAT) 1 Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 26.6). CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.28 880 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation. 0 Flash command in progress 1 Flash command has completed 5 ACCERR Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory caused by either a violation of the command write sequence (see Section 26.4.4.2) or issuing an illegal Flash command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR. 0 No access error detected 1 Access error detected 4 FPVIOL Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of P-Flash or EEPROM memory during a command write sequence. The FPVIOL bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected 1 Protection violation detected 3 MGBUSY 2 RSVD Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller. 0 Memory Controller is idle 1 Memory Controller is busy executing a Flash command (CCIF = 0) Reserved Bit — This bit is reserved and always reads 0. 1–0 Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See Section 26.4.6, “Flash Command Description,” and Section 26.6, “Initialization” for details. 26.3.2.8 Flash Error Status Register (FERSTAT) The FERSTAT register reflects the error status of internal Flash operations. Offset Module Base + 0x0007 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDIF SFDIF 0 0 = Unimplemented or Reserved Figure 26-12. Flash Error Status Register (FERSTAT) All flags in the FERSTAT register are readable and only writable to clear the flag. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 881 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The DFDIF flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.2 0 No double bit fault detected 1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command running 0 SFDIF Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF. 0 No single bit fault detected 1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted while command running 1 The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either single fault or double fault but never both). A simultaneous access collision (Flash array read operation returning invalid data attempted while command running) is indicated when both SFDIF and DFDIF flags are high. 2 There is a one cycle delay in storing the ECC DFDIF and SFDIF fault flags in this register. At least one NOP is required after a flash memory read before checking FERSTAT for the occurrence of ECC errors. 26.3.2.9 P-Flash Protection Register (FPROT) The FPROT register defines which P-Flash sectors are protected against program and erase operations. Offset Module Base + 0x0008 7 R W Reset FPOPEN F1 6 5 RNV6 F1 4 FPHDIS F1 3 FPHS[1:0] F1 2 1 FPLDIS F1 F1 0 FPLS[1:0] F1 F1 = Unimplemented or Reserved Figure 26-13. Flash Protection Register (FPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected region can only be increased (see Section 26.3.2.9.1, “P-Flash Protection Restrictions,” and Table 26-21). During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte in the Flash configuration field at global address 0x3_FF0C located in P-Flash memory (see Table 26-4) as indicated by reset condition ‘F’ in Figure 26-13. To change the P-Flash protection that will be loaded during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected. MC9S12G Family Reference Manual Rev.1.28 882 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. Table 26-17. FPROT Field Descriptions Field Description 7 FPOPEN Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or erase operations as shown in Table 26-18 for the P-Flash block. 0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits 1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits 6 RNV[6] Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements. 5 FPHDIS Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory ending with global address 0x3_FFFF. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 4–3 FPHS[1:0] Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area in P-Flash memory as shown inTable 26-19. The FPHS bits can only be written to while the FPHDIS bit is set. 2 FPLDIS Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory beginning with global address 0x3_8000. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 1–0 FPLS[1:0] Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area in P-Flash memory as shown in Table 26-20. The FPLS bits can only be written to while the FPLDIS bit is set. Table 26-18. P-Flash Protection Function 1 Function1 FPOPEN FPHDIS FPLDIS 1 1 1 No P-Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P-Flash Memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges For range sizes, refer to Table 26-19 and Table 26-20. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 883 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-19. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 00 0x3_F800–0x3_FFFF 2 Kbytes 01 0x3_F000–0x3_FFFF 4 Kbytes 10 0x3_E000–0x3_FFFF 8 Kbytes 11 0x3_C000–0x3_FFFF 16 Kbytes Table 26-20. P-Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 00 0x3_8000–0x3_83FF 1 Kbyte 01 0x3_8000–0x3_87FF 2 Kbytes 10 0x3_8000–0x3_8FFF 4 Kbytes 11 0x3_8000–0x3_9FFF 8 Kbytes All possible P-Flash protection scenarios are shown in Figure 26-14 . Although the protection scheme is loaded from the Flash memory at global address 0x3_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12G Family Reference Manual Rev.1.28 884 NXP Semiconductors FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 0x3_8000 Scenario FLASH START FPLS[1:0] 0x3_FFFF FPHS[1:0] 0x3_8000 FPOPEN = 0 FPHDIS = 0 FPLDIS = 1 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 48 KByte Flash Module (S12FTMRG48K1V1) 0x3_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 26-14. P-Flash Protection Scenarios MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 885 48 KByte Flash Module (S12FTMRG48K1V1) 26.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 26-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 26-21. P-Flash Protection Scenario Transitions To Protection Scenario1 From Protection Scenario 0 1 2 3 0 X X X X X 1 X 4 X X X X X X X X X X 6 X 7 1 X 6 7 X 3 5 5 X X 2 4 X X X X X X Allowed transitions marked with X, see Figure 26-14 for a definition of the scenarios. 26.3.2.10 EEPROM Protection Register (EEPROT) The EEPROT register defines which EEPROM sectors are protected against program and erase operations. Offset Module Base + 0x0009 7 R W Reset DPOPEN F1 6 5 4 3 0 0 2 1 0 F1 F1 F1 DPS[5:0] F1 F1 F1 = Unimplemented or Reserved Figure 26-15. EEPROM Protection Register (EEPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the EEPROT register are writable with the restriction that protection can be added but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1 (protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is irrelevant. MC9S12G Family Reference Manual Rev.1.28 886 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in P-Flash memory (see Table 26-4) as indicated by reset condition F in Table 26-23. To change the EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase containing the EEPROM protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the EEPROM memory fully protected. Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. Block erase of the EEPROM memory is not possible if any of the EEPROM sectors are protected. Table 26-22. EEPROT Field Descriptions Field Description 7 DPOPEN EEPROM Protection Control 0 Enables EEPROM memory protection from program and erase with protected address range defined by DPS bits 1 Disables EEPROM memory protection from program and erase 5–0 DPS[5:0] EEPROM Protection Size — The DPS[5:0] bits determine the size of the protected area in the EEPROM memory as shown in Table 26-23 . Table 26-23. EEPROM Protection Address Range DPS[5:0] Global Address Range Protected Size 000000 0x0_0400 – 0x0_041F 32 bytes 000001 0x0_0400 – 0x0_043F 64 bytes 000010 0x0_0400 – 0x0_045F 96 bytes 000011 0x0_0400 – 0x0_047F 128 bytes 000100 0x0_0400 – 0x0_049F 160 bytes 000101 0x0_0400 – 0x0_04BF 192 bytes The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increasing of one. . . . 101111 - to - 111111 0x0_0400 – 0x0_09FF 1,536 bytes MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 887 48 KByte Flash Module (S12FTMRG48K1V1) 26.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. Offset Module Base + 0x000A 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[15:8] W Reset 3 0 0 0 0 Figure 26-16. Flash Common Command Object High Register (FCCOBHI) Offset Module Base + 0x000B 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[7:0] W Reset 3 0 0 0 0 Figure 26-17. Flash Common Command Object Low Register (FCCOBLO) 26.3.2.11.1 FCCOB - NVM Command Mode NVM command mode uses the indexed FCCOB register to provide a command code and its relevant parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes (as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array. The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 26-24. The return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller. Writes to the unimplemented parameter fields (CCOBIX = 110 and CCOBIX = 111) are ignored with reads from these fields returning 0x0000. Table 26-24 shows the generic Flash command format. The high byte of the first word in the CCOB array contains the command code, followed by the parameters for this specific Flash command. For details on the FCCOB settings required by each command, see the Flash command descriptions in Section 26.4.6. Table 26-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] 000 001 Byte FCCOB Parameter Fields (NVM Command Mode) HI FCMD[7:0] defining Flash command LO 6’h0, Global address [17:16] HI Global address [15:8] LO Global address [7:0] MC9S12G Family Reference Manual Rev.1.28 888 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] 010 011 100 101 Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 0 [15:8] LO Data 0 [7:0] HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 26.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing. Offset Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 26-18. Flash Reserved1 Register (FRSV1) All bits in the FRSV1 register read 0 and are not writable. 26.3.2.13 Flash Reserved2 Register (FRSV2) This Flash register is reserved for factory testing. Offset Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 26-19. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. 26.3.2.14 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 889 48 KByte Flash Module (S12FTMRG48K1V1) Offset Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 26-20. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 26.3.2.15 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing. Offset Module Base + 0x000F R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 26-21. Flash Reserved4 Register (FRSV4) All bits in the FRSV4 register read 0 and are not writable. 26.3.2.16 Flash Option Register (FOPT) The FOPT register is the Flash option register. Offset Module Base + 0x0010 7 6 5 4 R 3 2 1 0 F1 F1 F1 F1 NV[7:0] W Reset F1 F1 F1 F1 = Unimplemented or Reserved Figure 26-22. Flash Option Register (FOPT) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FOPT register are readable but are not writable. During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global address 0x3_FF0E located in P-Flash memory (see Table 26-4) as indicated by reset condition F in Figure 26-22. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. MC9S12G Family Reference Manual Rev.1.28 890 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-25. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits. 26.3.2.17 Flash Reserved5 Register (FRSV5) This Flash register is reserved for factory testing. Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 26-23. Flash Reserved5 Register (FRSV5) All bits in the FRSV5 register read 0 and are not writable. 26.3.2.18 Flash Reserved6 Register (FRSV6) This Flash register is reserved for factory testing. Offset Module Base + 0x0012 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 26-24. Flash Reserved6 Register (FRSV6) All bits in the FRSV6 register read 0 and are not writable. 26.3.2.19 Flash Reserved7 Register (FRSV7) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 891 48 KByte Flash Module (S12FTMRG48K1V1) Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 26-25. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. 26.4 26.4.1 Functional Description Modes of Operation The FTMRG48K1 module provides the modes of operation normal and special . The operating mode is determined by module-level inputs and affects the FCLKDIV, FCNFG, and EEPROT registers (see Table 26-27). 26.4.2 IFR Version ID Word The version ID word is stored in the IFR at address 0x0_40B6. The contents of the word are defined in Table 26-26. Table 26-26. IFR Version ID Fields [15:4] [3:0] Reserved VERNUM MC9S12G Family Reference Manual Rev.1.28 892 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) • VERNUM: Version number. The first version is number 0b_0001 with both 0b_0000 and 0b_1111 meaning ‘none’. 26.4.3 Internal NVM resource (NVMRES) IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown in Table 26-5. The NVMRES global address map is shown in Table 26-6. 26.4.4 Flash Command Operations Flash command operations are used to modify Flash memory contents. The next sections describe: • How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from BUSCLK for Flash program and erase command operations • The command write sequence used to set Flash command parameters and launch execution • Valid Flash commands available for execution, according to MCU functional mode and MCU security state. 26.4.4.1 Writing the FCLKDIV Register Prior to issuing any Flash program or erase command after a reset, the user is required to write the FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz. Table 26-8 shows recommended values for the FDIV field based on BUSCLK frequency. NOTE Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash memory due to overstress. Setting FDIV too low can result in incomplete programming or erasure of the Flash memory cells. When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written, any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set. 26.4.4.2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see Section 26.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence. If CCIF is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the FCCOB register are ignored. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 893 48 KByte Flash Module (S12FTMRG48K1V1) 26.4.4.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 26.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag will remain clear until the Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 26-26. MC9S12G Family Reference Manual Rev.1.28 894 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no yes FCCOB Availability Check CCIF Set? Read: FSTAT register yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load. Write to FCCOB register to load required command parameter. More Parameters? yes no Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 26-26. Generic Flash Command Write Sequence Flowchart MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 895 48 KByte Flash Module (S12FTMRG48K1V1) 26.4.4.3 Valid Flash Module Commands Table 26-27 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 26-27. Flash Commands by Mode and Security State Unsecured FCMD Command Secured NS1 SS2 NS3 SS4 0x01 Erase Verify All Blocks     0x02 Erase Verify Block     0x03 Erase Verify P-Flash Section    0x04 Read Once    0x06 Program P-Flash    0x07 Program Once    0x08 Erase All Blocks 0x09 Erase Flash Block    0x0A Erase P-Flash Sector    0x0B Unsecure Flash 0x0C Verify Backdoor Access Key  0x0D Set User Margin Level  0x0E Set Field Margin Level 0x10 Erase Verify EEPROM Section    0x11 Program EEPROM    0x12 Erase EEPROM Sector            1 Unsecured Normal Single Chip mode Unsecured Special Single Chip mode. 3 Secured Normal Single Chip mode. 4 Secured Special Single Chip mode. 2 26.4.4.4 P-Flash Commands Table 26-28 summarizes the valid P-Flash commands along with the effects of the commands on the P-Flash block and other resources within the Flash module. Table 26-28. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks Function on P-Flash Memory Verify that all P-Flash (and EEPROM) blocks are erased. MC9S12G Family Reference Manual Rev.1.28 896 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-28. P-Flash Commands FCMD Command 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a P-Flash (or EEPROM) block. An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. 0x0A Erase P-Flash Sector 0x0B Unsecure Flash 0x0C Verify Backdoor Access Key Supports a method of releasing MCU security by verifying a set of security keys. 0x0D Set User Margin Level Specifies a user margin read level for all P-Flash blocks. 0x0E Set Field Margin Level Specifies a field margin read level for all P-Flash blocks (special modes only). 26.4.4.5 Function on P-Flash Memory Verify that a P-Flash block is erased. Verify that a given number of words starting at the address provided are erased. Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block that was previously programmed using the Program Once command. Program a phrase in a P-Flash block. Erase all bytes in a P-Flash sector. Supports a method of releasing MCU security by erasing all P-Flash (and EEPROM) blocks and verifying that all P-Flash (and EEPROM) blocks are erased. EEPROM Commands Table 26-29 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. Table 26-29. EEPROM Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block Function on EEPROM Memory Verify that all EEPROM (and P-Flash) blocks are erased. Verify that the EEPROM block is erased. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 897 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-29. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block. An erase of the full EEPROM block is only possible when DPOPEN bit in the EEPROT register is set prior to launching the command. 0x0B Unsecure Flash 0x0D Set User Margin Level Specifies a user margin read level for the EEPROM block. 0x0E Set Field Margin Level Specifies a field margin read level for the EEPROM block (special modes only). 0x10 Erase Verify EEPROM Section Verify that a given number of words starting at the address provided are erased. 0x11 Program EEPROM Program up to four words in the EEPROM block. 0x12 Erase EEPROM Sector Erase all bytes in a sector of the EEPROM block. 26.4.5 Supports a method of releasing MCU security by erasing all EEPROM (and P-Flash) blocks and verifying that all EEPROM (and P-Flash) blocks are erased. Allowed Simultaneous P-Flash and EEPROM Operations Only the operations marked ‘OK’ in Table 26-30 are permitted to be run simultaneously on the Program Flash and EEPROM blocks. Some operations cannot be executed simultaneously because certain hardware resources are shared by the two memories. The priority has been placed on permitting Program Flash reads while program and erase operations execute on the EEPROM, providing read (P-Flash) while write (EEPROM) functionality. Table 26-30. Allowed P-Flash and EEPROM Simultaneous Operations EEPROM Program Flash Read Read Margin Read1 Program Sector Erase OK OK OK Mass Erase2 Margin Read1 Program Sector Erase Mass Erase2 OK 1 A ‘Margin Read’ is any read after executing the margin setting commands ‘Set User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified. See the Note on margin settings in Section 26.4.6.12 and Section 26.4.6.13. 2 The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ MC9S12G Family Reference Manual Rev.1.28 898 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) 26.4.6 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence. The ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be processed by the Memory Controller: • Starting any command write sequence that programs or erases Flash memory before initializing the FCLKDIV register • Writing an invalid command as part of the command write sequence • For additional possible errors, refer to the error handling table provided for each command If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation will return invalid data if both flags SFDIF and DFDIF are set. If the SFDIF or DFDIF flags were not previously set when the invalid read operation occurred, both the SFDIF and DFDIF flags will be set. If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting any command write sequence (see Section 26.3.2.7). CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. 26.4.6.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and EEPROM blocks have been erased. Table 26-31. Erase Verify All Blocks Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x01 Not required Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks operation has completed. If all blocks are not erased, it means blank check failed, both MGSTAT bits will be set. Table 26-32. Erase Verify All Blocks Command Error Handling Register Error Bit ACCERR FPVIOL FSTAT Error Condition Set if CCOBIX[2:0] != 000 at command launch None MGSTAT1 Set if any errors have been encountered during the reador if blank check failed . MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 899 48 KByte Flash Module (S12FTMRG48K1V1) 26.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0] bits determine which block must be verified. Table 26-33. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. See Table 26-34 Table 26-34. Flash block selection code description Selection code[1:0] Flash block to be verified 00 EEPROM 01 Invalid (ACCERR) 10 Invalid (ACCERR) 11 P-Flash Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that the selected P-Flash or EEPROM block is erased. The CCIF flag will set after the Erase Verify Block operation has completed.If the block is not erased, it means blank check failed, both MGSTAT bits will be set. Table 26-35. Erase Verify Block Command Error Handling Register Error Bit ACCERR FSTAT 26.4.6.3 FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if an invalid FlashBlockSelectionCode[1:0] is supplied None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. Erase Verify P-Flash Section Command The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. MC9S12G Family Reference Manual Rev.1.28 900 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-36. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. Table 26-37. Erase Verify P-Flash Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 26-27) ACCERR Set if an invalid global address [17:0] is supplied see Table 26-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT Set if the requested section crosses a the P-Flash address boundary FPVIOL 26.4.6.4 None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. Read Once Command The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of P-Flash. The Read Once field is programmed using the Program Once command described in Section 26.4.6.6. The Read Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 26-38. Read Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x04 Not Required 001 Read Once phrase index (0x0000 - 0x0007) 010 Read Once word 0 value 011 Read Once word 1 value 100 Read Once word 2 value 101 Read Once word 3 value MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 901 48 KByte Flash Module (S12FTMRG48K1V1) Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. 8 Table 26-39. Read Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if an invalid phrase index is supplied FSTAT 26.4.6.5 Set if command not available in current mode (see Table 26-27) FPVIOL None MGSTAT1 Set if any errors have been encountered during the read MGSTAT0 Set if any non-correctable errors have been encountered during the read Program P-Flash Command The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an embedded algorithm. CAUTION A P-Flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash phrase is not allowed. Table 26-40. Program P-Flash Command FCCOB Requirements CCOBIX[2:0] 000 1 FCCOB Parameters 0x06 Global address [17:16] to identify P-Flash block 001 Global address [15:0] of phrase location to be programmed1 010 Word 0 program value 011 Word 1 program value 100 Word 2 program value 101 Word 3 program value Global address [2:0] must be 000 Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. The CCIF flag will set after the Program P-Flash operation has completed. MC9S12G Family Reference Manual Rev.1.28 902 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-41. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid global address [17:0] is supplied see Table 26-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 26.4.6.6 Set if command not available in current mode (see Table 26-27) Set if the global address [17:0] points to a protected area MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Program Once Command The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in P-Flash. The Program Once reserved field can be read using the Read Once command as described in Section 26.4.6.4. The Program Once command must only be issued once since the nonvolatile information register in P-Flash cannot be erased. The Program Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 26-42. Program Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x07 Not Required 001 Program Once phrase index (0x0000 - 0x0007) 010 Program Once word 0 value 011 Program Once word 1 value 100 Program Once word 2 value 101 Program Once word 3 value Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with read back. The CCIF flag will remain clear, setting only after the Program Once operation has completed. The reserved nonvolatile information register accessed by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 903 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-43. Program Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed1 FSTAT FPVIOL 1 Set if command not available in current mode (see Table 26-27) None MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will be allowed to execute again on that same phrase. 26.4.6.7 Erase All Blocks Command The Erase All Blocks operation will erase the entire P-Flash and EEPROM memory space. Table 26-44. Erase All Blocks Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x08 Not required Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All Blocks operation has completed. Table 26-45. Erase All Blocks Command Error Handling Register Error Bit ACCERR FSTAT 26.4.6.8 FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 26-27) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or EEPROM block. MC9S12G Family Reference Manual Rev.1.28 904 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-46. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 26-47. Erase Flash Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 26-27) ACCERR Set if the supplied P-Flash address is not phrase-aligned or if the EEPROM address is not word-aligned FSTAT FPVIOL 26.4.6.9 Set if an invalid global address [17:16] is supplied Set if an area of the selected Flash block is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Erase P-Flash Sector Command The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector. Table 26-48. Erase P-Flash Sector Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x0A Global address [17:16] to identify P-Flash block to be erased Global address [15:0] anywhere within the sector to be erased. Refer to Section 26.1.2.1 for the P-Flash sector size. Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 905 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-49. Erase P-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if command not available in current mode (see Table 26-27) Set if an invalid global address [17:16] is supplied see Table 26-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL Set if the selected P-Flash sector is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 26.4.6.10 Unsecure Flash Command The Unsecure Flash command will erase the entire P-Flash and EEPROM memory space and, if the erase is successful, will release security. Table 26-50. Unsecure Flash Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x0B Not required Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire P-Flash and EEPROM memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. If the erase verify is not successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security state. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag is set after the Unsecure Flash operation has completed. Table 26-51. Unsecure Flash Command Error Handling Register Error Bit ACCERR FSTAT FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 26-27) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 26.4.6.11 Verify Backdoor Access Key Command The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 26-10). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see MC9S12G Family Reference Manual Rev.1.28 906 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-4). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 26-52. Verify Backdoor Access Key Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0C Not required 001 Key 0 010 Key 1 011 Key 2 100 Key 3 Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash configuration field with Key 0 compared to 0x3_FF00, etc. If the backdoor keys match, security will be released. If the backdoor keys do not match, security is not released and all future attempts to execute the Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is set after the Verify Backdoor Access Key operation has completed. Table 26-53. Verify Backdoor Access Key Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 100 at command launch Set if an incorrect backdoor key is supplied ACCERR FSTAT Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see Section 26.3.2.2) Set if the backdoor key has mismatched since the last reset FPVIOL None MGSTAT1 None MGSTAT0 None 26.4.6.12 Set User Margin Level Command The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P-Flash or EEPROM block. Table 26-54. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x0D Flash block selection code [1:0]. See Margin level setting. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 907 48 KByte Flash Module (S12FTMRG48K1V1) Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply user margin levels to the P-Flash block only. Valid margin level settings for the Set User Margin Level command are defined in Table 26-55. Table 26-55. Valid Set User Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state Table 26-56. Set User Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR FSTAT Set if command not available in current mode (see Table 26-27) Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 26-34 ) Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None NOTE User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. MC9S12G Family Reference Manual Rev.1.28 908 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) 26.4.6.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of the P-Flash or EEPROM block. Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the Table 26-57. Set Field Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0E 001 Flash block selection code [1:0]. Table 26-34 See Margin level setting. field margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM field margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash field margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply field margin levels to the P-Flash block only. Valid margin level settings for the Set Field Margin Level command are defined in Table 26-58. Table 26-58. Valid Set Field Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 0x0003 Field Margin-1 Level1 0x0004 Field Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 909 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-59. Set Field Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR FSTAT Set if command not available in current mode (see Table 26-27) Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 26-34 ) Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None CAUTION Field margin levels must only be used during verify of the initial factory programming. NOTE Field margin levels can be used to check that Flash memory contents have adequate margin for data retention at the normal level setting. If unexpected results are encountered when checking Flash memory contents at field margin levels, the Flash memory contents should be erased and reprogrammed. 26.4.6.14 Erase Verify EEPROM Section Command The Erase Verify EEPROM Section command will verify that a section of code in the EEPROM is erased. The Erase Verify EEPROM Section command defines the starting point of the data to be verified and the number of words. Table 26-60. Erase Verify EEPROM Section Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x10 Global address [17:16] to identify the EEPROM block 001 Global address [15:0] of the first word to be verified 010 Number of words to be verified Upon clearing CCIF to launch the Erase Verify EEPROM Section command, the Memory Controller will verify the selected section of EEPROM memory is erased. The CCIF flag will set after the Erase Verify EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12G Family Reference Manual Rev.1.28 910 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-61. Erase Verify EEPROM Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 26-27) ACCERR Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested section breaches the end of the EEPROM block FPVIOL None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. 26.4.6.15 Program EEPROM Command The Program EEPROM operation programs one to four previously erased words in the EEPROM block. The Program EEPROM operation will confirm that the targeted location(s) were successfully programmed upon completion. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Table 26-62. Program EEPROM Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x11 Global address [17:16] to identify the EEPROM block 001 Global address [15:0] of word to be programmed 010 Word 0 program value 011 Word 1 program value, if desired 100 Word 2 program value, if desired 101 Word 3 program value, if desired Upon clearing CCIF to launch the Program EEPROM command, the user-supplied words will be transferred to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program EEPROM command launch determines how many words will be programmed in the EEPROM block. The CCIF flag is set when the operation has completed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 911 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-63. Program EEPROM Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] < 010 at command launch Set if CCOBIX[2:0] > 101 at command launch ACCERR Set if command not available in current mode (see Table 26-27) Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested group of words breaches the end of the EEPROM block FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 26.4.6.16 Erase EEPROM Sector Command The Erase EEPROM Sector operation will erase all addresses in a sector of the EEPROM block. Table 26-64. Erase EEPROM Sector Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x12 Global address [17:16] to identify EEPROM block Global address [15:0] anywhere within the sector to be erased. See Section 26.1.2.2 for EEPROM sector size. Upon clearing CCIF to launch the Erase EEPROM Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase EEPROM Sector operation has completed. Table 26-65. Erase EEPROM Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if command not available in current mode (see Table 26-27) Set if an invalid global address [17:0] is suppliedsee Table 26-3) Set if a misaligned word address is supplied (global address [0] != 0) FSTAT FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation MC9S12G Family Reference Manual Rev.1.28 912 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) 26.4.7 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 26-66. Flash Interrupt Sources Interrupt Source Global (CCR) Mask Interrupt Flag Local Enable CCIF (FSTAT register) CCIE (FCNFG register) I Bit ECC Double Bit Fault on Flash Read DFDIF (FERSTAT register) DFDIE (FERCNFG register) I Bit ECC Single Bit Fault on Flash Read SFDIF (FERSTAT register) SFDIE (FERCNFG register) I Bit Flash Command Complete NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 26.4.7.1 Description of Flash Interrupt Operation The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed description of the register bits involved, refer to Section 26.3.2.5, “Flash Configuration Register (FCNFG)”, Section 26.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 26.3.2.7, “Flash Status Register (FSTAT)”, and Section 26.3.2.8, “Flash Error Status Register (FERSTAT)”. The logic used for generating the Flash module interrupts is shown in Figure 26-27. CCIE CCIF DFDIE DFDIF Flash Command Interrupt Request Flash Error Interrupt Request SFDIE SFDIF Figure 26-27. Flash Module Interrupts Implementation MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 913 48 KByte Flash Module (S12FTMRG48K1V1) 26.4.8 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 26.4.7, “Interrupts”). 26.4.9 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. 26.5 Security The Flash module provides security information to the MCU. The Flash security state is defined by the SEC bits of the FSEC register (see Table 26-11). During reset, the Flash module initializes the FSEC register using data read from the security byte of the Flash configuration field at global address 0x3_FF0F. The security state out of reset can be permanently changed by programming the security byte assuming that the MCU is starting from a mode where the necessary P-Flash erase and program commands are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset. The following subsections describe these security-related subjects: • Unsecuring the MCU using Backdoor Key Access • Unsecuring the MCU in Special Single Chip Mode using BDM • Mode and Security Effects on Flash Command Availability 26.5.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x3_FF00-0x3_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 26.3.2.2), the Verify Backdoor Access Key command (see Section 26.4.6.11) allows the user to present four prospective keys for comparison to the keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC register (see Table 26-11) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash memory and EEPROM memory will not be available for read access and will return invalid data. MC9S12G Family Reference Manual Rev.1.28 914 NXP Semiconductors 48 KByte Flash Module (S12FTMRG48K1V1) The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 26.3.2.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 26.4.6.11 2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10 The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method to re-enable the Verify Backdoor Access Key command. The security as defined in the Flash security byte (0x3_FF0F) is not changed by using the Verify Backdoor Access Key command sequence. The backdoor keys stored in addresses 0x3_FF00-0x3_FF07 are unaffected by the Verify Backdoor Access Key command sequence. The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection register, FPROT. After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is unsecured, the sector containing the Flash security byte can be erased and the Flash security byte can be reprogrammed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x3_FF00-0x3_FF07 in the Flash configuration field. 26.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM A secured MCU can be unsecured in special single chip mode by using the following method to erase the P-Flash and EEPROM memory: 1. Reset the MCU into special single chip mode 2. Delay while the BDM executes the Erase Verify All Blocks command write sequence to check if the P-Flash and EEPROM memories are erased 3. Send BDM commands to disable protection in the P-Flash and EEPROM memory 4. Execute the Erase All Blocks command write sequence to erase the P-Flash and EEPROM memory. Alternatively the Unsecure Flash command can be executed, if so the steps 5 and 6 below are skeeped. 5. After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into special single chip mode 6. Delay while the BDM executes the Erase Verify All Blocks command write sequence to verify that the P-Flash and EEPROM memory are erased If the P-Flash and EEPROM memory are verified as erased, the MCU will be unsecured. All BDM commands will now be enabled and the Flash security byte may be programmed to the unsecure state by continuing with the following steps: 7. Send BDM commands to execute the Program P-Flash command write sequence to program the Flash security byte to the unsecured state MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 915 48 KByte Flash Module (S12FTMRG48K1V1) 8. Reset the MCU 26.5.3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 26-27. 26.6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the Flash Block Configuration Parameters, the FPROT and EEPROT protection registers, and the FOPT and FSEC registers. The initialization routine reverts to built-in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence. If a double bit fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set. CCIF is cleared throughout the initialization sequence. The Flash module holds off all CPU access for a portion of the initialization sequence. Flash reads are allowed once the hold is removed. Completion of the initialization sequence is marked by setting CCIF high which enables user commands. If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12G Family Reference Manual Rev.1.28 916 NXP Semiconductors Chapter 27 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-1. Revision History Revision Number Revision Date V01.04 Sections Affected Description of Changes 17 Jun 2010 27.4.6.1/27-950 27.4.6.2/27-951 27.4.6.3/27-951 27.4.6.14/27-961 Clarify Erase Verify Commands Descriptions related to the bits MGSTAT[1:0] of the register FSTAT. V01.05 20 Aug 2010 27.4.6.2/27-951 27.4.6.12/27-958 27.4.6.13/27-960 Updated description of the commands RD1BLK, MLOADU and MLOADF V01.06 31 Jan 2011 27.3.2.9/27-933 Updated description of protection on Section 27.3.2.9 27.1 Introduction The FTMRG64K1 module implements the following: • 64Kbytes of P-Flash (Program Flash) memory • 2 Kbytes of EEPROM memory The Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory contents. The user interface to the memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is written to with the command, global address, data, and any required command parameters. The memory controller must complete the execution of a command before the FCCOB register can be written to with a new command. CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 917 It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory. Simultaneous P-Flash and EEPROM operations are discussed in Section 27.4.5. Both P-Flash and EEPROM memories are implemented with Error Correction Codes (ECC) that can resolve single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read by half-phrase, only one single bit fault in an aligned 4 byte half-phrase containing the byte or word accessed will be corrected. 27.1.1 Glossary Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. EEPROM Memory — The EEPROM memory constitutes the nonvolatile memory store for data. EEPROM Sector — The EEPROM sector is the smallest portion of the EEPROM memory that can be erased. The EEPROM sector consists of 4 bytes. NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters required for Flash command execution. Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double bit fault detection within each double word. P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications. P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased. Each P-Flash sector contains 512 bytes. Program IFR — Nonvolatile information register located in the P-Flash block that contains the Version ID, and the Program Once field. 27.1.2 27.1.2.1 • • • Features P-Flash Features 64 Kbytes of P-Flash memory composed of one 64 Kbyte Flash block divided into 128 sectors of 512 bytes Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 918 64 KByte Flash Module (S12FTMRG64K1V1) • • • Fast sector erase and phrase program operation Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 27.1.2.2 • • • • • • 2 Kbytes of EEPROM memory composed of one 2 Kbyte Flash block divided into 512 sectors of 4 bytes Single bit fault correction and double bit fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Protection scheme to prevent accidental program or erase of EEPROM memory Ability to program up to four words in a burst sequence 27.1.2.3 • • • EEPROM Features Other Flash Module Features No external high-voltage power supply required for Flash memory program and erase operations Interrupt generation on Flash command completion and Flash error detection Security mechanism to prevent unauthorized access to the Flash memory 27.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 27-1. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 919 64 KByte Flash Module (S12FTMRG64K1V1) Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 16Kx39 sector 0 sector 1 Protection sector 127 Security Bus Clock Clock Divider FCLK Memory Controller CPU EEPROM 1Kx22 sector 0 sector 1 sector 511 Figure 27-1. FTMRG64K1 Block Diagram 27.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual Rev.1.28 920 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) 27.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed. If such action is attempted the write operation will not change the register value. Writing to the Flash registers is allowed when the Flash is not busy executing commands (CCIF = 1) and during initialization right after reset, despite the value of flag CCIF in that case (refer to Section 27.6 for a complete description of the reset sequence). . Table 27-2. FTMRG Memory Map Global Address (in Bytes) 0x0_0000 - 0x0_03FF 1 Size (Bytes) 1,024 Description Register Space 0x0_0400 – 0x0_0BFF 2,048 EEPROM Memory 0x0_4000 – 0x0_7FFF 16,284 NVMRES1=1 : NVM Resource area (see Figure 27-3) 0x3_0000 – 0x3_FFFF 65,536 P-Flash Memory See NVMRES description in Section 27.4.3 27.3.1 Module Memory Map The S12 architecture places the P-Flash memory between global addresses 0x3_0000 and 0x3_FFFF as shown in Table 27-3.The P-Flash memory map is shown in Figure 27-2. Table 27-3. P-Flash Memory Addressing Global Address Size (Bytes) 0x3_0000 – 0x3_FFFF 64 K Description P-Flash Block Contains Flash Configuration Field (see Table 27-4) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 921 64 KByte Flash Module (S12FTMRG64K1V1) The FPROT register, described in Section 27.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. Three separate memory regions, one growing upward from global address 0x3_8000 in the Flash memory (called the lower region), one growing downward from global address 0x3_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection. The Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 27-4. Table 27-4. Flash Configuration Field 1 Global Address Size (Bytes) 0x3_FF00-0x3_FF07 8 Backdoor Comparison Key Refer to Section 27.4.6.11, “Verify Backdoor Access Key Command,” and Section 27.5.1, “Unsecuring the MCU using Backdoor Key Access” 0x3_FF08-0x3_FF0B1 4 Reserved 0x3_FF0C1 1 P-Flash Protection byte. Refer to Section 27.3.2.9, “P-Flash Protection Register (FPROT)” 0x3_FF0D1 1 EEPROM Protection byte. Refer to Section 27.3.2.10, “EEPROM Protection Register (EEPROT)” 0x3_FF0E1 1 Flash Nonvolatile byte Refer to Section 27.3.2.16, “Flash Option Register (FOPT)” 0x3_FF0F1 1 Flash Security byte Refer to Section 27.3.2.2, “Flash Security Register (FSEC)” Description 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B reserved field should be programmed to 0xFF. MC9S12G Family Reference Manual Rev.1.28 922 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) P-Flash START = 0x3_0000 Flash Protected/Unprotected Region 32 Kbytes 0x3_8000 0x3_8400 0x3_8800 0x3_9000 Protection Fixed End Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x3_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) Protection Movable End 0x3_C000 Protection Fixed End 0x3_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 P-Flash END = 0x3_FFFF Flash Configuration Field 16 bytes (0x3_FF00 - 0x3_FF0F) Figure 27-2. P-Flash Memory Map Table 27-5. Program IFR Fields 1 Global Address Size (Bytes) 0x0_4000 – 0x0_4007 8 Reserved 0x0_4008 – 0x0_40B5 174 Reserved 0x0_40B6 – 0x0_40B7 2 Version ID1 0x0_40B8 – 0x0_40BF 8 Reserved 0x0_40C0 – 0x0_40FF 64 Program Once Field Refer to Section 27.4.6.6, “Program Once Command” Field Description Used to track firmware patch versions, see Section 27.4.2 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 923 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-6. Memory Controller Resource Fields (NVMRES1=1) Global Address Size (Bytes) 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 27-5) 0x0_4100 – 0x0_41FF 256 Reserved. 0x0_4200 – 0x0_57FF 1 Description Reserved 0x0_5800 – 0x0_59FF 512 Reserved 0x0_5A00 – 0x0_5FFF 1,536 Reserved 0x0_6000 – 0x0_6BFF 3,072 Reserved 0x0_6C00 – 0x0_7FFF 5,120 Reserved NVMRES - See Section 27.4.3 for NVMRES (NVM Resource) detail. 0x0_4000 0x0_4400 RAM Start = 0x0_5800 RAM End = 0x0_59FF P-Flash IFR 1 Kbyte (NVMRES=1) Reserved 5k bytes Reserved 512 bytes Reserved 4608 bytes 0x0_6C00 Reserved 5120 bytes 0x0_7FFF Figure 27-3. Memory Controller Resource Memory Map (NVMRES=1) 27.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 27.3). MC9S12G Family Reference Manual Rev.1.28 924 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) A summary of the Flash module registers is given in Figure 27-4 with detailed descriptions in the following subsections. Address & Name 0x0000 FCLKDIV 0x0001 FSEC 0x0002 FCCOBIX 0x0003 FRSV0 0x0004 FCNFG 0x0005 FERCNFG 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 EEPROT 0x000A FCCOBHI 0x000B FCCOBLO 0x000C FRSV1 7 R 6 5 4 3 2 1 0 FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0 0 0 0 0 0 0 0 0 0 0 0 0 FDFD FSFD 0 0 0 0 0 DFDIE SFDIE ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0 0 0 0 0 DFDIF SFDIF FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 DPS5 DPS4 DPS3 DPS2 DPS1 DPS0 FDIVLD W R W R W R W R W R CCIE 0 IGNSF W R W R CCIF 0 0 0 W R W R W R W R W R FPOPEN DPOPEN RNV6 0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0 0 0 0 0 0 0 0 W Figure 27-4. FTMRG64K1 Register Summary MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 925 64 KByte Flash Module (S12FTMRG64K1V1) Address & Name 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT 0x0011 FRSV5 0x0012 FRSV6 0x0013 FRSV7 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W R W R W R W R W = Unimplemented or Reserved Figure 27-4. FTMRG64K1 Register Summary (continued) 27.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Offset Module Base + 0x0000 7 R FDIVLD W Reset 0 6 5 4 3 FDIVLCK 0 2 1 0 0 0 0 FDIV[5:0] 0 0 0 = Unimplemented or Reserved Figure 27-5. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. MC9S12G Family Reference Manual Rev.1.28 926 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). Table 27-7. FCLKDIV Field Descriptions Field 7 FDIVLD Description Clock Divider Loaded 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset 6 FDIVLCK Clock Divider Locked 0 FDIV field is open for writing 1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in normal mode. 5–0 FDIV[5:0] Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events during Flash program and erase algorithms. Table 27-8 shows recommended values for FDIV[5:0] based on the BUSCLK frequency. Please refer to Section 27.4.4, “Flash Command Operations,” for more information. Table 27-8. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) 1 2 MIN1 MAX2 1.0 1.6 1.6 FDIV[5:0] BUSCLK Frequency (MHz) FDIV[5:0] MIN1 MAX2 0x00 16.6 17.6 0x10 2.6 0x01 17.6 18.6 0x11 2.6 3.6 0x02 18.6 19.6 0x12 3.6 4.6 0x03 19.6 20.6 0x13 4.6 5.6 0x04 20.6 21.6 0x14 5.6 6.6 0x05 21.6 22.6 0x15 6.6 7.6 0x06 22.6 23.6 0x16 7.6 8.6 0x07 23.6 24.6 0x17 8.6 9.6 0x08 24.6 25.6 0x18 9.6 10.6 0x09 10.6 11.6 0x0A 11.6 12.6 0x0B 12.6 13.6 0x0C 13.6 14.6 0x0D 14.6 15.6 0x0E 15.6 16.6 0x0F BUSCLK is Greater Than this value. BUSCLK is Less Than or Equal to this value. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 927 64 KByte Flash Module (S12FTMRG64K1V1) 27.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 27-6. Flash Security Register (FSEC) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FSEC register are readable but not writable. During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the Flash configuration field at global address 0x3_FF0F located in P-Flash memory (see Table 27-4) as indicated by reset condition F in Figure 27-6. If a double bit fault is detected while reading the P-Flash phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set to leave the Flash module in a secured state with backdoor key access disabled. Table 27-9. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the KEYEN[1:0] Flash module as shown in Table 27-10. 5–2 RNV[5:2] Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements. 1–0 SEC[1:0] Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 27-11. If the Flash module is unsecured using backdoor key access, the SEC bits are forced to 10. Table 27-10. Flash KEYEN States 1 KEYEN[1:0] Status of Backdoor Key Access 00 DISABLED 01 DISABLED1 10 ENABLED 11 DISABLED Preferred KEYEN state to disable backdoor key access. MC9S12G Family Reference Manual Rev.1.28 928 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-11. Flash Security States 1 SEC[1:0] Status of Security 00 SECURED 01 SECURED1 10 UNSECURED 11 SECURED Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 27.5. 27.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations. Offset Module Base + 0x0002 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 CCOBIX[2:0] W Reset 1 0 0 0 = Unimplemented or Reserved Figure 27-7. FCCOB Index Register (FCCOBIX) CCOBIX bits are readable and writable while remaining bits read 0 and are not writable. Table 27-12. FCCOBIX Field Descriptions Field Description 2–0 CCOBIX[1:0] Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to. See 27.3.2.11 Flash Common Command Object Register (FCCOB),” for more details. 27.3.2.4 Flash Reserved0 Register (FRSV0) This Flash register is reserved for factory testing. Offset Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 27-8. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 929 64 KByte Flash Module (S12FTMRG64K1V1) 27.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU. Offset Module Base + 0x0004 7 R W Reset CCIE 0 6 5 0 0 0 0 4 IGNSF 0 3 2 0 0 0 0 1 0 FDFD FSFD 0 0 = Unimplemented or Reserved Figure 27-9. Flash Configuration Register (FCNFG) CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not writable. Table 27-13. FCNFG Field Descriptions Field Description 7 CCIE Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command has completed. 0 Command complete interrupt disabled 1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 27.3.2.7) 4 IGNSF Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see Section 27.3.2.8). 0 All single bit faults detected during array reads are reported 1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated 1 FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. 0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected 1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see Section 27.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG register is set (see Section 27.3.2.6) 0 FSFD Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. 0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected 1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 27.3.2.7) and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see Section 27.3.2.6) 27.3.2.6 Flash Error Configuration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. MC9S12G Family Reference Manual Rev.1.28 930 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) Offset Module Base + 0x0005 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDIE SFDIE 0 0 = Unimplemented or Reserved Figure 27-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. Table 27-14. FERCNFG Field Descriptions Field Description 1 DFDIE Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation. 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set (see Section 27.3.2.8) 0 SFDIE Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault is detected during a Flash block read operation. 0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 27.3.2.8) 1 An interrupt will be requested whenever the SFDIF flag is set (see Section 27.3.2.8) 27.3.2.7 Flash Status Register (FSTAT) The FSTAT register reports the operational status of the Flash module. Offset Module Base + 0x0006 7 R W Reset CCIF 1 6 0 0 5 4 ACCERR FPVIOL 0 0 3 2 MGBUSY RSVD 0 0 1 0 MGSTAT[1:0] 01 01 = Unimplemented or Reserved Figure 27-11. Flash Status Register (FSTAT) 1 Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 27.6). CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 931 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation. 0 Flash command in progress 1 Flash command has completed 5 ACCERR Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory caused by either a violation of the command write sequence (see Section 27.4.4.2) or issuing an illegal Flash command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR. 0 No access error detected 1 Access error detected 4 FPVIOL Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of P-Flash or EEPROM memory during a command write sequence. The FPVIOL bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected 1 Protection violation detected 3 MGBUSY 2 RSVD Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller. 0 Memory Controller is idle 1 Memory Controller is busy executing a Flash command (CCIF = 0) Reserved Bit — This bit is reserved and always reads 0. 1–0 Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See Section 27.4.6, “Flash Command Description,” and Section 27.6, “Initialization” for details. 27.3.2.8 Flash Error Status Register (FERSTAT) The FERSTAT register reflects the error status of internal Flash operations. Offset Module Base + 0x0007 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDIF SFDIF 0 0 = Unimplemented or Reserved Figure 27-12. Flash Error Status Register (FERSTAT) All flags in the FERSTAT register are readable and only writable to clear the flag. MC9S12G Family Reference Manual Rev.1.28 932 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The DFDIF flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.2 0 No double bit fault detected 1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command running 0 SFDIF Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF. 0 No single bit fault detected 1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted while command running 1 The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either single fault or double fault but never both). A simultaneous access collision (Flash array read operation returning invalid data attempted while command running) is indicated when both SFDIF and DFDIF flags are high. 2 There is a one cycle delay in storing the ECC DFDIF and SFDIF fault flags in this register. At least one NOP is required after a flash memory read before checking FERSTAT for the occurrence of ECC errors. 27.3.2.9 P-Flash Protection Register (FPROT) The FPROT register defines which P-Flash sectors are protected against program and erase operations. Offset Module Base + 0x0008 7 R W Reset FPOPEN F1 6 5 RNV6 F1 4 FPHDIS F1 3 FPHS[1:0] F1 2 1 FPLDIS F1 F1 0 FPLS[1:0] F1 F1 = Unimplemented or Reserved Figure 27-13. Flash Protection Register (FPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected region can only be increased (see Section 27.3.2.9.1, “P-Flash Protection Restrictions,” and Table 27-21). During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte in the Flash configuration field at global address 0x3_FF0C located in P-Flash memory (see Table 27-4) as indicated by reset condition ‘F’ in Figure 27-13. To change the P-Flash protection that will be loaded during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 933 64 KByte Flash Module (S12FTMRG64K1V1) Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. Table 27-17. FPROT Field Descriptions Field Description 7 FPOPEN Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or erase operations as shown in Table 27-18 for the P-Flash block. 0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits 1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits 6 RNV[6] Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements. 5 FPHDIS Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory ending with global address 0x3_FFFF. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 4–3 FPHS[1:0] Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area in P-Flash memory as shown inTable 27-19. The FPHS bits can only be written to while the FPHDIS bit is set. 2 FPLDIS Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory beginning with global address 0x3_8000. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 1–0 FPLS[1:0] Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area in P-Flash memory as shown in Table 27-20. The FPLS bits can only be written to while the FPLDIS bit is set. Table 27-18. P-Flash Protection Function 1 Function1 FPOPEN FPHDIS FPLDIS 1 1 1 No P-Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P-Flash Memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges For range sizes, refer to Table 27-19 and Table 27-20. MC9S12G Family Reference Manual Rev.1.28 934 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-19. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 00 0x3_F800–0x3_FFFF 2 Kbytes 01 0x3_F000–0x3_FFFF 4 Kbytes 10 0x3_E000–0x3_FFFF 8 Kbytes 11 0x3_C000–0x3_FFFF 16 Kbytes Table 27-20. P-Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 00 0x3_8000–0x3_83FF 1 Kbyte 01 0x3_8000–0x3_87FF 2 Kbytes 10 0x3_8000–0x3_8FFF 4 Kbytes 11 0x3_8000–0x3_9FFF 8 Kbytes All possible P-Flash protection scenarios are shown in Figure 27-14 . Although the protection scheme is loaded from the Flash memory at global address 0x3_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 935 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 Scenario FLASH START FPLS[1:0] 0x3_FFFF FPHS[1:0] 0x3_8000 FPOPEN = 0 0x3_8000 FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 64 KByte Flash Module (S12FTMRG64K1V1) 0x3_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 27-14. P-Flash Protection Scenarios MC9S12G Family Reference Manual Rev.1.28 936 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) 27.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 27-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 27-21. P-Flash Protection Scenario Transitions To Protection Scenario1 From Protection Scenario 0 1 2 3 0 X X X X X 1 X 4 X X X X X X X X X X 6 X 7 1 X 6 7 X 3 5 5 X X 2 4 X X X X X X Allowed transitions marked with X, see Figure 27-14 for a definition of the scenarios. 27.3.2.10 EEPROM Protection Register (EEPROT) The EEPROT register defines which EEPROM sectors are protected against program and erase operations. Offset Module Base + 0x0009 7 R W Reset DPOPEN F1 6 5 4 3 0 0 2 1 0 F1 F1 F1 DPS[5:0] F1 F1 F1 = Unimplemented or Reserved Figure 27-15. EEPROM Protection Register (EEPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the EEPROT register are writable with the restriction that protection can be added but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1 (protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is irrelevant. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 937 64 KByte Flash Module (S12FTMRG64K1V1) During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in P-Flash memory (see Table 27-4) as indicated by reset condition F in Table 27-23. To change the EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase containing the EEPROM protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the EEPROM memory fully protected. Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. Block erase of the EEPROM memory is not possible if any of the EEPROM sectors are protected. Table 27-22. EEPROT Field Descriptions Field Description 7 DPOPEN EEPROM Protection Control 0 Enables EEPROM memory protection from program and erase with protected address range defined by DPS bits 1 Disables EEPROM memory protection from program and erase 5–0 DPS[5:0] EEPROM Protection Size — The DPS[5:0] bits determine the size of the protected area in the EEPROM memory as shown in Table 27-23 . Table 27-23. EEPROM Protection Address Range DPS[5:0] Global Address Range Protected Size 000000 0x0_0400 – 0x0_041F 32 bytes 000001 0x0_0400 – 0x0_043F 64 bytes 000010 0x0_0400 – 0x0_045F 96 bytes 000011 0x0_0400 – 0x0_047F 128 bytes 000100 0x0_0400 – 0x0_049F 160 bytes 000101 0x0_0400 – 0x0_04BF 192 bytes The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increasing of one. . . . 111111 0x0_0400 – 0x0_0BFF 2,048 bytes MC9S12G Family Reference Manual Rev.1.28 938 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) 27.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. Offset Module Base + 0x000A 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[15:8] W Reset 3 0 0 0 0 Figure 27-16. Flash Common Command Object High Register (FCCOBHI) Offset Module Base + 0x000B 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[7:0] W Reset 3 0 0 0 0 Figure 27-17. Flash Common Command Object Low Register (FCCOBLO) 27.3.2.11.1 FCCOB - NVM Command Mode NVM command mode uses the indexed FCCOB register to provide a command code and its relevant parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes (as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array. The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 27-24. The return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller. Writes to the unimplemented parameter fields (CCOBIX = 110 and CCOBIX = 111) are ignored with reads from these fields returning 0x0000. Table 27-24 shows the generic Flash command format. The high byte of the first word in the CCOB array contains the command code, followed by the parameters for this specific Flash command. For details on the FCCOB settings required by each command, see the Flash command descriptions in Section 27.4.6. Table 27-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] 000 001 Byte FCCOB Parameter Fields (NVM Command Mode) HI FCMD[7:0] defining Flash command LO 6’h0, Global address [17:16] HI Global address [15:8] LO Global address [7:0] MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 939 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] 010 011 100 101 Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 0 [15:8] LO Data 0 [7:0] HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 27.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing. Offset Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 27-18. Flash Reserved1 Register (FRSV1) All bits in the FRSV1 register read 0 and are not writable. 27.3.2.13 Flash Reserved2 Register (FRSV2) This Flash register is reserved for factory testing. Offset Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 27-19. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. 27.3.2.14 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.28 940 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) Offset Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 27-20. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 27.3.2.15 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing. Offset Module Base + 0x000F R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 27-21. Flash Reserved4 Register (FRSV4) All bits in the FRSV4 register read 0 and are not writable. 27.3.2.16 Flash Option Register (FOPT) The FOPT register is the Flash option register. Offset Module Base + 0x0010 7 6 5 4 R 3 2 1 0 F1 F1 F1 F1 NV[7:0] W Reset F1 F1 F1 F1 = Unimplemented or Reserved Figure 27-22. Flash Option Register (FOPT) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FOPT register are readable but are not writable. During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global address 0x3_FF0E located in P-Flash memory (see Table 27-4) as indicated by reset condition F in Figure 27-22. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 941 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-25. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits. 27.3.2.17 Flash Reserved5 Register (FRSV5) This Flash register is reserved for factory testing. Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 27-23. Flash Reserved5 Register (FRSV5) All bits in the FRSV5 register read 0 and are not writable. 27.3.2.18 Flash Reserved6 Register (FRSV6) This Flash register is reserved for factory testing. Offset Module Base + 0x0012 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 27-24. Flash Reserved6 Register (FRSV6) All bits in the FRSV6 register read 0 and are not writable. 27.3.2.19 Flash Reserved7 Register (FRSV7) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.28 942 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 27-25. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. 27.4 27.4.1 Functional Description Modes of Operation The FTMRG64K1 module provides the modes of operation normal and special . The operating mode is determined by module-level inputs and affects the FCLKDIV, FCNFG, and EEPROT registers (see Table 27-27). 27.4.2 IFR Version ID Word The version ID word is stored in the IFR at address 0x0_40B6. The contents of the word are defined in Table 27-26. Table 27-26. IFR Version ID Fields [15:4] [3:0] Reserved VERNUM MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 943 64 KByte Flash Module (S12FTMRG64K1V1) • VERNUM: Version number. The first version is number 0b_0001 with both 0b_0000 and 0b_1111 meaning ‘none’. 27.4.3 Internal NVM resource (NVMRES) IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown in Table 27-5. The NVMRES global address map is shown in Table 27-6. 27.4.4 Flash Command Operations Flash command operations are used to modify Flash memory contents. The next sections describe: • How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from BUSCLK for Flash program and erase command operations • The command write sequence used to set Flash command parameters and launch execution • Valid Flash commands available for execution, according to MCU functional mode and MCU security state. 27.4.4.1 Writing the FCLKDIV Register Prior to issuing any Flash program or erase command after a reset, the user is required to write the FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz. Table 27-8 shows recommended values for the FDIV field based on BUSCLK frequency. NOTE Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash memory due to overstress. Setting FDIV too low can result in incomplete programming or erasure of the Flash memory cells. When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written, any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set. 27.4.4.2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see Section 27.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence. If CCIF is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the FCCOB register are ignored. MC9S12G Family Reference Manual Rev.1.28 944 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) 27.4.4.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 27.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag will remain clear until the Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 27-26. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 945 64 KByte Flash Module (S12FTMRG64K1V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no Read: FSTAT register yes FCCOB Availability Check CCIF Set? yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load. Write to FCCOB register to load required command parameter. More Parameters? yes no Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 27-26. Generic Flash Command Write Sequence Flowchart MC9S12G Family Reference Manual Rev.1.28 946 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) 27.4.4.3 Valid Flash Module Commands Table 27-27 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 27-27. Flash Commands by Mode and Security State Unsecured FCMD Command Secured NS1 SS2 NS3 SS4 0x01 Erase Verify All Blocks     0x02 Erase Verify Block     0x03 Erase Verify P-Flash Section    0x04 Read Once    0x06 Program P-Flash    0x07 Program Once    0x08 Erase All Blocks 0x09 Erase Flash Block    0x0A Erase P-Flash Sector    0x0B Unsecure Flash 0x0C Verify Backdoor Access Key  0x0D Set User Margin Level  0x0E Set Field Margin Level 0x10 Erase Verify EEPROM Section    0x11 Program EEPROM    0x12 Erase EEPROM Sector            1 Unsecured Normal Single Chip mode Unsecured Special Single Chip mode. 3 Secured Normal Single Chip mode. 4 Secured Special Single Chip mode. 2 27.4.4.4 P-Flash Commands Table 27-28 summarizes the valid P-Flash commands along with the effects of the commands on the P-Flash block and other resources within the Flash module. Table 27-28. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks Function on P-Flash Memory Verify that all P-Flash (and EEPROM) blocks are erased. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 947 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-28. P-Flash Commands FCMD Command 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a P-Flash (or EEPROM) block. An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. 0x0A Erase P-Flash Sector 0x0B Unsecure Flash 0x0C Verify Backdoor Access Key Supports a method of releasing MCU security by verifying a set of security keys. 0x0D Set User Margin Level Specifies a user margin read level for all P-Flash blocks. 0x0E Set Field Margin Level Specifies a field margin read level for all P-Flash blocks (special modes only). 27.4.4.5 Function on P-Flash Memory Verify that a P-Flash block is erased. Verify that a given number of words starting at the address provided are erased. Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block that was previously programmed using the Program Once command. Program a phrase in a P-Flash block. Erase all bytes in a P-Flash sector. Supports a method of releasing MCU security by erasing all P-Flash (and EEPROM) blocks and verifying that all P-Flash (and EEPROM) blocks are erased. EEPROM Commands Table 27-29 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. Table 27-29. EEPROM Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block Function on EEPROM Memory Verify that all EEPROM (and P-Flash) blocks are erased. Verify that the EEPROM block is erased. MC9S12G Family Reference Manual Rev.1.28 948 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-29. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block. An erase of the full EEPROM block is only possible when DPOPEN bit in the EEPROT register is set prior to launching the command. 0x0B Unsecure Flash 0x0D Set User Margin Level Specifies a user margin read level for the EEPROM block. 0x0E Set Field Margin Level Specifies a field margin read level for the EEPROM block (special modes only). 0x10 Erase Verify EEPROM Section Verify that a given number of words starting at the address provided are erased. 0x11 Program EEPROM Program up to four words in the EEPROM block. 0x12 Erase EEPROM Sector Erase all bytes in a sector of the EEPROM block. 27.4.5 Supports a method of releasing MCU security by erasing all EEPROM (and P-Flash) blocks and verifying that all EEPROM (and P-Flash) blocks are erased. Allowed Simultaneous P-Flash and EEPROM Operations Only the operations marked ‘OK’ in Table 27-30 are permitted to be run simultaneously on the Program Flash and EEPROM blocks. Some operations cannot be executed simultaneously because certain hardware resources are shared by the two memories. The priority has been placed on permitting Program Flash reads while program and erase operations execute on the EEPROM, providing read (P-Flash) while write (EEPROM) functionality. Table 27-30. Allowed P-Flash and EEPROM Simultaneous Operations EEPROM Program Flash Read Read Margin Read1 Program Sector Erase OK OK OK Mass Erase2 Margin Read1 Program Sector Erase Mass Erase2 OK 1 A ‘Margin Read’ is any read after executing the margin setting commands ‘Set User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified. See the Note on margin settings in Section 27.4.6.12 and Section 27.4.6.13. 2 The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 949 64 KByte Flash Module (S12FTMRG64K1V1) 27.4.6 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence. The ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be processed by the Memory Controller: • Starting any command write sequence that programs or erases Flash memory before initializing the FCLKDIV register • Writing an invalid command as part of the command write sequence • For additional possible errors, refer to the error handling table provided for each command If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation will return invalid data if both flags SFDIF and DFDIF are set. If the SFDIF or DFDIF flags were not previously set when the invalid read operation occurred, both the SFDIF and DFDIF flags will be set. If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting any command write sequence (see Section 27.3.2.7). CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. 27.4.6.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and EEPROM blocks have been erased. Table 27-31. Erase Verify All Blocks Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x01 Not required Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks operation has completed. If all blocks are not erased, it means blank check failed, both MGSTAT bits will be set. Table 27-32. Erase Verify All Blocks Command Error Handling Register Error Bit ACCERR FPVIOL FSTAT Error Condition Set if CCOBIX[2:0] != 000 at command launch None MGSTAT1 Set if any errors have been encountered during the reador if blank check failed . MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. MC9S12G Family Reference Manual Rev.1.28 950 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) 27.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0] bits determine which block must be verified. Table 27-33. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. See Table 27-34 Table 27-34. Flash block selection code description Selection code[1:0] Flash block to be verified 00 EEPROM 01 Invalid (ACCERR) 10 Invalid (ACCERR) 11 P-Flash Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that the selected P-Flash or EEPROM block is erased. The CCIF flag will set after the Erase Verify Block operation has completed.If the block is not erased, it means blank check failed, both MGSTAT bits will be set. Table 27-35. Erase Verify Block Command Error Handling Register Error Bit ACCERR FSTAT 27.4.6.3 FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if an invalid FlashBlockSelectionCode[1:0] is supplied None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. Erase Verify P-Flash Section Command The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 951 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-36. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. Table 27-37. Erase Verify P-Flash Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 27-27) ACCERR Set if an invalid global address [17:0] is supplied see Table 27-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT Set if the requested section crosses a the P-Flash address boundary FPVIOL 27.4.6.4 None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. Read Once Command The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of P-Flash. The Read Once field is programmed using the Program Once command described in Section 27.4.6.6. The Read Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 27-38. Read Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x04 Not Required 001 Read Once phrase index (0x0000 - 0x0007) 010 Read Once word 0 value 011 Read Once word 1 value 100 Read Once word 2 value 101 Read Once word 3 value MC9S12G Family Reference Manual Rev.1.28 952 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. 8 Table 27-39. Read Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if an invalid phrase index is supplied FSTAT 27.4.6.5 Set if command not available in current mode (see Table 27-27) FPVIOL None MGSTAT1 Set if any errors have been encountered during the read MGSTAT0 Set if any non-correctable errors have been encountered during the read Program P-Flash Command The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an embedded algorithm. CAUTION A P-Flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash phrase is not allowed. Table 27-40. Program P-Flash Command FCCOB Requirements CCOBIX[2:0] 000 1 FCCOB Parameters 0x06 Global address [17:16] to identify P-Flash block 001 Global address [15:0] of phrase location to be programmed1 010 Word 0 program value 011 Word 1 program value 100 Word 2 program value 101 Word 3 program value Global address [2:0] must be 000 Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. The CCIF flag will set after the Program P-Flash operation has completed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 953 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-41. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid global address [17:0] is supplied see Table 27-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 27.4.6.6 Set if command not available in current mode (see Table 27-27) Set if the global address [17:0] points to a protected area MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Program Once Command The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in P-Flash. The Program Once reserved field can be read using the Read Once command as described in Section 27.4.6.4. The Program Once command must only be issued once since the nonvolatile information register in P-Flash cannot be erased. The Program Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 27-42. Program Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x07 Not Required 001 Program Once phrase index (0x0000 - 0x0007) 010 Program Once word 0 value 011 Program Once word 1 value 100 Program Once word 2 value 101 Program Once word 3 value Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with read back. The CCIF flag will remain clear, setting only after the Program Once operation has completed. The reserved nonvolatile information register accessed by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. MC9S12G Family Reference Manual Rev.1.28 954 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-43. Program Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed1 FSTAT FPVIOL 1 Set if command not available in current mode (see Table 27-27) None MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will be allowed to execute again on that same phrase. 27.4.6.7 Erase All Blocks Command The Erase All Blocks operation will erase the entire P-Flash and EEPROM memory space. Table 27-44. Erase All Blocks Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x08 Not required Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All Blocks operation has completed. Table 27-45. Erase All Blocks Command Error Handling Register Error Bit ACCERR FSTAT 27.4.6.8 FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 27-27) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or EEPROM block. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 955 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-46. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 27-47. Erase Flash Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 27-27) ACCERR Set if the supplied P-Flash address is not phrase-aligned or if the EEPROM address is not word-aligned FSTAT FPVIOL 27.4.6.9 Set if an invalid global address [17:16] is supplied Set if an area of the selected Flash block is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Erase P-Flash Sector Command The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector. Table 27-48. Erase P-Flash Sector Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x0A Global address [17:16] to identify P-Flash block to be erased Global address [15:0] anywhere within the sector to be erased. Refer to Section 27.1.2.1 for the P-Flash sector size. Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed. MC9S12G Family Reference Manual Rev.1.28 956 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-49. Erase P-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if command not available in current mode (see Table 27-27) Set if an invalid global address [17:16] is supplied see Table 27-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL Set if the selected P-Flash sector is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 27.4.6.10 Unsecure Flash Command The Unsecure Flash command will erase the entire P-Flash and EEPROM memory space and, if the erase is successful, will release security. Table 27-50. Unsecure Flash Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x0B Not required Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire P-Flash and EEPROM memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. If the erase verify is not successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security state. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag is set after the Unsecure Flash operation has completed. Table 27-51. Unsecure Flash Command Error Handling Register Error Bit ACCERR FSTAT FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 27-27) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 27.4.6.11 Verify Backdoor Access Key Command The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 27-10). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 957 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-4). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 27-52. Verify Backdoor Access Key Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0C Not required 001 Key 0 010 Key 1 011 Key 2 100 Key 3 Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash configuration field with Key 0 compared to 0x3_FF00, etc. If the backdoor keys match, security will be released. If the backdoor keys do not match, security is not released and all future attempts to execute the Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is set after the Verify Backdoor Access Key operation has completed. Table 27-53. Verify Backdoor Access Key Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 100 at command launch Set if an incorrect backdoor key is supplied ACCERR FSTAT Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see Section 27.3.2.2) Set if the backdoor key has mismatched since the last reset FPVIOL None MGSTAT1 None MGSTAT0 None 27.4.6.12 Set User Margin Level Command The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P-Flash or EEPROM block. Table 27-54. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x0D Flash block selection code [1:0]. Table 27-34 See Margin level setting. MC9S12G Family Reference Manual Rev.1.28 958 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply user margin levels to the P-Flash block only. Valid margin level settings for the Set User Margin Level command are defined in Table 27-55. Table 27-55. Valid Set User Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state Table 27-56. Set User Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR FSTAT Set if command not available in current mode (see Table 27-27) Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 27-34 ) Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None NOTE User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 959 64 KByte Flash Module (S12FTMRG64K1V1) 27.4.6.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of the P-Flash or EEPROM block. Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the Table 27-57. Set Field Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0E 001 Flash block selection code [1:0]. Table 27-34 See Margin level setting. field margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM field margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash field margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply field margin levels to the P-Flash block only. Valid margin level settings for the Set Field Margin Level command are defined in Table 27-58. Table 27-58. Valid Set Field Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 0x0003 Field Margin-1 Level1 0x0004 Field Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state MC9S12G Family Reference Manual Rev.1.28 960 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-59. Set Field Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR FSTAT Set if command not available in current mode (see Table 27-27) Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 27-34 ) Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None CAUTION Field margin levels must only be used during verify of the initial factory programming. NOTE Field margin levels can be used to check that Flash memory contents have adequate margin for data retention at the normal level setting. If unexpected results are encountered when checking Flash memory contents at field margin levels, the Flash memory contents should be erased and reprogrammed. 27.4.6.14 Erase Verify EEPROM Section Command The Erase Verify EEPROM Section command will verify that a section of code in the EEPROM is erased. The Erase Verify EEPROM Section command defines the starting point of the data to be verified and the number of words. Table 27-60. Erase Verify EEPROM Section Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x10 Global address [17:16] to identify the EEPROM block 001 Global address [15:0] of the first word to be verified 010 Number of words to be verified Upon clearing CCIF to launch the Erase Verify EEPROM Section command, the Memory Controller will verify the selected section of EEPROM memory is erased. The CCIF flag will set after the Erase Verify EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 961 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-61. Erase Verify EEPROM Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 27-27) ACCERR Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested section breaches the end of the EEPROM block FPVIOL None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. 27.4.6.15 Program EEPROM Command The Program EEPROM operation programs one to four previously erased words in the EEPROM block. The Program EEPROM operation will confirm that the targeted location(s) were successfully programmed upon completion. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Table 27-62. Program EEPROM Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x11 Global address [17:16] to identify the EEPROM block 001 Global address [15:0] of word to be programmed 010 Word 0 program value 011 Word 1 program value, if desired 100 Word 2 program value, if desired 101 Word 3 program value, if desired Upon clearing CCIF to launch the Program EEPROM command, the user-supplied words will be transferred to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program EEPROM command launch determines how many words will be programmed in the EEPROM block. The CCIF flag is set when the operation has completed. MC9S12G Family Reference Manual Rev.1.28 962 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-63. Program EEPROM Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] < 010 at command launch Set if CCOBIX[2:0] > 101 at command launch ACCERR Set if command not available in current mode (see Table 27-27) Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested group of words breaches the end of the EEPROM block FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 27.4.6.16 Erase EEPROM Sector Command The Erase EEPROM Sector operation will erase all addresses in a sector of the EEPROM block. Table 27-64. Erase EEPROM Sector Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x12 Global address [17:16] to identify EEPROM block Global address [15:0] anywhere within the sector to be erased. See Section 27.1.2.2 for EEPROM sector size. Upon clearing CCIF to launch the Erase EEPROM Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase EEPROM Sector operation has completed. Table 27-65. Erase EEPROM Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if command not available in current mode (see Table 27-27) Set if an invalid global address [17:0] is suppliedsee Table 27-3) Set if a misaligned word address is supplied (global address [0] != 0) FSTAT FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 963 64 KByte Flash Module (S12FTMRG64K1V1) 27.4.7 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 27-66. Flash Interrupt Sources Interrupt Source Global (CCR) Mask Interrupt Flag Local Enable CCIF (FSTAT register) CCIE (FCNFG register) I Bit ECC Double Bit Fault on Flash Read DFDIF (FERSTAT register) DFDIE (FERCNFG register) I Bit ECC Single Bit Fault on Flash Read SFDIF (FERSTAT register) SFDIE (FERCNFG register) I Bit Flash Command Complete NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 27.4.7.1 Description of Flash Interrupt Operation The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed description of the register bits involved, refer to Section 27.3.2.5, “Flash Configuration Register (FCNFG)”, Section 27.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 27.3.2.7, “Flash Status Register (FSTAT)”, and Section 27.3.2.8, “Flash Error Status Register (FERSTAT)”. The logic used for generating the Flash module interrupts is shown in Figure 27-27. CCIE CCIF DFDIE DFDIF Flash Command Interrupt Request Flash Error Interrupt Request SFDIE SFDIF Figure 27-27. Flash Module Interrupts Implementation MC9S12G Family Reference Manual Rev.1.28 964 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) 27.4.8 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 27.4.7, “Interrupts”). 27.4.9 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. 27.5 Security The Flash module provides security information to the MCU. The Flash security state is defined by the SEC bits of the FSEC register (see Table 27-11). During reset, the Flash module initializes the FSEC register using data read from the security byte of the Flash configuration field at global address 0x3_FF0F. The security state out of reset can be permanently changed by programming the security byte assuming that the MCU is starting from a mode where the necessary P-Flash erase and program commands are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset. The following subsections describe these security-related subjects: • Unsecuring the MCU using Backdoor Key Access • Unsecuring the MCU in Special Single Chip Mode using BDM • Mode and Security Effects on Flash Command Availability 27.5.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x3_FF00-0x3_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 27.3.2.2), the Verify Backdoor Access Key command (see Section 27.4.6.11) allows the user to present four prospective keys for comparison to the keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC register (see Table 27-11) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash memory and EEPROM memory will not be available for read access and will return invalid data. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 965 64 KByte Flash Module (S12FTMRG64K1V1) The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 27.3.2.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 27.4.6.11 2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10 The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method to re-enable the Verify Backdoor Access Key command. The security as defined in the Flash security byte (0x3_FF0F) is not changed by using the Verify Backdoor Access Key command sequence. The backdoor keys stored in addresses 0x3_FF00-0x3_FF07 are unaffected by the Verify Backdoor Access Key command sequence. The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection register, FPROT. After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is unsecured, the sector containing the Flash security byte can be erased and the Flash security byte can be reprogrammed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x3_FF00-0x3_FF07 in the Flash configuration field. 27.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM A secured MCU can be unsecured in special single chip mode by using the following method to erase the P-Flash and EEPROM memory: 1. Reset the MCU into special single chip mode 2. Delay while the BDM executes the Erase Verify All Blocks command write sequence to check if the P-Flash and EEPROM memories are erased 3. Send BDM commands to disable protection in the P-Flash and EEPROM memory 4. Execute the Erase All Blocks command write sequence to erase the P-Flash and EEPROM memory. Alternatively the Unsecure Flash command can be executed, if so the steps 5 and 6 below are skeeped. 5. After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into special single chip mode 6. Delay while the BDM executes the Erase Verify All Blocks command write sequence to verify that the P-Flash and EEPROM memory are erased If the P-Flash and EEPROM memory are verified as erased, the MCU will be unsecured. All BDM commands will now be enabled and the Flash security byte may be programmed to the unsecure state by continuing with the following steps: 7. Send BDM commands to execute the Program P-Flash command write sequence to program the Flash security byte to the unsecured state MC9S12G Family Reference Manual Rev.1.28 966 NXP Semiconductors 64 KByte Flash Module (S12FTMRG64K1V1) 8. Reset the MCU 27.5.3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 27-27. 27.6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the Flash Block Configuration Parameters, the FPROT and EEPROT protection registers, and the FOPT and FSEC registers. The initialization routine reverts to built-in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence. If a double bit fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set. CCIF is cleared throughout the initialization sequence. The Flash module holds off all CPU access for a portion of the initialization sequence. Flash reads are allowed once the hold is removed. Completion of the initialization sequence is marked by setting CCIF high which enables user commands. If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 967 64 KByte Flash Module (S12FTMRG64K1V1) MC9S12G Family Reference Manual Rev.1.28 968 NXP Semiconductors Chapter 28 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-1. Revision History Revision Number Revision Date V01.04 17 Jun 2010 28.4.6.1/28-1002 Clarify Erase Verify Commands Descriptions related to the bits MGSTAT[1:0] 28.4.6.2/28-1003 of the register FSTAT. 28.4.6.3/28-1004 28.4.6.14/28-1013 V01.05 20 Aug 2010 28.4.6.2/28-1003 Updated description of the commands RD1BLK, MLOADU and MLOADF 28.4.6.12/28-1010 28.4.6.13/28-1012 V01.06 31 Jan 2011 28.1 Sections Affected 28.3.2.9/28-985 Description of Changes Updated description of protection on Section 28.3.2.9 Introduction The FTMRG96K1 module implements the following: • 96Kbytes of P-Flash (Program Flash) memory • 3 Kbytes of EEPROM memory The Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory contents. The user interface to the memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is written to with the command, global address, data, and any required command parameters. The memory controller must complete the execution of a command before the FCCOB register can be written to with a new command. CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 969 It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory. Simultaneous P-Flash and EEPROM operations are discussed in Section 28.4.5. Both P-Flash and EEPROM memories are implemented with Error Correction Codes (ECC) that can resolve single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read by half-phrase, only one single bit fault in an aligned 4 byte half-phrase containing the byte or word accessed will be corrected. 28.1.1 Glossary Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. EEPROM Memory — The EEPROM memory constitutes the nonvolatile memory store for data. EEPROM Sector — The EEPROM sector is the smallest portion of the EEPROM memory that can be erased. The EEPROM sector consists of 4 bytes. NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters required for Flash command execution. Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double bit fault detection within each double word. P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications. P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased. Each P-Flash sector contains 512 bytes. Program IFR — Nonvolatile information register located in the P-Flash block that contains the Version ID, and the Program Once field. 28.1.2 28.1.2.1 • • • Features P-Flash Features 96 Kbytes of P-Flash memory composed of one 96 Kbyte Flash block divided into 192 sectors of 512 bytes Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 970 96 KByte Flash Module (S12FTMRG96K1V1) • • • Fast sector erase and phrase program operation Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 28.1.2.2 • • • • • • 3 Kbytes of EEPROM memory composed of one 3 Kbyte Flash block divided into 768 sectors of 4 bytes Single bit fault correction and double bit fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Protection scheme to prevent accidental program or erase of EEPROM memory Ability to program up to four words in a burst sequence 28.1.2.3 • • • EEPROM Features Other Flash Module Features No external high-voltage power supply required for Flash memory program and erase operations Interrupt generation on Flash command completion and Flash error detection Security mechanism to prevent unauthorized access to the Flash memory 28.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 28-1. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 971 96 KByte Flash Module (S12FTMRG96K1V1) Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 24Kx39 sector 0 sector 1 Protection sector 191 Security Bus Clock Clock Divider FCLK Memory Controller CPU EEPROM 1.5Kx22 sector 0 sector 1 sector 767 Figure 28-1. FTMRG96K1 Block Diagram 28.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual Rev.1.28 972 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) 28.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed. If such action is attempted the write operation will not change the register value. Writing to the Flash registers is allowed when the Flash is not busy executing commands (CCIF = 1) and during initialization right after reset, despite the value of flag CCIF in that case (refer to Section 28.6 for a complete description of the reset sequence). . Table 28-2. FTMRG Memory Map Global Address (in Bytes) 0x0_0000 - 0x0_03FF 1 Size (Bytes) 1,024 Description Register Space 0x0_0400 – 0x0_0FFF 3,072 EEPROM Memory 0x0_1000 – 0x0_13FF 1,024 FTMRG reserved area 0x0_4000 – 0x0_7FFF 16,284 NVMRES1=1 : NVM Resource area (see Figure 28-3) 0x2_0000 – 0x2_7FFF 32,767 FTMRG reserved area 0x2_8000 – 0x3_FFFF 98,304 P-Flash Memory See NVMRES description in Section 28.4.3 28.3.1 Module Memory Map The S12 architecture places the P-Flash memory between global addresses 0x2_8000 and 0x3_FFFF as shown in Table 28-3.The P-Flash memory map is shown in Figure 28-2. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 973 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-3. P-Flash Memory Addressing Global Address Size (Bytes) 0x2_8000 – 0x3_FFFF 96 K Description P-Flash Block Contains Flash Configuration Field (see Table 28-4) The FPROT register, described in Section 28.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. Three separate memory regions, one growing upward from global address 0x3_8000 in the Flash memory (called the lower region), one growing downward from global address 0x3_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection. The Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 28-4. Table 28-4. Flash Configuration Field 1 Global Address Size (Bytes) 0x3_FF00-0x3_FF07 8 Backdoor Comparison Key Refer to Section 28.4.6.11, “Verify Backdoor Access Key Command,” and Section 28.5.1, “Unsecuring the MCU using Backdoor Key Access” 0x3_FF08-0x3_FF0B1 4 Reserved 0x3_FF0C1 1 P-Flash Protection byte. Refer to Section 28.3.2.9, “P-Flash Protection Register (FPROT)” 0x3_FF0D1 1 EEPROM Protection byte. Refer to Section 28.3.2.10, “EEPROM Protection Register (EEPROT)” 0x3_FF0E1 1 Flash Nonvolatile byte Refer to Section 28.3.2.16, “Flash Option Register (FOPT)” 0x3_FF0F1 1 Flash Security byte Refer to Section 28.3.2.2, “Flash Security Register (FSEC)” Description 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B reserved field should be programmed to 0xFF. MC9S12G Family Reference Manual Rev.1.28 974 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) P-Flash START = 0x2_8000 Flash Protected/Unprotected Region 64 Kbytes 0x3_8000 0x3_8400 0x3_8800 0x3_9000 Protection Fixed End Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x3_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) Protection Movable End 0x3_C000 Protection Fixed End 0x3_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 P-Flash END = 0x3_FFFF Flash Configuration Field 16 bytes (0x3_FF00 - 0x3_FF0F) Figure 28-2. P-Flash Memory Map Table 28-5. Program IFR Fields 1 Global Address Size (Bytes) 0x0_4000 – 0x0_4007 8 Reserved 0x0_4008 – 0x0_40B5 174 Reserved 0x0_40B6 – 0x0_40B7 2 Version ID1 0x0_40B8 – 0x0_40BF 8 Reserved 0x0_40C0 – 0x0_40FF 64 Program Once Field Refer to Section 28.4.6.6, “Program Once Command” Field Description Used to track firmware patch versions, see Section 28.4.2 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 975 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-6. Memory Controller Resource Fields (NVMRES1=1) Global Address Size (Bytes) 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 28-5) 0x0_4100 – 0x0_41FF 256 Reserved. 0x0_4200 – 0x0_57FF 1 Description Reserved 0x0_5800 – 0x0_59FF 512 Reserved 0x0_5A00 – 0x0_5FFF 1,536 Reserved 0x0_6000 – 0x0_6BFF 3,072 Reserved 0x0_6C00 – 0x0_7FFF 5,120 Reserved NVMRES - See Section 28.4.3 for NVMRES (NVM Resource) detail. 0x0_4000 0x0_4400 RAM Start = 0x0_5800 RAM End = 0x0_59FF P-Flash IFR 1 Kbyte (NVMRES=1) Reserved 5k bytes Reserved 512 bytes Reserved 4608 bytes 0x0_6C00 Reserved 5120 bytes 0x0_7FFF Figure 28-3. Memory Controller Resource Memory Map (NVMRES=1) 28.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 28.3). MC9S12G Family Reference Manual Rev.1.28 976 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) A summary of the Flash module registers is given in Figure 28-4 with detailed descriptions in the following subsections. Address & Name 0x0000 FCLKDIV 0x0001 FSEC 0x0002 FCCOBIX 0x0003 FRSV0 0x0004 FCNFG 0x0005 FERCNFG 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 EEPROT 0x000A FCCOBHI 0x000B FCCOBLO 0x000C FRSV1 7 R 6 5 4 3 2 1 0 FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0 0 0 0 0 0 0 0 0 0 0 0 0 FDFD FSFD 0 0 0 0 0 DFDIE SFDIE ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0 0 0 0 0 DFDIF SFDIF FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 FDIVLD W R W R W R W R W R CCIE 0 IGNSF W R W R CCIF 0 0 0 W R W R W R W R W R FPOPEN RNV6 DPOPEN DPS6 DPS5 DPS4 DPS3 DPS2 DPS1 DPS0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0 0 0 0 0 0 0 0 W Figure 28-4. FTMRG96K1 Register Summary MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 977 96 KByte Flash Module (S12FTMRG96K1V1) Address & Name 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT 0x0011 FRSV5 0x0012 FRSV6 0x0013 FRSV7 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W R W R W R W R W = Unimplemented or Reserved Figure 28-4. FTMRG96K1 Register Summary (continued) 28.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Offset Module Base + 0x0000 7 R FDIVLD W Reset 0 6 5 4 3 FDIVLCK 0 2 1 0 0 0 0 FDIV[5:0] 0 0 0 = Unimplemented or Reserved Figure 28-5. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. MC9S12G Family Reference Manual Rev.1.28 978 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). Table 28-7. FCLKDIV Field Descriptions Field 7 FDIVLD Description Clock Divider Loaded 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset 6 FDIVLCK Clock Divider Locked 0 FDIV field is open for writing 1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in normal mode. 5–0 FDIV[5:0] Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events during Flash program and erase algorithms. Table 28-8 shows recommended values for FDIV[5:0] based on the BUSCLK frequency. Please refer to Section 28.4.4, “Flash Command Operations,” for more information. Table 28-8. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) 1 2 MIN1 MAX2 1.0 1.6 1.6 FDIV[5:0] BUSCLK Frequency (MHz) FDIV[5:0] MIN1 MAX2 0x00 16.6 17.6 0x10 2.6 0x01 17.6 18.6 0x11 2.6 3.6 0x02 18.6 19.6 0x12 3.6 4.6 0x03 19.6 20.6 0x13 4.6 5.6 0x04 20.6 21.6 0x14 5.6 6.6 0x05 21.6 22.6 0x15 6.6 7.6 0x06 22.6 23.6 0x16 7.6 8.6 0x07 23.6 24.6 0x17 8.6 9.6 0x08 24.6 25.6 0x18 9.6 10.6 0x09 10.6 11.6 0x0A 11.6 12.6 0x0B 12.6 13.6 0x0C 13.6 14.6 0x0D 14.6 15.6 0x0E 15.6 16.6 0x0F BUSCLK is Greater Than this value. BUSCLK is Less Than or Equal to this value. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 979 96 KByte Flash Module (S12FTMRG96K1V1) 28.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 28-6. Flash Security Register (FSEC) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FSEC register are readable but not writable. During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the Flash configuration field at global address 0x3_FF0F located in P-Flash memory (see Table 28-4) as indicated by reset condition F in Figure 28-6. If a double bit fault is detected while reading the P-Flash phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set to leave the Flash module in a secured state with backdoor key access disabled. Table 28-9. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the KEYEN[1:0] Flash module as shown in Table 28-10. 5–2 RNV[5:2] Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements. 1–0 SEC[1:0] Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 28-11. If the Flash module is unsecured using backdoor key access, the SEC bits are forced to 10. Table 28-10. Flash KEYEN States 1 KEYEN[1:0] Status of Backdoor Key Access 00 DISABLED 01 DISABLED1 10 ENABLED 11 DISABLED Preferred KEYEN state to disable backdoor key access. MC9S12G Family Reference Manual Rev.1.28 980 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-11. Flash Security States 1 SEC[1:0] Status of Security 00 SECURED 01 SECURED1 10 UNSECURED 11 SECURED Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 28.5. 28.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations. Offset Module Base + 0x0002 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 CCOBIX[2:0] W Reset 1 0 0 0 = Unimplemented or Reserved Figure 28-7. FCCOB Index Register (FCCOBIX) CCOBIX bits are readable and writable while remaining bits read 0 and are not writable. Table 28-12. FCCOBIX Field Descriptions Field Description 2–0 CCOBIX[1:0] Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to. See 28.3.2.11 Flash Common Command Object Register (FCCOB),” for more details. 28.3.2.4 Flash Reserved0 Register (FRSV0) This Flash register is reserved for factory testing. Offset Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 28-8. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 981 96 KByte Flash Module (S12FTMRG96K1V1) 28.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU. Offset Module Base + 0x0004 7 R W Reset CCIE 0 6 5 0 0 0 0 4 IGNSF 0 3 2 0 0 0 0 1 0 FDFD FSFD 0 0 = Unimplemented or Reserved Figure 28-9. Flash Configuration Register (FCNFG) CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not writable. Table 28-13. FCNFG Field Descriptions Field Description 7 CCIE Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command has completed. 0 Command complete interrupt disabled 1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 28.3.2.7) 4 IGNSF Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see Section 28.3.2.8). 0 All single bit faults detected during array reads are reported 1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated 1 FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. 0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected 1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see Section 28.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG register is set (see Section 28.3.2.6) 0 FSFD Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. 0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected 1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 28.3.2.7) and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see Section 28.3.2.6) 28.3.2.6 Flash Error Configuration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. MC9S12G Family Reference Manual Rev.1.28 982 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) Offset Module Base + 0x0005 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDIE SFDIE 0 0 = Unimplemented or Reserved Figure 28-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. Table 28-14. FERCNFG Field Descriptions Field Description 1 DFDIE Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation. 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set (see Section 28.3.2.8) 0 SFDIE Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault is detected during a Flash block read operation. 0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 28.3.2.8) 1 An interrupt will be requested whenever the SFDIF flag is set (see Section 28.3.2.8) 28.3.2.7 Flash Status Register (FSTAT) The FSTAT register reports the operational status of the Flash module. Offset Module Base + 0x0006 7 R W Reset CCIF 1 6 0 0 5 4 ACCERR FPVIOL 0 0 3 2 MGBUSY RSVD 0 0 1 0 MGSTAT[1:0] 01 01 = Unimplemented or Reserved Figure 28-11. Flash Status Register (FSTAT) 1 Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 28.6). CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 983 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation. 0 Flash command in progress 1 Flash command has completed 5 ACCERR Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory caused by either a violation of the command write sequence (see Section 28.4.4.2) or issuing an illegal Flash command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR. 0 No access error detected 1 Access error detected 4 FPVIOL Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of P-Flash or EEPROM memory during a command write sequence. The FPVIOL bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected 1 Protection violation detected 3 MGBUSY 2 RSVD Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller. 0 Memory Controller is idle 1 Memory Controller is busy executing a Flash command (CCIF = 0) Reserved Bit — This bit is reserved and always reads 0. 1–0 Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See Section 28.4.6, “Flash Command Description,” and Section 28.6, “Initialization” for details. 28.3.2.8 Flash Error Status Register (FERSTAT) The FERSTAT register reflects the error status of internal Flash operations. Offset Module Base + 0x0007 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDIF SFDIF 0 0 = Unimplemented or Reserved Figure 28-12. Flash Error Status Register (FERSTAT) All flags in the FERSTAT register are readable and only writable to clear the flag. MC9S12G Family Reference Manual Rev.1.28 984 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The DFDIF flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.2 0 No double bit fault detected 1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command running 0 SFDIF Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF. 0 No single bit fault detected 1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted while command running 1 The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either single fault or double fault but never both). A simultaneous access collision (Flash array read operation returning invalid data attempted while command running) is indicated when both SFDIF and DFDIF flags are high. 2 There is a one cycle delay in storing the ECC DFDIF and SFDIF fault flags in this register. At least one NOP is required after a flash memory read before checking FERSTAT for the occurrence of ECC errors. 28.3.2.9 P-Flash Protection Register (FPROT) The FPROT register defines which P-Flash sectors are protected against program and erase operations. Offset Module Base + 0x0008 7 R W Reset FPOPEN F1 6 5 RNV6 F1 4 FPHDIS F1 3 FPHS[1:0] F1 2 1 FPLDIS F1 F1 0 FPLS[1:0] F1 F1 = Unimplemented or Reserved Figure 28-13. Flash Protection Register (FPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected region can only be increased (see Section 28.3.2.9.1, “P-Flash Protection Restrictions,” and Table 28-21). During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte in the Flash configuration field at global address 0x3_FF0C located in P-Flash memory (see Table 28-4) as indicated by reset condition ‘F’ in Figure 28-13. To change the P-Flash protection that will be loaded during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 985 96 KByte Flash Module (S12FTMRG96K1V1) Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. Table 28-17. FPROT Field Descriptions Field Description 7 FPOPEN Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or erase operations as shown in Table 28-18 for the P-Flash block. 0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits 1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits 6 RNV[6] Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements. 5 FPHDIS Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory ending with global address 0x3_FFFF. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 4–3 FPHS[1:0] Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area in P-Flash memory as shown inTable 28-19. The FPHS bits can only be written to while the FPHDIS bit is set. 2 FPLDIS Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory beginning with global address 0x3_8000. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 1–0 FPLS[1:0] Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area in P-Flash memory as shown in Table 28-20. The FPLS bits can only be written to while the FPLDIS bit is set. Table 28-18. P-Flash Protection Function 1 Function1 FPOPEN FPHDIS FPLDIS 1 1 1 No P-Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P-Flash Memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges For range sizes, refer to Table 28-19 and Table 28-20. MC9S12G Family Reference Manual Rev.1.28 986 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-19. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 00 0x3_F800–0x3_FFFF 2 Kbytes 01 0x3_F000–0x3_FFFF 4 Kbytes 10 0x3_E000–0x3_FFFF 8 Kbytes 11 0x3_C000–0x3_FFFF 16 Kbytes Table 28-20. P-Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 00 0x3_8000–0x3_83FF 1 Kbyte 01 0x3_8000–0x3_87FF 2 Kbytes 10 0x3_8000–0x3_8FFF 4 Kbytes 11 0x3_8000–0x3_9FFF 8 Kbytes All possible P-Flash protection scenarios are shown in Figure 28-14 . Although the protection scheme is loaded from the Flash memory at global address 0x3_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 987 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 Scenario FLASH START FPLS[1:0] 0x3_FFFF FPHS[1:0] 0x3_8000 FPOPEN = 0 0x3_8000 FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 96 KByte Flash Module (S12FTMRG96K1V1) 0x3_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 28-14. P-Flash Protection Scenarios MC9S12G Family Reference Manual Rev.1.28 988 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) 28.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 28-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 28-21. P-Flash Protection Scenario Transitions To Protection Scenario1 From Protection Scenario 0 1 2 3 0 X X X X X 1 X 4 X X X X X X X X X X 6 X 7 1 X 6 7 X 3 5 5 X X 2 4 X X X X X X Allowed transitions marked with X, see Figure 28-14 for a definition of the scenarios. 28.3.2.10 EEPROM Protection Register (EEPROT) The EEPROT register defines which EEPROM sectors are protected against program and erase operations. Offset Module Base + 0x0009 7 R W Reset 6 5 4 DPOPEN F1 3 2 1 0 F1 F1 F1 DPS[6:0] F1 F1 F1 F1 Figure 28-15. EEPROM Protection Register (EEPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the EEPROT register are writable with the restriction that protection can be added but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1 (protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is irrelevant. During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 989 96 KByte Flash Module (S12FTMRG96K1V1) P-Flash memory (see Table 28-4) as indicated by reset condition F in Table 28-23. To change the EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase containing the EEPROM protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the EEPROM memory fully protected. Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. Block erase of the EEPROM memory is not possible if any of the EEPROM sectors are protected. Table 28-22. EEPROT Field Descriptions Field Description 7 DPOPEN EEPROM Protection Control 0 Enables EEPROM memory protection from program and erase with protected address range defined by DPS bits 1 Disables EEPROM memory protection from program and erase 6–0 DPS[6:0] EEPROM Protection Size — The DPS[6:0] bits determine the size of the protected area in the EEPROM memory, this size increase in step of 32 bytes, as shown in Table 28-23 . Table 28-23. EEPROM Protection Address Range DPS[6:0] Global Address Range Protected Size 0000000 0x0_0400 – 0x0_041F 32 bytes 0000001 0x0_0400 – 0x0_043F 64 bytes 0000010 0x0_0400 – 0x0_045F 96 bytes 0000011 0x0_0400 – 0x0_047F 128 bytes 0000100 0x0_0400 – 0x0_049F 160 bytes 0000101 0x0_0400 – 0x0_04BF 192 bytes The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increasing of one. . . . 1011111 - to - 1111111 0x0_0400 – 0x0_0FFF 3,072 bytes MC9S12G Family Reference Manual Rev.1.28 990 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) 28.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. Offset Module Base + 0x000A 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[15:8] W Reset 3 0 0 0 0 Figure 28-16. Flash Common Command Object High Register (FCCOBHI) Offset Module Base + 0x000B 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[7:0] W Reset 3 0 0 0 0 Figure 28-17. Flash Common Command Object Low Register (FCCOBLO) 28.3.2.11.1 FCCOB - NVM Command Mode NVM command mode uses the indexed FCCOB register to provide a command code and its relevant parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes (as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array. The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 28-24. The return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller. Writes to the unimplemented parameter fields (CCOBIX = 110 and CCOBIX = 111) are ignored with reads from these fields returning 0x0000. Table 28-24 shows the generic Flash command format. The high byte of the first word in the CCOB array contains the command code, followed by the parameters for this specific Flash command. For details on the FCCOB settings required by each command, see the Flash command descriptions in Section 28.4.6. Table 28-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] 000 001 Byte FCCOB Parameter Fields (NVM Command Mode) HI FCMD[7:0] defining Flash command LO 6’h0, Global address [17:16] HI Global address [15:8] LO Global address [7:0] MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 991 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] 010 011 100 101 Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 0 [15:8] LO Data 0 [7:0] HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 28.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing. Offset Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 28-18. Flash Reserved1 Register (FRSV1) All bits in the FRSV1 register read 0 and are not writable. 28.3.2.13 Flash Reserved2 Register (FRSV2) This Flash register is reserved for factory testing. Offset Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 28-19. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. 28.3.2.14 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.28 992 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) Offset Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 28-20. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 28.3.2.15 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing. Offset Module Base + 0x000F R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 28-21. Flash Reserved4 Register (FRSV4) All bits in the FRSV4 register read 0 and are not writable. 28.3.2.16 Flash Option Register (FOPT) The FOPT register is the Flash option register. Offset Module Base + 0x0010 7 6 5 4 R 3 2 1 0 F1 F1 F1 F1 NV[7:0] W Reset F1 F1 F1 F1 = Unimplemented or Reserved Figure 28-22. Flash Option Register (FOPT) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FOPT register are readable but are not writable. During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global address 0x3_FF0E located in P-Flash memory (see Table 28-4) as indicated by reset condition F in Figure 28-22. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 993 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-25. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits. 28.3.2.17 Flash Reserved5 Register (FRSV5) This Flash register is reserved for factory testing. Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 28-23. Flash Reserved5 Register (FRSV5) All bits in the FRSV5 register read 0 and are not writable. 28.3.2.18 Flash Reserved6 Register (FRSV6) This Flash register is reserved for factory testing. Offset Module Base + 0x0012 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 28-24. Flash Reserved6 Register (FRSV6) All bits in the FRSV6 register read 0 and are not writable. 28.3.2.19 Flash Reserved7 Register (FRSV7) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.28 994 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 28-25. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. 28.4 28.4.1 Functional Description Modes of Operation The FTMRG96K1 module provides the modes of operation normal and special . The operating mode is determined by module-level inputs and affects the FCLKDIV, FCNFG, and EEPROT registers (see Table 28-27). 28.4.2 IFR Version ID Word The version ID word is stored in the IFR at address 0x0_40B6. The contents of the word are defined in Table 28-26. Table 28-26. IFR Version ID Fields [15:4] [3:0] Reserved VERNUM MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 995 96 KByte Flash Module (S12FTMRG96K1V1) • VERNUM: Version number. The first version is number 0b_0001 with both 0b_0000 and 0b_1111 meaning ‘none’. 28.4.3 Internal NVM resource (NVMRES) IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown in Table 28-5. The NVMRES global address map is shown in Table 28-6. 28.4.4 Flash Command Operations Flash command operations are used to modify Flash memory contents. The next sections describe: • How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from BUSCLK for Flash program and erase command operations • The command write sequence used to set Flash command parameters and launch execution • Valid Flash commands available for execution, according to MCU functional mode and MCU security state. 28.4.4.1 Writing the FCLKDIV Register Prior to issuing any Flash program or erase command after a reset, the user is required to write the FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz. Table 28-8 shows recommended values for the FDIV field based on BUSCLK frequency. NOTE Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash memory due to overstress. Setting FDIV too low can result in incomplete programming or erasure of the Flash memory cells. When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written, any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set. 28.4.4.2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see Section 28.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence. If CCIF is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the FCCOB register are ignored. MC9S12G Family Reference Manual Rev.1.28 996 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) 28.4.4.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 28.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag will remain clear until the Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 28-26. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 997 96 KByte Flash Module (S12FTMRG96K1V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no Read: FSTAT register yes FCCOB Availability Check CCIF Set? yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load. Write to FCCOB register to load required command parameter. More Parameters? yes no Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 28-26. Generic Flash Command Write Sequence Flowchart MC9S12G Family Reference Manual Rev.1.28 998 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) 28.4.4.3 Valid Flash Module Commands Table 28-27 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 28-27. Flash Commands by Mode and Security State Unsecured FCMD Command Secured NS1 SS2 NS3 SS4 0x01 Erase Verify All Blocks     0x02 Erase Verify Block     0x03 Erase Verify P-Flash Section    0x04 Read Once    0x06 Program P-Flash    0x07 Program Once    0x08 Erase All Blocks 0x09 Erase Flash Block    0x0A Erase P-Flash Sector    0x0B Unsecure Flash 0x0C Verify Backdoor Access Key  0x0D Set User Margin Level  0x0E Set Field Margin Level 0x10 Erase Verify EEPROM Section    0x11 Program EEPROM    0x12 Erase EEPROM Sector            1 Unsecured Normal Single Chip mode Unsecured Special Single Chip mode. 3 Secured Normal Single Chip mode. 4 Secured Special Single Chip mode. 2 28.4.4.4 P-Flash Commands Table 28-28 summarizes the valid P-Flash commands along with the effects of the commands on the P-Flash block and other resources within the Flash module. Table 28-28. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks Function on P-Flash Memory Verify that all P-Flash (and EEPROM) blocks are erased. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 999 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-28. P-Flash Commands FCMD Command 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a P-Flash (or EEPROM) block. An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. 0x0A Erase P-Flash Sector 0x0B Unsecure Flash 0x0C Verify Backdoor Access Key Supports a method of releasing MCU security by verifying a set of security keys. 0x0D Set User Margin Level Specifies a user margin read level for all P-Flash blocks. 0x0E Set Field Margin Level Specifies a field margin read level for all P-Flash blocks (special modes only). 28.4.4.5 Function on P-Flash Memory Verify that a P-Flash block is erased. Verify that a given number of words starting at the address provided are erased. Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block that was previously programmed using the Program Once command. Program a phrase in a P-Flash block. Erase all bytes in a P-Flash sector. Supports a method of releasing MCU security by erasing all P-Flash (and EEPROM) blocks and verifying that all P-Flash (and EEPROM) blocks are erased. EEPROM Commands Table 28-29 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. Table 28-29. EEPROM Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block Function on EEPROM Memory Verify that all EEPROM (and P-Flash) blocks are erased. Verify that the EEPROM block is erased. MC9S12G Family Reference Manual Rev.1.28 1000 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-29. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block. An erase of the full EEPROM block is only possible when DPOPEN bit in the EEPROT register is set prior to launching the command. 0x0B Unsecure Flash 0x0D Set User Margin Level Specifies a user margin read level for the EEPROM block. 0x0E Set Field Margin Level Specifies a field margin read level for the EEPROM block (special modes only). 0x10 Erase Verify EEPROM Section Verify that a given number of words starting at the address provided are erased. 0x11 Program EEPROM Program up to four words in the EEPROM block. 0x12 Erase EEPROM Sector Erase all bytes in a sector of the EEPROM block. 28.4.5 Supports a method of releasing MCU security by erasing all EEPROM (and P-Flash) blocks and verifying that all EEPROM (and P-Flash) blocks are erased. Allowed Simultaneous P-Flash and EEPROM Operations Only the operations marked ‘OK’ in Table 28-30 are permitted to be run simultaneously on the Program Flash and EEPROM blocks. Some operations cannot be executed simultaneously because certain hardware resources are shared by the two memories. The priority has been placed on permitting Program Flash reads while program and erase operations execute on the EEPROM, providing read (P-Flash) while write (EEPROM) functionality. Table 28-30. Allowed P-Flash and EEPROM Simultaneous Operations EEPROM Program Flash Read Read Margin Read1 Program Sector Erase OK OK OK Mass Erase2 Margin Read1 Program Sector Erase Mass Erase2 OK 1 A ‘Margin Read’ is any read after executing the margin setting commands ‘Set User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified. See the Note on margin settings in Section 28.4.6.12 and Section 28.4.6.13. 2 The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1001 96 KByte Flash Module (S12FTMRG96K1V1) 28.4.6 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence. The ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be processed by the Memory Controller: • Starting any command write sequence that programs or erases Flash memory before initializing the FCLKDIV register • Writing an invalid command as part of the command write sequence • For additional possible errors, refer to the error handling table provided for each command If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation will return invalid data if both flags SFDIF and DFDIF are set. If the SFDIF or DFDIF flags were not previously set when the invalid read operation occurred, both the SFDIF and DFDIF flags will be set. If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting any command write sequence (see Section 28.3.2.7). CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. 28.4.6.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and EEPROM blocks have been erased. Table 28-31. Erase Verify All Blocks Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x01 Not required Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks operation has completed. If all blocks are not erased, it means blank check failed, both MGSTAT bits will be set. Table 28-32. Erase Verify All Blocks Command Error Handling Register Error Bit ACCERR FPVIOL FSTAT 1 Error Condition Set if CCOBIX[2:0] != 000 at command launch None MGSTAT1 Set if any errors have been encountered during the read1or if blank check failed . MGSTAT0 Set if any non-correctable errors have been encountered during the read1 or if blank check failed. As found in the memory map for FTMRG96K1. MC9S12G Family Reference Manual Rev.1.28 1002 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) 28.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0] bits determine which block must be verified. Table 28-33. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. Table 28-34 See Table 28-34. Flash block selection code description Selection code[1:0] Flash block to be verified 00 EEPROM 01 Invalid (ACCERR) 10 P-Flash 11 P-Flash Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that the selected P-Flash or EEPROM block is erased. The CCIF flag will set after the Erase Verify Block operation has completed.If the block is not erased, it means blank check failed, both MGSTAT bits will be set. Table 28-35. Erase Verify Block Command Error Handling Register Error Bit ACCERR FSTAT 1 2 FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if an invalid FlashBlockSelectionCode[1:0] is supplied1 None MGSTAT1 Set if any errors have been encountered during the read2 or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read2 or if blank check failed. As defined by the memory map for FTMRG96K1. As found in the memory map for FTMRG96K1. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1003 96 KByte Flash Module (S12FTMRG96K1V1) 28.4.6.3 Erase Verify P-Flash Section Command The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. Table 28-36. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. Table 28-37. Erase Verify P-Flash Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 28-27) ACCERR Set if an invalid global address [17:0] is supplied see Table 28-3)1 Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT Set if the requested section crosses a the P-Flash address boundary FPVIOL 1 2 None MGSTAT1 Set if any errors have been encountered during the read2 or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read2 or if blank check failed. As defined by the memory map for FTMRG96K1. As found in the memory map for FTMRG96K1. 28.4.6.4 Read Once Command The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of P-Flash. The Read Once field is programmed using the Program Once command described in Section 28.4.6.6. The Read Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 28-38. Read Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x04 Not Required MC9S12G Family Reference Manual Rev.1.28 1004 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-38. Read Once Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 001 Read Once phrase index (0x0000 - 0x0007) 010 Read Once word 0 value 011 Read Once word 1 value 100 Read Once word 2 value 101 Read Once word 3 value Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. 8 Table 28-39. Read Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if an invalid phrase index is supplied FSTAT 28.4.6.5 Set if command not available in current mode (see Table 28-27) FPVIOL None MGSTAT1 Set if any errors have been encountered during the read MGSTAT0 Set if any non-correctable errors have been encountered during the read Program P-Flash Command The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an embedded algorithm. CAUTION A P-Flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash phrase is not allowed. Table 28-40. Program P-Flash Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x06 Global address [17:16] to identify P-Flash block 001 Global address [15:0] of phrase location to be programmed1 010 Word 0 program value 011 Word 1 program value 100 Word 2 program value 101 Word 3 program value MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1005 96 KByte Flash Module (S12FTMRG96K1V1) 1 Global address [2:0] must be 000 Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. The CCIF flag will set after the Program P-Flash operation has completed. Table 28-41. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid global address [17:0] is supplied see Table 28-3)1 Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 1 Set if command not available in current mode (see Table 28-27) Set if the global address [17:0] points to a protected area MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation As defined by the memory map for FTMRG96K1. 28.4.6.6 Program Once Command The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in P-Flash. The Program Once reserved field can be read using the Read Once command as described in Section 28.4.6.4. The Program Once command must only be issued once since the nonvolatile information register in P-Flash cannot be erased. The Program Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 28-42. Program Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x07 Not Required 001 Program Once phrase index (0x0000 - 0x0007) 010 Program Once word 0 value 011 Program Once word 1 value 100 Program Once word 2 value 101 Program Once word 3 value Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with read back. The CCIF flag will remain clear, setting only after the Program Once operation has completed. MC9S12G Family Reference Manual Rev.1.28 1006 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) The reserved nonvolatile information register accessed by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. Table 28-43. Program Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed1 FSTAT FPVIOL 1 Set if command not available in current mode (see Table 28-27) None MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will be allowed to execute again on that same phrase. 28.4.6.7 Erase All Blocks Command The Erase All Blocks operation will erase the entire P-Flash and EEPROM memory space. Table 28-44. Erase All Blocks Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x08 Not required Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All Blocks operation has completed. Table 28-45. Erase All Blocks Command Error Handling Register Error Bit ACCERR FSTAT 1 FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 28-27) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation1 MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation1 As found in the memory map for FTMRG96K1. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1007 96 KByte Flash Module (S12FTMRG96K1V1) 28.4.6.8 Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or EEPROM block. Table 28-46. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 28-47. Erase Flash Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 28-27) ACCERR Set if the supplied P-Flash address is not phrase-aligned or if the EEPROM address is not word-aligned FSTAT FPVIOL 1 2 Set if an invalid global address [17:16] is supplied1 Set if an area of the selected Flash block is protected MGSTAT1 Set if any errors have been encountered during the verify operation2 MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation2 As defined by the memory map for FTMRG96K1. As found in the memory map for FTMRG96K1. 28.4.6.9 Erase P-Flash Sector Command The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector. Table 28-48. Erase P-Flash Sector Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x0A Global address [17:16] to identify P-Flash block to be erased Global address [15:0] anywhere within the sector to be erased. Refer to Section 28.1.2.1 for the P-Flash sector size. Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed. MC9S12G Family Reference Manual Rev.1.28 1008 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-49. Erase P-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if an invalid global address [17:16] is supplied see Table 28-3)1 Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 1 Set if command not available in current mode (see Table 28-27) Set if the selected P-Flash sector is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation As defined by the memory map for FTMRG96K1. 28.4.6.10 Unsecure Flash Command The Unsecure Flash command will erase the entire P-Flash and EEPROM memory space and, if the erase is successful, will release security. Table 28-50. Unsecure Flash Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x0B Not required Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire P-Flash and EEPROM memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. If the erase verify is not successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security state. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag is set after the Unsecure Flash operation has completed. Table 28-51. Unsecure Flash Command Error Handling Register Error Bit ACCERR FSTAT 1 FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 28-27) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation1 MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation1 As found in the memory map for FTMRG96K1. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1009 96 KByte Flash Module (S12FTMRG96K1V1) 28.4.6.11 Verify Backdoor Access Key Command The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 28-10). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see Table 28-4). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 28-52. Verify Backdoor Access Key Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0C Not required 001 Key 0 010 Key 1 011 Key 2 100 Key 3 Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash configuration field with Key 0 compared to 0x3_FF00, etc. If the backdoor keys match, security will be released. If the backdoor keys do not match, security is not released and all future attempts to execute the Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is set after the Verify Backdoor Access Key operation has completed. Table 28-53. Verify Backdoor Access Key Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 100 at command launch Set if an incorrect backdoor key is supplied ACCERR FSTAT Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see Section 28.3.2.2) Set if the backdoor key has mismatched since the last reset FPVIOL None MGSTAT1 None MGSTAT0 None 28.4.6.12 Set User Margin Level Command The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P-Flash or EEPROM block. MC9S12G Family Reference Manual Rev.1.28 1010 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-54. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0D 001 Flash block selection code [1:0]. Table 28-34 See Margin level setting. Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply user margin levels to the P-Flash block only. Valid margin level settings for the Set User Margin Level command are defined in Table 28-55. Table 28-55. Valid Set User Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state Table 28-56. Set User Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR FSTAT Set if command not available in current mode (see Table 28-27) Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 28-34 ) Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1011 96 KByte Flash Module (S12FTMRG96K1V1) NOTE User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. 28.4.6.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of the P-Flash or EEPROM block. Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the Table 28-57. Set Field Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0E 001 Flash block selection code [1:0]. Table 28-34 See Margin level setting. field margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM field margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash field margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply field margin levels to the P-Flash block only. Valid margin level settings for the Set Field Margin Level command are defined in Table 28-58. Table 28-58. Valid Set Field Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 0x0003 Field Margin-1 Level1 0x0004 Field Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state MC9S12G Family Reference Manual Rev.1.28 1012 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-59. Set Field Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR FSTAT 1 Set if command not available in current mode (see Table 28-27) Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 28-34 )1 Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None As defined by the memory map for FTMRG96K1. CAUTION Field margin levels must only be used during verify of the initial factory programming. NOTE Field margin levels can be used to check that Flash memory contents have adequate margin for data retention at the normal level setting. If unexpected results are encountered when checking Flash memory contents at field margin levels, the Flash memory contents should be erased and reprogrammed. 28.4.6.14 Erase Verify EEPROM Section Command The Erase Verify EEPROM Section command will verify that a section of code in the EEPROM is erased. The Erase Verify EEPROM Section command defines the starting point of the data to be verified and the number of words. Table 28-60. Erase Verify EEPROM Section Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x10 Global address [17:16] to identify the EEPROM block 001 Global address [15:0] of the first word to be verified 010 Number of words to be verified Upon clearing CCIF to launch the Erase Verify EEPROM Section command, the Memory Controller will verify the selected section of EEPROM memory is erased. The CCIF flag will set after the Erase Verify EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1013 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-61. Erase Verify EEPROM Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 28-27) ACCERR Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested section breaches the end of the EEPROM block FPVIOL None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. 28.4.6.15 Program EEPROM Command The Program EEPROM operation programs one to four previously erased words in the EEPROM block. The Program EEPROM operation will confirm that the targeted location(s) were successfully programmed upon completion. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Table 28-62. Program EEPROM Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x11 Global address [17:16] to identify the EEPROM block 001 Global address [15:0] of word to be programmed 010 Word 0 program value 011 Word 1 program value, if desired 100 Word 2 program value, if desired 101 Word 3 program value, if desired Upon clearing CCIF to launch the Program EEPROM command, the user-supplied words will be transferred to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program EEPROM command launch determines how many words will be programmed in the EEPROM block. The CCIF flag is set when the operation has completed. MC9S12G Family Reference Manual Rev.1.28 1014 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-63. Program EEPROM Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] < 010 at command launch Set if CCOBIX[2:0] > 101 at command launch ACCERR Set if command not available in current mode (see Table 28-27) Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested group of words breaches the end of the EEPROM block FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 28.4.6.16 Erase EEPROM Sector Command The Erase EEPROM Sector operation will erase all addresses in a sector of the EEPROM block. Table 28-64. Erase EEPROM Sector Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x12 Global address [17:16] to identify EEPROM block Global address [15:0] anywhere within the sector to be erased. See Section 28.1.2.2 for EEPROM sector size. Upon clearing CCIF to launch the Erase EEPROM Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase EEPROM Sector operation has completed. Table 28-65. Erase EEPROM Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if command not available in current mode (see Table 28-27) Set if an invalid global address [17:0] is suppliedsee Table 28-3) Set if a misaligned word address is supplied (global address [0] != 0) FSTAT FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1015 96 KByte Flash Module (S12FTMRG96K1V1) 28.4.7 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 28-66. Flash Interrupt Sources Interrupt Source Global (CCR) Mask Interrupt Flag Local Enable CCIF (FSTAT register) CCIE (FCNFG register) I Bit ECC Double Bit Fault on Flash Read DFDIF (FERSTAT register) DFDIE (FERCNFG register) I Bit ECC Single Bit Fault on Flash Read SFDIF (FERSTAT register) SFDIE (FERCNFG register) I Bit Flash Command Complete NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 28.4.7.1 Description of Flash Interrupt Operation The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed description of the register bits involved, refer to Section 28.3.2.5, “Flash Configuration Register (FCNFG)”, Section 28.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 28.3.2.7, “Flash Status Register (FSTAT)”, and Section 28.3.2.8, “Flash Error Status Register (FERSTAT)”. The logic used for generating the Flash module interrupts is shown in Figure 28-27. CCIE CCIF DFDIE DFDIF Flash Command Interrupt Request Flash Error Interrupt Request SFDIE SFDIF Figure 28-27. Flash Module Interrupts Implementation MC9S12G Family Reference Manual Rev.1.28 1016 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) 28.4.8 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 28.4.7, “Interrupts”). 28.4.9 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. 28.5 Security The Flash module provides security information to the MCU. The Flash security state is defined by the SEC bits of the FSEC register (see Table 28-11). During reset, the Flash module initializes the FSEC register using data read from the security byte of the Flash configuration field at global address 0x3_FF0F. The security state out of reset can be permanently changed by programming the security byte assuming that the MCU is starting from a mode where the necessary P-Flash erase and program commands are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset. The following subsections describe these security-related subjects: • Unsecuring the MCU using Backdoor Key Access • Unsecuring the MCU in Special Single Chip Mode using BDM • Mode and Security Effects on Flash Command Availability 28.5.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x3_FF00-0x3_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 28.3.2.2), the Verify Backdoor Access Key command (see Section 28.4.6.11) allows the user to present four prospective keys for comparison to the keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC register (see Table 28-11) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash memory and EEPROM memory will not be available for read access and will return invalid data. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1017 96 KByte Flash Module (S12FTMRG96K1V1) The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 28.3.2.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 28.4.6.11 2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10 The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method to re-enable the Verify Backdoor Access Key command. The security as defined in the Flash security byte (0x3_FF0F) is not changed by using the Verify Backdoor Access Key command sequence. The backdoor keys stored in addresses 0x3_FF00-0x3_FF07 are unaffected by the Verify Backdoor Access Key command sequence. The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection register, FPROT. After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is unsecured, the sector containing the Flash security byte can be erased and the Flash security byte can be reprogrammed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x3_FF00-0x3_FF07 in the Flash configuration field. 28.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM A secured MCU can be unsecured in special single chip mode by using the following method to erase the P-Flash and EEPROM memory: 1. Reset the MCU into special single chip mode 2. Delay while the BDM executes the Erase Verify All Blocks command write sequence to check if the P-Flash and EEPROM memories are erased 3. Send BDM commands to disable protection in the P-Flash and EEPROM memory 4. Execute the Erase All Blocks command write sequence to erase the P-Flash and EEPROM memory. Alternatively the Unsecure Flash command can be executed, if so the steps 5 and 6 below are skeeped. 5. After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into special single chip mode 6. Delay while the BDM executes the Erase Verify All Blocks command write sequence to verify that the P-Flash and EEPROM memory are erased If the P-Flash and EEPROM memory are verified as erased, the MCU will be unsecured. All BDM commands will now be enabled and the Flash security byte may be programmed to the unsecure state by continuing with the following steps: 7. Send BDM commands to execute the Program P-Flash command write sequence to program the Flash security byte to the unsecured state MC9S12G Family Reference Manual Rev.1.28 1018 NXP Semiconductors 96 KByte Flash Module (S12FTMRG96K1V1) 8. Reset the MCU 28.5.3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 28-27. 28.6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the Flash Block Configuration Parameters, the FPROT and EEPROT protection registers, and the FOPT and FSEC registers. The initialization routine reverts to built-in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence. If a double bit fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set. CCIF is cleared throughout the initialization sequence. The Flash module holds off all CPU access for a portion of the initialization sequence. Flash reads are allowed once the hold is removed. Completion of the initialization sequence is marked by setting CCIF high which enables user commands. If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1019 96 KByte Flash Module (S12FTMRG96K1V1) MC9S12G Family Reference Manual Rev.1.28 1020 NXP Semiconductors Chapter 29 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-1. Revision History Revision Number Revision Date V01.11 17 Jun 2010 29.4.6.1/29-1054 Clarify Erase Verify Commands Descriptions related to the bits MGSTAT[1:0] 29.4.6.2/29-1055 of the register FSTAT. 29.4.6.3/29-1055 29.4.6.14/29-1065 V01.12 31 Aug 2010 29.4.6.2/29-1055 Updated description of the commands RD1BLK, MLOADU and MLOADF 29.4.6.12/29-1062 29.4.6.13/29-1064 V01.13 31 Jan 2011 29.3.2.9/29-1038 29.1 Sections Affected Description of Changes Updated description of protection on Section 29.3.2.9 Introduction The FTMRG128K1 module implements the following: • 128Kbytes of P-Flash (Program Flash) memory • 4 Kbytes of EEPROM memory The Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory contents. The user interface to the memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is written to with the command, global address, data, and any required command parameters. The memory controller must complete the execution of a command before the FCCOB register can be written to with a new command. CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1021 It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory. Simultaneous P-Flash and EEPROM operations are discussed in Section 29.4.5. Both P-Flash and EEPROM memories are implemented with Error Correction Codes (ECC) that can resolve single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read by half-phrase, only one single bit fault in an aligned 4 byte half-phrase containing the byte or word accessed will be corrected. 29.1.1 Glossary Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. EEPROM Memory — The EEPROM memory constitutes the nonvolatile memory store for data. EEPROM Sector — The EEPROM sector is the smallest portion of the EEPROM memory that can be erased. The EEPROM sector consists of 4 bytes. NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters required for Flash command execution. Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double bit fault detection within each double word. P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications. P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased. Each P-Flash sector contains 512 bytes. Program IFR — Nonvolatile information register located in the P-Flash block that contains the Version ID, and the Program Once field. 29.1.2 29.1.2.1 • • • Features P-Flash Features 128 Kbytes of P-Flash memory composed of one 128 Kbyte Flash block divided into 256 sectors of 512 bytes Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1022 128 KByte Flash Module (S12FTMRG128K1V1) • • • Fast sector erase and phrase program operation Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 29.1.2.2 • • • • • • 4 Kbytes of EEPROM memory composed of one 4 Kbyte Flash block divided into 1024 sectors of 4 bytes Single bit fault correction and double bit fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Protection scheme to prevent accidental program or erase of EEPROM memory Ability to program up to four words in a burst sequence 29.1.2.3 • • • EEPROM Features Other Flash Module Features No external high-voltage power supply required for Flash memory program and erase operations Interrupt generation on Flash command completion and Flash error detection Security mechanism to prevent unauthorized access to the Flash memory 29.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 29-1. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1023 128 KByte Flash Module (S12FTMRG128K1V1) Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 32Kx39 sector 0 sector 1 Protection sector 255 Security Bus Clock Clock Divider FCLK Memory Controller CPU EEPROM 2Kx22 sector 0 sector 1 sector 1023 Figure 29-1. FTMRG128K1 Block Diagram 29.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual Rev.1.28 1024 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) 29.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed. If such action is attempted the write operation will not change the register value. Writing to the Flash registers is allowed when the Flash is not busy executing commands (CCIF = 1) and during initialization right after reset, despite the value of flag CCIF in that case (refer to Section 29.6 for a complete description of the reset sequence). . Table 29-2. FTMRG Memory Map Global Address (in Bytes) 0x0_0000 - 0x0_03FF 0x0_0400 – 0x0_13FF 0x0_4000 – 0x0_7FFF 0x2_0000 – 0x3_FFFF 1 Size (Bytes) 1,024 4,096 16,284 131,072 Description Register Space EEPROM Memory NVMRES1=1 : NVM Resource area (see Figure 29-3) P-Flash Memory See NVMRES description in Section 29.4.3 29.3.1 Module Memory Map The S12 architecture places the P-Flash memory between global addresses 0x2_0000 and 0x3_FFFF as shown in Table 29-3.The P-Flash memory map is shown in Figure 29-2. Table 29-3. P-Flash Memory Addressing Global Address Size (Bytes) 0x2_0000 – 0x3_FFFF 128 K Description P-Flash Block Contains Flash Configuration Field (see Table 29-4) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1025 128 KByte Flash Module (S12FTMRG128K1V1) The FPROT register, described in Section 29.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. Three separate memory regions, one growing upward from global address 0x3_8000 in the Flash memory (called the lower region), one growing downward from global address 0x3_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection. The Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 29-4. Table 29-4. Flash Configuration Field 1 Global Address Size (Bytes) 0x3_FF00-0x3_FF07 8 Backdoor Comparison Key Refer to Section 29.4.6.11, “Verify Backdoor Access Key Command,” and Section 29.5.1, “Unsecuring the MCU using Backdoor Key Access” 0x3_FF08-0x3_FF0B1 4 Reserved 0x3_FF0C1 1 P-Flash Protection byte. Refer to Section 29.3.2.9, “P-Flash Protection Register (FPROT)” 0x3_FF0D1 1 EEPROM Protection byte. Refer to Section 29.3.2.10, “EEPROM Protection Register (DFPROT)” 0x3_FF0E1 1 Flash Nonvolatile byte Refer to Section 29.3.2.16, “Flash Option Register (FOPT)” 0x3_FF0F1 1 Flash Security byte Refer to Section 29.3.2.2, “Flash Security Register (FSEC)” Description 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B reserved field should be programmed to 0xFF. MC9S12G Family Reference Manual Rev.1.28 1026 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) P-Flash START = 0x2_0000 Flash Protected/Unprotected Region 96 Kbytes 0x3_8000 0x3_8400 0x3_8800 0x3_9000 Protection Fixed End Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x3_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) Protection Movable End 0x3_C000 Protection Fixed End 0x3_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 P-Flash END = 0x3_FFFF Flash Configuration Field 16 bytes (0x3_FF00 - 0x3_FF0F) Figure 29-2. P-Flash Memory Map Table 29-5. Program IFR Fields Global Address Size (Bytes) 0x0_4000 – 0x0_4007 8 Reserved 0x0_4008 – 0x0_40B5 174 Reserved 0x0_40B6 – 0x0_40B7 2 Field Description Version ID1 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1027 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-5. Program IFR Fields 1 Global Address Size (Bytes) 0x0_40B8 – 0x0_40BF 8 Reserved 0x0_40C0 – 0x0_40FF 64 Program Once Field Refer to Section 29.4.6.6, “Program Once Command” Field Description Used to track firmware patch versions, see Section 29.4.2 Table 29-6. Memory Controller Resource Fields (NVMRES1=1) Global Address Size (Bytes) 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 29-5) 0x0_4100 – 0x0_41FF 256 Reserved. 0x0_4200 – 0x0_57FF 1 Description Reserved 0x0_5800 – 0x0_59FF 512 Reserved 0x0_5A00 – 0x0_5FFF 1,536 Reserved 0x0_6000 – 0x0_6BFF 3,072 Reserved 0x0_6C00 – 0x0_7FFF 5,120 Reserved NVMRES - See Section 29.4.3 for NVMRES (NVM Resource) detail. 0x0_4000 0x0_4400 RAM Start = 0x0_5800 RAM End = 0x0_59FF P-Flash IFR 1 Kbyte (NVMRES=1) Reserved 5k bytes Reserved 512 bytes Reserved 4608 bytes 0x0_6C00 Reserved 5120 bytes 0x0_7FFF Figure 29-3. Memory Controller Resource Memory Map (NVMRES=1) MC9S12G Family Reference Manual Rev.1.28 1028 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) 29.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 29.3). A summary of the Flash module registers is given in Figure 29-4 with detailed descriptions in the following subsections. Address & Name 0x0000 FCLKDIV 0x0001 FSEC 0x0002 FCCOBIX 0x0003 FRSV0 0x0004 FCNFG 0x0005 FERCNFG 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 DFPROT 7 R 6 5 4 3 2 1 0 FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0 0 0 0 0 0 0 0 0 0 0 0 0 FDFD FSFD 0 0 0 0 0 DFDIE SFDIE ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0 0 0 0 0 DFDIF SFDIF FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 DPS5 DPS4 DPS3 DPS2 DPS1 DPS0 FDIVLD W R W R W R W R W R CCIE 0 IGNSF W R W R CCIF 0 0 0 W R W R W FPOPEN DPOPEN RNV6 DPS6 Figure 29-4. FTMRG128K1 Register Summary MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1029 128 KByte Flash Module (S12FTMRG128K1V1) Address & Name 0x000A FCCOBHI 0x000B FCCOBLO 0x000C FRSV1 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT 0x0011 FRSV5 0x0012 FRSV6 0x0013 FRSV7 R W R W R 7 6 5 4 3 2 1 0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W R W R W R W R W R W = Unimplemented or Reserved Figure 29-4. FTMRG128K1 Register Summary (continued) 29.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. MC9S12G Family Reference Manual Rev.1.28 1030 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) Offset Module Base + 0x0000 7 R 6 FDIVLD W Reset 0 5 4 3 FDIVLCK 0 2 1 0 0 0 0 FDIV[5:0] 0 0 0 = Unimplemented or Reserved Figure 29-5. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). Table 29-7. FCLKDIV Field Descriptions Field 7 FDIVLD Description Clock Divider Loaded 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset 6 FDIVLCK Clock Divider Locked 0 FDIV field is open for writing 1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in normal mode. 5–0 FDIV[5:0] Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events during Flash program and erase algorithms. Table 29-8 shows recommended values for FDIV[5:0] based on the BUSCLK frequency. Please refer to Section 29.4.4, “Flash Command Operations,” for more information. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1031 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-8. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) 1 1 2 29.3.2.2 BUSCLK Frequency (MHz) FDIV[5:0] 2 1 MIN MAX FDIV[5:0] 2 MIN MAX 1.0 1.6 0x00 16.6 17.6 0x10 1.6 2.6 0x01 17.6 18.6 0x11 2.6 3.6 0x02 18.6 19.6 0x12 3.6 4.6 0x03 19.6 20.6 0x13 4.6 5.6 0x04 20.6 21.6 0x14 5.6 6.6 0x05 21.6 22.6 0x15 6.6 7.6 0x06 22.6 23.6 0x16 7.6 8.6 0x07 23.6 24.6 0x17 8.6 9.6 0x08 24.6 25.6 0x18 9.6 10.6 0x09 10.6 11.6 0x0A 11.6 12.6 0x0B 12.6 13.6 0x0C 13.6 14.6 0x0D 14.6 15.6 0x0E 15.6 16.6 0x0F BUSCLK is Greater Than this value. BUSCLK is Less Than or Equal to this value. Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 29-6. Flash Security Register (FSEC) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FSEC register are readable but not writable. During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the Flash configuration field at global address 0x3_FF0F located in P-Flash memory (see Table 29-4) as MC9S12G Family Reference Manual Rev.1.28 1032 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) indicated by reset condition F in Figure 29-6. If a double bit fault is detected while reading the P-Flash phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set to leave the Flash module in a secured state with backdoor key access disabled. Table 29-9. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the KEYEN[1:0] Flash module as shown in Table 29-10. 5–2 RNV[5:2] Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements. 1–0 SEC[1:0] Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 29-11. If the Flash module is unsecured using backdoor key access, the SEC bits are forced to 10. Table 29-10. Flash KEYEN States 1 KEYEN[1:0] Status of Backdoor Key Access 00 DISABLED 01 DISABLED1 10 ENABLED 11 DISABLED Preferred KEYEN state to disable backdoor key access. Table 29-11. Flash Security States 1 SEC[1:0] Status of Security 00 SECURED 01 SECURED1 10 UNSECURED 11 SECURED Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 29.5. 29.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations. Offset Module Base + 0x0002 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 CCOBIX[2:0] W Reset 1 0 0 0 = Unimplemented or Reserved Figure 29-7. FCCOB Index Register (FCCOBIX) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1033 128 KByte Flash Module (S12FTMRG128K1V1) CCOBIX bits are readable and writable while remaining bits read 0 and are not writable. Table 29-12. FCCOBIX Field Descriptions Field Description 2–0 CCOBIX[1:0] Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to. See 29.3.2.11 Flash Common Command Object Register (FCCOB),” for more details. 29.3.2.4 Flash Reserved0 Register (FRSV0) This Flash register is reserved for factory testing. Offset Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 29-8. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. 29.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU. Offset Module Base + 0x0004 7 R W Reset CCIE 0 6 5 0 0 0 0 4 IGNSF 0 3 2 0 0 0 0 1 0 FDFD FSFD 0 0 = Unimplemented or Reserved Figure 29-9. Flash Configuration Register (FCNFG) CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.28 1034 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-13. FCNFG Field Descriptions Field Description 7 CCIE Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command has completed. 0 Command complete interrupt disabled 1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 29.3.2.7) 4 IGNSF Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see Section 29.3.2.8). 0 All single bit faults detected during array reads are reported 1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated 1 FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. 0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected 1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see Section 29.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG register is set (see Section 29.3.2.6) 0 FSFD Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. 0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected 1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 29.3.2.7) and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see Section 29.3.2.6) 29.3.2.6 Flash Error Configuration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. Offset Module Base + 0x0005 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDIE SFDIE 0 0 = Unimplemented or Reserved Figure 29-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1035 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-14. FERCNFG Field Descriptions Field Description 1 DFDIE Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation. 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set (see Section 29.3.2.8) 0 SFDIE Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault is detected during a Flash block read operation. 0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 29.3.2.8) 1 An interrupt will be requested whenever the SFDIF flag is set (see Section 29.3.2.8) 29.3.2.7 Flash Status Register (FSTAT) The FSTAT register reports the operational status of the Flash module. Offset Module Base + 0x0006 7 R W Reset CCIF 1 6 0 0 5 4 ACCERR FPVIOL 0 0 3 2 MGBUSY RSVD 0 0 1 0 MGSTAT[1:0] 01 01 = Unimplemented or Reserved Figure 29-11. Flash Status Register (FSTAT) 1 Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 29.6). CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. Table 29-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation. 0 Flash command in progress 1 Flash command has completed 5 ACCERR Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory caused by either a violation of the command write sequence (see Section 29.4.4.2) or issuing an illegal Flash command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR. 0 No access error detected 1 Access error detected 4 FPVIOL Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of P-Flash or EEPROM memory during a command write sequence. The FPVIOL bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected 1 Protection violation detected MC9S12G Family Reference Manual Rev.1.28 1036 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-15. FSTAT Field Descriptions (continued) Field 3 MGBUSY 2 RSVD Description Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller. 0 Memory Controller is idle 1 Memory Controller is busy executing a Flash command (CCIF = 0) Reserved Bit — This bit is reserved and always reads 0. 1–0 Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See Section 29.4.6, “Flash Command Description,” and Section 29.6, “Initialization” for details. 29.3.2.8 Flash Error Status Register (FERSTAT) The FERSTAT register reflects the error status of internal Flash operations. Offset Module Base + 0x0007 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDIF SFDIF 0 0 = Unimplemented or Reserved Figure 29-12. Flash Error Status Register (FERSTAT) All flags in the FERSTAT register are readable and only writable to clear the flag. Table 29-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The DFDIF flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.2 0 No double bit fault detected 1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command running 0 SFDIF Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF. 0 No single bit fault detected 1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted while command running 1 The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either single fault or double fault but never both). A simultaneous access collision (Flash array read operation returning invalid data attempted while command running) is indicated when both SFDIF and DFDIF flags are high. 2 There is a one cycle delay in storing the ECC DFDIF and SFDIF fault flags in this register. At least one NOP is required after a flash memory read before checking FERSTAT for the occurrence of ECC errors. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1037 128 KByte Flash Module (S12FTMRG128K1V1) 29.3.2.9 P-Flash Protection Register (FPROT) The FPROT register defines which P-Flash sectors are protected against program and erase operations. Offset Module Base + 0x0008 7 R W Reset FPOPEN F1 6 5 RNV6 F1 4 FPHDIS F1 3 FPHS[1:0] F1 2 1 FPLDIS F1 F1 0 FPLS[1:0] F1 F1 = Unimplemented or Reserved Figure 29-13. Flash Protection Register (FPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected region can only be increased (see Section 29.3.2.9.1, “P-Flash Protection Restrictions,” and Table 29-21). During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte in the Flash configuration field at global address 0x3_FF0C located in P-Flash memory (see Table 29-4) as indicated by reset condition ‘F’ in Figure 29-13. To change the P-Flash protection that will be loaded during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected. Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. Table 29-17. FPROT Field Descriptions Field Description 7 FPOPEN Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or erase operations as shown in Table 29-18 for the P-Flash block. 0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits 1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits 6 RNV[6] Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements. 5 FPHDIS Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory ending with global address 0x3_FFFF. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 4–3 FPHS[1:0] Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area in P-Flash memory as shown inTable 29-19. The FPHS bits can only be written to while the FPHDIS bit is set. MC9S12G Family Reference Manual Rev.1.28 1038 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-17. FPROT Field Descriptions (continued) Field Description 2 FPLDIS Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory beginning with global address 0x3_8000. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 1–0 FPLS[1:0] Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area in P-Flash memory as shown in Table 29-20. The FPLS bits can only be written to while the FPLDIS bit is set. Table 29-18. P-Flash Protection Function 1 Function1 FPOPEN FPHDIS FPLDIS 1 1 1 No P-Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P-Flash Memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges For range sizes, refer to Table 29-19 and Table 29-20. Table 29-19. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 00 0x3_F800–0x3_FFFF 2 Kbytes 01 0x3_F000–0x3_FFFF 4 Kbytes 10 0x3_E000–0x3_FFFF 8 Kbytes 11 0x3_C000–0x3_FFFF 16 Kbytes Table 29-20. P-Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 00 0x3_8000–0x3_83FF 1 Kbyte 01 0x3_8000–0x3_87FF 2 Kbytes 10 0x3_8000–0x3_8FFF 4 Kbytes 11 0x3_8000–0x3_9FFF 8 Kbytes All possible P-Flash protection scenarios are shown in Figure 29-14 . Although the protection scheme is loaded from the Flash memory at global address 0x3_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1039 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 Scenario FLASH START FPLS[1:0] 0x3_FFFF FPHS[1:0] 0x3_8000 FPOPEN = 0 0x3_8000 FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 128 KByte Flash Module (S12FTMRG128K1V1) 0x3_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 29-14. P-Flash Protection Scenarios MC9S12G Family Reference Manual Rev.1.28 1040 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) 29.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 29-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 29-21. P-Flash Protection Scenario Transitions To Protection Scenario1 From Protection Scenario 0 1 2 3 0 X X X X X 1 X 4 X X X X X X X X X X 6 X 7 1 X 6 7 X 3 5 5 X X 2 4 X X X X X X Allowed transitions marked with X, see Figure 29-14 for a definition of the scenarios. 29.3.2.10 EEPROM Protection Register (DFPROT) The DFPROT register defines which EEPROM sectors are protected against program and erase operations. Offset Module Base + 0x0009 7 R W Reset 6 5 4 DPOPEN F1 3 2 1 0 F1 F1 F1 DPS[6:0] F1 F1 F1 F1 Figure 29-15. EEPROM Protection Register (DFPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the DFPROT register are writable with the restriction that protection can be added but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1 (protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is irrelevant. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1041 128 KByte Flash Module (S12FTMRG128K1V1) During the reset sequence, fields DPOPEN and DPS of the DFPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in P-Flash memory (see Table 29-4) as indicated by reset condition F in Table 29-23. To change the EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase containing the EEPROM protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the EEPROM memory fully protected. Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. Block erase of the EEPROM memory is not possible if any of the EEPROM sectors are protected. Table 29-22. DFPROT Field Descriptions Field Description 7 DPOPEN EEPROM Protection Control 0 Enables EEPROM memory protection from program and erase with protected address range defined by DPS bits 1 Disables EEPROM memory protection from program and erase 6–0 DPS[6:0] EEPROM Protection Size — The DPS[6:0] bits determine the size of the protected area in the EEPROM memory, this size increase in step of 32 bytes, as shown in Table 29-23 . Table 29-23. EEPROM Protection Address Range DPS[6:0] Global Address Range Protected Size 0000000 0x0_0400 – 0x0_041F 32 bytes 0000001 0x0_0400 – 0x0_043F 64 bytes 0000010 0x0_0400 – 0x0_045F 96 bytes 0000011 0x0_0400 – 0x0_047F 128 bytes 0000100 0x0_0400 – 0x0_049F 160 bytes 0000101 0x0_0400 – 0x0_04BF 192 bytes The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increasing of one. . . . 1111111 0x0_0400 – 0x0_13FF 4,096 bytes MC9S12G Family Reference Manual Rev.1.28 1042 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) 29.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. Offset Module Base + 0x000A 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[15:8] W Reset 3 0 0 0 0 Figure 29-16. Flash Common Command Object High Register (FCCOBHI) Offset Module Base + 0x000B 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[7:0] W Reset 3 0 0 0 0 Figure 29-17. Flash Common Command Object Low Register (FCCOBLO) 29.3.2.11.1 FCCOB - NVM Command Mode NVM command mode uses the indexed FCCOB register to provide a command code and its relevant parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes (as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array. The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 29-24. The return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller. Writes to the unimplemented parameter fields (CCOBIX = 110 and CCOBIX = 111) are ignored with reads from these fields returning 0x0000. Table 29-24 shows the generic Flash command format. The high byte of the first word in the CCOB array contains the command code, followed by the parameters for this specific Flash command. For details on the FCCOB settings required by each command, see the Flash command descriptions in Section 29.4.6. Table 29-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] 000 001 Byte FCCOB Parameter Fields (NVM Command Mode) HI FCMD[7:0] defining Flash command LO 6’h0, Global address [17:16] HI Global address [15:8] LO Global address [7:0] MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1043 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] 010 011 100 101 Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 0 [15:8] LO Data 0 [7:0] HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 29.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing. Offset Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 29-18. Flash Reserved1 Register (FRSV1) All bits in the FRSV1 register read 0 and are not writable. 29.3.2.13 Flash Reserved2 Register (FRSV2) This Flash register is reserved for factory testing. Offset Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 29-19. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. 29.3.2.14 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.28 1044 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) Offset Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 29-20. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 29.3.2.15 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing. Offset Module Base + 0x000F R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 29-21. Flash Reserved4 Register (FRSV4) All bits in the FRSV4 register read 0 and are not writable. 29.3.2.16 Flash Option Register (FOPT) The FOPT register is the Flash option register. Offset Module Base + 0x0010 7 6 5 4 R 3 2 1 0 F1 F1 F1 F1 NV[7:0] W Reset F1 F1 F1 F1 = Unimplemented or Reserved Figure 29-22. Flash Option Register (FOPT) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FOPT register are readable but are not writable. During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global address 0x3_FF0E located in P-Flash memory (see Table 29-4) as indicated by reset condition F in Figure 29-22. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1045 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-25. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits. 29.3.2.17 Flash Reserved5 Register (FRSV5) This Flash register is reserved for factory testing. Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 29-23. Flash Reserved5 Register (FRSV5) All bits in the FRSV5 register read 0 and are not writable. 29.3.2.18 Flash Reserved6 Register (FRSV6) This Flash register is reserved for factory testing. Offset Module Base + 0x0012 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 29-24. Flash Reserved6 Register (FRSV6) All bits in the FRSV6 register read 0 and are not writable. 29.3.2.19 Flash Reserved7 Register (FRSV7) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.28 1046 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 29-25. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. 29.4 29.4.1 Functional Description Modes of Operation The FTMRG128K1 module provides the modes of operation normal and special . The operating mode is determined by module-level inputs and affects the FCLKDIV, FCNFG, and DFPROT registers (see Table 29-27). 29.4.2 IFR Version ID Word The version ID word is stored in the IFR at address 0x0_40B6. The contents of the word are defined in Table 29-26. Table 29-26. IFR Version ID Fields [15:4] [3:0] Reserved VERNUM MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1047 128 KByte Flash Module (S12FTMRG128K1V1) • VERNUM: Version number. The first version is number 0b_0001 with both 0b_0000 and 0b_1111 meaning ‘none’. 29.4.3 Internal NVM resource (NVMRES) IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown in Table 29-5. The NVMRES global address map is shown in Table 29-6. 29.4.4 Flash Command Operations Flash command operations are used to modify Flash memory contents. The next sections describe: • How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from BUSCLK for Flash program and erase command operations • The command write sequence used to set Flash command parameters and launch execution • Valid Flash commands available for execution, according to MCU functional mode and MCU security state. 29.4.4.1 Writing the FCLKDIV Register Prior to issuing any Flash program or erase command after a reset, the user is required to write the FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz. Table 29-8 shows recommended values for the FDIV field based on BUSCLK frequency. NOTE Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash memory due to overstress. Setting FDIV too low can result in incomplete programming or erasure of the Flash memory cells. When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written, any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set. 29.4.4.2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see Section 29.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence. If CCIF is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the FCCOB register are ignored. MC9S12G Family Reference Manual Rev.1.28 1048 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) 29.4.4.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 29.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag will remain clear until the Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 29-26. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1049 128 KByte Flash Module (S12FTMRG128K1V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no Read: FSTAT register yes FCCOB Availability Check CCIF Set? yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load. Write to FCCOB register to load required command parameter. More Parameters? yes no Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 29-26. Generic Flash Command Write Sequence Flowchart MC9S12G Family Reference Manual Rev.1.28 1050 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) 29.4.4.3 Valid Flash Module Commands Table 29-27 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 29-27. Flash Commands by Mode and Security State Unsecured FCMD Command Secured NS1 SS2 NS3 SS4 0x01 Erase Verify All Blocks     0x02 Erase Verify Block     0x03 Erase Verify P-Flash Section    0x04 Read Once    0x06 Program P-Flash    0x07 Program Once    0x08 Erase All Blocks 0x09 Erase Flash Block    0x0A Erase P-Flash Sector    0x0B Unsecure Flash 0x0C Verify Backdoor Access Key  0x0D Set User Margin Level  0x0E Set Field Margin Level 0x10 Erase Verify EEPROM Section    0x11 Program EEPROM    0x12 Erase EEPROM Sector            1 Unsecured Normal Single Chip mode Unsecured Special Single Chip mode. 3 Secured Normal Single Chip mode. 4 Secured Special Single Chip mode. 2 29.4.4.4 P-Flash Commands Table 29-28 summarizes the valid P-Flash commands along with the effects of the commands on the P-Flash block and other resources within the Flash module. Table 29-28. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks Function on P-Flash Memory Verify that all P-Flash (and EEPROM) blocks are erased. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1051 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-28. P-Flash Commands FCMD Command 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the DFPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a P-Flash (or EEPROM) block. An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. 0x0A Erase P-Flash Sector 0x0B Unsecure Flash 0x0C Verify Backdoor Access Key Supports a method of releasing MCU security by verifying a set of security keys. 0x0D Set User Margin Level Specifies a user margin read level for all P-Flash blocks. 0x0E Set Field Margin Level Specifies a field margin read level for all P-Flash blocks (special modes only). 29.4.4.5 Function on P-Flash Memory Verify that a P-Flash block is erased. Verify that a given number of words starting at the address provided are erased. Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block that was previously programmed using the Program Once command. Program a phrase in a P-Flash block. Erase all bytes in a P-Flash sector. Supports a method of releasing MCU security by erasing all P-Flash (and EEPROM) blocks and verifying that all P-Flash (and EEPROM) blocks are erased. EEPROM Commands Table 29-29 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. Table 29-29. EEPROM Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block Function on EEPROM Memory Verify that all EEPROM (and P-Flash) blocks are erased. Verify that the EEPROM block is erased. MC9S12G Family Reference Manual Rev.1.28 1052 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-29. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the DFPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block. An erase of the full EEPROM block is only possible when DPOPEN bit in the DFPROT register is set prior to launching the command. 0x0B Unsecure Flash 0x0D Set User Margin Level Specifies a user margin read level for the EEPROM block. 0x0E Set Field Margin Level Specifies a field margin read level for the EEPROM block (special modes only). 0x10 Erase Verify EEPROM Section Verify that a given number of words starting at the address provided are erased. 0x11 Program EEPROM Program up to four words in the EEPROM block. 0x12 Erase EEPROM Sector Erase all bytes in a sector of the EEPROM block. 29.4.5 Supports a method of releasing MCU security by erasing all EEPROM (and P-Flash) blocks and verifying that all EEPROM (and P-Flash) blocks are erased. Allowed Simultaneous P-Flash and EEPROM Operations Only the operations marked ‘OK’ in Table 29-30 are permitted to be run simultaneously on the Program Flash and EEPROM blocks. Some operations cannot be executed simultaneously because certain hardware resources are shared by the two memories. The priority has been placed on permitting Program Flash reads while program and erase operations execute on the EEPROM, providing read (P-Flash) while write (EEPROM) functionality. Table 29-30. Allowed P-Flash and EEPROM Simultaneous Operations EEPROM Program Flash Read Read Margin Read1 Program Sector Erase OK OK OK Mass Erase2 Margin Read1 Program Sector Erase Mass Erase2 OK 1 A ‘Margin Read’ is any read after executing the margin setting commands ‘Set User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified. See the Note on margin settings in Section 29.4.6.12 and Section 29.4.6.13. 2 The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1053 128 KByte Flash Module (S12FTMRG128K1V1) 29.4.6 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence. The ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be processed by the Memory Controller: • Starting any command write sequence that programs or erases Flash memory before initializing the FCLKDIV register • Writing an invalid command as part of the command write sequence • For additional possible errors, refer to the error handling table provided for each command If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation will return invalid data if both flags SFDIF and DFDIF are set. If the SFDIF or DFDIF flags were not previously set when the invalid read operation occurred, both the SFDIF and DFDIF flags will be set. If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting any command write sequence (see Section 29.3.2.7). CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. 29.4.6.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and EEPROM blocks have been erased. Table 29-31. Erase Verify All Blocks Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x01 Not required Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks operation has completed. If all blocks are not erased, it means blank check failed, both MGSTAT bits will be set. Table 29-32. Erase Verify All Blocks Command Error Handling Register Error Bit ACCERR FPVIOL FSTAT Error Condition Set if CCOBIX[2:0] != 000 at command launch None MGSTAT1 Set if any errors have been encountered during the reador if blank check failed . MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. MC9S12G Family Reference Manual Rev.1.28 1054 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) 29.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0] bits determine which block must be verified. Table 29-33. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. Table 29-34 See Table 29-34. Flash block selection code description Selection code[1:0] Flash block to be verified 00 EEPROM 01 Invalid (ACCERR) 10 P-Flash 11 P-Flash Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that the selected P-Flash or EEPROM block is erased. The CCIF flag will set after the Erase Verify Block operation has completed.If the block is not erased, it means blank check failed, both MGSTAT bits will be set. Table 29-35. Erase Verify Block Command Error Handling Register Error Bit ACCERR FSTAT 29.4.6.3 FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if an invalid FlashBlockSelectionCode[1:0] is supplied None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. Erase Verify P-Flash Section Command The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1055 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-36. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. Table 29-37. Erase Verify P-Flash Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 29-27) ACCERR Set if an invalid global address [17:0] is supplied (see Table 29-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT Set if the requested section crosses a the P-Flash address boundary FPVIOL 29.4.6.4 None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. Read Once Command The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of P-Flash. The Read Once field is programmed using the Program Once command described in Section 29.4.6.6. The Read Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 29-38. Read Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x04 Not Required 001 Read Once phrase index (0x0000 - 0x0007) 010 Read Once word 0 value 011 Read Once word 1 value 100 Read Once word 2 value 101 Read Once word 3 value MC9S12G Family Reference Manual Rev.1.28 1056 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. 8 Table 29-39. Read Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if an invalid phrase index is supplied FSTAT 29.4.6.5 Set if command not available in current mode (see Table 29-27) FPVIOL None MGSTAT1 Set if any errors have been encountered during the read MGSTAT0 Set if any non-correctable errors have been encountered during the read Program P-Flash Command The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an embedded algorithm. CAUTION A P-Flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash phrase is not allowed. Table 29-40. Program P-Flash Command FCCOB Requirements CCOBIX[2:0] 000 1 FCCOB Parameters 0x06 Global address [17:16] to identify P-Flash block 001 Global address [15:0] of phrase location to be programmed1 010 Word 0 program value 011 Word 1 program value 100 Word 2 program value 101 Word 3 program value Global address [2:0] must be 000 Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. The CCIF flag will set after the Program P-Flash operation has completed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1057 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-41. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid global address [17:0] is supplied (see Table 29-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 29.4.6.6 Set if command not available in current mode (see Table 29-27) Set if the global address [17:0] points to a protected area MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Program Once Command The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in P-Flash. The Program Once reserved field can be read using the Read Once command as described in Section 29.4.6.4. The Program Once command must only be issued once since the nonvolatile information register in P-Flash cannot be erased. The Program Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 29-42. Program Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x07 Not Required 001 Program Once phrase index (0x0000 - 0x0007) 010 Program Once word 0 value 011 Program Once word 1 value 100 Program Once word 2 value 101 Program Once word 3 value Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with read back. The CCIF flag will remain clear, setting only after the Program Once operation has completed. The reserved nonvolatile information register accessed by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. MC9S12G Family Reference Manual Rev.1.28 1058 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-43. Program Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed1 FSTAT FPVIOL 1 Set if command not available in current mode (see Table 29-27) None MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will be allowed to execute again on that same phrase. 29.4.6.7 Erase All Blocks Command The Erase All Blocks operation will erase the entire P-Flash and EEPROM memory space. Table 29-44. Erase All Blocks Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x08 Not required Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All Blocks operation has completed. Table 29-45. Erase All Blocks Command Error Handling Register Error Bit ACCERR FSTAT 29.4.6.8 FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 29-27) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or EEPROM block. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1059 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-46. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 29-47. Erase Flash Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 29-27) ACCERR Set if the supplied P-Flash address is not phrase-aligned or if the EEPROM address is not word-aligned FSTAT FPVIOL 29.4.6.9 Set if an invalid global address [17:16] is supplied Set if an area of the selected Flash block is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Erase P-Flash Sector Command The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector. Table 29-48. Erase P-Flash Sector Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x0A Global address [17:16] to identify P-Flash block to be erased Global address [15:0] anywhere within the sector to be erased. Refer to Section 29.1.2.1 for the P-Flash sector size. Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed. MC9S12G Family Reference Manual Rev.1.28 1060 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-49. Erase P-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if command not available in current mode (see Table 29-27) Set if an invalid global address [17:16] is supplied (see Table 29-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL Set if the selected P-Flash sector is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 29.4.6.10 Unsecure Flash Command The Unsecure Flash command will erase the entire P-Flash and EEPROM memory space and, if the erase is successful, will release security. Table 29-50. Unsecure Flash Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x0B Not required Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire P-Flash and EEPROM memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. If the erase verify is not successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security state. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag is set after the Unsecure Flash operation has completed. Table 29-51. Unsecure Flash Command Error Handling Register Error Bit ACCERR FSTAT FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 29-27) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 29.4.6.11 Verify Backdoor Access Key Command The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 29-10). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1061 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-4). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 29-52. Verify Backdoor Access Key Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0C Not required 001 Key 0 010 Key 1 011 Key 2 100 Key 3 Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash configuration field with Key 0 compared to 0x3_FF00, etc. If the backdoor keys match, security will be released. If the backdoor keys do not match, security is not released and all future attempts to execute the Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is set after the Verify Backdoor Access Key operation has completed. Table 29-53. Verify Backdoor Access Key Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 100 at command launch Set if an incorrect backdoor key is supplied ACCERR FSTAT Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see Section 29.3.2.2) Set if the backdoor key has mismatched since the last reset FPVIOL None MGSTAT1 None MGSTAT0 None 29.4.6.12 Set User Margin Level Command The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P-Flash or EEPROM block. Table 29-54. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x0D Flash block selection code [1:0]. Table 29-34 See Margin level setting. MC9S12G Family Reference Manual Rev.1.28 1062 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply user margin levels to the P-Flash block only. Valid margin level settings for the Set User Margin Level command are defined in Table 29-55. Table 29-55. Valid Set User Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state Table 29-56. Set User Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR FSTAT Set if command not available in current mode (see Table 29-27) Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 29-34 ) Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None NOTE User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1063 128 KByte Flash Module (S12FTMRG128K1V1) 29.4.6.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of the P-Flash or EEPROM block. Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the Table 29-57. Set Field Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0E 001 Flash block selection code [1:0]. Table 29-34 See Margin level setting. field margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM field margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash field margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply field margin levels to the P-Flash block only. Valid margin level settings for the Set Field Margin Level command are defined in Table 29-58. Table 29-58. Valid Set Field Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 0x0003 Field Margin-1 Level1 0x0004 Field Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state MC9S12G Family Reference Manual Rev.1.28 1064 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-59. Set Field Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR FSTAT Set if command not available in current mode (see Table 29-27) Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 29-34 ) Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None CAUTION Field margin levels must only be used during verify of the initial factory programming. NOTE Field margin levels can be used to check that Flash memory contents have adequate margin for data retention at the normal level setting. If unexpected results are encountered when checking Flash memory contents at field margin levels, the Flash memory contents should be erased and reprogrammed. 29.4.6.14 Erase Verify EEPROM Section Command The Erase Verify EEPROM Section command will verify that a section of code in the EEPROM is erased. The Erase Verify EEPROM Section command defines the starting point of the data to be verified and the number of words. Table 29-60. Erase Verify EEPROM Section Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x10 Global address [17:16] to identify the EEPROM block 001 Global address [15:0] of the first word to be verified 010 Number of words to be verified Upon clearing CCIF to launch the Erase Verify EEPROM Section command, the Memory Controller will verify the selected section of EEPROM memory is erased. The CCIF flag will set after the Erase Verify EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1065 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-61. Erase Verify EEPROM Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 29-27) ACCERR Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested section breaches the end of the EEPROM block FPVIOL None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. 29.4.6.15 Program EEPROM Command The Program EEPROM operation programs one to four previously erased words in the EEPROM block. The Program EEPROM operation will confirm that the targeted location(s) were successfully programmed upon completion. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Table 29-62. Program EEPROM Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x11 Global address [17:16] to identify the EEPROM block 001 Global address [15:0] of word to be programmed 010 Word 0 program value 011 Word 1 program value, if desired 100 Word 2 program value, if desired 101 Word 3 program value, if desired Upon clearing CCIF to launch the Program EEPROM command, the user-supplied words will be transferred to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program EEPROM command launch determines how many words will be programmed in the EEPROM block. The CCIF flag is set when the operation has completed. MC9S12G Family Reference Manual Rev.1.28 1066 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-63. Program EEPROM Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] < 010 at command launch Set if CCOBIX[2:0] > 101 at command launch ACCERR Set if command not available in current mode (see Table 29-27) Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested group of words breaches the end of the EEPROM block FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 29.4.6.16 Erase EEPROM Sector Command The Erase EEPROM Sector operation will erase all addresses in a sector of the EEPROM block. Table 29-64. Erase EEPROM Sector Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x12 Global address [17:16] to identify EEPROM block Global address [15:0] anywhere within the sector to be erased. See Section 29.1.2.2 for EEPROM sector size. Upon clearing CCIF to launch the Erase EEPROM Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase EEPROM Sector operation has completed. Table 29-65. Erase EEPROM Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if command not available in current mode (see Table 29-27) Set if an invalid global address [17:0] is supplied (see Table 29-3) Set if a misaligned word address is supplied (global address [0] != 0) FSTAT FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1067 128 KByte Flash Module (S12FTMRG128K1V1) 29.4.7 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 29-66. Flash Interrupt Sources Interrupt Source Global (CCR) Mask Interrupt Flag Local Enable CCIF (FSTAT register) CCIE (FCNFG register) I Bit ECC Double Bit Fault on Flash Read DFDIF (FERSTAT register) DFDIE (FERCNFG register) I Bit ECC Single Bit Fault on Flash Read SFDIF (FERSTAT register) SFDIE (FERCNFG register) I Bit Flash Command Complete NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 29.4.7.1 Description of Flash Interrupt Operation The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed description of the register bits involved, refer to Section 29.3.2.5, “Flash Configuration Register (FCNFG)”, Section 29.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 29.3.2.7, “Flash Status Register (FSTAT)”, and Section 29.3.2.8, “Flash Error Status Register (FERSTAT)”. The logic used for generating the Flash module interrupts is shown in Figure 29-27. CCIE CCIF DFDIE DFDIF Flash Command Interrupt Request Flash Error Interrupt Request SFDIE SFDIF Figure 29-27. Flash Module Interrupts Implementation MC9S12G Family Reference Manual Rev.1.28 1068 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) 29.4.8 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 29.4.7, “Interrupts”). 29.4.9 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. 29.5 Security The Flash module provides security information to the MCU. The Flash security state is defined by the SEC bits of the FSEC register (see Table 29-11). During reset, the Flash module initializes the FSEC register using data read from the security byte of the Flash configuration field at global address 0x3_FF0F. The security state out of reset can be permanently changed by programming the security byte assuming that the MCU is starting from a mode where the necessary P-Flash erase and program commands are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset. The following subsections describe these security-related subjects: • Unsecuring the MCU using Backdoor Key Access • Unsecuring the MCU in Special Single Chip Mode using BDM • Mode and Security Effects on Flash Command Availability 29.5.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x3_FF00-0x3_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 29.3.2.2), the Verify Backdoor Access Key command (see Section 29.4.6.11) allows the user to present four prospective keys for comparison to the keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC register (see Table 29-11) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash memory and EEPROM memory will not be available for read access and will return invalid data. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1069 128 KByte Flash Module (S12FTMRG128K1V1) The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 29.3.2.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 29.4.6.11 2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10 The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method to re-enable the Verify Backdoor Access Key command. The security as defined in the Flash security byte (0x3_FF0F) is not changed by using the Verify Backdoor Access Key command sequence. The backdoor keys stored in addresses 0x3_FF00-0x3_FF07 are unaffected by the Verify Backdoor Access Key command sequence. The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection register, FPROT. After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is unsecured, the sector containing the Flash security byte can be erased and the Flash security byte can be reprogrammed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x3_FF00-0x3_FF07 in the Flash configuration field. 29.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM A secured MCU can be unsecured in special single chip mode by using the following method to erase the P-Flash and EEPROM memory: 1. Reset the MCU into special single chip mode 2. Delay while the BDM executes the Erase Verify All Blocks command write sequence to check if the P-Flash and EEPROM memories are erased 3. Send BDM commands to disable protection in the P-Flash and EEPROM memory 4. Execute the Erase All Blocks command write sequence to erase the P-Flash and EEPROM memory. Alternatively the Unsecure Flash command can be executed, if so the steps 5 and 6 below are skeeped. 5. After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into special single chip mode 6. Delay while the BDM executes the Erase Verify All Blocks command write sequence to verify that the P-Flash and EEPROM memory are erased If the P-Flash and EEPROM memory are verified as erased, the MCU will be unsecured. All BDM commands will now be enabled and the Flash security byte may be programmed to the unsecure state by continuing with the following steps: 7. Send BDM commands to execute the Program P-Flash command write sequence to program the Flash security byte to the unsecured state MC9S12G Family Reference Manual Rev.1.28 1070 NXP Semiconductors 128 KByte Flash Module (S12FTMRG128K1V1) 8. Reset the MCU 29.5.3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 29-27. 29.6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the Flash Block Configuration Parameters, the FPROT and DFPROT protection registers, and the FOPT and FSEC registers. The initialization routine reverts to built-in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence. If a double bit fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set. CCIF is cleared throughout the initialization sequence. The Flash module holds off all CPU access for a portion of the initialization sequence. Flash reads are allowed once the hold is removed. Completion of the initialization sequence is marked by setting CCIF high which enables user commands. If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1071 128 KByte Flash Module (S12FTMRG128K1V1) MC9S12G Family Reference Manual Rev.1.28 1072 NXP Semiconductors Chapter 30 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-1. Revision History Revision Number Revision Date V01.06 23 Jun 2010 30.4.6.2/30-1107 Updated description of the commands RD1BLK, MLOADU and MLOADF 30.4.6.12/30-1114 30.4.6.13/30-1115 V01.07 20 Aug 2010 30.4.6.2/30-1107 Updated description of the commands RD1BLK, MLOADU and MLOADF 30.4.6.12/30-1114 30.4.6.13/30-1115 V01.08 31 Jan 2011 30.3.2.9/30-1090 30.1 Sections Affected Description of Changes Updated description of protection on Section 30.3.2.9 Introduction The FTMRG192K2 module implements the following: • 192Kbytes of P-Flash (Program Flash) memory • 4Kbytes of EEPROM memory The Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory contents. The user interface to the memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is written to with the command, global address, data, and any required command parameters. The memory controller must complete the execution of a command before the FCCOB register can be written to with a new command. CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1073 It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory. Simultaneous P-Flash and EEPROM operations are discussed in Section 30.4.5. Both P-Flash and EEPROM memories are implemented with Error Correction Codes (ECC) that can resolve single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read by half-phrase, only one single bit fault in an aligned 4 byte half-phrase containing the byte or word accessed will be corrected. 30.1.1 Glossary Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. EEPROM Memory — The EEPROM memory constitutes the nonvolatile memory store for data. EEPROM Sector — The EEPROM sector is the smallest portion of the EEPROM memory that can be erased. The EEPROM sector consists of 4 bytes. NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters required for Flash command execution. Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double bit fault detection within each double word. P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications. P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased. Each P-Flash sector contains 512 bytes. Program IFR — Nonvolatile information register located in the P-Flash block that contains the Version ID, and the Program Once field. 30.1.2 30.1.2.1 • • • • Features P-Flash Features 192 Kbytes of P-Flash memory divided into 384 sectors of 512 bytes Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phrase program operation MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1074 192 KByte Flash Module (S12FTMRG192K2V1) • • Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 30.1.2.2 • • • • • • 4Kbytes of EEPROM memory composed of one 4 Kbyte Flash block divided into 1024 sectors of 4 bytes Single bit fault correction and double bit fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Protection scheme to prevent accidental program or erase of EEPROM memory Ability to program up to four words in a burst sequence 30.1.2.3 • • • EEPROM Features Other Flash Module Features No external high-voltage power supply required for Flash memory program and erase operations Interrupt generation on Flash command completion and Flash error detection Security mechanism to prevent unauthorized access to the Flash memory 30.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 30-1. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1075 192 KByte Flash Module (S12FTMRG192K2V1) Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 48Kx39 sector 0 sector 1 Protection sector 383 Security Bus Clock Clock Divider FCLK Memory Controller CPU EEPROM 2Kx22 sector 0 sector 1 sector 1023 Figure 30-1. FTMRG192K2 Block Diagram 30.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual Rev.1.28 1076 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) 30.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed. If such action is attempted the write operation will not change the register value. Writing to the Flash registers is allowed when the Flash is not busy executing commands (CCIF = 1) and during initialization right after reset, despite the value of flag CCIF in that case (refer to Section 30.6 for a complete description of the reset sequence). . Table 30-2. FTMRG Memory Map Global Address (in Bytes) 0x0_0000 - 0x0_03FF 1 Size (Bytes) 1,024 Description Register Space 0x0_0400 – 0x0_13FF 4,096 EEPROM Memory 0x0_4000 – 0x0_7FFF 16,284 NVMRES1=1 : NVM Resource area (see Figure 30-3) 0x0_4000 – 0x0_FFFF 49,152 FTMRG reserved area 0x1_0000 – 0x3_FFFF 196,608 P-Flash Memory See NVMRES description in Section 30.4.3 30.3.1 Module Memory Map The S12 architecture places the P-Flash memory between global addresses 0x1_0000 and 0x3_FFFF as shown in Table 30-3 .The P-Flash memory map is shown in Figure 30-2. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1077 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-3. P-Flash Memory Addressing Global Address Size (Bytes) 0x1_0000 – 0x3_FFFF 192 K Description P-Flash Block Contains Flash Configuration Field (see Table 30-4). The FPROT register, described in Section 30.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. The Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 30-4. Table 30-4. Flash Configuration Field 1 Global Address Size (Bytes) 0x3_FF00-0x3_FF07 8 Backdoor Comparison Key Refer to Section 30.4.6.11, “Verify Backdoor Access Key Command,” and Section 30.5.1, “Unsecuring the MCU using Backdoor Key Access” 0x3_FF08-0x3_FF0B1 4 Reserved 0x3_FF0C1 1 P-Flash Protection byte. Refer to Section 30.3.2.9, “P-Flash Protection Register (FPROT)” 0x3_FF0D1 1 EEPROM Protection byte. Refer to Section 30.3.2.10, “EEPROM Protection Register (EEPROT)” 0x3_FF0E1 1 Flash Nonvolatile byte Refer to Section 30.3.2.16, “Flash Option Register (FOPT)” 0x3_FF0F1 1 Flash Security byte Refer to Section 30.3.2.2, “Flash Security Register (FSEC)” Description 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B reserved field should be programmed to 0xFF. MC9S12G Family Reference Manual Rev.1.28 1078 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) P-Flash START = 0x1_0000 Flash Protected/Unprotected Region 160 Kbytes 0x3_8000 0x3_8400 0x3_8800 0x3_9000 Protection Fixed End Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x3_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) Protection Movable End 0x3_C000 Protection Fixed End 0x3_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 P-Flash END = 0x3_FFFF Flash Configuration Field 16 bytes (0x3_FF00 - 0x3_FF0F) Figure 30-2. P-Flash Memory Map Table 30-5. Program IFR Fields Global Address Size (Bytes) 0x0_4000 – 0x0_4007 8 Reserved 0x0_4008 – 0x0_40B5 174 Reserved 0x0_40B6 – 0x0_40B7 2 Field Description Version ID1 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1079 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-5. Program IFR Fields 1 Global Address Size (Bytes) 0x0_40B8 – 0x0_40BF 8 Reserved 0x0_40C0 – 0x0_40FF 64 Program Once Field Refer to Section 30.4.6.6, “Program Once Command” Field Description Used to track firmware patch versions, see Section 30.4.2 Table 30-6. Memory Controller Resource Fields (NVMRES1=1) Global Address Size (Bytes) 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 30-5) 0x0_4100 – 0x0_41FF 256 Reserved. 0x0_4200 – 0x0_57FF 1 Description Reserved 0x0_5800 – 0x0_5AFF 768 Reserved 0x0_5B00 – 0x0_5FFF 1,280 Reserved 0x0_6000 – 0x0_67FF 2,048 Reserved 0x0_6800 – 0x0_7FFF 6,144 Reserved NVMRES - See Section 30.4.3 for NVMRES (NVM Resource) detail. 0x0_4000 0x0_4100 P-Flash IFR 128 bytes (NVMRES=1) Reserved 128 bytes 0x0_4200 Reserved 5632 bytes 0x0_5800 Reserved 768 bytes 0x0_5AFF Reserved 3328 bytes 0x0_6800 Reserved 6144 bytes 0x0_7FFF Figure 30-3. Memory Controller Resource Memory Map (NVMRES=1) MC9S12G Family Reference Manual Rev.1.28 1080 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) 30.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 30.3). A summary of the Flash module registers is given in Figure 30-4 with detailed descriptions in the following subsections. Address & Name 0x0000 FCLKDIV 0x0001 FSEC 0x0002 FCCOBIX 0x0003 FRSV0 0x0004 FCNFG 0x0005 FERCNFG 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 EEPROT 7 R 6 5 4 3 2 1 0 FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0 0 0 0 0 0 0 0 0 0 0 0 0 FDFD FSFD 0 0 0 0 0 DFDIE SFDIE ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0 0 0 0 0 DFDIF SFDIF FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 DPS5 DPS4 DPS3 DPS2 DPS1 DPS0 FDIVLD W R W R W R W R W R CCIE 0 IGNSF W R W R CCIF 0 0 0 W R W R W FPOPEN DPOPEN RNV6 DPS6 Figure 30-4. FTMRG192K2 Register Summary MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1081 192 KByte Flash Module (S12FTMRG192K2V1) Address & Name 0x000A FCCOBHI 0x000B FCCOBLO 0x000C FRSV1 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT 0x0011 FRSV5 0x0012 FRSV6 0x0013 FRSV7 R W R W R 7 6 5 4 3 2 1 0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W R W R W R W R W R W = Unimplemented or Reserved Figure 30-4. FTMRG192K2 Register Summary (continued) 30.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. MC9S12G Family Reference Manual Rev.1.28 1082 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) Offset Module Base + 0x0000 7 R 6 FDIVLD W Reset 0 5 4 3 FDIVLCK 0 2 1 0 0 0 0 FDIV[5:0] 0 0 0 = Unimplemented or Reserved Figure 30-5. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). Table 30-7. FCLKDIV Field Descriptions Field 7 FDIVLD Description Clock Divider Loaded 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset 6 FDIVLCK Clock Divider Locked 0 FDIV field is open for writing 1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in normal mode. 5–0 FDIV[5:0] Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events during Flash program and erase algorithms. Table 30-8 shows recommended values for FDIV[5:0] based on the BUSCLK frequency. Please refer to Section 30.4.4, “Flash Command Operations,” for more information. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1083 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-8. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) 1 1 2 30.3.2.2 BUSCLK Frequency (MHz) FDIV[5:0] 2 1 MIN MAX FDIV[5:0] 2 MIN MAX 1.0 1.6 0x00 16.6 17.6 0x10 1.6 2.6 0x01 17.6 18.6 0x11 2.6 3.6 0x02 18.6 19.6 0x12 3.6 4.6 0x03 19.6 20.6 0x13 4.6 5.6 0x04 20.6 21.6 0x14 5.6 6.6 0x05 21.6 22.6 0x15 6.6 7.6 0x06 22.6 23.6 0x16 7.6 8.6 0x07 23.6 24.6 0x17 8.6 9.6 0x08 24.6 25.6 0x18 9.6 10.6 0x09 10.6 11.6 0x0A 11.6 12.6 0x0B 12.6 13.6 0x0C 13.6 14.6 0x0D 14.6 15.6 0x0E 15.6 16.6 0x0F BUSCLK is Greater Than this value. BUSCLK is Less Than or Equal to this value. Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 30-6. Flash Security Register (FSEC) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FSEC register are readable but not writable. During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the Flash configuration field at global address 0x3_FF0F located in P-Flash memory (see Table 30-4) as MC9S12G Family Reference Manual Rev.1.28 1084 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) indicated by reset condition F in Figure 30-6. If a double bit fault is detected while reading the P-Flash phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set to leave the Flash module in a secured state with backdoor key access disabled. Table 30-9. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the KEYEN[1:0] Flash module as shown in Table 30-10. 5–2 RNV[5:2] Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements. 1–0 SEC[1:0] Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 30-11. If the Flash module is unsecured using backdoor key access, the SEC bits are forced to 10. Table 30-10. Flash KEYEN States 1 KEYEN[1:0] Status of Backdoor Key Access 00 DISABLED 01 DISABLED1 10 ENABLED 11 DISABLED Preferred KEYEN state to disable backdoor key access. Table 30-11. Flash Security States 1 SEC[1:0] Status of Security 00 SECURED 01 SECURED1 10 UNSECURED 11 SECURED Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 30.5. 30.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations. Offset Module Base + 0x0002 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 CCOBIX[2:0] W Reset 1 0 0 0 = Unimplemented or Reserved Figure 30-7. FCCOB Index Register (FCCOBIX) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1085 192 KByte Flash Module (S12FTMRG192K2V1) CCOBIX bits are readable and writable while remaining bits read 0 and are not writable. Table 30-12. FCCOBIX Field Descriptions Field Description 2–0 CCOBIX[1:0] Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to. See 30.3.2.11 Flash Common Command Object Register (FCCOB),” for more details. 30.3.2.4 Flash Reserved0 Register (FRSV0) This Flash register is reserved for factory testing. Offset Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 30-8. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. 30.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU. Offset Module Base + 0x0004 7 R W Reset CCIE 0 6 5 0 0 0 0 4 IGNSF 0 3 2 0 0 0 0 1 0 FDFD FSFD 0 0 = Unimplemented or Reserved Figure 30-9. Flash Configuration Register (FCNFG) CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.28 1086 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-13. FCNFG Field Descriptions Field Description 7 CCIE Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command has completed. 0 Command complete interrupt disabled 1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 30.3.2.7) 4 IGNSF Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see Section 30.3.2.8). 0 All single bit faults detected during array reads are reported 1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated 1 FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. 0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected 1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see Section 30.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG register is set (see Section 30.3.2.6) 0 FSFD Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. 0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected 1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 30.3.2.7) and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see Section 30.3.2.6) 30.3.2.6 Flash Error Configuration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. Offset Module Base + 0x0005 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDIE SFDIE 0 0 = Unimplemented or Reserved Figure 30-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1087 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-14. FERCNFG Field Descriptions Field Description 1 DFDIE Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation. 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set (see Section 30.3.2.8) 0 SFDIE Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault is detected during a Flash block read operation. 0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 30.3.2.8) 1 An interrupt will be requested whenever the SFDIF flag is set (see Section 30.3.2.8) 30.3.2.7 Flash Status Register (FSTAT) The FSTAT register reports the operational status of the Flash module. Offset Module Base + 0x0006 7 R W Reset CCIF 1 6 0 0 5 4 ACCERR FPVIOL 0 0 3 2 MGBUSY RSVD 0 0 1 0 MGSTAT[1:0] 01 01 = Unimplemented or Reserved Figure 30-11. Flash Status Register (FSTAT) 1 Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 30.6). CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. Table 30-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation. 0 Flash command in progress 1 Flash command has completed 5 ACCERR Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory caused by either a violation of the command write sequence (see Section 30.4.4.2) or issuing an illegal Flash command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR. 0 No access error detected 1 Access error detected 4 FPVIOL Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of P-Flash or EEPROM memory during a command write sequence. The FPVIOL bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected 1 Protection violation detected MC9S12G Family Reference Manual Rev.1.28 1088 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-15. FSTAT Field Descriptions (continued) Field 3 MGBUSY 2 RSVD Description Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller. 0 Memory Controller is idle 1 Memory Controller is busy executing a Flash command (CCIF = 0) Reserved Bit — This bit is reserved and always reads 0. 1–0 Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See Section 30.4.6, “Flash Command Description,” and Section 30.6, “Initialization” for details. 30.3.2.8 Flash Error Status Register (FERSTAT) The FERSTAT register reflects the error status of internal Flash operations. Offset Module Base + 0x0007 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDIF SFDIF 0 0 = Unimplemented or Reserved Figure 30-12. Flash Error Status Register (FERSTAT) All flags in the FERSTAT register are readable and only writable to clear the flag. Table 30-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The DFDIF flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.2 0 No double bit fault detected 1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command running 0 SFDIF Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF. 0 No single bit fault detected 1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted while command running 1 The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either single fault or double fault but never both). A simultaneous access collision (Flash array read operation returning invalid data attempted while command running) is indicated when both SFDIF and DFDIF flags are high. 2 There is a one cycle delay in storing the ECC DFDIF and SFDIF fault flags in this register. At least one NOP is required after a flash memory read before checking FERSTAT for the occurrence of ECC errors. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1089 192 KByte Flash Module (S12FTMRG192K2V1) 30.3.2.9 P-Flash Protection Register (FPROT) The FPROT register defines which P-Flash sectors are protected against program and erase operations. Offset Module Base + 0x0008 7 R W Reset FPOPEN F1 6 5 RNV6 F1 4 FPHDIS F1 3 FPHS[1:0] F1 2 1 FPLDIS F1 F1 0 FPLS[1:0] F1 F1 = Unimplemented or Reserved Figure 30-13. Flash Protection Register (FPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected region can only be increased (see Section 30.3.2.9.1, “P-Flash Protection Restrictions,” and Table 30-21). During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte in the Flash configuration field at global address 0x3_FF0C located in P-Flash memory (see Table 30-4) as indicated by reset condition ‘F’ in Figure 30-13. To change the P-Flash protection that will be loaded during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected. Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. Table 30-17. FPROT Field Descriptions Field Description 7 FPOPEN Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or erase operations as shown in Table 30-18 for the P-Flash block. 0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits 1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits 6 RNV[6] Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements. 5 FPHDIS Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory ending with global address 0x3_FFFF. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 4–3 FPHS[1:0] Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area in P-Flash memory as shown inTable 30-19. The FPHS bits can only be written to while the FPHDIS bit is set. MC9S12G Family Reference Manual Rev.1.28 1090 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-17. FPROT Field Descriptions (continued) Field Description 2 FPLDIS Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory beginning with global address 0x3_8000. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 1–0 FPLS[1:0] Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area in P-Flash memory as shown in Table 30-20. The FPLS bits can only be written to while the FPLDIS bit is set. Table 30-18. P-Flash Protection Function 1 Function1 FPOPEN FPHDIS FPLDIS 1 1 1 No P-Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P-Flash Memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges For range sizes, refer to Table 30-19 and Table 30-20. Table 30-19. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 00 0x3_F800–0x3_FFFF 2 Kbytes 01 0x3_F000–0x3_FFFF 4 Kbytes 10 0x3_E000–0x3_FFFF 8 Kbytes 11 0x3_C000–0x3_FFFF 16 Kbytes Table 30-20. P-Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 00 0x3_8000–0x3_83FF 1 Kbyte 01 0x3_8000–0x3_87FF 2 Kbytes 10 0x3_8000–0x3_8FFF 4 Kbytes 11 0x3_8000–0x3_9FFF 8 Kbytes All possible P-Flash protection scenarios are shown in Figure 30-14 . Although the protection scheme is loaded from the Flash memory at global address 0x3_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1091 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 Scenario FLASH START FPLS[1:0] 0x3_FFFF FPHS[1:0] 0x3_8000 FPOPEN = 0 0x3_8000 FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 192 KByte Flash Module (S12FTMRG192K2V1) 0x3_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 30-14. P-Flash Protection Scenarios MC9S12G Family Reference Manual Rev.1.28 1092 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) 30.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 30-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 30-21. P-Flash Protection Scenario Transitions To Protection Scenario1 From Protection Scenario 0 1 2 3 0 X X X X X 1 X 4 X X X X X X X X X X 6 X 7 1 X 6 7 X 3 5 5 X X 2 4 X X X X X X Allowed transitions marked with X, see Figure 30-14 for a definition of the scenarios. 30.3.2.10 EEPROM Protection Register (EEPROT) The EEPROT register defines which EEPROM sectors are protected against program and erase operations. Offset Module Base + 0x0009 7 R W Reset 6 5 4 DPOPEN F1 3 2 1 0 F1 F1 F1 DPS[6:0] F1 F1 F1 F1 Figure 30-15. EEPROM Protection Register (EEPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the EEPROT register are writable with the restriction that protection can be added but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1 (protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is irrelevant. During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1093 192 KByte Flash Module (S12FTMRG192K2V1) P-Flash memory (see Table 30-4) as indicated by reset condition F in Table 30-23. To change the EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase containing the EEPROM protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the EEPROM memory fully protected. Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. Block erase of the EEPROM memory is not possible if any of the EEPROM sectors are protected. Table 30-22. EEPROT Field Descriptions Field Description 7 DPOPEN EEPROM Protection Control 0 Enables EEPROM memory protection from program and erase with protected address range defined by DPS bits 1 Disables EEPROM memory protection from program and erase 6–0 DPS[6:0] EEPROM Protection Size — The DPS[6:0] bits determine the size of the protected area in the EEPROM memory, this size increase in step of 32 bytes, as shown in Table 30-23 . Table 30-23. EEPROM Protection Address Range DPS[6:0] Global Address Range Protected Size 0000000 0x0_0400 – 0x0_041F 32 bytes 0000001 0x0_0400 – 0x0_043F 64 bytes 0000010 0x0_0400 – 0x0_045F 96 bytes 0000011 0x0_0400 – 0x0_047F 128 bytes 0000100 0x0_0400 – 0x0_049F 160 bytes 0000101 0x0_0400 – 0x0_04BF 192 bytes The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increasing of one. . . . 1111111 0x0_0400 – 0x0_13FF 4,096 bytes MC9S12G Family Reference Manual Rev.1.28 1094 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) 30.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. Offset Module Base + 0x000A 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[15:8] W Reset 3 0 0 0 0 Figure 30-16. Flash Common Command Object High Register (FCCOBHI) Offset Module Base + 0x000B 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[7:0] W Reset 3 0 0 0 0 Figure 30-17. Flash Common Command Object Low Register (FCCOBLO) 30.3.2.11.1 FCCOB - NVM Command Mode NVM command mode uses the indexed FCCOB register to provide a command code and its relevant parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes (as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array. The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 30-24. The return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller. Writes to the unimplemented parameter fields (CCOBIX = 110 and CCOBIX = 111) are ignored with reads from these fields returning 0x0000. Table 30-24 shows the generic Flash command format. The high byte of the first word in the CCOB array contains the command code, followed by the parameters for this specific Flash command. For details on the FCCOB settings required by each command, see the Flash command descriptions in Section 30.4.6. Table 30-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] 000 001 Byte FCCOB Parameter Fields (NVM Command Mode) HI FCMD[7:0] defining Flash command LO 6’h0, Global address [17:16] HI Global address [15:8] LO Global address [7:0] MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1095 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] 010 011 100 101 Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 0 [15:8] LO Data 0 [7:0] HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 30.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing. Offset Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 30-18. Flash Reserved1 Register (FRSV1) All bits in the FRSV1 register read 0 and are not writable. 30.3.2.13 Flash Reserved2 Register (FRSV2) This Flash register is reserved for factory testing. Offset Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 30-19. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. 30.3.2.14 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.28 1096 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) Offset Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 30-20. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 30.3.2.15 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing. Offset Module Base + 0x000F R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 30-21. Flash Reserved4 Register (FRSV4) All bits in the FRSV4 register read 0 and are not writable. 30.3.2.16 Flash Option Register (FOPT) The FOPT register is the Flash option register. Offset Module Base + 0x0010 7 6 5 4 R 3 2 1 0 F1 F1 F1 F1 NV[7:0] W Reset F1 F1 F1 F1 = Unimplemented or Reserved Figure 30-22. Flash Option Register (FOPT) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FOPT register are readable but are not writable. During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global address 0x3_FF0E located in P-Flash memory (see Table 30-4) as indicated by reset condition F in Figure 30-22. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1097 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-25. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits. 30.3.2.17 Flash Reserved5 Register (FRSV5) This Flash register is reserved for factory testing. Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 30-23. Flash Reserved5 Register (FRSV5) All bits in the FRSV5 register read 0 and are not writable. 30.3.2.18 Flash Reserved6 Register (FRSV6) This Flash register is reserved for factory testing. Offset Module Base + 0x0012 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 30-24. Flash Reserved6 Register (FRSV6) All bits in the FRSV6 register read 0 and are not writable. 30.3.2.19 Flash Reserved7 Register (FRSV7) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.28 1098 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 30-25. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. 30.4 30.4.1 Functional Description Modes of Operation The FTMRG192K2 module provides the modes of operation normal and special . The operating mode is determined by module-level inputs and affects the FCLKDIV, FCNFG, and EEPROT registers (see Table 30-27). 30.4.2 IFR Version ID Word The version ID word is stored in the IFR at address 0x0_40B6. The contents of the word are defined in Table 30-26. Table 30-26. IFR Version ID Fields [15:4] [3:0] Reserved VERNUM MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1099 192 KByte Flash Module (S12FTMRG192K2V1) • VERNUM: Version number. The first version is number 0b_0001 with both 0b_0000 and 0b_1111 meaning ‘none’. 30.4.3 Internal NVM resource (NVMRES) IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown in Table 30-5. The NVMRES global address map is shown in Table 30-6. 30.4.4 Flash Command Operations Flash command operations are used to modify Flash memory contents. The next sections describe: • How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from BUSCLK for Flash program and erase command operations • The command write sequence used to set Flash command parameters and launch execution • Valid Flash commands available for execution, according to MCU functional mode and MCU security state. 30.4.4.1 Writing the FCLKDIV Register Prior to issuing any Flash program or erase command after a reset, the user is required to write the FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz. Table 30-8 shows recommended values for the FDIV field based on BUSCLK frequency. NOTE Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash memory due to overstress. Setting FDIV too low can result in incomplete programming or erasure of the Flash memory cells. When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written, any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set. 30.4.4.2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see Section 30.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence. If CCIF is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the FCCOB register are ignored. MC9S12G Family Reference Manual Rev.1.28 1100 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) 30.4.4.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 30.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag will remain clear until the Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 30-26. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1101 192 KByte Flash Module (S12FTMRG192K2V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no Read: FSTAT register yes FCCOB Availability Check CCIF Set? yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load. Write to FCCOB register to load required command parameter. More Parameters? yes no Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 30-26. Generic Flash Command Write Sequence Flowchart MC9S12G Family Reference Manual Rev.1.28 1102 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) 30.4.4.3 Valid Flash Module Commands Table 30-27 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 30-27. Flash Commands by Mode and Security State Unsecured FCMD Command Secured NS1 SS2 NS3 SS4 0x01 Erase Verify All Blocks     0x02 Erase Verify Block     0x03 Erase Verify P-Flash Section    0x04 Read Once    0x06 Program P-Flash    0x07 Program Once    0x08 Erase All Blocks 0x09 Erase Flash Block    0x0A Erase P-Flash Sector    0x0B Unsecure Flash 0x0C Verify Backdoor Access Key  0x0D Set User Margin Level  0x0E Set Field Margin Level 0x10 Erase Verify EEPROM Section    0x11 Program EEPROM    0x12 Erase EEPROM Sector            1 Unsecured Normal Single Chip mode Unsecured Special Single Chip mode. 3 Secured Normal Single Chip mode. 4 Secured Special Single Chip mode. 2 30.4.4.4 P-Flash Commands Table 30-28 summarizes the valid P-Flash commands along with the effects of the commands on the P-Flash block and other resources within the Flash module. Table 30-28. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks Function on P-Flash Memory Verify that all P-Flash (and EEPROM) blocks are erased. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1103 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-28. P-Flash Commands FCMD Command 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a P-Flash (or EEPROM) block. An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. 0x0A Erase P-Flash Sector 0x0B Unsecure Flash 0x0C Verify Backdoor Access Key Supports a method of releasing MCU security by verifying a set of security keys. 0x0D Set User Margin Level Specifies a user margin read level for all P-Flash blocks. 0x0E Set Field Margin Level Specifies a field margin read level for all P-Flash blocks (special modes only). 30.4.4.5 Function on P-Flash Memory Verify that a P-Flash block is erased. Verify that a given number of words starting at the address provided are erased. Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block that was previously programmed using the Program Once command. Program a phrase in a P-Flash block. Erase all bytes in a P-Flash sector. Supports a method of releasing MCU security by erasing all P-Flash (and EEPROM) blocks and verifying that all P-Flash (and EEPROM) blocks are erased. EEPROM Commands Table 30-29 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. Table 30-29. EEPROM Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block Function on EEPROM Memory Verify that all EEPROM (and P-Flash) blocks are erased. Verify that the EEPROM block is erased. MC9S12G Family Reference Manual Rev.1.28 1104 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-29. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block. An erase of the full EEPROM block is only possible when DPOPEN bit in the EEPROT register is set prior to launching the command. 0x0B Unsecure Flash 0x0D Set User Margin Level Specifies a user margin read level for the EEPROM block. 0x0E Set Field Margin Level Specifies a field margin read level for the EEPROM block (special modes only). 0x10 Erase Verify EEPROM Section Verify that a given number of words starting at the address provided are erased. 0x11 Program EEPROM Program up to four words in the EEPROM block. 0x12 Erase EEPROM Sector Erase all bytes in a sector of the EEPROM block. 30.4.5 Supports a method of releasing MCU security by erasing all EEPROM (and P-Flash) blocks and verifying that all EEPROM (and P-Flash) blocks are erased. Allowed Simultaneous P-Flash and EEPROM Operations Only the operations marked ‘OK’ in Table 30-30 are permitted to be run simultaneously on the Program Flash and EEPROM blocks. Some operations cannot be executed simultaneously because certain hardware resources are shared by the two memories. The priority has been placed on permitting Program Flash reads while program and erase operations execute on the EEPROM, providing read (P-Flash) while write (EEPROM) functionality. Table 30-30. Allowed P-Flash and EEPROM Simultaneous Operations EEPROM Program Flash Read Read Margin Read1 Program Sector Erase OK OK OK Mass Erase2 Margin Read1 Program Sector Erase Mass Erase2 OK 1 A ‘Margin Read’ is any read after executing the margin setting commands ‘Set User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified. See the Note on margin settings in Section 30.4.6.12 and Section 30.4.6.13. 2 The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1105 192 KByte Flash Module (S12FTMRG192K2V1) 30.4.6 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence. The ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be processed by the Memory Controller: • Starting any command write sequence that programs or erases Flash memory before initializing the FCLKDIV register • Writing an invalid command as part of the command write sequence • For additional possible errors, refer to the error handling table provided for each command If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation will return invalid data if both flags SFDIF and DFDIF are set. If the SFDIF or DFDIF flags were not previously set when the invalid read operation occurred, both the SFDIF and DFDIF flags will be set. If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting any command write sequence (see Section 30.3.2.7). CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. 30.4.6.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and EEPROM blocks have been erased. Table 30-31. Erase Verify All Blocks Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x01 Not required Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks operation has completed. If all blocks are not erased, it means blank check failed, both MGSTAT bits will be set. Table 30-32. Erase Verify All Blocks Command Error Handling Register Error Bit ACCERR FPVIOL FSTAT Error Condition Set if CCOBIX[2:0] != 000 at command launch None MGSTAT1 Set if any errors have been encountered during the reador if blank check failed . MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. MC9S12G Family Reference Manual Rev.1.28 1106 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) 30.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0]bits determine which block must be verified. Table 30-33. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. Table 30-34 See Table 30-34. Flash block selection code description Selection code[1:0] Flash block to be verified 00 EEPROM 01 P-Flash 10 P-Flash 11 P-Flash Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that the selected P-Flash or EEPROM block is erased. The CCIF flag will set after the Erase Verify Block operation has completed.If the block is not erased, it means blank check failed, both MGSTAT bits will be set. Table 30-35. Erase Verify Block Command Error Handling Register Error Bit ACCERR FPVIOL FSTAT 30.4.6.3 Error Condition Set if CCOBIX[2:0] != 000 at command launch. None. MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read1 or if blank check failed. Erase Verify P-Flash Section Command The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1107 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-36. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. Table 30-37. Erase Verify P-Flash Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 30-27) ACCERR Set if an invalid global address [17:0] is supplied see Table 30-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT Set if the requested section crosses a the P-Flash address boundary FPVIOL 30.4.6.4 None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. Read Once Command The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of P-Flash. The Read Once field is programmed using the Program Once command described in Section 30.4.6.6. The Read Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 30-38. Read Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x04 Not Required 001 Read Once phrase index (0x0000 - 0x0007) 010 Read Once word 0 value 011 Read Once word 1 value 100 Read Once word 2 value 101 Read Once word 3 value MC9S12G Family Reference Manual Rev.1.28 1108 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. 8 Table 30-39. Read Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if an invalid phrase index is supplied FSTAT 30.4.6.5 Set if command not available in current mode (see Table 30-27) FPVIOL None MGSTAT1 Set if any errors have been encountered during the read MGSTAT0 Set if any non-correctable errors have been encountered during the read Program P-Flash Command The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an embedded algorithm. CAUTION A P-Flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash phrase is not allowed. Table 30-40. Program P-Flash Command FCCOB Requirements CCOBIX[2:0] 000 1 FCCOB Parameters 0x06 Global address [17:16] to identify P-Flash block 001 Global address [15:0] of phrase location to be programmed1 010 Word 0 program value 011 Word 1 program value 100 Word 2 program value 101 Word 3 program value Global address [2:0] must be 000 Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. The CCIF flag will set after the Program P-Flash operation has completed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1109 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-41. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid global address [17:0] is supplied see Table 30-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 30.4.6.6 Set if command not available in current mode (see Table 30-27) Set if the global address [17:0] points to a protected area MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Program Once Command The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in P-Flash. The Program Once reserved field can be read using the Read Once command as described in Section 30.4.6.4. The Program Once command must only be issued once since the nonvolatile information register in P-Flash cannot be erased. The Program Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 30-42. Program Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x07 Not Required 001 Program Once phrase index (0x0000 - 0x0007) 010 Program Once word 0 value 011 Program Once word 1 value 100 Program Once word 2 value 101 Program Once word 3 value Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with read back. The CCIF flag will remain clear, setting only after the Program Once operation has completed. The reserved nonvolatile information register accessed by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. MC9S12G Family Reference Manual Rev.1.28 1110 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-43. Program Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed1 FSTAT FPVIOL 1 Set if command not available in current mode (see Table 30-27) None MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will be allowed to execute again on that same phrase. 30.4.6.7 Erase All Blocks Command The Erase All Blocks operation will erase the entire P-Flash and EEPROM memory space. Table 30-44. Erase All Blocks Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x08 Not required Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All Blocks operation has completed. Table 30-45. Erase All Blocks Command Error Handling Register Error Bit ACCERR FSTAT 30.4.6.8 FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 30-27) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or EEPROM block. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1111 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-46. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 30-47. Erase Flash Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 30-27) ACCERR Set if the supplied P-Flash address is not phrase-aligned or if the EEPROM address is not word-aligned FSTAT FPVIOL 30.4.6.9 Set if an invalid global address [17:16] is supplied Set if an area of the selected Flash block is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Erase P-Flash Sector Command The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector. Table 30-48. Erase P-Flash Sector Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x0A Global address [17:16] to identify P-Flash block to be erased Global address [15:0] anywhere within the sector to be erased. Refer to Section 30.1.2.1 for the P-Flash sector size. Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed. MC9S12G Family Reference Manual Rev.1.28 1112 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-49. Erase P-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if command not available in current mode (see Table 30-27) Set if an invalid global address [17:16] is supplied see Table 30-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL Set if the selected P-Flash sector is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 30.4.6.10 Unsecure Flash Command The Unsecure Flash command will erase the entire P-Flash and EEPROM memory space and, if the erase is successful, will release security. Table 30-50. Unsecure Flash Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x0B Not required Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire P-Flash and EEPROM memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. If the erase verify is not successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security state. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag is set after the Unsecure Flash operation has completed. Table 30-51. Unsecure Flash Command Error Handling Register Error Bit ACCERR FSTAT FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 30-27) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 30.4.6.11 Verify Backdoor Access Key Command The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 30-10). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1113 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-4). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 30-52. Verify Backdoor Access Key Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0C Not required 001 Key 0 010 Key 1 011 Key 2 100 Key 3 Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash configuration field with Key 0 compared to 0x3_FF00, etc. If the backdoor keys match, security will be released. If the backdoor keys do not match, security is not released and all future attempts to execute the Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is set after the Verify Backdoor Access Key operation has completed. Table 30-53. Verify Backdoor Access Key Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 100 at command launch Set if an incorrect backdoor key is supplied ACCERR FSTAT Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see Section 30.3.2.2) Set if the backdoor key has mismatched since the last reset FPVIOL None MGSTAT1 None MGSTAT0 None 30.4.6.12 Set User Margin Level Command The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P-Flash or EEPROM block. Table 30-54. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x0D Flash block selection code [1:0]. Table 30-34 See Margin level setting. MC9S12G Family Reference Manual Rev.1.28 1114 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply user margin levels to the P-Flash block only. Valid margin level settings for the Set User Margin Level command are defined in Table 30-55. Table 30-55. Valid Set User Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state Table 30-56. Set User Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch. ACCERR Set if command not available in current mode (see Table 30-27). Set if an invalid margin level setting is supplied. FSTAT FPVIOL None MGSTAT1 None MGSTAT0 None NOTE User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. 30.4.6.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of the P-Flash or EEPROM block. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1115 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-57. Set Field Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0E 001 Flash block selection code [1:0]. Table 30-34 See Margin level setting. Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the field margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM field margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash field margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply field margin levels to the P-Flash block only. Valid margin level settings for the Set Field Margin Level command are defined in Table 30-58. Table 30-58. Valid Set Field Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 0x0003 Field Margin-1 Level1 0x0004 Field Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state Table 30-59. Set Field Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch. ACCERR FSTAT Set if command not available in current mode (see Table 30-27). Set if an invalid margin level setting is supplied. FPVIOL None MGSTAT1 None MGSTAT0 None MC9S12G Family Reference Manual Rev.1.28 1116 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) CAUTION Field margin levels must only be used during verify of the initial factory programming. NOTE Field margin levels can be used to check that Flash memory contents have adequate margin for data retention at the normal level setting. If unexpected results are encountered when checking Flash memory contents at field margin levels, the Flash memory contents should be erased and reprogrammed. 30.4.6.14 Erase Verify EEPROM Section Command The Erase Verify EEPROM Section command will verify that a section of code in the EEPROM is erased. The Erase Verify EEPROM Section command defines the starting point of the data to be verified and the number of words. Table 30-60. Erase Verify EEPROM Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x10 Global address [17:16] to identify the EEPROM block 001 Global address [15:0] of the first word to be verified 010 Number of words to be verified Upon clearing CCIF to launch the Erase Verify EEPROM Section command, the Memory Controller will verify the selected section of EEPROM memory is erased. The CCIF flag will set after the Erase Verify EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. Table 30-61. Erase Verify EEPROM Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 30-27) ACCERR Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested section breaches the end of the EEPROM block FPVIOL None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1117 192 KByte Flash Module (S12FTMRG192K2V1) 30.4.6.15 Program EEPROM Command The Program EEPROM operation programs one to four previously erased words in the EEPROM block. The Program EEPROM operation will confirm that the targeted location(s) were successfully programmed upon completion. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Table 30-62. Program EEPROM Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters Global address [17:16] to identify the EEPROM block 0x11 001 Global address [15:0] of word to be programmed 010 Word 0 program value 011 Word 1 program value, if desired 100 Word 2 program value, if desired 101 Word 3 program value, if desired Upon clearing CCIF to launch the Program EEPROM command, the user-supplied words will be transferred to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program EEPROM command launch determines how many words will be programmed in the EEPROM block. The CCIF flag is set when the operation has completed. Table 30-63. Program EEPROM Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] < 010 at command launch Set if CCOBIX[2:0] > 101 at command launch ACCERR Set if command not available in current mode (see Table 30-27) Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested group of words breaches the end of the EEPROM block FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 30.4.6.16 Erase EEPROM Sector Command The Erase EEPROM Sector operation will erase all addresses in a sector of the EEPROM block. MC9S12G Family Reference Manual Rev.1.28 1118 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-64. Erase EEPROM Sector Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 001 0x12 Global address [17:16] to identify EEPROM block Global address [15:0] anywhere within the sector to be erased. See Section 30.1.2.2 for EEPROM sector size. Upon clearing CCIF to launch the Erase EEPROM Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase EEPROM Sector operation has completed. Table 30-65. Erase EEPROM Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if an invalid global address [17:0] is suppliedsee Table 30-3) Set if a misaligned word address is supplied (global address [0] != 0) FSTAT FPVIOL 30.4.7 Set if command not available in current mode (see Table 30-27) Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 30-66. Flash Interrupt Sources Interrupt Source Global (CCR) Mask Interrupt Flag Local Enable CCIF (FSTAT register) CCIE (FCNFG register) I Bit ECC Double Bit Fault on Flash Read DFDIF (FERSTAT register) DFDIE (FERCNFG register) I Bit ECC Single Bit Fault on Flash Read SFDIF (FERSTAT register) SFDIE (FERCNFG register) I Bit Flash Command Complete MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1119 192 KByte Flash Module (S12FTMRG192K2V1) NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 30.4.7.1 Description of Flash Interrupt Operation The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed description of the register bits involved, refer to Section 30.3.2.5, “Flash Configuration Register (FCNFG)”, Section 30.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 30.3.2.7, “Flash Status Register (FSTAT)”, and Section 30.3.2.8, “Flash Error Status Register (FERSTAT)”. The logic used for generating the Flash module interrupts is shown in Figure 30-27. Flash Command Interrupt Request CCIE CCIF DFDIE DFDIF Flash Error Interrupt Request SFDIE SFDIF Figure 30-27. Flash Module Interrupts Implementation 30.4.8 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 30.4.7, “Interrupts”). 30.4.9 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. MC9S12G Family Reference Manual Rev.1.28 1120 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) 30.5 Security The Flash module provides security information to the MCU. The Flash security state is defined by the SEC bits of the FSEC register (see Table 30-11). During reset, the Flash module initializes the FSEC register using data read from the security byte of the Flash configuration field at global address 0x3_FF0F. The security state out of reset can be permanently changed by programming the security byte assuming that the MCU is starting from a mode where the necessary P-Flash erase and program commands are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset. The following subsections describe these security-related subjects: • Unsecuring the MCU using Backdoor Key Access • Unsecuring the MCU in Special Single Chip Mode using BDM • Mode and Security Effects on Flash Command Availability 30.5.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x3_FF00-0x3_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 30.3.2.2), the Verify Backdoor Access Key command (see Section 30.4.6.11) allows the user to present four prospective keys for comparison to the keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC register (see Table 30-11) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash memory and EEPROM memory will not be available for read access and will return invalid data. The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 30.3.2.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 30.4.6.11 2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10 The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method to re-enable the Verify Backdoor Access Key command. The security as defined in the Flash security byte (0x3_FF0F) is not changed by using the Verify Backdoor Access Key command sequence. The backdoor keys stored in addresses 0x3_FF00-0x3_FF07 are unaffected by the Verify Backdoor Access Key command sequence. The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection register, FPROT. After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is unsecured, the sector containing the Flash security byte can be erased and the Flash security byte can be MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1121 192 KByte Flash Module (S12FTMRG192K2V1) reprogrammed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x3_FF00-0x3_FF07 in the Flash configuration field. 30.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM A secured MCU can be unsecured in special single chip mode by using the following method to erase the P-Flash and EEPROM memory: 1. Reset the MCU into special single chip mode 2. Delay while the BDM executes the Erase Verify All Blocks command write sequence to check if the P-Flash and EEPROM memories are erased 3. Send BDM commands to disable protection in the P-Flash and EEPROM memory 4. Execute the Erase All Blocks command write sequence to erase the P-Flash and EEPROM memory. Alternatively the Unsecure Flash command can be executed, if so the steps 5 and 6 below are skeeped. 5. After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into special single chip mode 6. Delay while the BDM executes the Erase Verify All Blocks command write sequence to verify that the P-Flash and EEPROM memory are erased If the P-Flash and EEPROM memory are verified as erased, the MCU will be unsecured. All BDM commands will now be enabled and the Flash security byte may be programmed to the unsecure state by continuing with the following steps: 7. Send BDM commands to execute the Program P-Flash command write sequence to program the Flash security byte to the unsecured state 8. Reset the MCU 30.5.3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 30-27. 30.6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the Flash Block Configuration Parameters, the FPROT and EEPROT protection registers, and the FOPT and FSEC registers. The initialization routine reverts to built-in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence. If a double bit fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set. CCIF is cleared throughout the initialization sequence. The Flash module holds off all CPU access for a portion of the initialization sequence. Flash reads are allowed once the hold is removed. Completion of the initialization sequence is marked by setting CCIF high which enables user commands. MC9S12G Family Reference Manual Rev.1.28 1122 NXP Semiconductors 192 KByte Flash Module (S12FTMRG192K2V1) If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1123 192 KByte Flash Module (S12FTMRG192K2V1) MC9S12G Family Reference Manual Rev.1.28 1124 NXP Semiconductors Chapter 31 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-1. Revision History Revision Number Revision Date V01.06 23 Jun 2010 31.4.6.2/31-1159 Updated description of the commands RD1BLK, MLOADU and MLOADF 31.4.6.12/31-1166 31.4.6.13/31-1167 V01.07 20 Aug 2010 31.4.6.2/31-1159 Updated description of the commands RD1BLK, MLOADU and MLOADF 31.4.6.12/31-1166 31.4.6.13/31-1167 V01.08 31 Jan 2011 31.3.2.9/31-1142 31.1 Sections Affected Description of Changes Updated description of protection on Section 31.3.2.9 Introduction The FTMRG240K2 module implements the following: • 240Kbytes of P-Flash (Program Flash) memory • 4Kbytes of EEPROM memory The Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory contents. The user interface to the memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is written to with the command, global address, data, and any required command parameters. The memory controller must complete the execution of a command before the FCCOB register can be written to with a new command. CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1125 It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory. Simultaneous P-Flash and EEPROM operations are discussed in Section 31.4.5. Both P-Flash and EEPROM memories are implemented with Error Correction Codes (ECC) that can resolve single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read by half-phrase, only one single bit fault in an aligned 4 byte half-phrase containing the byte or word accessed will be corrected. 31.1.1 Glossary Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. EEPROM Memory — The EEPROM memory constitutes the nonvolatile memory store for data. EEPROM Sector — The EEPROM sector is the smallest portion of the EEPROM memory that can be erased. The EEPROM sector consists of 4 bytes. NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters required for Flash command execution. Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double bit fault detection within each double word. P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications. P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased. Each P-Flash sector contains 512 bytes. Program IFR — Nonvolatile information register located in the P-Flash block that contains the Version ID, and the Program Once field. 31.1.2 31.1.2.1 • • • • Features P-Flash Features 240 Kbytes of P-Flash memory divided into 480 sectors of 512 bytes Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phrase program operation MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1126 240 KByte Flash Module (S12FTMRG240K2V1) • • Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 31.1.2.2 • • • • • • 4 Kbytes of EEPROM memory composed of one 4 Kbyte Flash block divided into 1024 sectors of 4 bytes Single bit fault correction and double bit fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Protection scheme to prevent accidental program or erase of EEPROM memory Ability to program up to four words in a burst sequence 31.1.2.3 • • • EEPROM Features Other Flash Module Features No external high-voltage power supply required for Flash memory program and erase operations Interrupt generation on Flash command completion and Flash error detection Security mechanism to prevent unauthorized access to the Flash memory 31.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 31-1. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1127 240 KByte Flash Module (S12FTMRG240K2V1) Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 60Kx39 sector 0 sector 1 Protection sector 479 Security Bus Clock Clock Divider FCLK Memory Controller CPU EEPROM 2Kx22 sector 0 sector 1 sector 1023 Figure 31-1. FTMRG240K2 Block Diagram 31.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual Rev.1.28 1128 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) 31.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed. If such action is attempted the write operation will not change the register value. Writing to the Flash registers is allowed when the Flash is not busy executing commands (CCIF = 1) and during initialization right after reset, despite the value of flag CCIF in that case (refer to Section 31.6 for a complete description of the reset sequence). . Table 31-2. FTMRG Memory Map Global Address (in Bytes) 0x0_0000 - 0x0_03FF 1 Size (Bytes) 1,024 Description Register Space 0x0_0400 – 0x0_13FF 4,096 EEPROM Memory 0x0_4000 – 0x0_7FFF 16,284 NVMRES=0 : P-Flash Memory area active 0x0_4000 – 0x0_7FFF 16,284 NVMRES1=1 : NVM Resource area (see Figure 31-3) 0x0_8000 – 0x3_FFFF 229,376 P-Flash Memory See NVMRES description in Section 31.4.3 31.3.1 Module Memory Map The S12 architecture places the P-Flash memory between global addresses 0x0_4000 and 0x3_FFFF as shown in Table 31-3 .The P-Flash memory map is shown in Figure 31-2. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1129 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-3. P-Flash Memory Addressing Global Address Size (Bytes) 0x0_4000 – 0x3_FFFF 240 K Description P-Flash Block Contains Flash Configuration Field (see Table 31-4). The FPROT register, described in Section 31.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. The Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 31-4. Table 31-4. Flash Configuration Field 1 Global Address Size (Bytes) 0x3_FF00-0x3_FF07 8 Backdoor Comparison Key Refer to Section 31.4.6.11, “Verify Backdoor Access Key Command,” and Section 31.5.1, “Unsecuring the MCU using Backdoor Key Access” 0x3_FF08-0x3_FF0B1 4 Reserved 0x3_FF0C1 1 P-Flash Protection byte. Refer to Section 31.3.2.9, “P-Flash Protection Register (FPROT)” 0x3_FF0D1 1 EEPROM Protection byte. Refer to Section 31.3.2.10, “EEPROM Protection Register (EEPROT)” 0x3_FF0E1 1 Flash Nonvolatile byte Refer to Section 31.3.2.16, “Flash Option Register (FOPT)” 0x3_FF0F1 1 Flash Security byte Refer to Section 31.3.2.2, “Flash Security Register (FSEC)” Description 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B reserved field should be programmed to 0xFF. MC9S12G Family Reference Manual Rev.1.28 1130 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) P-Flash START = 0x0_4000 Flash Protected/Unprotected Region 208 Kbytes 0x3_8000 0x3_8400 0x3_8800 0x3_9000 Protection Fixed End Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x3_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) Protection Movable End 0x3_C000 Protection Fixed End 0x3_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 P-Flash END = 0x3_FFFF Flash Configuration Field 16 bytes (0x3_FF00 - 0x3_FF0F) Figure 31-2. P-Flash Memory Map Table 31-5. Program IFR Fields Global Address Size (Bytes) 0x0_4000 – 0x0_4007 8 Reserved 0x0_4008 – 0x0_40B5 174 Reserved 0x0_40B6 – 0x0_40B7 2 Field Description Version ID1 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1131 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-5. Program IFR Fields 1 Global Address Size (Bytes) 0x0_40B8 – 0x0_40BF 8 Reserved 0x0_40C0 – 0x0_40FF 64 Program Once Field Refer to Section 31.4.6.6, “Program Once Command” Field Description Used to track firmware patch versions, see Section 31.4.2 Table 31-6. Memory Controller Resource Fields (NVMRES1=1) Global Address Size (Bytes) 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 31-5) 0x0_4100 – 0x0_41FF 256 Reserved. 0x0_4200 – 0x0_57FF 1 Description Reserved 0x0_5800 – 0x0_5AFF 768 Reserved 0x0_5B00 – 0x0_5FFF 1,280 Reserved 0x0_6000 – 0x0_67FF 2,048 Reserved 0x0_6800 – 0x0_7FFF 6,144 Reserved NVMRES - See Section 31.4.3 for NVMRES (NVM Resource) detail. 0x0_4000 0x0_4100 P-Flash IFR 128 bytes (NVMRES=1) Reserved 128 bytes 0x0_4200 Reserved 5632 bytes 0x0_5800 Reserved 768 bytes 0x0_5AFF Reserved 3328 bytes 0x0_6800 Reserved 6144 bytes 0x0_7FFF Figure 31-3. Memory Controller Resource Memory Map (NVMRES=1) MC9S12G Family Reference Manual Rev.1.28 1132 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) 31.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 31.3). A summary of the Flash module registers is given in Figure 31-4 with detailed descriptions in the following subsections. Address & Name 0x0000 FCLKDIV 0x0001 FSEC 0x0002 FCCOBIX 0x0003 FRSV0 0x0004 FCNFG 0x0005 FERCNFG 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 EEPROT 7 R 6 5 4 3 2 1 0 FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0 0 0 0 0 0 0 0 0 0 0 0 0 FDFD FSFD 0 0 0 0 0 DFDIE SFDIE ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0 0 0 0 0 DFDIF SFDIF FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 DPS5 DPS4 DPS3 DPS2 DPS1 DPS0 FDIVLD W R W R W R W R W R CCIE 0 IGNSF W R W R CCIF 0 0 0 W R W R W FPOPEN DPOPEN RNV6 DPS6 Figure 31-4. FTMRG240K2 Register Summary MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1133 240 KByte Flash Module (S12FTMRG240K2V1) Address & Name 0x000A FCCOBHI 0x000B FCCOBLO 0x000C FRSV1 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT 0x0011 FRSV5 0x0012 FRSV6 0x0013 FRSV7 R W R W R 7 6 5 4 3 2 1 0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W R W R W R W R W R W = Unimplemented or Reserved Figure 31-4. FTMRG240K2 Register Summary (continued) 31.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. MC9S12G Family Reference Manual Rev.1.28 1134 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) Offset Module Base + 0x0000 7 R 6 FDIVLD W Reset 0 5 4 3 FDIVLCK 0 2 1 0 0 0 0 FDIV[5:0] 0 0 0 = Unimplemented or Reserved Figure 31-5. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). Table 31-7. FCLKDIV Field Descriptions Field 7 FDIVLD Description Clock Divider Loaded 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset 6 FDIVLCK Clock Divider Locked 0 FDIV field is open for writing 1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in normal mode. 5–0 FDIV[5:0] Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events during Flash program and erase algorithms. Table 31-8 shows recommended values for FDIV[5:0] based on the BUSCLK frequency. Please refer to Section 31.4.4, “Flash Command Operations,” for more information. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1135 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-8. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) 1 1 2 31.3.2.2 BUSCLK Frequency (MHz) FDIV[5:0] 2 1 MIN MAX FDIV[5:0] 2 MIN MAX 1.0 1.6 0x00 16.6 17.6 0x10 1.6 2.6 0x01 17.6 18.6 0x11 2.6 3.6 0x02 18.6 19.6 0x12 3.6 4.6 0x03 19.6 20.6 0x13 4.6 5.6 0x04 20.6 21.6 0x14 5.6 6.6 0x05 21.6 22.6 0x15 6.6 7.6 0x06 22.6 23.6 0x16 7.6 8.6 0x07 23.6 24.6 0x17 8.6 9.6 0x08 24.6 25.6 0x18 9.6 10.6 0x09 10.6 11.6 0x0A 11.6 12.6 0x0B 12.6 13.6 0x0C 13.6 14.6 0x0D 14.6 15.6 0x0E 15.6 16.6 0x0F BUSCLK is Greater Than this value. BUSCLK is Less Than or Equal to this value. Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 31-6. Flash Security Register (FSEC) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FSEC register are readable but not writable. During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the Flash configuration field at global address 0x3_FF0F located in P-Flash memory (see Table 31-4) as MC9S12G Family Reference Manual Rev.1.28 1136 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) indicated by reset condition F in Figure 31-6. If a double bit fault is detected while reading the P-Flash phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set to leave the Flash module in a secured state with backdoor key access disabled. Table 31-9. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the KEYEN[1:0] Flash module as shown in Table 31-10. 5–2 RNV[5:2] Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements. 1–0 SEC[1:0] Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 31-11. If the Flash module is unsecured using backdoor key access, the SEC bits are forced to 10. Table 31-10. Flash KEYEN States 1 KEYEN[1:0] Status of Backdoor Key Access 00 DISABLED 01 DISABLED1 10 ENABLED 11 DISABLED Preferred KEYEN state to disable backdoor key access. Table 31-11. Flash Security States 1 SEC[1:0] Status of Security 00 SECURED 01 SECURED1 10 UNSECURED 11 SECURED Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 31.5. 31.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations. Offset Module Base + 0x0002 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 CCOBIX[2:0] W Reset 1 0 0 0 = Unimplemented or Reserved Figure 31-7. FCCOB Index Register (FCCOBIX) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1137 240 KByte Flash Module (S12FTMRG240K2V1) CCOBIX bits are readable and writable while remaining bits read 0 and are not writable. Table 31-12. FCCOBIX Field Descriptions Field Description 2–0 CCOBIX[1:0] Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to. See 31.3.2.11 Flash Common Command Object Register (FCCOB),” for more details. 31.3.2.4 Flash Reserved0 Register (FRSV0) This Flash register is reserved for factory testing. Offset Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 31-8. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. 31.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU. Offset Module Base + 0x0004 7 R W Reset CCIE 0 6 5 0 0 0 0 4 IGNSF 0 3 2 0 0 0 0 1 0 FDFD FSFD 0 0 = Unimplemented or Reserved Figure 31-9. Flash Configuration Register (FCNFG) CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.28 1138 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-13. FCNFG Field Descriptions Field Description 7 CCIE Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command has completed. 0 Command complete interrupt disabled 1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 31.3.2.7) 4 IGNSF Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see Section 31.3.2.8). 0 All single bit faults detected during array reads are reported 1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated 1 FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. 0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected 1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see Section 31.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG register is set (see Section 31.3.2.6) 0 FSFD Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. 0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected 1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 31.3.2.7) and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see Section 31.3.2.6) 31.3.2.6 Flash Error Configuration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. Offset Module Base + 0x0005 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDIE SFDIE 0 0 = Unimplemented or Reserved Figure 31-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1139 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-14. FERCNFG Field Descriptions Field Description 1 DFDIE Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation. 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set (see Section 31.3.2.8) 0 SFDIE Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault is detected during a Flash block read operation. 0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 31.3.2.8) 1 An interrupt will be requested whenever the SFDIF flag is set (see Section 31.3.2.8) 31.3.2.7 Flash Status Register (FSTAT) The FSTAT register reports the operational status of the Flash module. Offset Module Base + 0x0006 7 R W Reset CCIF 1 6 0 0 5 4 ACCERR FPVIOL 0 0 3 2 MGBUSY RSVD 0 0 1 0 MGSTAT[1:0] 01 01 = Unimplemented or Reserved Figure 31-11. Flash Status Register (FSTAT) 1 Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 31.6). CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. Table 31-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation. 0 Flash command in progress 1 Flash command has completed 5 ACCERR Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory caused by either a violation of the command write sequence (see Section 31.4.4.2) or issuing an illegal Flash command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR. 0 No access error detected 1 Access error detected 4 FPVIOL Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of P-Flash or EEPROM memory during a command write sequence. The FPVIOL bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected 1 Protection violation detected MC9S12G Family Reference Manual Rev.1.28 1140 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-15. FSTAT Field Descriptions (continued) Field 3 MGBUSY 2 RSVD Description Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller. 0 Memory Controller is idle 1 Memory Controller is busy executing a Flash command (CCIF = 0) Reserved Bit — This bit is reserved and always reads 0. 1–0 Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See Section 31.4.6, “Flash Command Description,” and Section 31.6, “Initialization” for details. 31.3.2.8 Flash Error Status Register (FERSTAT) The FERSTAT register reflects the error status of internal Flash operations. Offset Module Base + 0x0007 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDIF SFDIF 0 0 = Unimplemented or Reserved Figure 31-12. Flash Error Status Register (FERSTAT) All flags in the FERSTAT register are readable and only writable to clear the flag. Table 31-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The DFDIF flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.2 0 No double bit fault detected 1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command running 0 SFDIF Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF. 0 No single bit fault detected 1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted while command running 1 The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either single fault or double fault but never both). A simultaneous access collision (Flash array read operation returning invalid data attempted while command running) is indicated when both SFDIF and DFDIF flags are high. 2 There is a one cycle delay in storing the ECC DFDIF and SFDIF fault flags in this register. At least one NOP is required after a flash memory read before checking FERSTAT for the occurrence of ECC errors. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1141 240 KByte Flash Module (S12FTMRG240K2V1) 31.3.2.9 P-Flash Protection Register (FPROT) The FPROT register defines which P-Flash sectors are protected against program and erase operations. Offset Module Base + 0x0008 7 R W Reset FPOPEN F1 6 5 RNV6 F1 4 FPHDIS F1 3 FPHS[1:0] F1 2 1 FPLDIS F1 F1 0 FPLS[1:0] F1 F1 = Unimplemented or Reserved Figure 31-13. Flash Protection Register (FPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected region can only be increased (see Section 31.3.2.9.1, “P-Flash Protection Restrictions,” and Table 31-21). During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte in the Flash configuration field at global address 0x3_FF0C located in P-Flash memory (see Table 31-4) as indicated by reset condition ‘F’ in Figure 31-13. To change the P-Flash protection that will be loaded during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected. Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. Table 31-17. FPROT Field Descriptions Field Description 7 FPOPEN Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or erase operations as shown in Table 31-18 for the P-Flash block. 0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits 1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits 6 RNV[6] Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements. 5 FPHDIS Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory ending with global address 0x3_FFFF. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 4–3 FPHS[1:0] Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area in P-Flash memory as shown inTable 31-19. The FPHS bits can only be written to while the FPHDIS bit is set. MC9S12G Family Reference Manual Rev.1.28 1142 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-17. FPROT Field Descriptions (continued) Field Description 2 FPLDIS Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory beginning with global address 0x3_8000. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 1–0 FPLS[1:0] Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area in P-Flash memory as shown in Table 31-20. The FPLS bits can only be written to while the FPLDIS bit is set. Table 31-18. P-Flash Protection Function 1 Function1 FPOPEN FPHDIS FPLDIS 1 1 1 No P-Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P-Flash Memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges For range sizes, refer to Table 31-19 and Table 31-20. Table 31-19. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 00 0x3_F800–0x3_FFFF 2 Kbytes 01 0x3_F000–0x3_FFFF 4 Kbytes 10 0x3_E000–0x3_FFFF 8 Kbytes 11 0x3_C000–0x3_FFFF 16 Kbytes Table 31-20. P-Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 00 0x3_8000–0x3_83FF 1 Kbyte 01 0x3_8000–0x3_87FF 2 Kbytes 10 0x3_8000–0x3_8FFF 4 Kbytes 11 0x3_8000–0x3_9FFF 8 Kbytes All possible P-Flash protection scenarios are shown in Figure 31-14 . Although the protection scheme is loaded from the Flash memory at global address 0x3_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1143 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 Scenario FLASH START FPLS[1:0] 0x3_FFFF FPHS[1:0] 0x3_8000 FPOPEN = 0 0x3_8000 FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 240 KByte Flash Module (S12FTMRG240K2V1) 0x3_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 31-14. P-Flash Protection Scenarios MC9S12G Family Reference Manual Rev.1.28 1144 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) 31.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 31-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 31-21. P-Flash Protection Scenario Transitions To Protection Scenario1 From Protection Scenario 0 1 2 3 0 X X X X X 1 X 4 X X X X X X X X X X 6 X 7 1 X 6 7 X 3 5 5 X X 2 4 X X X X X X Allowed transitions marked with X, see Figure 31-14 for a definition of the scenarios. 31.3.2.10 EEPROM Protection Register (EEPROT) The EEPROT register defines which EEPROM sectors are protected against program and erase operations. Offset Module Base + 0x0009 7 R W Reset 6 5 4 DPOPEN F1 3 2 1 0 F1 F1 F1 DPS[6:0] F1 F1 F1 F1 Figure 31-15. EEPROM Protection Register (EEPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the EEPROT register are writable with the restriction that protection can be added but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1 (protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is irrelevant. During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1145 240 KByte Flash Module (S12FTMRG240K2V1) P-Flash memory (see Table 31-4) as indicated by reset condition F in Table 31-23. To change the EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase containing the EEPROM protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the EEPROM memory fully protected. Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. Block erase of the EEPROM memory is not possible if any of the EEPROM sectors are protected. Table 31-22. EEPROT Field Descriptions Field Description 7 DPOPEN EEPROM Protection Control 0 Enables EEPROM memory protection from program and erase with protected address range defined by DPS bits 1 Disables EEPROM memory protection from program and erase 6–0 DPS[6:0] EEPROM Protection Size — The DPS[6:0] bits determine the size of the protected area in the EEPROM memory, this size increase in step of 32 bytes, as shown in Table 31-23 . Table 31-23. EEPROM Protection Address Range DPS[6:0] Global Address Range Protected Size 0000000 0x0_0400 – 0x0_041F 32 bytes 0000001 0x0_0400 – 0x0_043F 64 bytes 0000010 0x0_0400 – 0x0_045F 96 bytes 0000011 0x0_0400 – 0x0_047F 128 bytes 0000100 0x0_0400 – 0x0_049F 160 bytes 0000101 0x0_0400 – 0x0_04BF 192 bytes The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increasing of one. . . . 1111111 0x0_0400 – 0x0_13FF 4,096 bytes MC9S12G Family Reference Manual Rev.1.28 1146 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) 31.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. Offset Module Base + 0x000A 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[15:8] W Reset 3 0 0 0 0 Figure 31-16. Flash Common Command Object High Register (FCCOBHI) Offset Module Base + 0x000B 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[7:0] W Reset 3 0 0 0 0 Figure 31-17. Flash Common Command Object Low Register (FCCOBLO) 31.3.2.11.1 FCCOB - NVM Command Mode NVM command mode uses the indexed FCCOB register to provide a command code and its relevant parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes (as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array. The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 31-24. The return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller. Writes to the unimplemented parameter fields (CCOBIX = 110 and CCOBIX = 111) are ignored with reads from these fields returning 0x0000. Table 31-24 shows the generic Flash command format. The high byte of the first word in the CCOB array contains the command code, followed by the parameters for this specific Flash command. For details on the FCCOB settings required by each command, see the Flash command descriptions in Section 31.4.6. Table 31-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] 000 001 Byte FCCOB Parameter Fields (NVM Command Mode) HI FCMD[7:0] defining Flash command LO 6’h0, Global address [17:16] HI Global address [15:8] LO Global address [7:0] MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1147 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] 010 011 100 101 Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 0 [15:8] LO Data 0 [7:0] HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 31.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing. Offset Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 31-18. Flash Reserved1 Register (FRSV1) All bits in the FRSV1 register read 0 and are not writable. 31.3.2.13 Flash Reserved2 Register (FRSV2) This Flash register is reserved for factory testing. Offset Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 31-19. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. 31.3.2.14 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.28 1148 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) Offset Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 31-20. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 31.3.2.15 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing. Offset Module Base + 0x000F R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 31-21. Flash Reserved4 Register (FRSV4) All bits in the FRSV4 register read 0 and are not writable. 31.3.2.16 Flash Option Register (FOPT) The FOPT register is the Flash option register. Offset Module Base + 0x0010 7 6 5 4 R 3 2 1 0 F1 F1 F1 F1 NV[7:0] W Reset F1 F1 F1 F1 = Unimplemented or Reserved Figure 31-22. Flash Option Register (FOPT) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FOPT register are readable but are not writable. During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global address 0x3_FF0E located in P-Flash memory (see Table 31-4) as indicated by reset condition F in Figure 31-22. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1149 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-25. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits. 31.3.2.17 Flash Reserved5 Register (FRSV5) This Flash register is reserved for factory testing. Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 31-23. Flash Reserved5 Register (FRSV5) All bits in the FRSV5 register read 0 and are not writable. 31.3.2.18 Flash Reserved6 Register (FRSV6) This Flash register is reserved for factory testing. Offset Module Base + 0x0012 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 31-24. Flash Reserved6 Register (FRSV6) All bits in the FRSV6 register read 0 and are not writable. 31.3.2.19 Flash Reserved7 Register (FRSV7) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.28 1150 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 31-25. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. 31.4 31.4.1 Functional Description Modes of Operation The FTMRG240K2 module provides the modes of operation normal and special . The operating mode is determined by module-level inputs and affects the FCLKDIV, FCNFG, and EEPROT registers (see Table 31-27). 31.4.2 IFR Version ID Word The version ID word is stored in the IFR at address 0x0_40B6. The contents of the word are defined in Table 31-26. Table 31-26. IFR Version ID Fields [15:4] [3:0] Reserved VERNUM MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1151 240 KByte Flash Module (S12FTMRG240K2V1) • VERNUM: Version number. The first version is number 0b_0001 with both 0b_0000 and 0b_1111 meaning ‘none’. 31.4.3 Internal NVM resource (NVMRES) IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown in Table 31-5. The NVMRES global address map is shown in Table 31-6. For FTMRG240K2 the NVMRES address area is shared with 16K space of P-Flash area, as shown in Figure 31-2. 31.4.4 Flash Command Operations Flash command operations are used to modify Flash memory contents. The next sections describe: • How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from BUSCLK for Flash program and erase command operations • The command write sequence used to set Flash command parameters and launch execution • Valid Flash commands available for execution, according to MCU functional mode and MCU security state. 31.4.4.1 Writing the FCLKDIV Register Prior to issuing any Flash program or erase command after a reset, the user is required to write the FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz. Table 31-8 shows recommended values for the FDIV field based on BUSCLK frequency. NOTE Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash memory due to overstress. Setting FDIV too low can result in incomplete programming or erasure of the Flash memory cells. When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written, any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set. 31.4.4.2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see Section 31.3.2.7) and the CCIF flag should be tested to determine the status of the current command write MC9S12G Family Reference Manual Rev.1.28 1152 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) sequence. If CCIF is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the FCCOB register are ignored. 31.4.4.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 31.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag will remain clear until the Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 31-26. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1153 240 KByte Flash Module (S12FTMRG240K2V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no Read: FSTAT register yes FCCOB Availability Check CCIF Set? yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load. Write to FCCOB register to load required command parameter. More Parameters? yes no Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 31-26. Generic Flash Command Write Sequence Flowchart MC9S12G Family Reference Manual Rev.1.28 1154 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) 31.4.4.3 Valid Flash Module Commands Table 31-27 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 31-27. Flash Commands by Mode and Security State Unsecured FCMD Command Secured NS1 SS2 NS3 SS4 0x01 Erase Verify All Blocks     0x02 Erase Verify Block     0x03 Erase Verify P-Flash Section    0x04 Read Once    0x06 Program P-Flash    0x07 Program Once    0x08 Erase All Blocks 0x09 Erase Flash Block    0x0A Erase P-Flash Sector    0x0B Unsecure Flash 0x0C Verify Backdoor Access Key  0x0D Set User Margin Level  0x0E Set Field Margin Level 0x10 Erase Verify EEPROM Section    0x11 Program EEPROM    0x12 Erase EEPROM Sector            1 Unsecured Normal Single Chip mode Unsecured Special Single Chip mode. 3 Secured Normal Single Chip mode. 4 Secured Special Single Chip mode. 2 31.4.4.4 P-Flash Commands Table 31-28 summarizes the valid P-Flash commands along with the effects of the commands on the P-Flash block and other resources within the Flash module. Table 31-28. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks Function on P-Flash Memory Verify that all P-Flash (and EEPROM) blocks are erased. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1155 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-28. P-Flash Commands FCMD Command 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a P-Flash (or EEPROM) block. An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. 0x0A Erase P-Flash Sector 0x0B Unsecure Flash 0x0C Verify Backdoor Access Key Supports a method of releasing MCU security by verifying a set of security keys. 0x0D Set User Margin Level Specifies a user margin read level for all P-Flash blocks. 0x0E Set Field Margin Level Specifies a field margin read level for all P-Flash blocks (special modes only). 31.4.4.5 Function on P-Flash Memory Verify that a P-Flash block is erased. Verify that a given number of words starting at the address provided are erased. Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block that was previously programmed using the Program Once command. Program a phrase in a P-Flash block. Erase all bytes in a P-Flash sector. Supports a method of releasing MCU security by erasing all P-Flash (and EEPROM) blocks and verifying that all P-Flash (and EEPROM) blocks are erased. EEPROM Commands Table 31-29 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. Table 31-29. EEPROM Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block Function on EEPROM Memory Verify that all EEPROM (and P-Flash) blocks are erased. Verify that the EEPROM block is erased. MC9S12G Family Reference Manual Rev.1.28 1156 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-29. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block. An erase of the full EEPROM block is only possible when DPOPEN bit in the EEPROT register is set prior to launching the command. 0x0B Unsecure Flash 0x0D Set User Margin Level Specifies a user margin read level for the EEPROM block. 0x0E Set Field Margin Level Specifies a field margin read level for the EEPROM block (special modes only). 0x10 Erase Verify EEPROM Section Verify that a given number of words starting at the address provided are erased. 0x11 Program EEPROM Program up to four words in the EEPROM block. 0x12 Erase EEPROM Sector Erase all bytes in a sector of the EEPROM block. 31.4.5 Supports a method of releasing MCU security by erasing all EEPROM (and P-Flash) blocks and verifying that all EEPROM (and P-Flash) blocks are erased. Allowed Simultaneous P-Flash and EEPROM Operations Only the operations marked ‘OK’ in Table 31-30 are permitted to be run simultaneously on the Program Flash and EEPROM blocks. Some operations cannot be executed simultaneously because certain hardware resources are shared by the two memories. The priority has been placed on permitting Program Flash reads while program and erase operations execute on the EEPROM, providing read (P-Flash) while write (EEPROM) functionality. Table 31-30. Allowed P-Flash and EEPROM Simultaneous Operations EEPROM Program Flash Read Read Margin Read1 Program Sector Erase OK OK OK Mass Erase2 Margin Read1 Program Sector Erase Mass Erase2 OK 1 A ‘Margin Read’ is any read after executing the margin setting commands ‘Set User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified. See the Note on margin settings in Section 31.4.6.12 and Section 31.4.6.13. 2 The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1157 240 KByte Flash Module (S12FTMRG240K2V1) 31.4.6 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence. The ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be processed by the Memory Controller: • Starting any command write sequence that programs or erases Flash memory before initializing the FCLKDIV register • Writing an invalid command as part of the command write sequence • For additional possible errors, refer to the error handling table provided for each command If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation will return invalid data if both flags SFDIF and DFDIF are set. If the SFDIF or DFDIF flags were not previously set when the invalid read operation occurred, both the SFDIF and DFDIF flags will be set. If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting any command write sequence (see Section 31.3.2.7). CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. 31.4.6.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and EEPROM blocks have been erased. Table 31-31. Erase Verify All Blocks Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x01 Not required Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks operation has completed. If all blocks are not erased, it means blank check failed, both MGSTAT bits will be set. Table 31-32. Erase Verify All Blocks Command Error Handling Register Error Bit ACCERR FPVIOL FSTAT Error Condition Set if CCOBIX[2:0] != 000 at command launch None MGSTAT1 Set if any errors have been encountered during the reador if blank check failed . MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. MC9S12G Family Reference Manual Rev.1.28 1158 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) 31.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0]bits determine which block must be verified. Table 31-33. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. Table 31-34 See Table 31-34. Flash block selection code description Selection code[1:0] Flash block to be verified 00 EEPROM 01 P-Flash 10 P-Flash 11 P-Flash Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that the selected P-Flash or EEPROM block is erased. The CCIF flag will set after the Erase Verify Block operation has completed.If the block is not erased, it means blank check failed, both MGSTAT bits will be set. Table 31-35. Erase Verify Block Command Error Handling Register Error Bit ACCERR FPVIOL FSTAT 31.4.6.3 Error Condition Set if CCOBIX[2:0] != 000 at command launch. None. MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read1 or if blank check failed. Erase Verify P-Flash Section Command The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1159 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-36. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. Table 31-37. Erase Verify P-Flash Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 31-27) ACCERR Set if an invalid global address [17:0] is supplied see Table 31-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT Set if the requested section crosses a the P-Flash address boundary FPVIOL 31.4.6.4 None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. Read Once Command The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of P-Flash. The Read Once field is programmed using the Program Once command described in Section 31.4.6.6. The Read Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 31-38. Read Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x04 Not Required 001 Read Once phrase index (0x0000 - 0x0007) 010 Read Once word 0 value 011 Read Once word 1 value 100 Read Once word 2 value 101 Read Once word 3 value MC9S12G Family Reference Manual Rev.1.28 1160 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. 8 Table 31-39. Read Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if an invalid phrase index is supplied FSTAT 31.4.6.5 Set if command not available in current mode (see Table 31-27) FPVIOL None MGSTAT1 Set if any errors have been encountered during the read MGSTAT0 Set if any non-correctable errors have been encountered during the read Program P-Flash Command The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an embedded algorithm. CAUTION A P-Flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash phrase is not allowed. Table 31-40. Program P-Flash Command FCCOB Requirements CCOBIX[2:0] 000 1 FCCOB Parameters 0x06 Global address [17:16] to identify P-Flash block 001 Global address [15:0] of phrase location to be programmed1 010 Word 0 program value 011 Word 1 program value 100 Word 2 program value 101 Word 3 program value Global address [2:0] must be 000 Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. The CCIF flag will set after the Program P-Flash operation has completed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1161 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-41. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid global address [17:0] is supplied see Table 31-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 31.4.6.6 Set if command not available in current mode (see Table 31-27) Set if the global address [17:0] points to a protected area MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Program Once Command The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in P-Flash. The Program Once reserved field can be read using the Read Once command as described in Section 31.4.6.4. The Program Once command must only be issued once since the nonvolatile information register in P-Flash cannot be erased. The Program Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 31-42. Program Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x07 Not Required 001 Program Once phrase index (0x0000 - 0x0007) 010 Program Once word 0 value 011 Program Once word 1 value 100 Program Once word 2 value 101 Program Once word 3 value Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with read back. The CCIF flag will remain clear, setting only after the Program Once operation has completed. The reserved nonvolatile information register accessed by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. MC9S12G Family Reference Manual Rev.1.28 1162 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-43. Program Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed1 FSTAT FPVIOL 1 Set if command not available in current mode (see Table 31-27) None MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will be allowed to execute again on that same phrase. 31.4.6.7 Erase All Blocks Command The Erase All Blocks operation will erase the entire P-Flash and EEPROM memory space. Table 31-44. Erase All Blocks Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x08 Not required Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All Blocks operation has completed. Table 31-45. Erase All Blocks Command Error Handling Register Error Bit ACCERR FSTAT 31.4.6.8 FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 31-27) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or EEPROM block. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1163 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-46. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 31-47. Erase Flash Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 31-27) ACCERR Set if the supplied P-Flash address is not phrase-aligned or if the EEPROM address is not word-aligned FSTAT FPVIOL 31.4.6.9 Set if an invalid global address [17:16] is supplied Set if an area of the selected Flash block is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Erase P-Flash Sector Command The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector. Table 31-48. Erase P-Flash Sector Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x0A Global address [17:16] to identify P-Flash block to be erased Global address [15:0] anywhere within the sector to be erased. Refer to Section 31.1.2.1 for the P-Flash sector size. Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed. MC9S12G Family Reference Manual Rev.1.28 1164 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-49. Erase P-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if command not available in current mode (see Table 31-27) Set if an invalid global address [17:16] is supplied see Table 31-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL Set if the selected P-Flash sector is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 31.4.6.10 Unsecure Flash Command The Unsecure Flash command will erase the entire P-Flash and EEPROM memory space and, if the erase is successful, will release security. Table 31-50. Unsecure Flash Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x0B Not required Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire P-Flash and EEPROM memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. If the erase verify is not successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security state. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag is set after the Unsecure Flash operation has completed. Table 31-51. Unsecure Flash Command Error Handling Register Error Bit ACCERR FSTAT FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 31-27) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 31.4.6.11 Verify Backdoor Access Key Command The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 31-10). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1165 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-4). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 31-52. Verify Backdoor Access Key Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0C Not required 001 Key 0 010 Key 1 011 Key 2 100 Key 3 Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash configuration field with Key 0 compared to 0x3_FF00, etc. If the backdoor keys match, security will be released. If the backdoor keys do not match, security is not released and all future attempts to execute the Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is set after the Verify Backdoor Access Key operation has completed. Table 31-53. Verify Backdoor Access Key Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 100 at command launch Set if an incorrect backdoor key is supplied ACCERR FSTAT Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see Section 31.3.2.2) Set if the backdoor key has mismatched since the last reset FPVIOL None MGSTAT1 None MGSTAT0 None 31.4.6.12 Set User Margin Level Command The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P-Flash or EEPROM block. Table 31-54. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x0D Flash block selection code [1:0]. Table 31-34 See Margin level setting. MC9S12G Family Reference Manual Rev.1.28 1166 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply user margin levels to the P-Flash block only. Valid margin level settings for the Set User Margin Level command are defined in Table 31-55. Table 31-55. Valid Set User Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state Table 31-56. Set User Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch. ACCERR Set if command not available in current mode (see Table 31-27). Set if an invalid margin level setting is supplied. FSTAT FPVIOL None MGSTAT1 None MGSTAT0 None NOTE User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. 31.4.6.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of the P-Flash or EEPROM block. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1167 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-57. Set Field Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0E 001 Flash block selection code [1:0]. Table 31-34 See Margin level setting. Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the field margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM field margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash field margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply field margin levels to the P-Flash block only. Valid margin level settings for the Set Field Margin Level command are defined in Table 31-58. Table 31-58. Valid Set Field Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 0x0003 Field Margin-1 Level1 0x0004 Field Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state Table 31-59. Set Field Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch. ACCERR FSTAT Set if command not available in current mode (see Table 31-27). Set if an invalid margin level setting is supplied. FPVIOL None MGSTAT1 None MGSTAT0 None MC9S12G Family Reference Manual Rev.1.28 1168 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) CAUTION Field margin levels must only be used during verify of the initial factory programming. NOTE Field margin levels can be used to check that Flash memory contents have adequate margin for data retention at the normal level setting. If unexpected results are encountered when checking Flash memory contents at field margin levels, the Flash memory contents should be erased and reprogrammed. 31.4.6.14 Erase Verify EEPROM Section Command The Erase Verify EEPROM Section command will verify that a section of code in the EEPROM is erased. The Erase Verify EEPROM Section command defines the starting point of the data to be verified and the number of words. Table 31-60. Erase Verify EEPROM Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x10 Global address [17:16] to identify the EEPROM block 001 Global address [15:0] of the first word to be verified 010 Number of words to be verified Upon clearing CCIF to launch the Erase Verify EEPROM Section command, the Memory Controller will verify the selected section of EEPROM memory is erased. The CCIF flag will set after the Erase Verify EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. Table 31-61. Erase Verify EEPROM Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 31-27) ACCERR Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested section breaches the end of the EEPROM block FPVIOL None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1169 240 KByte Flash Module (S12FTMRG240K2V1) 31.4.6.15 Program EEPROM Command The Program EEPROM operation programs one to four previously erased words in the EEPROM block. The Program EEPROM operation will confirm that the targeted location(s) were successfully programmed upon completion. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Table 31-62. Program EEPROM Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters Global address [17:16] to identify the EEPROM block 0x11 001 Global address [15:0] of word to be programmed 010 Word 0 program value 011 Word 1 program value, if desired 100 Word 2 program value, if desired 101 Word 3 program value, if desired Upon clearing CCIF to launch the Program EEPROM command, the user-supplied words will be transferred to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program EEPROM command launch determines how many words will be programmed in the EEPROM block. The CCIF flag is set when the operation has completed. Table 31-63. Program EEPROM Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] < 010 at command launch Set if CCOBIX[2:0] > 101 at command launch ACCERR Set if command not available in current mode (see Table 31-27) Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested group of words breaches the end of the EEPROM block FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 31.4.6.16 Erase EEPROM Sector Command The Erase EEPROM Sector operation will erase all addresses in a sector of the EEPROM block. MC9S12G Family Reference Manual Rev.1.28 1170 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-64. Erase EEPROM Sector Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 001 0x12 Global address [17:16] to identify EEPROM block Global address [15:0] anywhere within the sector to be erased. See Section 31.1.2.2 for EEPROM sector size. Upon clearing CCIF to launch the Erase EEPROM Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase EEPROM Sector operation has completed. Table 31-65. Erase EEPROM Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if an invalid global address [17:0] is suppliedsee Table 31-3) Set if a misaligned word address is supplied (global address [0] != 0) FSTAT FPVIOL 31.4.7 Set if command not available in current mode (see Table 31-27) Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 31-66. Flash Interrupt Sources Interrupt Source Global (CCR) Mask Interrupt Flag Local Enable CCIF (FSTAT register) CCIE (FCNFG register) I Bit ECC Double Bit Fault on Flash Read DFDIF (FERSTAT register) DFDIE (FERCNFG register) I Bit ECC Single Bit Fault on Flash Read SFDIF (FERSTAT register) SFDIE (FERCNFG register) I Bit Flash Command Complete MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1171 240 KByte Flash Module (S12FTMRG240K2V1) NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 31.4.7.1 Description of Flash Interrupt Operation The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed description of the register bits involved, refer to Section 31.3.2.5, “Flash Configuration Register (FCNFG)”, Section 31.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 31.3.2.7, “Flash Status Register (FSTAT)”, and Section 31.3.2.8, “Flash Error Status Register (FERSTAT)”. The logic used for generating the Flash module interrupts is shown in Figure 31-27. Flash Command Interrupt Request CCIE CCIF DFDIE DFDIF Flash Error Interrupt Request SFDIE SFDIF Figure 31-27. Flash Module Interrupts Implementation 31.4.8 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 31.4.7, “Interrupts”). 31.4.9 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. MC9S12G Family Reference Manual Rev.1.28 1172 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) 31.5 Security The Flash module provides security information to the MCU. The Flash security state is defined by the SEC bits of the FSEC register (see Table 31-11). During reset, the Flash module initializes the FSEC register using data read from the security byte of the Flash configuration field at global address 0x3_FF0F. The security state out of reset can be permanently changed by programming the security byte assuming that the MCU is starting from a mode where the necessary P-Flash erase and program commands are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset. The following subsections describe these security-related subjects: • Unsecuring the MCU using Backdoor Key Access • Unsecuring the MCU in Special Single Chip Mode using BDM • Mode and Security Effects on Flash Command Availability 31.5.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x3_FF00-0x3_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 31.3.2.2), the Verify Backdoor Access Key command (see Section 31.4.6.11) allows the user to present four prospective keys for comparison to the keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC register (see Table 31-11) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash memory and EEPROM memory will not be available for read access and will return invalid data. The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 31.3.2.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 31.4.6.11 2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10 The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method to re-enable the Verify Backdoor Access Key command. The security as defined in the Flash security byte (0x3_FF0F) is not changed by using the Verify Backdoor Access Key command sequence. The backdoor keys stored in addresses 0x3_FF00-0x3_FF07 are unaffected by the Verify Backdoor Access Key command sequence. The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection register, FPROT. After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is unsecured, the sector containing the Flash security byte can be erased and the Flash security byte can be MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1173 240 KByte Flash Module (S12FTMRG240K2V1) reprogrammed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x3_FF00-0x3_FF07 in the Flash configuration field. 31.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM A secured MCU can be unsecured in special single chip mode by using the following method to erase the P-Flash and EEPROM memory: 1. Reset the MCU into special single chip mode 2. Delay while the BDM executes the Erase Verify All Blocks command write sequence to check if the P-Flash and EEPROM memories are erased 3. Send BDM commands to disable protection in the P-Flash and EEPROM memory 4. Execute the Erase All Blocks command write sequence to erase the P-Flash and EEPROM memory. Alternatively the Unsecure Flash command can be executed, if so the steps 5 and 6 below are skeeped. 5. After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into special single chip mode 6. Delay while the BDM executes the Erase Verify All Blocks command write sequence to verify that the P-Flash and EEPROM memory are erased If the P-Flash and EEPROM memory are verified as erased, the MCU will be unsecured. All BDM commands will now be enabled and the Flash security byte may be programmed to the unsecure state by continuing with the following steps: 7. Send BDM commands to execute the Program P-Flash command write sequence to program the Flash security byte to the unsecured state 8. Reset the MCU 31.5.3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 31-27. 31.6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the Flash Block Configuration Parameters, the FPROT and EEPROT protection registers, and the FOPT and FSEC registers. The initialization routine reverts to built-in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence. If a double bit fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set. CCIF is cleared throughout the initialization sequence. The Flash module holds off all CPU access for a portion of the initialization sequence. Flash reads are allowed once the hold is removed. Completion of the initialization sequence is marked by setting CCIF high which enables user commands. MC9S12G Family Reference Manual Rev.1.28 1174 NXP Semiconductors 240 KByte Flash Module (S12FTMRG240K2V1) If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1175 240 KByte Flash Module (S12FTMRG240K2V1) MC9S12G Family Reference Manual Rev.1.28 1176 NXP Semiconductors Appendix A Electrical Characteristics Revision History Version Number Revision Date Rev 0.43 22-Nov-2012 • • • • • • Updated Table A-4 (temperature option W) Added Table A-7 Added Table A-9 Updated Table A-18 (Num 4, 8) Updated Table A-19 (Num 4) Added Table A-23Added Table A-25Added Table A-27Added Table A-29Added Table A-33 Rev 0.44 2-Dec-2012 • • • • • • • • • • • • • • • • • Updated Table A-1 (Num 1) Updated Table A-4 (added parameter TJmax) Updated Table A-7 (Num 6, conditions) Updated Table A-9 (Num 6, conditions) Updated Table A-10 (conditions) Added Table A-17 Updated Table A-18 (Num 8) Updated Table A-20 (conditions) Updated Table A-21 (conditions) Updated Table A-23 (all rows, conditions) Updated Table A-25 (all rows, conditions) Updated Table A-27 (all rows, conditions) Updated Table A-33 (conditions) Updated Table A-34 (conditions) Updated Table A-51 (conditions) Updated Table A-52 (conditions) Updated Table A-53 (conditions) Rev 0.45 9-Jan-2013 • • • • • • • • Updated Table A-1 (Num 9, 10) Updated Table A-4 (removed paramerer TJmax) Added Table A-11 Updated Table A-17 (Num 1-3) Updated Table A-18 (Num 4) Updated Table A-19 (Num 1) Added Table A-46 Updated Table A-49 (all rows, conditions) Rev 0.46 24-Jan-2013 • Updated Table A-17 (Num 1-3) • Updated Table A-18 (Num 4, 8) • Added Table A-49 (Num 1-3) Rev 0.47 25-Jan-2013 • Updated Table A-30 (Num 5, 6) • Added Table A-43 Rev 0.48 2-Apr-2013 Description of Changes • Corrected Table A-4 (TJ, temperature option V) MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1177 Electrical Characteristics Version Number Revision Date Rev 0.49 5-Jun-2013 • Updated Section A.1.1, “Parameter Classification” • Applied new M-parameter tag in Table A-7, Table A-9, Table A-11, Table A-17, Table A-23, Table A-25, Table A-27, Table A-29, Table A-33, Table A-44, Table A-46, and Table A-49 • Updated Table A-40 (Num 2b, 6b) Rev 0.50 15-Jul-2013 • Updated Section A.7, “NVM” (format and timing parameters) Rev 0.51 23-Oct-2017 • Updated mask set condition in Table A-45 (Num 7a, 7b, 8a, 8b) • Updated mask set condition in Table A-46 (Num 7a, 7b, 8a, 8b) Rev 0.52 22-Jun-2020 • Added Table A-14 (GPIO Configuration for Full Stop and Pseudo Stop Current Measurement) • Updated Table A-18 and Table A-19 (conditions header) A.1 Description of Changes General This supplement contains the most accurate electrical information for the MC9S12G microcontroller available at the time of publication. This introduction is intended to give an overview on several common topics like power supply, current injection etc. A.1.1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. NOTE This classification is shown in the column labeled “C” in the parameter tables where appropriate. P: M: C: T: D: A.1.2 Those parameters are guaranteed during production testing on each individual device. These parameters are characterized at 160C and tested in production at an ambient temperature of 150C with appropriate guardbanding to guarantee operation at 160C. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. Power Supply The VDDA, VSSA pin pairs supply the A/D converter and parts of the internal voltage regulator. The VDDX, VSSX pin pairs [3:1] supply the I/O pins. MC9S12G Family Reference Manual Rev.1.28 1178 NXP Semiconductors Electrical Characteristics VDDR supplies the internal voltage regulator. The VDDF, VSS1 pin pair supplies the internal NVM logic. All VDDX pins are internally connected by metal. All VSSX pins are internally connected by metal. VDDA, VDDX and VSSA, VSSX are connected by diodes for ESD protection. NOTE In the following context VDD35 is used for either VDDA, VDDR, and VDDX; VSS35 is used for either VSSA and VSSX unless otherwise noted. IDD35 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. A.1.3 Pins There are four groups of functional pins. A.1.3.1 I/O Pins The I/O pins have a level in the range of 3.13V to 5.5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD and the RESET pins. Some functionality may be disabled. A.1.3.2 Analog Reference This group consists of the VRH pin. A.1.3.3 Oscillator The pins EXTAL, XTAL dedicated to the oscillator have a nominal 1.8V level. A.1.3.4 TEST This pin is used for production testing only. The TEST pin must be tied to ground in all applications. A.1.4 Current Injection Power supply must maintain regulation within operating VDD35 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD35) is greater than IDD35, the injection current may flow out of VDD35 and could result in external power supply going out of regulation. Ensure external VDD35 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g., if no system clock is present, or if clock rate is very low which would reduce overall power consumption. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1179 Electrical Characteristics A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS35 or VDD35). Table A-1. Absolute Maximum Ratings1 Num 1 2 Rating Symbol Min Max Unit 1 I/O, regulator and analog supply voltage VDD35 –0.3 6.0 V 2 Voltage difference VDDX to VDDA VDDX –6.0 0.3 V 3 Voltage difference VSSX to VSSA VSSX –0.3 0.3 V 4 Digital I/O input voltage VIN –0.3 6.0 V 5 Analog reference VRH –0.3 6.0 V 6 EXTAL, XTAL VILV –0.3 2.16 V 7 Instantaneous maximum current Single pin limit for all digital I/O pins2 ID –25 +25 mA 8 Instantaneous maximum current Single pin limit for EXTAL, XTAL I –25 +25 mA 9 Maximum current Single pin limit for power supply pins I –60 +60 mA 10 Storage temperature range Tstg –65 155 C DL DV Beyond absolute maximum ratings device might be damaged. All digital I/O pins are internally clamped to VSSX and VDDX, or VSSA and VDDA. A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade integrated circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. MC9S12G Family Reference Manual Rev.1.28 1180 NXP Semiconductors Electrical Characteristics Table A-2. ESD and Latch-up Test Conditions Model Description Human Body Symbol Value Unit Series Resistance R1 1500  Storage Capacitance C 100 pF Number of Pulse per pin positive negative - 3 3 Symbol Min Max Unit Table A-3. ESD and Latch-Up Protection Characteristics Num C 1 C Human Body Model (HBM) VHBM 2000 - V 2 C Charge Device Model (CDM) VCDM 500 - V 3 C Charge Device Model (CDM) (Corner Pins) VCDM 750 - V 4 C Latch-up Current at 125C positive negative ILAT +100 -100 - mA Latch-up Current at 27C positive negative ILAT +200 -200 - mA 5 A.1.7 Rating C Operating Conditions This section describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE Please refer to the temperature rating of the device (C, V, M, W) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8, “Power Dissipation and Thermal Characteristics”. Table A-4. Operating Conditions Rating Symbol Min Typ Max Unit VDD35 3.13 5 5.5 V Oscillator fosc 4 — 16 MHz Bus frequency fbus 0.5 — 25 MHz Temperature Option C Operating ambient temperature range1 Operating junction temperature range TA TJ –40 –40 27 — 85 105 I/O, regulator and analog supply voltage C MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1181 Electrical Characteristics Table A-4. Operating Conditions Rating Symbol Min Typ Max Temperature Option V Operating ambient temperature range1 Operating junction temperature range TA TJ –40 –40 27 — 105 125 Temperature Option M Operating ambient temperature range1 Operating junction temperature range TA TJ –40 –40 27 — 125 150 Temperature Option W Operating ambient temperature range1 Operating junction temperature range TA TJ –40 –40 27 — 150 160 1 Unit C C C Please refer to Section A.1.8, “Power Dissipation and Thermal Characteristics” for more details about the relation between ambient temperature TA and device junction temperature TJ. NOTE Operation is guaranteed when powering down until low voltage reset assertion. MC9S12G Family Reference Manual Rev.1.28 1182 NXP Semiconductors Electrical Characteristics A.1.8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in C can be obtained from: T T T A = Ambient Temperature, [C  = Total Chip Power Dissipation, [W] D  = T + P    A D JA = Junction Temperature, [C  J P J JA = Package Thermal Resistance, [C/W] The total power dissipation can be calculated from: P P D INT = P INT +P IO = Chip Internal Power Dissipation, [W] P IO =  RDSON  IIOi 2 i PIO is the sum of all output currents on I/O ports associated with VDDX, whereby R R V OL = ------------ ;for outputs driven low DSON I OL V –V DD35 OH = --------------------------------------- ;for outputs driven high DSON I OH P INT = I DDR V DDR +I DDA V DDA MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1183 Electrical Characteristics MC9S12G Family Reference Manual Rev.1.28 1184 NXP Semiconductors Electrical Characteristics Table A-5. Thermal Package Characteristics1 Num C Rating Symbol S12G64, S12GN32, S12G128, S12G240, S12GA64, S12GNA32, S12GA128, S12GA240, S12G48, Unit S12GN16, S12G96, S12G192, S12GN48, S12GNA16 S12GA96 S12GA192 S12GA64 20-pin TSSOP 1 D Thermal resistance single sided PCB, natural convection2 JA 91 C/W 2 D Thermal resistance single sided PCB @ 200 ft/min3 JMA 72 C/W 3 D Thermal resistance double sided PCB with 2 internal planes, natural convection3 JA 58 C/W 4 D Thermal resistance double sided PCB with 2 internal planes @ 200 ft/min3 JMA 51 C/W 5 D Junction to Board4 JB 29 C/W 6 D Junction to Case5 JC 20 C/W JT 4 C/W 7 6 D Junction to Package Top 32-pin LQFP 8 D Thermal resistance single sided PCB, natural convection2 JA 81 84 C/W 9 D Thermal resistance single sided PCB @ 200 ft/min3 JMA 68 70 C/W 10 D Thermal resistance double sided PCB with 2 internal planes, natural convection3 JA 57 56 C/W 11 D Thermal resistance double sided PCB with 2 internal planes @ 200 ft/min3 JMA 50 49 C/W 12 D Junction to Board4 JB 35 32 C/W 13 D Junction to Case5 JC 25 23 C/W JT 8 6 C/W 14 6 D Junction to Package Top 48-pin LQFP 15 D Thermal resistance single sided PCB, natural convection2 JA 81 80 79 75 C/W 16 D Thermal resistance single sided PCB @ 200 ft/min3 JMA 68 67 66 62 C/W 17 D Thermal resistance double sided PCB with 2 internal planes, natural convection3 JA 57 56 56 51 C/W 18 D Thermal resistance double sided PCB with 2 internal planes @ 200 ft/min3 JMA 50 50 49 45 C/W 19 D Junction to Board4 JB 35 34 33 30 C/W 20 D Junction to Case5 JC 25 24 21 19 C/W JT 8 6 4 N/A C/W 21 6 D Junction to Package Top MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1185 Electrical Characteristics Table A-5. Thermal Package Characteristics1 Num C Rating Symbol S12G64, S12GN32, S12G128, S12G240, S12GA64, S12GNA32, S12GA128, S12GA240, S12G48, Unit S12GN16, S12G96, S12G192, S12GN48, S12GNA16 S12GA96 S12GA192 S12GA64 48-pin QFN 22 D Thermal resistance single sided PCB, natural convection2 JA 82 C/W 23 D Thermal resistance single sided PCB @ 200 ft/min3 JMA 67 C/W 24 D Thermal resistance double sided PCB with 2 internal planes, natural convection3 JA 28 C/W 25 D Thermal resistance double sided PCB with 2 internal planes @ 200 ft/min3 JMA 23 C/W 26 D Junction to Board4 JB 11 C/W 27 D Junction to Case5 JC N/A C/W JT 4 C/W 28 6 D Junction to Package Top 64-pin LQFP 29 D Thermal resistance single sided PCB, natural convection2 JA 70 70 70 C/W 30 D Thermal resistance single sided PCB @ 200 ft/min3 JMA 59 58 58 C/W 31 D Thermal resistance double sided PCB with 2 internal planes, natural convection3 JA 52 52 52 C/W 32 D Thermal resistance double sided PCB with 2 internal planes @ 200 ft/min3 JMA 46 46 45 C/W 33 D Junction to Board4 JB 34 34 35 C/W 34 D Junction to Case5 JC 20 18 17 C/W JT 5 4 N/A C/W 35 6 D Junction to Package Top 100-pin LQFP 36 D Thermal resistance single sided PCB, natural convection2 JA 61 62 C/W 37 D Thermal resistance single sided PCB @ 200 ft/min3 JMA 51 55 C/W 38 D Thermal resistance double sided PCB with 2 internal planes, natural convection3 JA 49 51 C/W 39 D Thermal resistance double sided PCB with 2 internal planes @ 200 ft/min3 JMA 43 47 C/W 40 D Junction to Board4 JB 34 37 C/W 41 D Junction to Case5 JC 16 17 C/W JT 3 N/A C/W 42 6 D Junction to Package Top MC9S12G Family Reference Manual Rev.1.28 1186 NXP Semiconductors Electrical Characteristics 1 The values for thermal resistance are achieved by package simulations Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.J Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. .Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured in simulation on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured in simulation by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. JT is a useful value to use to estimate junction temperature in a steady state customer enviroment. 2 3 4 5 6 A.2 I/O Characteristics This section describes the characteristics of all I/O pins except EXTAL, XTAL, TEST, and supply pins. Table A-6. 3.3-V I/O Characteristics (Junction Temperature From –40C To +150C) Conditions are 3.15 V < VDD35 < 3.6 V junction temperature from –40C to +150C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. Num C Rating Symbol Min Typ Max Unit 1 P Input high voltage VIH 0.65*VDD35 — — V 2 T Input high voltage VIH — — VDD35+0.3 V 3 P Input low voltage VIL — — 0.35*VDD35 V 4 T Input low voltage VIL VSS35 – 0.3 — — V 5 C Input hysteresis VHYS 0.06*VDD35 — 0.3*VDD35 mV 6 P Input leakage current (pins in high impedance input mode)1 Vin = VDD35 or VSS35 +125C to < TJ < 150C +105C to < TJ < 125 –40C to < TJ < 105C A Iin -1 -0.5 -0.4 — — — 1 0.5 0.4 VDD35-0.4 — — — 7 P Output high voltage (pins in output mode) IOH = –1.75 mA V 8 C Output low voltage (pins in output mode) IOL = +1.75 mA V — 9 P Internal pull up device current VIH min > input voltage > VIL max IPUL -1 10 P Internal pull down device current VIH min > input voltage > VIL max IPDH 1 11 D Input capacitance Cin — IICS IICP –2.5 –25 12 OH OL 2 T Injection current Single pin limit Total device limit, sum of all injected currents — — 7 0.4 –70 70 — — V V A A pF mA 2.5 25 1 Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8°C to 12°C in the temperature range from 50C to 125C. 2 Refer to Section A.1.4, “Current Injection” for more details MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1187 Electrical Characteristics Table A-7. 3.3-V I/O Characteristics (Junction Temperature From +150C To +160C) Conditions are 3.15 V < VDD35 < 3.6 V junction temperature from +150C to +160C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. Num C Rating Symbol Min Typ Max Unit 1 M Input high voltage VIH 0.65*VDD35 — — V 2 T Input high voltage VIH — — VDD35+0.3 V 3 M Input low voltage VIL — — 0.35*VDD35 V 4 T Input low voltage VIL VSS35 – 0.3 — — V 5 C Input hysteresis VHYS 0.06*VDD35 — 0.3*VDD35 mV 6 M Input leakage current (pins in high impedance input mode)1 Vin = VDD35 or VSS35 Iin -1 — 1 A 7 P Output high voltage (pins in output mode) IOH = –1.75 mA V VDD35-0.4 — — V 8 C Output low voltage (pins in output mode) IOL = +1.75 mA VOL — — 9 M Internal pull up device current VIH min > input voltage > VIL max IPUL -1 10 M Internal pull down device current VIH min > input voltage > VIL max IPDH 1 11 D Input capacitance Cin — 12 T Injection current2 Single pin limit Total device limit, sum of all injected currents IICS IICP –2.5 –25 OH — — 7 0.4 –70 70 — — V A A pF mA 2.5 25 1 Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8°C to 12°C in the temperature range from 50C to 125C. 2 Refer to Section A.1.4, “Current Injection” for more details MC9S12G Family Reference Manual Rev.1.28 1188 NXP Semiconductors Electrical Characteristics Table A-8. 5-V I/O Characteristics (Junction Temperature From –40C To +150C) Conditions are 4.5 V < VDD35 < 5.5 V junction temperature from –40C to +150C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. Num C Rating Symbol Min Typ Max Unit 1 P Input high voltage VIH 0.65*VDD35 — — V 2 T Input high voltage VIH — — VDD35+0.3 V 3 P Input low voltage VIL — — 0.35*VDD35 V 4 T Input low voltage VIL VSSRX–0.3 — — V 5 C Input hysteresis VHYS 0.06*VDD35 — 0.3*VDD35 mV 6 P Input leakage current (pins in high impedance input mode)1 Vin = VDD35 or VSS35 +125C to < TJ < 150C +105C to < TJ < 125 –40C to < TJ < 105C A Iin -1 -0.5 -0.4 — — — 1 0.5 0.4 VDD35 – 0.8 — — V 7 P Output high voltage (pins in output mode) IOH = –4 mA V 8 P Output low voltage (pins in output mode) IOL = +4mA VOL — — 0.8 V 9 P Internal pull up current VIH min > input voltage > VIL max IPUL -10 — -130 A 10 P Internal pull down current VIH min > input voltage > VIL max IPDH 10 — 130 A 11 D Input capacitance Cin — 7 — pF 12 current2 IICS IICP –2.5 –25 T Injection Single pin limit Total device Limit, sum of all injected currents OH — mA 2.5 25 1 Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8°C to 12°C in the temperature range from 50C to 125C. 2 Refer to Section A.1.4, “Current Injection” for more details MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1189 Electrical Characteristics Table A-9. 5-V I/O Characteristics (Junction Temperature From +150C To +160C) Conditions are 4.5 V < VDD35 < 5.5 V junction temperature from +150C to +160C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. Num C Rating Symbol Min Typ Max Unit 1 M Input high voltage VIH 0.65*VDD35 — — V 2 T Input high voltage VIH — — VDD35+0.3 V 3 M Input low voltage VIL — — 0.35*VDD35 V 4 T Input low voltage VIL VSSRX–0.3 — — V 5 C Input hysteresis VHYS 0.06*VDD35 — 0.3*VDD35 mV 6 M Input leakage current (pins in high impedance input mode)1 Vin = VDD35 or VSS35 Iin -1 — 1 A 7 M Output high voltage (pins in output mode) IOH = –4 mA V VDD35 – 0.8 — — V 8 M Output low voltage (pins in output mode) IOL = +4mA VOL — — 0.8 V 9 M Internal pull up current VIH min > input voltage > VIL max IPUL -10 — -130 A 10 M Internal pull down current VIH min > input voltage > VIL max IPDH 10 — 130 A 11 D Input capacitance Cin — 7 — pF 12 T Injection current2 Single pin limit Total device Limit, sum of all injected currents IICS IICP –2.5 –25 OH — mA 2.5 25 1 Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8°C to 12°C in the temperature range from 50C to 125C. 2 Refer to Section A.1.4, “Current Injection” for more details Table A-10. Pin Interrupt Characteristics (Junction Temperature From –40C To +150C) Conditions are 3.13V < VDD35 < 5.5 V unless otherwise noted. Num C 1 Rating Symbol Min Typ Max Unit 1 P Port J, P, AD interrupt input pulse filtered (STOP)1 tP_MASK — — 3 s 2 P Port J, P, AD interrupt input pulse passed (STOP) 1 tP_PASS 10 — — s 3 D Port J, P, AD interrupt input pulse filtered (STOP) in number of bus clock cycles of period 1/fbus nP_MASK — — 3 4 D Port J, P, AD interrupt input pulse passed (STOP) in number of bus clock cycles of period 1/fbus nP_PASS 4 — — 5 D IRQ pulse width, edge-sensitive mode (STOP) in number of bus clock cycles of period 1/fbus nIRQ 1 — — Parameter only applies in stop or pseudo stop mode. MC9S12G Family Reference Manual Rev.1.28 1190 NXP Semiconductors Electrical Characteristics Table A-11. Pin Interrupt Characteristics (Junction Temperature From +150C To +160C) Conditions are 3.13V < VDD35 < 5.5 V unless otherwise noted. Nu m 1 C Rating Symbol Min Typ Max Unit 1 M Port J, P, AD interrupt input pulse filtered (STOP)1 tP_MASK — — 3 s 2 M Port J, P, AD interrupt input pulse passed (STOP) 1 tP_PASS 10 — — s 3 D Port J, P, AD interrupt input pulse filtered (STOP) in number of bus clock cycles of period 1/fbus nP_MASK — — 3 4 D Port J, P, AD interrupt input pulse passed (STOP) in number of bus clock cycles of period 1/fbus nP_PASS 4 — — 5 D IRQ pulse width, edge-sensitive mode (STOP) in number of bus clock cycles of period 1/fbus nIRQ 1 — — Parameter only applies in stop or pseudo stop mode. A.3 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.3.1 Measurement Conditions Run current is measured on the VDDX, VDDR1, and VDDA2 pins. It does not include the current to drive external loads. Unless otherwise noted the currents are measured in special single chip mode and the CPU code is executed from RAM. For Run and Wait current measurements PLL is on and the reference clock is the IRC1M trimmed to 1MHz. The bus frequency is 25MHz and the CPU frequency is 50MHz. Table A-12., Table A-13. and Table A-15. show the configuration of the CPMU module and the peripherals for Run, Wait and Stop current measurement. Table A-12. CPMU Configuration for Pseudo Stop Current Measurement CPMU REGISTER CPMUCLKS Bit settings/Conditions PLLSEL=0, PSTP=1, PRE=PCE=RTIOSCSEL=COPOSCSEL=1 1. On some packages VDDR is bonded to VDDX and the pin is named VDDXR. Refer to Section 1.8, “Device Pinouts” for further details. 2. On some packages VDDA is connected with VDDXR and the common pin is named VDDXRA.On some packages VSSA is connected to VSSX and the common pin is named VSSXA. See section Section 1.8, “Device Pinouts” for further details. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1191 Electrical Characteristics Table A-12. CPMU Configuration for Pseudo Stop Current Measurement CPMU REGISTER Bit settings/Conditions CPMUOSC OSCE=1, External Square wave on EXTAL fEXTAL=4MHz, VIH= 1.8V, VIL=0V CPMURTI RTDEC=0, RTR[6:4]=111, RTR[3:0]=1111; CPMUCOP WCOP=1, CR[2:0]=111 Table A-13. CPMU Configuration for Run/Wait and Full Stop Current Measurement CPMU REGISTER CPMUSYNR CPMUPOSTDIV Bit settings/Conditions VCOFRQ[1:0]=01,SYNDIV[5:0] = 24 POSTDIV[4:0]=0 CPMUCLKS PLLSEL=1 CPMUOSC OSCE=0, Reference clock for PLL is fref=firc1m trimmed to 1MHz API settings for STOP current measurement CPMUAPICTL APIEA=0, APIFE=1, APIE=0 CPMUAPITR trimmed to 10Khz CPMUAPIRH/RL set to $FFFF Table A-14. GPIO Configuration for Full Stop and Pseudo Stop Current Measurement PIM REGISTER DDRx PUCR/PERx Configuration All GPIO pins configured as outputs All pull-ups/pull-downs disabled Table A-15. Peripheral Configurations for Run & Wait Current Measurement Peripheral MSCAN Configuration Configured to loop-back mode using a bit rate of 1Mbit/s MC9S12G Family Reference Manual Rev.1.28 1192 NXP Semiconductors Electrical Characteristics Table A-15. Peripheral Configurations for Run & Wait Current Measurement Peripheral Configuration SPI Configured to master mode, continuously transmit data (0x55 or 0xAA) at 1Mbit/s SCI Configured into loop mode, continuously transmit data (0x55) at speed of 57600 baud PWM Configured to toggle its pins at the rate of 40kHz ADC The peripheral is configured to operate at its maximum specified frequency and to continuously convert voltages on all input channels in sequence. DBG The module is enabled and the comparators are configured to trigger in outside range.The range covers all the code executed by the core. TIM The peripheral shall be configured to output compare mode, pulse accumulator and modulus counter enabled. COP & RTI ACMP1 Both modules are enabled. The module is enabled with analog output on. The ACMPP and ACMPM are toggling with 0-1 and 1-0. DAC2 DAC0 and DAC1 is buffered at full voltage range (DACxCTL = $87). RVA3 The module is enabled and ADC is running at 6.25MHz with maximum bus freq 1 Onlly available on S12GN16, S12GN32, S12GN48, S12G48, and S12G64 Only available on S12G192, S12GA192, S12G340, and S12GA240 3 Only available on S12GA192 and S12GA240 2 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1193 Electrical Characteristics Table A-16. Run and Wait Current Characteristics (Junction Temperature From –40C To +150C) Conditions are: VDDR=5.5V, TA=125C, see Table A-13. and Table A-15. Num C Rating Symbol Min Typ Max Unit S12GN16, S12GN32 1 P IDD Run Current (code execution from RAM) IDDRr 12.5 16 mA 2 C IDD Run Current (code execution from flash) IDDRf 13 17 mA 3 P IDD Wait Current IDDW 7.2 10 mA S12GN48, S12G48, S12G64 4 P IDD Run Current (code execution from RAM) IDDRr 14 19 mA 5 C IDD Run Current (code execution from flash) IDDRf 15.5 20 mA 6 P IDD Wait Current IDDW 8.7 11 mA S12G96, S12G128 7 P IDD Run Current (code execution from RAM) IDDRr 15 21 mA 8 C IDD Run Current (code execution from flash) IDDRf 17 22 mA 9 P IDD Wait Current IDDW 9 11.5 mA S12G192, S12GA192, S12G240, S12GA240 10 P IDD Run Current (code execution from RAM) IDDRr 18 22.5 mA 11 C IDD Run Current (code execution from flash) IDDRf 17 23.5 mA 12 P IDD Wait Current IDDW 9.5 12 mA Table A-17. Run and Wait Current Characteristics (Junction Temperature From +150C To +160C) Conditions are: VDDR=5.5V, TA=150C, see Table A-13. and Table A-15. Num C Rating Symbol Min Typ Max Unit S12GN16, S12GN32 M IDD Run Current (code execution from RAM) IDDRr 12.7 mA 2 C IDD Run Current (code execution from flash) IDDRf 13.2 mA 3 M IDD Wait Current IDDW 7.4 mA 1 MC9S12G Family Reference Manual Rev.1.28 1194 NXP Semiconductors Electrical Characteristics Table A-18. Full Stop Current Characteristics Conditions are: Typ: VDDX,VDDR,VDDA=5V, Max: VDDX,VDDR,VDDA=5.5V API see Table A-13.and Table A-14. Num C Rating Symbol Min Typ Max Unit S12GN16, S12GN32 Stop Current API disabled 1 P -40C IDDS 14.4 24 A 2 P 25C IDDS 16.5 28 A 3 P 150C IDDS 120 320 A 4 C 160C IDDS 140 A Stop Current API enabled 5 C -40C IDDS 18.5 A 6 C 25C IDDS 21.5 A 7 C 150C IDDS 130 A 8 C 160C IDDS 150 A S12GN48, S12G48, S12G64 Stop Current API disabled 9 P -40C IDDS 16 27 A 10 P 25C IDDS 18.5 30 A 11 P 150C IDDS 140 370 A Stop Current API enabled 12 C -40C IDDS 20 A 13 C 25C IDDS 23.5 A 14 C 150C IDDS 150 A S12G96, S12G128 Stop Current API disabled 15 P -40C IDDS 16.5 28 A 16 P 25C IDDS 19 32 A 17 P 150C IDDS 150 400 A 18 C -40C IDDS 20.5 A 19 C 25C IDDS 24 A 20 C 150C IDDS 160 A Stop Current API enabled S12G192, S12GA192, S12G240, S12GA240 Stop Current API disabled 21 P -40C IDDS 17 30 A 22 P 25C IDDS 19.5 34 A 23 P 150C IDDS 155 420 A Stop Current API enabled 24 C -40C IDDS 21 A 25 C 25C IDDS 24.5 A 26 C 150C IDDS 160 A MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1195 Electrical Characteristics Table A-19. Pseudo Stop Current Characteristics Conditions are: VDDX=5V, VDDR=5V, VDDA=5V, RTI and COP and API enabled, see Table A-12.and Table A-14. Num C Rating Symbol Min Typ Max Unit S12GN16, S12GN32 1 C -40C IDDPS 155 A 2 C 25C IDDPS 165 A 3 C 150C IDDPS 265 A 4 C 160C IDDPS 295 A -40C IDDPS 160 A S12GN48, S12G48, S12G64 5 C 6 C 25C IDDPS 170 A 7 C 150C IDDPS 285 A -40C IDDPS 165 A S12G96, S12G128 8 C 9 C 25C IDDPS 175 A 10 C 150C IDDPS 320 A S12G192, S12GA192, S12G240, S12GA240 11 C -40C IDDPS 175 A 12 C 25C IDDPS 185 A 13 C 150C IDDPS 430 A A.4 ADC Characteristics This section describes the characteristics of the analog-to-digital converter. A.4.1 ADC Operating Characteristics The Table A-20 and Table A-21 show conditions under which the ADC operates. The following constraints exist to obtain full-scale, full range results: VSSA VRLVINVRHVDDA MC9S12G Family Reference Manual Rev.1.28 1196 NXP Semiconductors Electrical Characteristics This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table A-20. ADC Operating Characteristics Supply voltage 3.13 V < VDDA < 5.5 V, -40oC < TJ < TJmax1 Num C 1 2 D Reference potential Low High Symbol Min Typ Max Unit VRL VRH VSSA VDDA/2 — — VDDA/2 VDDA V V 2 D Voltage difference VDDX to VDDA VDDX –2.35 0 0.1 V 3 D Voltage difference VSSX to VSSA VSSX –0.1 0 0.1 V 4 C Differential reference voltage VRH-VRL 3.13 5.0 5.5 V 5 C ADC Clock Frequency (derived from bus clock via the prescaler bus) 0.25 8.0 MHz 20 19 17 42 41 39 ADC clock Cycles 8 1 Rating ADC Conversion Period2 D 12 bit resolution: 10 bit resolution: 8 bit resolution: fATDCLk NCONV12 NCONV10 NCONV8 see Table A-4 The minimum time assumes a sample time of 4 ADC clock cycles. The maximum time assumes a sample time of 24 ADC clock cycles and the discharge feature (SMP_DIS) enabled, which adds 2 ADC clock cycles. A.4.2 Factors Influencing Accuracy Source resistance, source capacitance and current injection have an influence on the accuracy of the ADC. A further factor is that port AD pins that are configured as output drivers switching. A.4.2.1 Differential Reference Voltage The accuracy is reduced if the differential reference voltage is less than 3.13V when using the ATD in the 3.3V range or if the differential reference voltage is less than 4.5V when using the ATD in the 5V range. A.4.2.2 Port AD Output Drivers Switching Port AD output drivers switching can adversely affect the ADC accuracy whilst converting the analog voltage on other port AD pins because the output drivers are supplied from the VDDA/VSSA ADC supply pins. Although internal design measures are implemented to minimize the affect of output driver noise, it is recommended to configure port AD pins as outputs only for low frequency, low load outputs. The impact on ADC accuracy is load dependent and not specified. The values specified are valid under condition that no port AD output drivers switch during conversion. A.4.2.3 Source Resistance Due to the input pin leakage current as specified in conjunction with the source resistance there will be a voltage drop from the signal source to the ADC input. The maximum source resistance RS specifies results MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1197 Electrical Characteristics in an error (10-bit resolution) of less than 1/2 LSB (2.5 mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance of up to 10Kohm are allowed. A.4.2.4 Source Capacitance When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage  1LSB (10-bit resilution), then the external filter capacitor, Cf  1024 * (CINS–CINN). A.4.2.5 Current Injection There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF (in 10-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive condition. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as: VERR = K * RS * IINJ with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. Table A-21. ADC Electrical Characteristics Supply voltage 3.13 V < VDDA < 5.5 V, -40oC < TJ < TJmax1 Num C 1 2 Rating Symbol Min Typ Max Unit RS — — 1 K 1 C Max input source resistance2 2 D Total input capacitance Non sampling Total input capacitance Sampling CINN CINS — — — — 10 16 pF 3 D Input internal Resistance RINA - 5 15 k 4 C Disruptive analog input current INA -2.5 — 2.5 mA 5 C Coupling ratio positive current injection Kp — — 1E-4 A/A 6 C Coupling ratio negative current injection Kn — — 5E-3 A/A see Table A-4 1 Refer to A.4.2.3 for further information concerning source resistance A.4.3 ADC Accuracy Table A-22 and Table A-27 specifies the ADC conversion performance excluding any errors due to current injection, input capacitance and source resistance. MC9S12G Family Reference Manual Rev.1.28 1198 NXP Semiconductors Electrical Characteristics A.4.3.1 ADC Accuracy Definitions For the following definitions see also Figure A-1. Differential non-linearity (DNL) is defined as the difference between two adjacent switching steps. V –V i i–1 DNL  i  = -------------------------- – 1 1LSB The integral non-linearity (INL) is defined as the sum of all DNLs: n INL  n  =  V –V n 0 DNL  i  = --------------------- – n 1LSB i=1 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1199 Electrical Characteristics DNL Vi-1 10-Bit Absolute Error Boundary LSB Vi $3FF 8-Bit Absolute Error Boundary $3FE $3FD $FF $3FC $3FB $3FA $3F9 $FE $3F8 $3F7 $3F6 $3F5 10-Bit Resolution $3F3 9 Ideal Transfer Curve 2 8 8-Bit Resolution $FD $3F4 7 10-Bit Transfer Curve 6 5 1 4 3 8-Bit Transfer Curve 2 1 0 5 10 15 20 25 30 35 40 45 55 60 65 70 75 80 85 90 95 100 105 110 115 120 5000 + Vin mV Figure A-1. ADC Accuracy Definitions NOTE Figure A-1 shows only definitions, for specification values refer to Table A-22 and Table A-27. MC9S12G Family Reference Manual Rev.1.28 1200 NXP Semiconductors Electrical Characteristics Table A-22. ADC Conversion Performance 5V range (Junction Temperature From –40C To +150C) S12GNA16, S12GNA32, S12GAS48, S12GA64, S12GA96, S12GA128, S12GA192 and S12GA240 Supply voltage 4.5V < VDDA < 5.5 V, -40oC < TJ < 150oC, VREF = VRH - VRL = VDDA, fADCCLK = 8.0MHz The values are tested to be valid with no port AD output drivers switching simultaneous with conversions. Rating1 Num C 2 Min Typ Max P Resolution 12-Bit LSB 2 P Differential Nonlinearity 12-Bit DNL -4 2 4 counts 3 P Integral Nonlinearity 12-Bit INL -5 2.5 5 counts 12-Bit AE -7 4 7 counts Error2 1.25 Unit 1 mV 4 P Absolute 5 C Resolution 10-Bit LSB 6 C Differential Nonlinearity 10-Bit DNL -1 0.5 1 counts 7 C Integral Nonlinearity 10-Bit INL -2 1 2 counts -3 2 3 counts 2 5 mV 8 C Absolute Error 10-Bit AE 9 C Resolution 8-Bit LSB 10 C Differential Nonlinearity 8-Bit DNL -0.5 0.3 0.5 counts 11 C Integral Nonlinearity 8-Bit INL -1 0.5 1 counts 8-Bit AE -1.5 1 1.5 counts 12 1 Symbol C Absolute Error2 20 mV The 8-bit and 10-bit mode operation is structurally tested in production test. Absolute values are tested in 12-bit mode. These values include the quantization error which is inherently 1/2 count for any A/D converter. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1201 Electrical Characteristics Table A-23. ADC Conversion Performance 5V range (Junction Temperature From +150C To +160C) S12GNA16, S12GNA32 Supply voltage 4.5V < VDDA < 5.5 V, +150oC < TJ < 160oC, VREF = VRH - VRL = VDDA, fADCCLK = 8.0MHz The values are tested to be valid with no port AD output drivers switching simultaneous with conversions. Rating1 Num C 2 Min Typ Max Unit 1 M Resolution 12-Bit LSB 1.25 mV 2 M Differential Nonlinearity 12-Bit DNL 2 counts 3 M Integral Nonlinearity 12-Bit INL 2.5 counts 12-Bit AE 4 counts Error2 4 M Absolute 5 C Resolution 10-Bit LSB 5 mV 6 C Differential Nonlinearity 10-Bit DNL 0.5 counts 7 C Integral Nonlinearity 10-Bit INL 1 counts 2 8 C Absolute Error 10-Bit AE 2 counts 9 C Resolution 8-Bit LSB 20 mV 10 C Differential Nonlinearity 8-Bit DNL 0.3 counts 11 C Integral Nonlinearity 8-Bit INL 0.5 counts 8-Bit AE 1 counts 12 1 Symbol C Absolute Error2 The 8-bit and 10-bit mode operation is structurally tested in production test. Absolute values are tested in 12-bit mode. These values include the quantization error which is inherently 1/2 count for any A/D converter. MC9S12G Family Reference Manual Rev.1.28 1202 NXP Semiconductors Electrical Characteristics Table A-24. ADC Conversion Performance 5V range (Junction Temperature From –40C To +150C) S12GN16, S12GN32, S12GN48, S12G48, S12G64, S12G96, S12G128, S12G192, and S12G240 Supply voltage 4.5V < VDDA < 5.5 V, -40oC < TJ < 150oC, VREF = VRH - VRL = VDDA, fADCCLK = 8.0MHz The values are tested to be valid with no port AD output drivers switching simultaneous with conversions. Rating1 Num C Symbol Min Typ Max 1 P Resolution 10-Bit LSB 2 P Differential Nonlinearity 10-Bit DNL -1 0.5 1 counts 3 P Integral Nonlinearity 10-Bit INL -2 1 2 counts -3 -4 2 2 3 4 counts 2 3 5 Unit mV 4 P Absolute Error 10-Bit 10-Bit4 AE 5 C Resolution 8-Bit LSB 6 C Differential Nonlinearity 8-Bit DNL -0.5 0.3 0.5 counts 7 C Integral Nonlinearity 8-Bit INL -1 0.5 1 counts 8 C Absolute Error2 8-Bit AE -1.5 1 1.5 counts 20 mV 1 The 8-bit mode operation is structurally tested in production test. Absolute values are tested in 10-bit mode. These values include the quantization error which is inherently 1/2 count for any A/D converter. 3 LQFP 48 and bigger 4 LQFP 32 and smaller 2 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1203 Electrical Characteristics Table A-25. ADC Conversion Performance 5V range (Junction Temperature From +150C To +160C) S12GN16, S12GN32 Supply voltage 4.5V < VDDA < 5.5 V, 150oC < TJ < 160oC, VREF = VRH - VRL = VDDA, fADCCLK = 8.0MHz The values are tested to be valid with no port AD output drivers switching simultaneous with conversions. Rating1 Num C Symbol Min Typ Max Unit 1 M Resolution 10-Bit LSB 5 mV 2 M Differential Nonlinearity 10-Bit DNL 0.5 counts 3 M Integral Nonlinearity 10-Bit INL 1 counts 2 3 4 M Absolute Error 10-Bit 10-Bit4 AE 2 2 counts 5 C Resolution 8-Bit LSB 20 mV 6 C Differential Nonlinearity 8-Bit DNL 0.3 counts 7 C Integral Nonlinearity 8-Bit INL 0.5 counts 8 C Absolute Error2 8-Bit AE 1 counts 1 The 8-bit mode operation is structurally tested in production test. Absolute values are tested in 10-bit mode. These values include the quantization error which is inherently 1/2 count for any A/D converter. 3 LQFP 48 and bigger 4 LQFP 32 and smaller 2 Table A-26. ADC Conversion Performance 3.3V range (Junction Temperature From –40C To +150C) S12GNA16, S12GNA32, S12GAS48, S12GA64, S12GA96, S12GA128, S12GA192 and S12GA240 Supply voltage 3.13V < VDDA < 4.5 V, -40oC < TJ < 150oC, VREF = VRH - VRL = VDDA, fADCCLK = 8.0MHz The values are tested to be valid with no port AD output drivers switching simultaneous with conversions. Num C 1 Rating1 Symbol Min Typ Max 0.80 Unit 1 P Resolution 12-Bit LSB mV 2 P Differential Nonlinearity 12-Bit DNL -6 3 6 counts 3 P Integral Nonlinearity 12-Bit INL -7 3 7 counts 4 P Absolute Error2 12-Bit AE -8 4 8 counts 5 C Resolution 10-Bit LSB 6 C Differential Nonlinearity 10-Bit DNL -1.5 1 1.5 counts 7 C Integral Nonlinearity 10-Bit INL -2 1 2 counts 8 C Absolute Error2 10-Bit AE -3 2 3 counts 9 C Resolution 8-Bit LSB 10 C Differential Nonlinearity 8-Bit DNL -0.5 0.3 0.5 counts 11 C Integral Nonlinearity 8-Bit INL -1 0.5 1 counts 12 C Absolute Error2 8-Bit AE -1.5 1 1.5 counts 3.22 mV 12.89 mV The 8-bit and 10-bit mode operation is structurally tested in production test. Absolute values are tested in 12-bit mode. MC9S12G Family Reference Manual Rev.1.28 1204 NXP Semiconductors Electrical Characteristics 2 These values include the quantization error which is inherently 1/2 count for any A/D converter. Table A-27. ADC Conversion Performance 3.3V range (Junction Temperature From +150C To +160C) S12GNA16, S12GNA32 Supply voltage 3.13V < VDDA < 4.5 V, 150oC < TJ < 160oC, VREF = VRH - VRL = VDDA, fADCCLK = 8.0MHz The values are tested to be valid with no port AD output drivers switching simultaneous with conversions. Rating1 Num C 1 2 Symbol Min Typ Max Unit 1 M Resolution 12-Bit LSB 0.80 mV 2 M Differential Nonlinearity 12-Bit DNL 3 counts 3 M Integral Nonlinearity 12-Bit INL 3 counts 4 M Absolute Error2 12-Bit AE 4 counts 5 C Resolution 10-Bit LSB 3.22 mV 6 C Differential Nonlinearity 10-Bit DNL 1 counts 7 C Integral Nonlinearity 10-Bit INL 1 counts 8 C Absolute Error2 10-Bit AE 2 counts 9 C Resolution 8-Bit LSB 12.89 mV 10 C Differential Nonlinearity 8-Bit DNL 0.3 counts 11 C Integral Nonlinearity 8-Bit INL 0.5 counts 12 C Absolute Error2 8-Bit AE 1 counts The 8-bit and 10-bit mode operation is structurally tested in production test. Absolute values are tested in 12-bit mode. These values include the quantization error which is inherently 1/2 count for any A/D converter. Table A-28. ADC Conversion Performance 3.3V range (Junction Temperature From –40C To +150C) S12GN16, S12GN32, S12GN48, S12G48, S12G64, S12G96, S12G128, S12G192, and S12G240 Supply voltage 3.13V < VDDA < 4.5 V, -40oC < TJ < 150oC, VREF = VRH - VRL = VDDA, fADCCLK = 8.0MHz The values are tested to be valid with no port AD output drivers switching simultaneous with conversions. Rating1 Num C Symbol Min Typ Max 1 P Resolution 10-Bit LSB 2 P Differential Nonlinearity 10-Bit DNL -1.5 1 1.5 counts 3 P Integral Nonlinearity 10-Bit INL -2 1 2 counts 10-Bit3 AE -3 -4 2 2 3 4 counts Error2 3.22 Unit mV 4 P Absolute 5 C Resolution 8-Bit LSB 6 C Differential Nonlinearity 8-Bit DNL -0.5 0.3 0.5 counts 7 C Integral Nonlinearity 8-Bit INL -1 0.5 1 counts 8 C Absolute Error2 8-Bit AE -1.5 1 1.5 counts 10-Bit4 12.89 mV MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1205 Electrical Characteristics 1 The 8-bit mode operation is structurally tested in production test. Absolute values are tested in 10-bit mode. These values include the quantization error which is inherently 1/2 count for any A/D converter. 3 LQFP 48 and bigger 4 LQFP 32 and smaller 2 Table A-29. ADC Conversion Performance 3.3V range (Junction Temperature From +150C To +160C) S12GN16, S12GN32 Supply voltage 3.13V < VDDA < 4.5 V, 150oC < TJ < 160oC, VREF = VRH - VRL = VDDA, fADCCLK = 8.0MHz The values are tested to be valid with no port AD output drivers switching simultaneous with conversions. Num C Rating1 Symbol Min Typ Max Unit 1 M Resolution 10-Bit LSB 3.22 mV 2 M Differential Nonlinearity 10-Bit DNL 1 counts 3 M Integral Nonlinearity 10-Bit INL 1 counts 4 M Absolute Error2 10-Bit3 10-Bit4 AE 2 2 counts 5 C Resolution 8-Bit LSB 12.89 mV 6 C Differential Nonlinearity 8-Bit DNL 0.3 counts 7 C Integral Nonlinearity 8-Bit INL 0.5 counts 8 C Absolute Error2 8-Bit AE 1 counts 1 The 8-bit mode operation is structurally tested in production test. Absolute values are tested in 10-bit mode. These values include the quantization error which is inherently 1/2 count for any A/D converter. 3 LQFP 48 and bigger 4 LQFP 32 and smaller 2 MC9S12G Family Reference Manual Rev.1.28 1206 NXP Semiconductors Electrical Characteristics Table A-30. ADC Conversion Performance 5V range, RVA enabled Supply voltage VDDA =5.0 V, -40oC < TJ < 150oC. VRH = 5.0V. fADCCLK = 0.25 .. 2MHz 1 The values are tested to be valid with no port AD/C output drivers switching simultaneous with conversions. Num C Rating Symbol Min Typ Max Unit 1 P Resolution 12-Bit LSB 0.61 2 P Differential Nonlinearity 12-Bit DNL 3 4 counts 3 P Integral Nonlinearity 12-Bit INL 3.5 5 counts 4 C Absolute Error2 12-Bit AE 8 counts 5 P internal VRH reference voltage LQFP48, LQFP64, LQFP100 KGD 6 P internal VRL reference voltage LQFP48, LQFP64, LQFP100 KGD temperature3 mV Vvrh_int 4.495 4.505 V Vvrh_int 4.490 4.510 V Vvrh_int 1.995 2.005V V Vvrl_int 1.990 2.010V V Vvrh_drift -2 2 mV -2.5 2.5 mV 7 C VRH_INT drift vs 8 C VRL_INT drift vs temperature Vvrl_drift 9 C rva turn on settling time tsettling_on 2.5 s 10 C rva turn off settling time tsettling_off 1 s 1 Upper limit of fADCCLK is restricted when RVA attenuation mode is engaged. These values include the quantization error which is inherently 1/2 count for any A/D converter and the error of the internally generated reference values.. 3 Please note: although different in value, drift of vrh_int and vrl_int will go in the same direction. 2 MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1207 Electrical Characteristics A.4.3.2 ADC Analog Input Parasitics Figure A-2. ADC Analog Input Parasitics VDDA sampling time is 4 to 24 adc clock cycles of 0.25MHz to 8MHz -> 96s >= tsample >= 500ns Ileakp < 0.5A PAD00PAD11 Ileakn < 0.5A Ctop 920 < Rpath < 9.9K (incl parasitics) 3.7pF < S/H Cap < 6.2pF (incl parasitics) Cbottom connected to low ohmic supply during sampling VSSA Ctop potential just prior to sampling is either a) ~ last converted channel potential or b) ground level if S/H discharge feature is enabled. Complete 10bit conversion takes between 19 and 41 adc clock cycles Switch resistance depends on input voltage, corner ranges are shown. Leakage current is guaranteed by specification. Tjmax=130oC A.4.4 ADC Temperature Sensor Table A-31. ADC Temperature Sensor Num C 1 A.5 T Rating Temperature Sensor Slope Symbol Min Typ Max Unit dVTS -4.0 -3.8 -3.6 mV/C ACMP Characteristics This section describes the electrical characteristics of the analog comparator. MC9S12G Family Reference Manual Rev.1.28 1208 NXP Semiconductors Electrical Characteristics Table A-32. ACMP Electrical Characteristics (Junction Temperature From –40C To +150C) Characteristics noted under conditions 3.13V = 100K to VSSA) buffered range A (load >= 100Kto VDDA) P buffered range B (load >= 100K to VSSA) buffered range B (load >= 100K to VDDA) 10 Symbol 0 0.15 - Unit V VDDA-0.15 VDDA V Vout full DAC Range B Output Voltage (DRIVE bit = 1)2 buffered range B with 6.4K load into resistor divider of 800 /6.56K between VDDA and VSSA. (equivalent load is >= 65Kto VSSA) or (equivalent load is >= 7.5K to VDDA) Vout full DAC Range B V 11 D Buffer Output Capacitive load Cload 0 - 100 pF 12 P Buffer Output Offset Voffset -30 - +30 mV 13 P Settling time tdelay - 3 5 s 14 D Reverence voltage high Vrefh VDDA-0.1V VDDA VDDA+0.1V V DRIVE bit = 1 is not recommended in this case. DRIVE bit = 0 is not allowed with this high load. A.7 A.7.1 NVM Timing Parameters The time base for all NVM program or erase operations is derived from the bus clock using the FCLKDIV register. The frequency of this derived clock must be set within the limits specified as fNVMOP. The NVM module does not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. When attempting to program or erase the NVM module at a lower frequency, a full program or erase transition is not assured. All timing parameters are a function of the bus clock frequency, fNVMBUS. All program and erase times are also a function of the NVM operating frequency, fNVMOP. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1211 Electrical Characteristics Each command timing is given by: 1 1 t command =  f NVMOP  cycle   --------------------- + f NVMBUS  cycle   -------------------------   f f NVMOP NVMBUS The timing parameters are captured exclusively during command execution (CCIF=0), excluding any time spent on the command write sequence to load and start the command. The formula above and the number of cycles in the following tables apply for the cases where the commands executed successfully in a new device, reflected in the minimum and typical timing parameters; however, due to aging, some of the commands will adjust their execution according to different margin settings and may eventually take longer to run than what the formula may return. The Max and Lfmax timing columns in the tables below already reflect this adjustment where applicable. A summary of key timing parameters can be found from Table A-35 to Table A-39. Table A-35. NVM Clock Timing Characteristics Num Rating Symbol Min Typ Max Unit 1 Bus frequency fNVMBUS 1 25 25 MHz 2 Operating frequency fNVMOP 0.8 1.0 1.05 MHz MC9S12G Family Reference Manual Rev.1.28 1212 NXP Semiconductors Electrical Characteristics Table A-36. NVM Timing Characteristics) S12GN16, S12GNA16, S12GN32, S12GNA32 Num 1 2 3 4 5 6 Command fNVMOP cycle fNVMBUS cycle Symbol Min1 Typ2 Max3 Lfmax4 Unit 1 Erase Verify All Blocks5,6 0 9233 tRD1ALL 0.37 0.37 0.74 18.47 ms 2 Erase Verify Block (Pflash)5 0 8737 tRD1BLK_P 0.35 0.35 0.7 17.47 ms 3 (EEPROM)6 0 1000 tRD1BLK_D 0.04 0.04 0.08 2 ms 4 Erase Verify P-Flash Section 0 486 tRD1SEC 19.44 19.44 38.88 972 ms 5 Read Once 0 445 tRDONCE 17.8 17.8 17.8 445 s 6 Program P-Flash (4 Word) 164 2935 tPGM_4 0.27 0.28 0.63 11.95 ms 7 Program Once 164 2888 tPGMONCE 0.27 0.28 0.28 3.09 ms 8 Erase All Blocks5,6 100066 9569 tERSALL 95.68 100.45 100.83 144.22 ms 9 Erase Flash Block (Pflash)5 100060 8975 tERSBLK_P 95.65 100.42 100.78 143.03 ms 10 Erase Flash Block (EEPROM)6 100060 1296 tERSBLK_D 95.35 100.11 100.16 127.67 ms 11 Erase P-Flash Sector 20015 875 tERSPG 19.1 20.05 20.09 26.77 ms 12 Unsecure Flash 100066 9647 tUNSECU 95.69 100.45 100.84 144.38 ms 13 Verify Backdoor Access Key 0 481 tVFYKEY 19.24 19.24 19.24 481 s 14 Set User Margin Level 0 404 tMLOADU 16.16 16.16 16.16 404 s 15 Set Factory Margin Level 0 413 tMLOADF 16.52 16.52 16.52 413 s 0.02 0.02 0.04 1.09 ms Erase Verify Block 16 Erase Verify EEPROM Section 0 546 tDRD1SEC 17 Program EEPROM (1 Word) 68 1565 tDPGM_1 0.13 0.13 0.32 6.35 ms 18 Program EEPROM (2 Word) 136 2512 tDPGM_2 0.23 0.24 0.54 10.22 ms 19 Program EEPROM (3 Word) 204 3459 tDPGM_3 0.33 0.34 0.76 14.09 ms 20 Program EEPROM (4 Word) 272 4406 tDPGM_4 0.44 0.45 0.98 17.96 ms 21 Erase EEPROM Sector 5015 753 tDERSPG 4.81 5.05 20.57 37.88 ms Minimum times are based on maximum fNVMOP and maximum fNVMBUS Typical times are based on typical fNVMOP and typical fNVMBUS Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging Lowest-frequency max times are based on minimum fNVMOP and minimum fNVMBUS plus aging Affected by Pflash size Affected by EEPROM size MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1213 Electrical Characteristics Table A-37. NVM Timing Characteristics) , S12GN48, S12G48, S12G64, S12GA64 Num 1 2 3 4 5 6 Command fNVMOP cycle fNVMBUS cycle Symbol Min1 Typ2 Max3 Lfmax4 Unit 1 Erase Verify All Blocks5,6 0 17937 tRD1ALL 0.72 0.72 1.43 35.87 ms 2 Erase Verify Block (Pflash)5 0 16924 tRD1BLK_P 0.68 0.68 1.35 33.85 ms 3 (EEPROM)6 0 1512 tRD1BLK_D 0.06 0.06 0.12 3.02 ms 4 Erase Verify P-Flash Section 0 476 tRD1SEC 19.04 19.04 38.08 952 ms 5 Read Once 0 445 tRDONCE 17.8 17.8 17.8 445 s 6 Program P-Flash (4 Word) 164 2925 tPGM_4 0.27 0.28 0.63 11.91 ms 7 Program Once 164 2888 tPGMONCE 0.27 0.28 0.28 3.09 ms 8 Erase All Blocks5,6 100066 18273 tERSALL 96.03 100.8 101.53 161.63 ms 9 Erase Flash Block (Pflash)5 100060 17157 tERSBLK_P 95.98 100.75 101.43 159.39 ms 10 Erase Flash Block (EEPROM)6 100060 1808 tERSBLK_D 95.37 100.13 100.2 128.69 ms 11 Erase P-Flash Sector 20015 865 tERSPG 19.1 20.05 20.08 26.75 ms 12 Unsecure Flash 100066 18351 tUNSECU 96.03 100.8 101.53 161.78 ms 13 Verify Backdoor Access Key 0 481 tVFYKEY 19.24 19.24 19.24 481 s 14 Set User Margin Level 0 399 tMLOADU 15.96 15.96 15.96 399 s 15 Set Factory Margin Level 0 408 tMLOADF 16.32 16.32 16.32 408 s 0.02 0.02 0.04 1.09 ms Erase Verify Block 16 Erase Verify EEPROM Section 0 546 tDRD1SEC 17 Program EEPROM (1 Word) 68 1565 tDPGM_1 0.13 0.13 0.32 6.35 ms 18 Program EEPROM (2 Word) 136 2512 tDPGM_2 0.23 0.24 0.54 10.22 ms 19 Program EEPROM (3 Word) 204 3459 tDPGM_3 0.33 0.34 0.76 14.09 ms 20 Program EEPROM (4 Word) 272 4406 tDPGM_4 0.44 0.45 0.98 17.96 ms 21 Erase EEPROM Sector 5015 753 tDERSPG 4.81 5.05 20.57 37.88 ms Minimum times are based on maximum fNVMOP and maximum fNVMBUS Typical times are based on typical fNVMOP and typical fNVMBUS Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging Lowest-frequency max times are based on minimum fNVMOP and minimum fNVMBUS plus aging Affected by Pflash size Affected by EEPROM size MC9S12G Family Reference Manual Rev.1.28 1214 NXP Semiconductors Electrical Characteristics Table A-38. NVM Timing Characteristics) S12G96, S12GA96, S12G128, S12GA128 Num 1 2 3 4 5 6 Command fNVMOP cycle fNVMBUS cycle Symbol Min1 Typ2 Max3 Lfmax4 Unit 1 Erase Verify All Blocks5,6 0 35345 tRD1ALL 1.41 1.41 2.83 70.69 ms 2 Erase Verify Block (Pflash)5 0 33308 tRD1BLK_P 1.33 1.33 2.66 66.62 ms 3 (EEPROM)6 0 2536 tRD1BLK_D 0.1 0.1 0.2 5.07 ms 4 Erase Verify P-Flash Section 0 476 tRD1SEC 19.04 19.04 38.08 952 ms 5 Read Once 0 445 tRDONCE 17.8 17.8 17.8 445 s 6 Program P-Flash (4 Word) 164 2925 tPGM_4 0.27 0.28 0.63 11.91 ms 7 Program Once 164 2888 tPGMONCE 0.27 0.28 0.28 3.09 ms 8 Erase All Blocks5,6 100066 35681 tERSALL 96.73 101.49 102.92 196.44 ms 9 Erase Flash Block (Pflash)5 100060 33541 tERSBLK_P 96.64 101.4 102.74 192.16 ms 10 Erase Flash Block (EEPROM)6 100060 2832 tERSBLK_D 95.41 100.17 100.29 130.74 ms 11 Erase P-Flash Sector 20015 865 tERSPG 19.1 20.05 20.08 26.75 ms 12 Unsecure Flash 100066 35759 tUNSECU 96.73 101.5 102.93 196.6 ms 13 Verify Backdoor Access Key 0 481 tVFYKEY 19.24 19.24 19.24 481 s 14 Set User Margin Level 0 399 tMLOADU 15.96 15.96 15.96 399 s 15 Set Factory Margin Level 0 408 tMLOADF 16.32 16.32 16.32 408 s 0.02 0.02 0.04 1.09 ms Erase Verify Block 16 Erase Verify EEPROM Section 0 546 tDRD1SEC 17 Program EEPROM (1 Word) 68 1565 tDPGM_1 0.13 0.13 0.32 6.35 ms 18 Program EEPROM (2 Word) 136 2512 tDPGM_2 0.23 0.24 0.54 10.22 ms 19 Program EEPROM (3 Word) 204 3459 tDPGM_3 0.33 0.34 0.76 14.09 ms 20 Program EEPROM (4 Word) 272 4406 tDPGM_4 0.44 0.45 0.98 17.96 ms 21 Erase EEPROM Sector 5015 753 tDERSPG 4.81 5.05 20.57 37.88 ms Minimum times are based on maximum fNVMOP and maximum fNVMBUS Typical times are based on typical fNVMOP and typical fNVMBUS Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging Lowest-frequency max times are based on minimum fNVMOP and minimum fNVMBUS plus aging Affected by Pflash size Affected by EEPROM size MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1215 Electrical Characteristics Table A-39. NVM Timing Characteristics) S12G192, S12GA192, S12G240, S12GA240 Num 1 2 3 4 5 6 Command fNVMOP cycle fNVMBUS cycle Symbol Min1 Typ2 Max3 Lfmax4 Unit 1 Erase Verify All Blocks5,6 0 64361 tRD1ALL 2.57 2.57 5.15 128.72 ms 2 Erase Verify Block (Pflash)5 0 62128 tRD1BLK_P 2.49 2.49 4.97 124.26 ms 3 (EEPROM)6 0 2586 tRD1BLK_D 0.1 0.1 0.21 5.17 ms 4 Erase Verify P-Flash Section 0 606 tRD1SEC 0.02 02 0.05 1.21 ms 5 Read Once 0 516 tRDONCE 20.64 20.64 20.64 516 s 6 Program P-Flash (4 Word) 164 3014 tPGM_4 0.28 0.28 0.65 12.26 ms 7 Program Once 164 2960 tPGMONCE 0.27 0.28 0.28 3.17 ms 8 Erase All Blocks5,6 200126 65067 tERSALL 193.2 202.73 205.33 380.29 ms 9 Erase Flash Block (Pflash)5 200120 62651 tERSBLK_P 193.1 202.63 205.13 375.45 ms 10 Erase Flash Block (EEPROM)6 100060 2871 tERSBLK_D 95.41 100.17 100.29 130.82 ms 11 Erase P-Flash Sector 20015 962 tERSPG 19.1 20.05 20.09 26.94 ms 12 Unsecure Flash 200126 65145 tUNSECU 193.2 202.73 205.34 380.45 ms 13 Verify Backdoor Access Key 0 549 tVFYKEY 21.96 21.96 21.96 549 s 14 Set User Margin Level 0 426 tMLOADU 17.04 17.04 17.04 426 s 15 Set Factory Margin Level 0 435 tMLOADF 17.4 17.4 17.4 435 s 0.02 0.02 0.05 1.16 ms Erase Verify Block 16 Erase Verify EEPROM Section 0 582 tDRD1SEC 17 Program EEPROM (1 Word) 68 1585 tDPGM_1 0.13 0.13 0.32 6.43 ms 18 Program EEPROM (2 Word) 136 2532 tDPGM_2 0.23 0.24 0.54 10.3 ms 19 Program EEPROM (3 Word) 204 3479 tDPGM_3 0.33 0.34 0.76 14.17 ms 20 Program EEPROM (4 Word) 272 4426 tDPGM_4 0.44 0.45 0.98 18.04 ms 21 Erase EEPROM Sector 5015 777 tDERSPG 4.81 5.05 20.59 38.28 ms Minimum times are based on maximum fNVMOP and maximum fNVMBUS Typical times are based on typical fNVMOP and typical fNVMBUS Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging Lowest-frequency max times are based on minimum fNVMOP and minimum fNVMBUS plus aging Affected by Pflash size Affected by EEPROM size A.7.2 NVM Reliability Parameters The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The data retention and program/erase cycling failure rates are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. MC9S12G Family Reference Manual Rev.1.28 1216 NXP Semiconductors Electrical Characteristics Table A-40. NVM Reliability Characteristics Conditions are shown in Table A-4 unless otherwise noted NUM C Rating Symbol Min Typ Max Unit tNVMRET 20 1002 — Years Program Flash Arrays 1 C Data retention at an average junction temperature of TJavg = 85C1 after up to 10,000 program/erase cycles 2a C Program Flash number of program/erase cycles (-40C  Tj  150C nFLPE 10K 100K3 — Cycles 2b C Program Flash number of program/erase cycles (150C  Tj  160C nFLPE 1K 100K3 — Cycles EEPROM Array 3 C Data retention at an average junction temperature of TJavg = 85C1 after up to 100,000 program/erase cycles tNVMRET 5 1002 — Years 4 C Data retention at an average junction temperature of TJavg = 85C1 after up to 10,000 program/erase cycles tNVMRET 10 1002 — Years 5 C Data retention at an average junction temperature of TJavg = 85C1 after less than 100 program/erase cycles tNVMRET 20 1002 — Years 6a C EEPROM number of program/erase cycles (-40C  Tj  150C nFLPE 100K 500K3 — Cycles 10K 500K3 — Cycles 6b C EEPROM number of program/erase cycles (150C  Tj  160C nFLPE 1 TJavg does not exceed 85C in a typical temperature profile over the lifetime of a consumer, industrial or automotive application. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how NXP defines Typical Data Retention, please refer to Engineering Bulletin EB618 3 Spec table quotes typical endurance evaluated at 25C for this product family. For additional information on how NXP defines Typical Endurance, please refer to Engineering Bulletin EB619. 2 A.8 A.8.1 Phase Locked Loop Jitter Definitions With each transition of the feedback clock, the deviation from the reference clock is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the VCOCLK frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4. MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1217 Electrical Characteristics 1 0 2 3 N-1 N tmin1 tnom tmax1 tminN tmaxN Figure A-4. Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as: t N t N   max min J  N  = max  1 – ----------------------- , 1 – -----------------------  Nt Nt  nom nom  For N < 100, the following equation is a good fit for the maximum jitter: j 1 J  N  = -------N J(N) 1 5 10 20 N Figure A-5. Maximum Bus Clock Jitter Approximation MC9S12G Family Reference Manual Rev.1.28 1218 NXP Semiconductors Electrical Characteristics NOTE On timers and serial modules a prescaler will eliminate the effect of the jitter to a large extent. A.8.2 Electrical Characteristics for the PLL Table A-41. PLL Characteristics Conditions are shown in Table A-16 unless otherwise noted Num C Rating Symbol Min fVCORST Typ Max Unit 8 25 MHz 50 MHz 1 D VCO frequency during system reset 2 C VCO locking range fVCO 32 3 C Reference Clock fREF 1 4 D Lock Detection Lock| 0 1.5 %1 5 D Un-Lock Detection unl| 0.5 2.5 %1 6 C Time to lock tlock 150 + 256/fREF s 7 C Jitter fit parameter 12 IRC as reference clock source jirc 1.4 % 8 C Jitter fit parameter 13 XOSCLCP as reference clock source jext 1.0 % MHz 1 % deviation from target frequency fREF = 1MHz (IRC), fBUS = 25MHz equivalent fPLL = 50MHz, CPMUSYNR=0x58, CPMUREFDIV=0x00, CPMUPOSTDIV=0x00 3 f REF = 4MHz (XOSCLCP), fBUS = 24MHz equivalent fPLL = 48MHz, CPMUSYNR=0x05, CPMUREFDIV=0x40, CPMUPOSTDIV=0x00 2 A.9 Electrical Characteristics for the IRC1M Table A-42. IRC1M Characteristics (Junction Temperature From –40C To +150C, all packages) Conditions are: Temperature option C, V, or M (see Table A-4) Num C 1 Rating P Internal Reference Frequency, factory trimmed Symbol Min Typ Max Unit fIRC1M_TRIM 0.987 1 1.013 MHz Table A-43. IRC1M Characteristics (Junction Temperature From –40C To +150C, KGD) Conditions are: Temperature option C, V, or M (see Table A-4) Num C 1 Rating P Internal Reference Frequency, factory trimmed Symbol Min Typ Max Unit fIRC1M_TRIM 0.980 1 1.020 MHz MC9S12G Family Reference Manual Rev.1.28 NXP Semiconductors 1219 Electrical Characteristics Table A-44. IRC1M Characteristics (Junction Temperature From +150C To +160C, all packages) Conditions are: Temperature option W (see Table A-4) Num C 1 Rating M Internal Reference Frequency, factory trimmed Symbol Min Typ Max Unit fIRC1M_TRIM 0.987 1 1.013 MHz MC9S12G Family Reference Manual Rev.1.28 1220 NXP Semiconductors Electrical Characteristics A.10 Electrical Characteristics for the Oscillator (XOSCLCP) Table A-45. XOSCLCP Characteristics (Junction Temperature From –40C To +150C) Conditions are shown in Table A-4 unless otherwise noted Num C Min Typ Max Unit 16 MHz C Nominal crystal or resonator frequency fOSC 4.0 2 P Startup Current iOSC 100 3a C Oscillator start-up time (4MHz)1 tUPOSC — 2 10 ms 3b C Oscillator start-up time (8MHz) 1 tUPOSC — 1.6 8 ms 3c C Oscillator start-up time (16MHz)1 tUPOSC — 1 5 ms 4 P Clock Monitor Failure Assert Frequency fCMFA 200 450 1200 KHz 5 D Input Capacitance (EXTAL, XTAL pins) CIN 7 8 2 Symbol 1 6 1 Rating C EXTAL Pin Input Hysteresis VHYS,EXTA EXTAL Pin oscillation amplitude (loop controlled Pierce) C all mask sets except for 2N75C and 2N55V A 7 pF — 120 — mV VPP,EXTAL — 1.0 — V EXTAL Pin oscillation required amplitude2 (loop controlled Pierce) D VPP,EXTAL all mask sets except for 2N75C and 2N55V 0.8 — 1.5 V L These values apply for carefully designed PCB layouts with capacitors that match the crystal/resonator requirements. Needs to be measured at room temperature on the application board using a probe with very low (

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