S9S12ZVL32F0MLC

MC9S12ZVL Family Reference Manual and Datasheet S12 MagniV Microcontrollers Rev. 2.48 April 3, 2019 MC9S12ZVLRM nxp.com The MC9S12ZVL family of microcontrollers is targeted at use in safety relevant systems and has been developed using an ISO26262 compliant development system under the NXP Safe Assure program. For more details of how to use the device in safety relevant systems refer to the MC9S12ZVL Safety Manual at : http://nxp.com/S12ZVL To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://nxp.com A full list of family members and options is included in the device overview section. This document contains information for all constituent modules, with the exception of the S12Z CPU. For S12ZCPU information please refer to the CPU S12Z Reference Manual. NOTE This reference manual documents the entire S12ZVL-Family. It contains a superset of features within the family. Some module versions differ from one part to another within the family. Section 1.2.1 MC9S12ZVL-Family Member Comparison provides support to access the correct information for a particular part within the family. MC9S12ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 2 Revision History Date Revision Level Description 0.14 • • • • • • • • Updated Chapter 1, “Device Overview MC9S12ZVL-Family” Updated Chapter 10, “Analog-to-Digital Converter (ADC12B_LBA)” Updated Chapter 18, “Serial Communication Interface (S12SCIV6)” Updated Chapter 19, “Serial Peripheral Interface (S12SPIV5)” Updated Chapter 21, “LIN Physical Layer (S12LINPHYV2)”” Updated Appendix A, “MCU Electrical Specifications” Updated Appendix O, “Detailed Register Address Map” Updated Appendix N, “Ordering Information” 0.15 • • • • • • • Updated Chapter 1, “Device Overview MC9S12ZVL-Family” Updated Chapter 8, “ECC Generation Module (SRAM_ECCV2)” Updated Chapter 10, “Analog-to-Digital Converter (ADC12B_LBA)” Updated MC9S12ZVL” Updated Chapter 19, “Serial Peripheral Interface (S12SPIV5)” Updated Chapter 21, “LIN Physical Layer (S12LINPHYV2)”” Updated Appendix A, “MCU Electrical Specifications” 17 September 2014 1.00 • • • • • • • • Updated Chapter 1, “Device Overview MC9S12ZVL-Family” Updated Chapter 5, “Background Debug Controller (S12ZBDCV2)” Updated Chapter 7, “S12Z DebugLite (S12ZDBGV3)” Updated Chapter 22, “Flash Module (S12ZFTMRZ)” Updated Chapter 21, “LIN Physical Layer (S12LINPHYV2)”” Updated Appendix A, “MCU Electrical Specifications” Updated Appendix O, “Detailed Register Address Map Updated Appendix M, “Package Information 16 October 2014 1.01 • Updated Appendix A, “MCU Electrical Specifications” 2.00 Initial version including ZVL128 • Updated Chapter 1, “Device Overview MC9S12ZVL-Family” • Updated Chapter 2, “Port Integration Module (S12ZVLPIMV2)” • Added Chapter 3, “5V Analog Comparator (ACMPV2)” • Updated Chapter 7, “S12Z DebugLite (S12ZDBGV3)” • Updated Chapter 10, “Analog-to-Digital Converter (ADC12B_LBA)” • Added Chapter 11, “Digital Analog Converter (DAC_8B5V_V2)” • Added Chapter 12, “Programmable Gain Amplifier (PGAV1)” • Added Chapter 13, “Scalable Controller Area Network (S12MSCANV2)” • Updated Chapter 22, “Flash Module (S12ZFTMRZ)” • Updated Appendix O, “Detailed Register Address Map” 28 September 2013 28 November 2013 11 December 2014 05 May 2015 2.00 Draft D • Updated Chapter 1, “Device Overview MC9S12ZVL-Family” • Added new version of Chapter 8, “ECC Generation Module (SRAM_ECCV2)” • Added new version of Chapter 9, “S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)” • Added new version of Chapter 12, “Programmable Gain Amplifier (PGAV1) • added VL128 specific parameter (3.3V VDDX mode, Supply Current Table) to Appendix A, “MCU Electrical Specifications MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 3 Revision History Revision Level Description 13 May 2015 2.00 Draft E • Added new version of Chapter 12, “Programmable Gain Amplifier (PGAV1) • Added new version of Chapter 11, “Digital Analog Converter (DAC_8B5V_V2) • added missing modules DAC, PGA, ACMP, PWM1 to Appendix O, “Detailed Register Address Map • update voltage range inside Appendix I, “ACMP Electrical Specifications and Appendix G, “DAC_8B5V Electrical Specifications 05 June 2015 2.00 Draft F • Added new version of Chapter 1, “Device Overview MC9S12ZVL-Family” • Added new version of Appendix A, “MCU Electrical Specifications 27 October 2015 2.00 Draft G • Added new version v0.4 of Appendix A, “MCU Electrical Specifications” • correct Order Information 25 February 2016 2.00Draft I 10 May 2016 2.00 • Added version 0.80 of Appendix A, “MCU Electrical Specifications • changed to Chapter 10, “Analog-to-Digital Converter (ADC12B_LBA) version V3 08 August 2017 2.10 • Added version 0.90 of Appendix A, “MCU Electrical Specifications • Added version 2.00 of Chapter 1, “Device Overview MC9S12ZVL-Family 12 September 2017 2.20 • Added version 1.0 of Appendix A, “MCU Electrical Specifications 10 October 2017 2.30 • Added version 1.1 of Appendix A, “MCU Electrical Specifications 19 October 2017 2.40 • Added version 1.2 of Appendix A, “MCU Electrical Specifications 24 October 2017 2.41 • Added version 1.21 of Appendix A, “MCU Electrical Specifications 28-March 2018 2.42 • Added version 2.1 of Chapter 1, “Device Overview MC9S12ZVL-Family • Added version 1.22 of Appendix A, “MCU Electrical Specifications 29-March 2018 2.43 • Added version 1.23 of Appendix A, “MCU Electrical Specifications 9-Jul 2018 2.44 • Added version 1.24 of Appendix A, “MCU Electrical Specifications • Added version 2.11 of Chapter 2, “Port Integration Module (S12ZVLPIMV2) 23-Aug 2018 2.45 • Added version 1.25 of Appendix A, “MCU Electrical Specifications 12 Nov 2018 2.46 • Added version 1.26 of Appendix A, “MCU Electrical Specifications 19 Nov 2018 2.47 • Added version 1.27 of Appendix A, “MCU Electrical Specifications • Added version 2.12 of Chapter 2, “Port Integration Module (S12ZVLPIMV2) 3 Apr 2019 2.48 • Added version 1.29 of Appendix A, “MCU Electrical Specifications • Added version 3.04 of Chapter 16, “Timer Module (TIM16B2CV3) • Added version 3.04 of Chapter 15, “Timer Module (TIM16B6CV3) Date • change to NXP style • Added new version of Appendix A, “MCU Electrical Specifications MC912ZVL Family Reference Manual, Rev. 2.48 4 NXP Semiconductors NXP Semiconductor reserves the right to make changes without further notice to any products herein. NXP Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does NXP Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in NXP Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. NXP Semiconductor does not convey any license under its patent rights nor the rights of others. NXP Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the NXP Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use NXP Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold NXP Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that NXP Semiconductor was negligent regarding the design or manufacture of the part. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 5 MC912ZVL Family Reference Manual, Rev. 2.48 6 NXP Semiconductors Chapter 1 Device Overview MC9S12ZVL-Family 1.1 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.2.1 MC9S12ZVL-Family Member Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.3 Chip-Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4.1 S12Z Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4.2 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4.3 Clocks, Reset & Power Management Unit (CPMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4.4 Main External Oscillator (XOSCLCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.4.5 Timer (TIM0 and TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.4.6 Pulse Width Modulation Module (PWM0 and PMW1) . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4.7 Inter-IC Module (IIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4.8 LIN physical layer transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4.9 Serial Communication Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4.10 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.4.11 Multi-Scalable Controller Area Network (MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.4.12 Analog-to-Digital Converter Module (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.4.13 Digital-to-Analog Converter Module (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.4.14 Analog Comparator Module (ACMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.4.15 Programmable Gain Amplifier (PGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.4.16 Supply Voltage Sensor (BATS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.4.17 On-Chip Voltage Regulator system (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.6 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.6.1 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.7 Signal Description and Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.7.1 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.7.2 Detailed External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.7.3 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.8 Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.9 Internal Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1.9.1 ADC Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1.9.2 BDC Clock Source Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1.9.3 FTMRZ Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1.9.4 CPMU Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1.9.5 LINPHY Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1.9.6 MC9S12ZVLA analog module Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1.9.7 PWM channel mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 1.10 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 1.10.1 3.3V - 5V VDDX behavior on MC9S12ZVL(A)128/96/64 devices . . . . . . . . . . . . . . . . 53 1.10.2 Chip Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 1.10.3 Debugging Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 1.10.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 7 1.11 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.11.2 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.11.3 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 1.11.4 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 1.11.5 Reprogramming the Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 1.11.6 Complete Memory Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 1.12 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 1.12.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 1.12.2 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 1.12.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.13 Module device level dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.13.1 COP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.13.2 BDC Command Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.13.3 Flash IFR Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 1.14 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 1.14.1 ADC Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 1.14.2 SCI Baud Rate Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.14.3 Voltage Domain Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Chapter 2 Port Integration Module (S12ZVLPIMV2) 2.1 2.2 2.3 2.4 2.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.3.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.3.2 PIM Registers 0x0200-0x020F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 2.3.3 PIM Generic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.3.4 PIM Generic Register Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.4.3 Pin I/O Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 2.4.5 High-Voltage Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2.5.1 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2.5.2 SCI Baud Rate Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2.5.3 Over-Current Protection on EVDD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2.5.4 Over-Current Protection on PP[5,3,1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2.5.5 Open Input Detection on HVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 MC912ZVL Family Reference Manual, Rev. 2.48 8 NXP Semiconductors Chapter 3 5V Analog Comparator (ACMPV2) 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 3.4.1 Internal Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 3.6.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 3.6.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Chapter 4 Memory Mapping Control (S12ZMMCV1) 4.1 4.2 4.3 4.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.4.1 Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.4.2 Illegal Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.4.3 Uncorrectable ECC Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Chapter 5 Background Debug Controller (S12ZBDCV2) 5.1 5.2 5.3 5.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 9 5.5 5.4.2 Enabling BDC And Entering Active BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.4.3 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.4.4 BDC Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.4.5 BDC Access Of Internal Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 5.4.6 BDC Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.4.7 Serial Interface Hardware Handshake (ACK Pulse) Protocol . . . . . . . . . . . . . . . . . . . . 161 5.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.4.9 Hardware Handshake Disabled (ACK Pulse Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.4.10 Single Stepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.4.11 Serial Communication Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 5.5.1 Clock Frequency Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Chapter 6 Interrupt (S12ZINTV0) 6.1 6.2 6.3 6.4 6.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.4.1 S12Z Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.4.3 Priority Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.4.4 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.4.5 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.4.6 Interrupt Vector Table Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 6.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 6.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 6.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Chapter 7 S12Z DebugLite (S12ZDBGV3) 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 7.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 7.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 7.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 MC912ZVL Family Reference Manual, Rev. 2.48 10 NXP Semiconductors 7.2 7.3 7.4 7.5 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 7.2.1 External Event Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 7.4.1 DBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 7.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 7.4.3 Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 7.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 7.4.5 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 7.5.1 Avoiding Unintended Breakpoint Re-triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 7.5.2 Breakpoints from other S12Z sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Chapter 8 ECC Generation Module (SRAM_ECCV2) 8.1 8.2 8.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 8.2.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 8.2.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 8.3.1 Aligned Memory Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 8.3.2 Non-aligned Memory Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 8.3.3 Memory Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 8.3.4 Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 8.3.5 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 8.3.6 ECC Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 8.3.7 ECC Debug Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Chapter 9 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) 9.1 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 9.1.3 S12CPMU_UHV Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 9.2.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 9.2.2 EXTAL and XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 9.2.3 VSUP — Regulator Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 9.2.4 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 9.2.5 VDDX, VSSX — Pad Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 9.2.6 BCTL — Base Control Pin for external PNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 11 9.3 9.4 9.5 9.6 9.7 9.2.7 VSS — Core Logic Ground Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 9.2.8 VDD — Internal Regulator Output Supply (Core Logic) . . . . . . . . . . . . . . . . . . . . . . . 229 9.2.9 VDDF — Internal Regulator Output Supply (NVM Logic) . . . . . . . . . . . . . . . . . . . . . 229 9.2.10 API_EXTCLK — API external clock output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 9.2.11 TEMPSENSE — Internal Temperature Sensor Output Voltage . . . . . . . . . . . . . . . . . . 229 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 9.4.1 Phase Locked Loop with Internal Filter (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 9.4.2 Startup from Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 9.4.3 Stop Mode using PLLCLK as source of the Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . 274 9.4.4 Full Stop Mode using Oscillator Clock as source of the Bus Clock . . . . . . . . . . . . . . . 274 9.4.5 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 9.4.6 System Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 9.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 9.5.2 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 9.5.3 Oscillator Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 9.5.4 PLL Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 9.5.5 Computer Operating Properly Watchdog (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 280 9.5.6 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 9.5.7 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 9.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 9.7.1 General Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 9.7.2 Application information for COP and API usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 9.7.3 Application Information for PLL and Oscillator Startup . . . . . . . . . . . . . . . . . . . . . . . . 284 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA) 10.1 Differences ADC12B_LBA V1 vs V2 vs V3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 10.3 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 10.3.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 10.3.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 10.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 10.4.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 10.5 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 10.5.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 10.5.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 10.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 10.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 MC912ZVL Family Reference Manual, Rev. 2.48 12 NXP Semiconductors 10.6.2 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 10.6.3 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 10.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 10.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 10.8.1 ADC Conversion Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 10.8.2 ADC Sequence Abort Done Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 10.8.3 ADC Error and Conversion Flow Control Issue Interrupt . . . . . . . . . . . . . . . . . . . . . . . 348 10.9 Use Cases and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 10.9.1 List Usage — CSL single buffer mode and RVL single buffer mode . . . . . . . . . . . . . . 349 10.9.2 List Usage — CSL single buffer mode and RVL double buffer mode . . . . . . . . . . . . . 349 10.9.3 List Usage — CSL double buffer mode and RVL double buffer mode . . . . . . . . . . . . . 350 10.9.4 List Usage — CSL double buffer mode and RVL single buffer mode . . . . . . . . . . . . . 350 10.9.5 List Usage — CSL double buffer mode and RVL double buffer mode . . . . . . . . . . . . . 351 10.9.6 RVL swapping in RVL double buffer mode and related registers ADCIMDRI and ADCEOLRI 351 10.9.7 Conversion flow control application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 10.9.8 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 10.9.9 Triggered Conversion — Single CSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 10.9.10Fully Timing Controlled Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Chapter 11 Digital Analog Converter (DAC_8B5V_V2) 11.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 11.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 11.2.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 11.2.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 11.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 11.3.1 DACU Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 11.3.2 AMP Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 11.3.3 AMPP Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 11.3.4 AMPM Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 11.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 11.4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 11.4.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 11.5.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 11.5.2 Mode “Off” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 11.5.3 Mode “Operational Amplifier” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 11.5.4 Mode “Internal DAC only“ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 11.5.5 Mode “Unbuffered DAC” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 11.5.6 Mode “Unbuffered DAC with Operational Amplifier” . . . . . . . . . . . . . . . . . . . . . . . . . 366 11.5.7 Mode “Buffered DAC” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 11.5.8 Analog output voltage calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 13 Chapter 12 Programmable Gain Amplifier (PGAV1) 12.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 12.2.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 12.2.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 12.2.4 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 12.2.5 Amplifier Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 12.2.6 PGA_OUT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 12.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 12.4.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 12.4.2 Offset Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 12.4.3 Application Example for differential voltage measurement . . . . . . . . . . . . . . . . . . . . . 377 Chapter 13 Scalable Controller Area Network (S12MSCANV2) 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 13.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 13.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 13.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 13.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 13.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 13.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 13.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 13.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 13.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 13.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 13.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 13.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 13.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 13.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 13.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 13.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 13.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 MC912ZVL Family Reference Manual, Rev. 2.48 14 NXP Semiconductors Chapter 14 Supply Voltage Sensor (BATSV3) 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 14.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 14.2.1 VSUP — Voltage Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 14.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 14.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 14.4.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 Chapter 15 Timer Module (TIM16B6CV3) 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 15.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 15.2.1 IOC5 - IOC0 — Input Capture and Output Compare Channel 5-0 . . . . . . . . . . . . . . . . 445 15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 15.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 15.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 15.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 15.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 15.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 15.6.1 Channel [5:0] Interrupt (C[5:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 15.6.2 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Chapter 16 Timer Module (TIM16B2CV3) 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 16.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 16.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 16.2.1 IOC1 - IOC0 — Input Capture and Output Compare Channel 1-0 . . . . . . . . . . . . . . . . 463 16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 15 16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 16.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 16.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 16.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 16.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 16.6.1 Channel [1:0] Interrupt (C[1:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 16.6.2 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 Chapter 17 Pulse-Width Modulator (S12PWM8B8CV2) 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 17.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 17.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 17.2.1 PWM7 - PWM0 — PWM Channel 7 - 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 17.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 17.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 17.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 17.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 17.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 17.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 17.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 Chapter 18 Serial Communication Interface (S12SCIV6) 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 18.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 18.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 18.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 18.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 18.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 18.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 18.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 18.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 MC912ZVL Family Reference Manual, Rev. 2.48 16 NXP Semiconductors 18.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 18.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 18.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 18.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 18.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 18.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 18.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 18.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 18.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 18.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 18.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 18.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 Chapter 19 Serial Peripheral Interface (S12SPIV5) 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 19.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 19.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 19.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 19.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 19.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 19.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 19.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 19.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 19.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 19.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 19.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 19.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 19.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 19.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 19.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 19.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 Chapter 20 Inter-Integrated Circuit (IICV3) 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 20.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 20.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 20.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 17 20.3 20.4 20.5 20.6 20.7 20.2.1 IIC_SCL — Serial Clock Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 20.2.2 IIC_SDA — Serial Data Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 20.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 20.4.1 I-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 20.4.2 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 20.4.3 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 20.4.4 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 20.7.1 IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 Chapter 21 LIN Physical Layer (S12LINPHYV2) 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 21.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 21.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 21.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601 21.2.1 LIN — LIN Bus Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601 21.2.2 LGND — LIN Ground Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 21.2.3 VLINSUP — Positive Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 21.2.4 LPTxD — LIN Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 21.2.5 LPRxD — LIN Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 21.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 21.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 21.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 21.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 21.4.2 Slew Rate and LIN Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 21.4.3 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 21.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 21.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 21.5.1 Module Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 21.5.2 Interrupt handling in Interrupt Service Routine (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . 616 Chapter 22 Flash Module (S12ZFTMRZ) 22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 22.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 22.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 22.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 MC912ZVL Family Reference Manual, Rev. 2.48 18 NXP Semiconductors 22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 22.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 22.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 22.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 22.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 22.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 22.4.3 Flash Block Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 22.4.4 Internal NVM resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 22.4.5 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 22.4.6 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 653 22.4.7 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 22.4.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 22.4.9 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 22.4.10Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 22.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 22.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 22.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 672 22.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 672 22.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 Appendix A MCU Electrical Specifications A.1 General A.1.1 A.1.2 A.1.3 A.1.4 A.1.5 A.1.6 A.1.7 A.1.8 A.1.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 ADC Calibration Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 Appendix B CPMU Electrical Specifications (VREG, OSC, IRC, PLL) B.1 VREG Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 B.2 IRC and OSC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 B.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 B.3.1 Jitter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 Appendix C ADC Specifications C.1 ADC Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 19 C.1.1 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 C.1.2 ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 Appendix D LINPHY Electrical Specifications D.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 D.2 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 D.3 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 Appendix E NVM Electrical Parameters E.1 E.2 NVM Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 NVM Reliability Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 Appendix F BATS Electrical Specifications F.1 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 Appendix G DAC_8B5V Electrical Specifications G.1 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 Appendix H PGA Electrical Specifications H.1 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 Appendix I ACMP Electrical Specifications I.1 I.2 I.3 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 Appendix J PIM Electrical Specifications J.1 High-Voltage Inputs (HVI) Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730 Appendix K SPI Electrical Specifications K.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 K.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 MC912ZVL Family Reference Manual, Rev. 2.48 20 NXP Semiconductors Appendix L MSCAN Electrical Specifications L.1 MSCAN Wake-up Pulse Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 Appendix M Package Information M.1 48 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 M.2 32 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 M.3 32 QFN, MC9S12ZVLS device only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 Appendix N Ordering Information Appendix O Detailed Register Address Map O.1 O.2 O.3 O.4 O.5 O.6 O.7 O.8 O.9 O.10 O.11 O.12 O.13 O.14 O.15 O.16 O.17 O.18 O.19 O.20 O.21 O.22 O.23 0x0000–0x0003 Part ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 0x0010–0x001F S12ZINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 0x0070-0x00FF S12ZMMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 0x0100-0x017F S12ZDBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 0x0200-0x037F PIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756 0x0380-0x039F FTMRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 0x03C0-0x03CF SRAM_ECC_32D7P. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 0x0400-0x042F TIM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 0x0480-x04AF PWM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 0x0500-x052F PWM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 0x05C0-0x05FF TIM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 0x0600-0x063F ADC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 0x0680-0x0687 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 0x0690-0x0697 ACMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 0x06C0-0x06DF CPMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 0x06F0-0x06F7 BATS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 0x0700-0x0707 SCI0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 0x0710-0x0717 SCI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 0x0780-0x0787 SPI0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 0x07C0-0x07C7 IIC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780 0x0800-0x083F CAN0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 0x0980-0x0987 LINPHY0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 0x0B40-0x0B47 PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 21 MC912ZVL Family Reference Manual, Rev. 2.48 22 NXP Semiconductors Chapter 1 Device Overview MC9S12ZVL-Family Table 1-1. Revision History Version Number Revision Date 1.0 28. May 2013 Description of Changes • added feedback from shared review • changed IFR mapping table conditional text to make the ADC reference conversion visible for the customer 1.1 26. Aug.2013 • added feedback from shared review 1.2 29. Aug.2013 • update table 1-12, replaced for SCI0/1 EX with RX 1.3 19.Sep. 2013 • added chapter 1.13.2, “BDC Command Restriction” 1.4 2 April 2014 • fix findings from the shared review 1.5 5 Aug. 2014 1.6 24 Sep. 2014 • added the VL128 device 1.7 21 Oct. 2014 • added PWM channel muxing • added PGA - DAC - ACMP - ADC analog connections 1.8 03 Jun. 2015 • correct alignment in table 1-15 1.9 27 Oct. 2015 • correct table 1-3 2.0 08 Aug. 2017 • correct CTRL register name for PAD6-PAD9, table 1-6 • correct 32-pin QFN-EP availability, table 1-2 2.1 08 Mar 2018 • Added Ambient Temperature to Table 1-2 1.1 • fix typo PMW -> PWM Introduction The MC9S12ZVL-Family is an automotive 16-bit microcontroller family using the 180nm NVM + UHV technology that offers the capability to integrate 40V analog components. This family reuses many features from the existing S12 portfolio. The particular differentiating features of this family are the enhanced S12Z core and the integration of “high-voltage” analog modules, including the voltage regulator (VREG) and a Local Interconnect Network (LIN) physical layer. The MC9S12ZVL-Family includes error correction code (ECC) on RAM, FLASH and EEPROM for diagnostic or data storage, a fast analog-to-digital converter (ADC) and a frequency modulated phase locked loop (IPLL) that improves the EMC performance. The MC9S12ZVL-Family delivers an optimized solution with the integration of several key system components into a single device, optimizing system architecture and achieving significant space savings. The MC9S12ZVL-Family delivers all the advantages and efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of existing S12 families. The MC9S12ZVL-Family is available in 48-pin, 32-pin LQFP and 32-pin QFN-EP. In addition to the I/O ports available in each module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait modes. MC9S12ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 23 Device Overview MC9S12ZVL-Family The MC9S12ZVL-Family is a general-purpose family of devices suitable for a wide range of applications. The MC9S12ZVL-Family is targeted at generic automotive applications requiring LIN connectivity. Typical examples of these applications include switch panels and body endpoints for sensors. 1.2 Features This section describes the key features of the MC9S12ZVL-Family. 1.2.1 MC9S12ZVL-Family Member Comparison Table 1-2 provides a summary of main features within the MC9S12ZVL-Family. MC9S12ZVL64 MC9S12ZVLA64 MC9S12ZVL32 MC9S12ZVL16 MC9S12ZVL8 MC9S12ZVLS32 MC9S12ZVLS16 Flash memory (ECC) [KB] MC9S12ZVL96 MC9S12ZVLA96 Feature MC9S12ZVL128 MC9S12ZVLA128 Table 1-2. MC9S12ZVL-Family Comparison 128 96 64 32 16 8 32 16 EEPROM (ECC) [Byte] 2048 1024 RAM (ECC) [Byte] 8192 4096 max bus clock 128 1024 1024 128 512 1024 32 MHz 32 MHz 32 MHz 1 1 1 1 1 1 yes yes 3% / 2%(2) yes yes yes 3% no yes yes 3% no A A A Package 48-pin / 32-pin LQFP / 32-pin QFN-EP 48-pin / 32-pin LQFP 32-pin QFN-EP Operating Ambient Temperature (Ta) C=-40C to 85C V=-40C to 105C M=-40C to 125C W=-40 C to 150C(3) C=-40C to 85C V=-40C to 105C M=-40C to 125C W=-40 C to 150C C=-40C to 85C V=-40C to 105C M=-40C to 125C 10(3) / 6 10(3)(2) / 6(2) 10(3) / 6 - 6 - PWM 8 16 bit Channels 8 Channel (up to 4 16 bit) 8 Channel (up to 4 16 bit) DAC 1(4)(2) - - HVI LIN Physical layer capability(1) Vreg current - 70 mA (VDDX) - 170 mA ballast option (BCTL) - tolerance - 3.3V VDDX support, see also: 9.3.2.27, “Voltage Regulator Control Register (CPMUVREGCTL) ASIL SEooC target ADC channels -10-bit -12-bit MC912ZVL Family Reference Manual, Rev. 2.48 24 NXP Semiconductors Device Overview MC9S12ZVL-Family PGA5 MC9S12ZVLS16 MC9S12ZVLS32 MC9S12ZVL8 MC9S12ZVL16 MC9S12ZVL32 MC9S12ZVL64 MC9S12ZVLA64 Feature MC9S12ZVL96 MC9S12ZVLA96 MC9S12ZVL128 MC9S12ZVLA128 Table 1-2. MC9S12ZVL-Family Comparison 1(2) - - (2) - - 6 + 2 channel 6 + 2 channel 6 + 2 channel 2 2 2 SPI 1 1 1 IIC 1 1 1 MSCAN 1 - - 4 Byte 2 Byte 2 Byte yes no no 34(3) / 34(3) / 19 3(3) / 1 1 18 3 1 22(3) / 16 / 1 14 / 1 ACMP 1 Timer SCI 6 max SRAM_ECC access width Supported ADC option bits General purpose I/O - pin to support 25 mA driver strength to VSSX - pin to support 20 mA driver strength from VDDX (EVDD) Interrupt capable pins7 5V / 12V 1 2 3 4 5 6 7 19 3(3) / 1 1 22(3) / 16 / 1 total current capability for MCU and MCU - external loads (on same PCB - board) MC9S12ZVLA device only available in 48-pin packages only to internally feed the ACMP or bonded out in 48-LQFP only 5V operation mode supported one SCI routed to the LINPHY IRQ / XIRQ and KWx pins After power up, the MC9S12ZVL(A)128/96/64 devices starts in 3.3V VDDX mode. Then is possible to switch to the 5.0V VDDX behavior. For more details see the “Clock, Reset and Power Management Unit” section, 9.3.2.27, “Voltage Regulator Control Register (CPMUVREGCTL) 1.3 Chip-Level Features On-chip modules available within the family include the following features: • S12Z CPU core • 128, 96, 64, 32, 16 or 8 KB on-chip flash with ECC • 2048, 1024, 128 byte EEPROM with ECC • 8192, 4096, 1024 or 512 byte on-chip SRAM with ECC MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 25 Device Overview MC9S12ZVL-Family • • • • • • • • • • • • • • • • • • • • • • • • • 1.4 Phase locked loop (IPLL) frequency multiplier with internal filter 1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range 4-20 MHz amplitude controlled pierce oscillator Internal COP (watchdog) module analog-to-digital converter (ADC) with 10 -bit or 12 -bit resolution and up to 10 channels available on external pins and Vbg (bandgap) result reference PGA module with two input channels One 8-bit 5V digital-to-analog converter (DAC) One analog comparators (ACMP) with rail-to-rail inputs MSCAN (1 Mbit/s, CAN 2.0 A, B software compatible) module One serial peripheral interface (SPI) module One serial communication interface (SCI) module with interface to internal LIN physical layer transceiver (with RX connected to a timer channel for frequency calibration purposes, if desired) Up to one additional SCI (not connected to LIN physical layer) One on-chip LIN physical layer transceiver fully compliant with the LIN 2.2 standard 6-channel timer module (TIM0) with input capture/output compare 2-channel timer module (TIM1) with input capture/output compare Inter-IC (IIC) module 8-channel Pulse Width Modulation module (PWM) On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages Autonomous periodic interrupt (API), supports cyclic wakeup from Stop mode Pins to support 25 mA drive strength to VSSX Pin to support 20 mA drive strength from VDDX (EVDD) High Voltage Input (HVI) Supply voltage sense with low battery warning On-chip temperature sensor, temperature value can be measured with ADC or can generate a high temperature warning Up to 23 pins can be used as keyboard wake-up interrupt (KWI) Module Features The following sections provide more details of the integrated modules. 1.4.1 S12Z Central Processor Unit (CPU) The S12Z CPU is a revolutionary high-speed core, with code size and execution efficiencies over the S12X CPU. The S12Z CPU also provides a linear memory map eliminating the inconvenience and performance impact of page swapping. • Harvard Architecture - parallel data and code access • 3 stage pipeline MC912ZVL Family Reference Manual, Rev. 2.48 26 NXP Semiconductors Device Overview MC9S12ZVL-Family • • • • • • 32-Bit wide instruction and databus 32-Bit ALU 24-bit addressing (16 MByte linear address space) Instructions and Addressing modes optimized for C-Programming & Compiler — MAC unit 32bit += 32bit*32bit — Hardware divider — Single cycle multi-bit shifts (Barrel shifter) — Special instructions for fixed point math Unimplemented opcode traps Unprogrammed byte value (0xFF) defaults to SWI instruction 1.4.1.1 • Background debug controller (BDC) with single-wire interface — Non-intrusive memory access commands — Supports in-circuit programming of on-chip nonvolatile memory 1.4.1.2 • • • • Background Debug Controller (BDC) Debugger (DBG) Three comparators (A, B and D) — Comparator A compares the full address bus and full 32-bit data bus — Comparators B and D compare the full address bus only — Each comparator can be configured to monitor PC addresses or addresses of data accesses — Each comparator can select either read or write access cycles — Comparator matches can force state sequencer state transitions Three comparator modes — Simple address/data comparator match mode — Inside address range mode, Addmin  Address Addmax — Outside address range match mode, Address Addminor Address  Addmax State sequencer control — State transitions forced by comparator matches — State transitions forced by software write to TRIG — State transitions forced by an external event The following types of breakpoints — CPU breakpoint entering active BDM on breakpoint (BDM) — CPU breakpoint executing SWI on breakpoint (SWI) MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 27 Device Overview MC9S12ZVL-Family 1.4.2 Embedded Memory 1.4.2.1 • • Memory Access Integrity Illegal address detection ECC support on embedded NVM and system RAM 1.4.2.2 Flash On-chip flash memory on the MC9S12ZVL-Family • Up to 128 KB of program flash memory — Automated program and erase algorithm — Protection scheme to prevent accidental program or erase 1.4.2.3 • Up to 2048 bytes EEPROM — 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction and double fault detection — Erase sector size 4 bytes — Automated program and erase algorithm — User margin level setting for reads 1.4.2.4 • 1.4.3 • • • • • • EEPROM SRAM Up to 8 KB of general-purpose RAM with ECC — Single bit error correction and double bit error detection code based on 16-bit data words Clocks, Reset & Power Management Unit (CPMU) Real time interrupt (RTI) Clock monitor, supervising the correct function of the oscillator (CM) Computer operating properly (COP) watchdog — Configurable as window COP for enhanced failure detection — Can be initialized out of reset using option bits located in flash memory System reset generation Autonomous periodic interrupt (API) (combination with cyclic, watchdog) Low Power Operation — RUN mode is the main full performance operating mode with the entire device clocked. — WAIT mode when the internal CPU clock is switched off, so the CPU does not execute instructions. MC912ZVL Family Reference Manual, Rev. 2.48 28 NXP Semiconductors Device Overview MC9S12ZVL-Family — Pseudo STOP - system clocks are stopped but the oscillator the RTI, the COP, and API modules can be enabled — STOP - the oscillator is stopped in this mode, all clocks are switched off and all counters and dividers remain frozen, with the exception of the COP and API which can optionally run from ACLK. 1.4.3.1 • Phase-locked-loop clock frequency multiplier — No external components required — Reference divider and multiplier allow large variety of clock rates — Automatic bandwidth control mode for low-jitter operation — Automatic frequency lock detector — Configurable option to spread spectrum for reduced EMC radiation (frequency modulation) — Reference clock sources: – Internal 1 MHz RC oscillator (IRC) – External 4-16MHz crystal oscillator/resonator 1.4.3.2 • 1.4.4 • 1.4.5 • Internal Phase-Locked Loop (IPLL) Internal RC Oscillator (IRC) 1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range Main External Oscillator (XOSCLCP) Amplitude controlled Pierce oscillator using 4 MHz to 20 MHz crystal — Current gain control on amplitude output — Signal with low harmonic distortion — Low power — Good noise immunity — Eliminates need for external current limiting resistor — Transconductance sized for optimum start-up margin for typical crystals — Oscillator pins shared with GPIO functionality Timer (TIM0 and TIM1) two independent timer modules with own 16-bit free-running counter and with 8-bit precision prescaler — 6 x 16-bit channels Timer module (TIM0) for input capture or output compare — 2 x 16-bit channels Timer module (TIM1) for input capture or output compare MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 29 Device Overview MC9S12ZVL-Family 1.4.6 • 1.4.7 • • • • 1.4.8 • • • • • • • • • • 1.4.9 • • • • • • • • Pulse Width Modulation Module (PWM0 and PMW1) Up to eight channel x 8-bit or up to four channel x 16-bit pulse width modulator — Programmable period and duty cycle per channel — Center-aligned or left-aligned outputs — Programmable clock select logic with a wide range of frequencies Inter-IC Module (IIC) Multi-master operation Software programmable for one of 256 different serial clock frequencies Broadcast mode support 10-bit address support LIN physical layer transceiver Compliant with LIN Physical Layer 2.2 specification Compliant with the SAE J2602-2 LIN standard Standby mode with glitch-filtered wake-up Slew rate selection optimized for the baud rates: 10.4kBit/s, 20kBit/s and Fast Mode (up to 250kBit/s) Switchable 34k/330k pull-ups Current limitation for LIN Bus pin falling edge Over-current protection LIN TxD-dominant timeout feature monitoring the LPTxD signal Automatic transmitter shutdown in case of an over-current or TxD-dominant timeout Fulfills the OEM “Hardware Requirements for LIN (CAN and FlexRay) Interfaces in Automotive Applications” v1.3 Serial Communication Interface Module (SCI) Full-duplex or single-wire operation Standard mark/space non-return-to-zero (NRZ) format Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths Baud rate generator by a 16-bit divider from the bus clock Programmable character length Programmable polarity for transmitter and receiver Active edge receive wakeup Break detect and transmit collision detect supporting LIN MC912ZVL Family Reference Manual, Rev. 2.48 30 NXP Semiconductors Device Overview MC9S12ZVL-Family 1.4.10 • • • • • • Configurable 8- or 16-bit data size Full-duplex or single-wire bidirectional Double-buffered transmit and receive Master or slave mode MSB-first or LSB-first shifting Serial clock phase and polarity options 1.4.11 • • • • • • Digital-to-Analog Converter Module (DAC) 8-bit resolution Buffered analog output voltage usable Operational amplifier stand alone usable 1.4.14 • • • Analog-to-Digital Converter Module (ADC) 10-bit or 12-bit resolution Up to 10 external channels & 8 internal channels Left or right aligned result data Continuous conversion mode Programmers model with list based command and result storage architecture ADC directly writes results to RAM, preventing stall of further conversions Internal signals monitored with the ADC module — Vrh, Vrl, (Vrl+Vrh)/2, Vsup monitor, Vbg, TempSense External pins can also be used as digital I/O 1.4.13 • • • Multi-Scalable Controller Area Network (MSCAN) Implementation of CAN protocol - Version 2.0A/B Five receive buffers with FIFO storage scheme Three transmit buffers with internal prioritization using “local priority” concept Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four 16-bit filters, or eight 8-bit filters Programmable wake-up functionality with integrated low-pass filter 1.4.12 • • • • • • • Serial Peripheral Interface Module (SPI) Analog Comparator Module (ACMP) 0V to VDDA supply rail-to-rail inputs Low offset Up to 4 inputs selectable as inverting and non-inverting comparator inputs: MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 31 Device Overview MC9S12ZVL-Family • • • • • — 2 low-impedance inputs with selectable low pass filter for external pins — 2 high-impedance inputs with fixed filter for SoC-internal signals Selectable hysteresis Selectable interrupt on rising edge, falling edge, or rising and falling edges of comparator output Option to output comparator signal on an external pin with selectable polarity Support for triggering timer input capture events Operational over supply range from 3.3V-5% to 5V+10% 1.4.15 • • • Amplification of analog input signal with selectable gain of 10x, 20x, 40x, 80x and offset compensation Amplifier output connected to ADC Amplifier signal reference voltage selectable from DAC, VDDA/2 or input pin 1.4.16 • • • • Supply Voltage Sensor (BATS) Monitoring of supply (VSUP) voltage Internal ADC interface from an internal resistive divider Generation of low or high voltage interrupts 1.4.17 • Programmable Gain Amplifier (PGA) On-Chip Voltage Regulator system (VREG) Voltage regulator — Linear voltage regulator directly supplied by VSUP — Supports 3.3V or 5V VDDX — Low-voltage detect on VSUP — Power-on reset (POR) — Low-voltage reset (LVR) for VDDX domain — External ballast device support to extend current capability and reduce internal power dissipation — Capable of supplying both the MCU internally plus external components — Over-temperature interrupt Internal voltage regulator — Linear voltage regulator with bandgap reference — Low-voltage detect on VDDA — Power-on reset (POR) circuit — Low-voltage reset for VDD domain MC912ZVL Family Reference Manual, Rev. 2.48 32 NXP Semiconductors Device Overview MC9S12ZVL-Family 1.5 Block Diagram VRH VRL VDDA VSSA ADC 10-bit / 12-bit Analog-Digital Converter Flash with ECC up to 128K bytes AN[9:0] ACMP analog Comparator RAM with ECC up to 8K bytes ACMP_0 ACMP_1 ACMPO DAC S12Z CPU PGA Programmable Gain Amplifier INT Interrupt Module EXTAL Low Power Pierce XTAL Oscillator PLL with Frequency Modulation option RESET TEST Reset Generation and Test Entry VSUP VSS VDDX VSSX[2:1] BCTL Clock Monitor COP Watchdog Real Time Interrupt Auton. Periodic Int. SDA SCL PP[7:0]/ KWP[7:0] PJ[1:0] PS[3:0]/ KWS[3:0] PT[7:0] Internal RC Oscillator SPI0 Synchronous Serial IF Voltage Regulator (Nominal 12V) MISO0 MOSI0 SCK0 SS0 TIM0 IOC0[5:0] 16-bit 6-Channel Timer High Voltage Input PTL IIC0 Inter IC IF BATS Voltage Supply Monitor PL[0]/ KWL[0] PWM[7:0] 8-bit 8-Channel Pulse Width Modulator PTP PE1 PTE CPMU PE0 PWM0 / PWM1 PTJ DBG Debug Module PGA_IN0 PGA_IN1 PGA_REF1 PTS BDC Background Debug Controller PAD[9:0]/ KWAD[9:0] PTT BKGD AMPP AMPM AMP 8 bit DAC PTAD EEPROM with ECC up to 2K bytes TIM1 HVI0 IOC1[1:0] 16-bit 2-Channel Timer CAN0 RXCAN0 TXCAN0 SCI1 RXD1 TXD1 Asynchronous Serial IF SCI0 LINPHY0 RXD0 TXD0 LIN LGND LIN LGND Asynchronous Serial IF Block Diagram shows the maximum configuration Not all pins or all peripherals are available on all devices and packages. Rerouting options are not shown. Figure 1-1. MC9S12ZVL-Family Block Diagram MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 33 Device Overview MC9S12ZVL-Family 1.6 Device Memory Map Table 1-3 shows the device register memory map. All modules that can be instantiated more than once on S12 devices are listed with an index number, even if they are only instantiated once on this device family. Table 1-3. Module Register Address Ranges Address Module Size (Bytes) 0x0000–0x0003 Part ID Register Section 1.6.1, “Part ID Assignments 4 0x0004–0x000F Reserved 12 0x0010–0x001F INT 16 0x0020–0x006F Reserved 80 0x0070–0x008F MMC 32 0x0090–0x00FF MMC Reserved 112 0x0100–0x017F DBG 128 0x0180–0x01FF Reserved 128 0x0200–0x037F PIM 384 0x0380–0x039F FTMRZ 32 0x03A0–0x03BF Reserved 32 0x03C0–0x03CF RAM ECC 16 0x03D0–0x03FF Reserved 48 0x0400–0x042F TIM1 48 0x0430–0x047F Reserved 80 0x0480–0x04AF PWM0 48 0x04B0–0x04FF Reserved1 80 0x0500–0x052F PWM1 48 0x0530–0x05BF Reserved1 144 0x05C0–0x05EF TIM0 48 0x05F0–0x05FF Reserved 16 0x0600–0x063F ADC 64 0x0640–0x067F Reserved 64 0x0680–0x0687 DAC 8 0x0688–0x068F Reserved 8 0x0690–0x0697 ACMP 8 0x0698–0x06BF Reserved 40 0x06C0–0x06DF CPMU 32 0x06E0–0x06EF Reserved 16 0x06F0–0x06F7 BATS 8 0x06F8–0x06FF Reserved 8 MC912ZVL Family Reference Manual, Rev. 2.48 34 NXP Semiconductors Device Overview MC9S12ZVL-Family Table 1-3. Module Register Address Ranges 1 Address Module Size (Bytes) 0x0700–0x0707 SCI0 8 0x0708–0x070F Reserved 8 0x0710–0x0717 SCI1 8 0x0718–0x077F Reserved 104 0x0780–0x0787 SPI0 8 0x0788–0x07BF Reserved 56 0x07C0–0x07C7 IIC0 8 0x07C8–0x07FF Reserved 56 0x0800–0x083F CAN0 64 0x0840–0x097F Reserved 320 0x0980–0x0987 LINPHY0 8 0x0988–0x0B3F Reserved 440 0x0B40–0x0B47 PGA 8 0x0B48–0x0FFF Reserved 1208 Reading from the first 16 locations in this range returns undefined data NOTE Reserved register space shown above is not allocated to any module. This register space is reserved for future use. Writing to these locations has no effect. Read access to these locations returns zero. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 35 Device Overview MC9S12ZVL-Family Register Space 4 KB 0x00_0000 0x00_1000 RAM max. 1 MByte - 4 KByte 0x10_0000 EEPROM max. 1 MByte - 48 KByte Reserved 512 Byte 0x1F_4000 Reserved (read only) 6 KByte 0x1F_8000 NVM IFR 256 Byte 0x1F_C000 0x20_0000 Unmapped 6 MByte 0x80_0000 Program NVM max. 8 MByte Unmapped address range Low address aligned High address aligned 0xFF_FFFF Figure 1-2. MC9S12ZVL-Family Global Memory Map. (See Table 1-2 for individual device details) MC912ZVL Family Reference Manual, Rev. 2.48 36 NXP Semiconductors Device Overview MC9S12ZVL-Family 1.6.1 Part ID Assignments The part ID is located in four 8-bit registers at addresses 0x0000-0x0003. The read-only value is a unique part ID for each revision of the chip. Table 1-4 shows the assigned part ID number and mask set number. Table 1-4. Assigned Part ID Numbers 1.7 Device Mask Set Number Part ID MC9S12ZVL32 N22G 0x04150000 MC9S12ZVL16 N22G 0x04150000 MC9S12ZVL8 N22G 0x04150000 MC9S12ZVLS32 N22G 0x04150000 MC9S12ZVLS16 N22G 0x04150000 MC9S12ZVL64 N37P 0x04170000 MC9S12ZVL96 N37P 0x04170000 MC9S12ZVL128 N37P 0x04170000 MC9S12ZVLA64 N37P 0x04170000 MC9S12ZVLA96 N37P 0x04170000 MC9S12ZVLA128 N37P 0x04170000 Signal Description and Device Pinouts This section describes signals that connect off-chip. It includes pin out diagrams a table of signal properties, and detailed discussion of signals. Internal inter module signal mapping at device level is described in 1.9 Internal Signal Mapping. 1.7.1 Pin Assignment Overview Table 1-5 provides a summary of which ports are available for 48-pin and 32-pin package option. Table 1-5. Port availability by Package Option MC9S12ZVL / MC9S12ZVLA MC9S12ZVLS Port 48-pin LQFP 32-pin LQFP / QFN-EP 32-pin QFN-EP Port AD PAD[9:0] PAD[5:0] PAD[5:0] Port E PE[1:0] PE[1:0] PE[1:0] Port L (HVI) PL0 PL0 PL0 Port J PJ[1:0] - - Port P PP[7:0] PP[7,5,3,1] PP[7,5,3,1] Port S PS[3:0] PS[3:0] PS[3:0] Port T PT[7:0] PT[2:0] PT[1:0] sum of ports 35 20 19 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 37 Device Overview MC9S12ZVL-Family To avoid current drawn from floating inputs, all non-bonded pins should be configured as output or configured as input with a pull up or pull down device enabled 1.7.2 Detailed External Signal Descriptions This section describes the properties of signals available at device pins. Signal names associated with modules that can be instantiated more than once on an S12 are indexed, even if the module is only instantiated once on the MC9S12ZVL-Family. If a signal already includes a channel number, then the index is inserted before the channel number. Thus ANx_y corresponds to AN instance x, channel number y. 1.7.2.1 RESET — External Reset Signal The RESET signal is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has an internal pull-up device. 1.7.2.2 TEST — Test Pin This input only pin is reserved for factory test. This pin has an internal pull-down device. NOTE The TEST pin must be tied to ground in all applications. 1.7.2.3 MODC — Mode C Signal The MODC signal is used as a MCU operating mode select during reset. The state of this signal is latched to the MODC bit at the rising edge of RESET. Out of reset the pull-up device is enabled. 1.7.2.4 PAD[9:0] / KWAD[9:0] — Port AD, Input Pins of ADC PAD[9:0] are general-purpose input or output signals. The signals can be configured on per signal basis as interrupt inputs with wake-up capability (KWAD[9:0]). These signals can have a pull-up or pull-down device selected and enabled on per signal basis. During and out of reset the pull devices are disabled. 1.7.2.5 PE[1:0] — Port E I/O Signals PE[1:0] are general-purpose input or output signals. The signals can have a pull-down device, enabled by on a per pin basis. Out of reset the pull-down devices are enabled. 1.7.2.6 PL0 — Port L Input Signal PL0 is the high voltage input port. The signal can be configured as interrupt input with wake-up capability (KWL[0]).The pin voltage is divided and mapped to an ADC channel. MC912ZVL Family Reference Manual, Rev. 2.48 38 NXP Semiconductors Device Overview MC9S12ZVL-Family 1.7.2.7 PJ[1:0] — Port P I/O Signals PJ[1:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. During and out of reset the pull devices are enabled. 1.7.2.8 PP[7:0] / KWP[7:0] — Port P I/O Signals PP[7:0] are general-purpose input or output signals. The signals can be configured on per signal basis as interrupt inputs with wake-up capability (KWP[7:0]). They can have a pull-up or pull-down device selected and enabled on per signal basis. During and out of reset the pull devices are disabled. 1.7.2.9 PS[3:0] / KWS[3:0] — Port S I/O Signals PS[3:0] are general-purpose input or output signals. The signals can be configured on per signal basis as interrupt inputs with wake-up capability (KWS[3:0]). They can have a pull-up or pull-down device selected and enabled on per signal basis. During and out of reset the pull-up devices are enabled. 1.7.2.10 PT[7:0] — Port T I/O Signals PT[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. During and out of reset the pull devices are disabled. 1.7.2.11 AN0[9:0] — ADC Input Signals These are the analog inputs of the Analog-to-Digital Converters. ADC has 10 analog input channels connected to PAD port pins. 1.7.2.12 1.7.2.12.1 ACMP Signals ACMP_0 / ACMP_1 — Analog Comparator Inputs ACMP_0 and ACMP_1 are the inputs of the analog comparator ACMP. 1.7.2.12.2 ACMPO — Analog Comparator Output ACMPO is the outputs of the analog comparators. 1.7.2.13 1.7.2.13.1 DAC Signals AMP Output Pin This analog pin is used for the buffered analog output voltage from the operational amplifier outputs, when the according mode is selected in DACCTL register bits DACM[2:0]. 1.7.2.13.2 AMPP Input Pin This analog input pin is used as input signal for the operational amplifier positive input pins when the according mode is selected in DACCTL register bits DACM[2:0]. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 39 Device Overview MC9S12ZVL-Family 1.7.2.13.3 AMPM Input Pin This analog input pin is used as input signal for the operational amplifiers negative input pin when the according mode is selected in DACCTL register bits DACM[2:0]. 1.7.2.14 1.7.2.14.1 PGA Signals PGA_IN0 / PGA_IN1 — Programmable Gain Amplifier Inputs PGA_IN0 and PGA_IN1 are the inputs of the Programmable Gain Amplifier. 1.7.2.14.2 PGA_REF1 — Programmable Gain Amplifier Reference Inputs PGA_REF1 is the reference voltage the input of the Programmable Gain Amplifier. 1.7.2.15 VRH, VRL — ADC Reference Signals VRH and VRL are the reference voltage input pins for the analog-to-digital converter. 1.7.2.16 SPI0 Signals 1.7.2.16.1 SS0 Signal This signal is associated with the slave select SS functionality of the serial peripheral interface SPI0. 1.7.2.16.2 SCK0 Signal This signal is associated with the serial clock SCK functionality of the serial peripheral interface SPI0. 1.7.2.16.3 MISO0 Signal This signal is associated with the MISO functionality of the serial peripheral interface SPI0. This signal acts as master input during master mode or as slave output during slave mode. 1.7.2.16.4 MOSI0 Signal This signal is associated with the MOSI functionality of the serial peripheral interface SPI0. This signal acts as master output during master mode or as slave input during slave mode 1.7.2.17 1.7.2.17.1 SCI[1:0] Signals RXD[1:0] Signals These signals are associated with the receive functionality of the serial communication interfaces (SCI[1:0]). MC912ZVL Family Reference Manual, Rev. 2.48 40 NXP Semiconductors Device Overview MC9S12ZVL-Family 1.7.2.17.2 TXD[1:0] Signals These signals are associated with the transmit functionality of the serial communication interfaces (SCI[1:0]). 1.7.2.18 1.7.2.18.1 IIC0 Signals SCL0 This signal is associated with the SCL functionality of the IIC0 module. 1.7.2.18.2 SDA0 This signal is associated with the SDA functionality of the IIC0 module. 1.7.2.19 Timer0 IOC0[5:0] Signals The signals IOC0[5:0] are associated with the input capture or output compare functionality of the timer (TIM0) module. 1.7.2.20 Timer1 IOC1[1:0] Signals The signals IOC1[1:0] are associated with the input capture or output compare functionality of the timer (TIM1) module. 1.7.2.21 PWM[7:0] Signals The signals PWM[7:0] are associated with the PWM module digital channel outputs. 1.7.2.22 Interrupt Signals — IRQ and XIRQ IRQ is a maskable level or falling edge sensitive input. XIRQ is a non-maskable level-sensitive interrupt. 1.7.2.23 1.7.2.23.1 Oscillator and Clock Signals Oscillator Signals — EXTAL and XTAL EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the internal PLLCLK, independent of EXTAL and XTAL. XTAL is the oscillator output. The EXTAL and XTAL signals are associated with PE[1:0]. 1.7.2.23.2 ECLK This signal is associated with the output of the bus clock (ECLK). NOTE This feature is only intended for debug purposes at room temperature. It must not be used for clocking external devices in an application. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 41 Device Overview MC9S12ZVL-Family 1.7.2.24 1.7.2.24.1 BDC and Debug Signals BKGD — Background Debug signal The BKGD signal is used as a pseudo-open-drain signal for the background debug communication. The BKGD signal has an internal pull-up device. 1.7.2.24.2 DBGEEV — External Event Input This signal is the DBG external event input. It is input only. Within the DBG module, it allows an external event to force a state sequencer transition. A falling edge at the external event signal constitutes an event. Rising edges have no effect. The maximum frequency of events is half the internal core bus frequency. 1.7.2.25 1.7.2.25.1 CAN0 Signals RXCAN0 Signal This signal is associated with the receive functionality of the scalable controller area network controller (MSCAN0). 1.7.2.25.2 TXCAN0 Signal This signal is associated with the transmit functionality of the scalable controller area network controller (MSCAN0). 1.7.2.26 1.7.2.26.1 LIN Physical Layer Signals LIN This pad is connected to the single-wire LIN data bus. 1.7.2.26.2 LPTXD This is the LIN physical layer transmitter input signal. 1.7.2.26.3 LPRXD This is the LIN physical layer receiver output signal. 1.7.2.26.4 LPDR1 This is the LIN LP0DR1 register bit, visible at the designated pin for debug purposes. 1.7.2.27 BCTL BCTL is the ballast connection for the on chip voltage regulator. It provides the base current of an external PNP transistor of the VDDX and VDDA supplies. MC912ZVL Family Reference Manual, Rev. 2.48 42 NXP Semiconductors Device Overview MC9S12ZVL-Family 1.7.3 Power Supply Pins The power and ground pins are described below. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. NOTE All ground pins must be connected together in the application. 1.7.3.1 VDDX, VSSX1, VSSX2 — Digital I/O Power and Ground Pins VDDX is the voltage regulator output to supply the digital I/O drivers.It supplies the VDDX domain pads. The VSSX1and VSSX2 pin are the ground pin for the digital I/O drivers. Bypass requirements on VDDX, VSSX2 depend on how heavily the MCU pins are loaded. 1.7.3.2 VDDA, VSSA — Power Supply Pins for ADC These are the power supply and ground pins for the analog-to-digital converter and the voltage regulator. These pins must be externally connected to the voltage regulator (VDDX, VSSX). A separate bypass capacitor for the ADC supply is recommended. 1.7.3.3 VSS — Core Ground Pin The voltage supply of nominally 1.8V is generated by the internal voltage regulator. The return current path is through the VSS pin. 1.7.3.4 LGND — LINPHY Ground Pin LGND is the ground pin for the LIN physical layer LINPHY. This pin must be connected to board ground, even if the LINPHY is not used. 1.7.3.5 VSUP — Voltage Supply Pin for Voltage Regulator VSUP is the 12V/18V supply voltage pin for the on chip voltage regulator. This is the voltage supply input from which the voltage regulator generates the on chip voltage supplies. It must be protected externally against a reverse battery connection. 1.8 Device Pinouts MC9S12ZVL-Family is available in 48-pin package and 32-pin package. Signals in parentheses in Figure 1-3 to Figure 1-5 denote alternative module routing options. The exposed pad must be connected to a grounded contact pad on the PCB. The exposed pad has an electrical connection within the package to VSSFLAG (VSSX die connection). MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 43 48 47 46 45 44 43 42 41 40 39 38 37 VSS PP1(1) / KWP1 / PWM1 / (IOC1_1) VSSX1 VDDX PP7(2) / /KWP7 / PWM7 / (IOC1_0) PT3 / IOC0_3 PJ1 / SCL0 / (PWM7) / (TXCAN0)(4) PJ0 / SDA0 / (PWM5) / (RXCAN0)(4) PT2 / IOC0_2 / ACMPO(3) PP5(1) / XIRQ / KWP5 / PWM5 VSSX2 PP3(1) / IRQ / KWP3 / PWM3 Device Overview MC9S12ZVL-Family 1 2 3 4 5 6 7 8 9 10 11 12 MC9S12ZVL(A)-Family 48-pin LQFP 36 35 34 33 32 31 30 29 28 27 26 25 RESET PS3 / KWS3 / SS0 / (IOC0_5) / ECLK PS2 / KWS2 / SCK0 / (IOC0_4) / DBGEEV / (TXCAN0)(4) PS1 / KWS1 / MOSI0 / (PWM6) / (TXD0)/(LPDC0) / (IOC0_3) PP4 / KWP4 / PWM4 PP2 / KWP2 / PWM2 PP0 / KWP0 / PWM0 PT7 / IOC1_1 PS0 / KWS0 / MISO0 / (PWM4) / (RXD0) / (IOC0_2) / (RXCAN0)(4) PT1 / IOC0_1 / (SCL0) / TXD1 / (PWM0) / (LPRXD0) BKGD / MODC LGND PGA_REF1(3) / VRL(5) / AN1 / KWAD1 / PAD1 VSSA VDDA (3) ACMP_0 / VRH / AN0 / KWAD0 / PAD0 IOC1_0 / PT6 PWM6 / (ETRIG0) / KWP6 / PP6 (RXD1) / IOC0_4 / PT4 (TXD1) / IOC0_5 / PT5 TEST (LPTXD0) / (PWM2) / RXD1 / (SDA0) / IOC0_0 / PT0 BCTL LIN 13 14 15 16 17 18 19 20 21 22 23 24 VSUP KWL0 / HVI0 / PL0 EXTAL / (ETRIG0) / PE0 XTAL / PE1 AN9 / KWAD9 / PAD9 AMPM(3) / AN8 / KWAD8 / PAD8 AMPP(3) / AN7 / KWAD7 / PAD7 AMP(3) / AN6 / KWAD6 / PAD6 AN5 / (ETRIG0) / KWAD5 / PAD5 ACMP_1(3) / AN4 / KWAD4 / PAD4 PGA_IN1(3) / AN3 / KWAD3 / PAD3 PGA_IN0(3) / AN2 / KWAD2 / PAD2 (1) supports 25 mA driver strength to VSSX 20 mA driver strength from VDDX (EVDD) (3) MC9S12ZVLA Family device only (4) MC9S12ZVL(A)128/96/64 device only (5) MC9S12ZVL(S)32/16/8 device only (2 )supports Figure 1-3. MC9S12ZVL-Family 48-pin LQFP pin out MC912ZVL Family Reference Manual, Rev. 2.48 44 NXP Semiconductors 32 31 30 29 28 27 26 25 VSS PP1(1) / KWP1 / PWM1 / (IOC1_1) VSSX1 VDDX PP7(2) / KWP7 / PWM7 / (IOC1_0) PT2 / IOC0_2 / ACMPO(3) PP5 / XIRQ / KWP5 / PWM5 PP3 / IRQ / KWP3 / PWM3 Device Overview MC9S12ZVL-Family 1 2 3 4 5 6 7 8 MC9S12ZVL(A)Family 32-pin LQFP / QFN(3) PGA_REF1(3) / VRL(5) / AN1 / KWAD1 / PAD1 VSSA VDDA ACMP_0(3) / VRH / AN0 / KWAD0 / PAD0 TEST (LPTXD0) / (PWM2) / RXD1 / (SDA0) / IOC0_0 / PT0 BCTL LIN 9 10 11 12 13 14 15 16 VSUP KWL0 / HVI0 / PL0 EXTAL / (ETRIG0) / PE0 XTAL / PE1 AN5 / (ETRIG0) / KWAD5 / PAD5 ACMP_1(3) / AN4 / KWAD4 / PAD4 PGA_IN1(3) / AN3 / KWAD3 / PAD3 PGA_IN0(3) / AN2 / KWAD2 / PAD2 24 23 22 21 20 19 18 17 RESET PS3 / KWS3 / SS0 / (IOC0_5) / ECLK PS2 / KWS2 / SCK0 / (IOC0_4) / DBGEEV / (TXCAN0)(4) PS1 / KWS1 / MOSI0 / (PWM6) / (TXD0) (LPDC0) / (IOC0_3) PS0 / KWS0 / MISO0 / (PWM4) / (RXD0) / (IOC0_2) / (RXCAN0)(4) PT1 / IOC0_1 / (SCL0) / TXD1 / (PWM0) / (LPRXD0) BKGD / MODC LGND (1) supports 25 mA driver strength to VSSX 20 mA driver strength from VDDX (EVDD) (3) MC9S12ZVLA Family device only (4) MC9S12ZVL(A)128/96/64 device only (5) MC9S12ZVL(S)32/16/8 device only (2 )supports Figure 1-4. MC9S12ZVL(A) 32-pin LQFP / QFN pin out MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 45 32 31 30 29 28 27 26 25 VSS PP1(1) / KWP1 / PWM1 / (IOC1_1) VSSX1 VDDX PP7(2) / KWP7 / PWM7 / (IOC1_0) PP5(1) / XIRQ / KWP5 / PWM5 VSSX2 PP3(1) / IRQ / KWP3 / PWM3 Device Overview MC9S12ZVL-Family 1 2 3 4 5 6 7 8 MC9S12ZVLSFamily 32-pin QFN 24 23 22 21 20 19 18 17 RESET PS3 / KWS3 / SS0 / (IOC0_5) / ECLK PS2 / KWS2 / SCK0 / (IOC0_4) / DBGEEV PS1 / KWS1 / MOSI0 / (PWM6) / (TXD0) (LPDC0) / (IOC0_3) PS0 / KWS0 / MISO0 / (PWM4) / (RXD0) / (IOC0_2) PT1 / IOC0_1 / (SCL0) / TXD1 / (PWM0) / (LPRXD0) BKGD / MODC LGND VRL / AN1 / KWAD1 / PAD1 VSSA VDDA VRH / AN0 / KWAD0 / PAD0 TEST (LPTXD0) / (PWM2) / RXD1 / (SDA0) / IOC0_0 / PT0 BCTL LIN 9 10 11 12 13 14 15 16 VSUP KWL0 / HVI0 / PL0 EXTAL / (ETRIG0) / PE0 XTAL / PE1 AN5 / (ETRIG0) / KWAD5 / PAD5 AN4 / KWAD4 / PAD4 AN3 / KWAD3 / PAD3 AN2 / KWAD2 / PAD2 (1) supports (2) 25 mA driver strength to VSSX supports 20 mA driver strength from VDDX (EVDD) Figure 1-5. MC9S12ZVLS 32-pin QFN pin out MC912ZVL Family Reference Manual, Rev. 2.48 46 NXP Semiconductors Device Overview MC9S12ZVL-Family Table 1-6. Pin Summary LQFP / QFN(2) Q F N1 Function Power Supply Internal Pull Resistor CTRL Reset State VSUP — — — VDDX — — — — VDDX PERE/ PPSE Down — — — VDDX PERE/ PPSE Down — — — — VDDA PERADH/ PPSADH Off AN8 AMPM2 — — — VDDA PERADH/ PPSADH Off KWAD7 AN7 AMPP(2) — — — VDDA PERADL/ PPSADL Off PAD6 KWAD6 AN6 AMP(2) — — — VDDA PERADL/ PPSADL Off 5 PAD5 KWAD5 ETRIG0 AN5 — — — VDDA PERADL/ PPSADL Off 6 6 PAD4 KWAD4 AN4 ACMP_1(2) — — — VDDA PERADL/ PPSADL Off 11 7 7 PAD3 KWAD3 AN3 PGA_IN1(2 — — — VDDA PERADL/ PPSADL Off 12 8 8 PAD2 KWAD2 AN2 PGA_IN0(2 — — — VDDA PERADL/ PPSADL Off 13 9 9 PAD1 KWAD1 AN1 VRL3 PGA_REF 1(2) — — VDDA PERADL/ PPSADL Off 14 10 10 VSSA — — — — — — — — — 15 11 11 VDDA — — — — — — VDDA — — — — VDDA PERADL/ PPSADL Off 48 32 32 Pin 1st Func. 2nd Func. 3rd Func. 4th Func. 5th Func. 6th Func. 1 1 1 VSUP — — — — — — 2 2 2 PL0 HVI0 KWL0 — — — 3 3 3 PE0 ETRIG0 EXTAL — — 4 4 4 PE1 XTAL — — 5 — — PAD9 KWAD9 AN9 6 — — PAD8 KWAD8 7 — — PAD7 8 — — 9 5 10 ) ) ACMP_0 (2) 16 12 12 PAD0 KWAD0 AN0 VRH 17 — — PT6 IOC1_0 — — — — — VDDX PERT/ PPST Off 18 — — PP6 KWP[6] ETRIG0 PWM6 — — — VDDX PERP/ PPSP Off 19 — — PT4 IOC0_4 RXD1 — — — — VDDX PERT/ PPST Off 20 — — PT5 IOC0_5 TXD1 — — — — VDDX PERT/ PPST Off 21 13 13 TEST — — — — — — — RESET Down 22 14 14 PT0 IOC0_0 SDA0 RXD1 PWM2 LPTXD0 — VDDX PERT/ PPST Off MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 47 Device Overview MC9S12ZVL-Family Table 1-6. Pin Summary LQFP / QFN(2) Q F N1 Function Power Supply Internal Pull Resistor CTRL Reset State — — — — — — — — — LGND — — — — — VDDX TXD1 PWM0 LPRXD0 — VDDX PERT/ PPST Off MISO0 PWM4 RXD0 IOC0_2 RXCAN04 VDDX PERS/ PPSS Up IOC1_1 — — — — — VDDX PERT/ PPST Off PP0 KWP0 PWM0 — — — — VDDX PERP/ PPSP Off — PP2 KWP2 PWM2 — — — — VDDX PERP/ PPSP Off — — PP4 KWP4 PWM4 — — — — VDDX PERP/ PPSP Off 33 21 21 PS1 KWS1 MOSI0 PWM6 TXD0 LPDC0 IOC0_3 — VDDX PERS/ PPSS Up 34 22 22 PS2 KWS2 SCK0 IOC0_4 DBGEEV TXCAN0(4) — VDDX PERS/ PPSS Up 35 23 23 PS3 KWS3 SS0 IOC0_5 ECLK — — VDDX PERS/ PPSS Up 36 24 24 RESET — — — — — — VDDX TEST pin Up IRQ KWP3 PWM3 — — — VDDX PERP/ PPSP Off 48 32 32 Pin 1st Func. 2nd Func. 3rd Func. 4th Func. 5th Func. 6th Func. 23 15 15 BCTL — — — — — — 24 16 16 LIN — — — — — 25 17 17 LGND — — — — 26 18 18 BKGD MODC — — 27 19 19 PT1 IOC0_1 SCL0 28 20 20 PS0 KWS0 29 — — PT7 30 — — 31 — 32 Up 37 25 25 PP35 38 — 26 VSSX2 — — — — — — VDDX — — 39 26 27 PP5(5) XIRQ KWP5 PWM5 — — — VDDX PERP/ PPSP Off 40 27 — PT2 IOC0_2 ACMPO(3) — — — — VDDX PERT/ PPST Off 41 — — PJ0 SDA0 PWM5 RXCAN0(4 — — — VDDX PERTJ/ PPSJ Up 42 — — PJ1 SCL0 PWM7 TXCAN0(4) — — — VDDX PERJ/ PPSJ Up 43 — — PT3 IOC0_3 — — — — —— VDDX PERT/ PPST Off 44 28 28 PP76 KWP7 PWM7 IOC1_0 — — — VDDX PERP/ PPSP Off 45 29 29 VDDX — — — — — — VDDX — — 46 30 30 VSSX1 — — — — — — VSSX — — ) MC912ZVL Family Reference Manual, Rev. 2.48 48 NXP Semiconductors Device Overview MC9S12ZVL-Family Table 1-6. Pin Summary LQFP / QFN(2) 1 2 3 4 5 6 7 Q F N1 Internal Pull Resistor Function Power Supply Reset State 48 32 32 Pin 1st Func. 2nd Func. 3rd Func. 4th Func. 5th Func. 6th Func. 47 31 31 PP17 KWP1 PWM1 IOC1_1 — — — VDDX PERP/ PPSP Off 48 32 32 VSS — — — — — — — — — CTRL MC9S12ZVLS devices only MC9S12ZVLA devices only MC9S12ZVL(S)32/16/8 devices only MC9S12ZVL(A)128/96/64 devices only 25 mA driver strength to VSSX, only available on MC9S12ZVL(A) 48-pin package and MC9S12ZVLS devices 20 mA driver strength from VDDX (EVDD) 25 mA driver strength to VSSX 1.9 Internal Signal Mapping This section specifies the mapping of inter-module signals at device level. 1.9.1 1.9.1.1 ADC Connectivity ADC Reference Voltages on S12ZVL(A)128/96/48 devices ADC reference Voltage signal VRH_1 is mapped to VDDA;VRH_0 is mapped to PAD0; VRL_1 and VRL_0 are mapped to VSSA. 1.9.1.2 ADC Reference Voltages on S12ZVL(S)32/16/8 devices ADC reference Voltage signal VRH_1 is mapped to VDDA;VRH_0 is mapped to PAD0; VRL_1 is mapped to VSSA and VRL_0 is mapped to PAD1. 1.9.1.3 ADC External Trigger Input Connection The ADC module includes one external trigger input ETRIG0. The external trigger allows the user to synchronize ADC conversion to external trigger events. 1.9.1.4 ADC Internal Channels The ADC internal channel mapping is shown in Table 1-7. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 49 Device Overview MC9S12ZVL-Family Table 1-7. Usage of ADC Internal Channels ADCCMD_1 CH_SEL[5:0] Usage ADC Channel 0 0 1 0 0 0 Internal_0 ADC temperature sensor1 0 0 1 0 0 1 Internal_1 Bandgap Voltage VBG or Chip temperature sensor VHT, see CPMU temperature sensor Temperature Control Register (CPMUHTCTL) 0 0 1 1 0 0 Internal_4 BATS VSUP sense voltage 0 0 1 1 0 1 Internal_5 High Voltage input Port L0 0 0 1 1 1 1 Internal_7 PGA_OUT voltage 1 The ADC internal temperature sensors must be calibrated by the user. No electrical parameters are specified for these sensors. The VREG temperature sensor electrical parameters are given in the appendices. 1.9.2 BDC Clock Source Connectivity The BDC clock, BDCCLK, is mapped to the IRCCLK generated in the CPMU module. The BDC clock, BDCFCLK is mapped to the device bus clock, generated in the CPMU module. 1.9.3 FTMRZ Connectivity The soc_erase_all_req input to the flash module is driven directly by a BDC erase flash request resulting from the BDC ERASE_FLASH command. 1.9.4 CPMU Connectivity The API clock generated in the CPMU is not mapped to a device pin in the MC9S12ZVL-Family. 1.9.5 LINPHY Connectivity The VLINSUP supply is internally connected to the device VSUP pin. 1.9.6 1.9.6.1 MC9S12ZVLA analog module Connectivity ACMP - PGA - DAC - ADC Connectivity Figure 1-6 shows the ACMP - PGA - DAC - ADC connectivity. The DAC and ADC VRH/VRL connections are not visible. The connection from the DAC AMP port via the PAD6 to the PGA is available even if the PAD6 is not available on the 32 pin packages. Therefore is possible to use the DAC as reference Voltage generation for the PGA in a 32 pin packages device. MC912ZVL Family Reference Manual, Rev. 2.48 50 NXP Semiconductors Device Overview MC9S12ZVL-Family PAD7 AMPP AMP PAD8 AMPM DACI PAD6 DAC TIM0 IOC2 acmpi_1 PAD0 acmpi_0 ACMPO ACO ACMP_0 PAD4 ACMP_1 PT2 ACMP PGA_REF0 PAD1 PGA_REF1 Trigger PGA_OUT PAD2 PGA_IN0 PAD3 PGA_IN1 Internal_7 ADC PGA Figure 1-6. MC9S12ZVLA ACMP - PGA - DAC - ADC Connectivity On the MC9S12ZVLA device follow ADC option bit decoding is used. Table 1-8. ADC option bit decoding ADC option bit OPT[1:0] PGA input source selection 2’b00 no input selected 2’b01 PGA_IN0 is used as input voltage 2’b10 PGA_IN1 is used as input voltage other Reserved MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 51 Device Overview MC9S12ZVL-Family 1.9.6.2 DAC Connectivity DAC reference Voltage signal VRH is mapped to VDDA and VRL is mapped to VSSA. The DACU pin is not connected on the MC9S12ZVLA device. 1.9.7 PWM channel mapping The table below shows the mapping of the available PWM module channels to the PIM module. 1.9.7.1 PWM channel mapping for MC9S12ZVL(S)32/16/8 See below the PWM0 channel mapping for MC9S12ZVL(S)32/16/8 devices. PWM0, channel 0 PWM0, channel 1 PWM0, channel 2 PWM0, channel 3 PWM0, channel 4 PWM0, channel 5 PWM0, channel 6 PWM0, channel 7 PWM0 PWM option 0 PWM option 1 PWM option 2 PWM option 3 PWM option 4 PWM option 5 PWM option 6 PWM option 7 P O R T P PIM Figure 1-7. PWM Channel mapping MC9S12ZVL(S)32/16/8 1.9.7.2 PWM channel mapping for MC9S12ZVL(A)128/96/64 See below the PWM0 and PWM1 channel mapping for MC9S12ZVL(A)128/96/64 devices. MC912ZVL Family Reference Manual, Rev. 2.48 52 NXP Semiconductors Device Overview MC9S12ZVL-Family PWM0, channel 0 PWM0, channel 1 PWM0, channel 2 PWM0, channel 3 PWM0, channel 4 PWM0, channel 5 PWM0, channel 6 PWM0, channel 7 PWM0 PWM option 0 PWM option 1 PWM option 2 PWM option 3 PWM option 4 PWM option 5 PWM option 6 PWM option 7 P O R T P PIM PWM1, channel 0 PWM1, channel 1 PWM1, channel 2 PWM1, channel 3 PWM1, channel 4 PWM1, channel 5 PWM1, channel 6 PWM1, channel 7 PWM1 Figure 1-8. PWM Channel mapping MC9S12ZVL(A)128/96/64 1.10 Modes of Operation The MCU can operate in different modes. These are described in 1.10.2 Chip Configuration Modes. The MCU can operate in different power modes to facilitate power saving when full system performance is not required. These are described in 1.10.4 Low Power Modes. Some modules feature a software programmable option to freeze the module status whilst the background debug module is active to facilitate debugging. This is referred to as freeze mode at module level. 1.10.1 3.3V - 5V VDDX behavior on MC9S12ZVL(A)128/96/64 devices The On-Chip Voltage Regulator inside MC9S12ZVL(A)128/96/64 devices supports 3.3V or 5.0V VDDX supply. After power up, the device is in 3.3V VDDX mode. Then is possible to switch to the 5.0V VDDX behavior. For more details see the “Clock, Reset and Power Management Unit” description. Some of the analog modules will work with a reduced specification during 3.3V VDDX mode, please see the Electrical Specification for mode details. 1.10.2 Chip Configuration Modes The different modes and the security state of the MCU affect the debug features (enabled or disabled). MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 53 Device Overview MC9S12ZVL-Family The operating mode out of reset is determined by the state of the MODC signal during reset (Table 1-9). The MODC bit in the MODE register shows the current operating mode and provides limited mode switching during operation. The state of the MODC signal is latched into this bit on the rising edge of RESET. Table 1-9. Chip Modes Chip Modes 1.10.2.1 MODC Normal single chip 1 Special single chip 0 Normal Single-Chip Mode This mode is intended for normal device operation. The opcode from the on-chip memory is being executed after reset (requires the reset vector to be programmed correctly). The processor program is executed from internal memory. To avoid unpredictable behavior do not start the device in Normal Single-Chip mode while the FLASH is erased. 1.10.2.2 Special Single-Chip Mode This mode is used for debugging operation, boot-strapping, or security related operations. The background debug mode (BDM) is active on leaving reset in this mode. 1.10.3 Debugging Modes The background debug mode (BDM) can be activated by the BDC module or directly when resetting into Special Single-Chip mode. Detailed information can be found in the BDC module section. Writing to internal memory locations using the debugger, whilst code is running or at a breakpoint, can change the flow of application code. The MC9S12ZVL-Family supports BDC communication throughout the device Stop mode. During Stop mode, writes to control registers can alter the operation and lead to unexpected results. It is thus recommended not to reconfigure the peripherals during STOP using the debugger. 1.10.4 Low Power Modes The device has two dynamic-power modes (run and wait) and two static low-power modes (stop and pseudo stop). For a detailed description refer to the CPMU section. • Dynamic power mode: Run — Run mode is the main full performance operating mode with the entire device clocked. The user can configure the device operating speed through selection of the clock source and the phase locked loop (PLL) frequency. To save power, unused peripherals must not be enabled. • Dynamic power mode: Wait — This mode is entered when the CPU executes the WAI instruction. In this mode the CPU does not execute instructions. The internal CPU clock is switched off. All peripherals can be active MC912ZVL Family Reference Manual, Rev. 2.48 54 NXP Semiconductors Device Overview MC9S12ZVL-Family • in system wait mode. For further power consumption the peripherals can individually turn off their local clocks. Asserting RESET, XIRQ, IRQ, or any other interrupt that is not masked, either locally or globally by a CCR bit, ends system wait mode. Static power modes: Static power (Stop) modes are entered following the CPU STOP instruction unless an NVM command is active. When no NVM commands are active, the Stop request is acknowledged and the device enters either Stop or Pseudo Stop mode. — Pseudo-stop: In this mode the system clocks are stopped but the oscillator is still running and the real time interrupt (RTI), watchdog (COP) and Autonomous Periodic Interrupt (API) may be enabled. Other peripherals are turned off. This mode consumes more current than system STOP mode but, as the oscillator continues to run, the full speed wake up time from this mode is significantly shorter. — Stop: In this mode the oscillator is stopped and clocks are switched off. The counters and dividers remain frozen. The autonomous periodic interrupt (API) may remain active but has a very low power consumption. If the BDC is enabled in Stop mode, the VREG remains in full performance mode and the CPMU continues operation as in run mode. With BDC enabled and BDCCIS bit set, then all clocks remain active to allow BDC access to internal peripherals. If the BDC is enabled and BDCCIS is clear, then the BDCSI clock remains active, but bus and core clocks are disabled. 1.11 Security The MCU security mechanism prevents unauthorized access to the flash memory. It must be emphasized that part of the security must lie with the application code. An extreme example would be application code that dumps the contents of the internal memory. This would defeat the purpose of security. Also, if an application has the capability of downloading code through a serial port and then executing that code (e.g. an application containing bootloader code), then this capability could potentially be used to read the EEPROM and Flash memory contents even when the microcontroller is in the secure state. In this example, the security of the application could be enhanced by requiring a response authentication before any code can be downloaded. Device security details are also described in the flash block description. 1.11.1 Features The security features of the S12Z chip family are: • Prevent external access of the non-volatile memories (Flash, EEPROM) content • Restrict execution of NVM commands 1.11.2 Securing the Microcontroller The chip can be secured by programming the security bits located in the options/security byte in the Flash memory array. These non-volatile bits keep the device secured through reset and power-down. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 55 Device Overview MC9S12ZVL-Family This byte can be erased and programmed like any other Flash location. Two bits of this byte are used for security (SEC[1:0]). The contents of this byte are copied into the Flash security register (FSEC) during a reset sequence. The meaning of the security bits SEC[1:0] is shown in Table 1-10. For security reasons, the state of device security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’. Table 1-10. Security Bits SEC[1:0] Security State 00 1 (secured) 01 1 (secured) 10 0 (unsecured) 11 1 (secured) NOTE Please refer to the Flash block description for more security byte details. 1.11.3 Operation of the Secured Microcontroller By securing the device, unauthorized access to the EEPROM and Flash memory contents is prevented. Secured operation has the following effects on the microcontroller: 1.11.3.1 • • Background debug controller (BDC) operation is completely disabled. Execution of Flash and EEPROM commands is restricted (described in flash block description). 1.11.3.2 • • Normal Single Chip Mode (NS) Special Single Chip Mode (SS) Background debug controller (BDC) commands are restricted Execution of Flash and EEPROM commands is restricted (described in flash block description). In special single chip mode the device is in active BDM after reset. In special single chip mode on a secure device, only the BDC mass erase and BDC control and status register commands are possible. BDC access to memory mapped resources is disabled. The BDC can only be used to erase the EEPROM and Flash memory without giving access to their contents. 1.11.4 Unsecuring the Microcontroller Unsecuring the microcontroller can be done using three different methods: 1. Backdoor key access 2. Reprogramming the security bits 3. Complete memory erase MC912ZVL Family Reference Manual, Rev. 2.48 56 NXP Semiconductors Device Overview MC9S12ZVL-Family 1.11.4.1 Unsecuring the MCU Using the Backdoor Key Access In normal single chip mode, security can be temporarily disabled using the backdoor key access method. This method requires that: • The backdoor key has been programmed to a valid value • The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’. • The application program programmed into the microcontroller has the capability to write to the backdoor key locations The backdoor key values themselves would not normally be stored within the application data, which means the application program would have to be designed to receive the backdoor key values from an external source (e.g. through a serial port) The backdoor key access method allows debugging of a secured microcontroller without having to erase the Flash This is particularly useful for failure analysis. NOTE No backdoor key word is allowed to have the value 0x0000 or 0xFFFF. 1.11.5 Reprogramming the Security Bits Security can also be disabled by erasing and reprogramming the security bits within the flash options/security byte to the unsecured value. Since the erase operation will erase the entire sector (0x7F_FE00–0x7F_FFFF) the backdoor key and the interrupt vectors will also be erased; this method is not recommended for normal single chip mode. The application software can only erase and program the Flash options/security byte if the Flash sector containing the Flash options/security byte is not protected (see Flash protection). Thus Flash protection is a useful means of preventing this method. The microcontroller enters the unsecured state after the next reset following the programming of the security bits to the unsecured value. This method requires that: • The application software previously programmed into the microcontroller has been designed to have the capability to erase and program the Flash options/security byte. • The Flash sector containing the Flash options/security byte is not protected. 1.11.6 Complete Memory Erase The microcontroller can be unsecured by erasing the entire EEPROM and Flash memory contents. If ERASE_FLASH is successfully completed, then the Flash unsecures the device and programs the security byte automatically. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 57 Device Overview MC9S12ZVL-Family 1.12 1.12.1 Resets and Interrupts Resets Table 1-11. lists all reset sources and the vector locations. Resets are explained in detail in the Chapter 9, “S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)”. Table 1-11. Reset Sources and Vector Locations 1.12.2 Vector Address Reset Source CCR Mask Local Enable 0xFFFFFC Power-On Reset (POR) None None Low Voltage Reset (LVR) None None External pin RESET None None Clock monitor reset None OSCE Bit in CPMUOSC and OMRE Bit in CPMUOSC2 register COP watchdog reset None CR[2:0] in CPMUCOP register Interrupt Vectors Table 1-12 lists all interrupt sources and vectors in the default order of priority. The interrupt module description provides an interrupt vector base register (IVBR) to relocate the vectors. Table 1-12. Interrupt Vector Locations (Sheet 1 of 4) CCR Mask Local Enable Unimplemented page1 op-code trap (SPARE) None None - - Vector base + 0x1F4 Unimplemented page2 op-code trap (TRAP) None None - - Vector base + 0x1F0 Software interrupt instruction (SWI) None None - - Vector base + 0x1EC System call interrupt instruction (SYS) None None - - Vector base + 0x1E8 Machine exception None None - - Vector Address1 Interrupt Source Vector base + 0x1F8 Vector base + 0x1E4 Reserved Vector base + 0x1E0 Reserved Wake up Wake up from STOP from WAIT Vector base + 0x1DC Spurious interrupt — None - - Vector base + 0x1D8 XIRQ interrupt request X bit None Yes Yes Vector base + 0x1D4 IRQ interrupt request I bit IRQCR(IRQEN) Yes Yes Vector base + 0x1D0 RTI time-out interrupt I bit CPMUINT (RTIE) See CPMU section Yes MC912ZVL Family Reference Manual, Rev. 2.48 58 NXP Semiconductors Device Overview MC9S12ZVL-Family Table 1-12. Interrupt Vector Locations (Sheet 2 of 4) Wake up Wake up from STOP from WAIT Vector Address1 Interrupt Source CCR Mask Local Enable Vector base + 0x1CC TIM0 timer channel 0 I bit TIM0TIE (C0I) No Yes Vector base + 0x1C8 TIM0 timer channel 1 I bit TIM0TIE (C1I) No Yes Vector base + 0x1C4 TIM0 timer channel 2 I bit TIM0TIE (C2I) No Yes Vector base + 0x1C0 TIM0 timer channel 3 I bit TIM0TIE (C3I) No Yes Vector base + 0x1BC TIM0 timer channel 4 I bit TIM0TIE (C4I) No Yes Vector base + 0x1B8 TIM0 timer channel 5 I bit TIM0TIE (C5I) No Yes No Yes Vector base + 0x1B4 to Vector base + 0x1B0 Vector base + 0x1AC Reserved TIM0 timer overflow I bit Vector base + 0x1A8 to Vector base + 0x1A4 TIM0TSCR2(TOI) Reserved Vector base + 0x1A0 SPI0 I bit SPI0CR1 (SPIE, SPTIE) No Yes Vector base + 0x19C SCI0 I bit SCI0CR2 (TIE, TCIE, RIE, ILIE) SCI0ACR1 (RXEDGIE, BERRIE, BKDIE) RXEDGIF only Yes Vector base + 0x198 SCI1 I bit SCI1CR2 (TIE, TCIE, RIE, ILIE) SCI1ACR1 (RXEDGIE, BERRIE, BKDIE) RXEDGIF only Yes Vector base + 0x194 to Vector base + 0x190 Reserved Vector base + 0x18C ADC Error I bit ADCEIE (IA_EIE, CMD_EIE, EOL_EIE, TRIG_EIE, RSTAR_EIE, LDOK_EIE) ADCIE(CONIF_OIE) No Yes Vector base + 0x188 ADC conversion sequence abort I bit ADCIE(SEQAD_IE) No Yes Vector base + 0x184 ADC conversion complete I bit ADCCONIE[15:0] No Yes Vector base + 0x180 Oscillator status interrupt I bit CPMUINT (OSCIE) No Yes Vector base + 0x17C PLL lock interrupt I bit CPMUINT (LOCKIE) No Yes Vector base + 0x178 ACMP I bit ACMPC(ACIE) No Yes No Yes Vector base + 0x174 to Vector base + 0x174 Vector base + 0x170 Reserved RAM error I bit EECIE (SBEEIE) MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 59 Device Overview MC9S12ZVL-Family Table 1-12. Interrupt Vector Locations (Sheet 3 of 4) Vector Address1 Interrupt Source CCR Mask Vector base + 0x16C to Vector base + 0x168 Local Enable Wake up Wake up from STOP from WAIT Reserved Vector base + 0x164 FLASH error I bit FERCNFG (SFDIE) No Yes Vector base + 0x160 FLASH command I bit FCNFG (CCIE) No Yes Vector base + 0x15C CAN0 wake-up I bit CANRIER(WUPIE) Yes Yes Vector base + 0x158 CAN0 error I bit CANRIER(CSCIE, OVRIE) No Yes Vector base + 0x154 CAN0 receive I bit CANRIER(RXFIE) No Yes Vector base + 0x150 CAN0 transmit I bit CANRIER(TXEIE[2:0]) No Yes Vector base + 0x14C to Vector base + 0x148 Reserved Vector base + 0x144 LINPHY over-current interrupt I bit LPIE (LPDTIE, LPOCIE) No Yes Vector base + 0x140 BATS supply voltage monitor interrupt I bit BATIE (BVHIE,BVLIE) No Yes Yes Yes Vector base + 0x13C to Vector base + 0x128 Vector base + 0x124 Reserved Port S interrupt I bit Vector base + 0x120 to Vector base + 0x110 PIES(PIES[3:0]) Reserved Vector base + 0x10C Port P interrupt I bit PIEP(PIEP[7:0]) Yes Yes Vector base + 0x108 Port P over-current interrupt I bit OCIEP (OCIEP7,OCIEP5,OCIEP3,O CIEP1,) No Yes Vector base + 0x104 Low-voltage interrupt (LVI) I bit CPMUCTRL (LVIE) No Yes Vector base + 0x100 Autonomous periodical interrupt (API) I bit Yes Yes Vector base + 0x0FC High temperature interrupt I bit No Yes Yes Yes Yes Yes Port AD interrupt I bit Vector base + 0x0F0 to Vector base + 0x0C4 Vector base + 0x0C0 Vector base + 0x0BC to Vector base + 0x0B0 CPMUHTCTL(HTIE) Reserved Vector base + 0x0F8 Vector base + 0x0F4 CPMUAPICTRL (APIE) PIEADH(PIEADH[1:0]) PIEADL(PIEADL[7:0]) Reserved Port L interrupt I bit PIEL(PIEL[0]) Reserved MC912ZVL Family Reference Manual, Rev. 2.48 60 NXP Semiconductors Device Overview MC9S12ZVL-Family Table 1-12. Interrupt Vector Locations (Sheet 4 of 4) Wake up Wake up from STOP from WAIT Vector Address1 Interrupt Source CCR Mask Local Enable Vector base + 0x0AC TIM1 timer channel 0 I bit TIM1TIE (C0I) No Yes Vector base + 0x0A8 TIM1 timer channel 1 I bit TIM1TIE (C1I) No Yes No Yes No Yes Vector base + 0x0A4 to Vector base + 0x090 Vector base + 0x08C Reserved TIM1 timer overflow I bit Vector base + 0x088 to Vector base + 0x064 Vector base + 060 Reserved IIC Vector base + 0x05C to Vector base + 0x10 1 TIM1TSCR2(TOI) I bit IBCR(IBIE) Reserved 15 bits vector address based 1.12.3 Effects of Reset When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections for register reset states. On each reset, the Flash module executes a reset sequence to load Flash configuration registers. 1.12.3.1 Flash Configuration Reset Sequence Phase On each reset, the Flash module will hold CPU activity while loading Flash module registers from the Flash memory. If double faults are detected in the reset phase, Flash module protection and security may be active on leaving reset. This is explained in more detail in the Flash module description. 1.12.3.2 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. 1.12.3.3 I/O Pins Refer to the PIM section for reset configurations of all peripheral module ports. 1.12.3.4 RAM The system RAM arrays, including their ECC syndromes, are initialized following a power on reset. With the exception of a power-on-reset the RAM content is unaltered by a reset occurrence. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 61 Device Overview MC9S12ZVL-Family 1.13 1.13.1 Module device level dependencies COP Configuration The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register are loaded from the Flash configuration field byte at global address 0xFF_FE0E during the reset sequence. See Table 1-13 and Table 1-14 for coding. Table 1-13. Initial COP Rate Configuration NV[2:0] in FOPT Register CR[2:0] in COPCTL Register 000 111 001 110 010 101 011 100 100 011 101 010 110 001 111 000 Table 1-14. Initial WCOP Configuration 1.13.2 NV[3] in FOPT Register WCOP in COPCTL Register 1 0 0 1 BDC Command Restriction The BDC command READ_DBGTB returns 0x00 on this device because the DBG module does not feature a trace buffer. MC912ZVL Family Reference Manual, Rev. 2.48 62 NXP Semiconductors Device Overview MC9S12ZVL-Family 1.13.3 Flash IFR Mapping Table 1-15. Flash IFR Mapping Target F 1.14 E D C B A 9 8 7 6 5 4 3 2 1 IFR Byte Address 0 ADC reference conversion using VDDA/VSSA 0x1F_C040 & 0x1F_C041 ADC reference conversion using VRH/VRL 0x1F_C042 & 0x1F_C043 Application Information 1.14.1 ADC Calibration For applications that do not provide external ADC reference voltages, the VDDA/VSSA supplies can be used as sources for VRH/VRL respectively. Since the VDDA must be connected to VDDX at board level in the application, the accuracy of the VDDA reference is limited by the internal voltage regulator accuracy. In order to compensate for VDDA reference voltage variation in this case, the reference voltage is measured during production test using the internal reference voltage VBG, which has a narrow variation over temperature and external voltage supply. VBG is mapped to an internal channel of the ADC module, see Table 1-7. The resulting 12-bit right justified ADC conversion results of VBG are stored to the flash IFR for reference, as listed in Table 1-15. The measurement conditions of the reference conversion are listed in the device electrical parameters appendix. By measuring the voltage VBG in the application environment and comparing the result to the reference value in the IFR, it is possible to determine the current ADC reference voltage VRH: StoredReference V RH = -------------------------------------------------------------  5V ConvertedReference The exact absolute value of an analog conversion can be determined as follows: StoredReference  5V Result = ConvertedADInput  ------------------------------------------------------------------------nConvertedReference  2 With: ConvertedADInput: ConvertedReference: StoredReference: n: Result of the analog to digital conversion of the desired pin Result of internal channel conversion Value in IFR location ADC resolution (12 bit) MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 63 Device Overview MC9S12ZVL-Family NOTE The ADC reference voltage VRH must remain at a constant level throughout the conversion process. 1.14.2 SCI Baud Rate Detection The baud rate for SCI0 and SCI1 is achieved by using a timer channel to measure the data rate on the RXD signal. 1. Establish the link: — For SCI0: Set [T0IC3RR1:T0IC3RR0]=0b01 to disconnect IOC0_3 from TIM0 input capture channel 3 and reroute the timer input to the RXD0 signal of SCI0. — For SCI1: Set [T0IC3RR1:T0IC3RR0]=0b10 to disconnect IOC0_3 from TIM0 input capture channel 3 and reroute the timer input to the RXD1 signal of SCI1. 2. Determine pulse width of incoming data: Configure TIM0 IC3 to measure time between incoming signals 1.14.3 Voltage Domain Monitoring The BATS module monitors the voltage on the VSUP pin, providing status and flag bits, an interrupt and a connection to the ADC, for accurate measurement of the scaled VSUP level. The POR circuit monitors the VDD and VDDA domains, ensuring a reset assertion until an adequate voltage level is attained. The LVR circuit monitors the VDD, VDDF and VDDX domains, generating a reset when the voltage in any of these domains drops below the specified assert level. The VDDX LVR monitor is disabled when the VREG is in reduced power mode. A low voltage interrupt circuit monitors the VDDA domain. MC912ZVL Family Reference Manual, Rev. 2.48 64 NXP Semiconductors Chapter 2 Port Integration Module (S12ZVLPIMV2) Revision History Rev. No. (Item No.) Date (Submitted By) V02.10 19 Nov 2014 V02.11 6-Jun 2018 V02.12 19-Nov 2018 2.1 2.1.1 Sections Affected Substantial Change(s) • Corrected bit descriptions for MODRR1 (PWMn becomes PWM option n). • Removed redundant mention of over-current protection on PP7 in output configuration (already specified in footnote). • Added T0IC3RR1-0 to Routing Register Bits controlling (IOC0_3) on PS1. • Added footnote 2 to MODRR3 register • Corrected footnote 2 to MODRR3 register Introduction Overview The S12ZVL-family port integration module establishes the interface between the peripheral modules and the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins. This document covers: • 2-pin port E associated with the external oscillator • 10-pin port AD with pin interrupts and key-wakeup function; associated with 10 ADC channels • 8-pin port T associated with 8 TIM channels, 1 routed SCI, 1 routed IIC, 2 routed PWM options and 1 ACMP output • 4-pin port S with pin interrupts and key-wakeup function; associated with 1 SPI, ECLK, 4 routed TIM channels, 2 routed PWM channels, 1 MSCAN and 1 routed SCI • 8-pin port P with pin interrupts and key-wakeup function or IRQ, XIRQ interrupt inputs; associated with 8 PWM channels and 2 routed TIM channels • 2-pin port J associated with 1 IIC, 1 routed MSCAN or 2 routed PWM channels • 1-pin port L with pin interrupts and key-wakeup function; associated with 1 high voltage input (HVI) Most I/O pins can be configured by register bits to select data direction and to enable and select pull-up or pull-down devices. MC9S12ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 65 Port Integration Module (S12ZVLPIMV2) NOTE This document assumes the availability of all features offered in the largest package option. Refer to the package and pin-out section in the device overview for functions not available in lower pin count packages. 2.1.2 Features The PIM includes these distinctive registers: • Data registers for ports E, AD, T, S, P and J when used as general-purpose I/O • Data direction registers for ports E, AD, T, S, P and J • Control registers to enable pull devices on ports E, AD, T, S, P, J and L • Control registers to select pull-ups or pull-downs on ports E, AD, T, S, P and J • Control register to enable open-drain (wired-or) mode on port S and J • Control register to enable digital input buffers on port AD and L • Interrupt enable register for pin interrupts and key-wakeup (KWU) on port AD, S, P and Interrupt flag register for pin interrupts and key-wakeup (KWU) on port AD, S, P and L • Control register to configure IRQ pin operation • Control register to enable ECLK output • Routing registers to support signal relocation on external pins and control internal routings: — 6 PWM channels to alternative pins (one option each) — 8 TIM channels to alternative pins (one option each) — IIC0 to alternative pins (one option each) — SCI1 to alternative pins (one option each) — MSCAN to alternative pins (one option each) — ADC0 trigger input with edge select from internal TIM output compare channel link, ACMP0 output or external pins (four options) — Various SCI0-LINPHY0 routing options supporting standalone and LIN conformance testing — Internal RXD0 and RXD1 link to TIM input capture channel (IC0_3) for baud rate detection — Internal ACLK link to TIM input capture channel A standard port pin has the following minimum features: • Input/output selection • 5V output drive • 5V digital and analog input • Input with selectable pull-up or pull-down device Optional features supported on dedicated pins: • Open drain for wired-or connections (ports S and J) • Interrupt input with glitch filtering • High current drive strength from VDDX with over-current protection MC912ZVL Family Reference Manual, Rev. 2.48 66 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) • High current drive strength to VSSX • Selectable drive strength for high current capable outputs 2.2 External Signal Description This section lists and describes the signals that do connect off-chip. Table 2-1 shows all pins with the pins and functions that are controlled by the PIM. Routing options are denoted in parentheses. NOTE If there is more than one function associated with a pin, the output priority is indicated by the position in the table from top (highest priority) to bottom (lowest priority). Inputs do not arbitrate priority unless noted differently in Table 2-28. Table 2-1. Pin Functions and Priorities Port Pin Pin Function & Priority I/O — BKGD MODC1 I BKGD E PE1 XTAL I/O S12ZBDC communication — CPMU OSC signal Pin Function after Reset — BKGD — — I/O General-purpose — EXTAL — — (ETRIG0) I PTE[0] PAD9 AN9 PTADH[1]/ KWADH[1] PAD8 MODC input during RESET Routing Register Bit PTE[1] PE0 AD Description CPMU OSC signal ADC0 external trigger I/O General-purpose I ADC0 analog input I/O General-purpose; with interrupt and key-wakeup TRIG0RR2-0 — — I DAC AMP inverting input (-) — AN8 I ADC0 analog input — I/O General-purpose; with interrupt and key-wakeup GPIO — AMPM (DAC) PTADH[0]/ KWADH[0] GPIO — MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 67 Port Integration Module (S12ZVLPIMV2) Port Pin Pin Function & Priority I/O AD PAD7 AMPP (DAC) I AN7 I PAD6 — DAC AMP output — AN6 I ADC0 analog input — I/O General-purpose; with interrupt and key-wakeup AN5 I ADC0 analog input (ETRIG0) I ADC0 external trigger I/O General-purpose; with interrupt and key-wakeup — — TRIG0RR2-0 — ACMP_1 I ACMP input 1 (to mux) — AN4 I ADC0 analog input — I/O General-purpose; with interrupt and key-wakeup — PGA_IN1 I PGA input option 1 — AN3 I ADC0 analog input — I/O General-purpose; with interrupt and key-wakeup — PGA_IN0 I PGA input option 0 — AN2 I ADC0 analog input — I/O General-purpose; with interrupt and key-wakeup — PGA_REF I PGA reference input — VRL I ADC0 voltage reference low — I ADC0 analog input — AN1 PTADL[1]/ KWADL[1] PAD0 ADC0 analog input O PTADL[2]/ KWADL[2] PAD1 GPIO AMP (DAC) PTADL[3]/ KWADL[3] PAD2 — — PTADL[4]/ KWADL[4] PAD3 DAC AMP non-inverting input (+) I/O General-purpose; with interrupt and key-wakeup PTADL[5]/ KWADL[5] PAD4 Pin Function after Reset PTADL[7]/ KWADL[7] PTADL[6]/ KWADL[6] PAD5 Routing Register Bit Description ACMP_0 I/O General-purpose; with interrupt and key-wakeup I ACMP input 0 — — VRH I ADC0 voltage reference high — AN0 I ADC0 analog input — PTADL[0]/ KWADL[0] I/O General-purpose; with interrupt and key-wakeup — MC912ZVL Family Reference Manual, Rev. 2.48 68 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) Port Pin Pin Function & Priority T PT7-6 IOC1_1:IOC1_0 PTT[7:6] PT5 PT4 PT1 PT0 I/O TIM1 channel 1-0 T1C1RR:T1C0RR GPIO I/O General-purpose — (TXD1) O I/O TIM0 channel 5 PTT[5] I/O General-purpose I SCI1 transmit I/O TIM0 channel 4 PTT[4] I/O General-purpose 2 IOC0_3 ACMPO0 SCI1RR T0C5RR — SCI1 receive IOC0_4 PTT[3] PT2 Pin Function after Reset Description IOC0_5 (RXD1) PT3 Routing Register Bit I/O I/O TIM0 channel 3 SCI1RR T0C4RR — T0C3RR, T0IC3RR1-0 I/O General-purpose O ACMP0 output IOC0_2 I/O TIM0 channel 2 PTT[2] I/O General-purpose — — T0C2RR — (LPRXD0) O LINPHY0 receive output (PWM0) O PWM option 0 PWM0RR TXD1 O SCI1 transmit SCI1RR (SCL0) I/O IIC0 IOC0_1 I/O TIM0 channel 1 PTT[1] I/O General-purpose S0L0RR2-0 IIC0RR — — (LPTXD0) I LINPHY0 transmit input S0L0RR2-0 (PWM2) O PWM option 2 PWM2RR RXD1 I SCI1 receive SCI1RR (SDA0) I/O IIC0 IOC0_0 I/O TIM0 channel 0 IIC0RR — PTT[0] I/O General-purpose — MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 69 Port Integration Module (S12ZVLPIMV2) Port Pin Pin Function & Priority I/O S PS3 ECLK O (IOC0_5) SS0 PTS[3]/ KWS[3] PS2 DBGEEV I/O TIM0 channel 5 Pin Function after Reset — GPIO T0C5RR I/O SPI0 slave select — I/O General-purpose; with interrupt and key-wakeup — I DBG external event MSCAN0 transmit — TXCAN0 O I/O TIM0 channel 4 T0C4RR SCK0 I/O SPI0 serial clock — I/O General-purpose; with interrupt and key-wakeup — (IOC0_32) (TXD0)/ (LPDC0) PS0 Free-running clock Routing Register Bit (IOC0_4) PTS[2]/ KWS[2] PS1 Description I/O TIM0 channel 3 CAN0RR T0C3RR, T0IC3RR1-0 O SCI0 transmit/ LPTXD0 direct control by LP0DR[LP0DR1] (PWM6) O PWM option 6 MOSI0 I/O SPI0 master out/slave in — PTS[1]/ KWS[1] I/O General-purpose; with interrupt and key-wakeup — RXCAN0 (IOC0_2) I MSCAN0 receive I/O TIM0 channel 2 S0L0RR2-0 PWM6RR CAN0RR T0C2RR (RXD0) I SCI0 receive S0L0RR2-0 (PWM4) O PWM option 4 PWM4RR MISO0 I/O SPI0 master in/slave out — PTS[0]/ KWS[0] I/O General-purpose; with interrupt and key-wakeup — MC912ZVL Family Reference Manual, Rev. 2.48 70 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) Port Pin Pin Function & Priority P PP73 (IOC1_0) PWM7 PTP[7]/ KWP[7]/ EVDD1 PP6 PWM6 (ETRIG0) PTP[6]/ KWP[6] PP54 XIRQ5 PP4 PP34 PP14 J PJ1 PJ0 L 1 2 I/O TIM1 channel 0 T1C0RR GPIO O PWM7RR PWM option 7 I/O General-purpose; with interrupt and key-wakeup O PWM option 6 I ADC0 external trigger — PWM6RR TRIG0RR1:TRIG0RR0 I/O General-purpose; with interrupt and key-wakeup I Non-maskable level-sensitive interrupt PWM option 5 PWM5 O I/O General-purpose; with interrupt and key-wakeup PWM4 O PTP[4]/ KWP[4] I/O General-purpose; with interrupt and key-wakeup PWM option 4 — — PWM5RR — PWM4RR — I Maskable level- or falling edge-sensitive interrupt — PWM option 3 — PWM3 O PTP[3]/ KWP[3] I/O General-purpose; with interrupt and key-wakeup PWM2 O PTP[2]/ KWP[2] I/O General-purpose; with interrupt and key-wakeup (IOC1_1) PP0 Pin Function after Reset Description PTP[5]/ KWP[5] IRQ PP2 Routing Register Bit I/O PWM option 2 I/O TIM1 channel 1 PWM1 O PWM option 1 PTP[1]/ KWP[1] I/O General-purpose; with interrupt and key-wakeup PWM0 O PTP[0]/ KWP[0] I/O General-purpose; with interrupt and key-wakeup PWM option 0 — PWM2RR — T1C1RR — — PWM0RR — (TXCAN0) O MSCAN0 transmit CAN0RR (PWM7) O PWM option 7 PWM7RR SCL0 I/O IIC0 PTJ[1] I/O General-purpose IIC0RR — (RXCAN0) I MSCAN0 receive CAN0RR (PWM5) O PWM option 5 PWM5RR PL0 SDA0 I/O IIC0 PTJ[0] I/O General-purpose PTIL[0]/ KWL[0] I General-purpose high-voltage input (HVI); with interrupt and wakeup; optional ADC link GPIO IIC0RR — — GPI (HVI) Function active when RESET asserted Routable input capture function MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 71 Port Integration Module (S12ZVLPIMV2) 3 High-current capable high-side output with over-current interrupt High-current capable low-side output with over-current interrupt 5 The interrupt is enabled by clearing the X mask bit in the CPU CCR. The pin is forced to input upon first clearing of the X bit and is held in this state until reset. A stop or wait recovery using XIRQ with the X bit set is not available. 4 2.3 Memory Map and Register Definition This section provides a detailed description of all port integration module registers. Subsection 1.3.1 shows all registers and bits at their related addresses within the global SoC register map. A detailed description of every register bit is given in subsection 1.3.2 to 1.3.4. MC912ZVL Family Reference Manual, Rev. 2.48 72 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) 2.3.1 Register Map Global Address Register Name 0x0200 MODRR0 0x0201 MODRR1 0x0202 MODRR2 0x0203 MODRR3 0x0204 MODRR4 0x0206– 0x0207 Reserved 0x0208 ECLKCTL 0x0209 IRQCR 0x020A– 0x020C Reserved 0x020D Reserved 0x020E Reserved 0x020F Reserved 0x0210– 0x025F Reserved 0x0260 PTE 0x0261 Reserved R Bit 7 6 0 0 W R W R W R 5 4 3 CAN0RR IIC0RR SCI1RR PWM7RR PWM6RR PWM5RR PWM4RR T0C3RR Bit 0 S0L0RR2-0 PWM2RR T0C2RR 0 0 PWM0RR 0 T1C0RR T0C5RR T0C4RR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG0RR2 TRIG0NEG TRIG0RR1 TRIG0RR0 W R 1 T1C1RR W R 0 2 T0IC3RR1-0 W R W R W R NECLK IRQE IRQEN 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTE1 PTE0 0 0 0 0 0 0 0 0 W R W R W R W R W R W R W MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 73 Port Integration Module (S12ZVLPIMV2) Global Address Register Name 0x0262 PTIE 0x0263 Reserved 0x0264 DDRE 0x0265 Reserved 0x0266 PERE 0x0267 Reserved 0x0268 PPSE 0x0269– 0x027F Reserved 0x0280 PTADH 0x0281 PTADL 0x0282 PTIADH 0x0283 PTIADL 0x0284 DDRADH 0x0285 DDRADL 0x0286 PERADH 0x0287 PERADL R Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 PTIE1 PTIE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDRE1 DDRE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERE1 PERE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPSE1 PPSE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTADH1 PTADH0 PTADL7 PTADL6 PTADL5 PTADL4 PTADL3 PTADL2 PTADL1 PTADL0 0 0 0 0 0 0 PTIADH1 PTIADH0 PTIADL6 PTIADL5 PTIADL4 PTIADL3 PTIADL2 PTIADL1 PTIADL0 0 0 0 0 0 W R W R W R W R W R W R W R W R W R W R W R PTIADL7 W R 0 W R W R DDRADL7 DDRADL6 DDRADL5 DDRADL4 DDRADL3 DDRADL2 DDRADL1 DDRADL0 0 0 0 0 0 W R W DDRADH1 DDRADH0 0 PERADH1 PERADH0 PERADL7 PERADL6 PERADL5 PERADL4 PERADL3 PERADL2 PERADL1 PERADL0 MC912ZVL Family Reference Manual, Rev. 2.48 74 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) Global Address Register Name 0x0288 PPSADH 0x0289 PPSADL 0x028A– 0x028B Reserved 0x028C PIEADH 0x028D PIEADL 0x028E PIFADH 0x028F PIFADL 0x0290– 0x0297 Reserved 0x0298 DIENADH 0x0299 DIENADL 0x029A– 0x02BF Reserved 0x02C0 PTT 0x02C1 PTIT 0x02C2 DDRT 0x02C3 PERT 0x02C4 PPST R Bit 7 6 5 4 3 2 0 0 0 0 0 0 W R W R 1 Bit 0 PPSADH1 PPSADH0 PPSADL7 PPSADL6 PPSADL5 PPSADL4 PPSADL3 PPSADL2 PPSADL1 PPSADL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIEADH1 PIEADH0 PIEADL7 PIEADL6 PIEADL5 PIEADL4 PIEADL3 PIEADL2 PIEADL1 PIEADL0 0 0 0 0 0 0 PIFADH1 PIFADH0 PIFADL7 PIFADL6 PIFADL5 PIFADL4 PIFADL3 PIFADL2 PIFADL1 PIFADL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W R W R W R W R W R W R DIENADH1 DIENADH0 DIENADL7 DIENADL6 DIENADL5 DIENADL4 DIENADL3 DIENADL2 DIENADL1 DIENADL0 0 0 0 0 0 0 0 0 PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 W R W R W R W R W R W MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 75 Port Integration Module (S12ZVLPIMV2) Global Address Register Name 0x02C5– 0x02CF Reserved 0x02D0 PTS 0x02D1 PTIS 0x02D2 DDRS 0x02D3 PERS 0x02D4 PPSS 0x02D5 Reserved 0x02D6 PIES 0x02D7 PIFS 0x02D8– 0x02DE Reserved 0x02DF WOMS 0x02E0– 0x02EF Reserved 0x02F0 PTP 0x02F1 PTIP 0x02F2 DDRP 0x02F3 PERP R Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 PTS3 PTS2 PTS1 PTS0 0 0 0 0 PTIS3 PTIS2 PTIS1 PTIS0 0 0 0 0 DDRS3 DDRS2 DDRS1 DDRS0 0 0 0 0 PERS3 PERS2 PERS1 PERS0 0 0 0 0 PPSS3 PPSS2 PPSS1 PPSS0 0 0 0 0 0 0 0 0 0 0 0 0 PIES3 PIES2 PIES1 PIES0 0 0 0 0 PIFS3 PIFS2 PIFS1 PIFS0 0 0 0 0 0 0 0 0 0 0 0 0 WOMS3 WOMS2 WOMS1 WOMS0 0 0 0 0 0 0 0 0 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W MC912ZVL Family Reference Manual, Rev. 2.48 76 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) Global Address Register Name 0x02F4 PPSP 0x02F5 Reserved 0x02F6 PIEP 0x02F7 PIFP 0x02F8 Reserved 0x02F9 OCPEP 0x02FA OCIEP 0x02FB OCIFP 0x02FC Reserved 0x02FD RDRP 0x02FE– 0x02FF Reserved 0x0300– 0x030F Reserved 0x0310 PTJ 0x0311 PTIJ 0x0312 DDRJ 0x0313 PERJ R W R Bit 7 6 5 4 3 2 1 Bit 0 PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 0 0 0 0 0 0 0 0 PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 0 0 0 0 0 0 0 0 W R W R W R W R W R W R W R OCPEP7 OCIEP7 OCIFP7 0 0 0 0 0 OCPEP5 OCIEP5 OCIFP5 0 0 0 0 0 OCPEP3 OCIEP3 OCIFP3 0 0 0 0 0 OCPEP1 OCIEP1 OCIFP1 0 0 0 0 0 W R W R RDRP7 0 RDRP5 0 RDRP3 0 RDRP1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTJ1 PTJ0 0 0 0 0 0 0 PTIJ1 PTIJ0 0 0 0 0 0 0 DDRJ1 DDRJ0 0 0 0 0 0 0 PERJ1 PERJ0 W R W R W R W R W R W MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 77 Port Integration Module (S12ZVLPIMV2) Global Address Register Name 0x0314 PPSJ 0x0315– 0x031E Reserved 0x031F WOMJ 0x0320– 0x032F Reserved 0x0330 Reserved 0x0331 PTIL 0x0332– 0x0333 Reserved 0x0334 PPSL 0x0335 Reserved 0x0336 PIEL 0x0337 PIFL 0x0338– 0x033B Reserved 0x033C DIENL 0x033D PTAL 0x033E PIRL R Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 PPSJ1 PPSJ0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WOMJ1 WOMJ0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTIL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTTEL PTPSL PTABYPL PTADIRL PTAENL 0 0 0 0 0 0 0 W R W R W R W R W R W R W R W R PPSL0 0 W R W R W R PIEL0 PIFL0 0 W R W R W R W 0 DIENL0 0 PIRL0[1:0] MC912ZVL Family Reference Manual, Rev. 2.48 78 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) Global Address Register Name 0x033F Reserved 0x0340– 0x037F Reserved 2.3.2 R Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W PIM Registers 0x0200-0x020F This section details the specific purposes of register implemented in address range 0x0200-0x020F. These registers serve for specific PIM related functions not part of the generic port registers. • If not stated differently, writing to reserved bits has no effect and read returns zero. • All register read accesses are synchronous to internal clocks. • Register bits can be written at any time if not stated differently. 2.3.2.1 Module Routing Register 0 (MODRR0) Access: User read/write1 Address 0x0200 R 7 6 5 4 3 0 0 CAN0RR IIC0RR SCI1RR S0L0RR2-0 — — TXCAN0 RXCAN0 SDA0 SCL0 TXD1 RXD1 SCI0-LINPHY0 (see Figure 2-2) 0 0 0 0 0 W Reset 2 0 1 0 0 0 Figure 2-1. Module Routing Register 0 (MODRR0) 1 Read: Anytime Write: Once in normal, anytime in special mode Table 2-2. MODRR0 Routing Register Field Descriptions Field 5 CAN0RR 4 IIC0RR Description Module Routing Register — CAN0 routing 1 RXCAN0 on PJ0; TXCAN0 on PJ1 0 RXCAN0 on PS0; TXCAN0 on PS2 Module Routing Register — IIC0 routing 1 SDA0 on PT0; SCL0 on PT1 0 SDA0 on PJ0; SCL0 on PJ1 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 79 Port Integration Module (S12ZVLPIMV2) Table 2-2. MODRR0 Routing Register Field Descriptions Field Description 3 SCI1RR 2-0 S0L0RR2-0 Module Routing Register — SCI1 routing 1 TXD1 on PT5; RXD1 on PT4 0 TXD1 on PT1; RXD1 on PT0 Module Routing Register — SCI0-LINPHY0 routing Selection of SCI0-LINPHY0 interface routing options to support probing and conformance testing. Refer to Figure 2-2 for an illustration and Table 2-3 for preferred settings. Note: SCI0 must be enabled for TXD0 routing to take effect on pins. LINPHY0 must be enabled for LPRXD0 and LPDC0 routings to take effect on pins. S0L0RR0 S0L0RR1 S0L0RR2 0 1 PS1 / TXD0 / LPDC0 PT0 / LPTXD0 SCI0 LINPHY0 1 0 TXD0 0 LPTXD0 1 LPDR1 0 RXD0 LIN LPRXD0 1 0 T0IC3RR1-0 1 01 PT1 / LPRXD0 10 RXD1 TIM0 input capture channel 3 11 ACLK 00 PS0 / RXD0 T0C3RR 0 PT3 1 PS1 Figure 2-2. SCI0-to-LINPHY0 Routing Options Illustration MC912ZVL Family Reference Manual, Rev. 2.48 80 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) Table 2-3. Preferred Interface Configurations S0L0RR[2:0] Description 000 Default setting: SCI0 connects to LINPHY0, interface internal only 001 Direct control setting: LP0DR[LPDR1] register bit controls LPTXD0, interface internal only 100 Probe setting: SCI0 connects to LINPHY0, interface accessible on 2 external pins 110 Conformance test setting: Interface opened and all 4 signals routed externally NOTE For standalone usage of SCI0 on external pins set S0L0RR[2:0]=0b110 and disable LINPHY0 (LPCR[LPE]=0). This releases PT0 and PT1 to other associated functions and maintains TXD0 and RXD0 signals on PS1 and PS0, respectively, if no other function with higher priority takes precedence. 2.3.2.2 Module Routing Register 1 (MODRR1) Access: User read/write1 Address 0x0201 R W Reset 7 6 5 4 3 PWM7RR PWM6RR PWM5RR PWM4RR PWM opt. 7 PWM opt. 6 PWM opt. 5 PWM opt. 4 — PWM opt. 2 — PWM opt. 0 0 0 0 0 0 0 0 0 0 2 PWM2RR 1 0 0 PWM0RR Figure 2-3. Module Routing Register 1 (MODRR1) 1 Read: Anytime Write: Once in normal, anytime in special mode Table 2-4. MODRR1 Routing Register Field Descriptions Field Description 7 Module Routing Register — PWM option 7 routing PWM7RR 1 PWM option 7 to PJ1 0 PWM option 7 to PP7 6 Module Routing Register — PWM option 6 routing PWM6RR 1 PWM option 6 to PS1 0 PWM option 6 to PP6 5 Module Routing Register — PWM option 5 routing PWM5RR 1 PWM option 5 to PJ0 0 PWM option 5 to PP5 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 81 Port Integration Module (S12ZVLPIMV2) Table 2-4. MODRR1 Routing Register Field Descriptions Field Description 4 Module Routing Register — PWM option 4 routing PWM4RR 1 PWM option 4 to PS0 0 PWM option 4 to PP4 2 Module Routing Register — PWM option 2 routing PWM2RR 1 PWM option 2 to PT0 0 PWM option 2 to PP2 0 Module Routing Register — PWM option 0 routing PWM0RR 1 PWM option 0 to PT1 0 PWM option 0 to PP0 2.3.2.3 Module Routing Register 2 (MODRR2) Access: User read/write1 Address 0x0202 R W Reset 7 6 5 4 3 2 1 0 T1C1RR T1C0RR T0C5RR T0C4RR T0C3RR T0C2RR 0 0 IOC1_1 IOC1_0 IOC0_5 IOC0_4 IOC0_3 IOC0_2 — — 0 0 0 0 0 0 0 0 Figure 2-4. Module Routing Register 2 (MODRR2) 1 Read: Anytime Write: Once in normal, anytime in special mode Table 2-5. MODRR2 Routing Register Field Descriptions Field Description 7 T1C1RR Module Routing Register — IOC1_1 routing 1 IOC1_1 to PP1 0 IOC1_1 to PT7 6 T1C0RR Module Routing Register — IOC1_0 routing 1 IOC1_0 to PP7 0 IOC1_0 to PT6 5 T0C5RR Module Routing Register — IOC0_5 routing 1 IOC0_5 to PS3 0 IOC0_5 to PT5 4 T0C4RR Module Routing Register — IOC0_4 routing 1 IOC0_4 to PS2 0 IOC0_4 to PT4 MC912ZVL Family Reference Manual, Rev. 2.48 82 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) Table 2-5. MODRR2 Routing Register Field Descriptions Field Description 3 T0C3RR Module Routing Register — IOC0_3 routing 1 IOC0_3 to PS1 0 IOC0_3 to PT3 2 T0C2RR Module Routing Register — IOC0_2 routing 1 IOC0_2 to PS0 0 IOC0_2 to PT2 2.3.2.4 Module Routing Register 3 (MODRR3) Access: User read/write1 Address 0x0203 R 7 6 5 4 0 0 0 0 — — — — 0 0 0 0 W Reset 3 2 1 0 TRIG0RR22 TRIG0NEG TRIG0RR1 TRIG0RR0 ADC0 Trigger 0 0 0 0 Figure 2-5. Module Routing Register 3 (MODRR3) 1 Read: Anytime Write: Once in normal, anytime in special mode 2 TRIG0RR2 bit is available on the S12ZVL A64/96/128 devices only. Table 2-6. MODRR3 Routing Register Field Descriptions Field Description 3 Module Routing Register — ADC0 Trigger input routing TRIG0RR2 1 ACMP0 output to ADC0 Trigger input 0 ADC0 Trigger input is defined by TRIG0RR1:TRIG0RR0 2 Module Routing Register — ADC0 Trigger input inverted polarity TRIG0NEG 1 Falling edge active on ADC0 Trigger input 0 Rising edge active on ADC0 Trigger input 1-0 TRIG0RR Module Routing Register — ADC0 Trigger input routing 11 PP6 (ETRIG0) to ADC0 Trigger input 10 PAD5 (ETRIG0) to ADC0 Trigger input 01 PE0 (ETRIG0) to ADC0 Trigger input 00 TIM0 output compare channel 2 to ADC0 Trigger input MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 83 Port Integration Module (S12ZVLPIMV2) 2.3.2.5 Module Routing Register 4 (MODRR4) Access: User read/write1 Address 0x0204 R 7 6 5 4 3 2 0 0 0 0 0 0 — — — — — — 0 0 0 0 0 0 1 T0IC3RR1-0 W Reset 0 TIM0 IC3 0 0 Figure 2-6. Module Routing Register 4 (MODRR4) 1 Read: Anytime Write: Anytime Table 2-7. MODRR4 Routing Register Field Descriptions Field Description 1-0 Module Routing Register — TIM0 IC3 routing T0IC3RR1-0 One out of four different sources can be selected as input to timer channel 3. 11 TIM0 input capture channel 3 is connected to ACLK 10 TIM0 input capture channel 3 is connected to RXD1 01 TIM0 input capture channel 3 is connected to RXD0 00 TIM0 input capture channel 3 is connected to pin selected by MODRR2[T0C3RR] MC912ZVL Family Reference Manual, Rev. 2.48 84 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) 2.3.2.6 ECLK Control Register (ECLKCTL) Access: User read/write1 Address 0x0208 7 R W Reset: NECLK 1 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 2-7. ECLK Control Register (ECLKCTL) 1 Read: Anytime Write: Anytime Table 2-8. ECLKCTL Register Field Descriptions Field Description 7 NECLK No ECLK — Disable ECLK output This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the internal bus clock. 1 ECLK disabled 0 ECLK enabled 2.3.2.7 IRQ Control Register (IRQCR) Access: User read/write1 Address 0x0209 R W Reset 7 6 IRQE IRQEN 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 2-8. IRQ Control Register (IRQCR) 1 Read: Anytime Write: IRQE: Once in normal mode, anytime in special mode IRQEN: Anytime Table 2-9. IRQCR Register Field Descriptions Field 7 IRQE 6 IRQEN Description IRQ select edge sensitive only — 1 IRQ pin configured to respond only to falling edges. Falling edges on the IRQ pin are detected anytime when IRQE=1 and will be cleared only upon a reset or the servicing of the IRQ interrupt. 0 IRQ configured for low level recognition IRQ enable — 1 IRQ pin is connected to interrupt logic 0 IRQ pin is disconnected from interrupt logic MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 85 Port Integration Module (S12ZVLPIMV2) 2.3.2.8 Reserved Register Access: User read/write1 Address 0x020D R W Reset 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved x x x x x x x x Figure 2-9. Reserved Register 1 Read: Anytime Write: Only in special mode. NOTE This reserved register is designed for factory test purposes only and is not intended for general user access. Writing to this register when in special modes can alter the modules functionality. 2.3.2.9 Reserved Register Access: User read/write1 Address 0x020E R W Reset 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved x x x x x x x x Figure 2-10. Reserved Register 1 Read: Anytime Write: Only in special mode NOTE This reserved register is designed for factory test purposes only and is not intended for general user access. Writing to this register when in special modes can alter the modules functionality. MC912ZVL Family Reference Manual, Rev. 2.48 86 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) 2.3.2.10 Reserved Register Access: User read/write1 Address 0x020F R W Reset 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved x x x x x x x x Figure 2-11. Reserved Register 1 Read: Anytime Write: Only in special mode NOTE This reserved register is designed for factory test purposes only and is not intended for general user access. Writing to this register when in special modes can alter the modules functionality. 2.3.3 PIM Generic Registers This section describes the details of all configuration registers. • Writing to reserved bits has no effect and read returns zero. • All register read accesses are synchronous to internal clocks. • All registers can be written at any time, however a specific configuration might not become active. E.g. a pull-up device does not become active while the port is used as a push-pull output. • General-purpose data output availability depends on priorization; input data registers always reflect the pin status independent of the use. • Pull-device availability, pull-device polarity, wired-or mode, key-wake up functionality are independent of the priorization unless noted differently. • For availability of individual bits refer to Section 2.3.1, “Register Map” and Table 2-27. NOTE This is a generic description of the standard PIM registers. Refer to Table 2-27 to determine the implemented bits in the respective register. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 87 Port Integration Module (S12ZVLPIMV2) 2.3.3.1 Port Data Register Access: User read/write1 Address 0x0260 PTE 0x0280 PTADH 0x0281 PTADL 0x02C0 PTT 0x02D0 PTS 0x02F0 PTP 0x0310 PTJ R W Reset 7 6 5 4 3 2 1 0 PTx7 PTx6 PTx5 PTx4 PTx3 PTx2 PTx1 PTx0 0 0 0 0 0 0 0 0 Figure 2-12. Port Data Register 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime Table 2-10. Port Data Register Field Descriptions Field Description 7-0 PTx7-0 Port — General purpose input/output data This register holds the value driven out to the pin if the pin is used as a general purpose output. When not used with the alternative function (refer to Table 2-1), these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. 2.3.3.2 Port Input Register Access: User read only1 Address 0x0262 PTIE 0x0282 PTIADH 0x0283 PTIADL 0x02C1 PTIT 0x02D1 PTIS 0x02F1 PTIP 0x0311 PTIJ R 7 6 5 4 3 2 1 0 PTIx7 PTIx6 PTIx5 PTIx4 PTIx3 PTIx2 PTIx1 PTIx0 0 0 0 0 0 0 0 0 W Reset Figure 2-13. Port Input Register 1 Read: Anytime Write: Never MC912ZVL Family Reference Manual, Rev. 2.48 88 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) Table 2-11. Port Input Register Field Descriptions Field Description 7-0 PTIx7-0 Port Input — Data input A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. 2.3.3.3 Data Direction Register Access: User read/write1 Address 0x0264 DDRE 0x0284 DDRADH 0x0285 DDRADL 0x02C2 DDRT 0x02D2 DDRS 0x02F2 DDRP 0x0312 DDRJ R W Reset 7 6 5 4 3 2 1 0 DDRx7 DDRx6 DDRx5 DDRx4 DDRx3 DDRx2 DDRx1 DDRx0 0 0 0 0 0 0 0 0 Figure 2-14. Data Direction Register 1 Read: Anytime Write: Anytime Table 2-12. Data Direction Register Field Descriptions Field Description 7-0 DDRx7-0 Data Direction — Select general-purpose data direction This bit determines whether the pin is a general-purpose input or output. If a peripheral module controls the pin the content of the data direction register is ignored. Independent of the pin usage with a peripheral module this register determines the source of data when reading the associated data register address. Note: Due to internal synchronization circuits, it can take up to two bus clock cycles until the correct value is read on port data and port input registers, when changing the data direction register. 1 Associated pin is configured as output 0 Associated pin is configured as input MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 89 Port Integration Module (S12ZVLPIMV2) 2.3.3.4 Pull Device Enable Register Access: User read/write1 Address 0x0266 PERE 0x0286 PERADH 0x0287 PERADL 0x02C3 PERT 0x02D3 PERS 0x02F3 PERP 0x0313 PERJ 7 6 5 4 3 2 1 0 PERx7 PERx6 PERx5 PERx4 PERx3 PERx2 PERx1 PERx0 Ports E, J: 0 0 0 0 0 0 1 1 Ports S: 0 0 0 0 1 1 1 1 Others: 0 0 0 0 0 0 0 0 R W Reset Figure 2-15. Pull Device Enable Register 1 Read: Anytime Write: Anytime Table 2-13. Pull Device Enable Register Field Descriptions Field Description 7-0 PERx7-0 Pull Enable — Activate pull device on input pin This bit controls whether a pull device on the associated port input or open-drain output pin is active. If a pin is used as push-pull output this bit has no effect. The polarity is selected by the related polarity select register bit. On open-drain output pins only a pull-up device can be enabled. 1 Pull device enabled 0 Pull device disabled MC912ZVL Family Reference Manual, Rev. 2.48 90 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) 2.3.3.5 Polarity Select Register Access: User read/write1 Address 0x0268 PPSE 0x0288 PPSADH 0x0289 PPSADL 0x02C4 PPST 0x02D4 PPSS 0x02F4 PPSP 0x0314 PPSJ 0x0334 PPSL 7 6 5 4 3 2 1 0 PPSx7 PPSx6 PPSx5 PPSx4 PPSx3 PPSx2 PPSx1 PPSx0 Ports E: 0 0 0 0 0 0 1 1 Others: 0 0 0 0 0 0 0 0 R W Reset Figure 2-16. Polarity Select Register 1 Read: Anytime Write: Anytime Table 2-14. Polarity Select Register Field Descriptions Field 7-0 PPSx7-0 2.3.3.6 Description Pull Polarity Select — Configure pull device and pin interrupt edge polarity on input pin This bit selects a pull-up or a pull-down device if enabled on the associated port input pin. If a port has interrupt functionality this bit also selects the polarity of the active edge. 1 Pull-down device selected; rising edge selected 0 Pull-up device selected; falling edge selected Port Interrupt Enable Register Access: User read/write1 Address 0x028C PIEADH 0x028D PIEADL 0x02D6 PIES 0x02F6 PIEP 0x0336 PIEL R W Reset 7 6 5 4 3 2 1 0 PIEx7 PIEx6 PIEx5 PIEx4 PIEx3 PIEx2 PIEx1 PIEx0 0 0 0 0 0 0 0 0 Figure 2-17. Port Interrupt Enable Register 1 Read: Anytime Write: Anytime MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 91 Port Integration Module (S12ZVLPIMV2) Table 2-15. Port Interrupt Enable Register Field Descriptions Field Description 7-0 PIEx7-0 Port Interrupt Enable — Activate pin interrupt (KWU) This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if the pin is operating in input or output mode when in use with the general-purpose or related peripheral function. 1 Interrupt is enabled 0 Interrupt is disabled (interrupt flag masked) 2.3.3.7 Port Interrupt Flag Register Access: User read/write1 Address 0x028E PIFADH 0x028F PIFADL 0x02D7 PIFS 0x02F7 PIFP 0x0337 PIFL R W Reset 7 6 5 4 3 2 1 0 PIFx7 PIFx6 PIFx5 PIFx4 PIFx3 PIFx2 PIFx1 PIFx0 0 0 0 0 0 0 0 0 Figure 2-18. Port Interrupt Flag Register 1 Read: Anytime Write: Anytime, write 1 to clear Table 2-16. Port Interrupt Flag Register Field Descriptions Field Description 7-0 PIFx7-0 Port Interrupt Flag — Signal pin event (KWU) This flag asserts after a valid active edge was detected on the related pin (see Section 2.4.4.2, “Pin interrupts and Key-Wakeup (KWU)”). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the associated interrupt enable bit is set. Writing a logic “1” to the corresponding bit field clears the flag. 1 Active edge on the associated bit has occurred 0 No active edge occurred 2.3.3.8 Digital Input Enable Register Access: User read/write1 Address 0x0298 DIENADH 0x0299 DIENADL R W Reset 7 6 5 4 3 2 1 0 DIENx7 DIENx6 DIENx5 DIENx4 DIENx3 DIENx2 DIENx1 DIENx0 0 0 0 0 0 0 0 0 Figure 2-19. Digital Input Enable Register MC912ZVL Family Reference Manual, Rev. 2.48 92 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) 1 Read: Anytime Write: Anytime Table 2-17. Digital Input Enable Register Field Descriptions Field Description 7-0 Digital Input Enable — Input buffer control DIENx7-0 This bit controls the digital input function. If set to 1 the input buffers are enabled and the pin can be used with the digital function. If a peripheral module is enabled which uses the pin with a digital function the input buffer is activated and the register bit is ignored. If the pin is used with an analog function this bit shall be cleared to avoid shoot-through current. 1 Associated pin is configured as digital input 0 Associated pin digital input is disabled 2.3.3.9 Reduced Drive Register Access: User read/write1 Address 0x02FD RDRP R W Reset 7 6 5 4 3 2 1 0 RDRx7 RDRx6 RDRx5 RDRx4 RDRx3 RDRx2 RDRx1 RDRx0 0 0 0 0 0 0 0 0 Figure 2-20. Reduced Drive Register 1 Read: Anytime Write: Anytime Table 2-18. Reduced Drive Register Field Descriptions Field Description 7-0 RDRx7-0 Reduced Drive Register — Select reduced drive for output pin This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin. 1 Reduced drive selected (approx. 1/10 of the full drive strength) 0 Full drive strength enabled 2.3.3.10 Wired-Or Mode Register Access: User read/write1 Address 0x02DF WOMS 0x031F WOMJ R W Reset 7 6 5 4 3 2 1 0 WOMx7 WOMx6 WOMx5 WOMx4 WOMx3 WOMx2 WOMx1 WOMx0 0 0 0 0 0 0 0 0 Figure 2-21. Wired-Or Mode Register MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 93 Port Integration Module (S12ZVLPIMV2) 1 Read: Anytime Write: Anytime Table 2-19. Wired-Or Mode Register Field Descriptions Field Description 7-0 Wired-Or Mode — Enable open-drain output WOMx7-0 This bit configures the output buffer as wired-or. If enabled the output is driven active low only (open-drain) while the active high drive is turned off. This allows a multipoint connection of several serial modules. These bits have no influence on pins used as inputs. 1 Output buffers operate as open-drain outputs 0 Output buffers operate as push-pull outputs 2.3.3.11 PIM Reserved Register Access: User read1 Address (any reserved, except when explicitly specified otherwise) R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 2-22. PIM Reserved Register 1 Read: Always reads 0x00 Write: Unimplemented 2.3.4 PIM Generic Register Exceptions This section lists registers with deviations from the generic description in one or more register bits. 2.3.4.1 Port P Over-Current Protection Enable Register (OCPEP) Access: User read/write1 Address 0x02F9 7 R W Reset OCPEP7 0 6 0 0 5 OCPEP5 0 4 0 0 3 OCPEP3 0 2 0 0 1 OCPEP1 0 0 0 0 Figure 2-23. Over-Current Protection Enable Register (OCPEP) 1 Read: Anytime Write:Anytime MC912ZVL Family Reference Manual, Rev. 2.48 94 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) Table 2-20. OCPEP Register Field Descriptions Field Description 7 OCPEP7 Over-Current Protection Enable — Activate over-current detector on EVDD1 Refer to Section 2.5.3, “Over-Current Protection on EVDD1” 1 EVDD1 over-current detector enabled 0 EVDD1 over-current detector disabled 5 OCPEP5 Over-Current Protection Enable — Activate over-current detector on PP5 Refer to Section 2.5.4, “Over-Current Protection on PP[5,3,1]” 1 PP5 over-current detector enabled 0 PP5 over-current detector disabled 3 OCPEP3 Over-Current Protection Enable — Activate over-current detector on PP3 Refer to Section 2.5.4, “Over-Current Protection on PP[5,3,1]” 1 PP3 over-current detector enabled 0 PP3 over-current detector disabled 1 OCPEP1 Over-Current Protection Enable — Activate over-current detector on PP1 Refer to Section 2.5.4, “Over-Current Protection on PP[5,3,1]” 1 PP1 over-current detector enabled 0 PP1 over-current detector disabled 2.3.4.2 Port P Over-Current Interrupt Enable Register (OCIEP) Access: User read/write1 Address 0x02FA 7 R W Reset OCIEP7 0 6 0 0 5 OCIEP5 0 4 0 3 OCIEP3 0 0 2 0 0 1 OCIEP1 0 0 0 0 Figure 2-24. Port P Over-Current Interrupt Enable Register 1 Read: Anytime Write: Anytime Table 2-21. Port P Over-Current Interrupt Enable Register Field Description 7 OCIEP7 Over-Current Interrupt Enable — This bit enables or disables the over-current interrupt on EVDD1. 1 EVDD1 over-current interrupt enabled 0 EVDD1 over-current interrupt disabled (interrupt flag masked) 5 OCIEP5 Over-Current Interrupt Enable — This bit enables or disables the over-current interrupt on PP5. 1 PP5 over-current interrupt enabled 0 PP5 over-current interrupt disabled (interrupt flag masked) MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 95 Port Integration Module (S12ZVLPIMV2) Table 2-21. Port P Over-Current Interrupt Enable Register (continued) Field Description 3 OCIEP3 Over-Current Interrupt Enable — This bit enables or disables the over-current interrupt on PP3. 1 PP3 over-current interrupt enabled 0 PP3 over-current interrupt disabled (interrupt flag masked) 1 OCIEP1 Over-Current Interrupt Enable — This bit enables or disables the over-current interrupt on PP1. 1 PP1 over-current interrupt enabled 0 PP1 over-current interrupt disabled (interrupt flag masked) 2.3.4.3 Port P Over-Current Interrupt Flag Register (OCIFP) Access: User read/write1 Address 0x02FB 7 R W Reset OCIFP7 0 6 0 0 5 OCIFP5 0 4 0 0 3 OCIFP3 0 2 0 0 1 OCIFP1 0 0 0 0 Figure 2-25. Port P Over-Current Interrupt Flag Register 1 Read: Anytime Write: Anytime, write 1 to clear Table 2-22. Port P Over-Current Interrupt Flag Register Field Description 7 OCIFP7 Over-Current Interrupt Flag — This flag asserts if an over-current condition is detected on EVDD1 (Section 2.4.4.3, “Over-Current Interrupt”). Writing a logic “1’ to the corresponding bit clears the flag. 1 EVDD1 over-current event occurred 0 No EVDD1 over-current event occurred 5 OCIFP5 Over-Current Interrupt Flag — This flag asserts if an over-current condition is detected on PP5 (Section 2.4.4.3, “Over-Current Interrupt”). Writing a logic “1’ to the corresponding bit clears the flag. 1 PP5 over-current event occurred 0 No PP5 over-current event occurred 3 OCIFP3 Over-Current Interrupt Flag — This flag asserts if an over-current condition is detected on PP3 (Section 2.4.4.3, “Over-Current Interrupt”). Writing a logic “1’ to the corresponding bit clears the flag. 1 PP3 over-current event occurred 0 No PP3 over-current event occurred 1 OCIFP1 Over-Current Interrupt Flag — This flag asserts if an over-current condition is detected on PP1 (Section 2.4.4.3, “Over-Current Interrupt”). Writing a logic “1’ to the corresponding bit clears the flag. 1 PP1 over-current event occurred 0 No PP1 over-current event occurred MC912ZVL Family Reference Manual, Rev. 2.48 96 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) 2.3.4.4 Port L Input Register (PTIL) Access: User read only1 Address 0x0331 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PTIL0 0 0 0 0 0 0 0 0 W Reset Figure 2-26. Port L Input Register (PTIL) 1 Read: Anytime Write: Never Table 2-23. PTIL - Register Field Descriptions 1 Field Description 0 PTIL Port Input Data Register Port L — A read returns the synchronized input state if the associated pin is used in digital mode, that is the related DIENL bit is set to 1 and the pin is not used in analog mode (PTAL[PTAENL]=0). See Section 2.3.4.6, “Port L Analog Access Register (PTAL)”. A one is read in any other case1. Refer to PTTEL bit description in Section 2.3.4.6, “Port L Analog Access Register (PTAL) for an override condition. 2.3.4.5 Port L Digital Input Enable Register (DIENL) Access: User read/write1 Address 0x33C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 DIENL0 0 Figure 2-27. Port L Digital Input Enable Register (DIENL) 1 Read: Anytime Write: Anytime Table 2-24. DIENL Register Field Descriptions 1 Field Description 0 DIENL Digital Input Enable Port L — Input buffer control This bit controls the HVI digital input function. If set to 1 the input buffers are enabled and the pin can be used with the digital function. If the analog input function is enabled (PTAL[PTAENL]=1) the input buffer of the selected HVI pin is forced off1 in run mode and is released to be active in stop mode only if DIENL=1. 1 Associated pin digital input is enabled if not used as analog input in run mode1 0 Associated pin digital input is disabled1 Refer to PTTEL bit description in Section 2.3.4.6, “Port L Analog Access Register (PTAL) for an override condition. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 97 Port Integration Module (S12ZVLPIMV2) 2.3.4.6 Port L Analog Access Register (PTAL) Access: User read/write1 Address 0x033D R W Reset 7 6 5 4 3 PTTEL PTPSL PTABYPL PTADIRL PTAENL 0 0 0 0 0 2 1 0 0 0 0 0 0 0 Figure 2-28. Port L Analog Access Register (PTAL) 1 Read: Anytime Write: Anytime Table 2-25. PTAL Register Field Descriptions Field Description 7 PTTEL Port L Test Enable — This bit forces the input buffer of the HVI pin to be active while using the analog function to support open input detection in run mode. Refer to Section 2.5.5, “Open Input Detection on HVI”). In stop mode this bit has no effect. Note: In direct input connection (PTAL[PTADIRL]=1) the digital input buffer is not enabled. 1 Input buffer enabled when used with analog function and not in direct mode (PTAL[PTADIRL]=0) 0 Input buffer disabled when used with analog function 6 PTPSL Port L Pull Select — This bit selects a pull device on the HVI pin in analog mode for open input detection. By default a pull-down device is active as part of the input voltage divider. If set to 1 and PTTEL=1 and not in stop mode a pull-up to a level close to VDDX takes effect and overrides the weak pull-down device. Refer to Section 2.5.5, “Open Input Detection on HVI”). 1 Pull-up enabled 0 Pull-down enabled 5 PTABYPL Port L ADC connection Bypass — This bit bypasses and powers down the impedance converter stage in the signal path from the analog input pin to the ADC channel input. This bit takes effect only if using direct input connection to the ADC channel (PTADIRL=1). 1 Bypass impedance converter in ADC channel signal path 0 Use impedance converter in ADC channel signal path 4 PTADIRL Port L ADC Direct connection — This bit connects the analog input signal directly to the ADC channel bypassing the voltage divider. This bit takes effect only in analog mode (PTAENL=1). 1 Input pin directly connected to ADC channel 0 Input voltage divider active on analog input to ADC channel 3 PTAENL Port L ADC connection Enable — This bit enables the analog signal link an HVI pin to an ADC channel. If set to 1 the analog input function takes precedence over the digital input in run mode by forcing off the input buffers if not overridden by PTTEL=1. Note: When enabling the resistor paths to ground by setting PTAL[PTAENL]=1, a settling time of tUNC_HVI + two bus cycles must be considered to let internal nodes be loaded with correct values. 1 PL0 is connected to ADC 0 PL0 is not connected to ADC MC912ZVL Family Reference Manual, Rev. 2.48 98 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) 2.3.4.7 Port L Input Divider Ratio Selection Register (PIRL) Access: User read/write1 Address 0x033E R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 1 PIRL0[1:0] W Reset 0 0 0 Figure 2-29. Port L Input Divider Ratio Selection Register (PIRL) 1 Read: Anytime Write: Anytime Table 2-26. PIRL Register Field Descriptions Field Description 10 PIRL0 Port L Input Divider Ratio Select — These bits select one of three voltage divider ratios for the associated high-voltage input pin in analog mode. 1x Ratio12_HVI selected 01 RatioL_HVI selected 00 RatioH_HVI selected 2.4 2.4.1 Functional Description General Each pin except BKGD can act as general-purpose I/O. In addition each pin can act as an output or input of a peripheral module. 2.4.2 Registers Table 2-27 lists the implemented configuration bits which are available on each port. These registers except the pin input registers can be written at any time, however a specific configuration might not become active. For example a pull-up device does not become active while the port is used as a push-pull output. Unimplemented bits read zero. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 99 Port Integration Module (S12ZVLPIMV2) Table 2-27. Bit Indices of Implemented Register Bits per Port Port Data Register Port Input Register Data Direction Register Pull Device Enable Register Polarity Select Register Port Interrupt Enable Register Port Interrupt Flag Register Digital Input Enable Register Port PT PTI DDR PER PPS PIE PIF DIE E 1-0 1-0 1-0 1-0 1-0 - - - - - ADH 1-0 1-0 1-0 1-0 1-0 1-0 1-0 1-0 - - Reduced Wired-Or Drive Mode Register Register RDR WOM ADL 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 - - T 7-0 7-0 7-0 7-0 7-0 - - - - - S 3-0 3-0 3-0 3-0 3-0 3-0 3-0 - - 3-0 P 7-0 7-0 7-0 7-0 7-0 7-0 7-0 - 7,5,3,1 - J 1-0 1-0 1-0 1-0 1-0 - - - - 1-0 L - 0 - - 0 0 0 0 - - 2.4.3 Pin I/O Control Figure 2-30 illustrates the data paths to and from an I/O pin. Input and output data can always be read via the input register (PTIx, Section 2.3.3.2, “Port Input Register”) independent if the pin is used as general-purpose I/O or with a shared peripheral function. If the pin is configured as input (DDRx=0, Section 2.3.3.3, “Data Direction Register”), the pin state can also be read through the data register (PTx, Section 2.3.3.1, “Port Data Register”). PTIx synch. 0 1 PTx 0 PIN 1 DDRx 0 1 data out Periph. Module output enable port enable data in Figure 2-30. Illustration of I/O pin functionality The general-purpose data direction configuration can be overruled by an enabled peripheral function shared on the same pin (Table 2-28). If more than one peripheral function is available and enabled at the MC912ZVL Family Reference Manual, Rev. 2.48 100 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) same time, the highest ranked module according the predefined priority scheme in Table 2-1 will take precedence on the pin. Table 2-28 shows the effect of enabled peripheral features on I/O state and enabled pull devices. Table 2-28. Effect of Enabled Features Enabled Feature1 CPMU OSC Effect on I/O state Related Signal(s) EXTAL, XTAL Effect on enabled pull device CPMU takes control Forced off TIMx output compare IOCx_y Forced output Forced off TIMx input capture IOCx_y None2 None3 SPI0 MISO0, MOSI0, SCK0, SS0 Controlled input/output Forced off if output SCIx transmitter TXDx Forced output Forced off SCIx receiver RXDx Forced input None3 IIC0 SDA0, SCL0 Forced open-drain Pull-down forced off S12ZDBG DBGEEV None2 None3 PWM channel PWMx Forced output Forced off ADC0 ANx None2 4 None3 ACMP0_0, ACMP0_1 None2 4 None3 ACMPO0 Forced output Forced off AMPP, AMPM None2 4 None3 AMP Forced analog output, digital output forced off Forced off PGA PGA_IN0, PGA_IN1, PGA_REF None2 4 None3 IRQ IRQ Forced input None3 XIRQ XIRQ Forced input None3 MSCAN0 TXCAN0 Forced output Forced off RXCAN0 Forced input Pull-down forced off LPTXD0 Forced input None3 LPRXD0 Forced output Forced off VRH, VRL ACMP DAC LINPHY0 1 If applicable the appropriate routing configuration must be set for the signals to take effect on the pins. DDR maintains control 3 PER/PPS maintain control 4 To use the digital input function the related bit in Digital Input Enable Register (DIENADx) must be set to logic level “1”. 2 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 101 Port Integration Module (S12ZVLPIMV2) 2.4.4 Interrupts This section describes the interrupts generated by the PIM and their individual sources. Vector addresses and interrupt priorities are defined at MCU level. Table 2-29. PIM Interrupt Sources Module Interrupt Sources 2.4.4.1 Local Enable XIRQ None IRQ IRQCR[IRQEN] Port AD pin interrupt PIEADH[PIEADL1:PIEADH0] PIEADL[PIEADL7:PIEADL0] Port S pin interrupt PIES[PIES3:PIES0] Port P pin interrupt PIEP[PIEP7:PIEP0] Port L pin interrupt PIEL[PIEL0] Port P over-current interrupt OCIEP[OCIEP7,OCIEP5,OCIEP3,OCIEP1] XIRQ, IRQ Interrupts The XIRQ pin allows requesting non-maskable interrupts after reset initialization. During reset, the X bit in the condition code register is set and any interrupts are masked until software enables them. The IRQ pin allows requesting asynchronous interrupts. The interrupt input is disabled out of reset. To enable the interrupt the IRQCR[IRQEN] bit must be set and the I bit cleared in the condition code register. The interrupt can be configured for level-sensitive or falling-edge-sensitive triggering. If IRQCR[IRQEN] is cleared while an interrupt is pending, the request will de-assert. Both interrupts are capable to wake-up the device from stop mode. Means for glitch filtering are not provided on these pins. 2.4.4.2 Pin interrupts and Key-Wakeup (KWU) Ports AD, S, P and L offer pin interrupt and key-wakeup capability. The related interrupt enable (PIE) as well as the sensitivity to rising or falling edges (PPS) can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs. An interrupt is generated when a bit in the port interrupt flag (PIF) and its corresponding port interrupt enable (PIE) are both set. The pin interrupt feature is also capable to wake up the CPU when it is in stop or wait mode (key-wakeup). A digital filter on each pin prevents short pulses from generating an interrupt. A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level. Else the sampling logic is restarted. In run and wait mode the filters are continuously clocked by the bus clock. Pulses with a duration of tPULSE < nP_MASK/fbus are assuredly filtered out while pulses with a duration of tPULSE > nP_PASS/fbus guarantee a pin interrupt. MC912ZVL Family Reference Manual, Rev. 2.48 102 NXP Semiconductors Port Integration Module (S12ZVLPIMV2) In stop mode the filter clock is generated by an RC-oscillator. The minimum pulse length varies over process conditions, temperature and voltage (Figure 2-31). Pulses with a duration of tPULSE < tP_MASK are assuredly filtered out while pulses with a duration of tPULSE > tP_PASS guarantee a wakeup event. Please refer to the appendix table “Pin Timing Characteristics” for pulse length limits. To maximize current saving the RC oscillator is active only if the following condition is true on any individual pin: Sample count VACMPM) before the initialization delay has passed, a flag will be set immediately after the delay if rising edge is selected as flag setting event. Similarly the ACMPS[ACIF] flag will also be set when disabling the ACMP, then re-enabling it with the inputs changing to produce an opposite result to the hold state before the end of the initialization delay. The unsynchronized comparator output can be connected to the synchronized timer input capture channel defined at SoC-level (see Figure 3-1). This feature can be used to generate time stamps and timer interrupts on ACMP events. The comparator output signal can be read at register bit location ACMPS[ACO]. The condition causing the interrupt flag to assert is selected with ACMPC0[ACMOD]. This includes any edge configuration, that is rising, or falling, or rising and falling edges of the comparator output. Also flag setting can be disabled. An interrupt will be generated if the interrupt enable bit (ACMPC2[ACIE]) and the interrupt flag (ACMPS[ACIF]) are both set. ACMPS[ACIF] is cleared by writing a 1. The comparator output signal ACMPO can be driven out on an external pin by setting ACMPC0[ACOPE] and optionally inverted by setting ACMPC0[ACOPS]. One out of four hysteresis levels can be selected by setting ACMPC0[ACHYS]. The input delay of the ACMP_0 and ACMP_1 input depends on the selected filter characteristic by ACMPC0[ACDLY]. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 115 5V Analog Comparator (ACMPV2) 3.8 Interrupts Table 3-6 shows the interrupt generated by the ACMP. Table 3-6. ACMP Interrupt Sources Module Interrupt Sources ACMP interrupt Local Enable ACMPC2[ACIE] MC912ZVL Family Reference Manual, Rev. 2.48 116 NXP Semiconductors Chapter 4 Memory Mapping Control (S12ZMMCV1) Table 4-1. Revision History Revision Number Revision Date V01.06 12 Feb 2013 V01.07 3 May 2013 4.1 Sections Affected Figure 4-8 4.3.2.2/4-122 Description of Changes • Changed “KByte:to “KB” • Corrected the description of the MMCECH/L register • • Fixed typos • Removed PTU references Introduction The S12ZDBG module controls the access to all internal memories and peripherals for the S12ZCPU, and the S12ZBDC module. It also provides dirct memory access for the ADC module. The S12ZDBG determines the address mapping of the on-chip resources, regulates access priorities and enforces memory protection. Figure 4-1 shows a block diagram of the S12ZDBG module. MC9S12ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 117 Memory Mapping Control (S12ZMMCV1) 4.1.1 Glossary Table 4-2. Glossary Of Terms Term Definition MCU Microcontroller Unit CPU S12Z Central Processing Unit BDC S12Z Background Debug Controller ADC Analog-to-Digital Converter unmapped address range Address space that is not assigned to a memory reserved address Address space that is reserved for future use cases range illegal access Memory access, that is not supported or prohibited by the S12ZDBG, e.g. a data store to NVM access violation Either an illegal access or an uncorrectable ECC error byte 8-bit data word 16-bit data 4.1.2 Overview The S12ZDBG provides access to on-chip memories and peripherals for the S12ZCPU, the S12ZBDC, and the ADC. It arbitrates memory accesses and determines all of the MCU memory maps. Furthermore, the S12ZDBG is responsible for selecting the MCUs functional mode. 4.1.3 • • • Features S12ZDBG mode operation control Memory mapping for S12ZCPU, S12ZBDC, and ADC — Maps peripherals and memories into a 16 MByte address space for the S12ZCPU, the S12ZBDC, and the ADC — Handles simultaneous accesses to different on-chip resources (NVM, RAM, and peripherals) Access violation detection and logging — Triggers S12ZCPU machine exceptions upon detection of illegal memory accesses and uncorrectable ECC errors — Logs the state of the S12ZCPU and the cause of the access error 4.1.4 4.1.4.1 Modes of Operation Chip configuration modes The S12ZDBG determines the chip configuration mode of the device. It captures the state of the MODC pin at reset and provides the ability to switch from special-single chip mode to normal single chip-mode. MC912ZVL Family Reference Manual, Rev. 2.48 118 NXP Semiconductors Memory Mapping Control (S12ZMMCV1) 4.1.4.2 Power modes The S12ZDBG module is only active in run and wait mode.There is no bus activity in stop mode. 4.1.5 Block Diagram e Run Mode Controller S12ZCPU S12ZBDC ADC Memory Protection Register Block Crossbar Switch Program Flash EEPROM RAM Peripherals Figure 4-1. S12ZDBG Block Diagram 4.2 External Signal Description The S12ZDBG uses two external pins to determine the devices operating mode: RESET and MODC (Table 4-3) See device overview for the mapping of these signals to device pins. Table 4-3. External System Pins Associated With S12ZDBG Pin Name 4.3 4.3.1 Description RESET External reset signal. The RESET signal is active low. MODC This input is captured in bit MODC of the MODE register when the external RESET pin deasserts. Memory Map and Register Definition Memory Map A summary of the registers associated with the MMC block is shown in Figure 4-2. Detailed descriptions of the registers and bits are given in the subsections that follow. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 119 Memory Mapping Control (S12ZMMCV1) Address Name 0x0070 MODE Bit 7 R W 0x00710x007F Reserved 0x0080 MMCECH R MODC 0 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R ITR[3:0] TGT[3:0] ACC[3:0] ERR[3:0] W 0x0081 MMCECL R W 0x0082 MMCCCRH R CPUU 0 0 0 0 0 0 0 0 CPUX 0 CPUI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0x0083 MMCCCRL R W 0x0084 Reserved R W 0x0085 MMCPCH R CPUPC[23:16] W 0x0086 MMCPCM R CPUPC[15:8] W 0x0087 MMCPCL R CPUPC[7:0] W 0x00880x00FF Reserved R 0 0 0 0 W = Unimplemented or Reserved Figure 4-2. S12ZDBG Register Summary 4.3.2 Register Descriptions This section consists of the S12ZDBG control and status register descriptions in address order. MC912ZVL Family Reference Manual, Rev. 2.48 120 NXP Semiconductors Memory Mapping Control (S12ZMMCV1) 4.3.2.1 Mode Register (MODE) Address: 0x0070 7 R W Reset MODC MODC1 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1. External signal (see Table 4-3). = Unimplemented or Reserved Figure 4-3. Mode Register (MODE) Read: Anytime. Write: Only if a transition is allowed (see Figure 4-4). The MODE register determines the operating mode of the MCU. CAUTION Table 4-4. MODE Field Descriptions Field Description 7 MODC Mode Select Bit — This bit determines the current operating mode of the MCU. Its reset value is captured from the MODC pin at the rising edge of the RESET pin. Figure 4-4 illustrates the only valid mode transition from special single-chip mode to normal single chip mode. Reset with MODC pin = 1 Reset with MODC pin = 0 Normal Single-Chip Mode (NS) Special Single-Chip Mode (SS) write access to MODE: 1  MODC bit Figure 4-4. Mode Transition Diagram MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 121 Memory Mapping Control (S12ZMMCV1) 4.3.2.2 Error Code Register (MMCECH, MMCECL) Address: 0x0080 (MMCECH) 7 6 R 4 3 2 ITR[3:0] W Reset 5 0 1 0 TGT[3:0] 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 Address: 0x0081 (MMCECL) 7 R ACC[3:0] W Reset 0 0 ERR[3:0] 0 0 0 0 Figure 4-5. Error Code Register (MMCEC) Read: Anytime Write: Write of 0xFFFF to MMCECH:MMCECL resets both registers to 0x0000 Table 4-5. MMCECH and MMCECL Field Descriptions Field Description 7-4 (MMCECH) ITR[3:0] Initiator Field — The ITR[3:0] bits capture the initiator which caused the access violation. The initiator is captured in form of a 4 bit value which is assigned as follows: 0:none (no error condition detected) 1:S12ZCPU 2:reserved 3:ADC 4-15: reserved 3-0 (MMCECH) TGT[3:0] Target Field — The TGT[3:0] bits capture the target of the faulty access. The target is captured in form of a 4 bit value which is assigned as follows: 0:none 1:register space 2:RAM 3:EEPROM 4:program flash 5:IFR 6-15: reserved MC912ZVL Family Reference Manual, Rev. 2.48 122 NXP Semiconductors Memory Mapping Control (S12ZMMCV1) Field Description 7-4 (MMCECL) ACC[3:0] Access Type Field — The ACC[3:0] bits capture the type of memory access, which caused the access violation. The access type is captured in form of a 4 bit value which is assigned as follows: 0:none (no error condition detected) 1:opcode fetch 2:vector fetch 3:data load 4:data store 5-15: reserved 3-0 (MMCECL) ERR[3:0] Error Type Field — The EC[3:0] bits capture the type of the access violation. The type is captured in form of a 4 bit value which is assigned as follows: 0:none (no error condition detected) 1:access to an illegal address 2:uncorrectable ECC error 3-15:reserved The MMCEC register captures debug information about access violations. It is set to a non-zero value if a S12ZCPU access violation or an uncorrectable ECC error has occurred. At the same time this register is set to a non-zero value, access information is captured in the MMCPCn and MMCCCRn registers. The MMCECn, the MMCPCn and the MMCCCRn registers are not updated if the MMCECn registers contain a non-zero value. The MMCECn registers are cleared by writing the value 0xFFFF. 4.3.2.3 Captured S12ZCPU Condition Code Register (MMCCCRH, MMCCCRL) Address: 0x0082 (MMCCCRH) R 7 6 5 4 3 2 1 0 CPUU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Address: 0x0083 (MMCCCRL) R 7 6 5 4 3 2 1 0 0 CPUX 0 CPUI 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 4-6. Captured S12ZCPU Condition Code Register (MMCCCRH, MMCCCRL) Read: Anytime Write: Never MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 123 Memory Mapping Control (S12ZMMCV1) Table 4-6. MMCCCRH and MMCCCRL Field Descriptions Field Description 7 (MMCCCRH) CPUU S12ZCPU User State Flag — This bit shows the state of the user/supervisor mode bit in the S12ZCPU’s CCR at the time the access violation has occurred. The S12ZCPU user state flag is read-only; it will be automatically updated when the next error condition is flagged through the MMCEC register. This bit is undefined if the error code registers (MMCECn) are cleared. 6 (MMCCCRL) CPUX S12ZCPU X-Interrupt Mask— This bit shows the state of the X-interrupt mask in the S12ZCPU’s CCR at the time the access violation has occurred. The S12ZCPU X-interrupt mask is read-only; it will be automatically updated when the next error condition is flagged through the MMCEC register. This bit is undefined if the error code registers (MMCECn) are cleared. 4 (MMCCCRL) CPUI S12ZCPU I-Interrupt Mask— This bit shows the state of the I-interrupt mask in the CPU’s CCR at the time the access violation has occurred. The S12ZCPU I-interrupt mask is read-only; it will be automatically updated when the next error condition is flagged through the MMCEC register. This bit is undefined if the error code registers (MMCECn) are cleared. 4.3.2.4 Captured S12ZCPU Program Counter (MMCPCH, MMCPCM, MMCPCL) Address: 0x0085 (MMCPCH) 7 6 5 R 4 3 2 1 0 CPUPC[23:16] W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 3 2 1 0 0 0 0 0 Address: 0x0086 (MMCPCM) 7 R CPUPC[15:8] W Reset 0 0 0 0 6 5 4 Address: 0x0087 (MMCPCL) 7 R CPUPC[7:0] W Reset 0 0 0 0 Figure 4-7. Captured S12ZCPU Program Counter (MMCPCH, MMCPCM, MMCPCL) Read: Anytime Write: Never MC912ZVL Family Reference Manual, Rev. 2.48 124 NXP Semiconductors Memory Mapping Control (S12ZMMCV1) Table 4-7. MMCPCH, MMCPCM, and MMCPCL Field Descriptions Field Description 7–0 (MMCPCH) S12ZCPU Program Counter Value— The CPUPC[23:0] stores the CPU’s program counter value at the time 7–0 (MMCPCM) the access violation occurred. CPUPC[23:0] always points to the instruction which triggered the violation. These 7–0 (MMCPCL) bits are undefined if the error code registers (MMCECn) are cleared. CPUPC[23:0] 4.4 Functional Description This section provides a complete functional description of the S12ZDBG module. 4.4.1 Global Memory Map The S12ZDBG maps all on-chip resources into an 16MB address space, the global memory map. The exact resource mapping is shown in Figure 4-8. The global address space is used by the S12ZCPU, ADC, and the S12ZBDC module. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 125 Memory Mapping Control (S12ZMMCV1) Register Space 4 KB 0x00_0000 0x00_1000 RAM max. 1 MByte - 4 KB 0x10_0000 EEPROM max. 1 MByte - 48 KB Reserved 512 Byte 0x1F_4000 Reserved (read only) 6 KBKB 0x1F_8000 NVM IFR 256 Byte 0x1F_C000 0x20_0000 Unmapped 6 MByte 0x80_0000 Program NVM max. 8 MByte Unmapped address range Low address aligned High address aligned 0xFF_FFFF Figure 4-8. Global Memory Map MC912ZVL Family Reference Manual, Rev. 2.48 126 NXP Semiconductors Memory Mapping Control (S12ZMMCV1) 4.4.2 Illegal Accesses The S12ZDBG module monitors all memory traffic for illegal accesses. See Table 4-8 for a complete list of all illegal accesses. Table 4-8. Illegal memory accesses Register space RAM EEPROM Reserved Space Reserved Read-only Space NVM IFR Program NVM Unmapped Space 1 S12ZCPU S12ZBDC ADC Read access ok ok illegal access Write access ok ok illegal access Code execution illegal access Read access ok ok ok Write access ok ok ok Code execution ok Read access ok1 ok1 ok1 Write access illegal access illegal access illegal access Code execution ok1 Read access ok ok illegal access Write access only permitted in SS mode ok illegal access Code execution illegal access Read access ok ok illegal access Write access illegal access illegal access illegal access Code execution illegal access Read access ok1 ok1 illegal access Write access illegal access illegal access illegal access Code execution illegal access Read access ok1 ok1 ok1 Write access illegal access illegal access illegal access Code execution ok1 Read access illegal access illegal access illegal access Write access illegal access illegal access illegal access Code execution illegal access Unsupported NVM accesses during NVM command execution (“collisions”), are treated as illegal accesses. Illegal accesses are reported in several ways: • All illegal accesses performed by the S12ZCPU trigger machine exceptions. • All illegal accesses performed through the S12ZBDC interface, are captured in the ILLACC bit of the BDCCSRL register. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 127 Memory Mapping Control (S12ZMMCV1) • All illegal accesses performed by the ADC module trigger error interrupts. See ADC section for details. NOTE Illegal accesses caused by S12ZCPU opcode prefetches will also trigger machine exceptions, even if those opcodes might not be executed in the program flow. To avoid these machine exceptions, S12ZCPU instructions must not be executed from the last (high addresses) 8 bytes of RAM, EEPROM, and Flash. 4.4.3 Uncorrectable ECC Faults RAM and flash use error correction codes (ECC) to detect and correct memory corruption. Each uncorrectable memory corruption, which is detected during a S12ZCPU or ADC access triggers a machine exception. Uncorrectable memory corruptions which are detected during a S12ZBDC access, are captured in the RAMWF or the RDINV bit of the BDCCSRL register. MC912ZVL Family Reference Manual, Rev. 2.48 128 NXP Semiconductors Chapter 5 Background Debug Controller (S12ZBDCV2) Table 5-1. Revision History Revision Number Revision Date Sections Affected V2.04 03.Dec.2012 Section 5.1.3.3, “Low-Power Modes V2.05 22.Jan.2013 Section 5.3.2.2, Improved NORESP description and added STEP1/ Wait mode dependency “BDC Control Status Register Low (BDCCSRL) V2.06 22.Mar.2013 Section 5.3.2.2, Improved NORESP description of STEP1/ Wait mode dependency “BDC Control Status Register Low (BDCCSRL) V2.07 11.Apr.2013 Section 5.1.3.3.1, Improved STOP and BACKGROUND interdepency description “Stop Mode V2.08 31.May.2013 Section 5.4.4.4, Removed misleading WAIT and BACKGROUND interdepency description “BACKGROUND Added subsection dedicated to Long-ACK Section 5.4.7.1, “Long-ACK Hardware Handshake Protocol V2.09 29.Aug.2013 Section 5.4.4.12, Noted that READ_DBGTB is only available for devices featuring a trace “READ_DBGTB buffer. V2.10 21.Oct.2013 Section 5.1.3.3.2, Improved description of NORESP dependence on WAIT and BACKROUND “Wait Mode V2.11 02.Feb.2015 Section 5.1.3.3.1, Corrected name of clock that can stay active in Stop mode “Stop Mode Section 5.3.2, “Register Descriptions 5.1 Description of Changes Included BACKGROUND/ Stop mode dependency Introduction The background debug controller (BDC) is a single-wire, background debug system implemented in on-chip hardware for minimal CPU intervention. The device BKGD pin interfaces directly to the BDC. The S12ZBDC maintains the standard S12 serial interface protocol but introduces an enhanced handshake protocol and enhanced BDC command set to support the linear instruction set family of S12Z devices and offer easier, more flexible internal resource access over the BDC serial interface. MC9S12ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 129 Background Debug Controller (S12ZBDCV2) 5.1.1 Glossary Table 5-2. Glossary Of Terms Term Definition DBG On chip Debug Module BDM Active Background Debug Mode CPU S12Z CPU SSC Special Single Chip Mode (device operating mode NSC Normal Single Chip Mode (device operating mode) BDCSI Background Debug Controller Serial Interface. This refers to the single pin BKGD serial interface. EWAIT Optional S12 feature which allows external devices to delay external accesses until deassertion of EWAIT 5.1.2 Features The BDC includes these distinctive features: • Single-wire communication with host development system • SYNC command to determine communication rate • Genuine non-intrusive handshake protocol • Enhanced handshake protocol for error detection and stop mode recognition • Active out of reset in special single chip mode • Most commands not requiring active BDM, for minimal CPU intervention • Full global memory map access without paging • Simple flash mass erase capability 5.1.3 Modes of Operation S12 devices feature power modes (run, wait, and stop) and operating modes (normal single chip, special single chip). Furthermore, the operation of the BDC is dependent on the device security status. 5.1.3.1 BDC Modes The BDC features module specific modes, namely disabled, enabled and active. These modes are dependent on the device security and operating mode. In active BDM the CPU ceases execution, to allow BDC system access to all internal resources including CPU internal registers. 5.1.3.2 Security and Operating mode Dependency In device run mode the BDC dependency is as follows • Normal modes, unsecure device General BDC operation available. The BDC is disabled out of reset. MC912ZVL Family Reference Manual, Rev. 2.48 130 NXP Semiconductors Background Debug Controller (S12ZBDCV2) • • • Normal modes, secure device BDC disabled. No BDC access possible. Special single chip mode, unsecure BDM active out of reset. All BDC commands are available. Special single chip mode, secure BDM active out of reset. Restricted command set available. When operating in secure mode, BDC operation is restricted to allow checking and clearing security by mass erasing the on-chip flash memory. Secure operation prevents BDC access to on-chip memory other than mass erase. The BDC command set is restricted to those commands classified as Always-available. 5.1.3.3 5.1.3.3.1 Low-Power Modes Stop Mode The execution of the CPU STOP instruction leads to stop mode only when all bus masters (CPU, or others, depending on the device) have finished processing. The operation during stop mode depends on the ENBDC and BDCCIS bit settings as summarized in Table 5-3 Table 5-3. BDC STOP Operation Dependencies ENBDC BDCCIS Description Of Operation 0 0 BDC has no effect on STOP mode. 0 1 BDC has no effect on STOP mode. 1 0 Only BDCCLK clock continues 1 1 All clocks continue A disabled BDC has no influence on stop mode operation. In this case the BDCSI clock is disabled in stop mode thus it is not possible to enable the BDC from within stop mode. STOP Mode With BDC Enabled And BDCCIS Clear If the BDC is enabled and BDCCIS is clear, then the BDC prevents the BDCCLK clock (Figure 5-5) from being disabled in stop mode. This allows BDC communication to continue throughout stop mode in order to access the BDCCSR register. All other device level clock signals are disabled on entering stop mode. NOTE This is intended for application debugging, not for fast flash programming. Thus the CLKSW bit must be clear to map the BDCSI to BDCCLK. With the BDC enabled, an internal acknowledge delays stop mode entry and exit by 2 BDCSI clock + 2 bus clock cycles. If no other module delays stop mode entry and exit, then these additional clock cycles represent a difference between the debug and not debug cases. Furthermore if a BDC internal access is being executed when the device is entering stop mode, then the stop mode entry is delayed until the internal access is complete (typically for 1 bus clock cycle). MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 131 Background Debug Controller (S12ZBDCV2) Accesses to the internal memory map are not possible when the internal device clocks are disabled. Thus attempted accesses to memory mapped resources are suppressed and the NORESP flag is set. Resources can be accessed again by the next command received following exit from Stop mode. A BACKGROUND command issued whilst in stop mode remains pending internally until the device leaves stop mode. This means that subsequent active BDM commands, issued whilst BACKGROUND is pending, set the ILLCMD flag because the device is not yet in active BDM. If ACK handshaking is enabled, then the first ACK, following a stop mode entry is long to indicate a stop exception. The BDC indicates a stop mode occurrence by setting the BDCCSR bit STOP. If the host attempts further communication before the ACK pulse generation then the OVRUN bit is set. STOP Mode With BDC Enabled And BDCCIS Set If the BDC is enabled and BDCCIS is set, then the BDC prevents core clocks being disabled in stop mode. This allows BDC communication, for access of internal memory mapped resources, but not CPU registers, to continue throughout stop mode. A BACKGROUND command issued whilst in stop mode remains pending internally until the device leaves stop mode. This means that subsequent active BDM commands, issued whilst BACKGROUND is pending, set the ILLCMD flag because the device is not yet in active BDM. If ACK handshaking is enabled, then the first ACK, following a stop mode entry is long to indicate a stop exception. The BDC indicates a stop mode occurrence by setting the BDCCSR bit STOP. If the host attempts further communication before the ACK pulse generation then the OVRUN bit is set. 5.1.3.3.2 Wait Mode The device enters wait mode when the CPU starts to execute the WAI instruction. The second part of the WAI instruction (return from wait mode) can only be performed when an interrupt occurs. Thus on entering wait mode the CPU is in the middle of the WAI instruction and cannot permit access to CPU internal resources, nor allow entry to active BDM. Thus only commands classified as Non-Intrusive or Always-Available are possible in wait mode. On entering wait mode, the WAIT flag in BDCCSR is set. If the ACK handshake protocol is enabled then the first ACK generated after WAIT has been set is a long-ACK pulse. Thus the host can recognize a wait mode occurrence. The WAIT flag remains set and cannot be cleared whilst the device remains in wait mode. After the device leaves wait mode the WAIT flag can be cleared by writing a “1” to it. A BACKGROUND command issued whilst in wait mode sets the NORESP bit and the BDM active request remains pending internally until the CPU leaves wait mode due to an interrupt. The device then enters BDM with the PC pointing to the address of the first instruction of the ISR. With ACK disabled, further Non-Intrusive or Always-Available commands are possible, in this pending state, but attempted Active-Background commands set NORESP and ILLCMD because the BDC is not in active BDM state. With ACK enabled, if the host attempts further communication before the ACK pulse generation then the OVRUN bit is set. MC912ZVL Family Reference Manual, Rev. 2.48 132 NXP Semiconductors Background Debug Controller (S12ZBDCV2) Similarly the STEP1 command issued from a WAI instruction cannot be completed by the CPU until the CPU leaves wait mode due to an interrupt. The first STEP1 into wait mode sets the BDCCSR WAIT bit. If the part is still in Wait mode and a further STEP1 is carried out then the NORESP and ILLCMD bits are set because the device is no longer in active BDM for the duration of WAI execution. 5.1.4 Block Diagram A block diagram of the BDC is shown in Figure 5-1. HOST SYSTEM BKGD SERIAL INTERFACE CONTROL AND SHIFT REGISTER CLOCK DOMAIN CONTROL INSTRUCTION DECODE AND FSM BDCSI CORE CLOCK ADDRESS BUS INTERFACE AND CONTROL LOGIC BDCCSR REGISTER AND DATAPATH CONTROL DATA BUS CONTROL CPU CONTROL ERASE FLASH FLASH ERASED FLASH SECURE Figure 5-1. BDC Block Diagram 5.2 External Signal Description A single-wire interface pin (BKGD) is used to communicate with the BDC system. During reset, this pin is a device mode select input. After reset, this pin becomes the dedicated serial interface pin for the BDC. BKGD is a pseudo-open-drain pin with an on-chip pull-up. Unlike typical open-drain pins, the external RC time constant on this pin due to external capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively driven speed-up pulses to force rapid rise times on this pin without risking harmful drive level conflicts. Refer to Section 5.4.6, “BDC Serial Interface” for more details. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 133 Background Debug Controller (S12ZBDCV2) 5.3 Memory Map and Register Definition 5.3.1 Module Memory Map Table 5-4 shows the BDC memory map. Table 5-4. BDC Memory Map 5.3.2 Global Address Module Size (Bytes) Not Applicable BDC registers 2 Register Descriptions The BDC registers are shown in Figure 5-2. Registers are accessed only by host-driven communications to the BDC hardware using READ_BDCCSR and WRITE_BDCCSR commands. They are not accessible in the device memory map. Global Address Register Name Bit 7 Not Applicable BDCCSRH R Not Applicable BDCCSRL W R W ENBDC WAIT 6 BDMACT STOP 5 4 0 BDCCIS RAMWF OVRUN = Unimplemented, Reserved 3 2 STEAL CLKSW NORESP RDINV 0 1 Bit 0 UNSEC ERASE ILLACC ILLCMD = Always read zero Figure 5-2. BDC Register Summary 5.3.2.1 BDC Control Status Register High (BDCCSRH) Register Address: This register is not in the device memory map. It is accessible using BDC inherent addressing commands 7 R W ENBDC 6 BDMACT 5 BDCCIS 4 0 3 2 STEAL CLKSW 1 0 UNSEC ERASE Reset Secure AND SSC-Mode 1 1 0 0 0 0 0 0 Unsecure AND SSC-Mode 1 1 0 0 0 0 1 0 Secure AND NSC-Mode 0 0 0 0 0 0 0 0 Unsecure AND NSC-Mode 0 0 0 0 0 0 1 0 = Unimplemented, Reserved 0 = Always read zero Figure 5-3. BDC Control Status Register High (BDCCSRH) MC912ZVL Family Reference Manual, Rev. 2.48 134 NXP Semiconductors Background Debug Controller (S12ZBDCV2) Read: All modes through BDC operation only. Write: All modes through BDC operation only, when not secured, but subject to the following: — Bits 7,3 and 2 can only be written by WRITE_BDCCSR commands. — Bit 5 can only be written by WRITE_BDCCSR commands when the device is not in stop mode. — Bits 6, 1 and 0 cannot be written. They can only be updated by internal hardware. Table 5-5. BDCCSRH Field Descriptions Field Description 7 ENBDC Enable BDC — This bit controls whether the BDC is enabled or disabled. When enabled, active BDM can be entered and non-intrusive commands can be carried out. When disabled, active BDM is not possible and the valid command set is restricted. Further information is provided in Table 5-7. 0 BDC disabled 1 BDC enabled Note: ENBDC is set out of reset in special single chip mode. 6 BDMACT BDM Active Status — This bit becomes set upon entering active BDM. BDMACT is cleared as part of the active BDM exit sequence. 0 BDM not active 1 BDM active Note: BDMACT is set out of reset in special single chip mode. 5 BDCCIS BDC Continue In Stop — If ENBDC is set then BDCCIS selects the type of BDC operation in stop mode (as shown in Table 5-3). If ENBDC is clear, then the BDC has no effect on stop mode and no BDC communication is possible.If ACK pulse handshaking is enabled, then the first ACK pulse following stop mode entry is a long ACK. This bit cannot be written when the device is in stop mode. 0 Only the BDCCLK clock continues in stop mode 1 All clocks continue in stop mode 3 STEAL Steal enabled with ACK— This bit forces immediate internal accesses with the ACK handshaking protocol enabled. If ACK handshaking is disabled then BDC accesses steal the next bus cycle. 0 If ACK is enabled then BDC accesses await a free cycle, with a timeout of 512 cycles 1 If ACK is enabled then BDC accesses are carried out in the next bus cycle 2 CLKSW Clock Switch — The CLKSW bit controls the BDCSI clock source. This bit is initialized to “0” by each reset and can be written to “1”. Once it has been set, it can only be cleared by a reset. When setting CLKSW a minimum delay of 150 cycles at the initial clock speed must elapse before the next command can be sent. This guarantees that the start of the next BDC command uses the new clock for timing subsequent BDC communications. 0 BDCCLK used as BDCSI clock source 1 Device fast clock used as BDCSI clock source Note: Refer to the device specification to determine which clock connects to the BDCCLK and fast clock inputs. 1 UNSEC Unsecure — If the device is unsecure, the UNSEC bit is set automatically. 0 Device is secure. 1 Device is unsecure. Note: When UNSEC is set, the device is unsecure and the state of the secure bits in the on-chip Flash EEPROM can be changed. 0 ERASE Erase Flash — This bit can only be set by the dedicated ERASE_FLASH command. ERASE is unaffected by write accesses to BDCCSR. ERASE is cleared either when the mass erase sequence is completed, independent of the actual status of the flash array or by a soft reset. Reading this bit indicates the status of the requested mass erase sequence. 0 No flash mass erase sequence pending completion 1 Flash mass erase sequence pending completion. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 135 Background Debug Controller (S12ZBDCV2) 5.3.2.2 BDC Control Status Register Low (BDCCSRL) Register Address: This register is not in the device memory map. It is accessible using BDC inherent addressing commands R W Reset 7 6 5 4 3 2 1 0 WAIT STOP RAMWF OVRUN NORESP RDINV ILLACC ILLCMD 0 0 0 0 0 0 0 0 Figure 5-4. BDC Control Status Register Low (BDCCSRL) Read: BDC access only. Write: Bits [7:5], [3:0] BDC access only, restricted to flag clearing by writing a “1” to the bit position. Write: Bit 4 never. It can only be cleared by a SYNC pulse. If ACK handshaking is enabled then BDC commands with ACK causing a BDCCSRL[3:1] flag setting condition also generate a long ACK pulse. Subsequent commands that are executed correctly generate a normal ACK pulse. Subsequent commands that are not correctly executed generate a long ACK pulse. The first ACK pulse after WAIT or STOP have been set also generates a long ACK. Subsequent ACK pulses are normal, whilst STOP and WAIT remain set. Long ACK pulses are not immediately generated if an overrun condition is caused by the host driving the BKGD pin low whilst a target ACK is pending, because this would conflict with an attempted host transmission following the BKGD edge. When a whole byte has been received following the offending BKGD edge, the OVRUN bit is still set, forcing subsequent ACK pulses to be long. Unimplemented BDC opcodes causing the ILLCMD bit to be set do not generate a long ACK because this could conflict with further transmission from the host. If the ILLCMD is set for another reason, then a long ACK is generated for the current command if it is a BDC command with ACK. Table 5-6. BDCCSRL Field Descriptions Field Description 7 WAIT WAIT Indicator Flag — Indicates that the device entered wait mode. Writing a “1” to this bit whilst in wait mode has no effect. Writing a “1” after exiting wait mode, clears the bit. 0 Device did not enter wait mode 1 Device entered wait mode. 6 STOP STOP Indicator Flag — Indicates that the CPU requested stop mode following a STOP instruction. Writing a “1” to this bit whilst not in stop mode clears the bit. Writing a “1” to this bit whilst in stop mode has no effect. This bit can only be set when the BDC is enabled. 0 Device did not enter stop mode 1 Device entered stop mode. 5 RAMWF RAM Write Fault — Indicates an ECC double fault during a BDC write access to RAM. Writing a “1” to this bit, clears the bit. 0 No RAM write double fault detected. 1 RAM write double fault detected. MC912ZVL Family Reference Manual, Rev. 2.48 136 NXP Semiconductors Background Debug Controller (S12ZBDCV2) Table 5-6. BDCCSRL Field Descriptions (continued) Field Description 4 OVRUN Overrun Flag — Indicates unexpected host activity before command completion. This occurs if a new command is received before the current command completion. With ACK enabled this also occurs if the host drives the BKGD pin low whilst a target ACK pulse is pending To protect internal resources from misinterpreted BDC accesses following an overrun, internal accesses are suppressed until a SYNC clears this bit. A SYNC clears the bit. 0 No overrun detected. 1 Overrun detected when issuing a BDC command. 3 NORESP No Response Flag — Indicates that the BDC internal action or data access did not complete. This occurs in the following scenarios: a) If no free cycle for an access is found within 512 core clock cycles. This could typically happen if a code loop without free cycles is executing with ACK enabled and STEAL clear. b) With ACK disabled or STEAL set, when an internal access is not complete before the host starts data/BDCCSRL retrieval or an internal write access is not complete before the host starts the next BDC command. c) Attempted internal memory or SYNC_PC accesses during STOP mode set NORESP if BDCCIS is clear. In the above cases, on setting NORESP, the BDC aborts the access if permitted. (For devices supporting EWAIT, BDC external accesses with EWAIT assertions, prevent a command from being aborted until EWAIT is deasserted). d) If a BACKGROUND command is issued whilst the device is in wait mode the NORESP bit is set but the command is not aborted. The active BDM request is completed when the device leaves wait mode. Furthermore subsequent CPU register access commands during wait mode set the NORESP bit, should it have been cleared. e) If a command is issued whilst awaiting return from Wait mode. This can happen when using STEP1 to step over a CPU WAI instruction, if the CPU has not returned from Wait mode before the next BDC command is received. f) If STEP1 is issued with the BDC enabled as the device enters Wait mode regardless of the BDMACT state. When NORESP is set a value of 0xEE is returned for each data byte associated with the current access. Writing a “1” to this bit, clears the bit. 0 Internal action or data access completed. 1 Internal action or data access did not complete. 2 RDINV Read Data Invalid Flag — Indicates invalid read data due to an ECC error during a BDC initiated read access. The access returns the actual data read from the location. Writing a “1” to this bit, clears the bit. 0 No invalid read data detected. 1 Invalid data returned during a BDC read access. 1 ILLACC Illegal Access Flag — Indicates an attempted illegal access. This is set in the following cases: When the attempted access addresses unimplemented memory When the access attempts to write to the flash array When a CPU register access is attempted with an invalid CRN (Section 5.4.5.1, “BDC Access Of CPU Registers). Illegal accesses return a value of 0xEE for each data byte Writing a “1” to this bit, clears the bit. 0 No illegal access detected. 1 Illegal BDC access detected. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 137 Background Debug Controller (S12ZBDCV2) Table 5-6. BDCCSRL Field Descriptions (continued) Field Description 0 ILLCMD Illegal Command Flag — Indicates an illegal BDC command. This bit is set in the following cases: When an unimplemented BDC command opcode is received. When a DUMP_MEM{_WS}, FILL_MEM{_WS} or READ_SAME{_WS} is attempted in an illegal sequence. When an active BDM command is received whilst BDM is not active When a non Always-available command is received whilst the BDC is disabled or a flash mass erase is ongoing. When a non Always-available command is received whilst the device is secure Read commands return a value of 0xEE for each data byte Writing a “1” to this bit, clears the bit. 0 No illegal command detected. 1 Illegal BDC command detected. 5.4 5.4.1 Functional Description Security If the device resets with the system secured, the device clears the BDCCSR UNSEC bit. In the secure state BDC access is restricted to the BDCCSR register. A mass erase can be requested using the ERASE_FLASH command. If the mass erase is completed successfully, the device programs the security bits to the unsecure state and sets the BDC UNSEC bit. If the mass erase is unsuccessful, the device remains secure and the UNSEC bit is not set. For more information regarding security, please refer to device specific security information. 5.4.2 Enabling BDC And Entering Active BDM BDM can be activated only after being enabled. BDC is enabled by setting the ENBDC bit in the BDCCSR register, via the single-wire interface, using the command WRITE_BDCCSR. After being enabled, BDM is activated by one of the following1: • The BDC BACKGROUND command • A CPU BGND instruction • The DBG Breakpoint mechanism Alternatively BDM can be activated directly from reset when resetting into Special Single Chip Mode. The BDC is ready for receiving the first command 10 core clock cycles after the deassertion of the internal reset signal. This is delayed relative to the external pin reset as specified in the device reset documentation. On S12Z devices an NVM initialization phase follows reset. During this phase the BDC commands classified as always available are carried out immediately, whereas other BDC commands are subject to delayed response due to the NVM initialization phase. NOTE After resetting into SSC mode, the initial PC address must be supplied by the host using the WRITE_Rn command before issuing the GO command. 1. BDM active immediately out of special single-chip reset. MC912ZVL Family Reference Manual, Rev. 2.48 138 NXP Semiconductors Background Debug Controller (S12ZBDCV2) When BDM is activated, the CPU finishes executing the current instruction. Thereafter only BDC commands can affect CPU register contents until the BDC GO command returns from active BDM to user code or a device reset occurs. When BDM is activated by a breakpoint, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction. NOTE Attempting to activate BDM using a BGND instruction whilst the BDC is disabled, the CPU requires clock cycles for the attempted BGND execution. However BACKGROUND commands issued whilst the BDC is disabled are ignored by the BDC and the CPU execution is not delayed. 5.4.3 Clock Source The BDC clock source can be mapped to a constant frequency clock source or a PLL based fast clock. The clock source for the BDC is selected by the CLKSW bit as shown in Figure 5-5. The BDC internal clock is named BDCSI clock. If BDCSI clock is mapped to the BDCCLK by CLKSW then the serial interface communication is not affected by bus/core clock frequency changes. If the BDC is mapped to BDCFCLK then the clock is connected to a PLL derived source at device level (typically bus clock), thus can be subject to frequency changes in application. Debugging through frequency changes requires SYNC pulses to re-synchronize. The sources of BDCCLK and BDCFCLK are specified at device level. BDC accesses of internal device resources always use the device core clock. Thus if the ACK handshake protocol is not enabled, the clock frequency relationship must be taken into account by the host. When changing the clock source via the CLKSW bit a minimum delay of 150 cycles at the initial clock speed must elapse before a SYNC can be sent. This guarantees that the start of the next BDC command uses the new clock for timing subsequent BDC communications. BDCCLK BDCFCLK 0 BDCSI Clock BDC serial interface and FSM 1 CLKSW Core clock BDC device resource interface Figure 5-5. Clock Switch 5.4.4 BDC Commands BDC commands can be classified into three types as shown in Table 5-7. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 139 Background Debug Controller (S12ZBDCV2) Table 5-7. BDC Command Types Command Type Secure Status BDC Status Always-available Secure or Unsecure Enabled or Disabled Non-intrusive Active background Unsecure Unsecure Enabled Active CPU Status Command Set — • • • • Read/write access to BDCCSR Mass erase flash memory using ERASE_FLASH SYNC ACK enable/disable Code execution allowed • • • • • • • • Read/write access to BDCCSR Memory access Memory access with status Mass erase flash memory using ERASE_FLASH Debug register access BACKGROUND SYNC ACK enable/disable Code execution halted • • • • • • • • • • Read/write access to BDCCSR Memory access Memory access with status Mass erase flash memory using ERASE_FLASH Debug register access Read or write CPU registers Single-step the application Exit active BDM to return to the application program (GO) SYNC ACK enable/disable Non-intrusive commands are used to read and write target system memory locations and to enter active BDM. Target system memory includes all memory and registers within the global memory map, including external memory. Active background commands are used to read and write all memory locations and CPU resources. Furthermore they allow single stepping through application code and to exit from active BDM. Non-intrusive commands can only be executed when the BDC is enabled and the device unsecure. Active background commands can only be executed when the system is not secure and is in active BDM. Non-intrusive commands do not require the system to be in active BDM for execution, although, they can still be executed in this mode. When executing a non-intrusive command with the ACK pulse handshake protocol disabled, the BDC steals the next bus cycle for the access. If an operation requires multiple cycles, then multiple cycles can be stolen. Thus if stolen cycles are not free cycles, the application code execution is delayed. The delay is negligible because the BDC serial transfer rate dictates that such accesses occur infrequently. For data read commands, the external host must wait at least 16 BDCSI clock cycles after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDC shift register, ready to be shifted out. For write commands, the external host must wait 16 bdcsi cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDC shift register before the write has been completed. The external host must wait at least for 16 bdcsi cycles after a control command before starting any new serial command. MC912ZVL Family Reference Manual, Rev. 2.48 140 NXP Semiconductors Background Debug Controller (S12ZBDCV2) If the ACK pulse handshake protocol is enabled and STEAL is cleared, then the BDC waits for the first free bus cycle to make a non-intrusive access. If no free bus cycle occurs within 512 core clock cycles then the BDC aborts the access, sets the NORESP bit and uses a long ACK pulse to indicate an error condition to the host. Table 5-8 summarizes the BDC command set. The subsequent sections describe each command in detail and illustrate the command structure in a series of packets, each consisting of eight bit times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is 8  16 target BDCSI clock cycles. The nomenclature below is used to describe the structure of the BDC commands. Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first) / d dack ad24 rd8 rd16 rd24 rd32 rd64 rd.sz wd8 wd16 wd32 wd.sz ss sz = = = = = = = = = = = = = = = = crn WS = = separates parts of the command delay 16 target BDCSI clock cycles (DLY) delay (16 cycles) no ACK; or delay (=> 32 cycles) then ACK.(DACK) 24-bit memory address in the host-to-target direction 8 bits of read data in the target-to-host direction 16 bits of read data in the target-to-host direction 24 bits of read data in the target-to-host direction 32 bits of read data in the target-to-host direction 64 bits of read data in the target-to-host direction read data, size defined by sz, in the target-to-host direction 8 bits of write data in the host-to-target direction 16 bits of write data in the host-to-target direction 32 bits of write data in the host-to-target direction write data, size defined by sz, in the host-to-target direction the contents of BDCCSRL in the target-to-host direction memory operand size (00 = byte, 01 = word, 10 = long) (sz = 11 is reserved and currently defaults to long) core register number, 32-bit data width command suffix signaling the operation is with status Table 5-8. BDC Command Summary Command Mnemonic Command Classification ACK Command Structure Description SYNC Always Available N/A N/A1 ACK_DISABLE Always Available No 0x03/d ACK_ENABLE Always Available Yes 0x02/dack Enable the communication handshake. Issues an ACK pulse after the command is executed. Non-Intrusive Yes 0x04/dack Halt the CPU if ENBDC is set. Otherwise, ignore as illegal command. BACKGROUND Request a timed reference pulse to determine the target BDC communication speed Disable the communication handshake. This command does not issue an ACK pulse. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 141 Background Debug Controller (S12ZBDCV2) Table 5-8. BDC Command Summary (continued) Command Mnemonic Command Classification ACK Command Structure DUMP_MEM.sz Non-Intrusive Yes (0x32+4 x sz)/dack/rd.sz Dump (read) memory based on operand size (sz). Used with READ_MEM to dump large blocks of memory. An initial READ_MEM is executed to set up the starting address of the block and to retrieve the first result. Subsequent DUMP_MEM commands retrieve sequential operands. DUMP_MEM.sz_WS Non-Intrusive No (0x33+4 x sz)/d/ss/rd.sz Dump (read) memory based on operand size (sz) and report status. Used with READ_MEM{_WS} to dump large blocks of memory. An initial READ_MEM{_WS} is executed to set up the starting address of the block and to retrieve the first result. Subsequent DUMP_MEM{_WS} commands retrieve sequential operands. FILL_MEM.sz Non-Intrusive Yes (0x12+4 x sz)/wd.sz/dack Fill (write) memory based on operand size (sz). Used with WRITE_MEM to fill large blocks of memory. An initial WRITE_MEM is executed to set up the starting address of the block and to write the first operand. Subsequent FILL_MEM commands write sequential operands. FILL_MEM.sz_WS Non-Intrusive No (0x13+4 x sz)/wd.sz/d/ss Fill (write) memory based on operand size (sz) and report status. Used with WRITE_MEM{_WS} to fill large blocks of memory. An initial WRITE_MEM{_WS} is executed to set up the starting address of the block and to write the first operand. Subsequent FILL_MEM{_WS} commands write sequential operands. GO Active Background Yes 0x08/dack Resume CPU user code execution GO_UNTIL2 Active Background Yes 0x0C/dack Go to user program. ACK is driven upon returning to active background mode. Non-Intrusive Yes 0x00/dack No operation Active Background Yes (0x60+CRN)/dack/rd32 READ_MEM.sz Non-Intrusive Yes (0x30+4 x sz)/ad24/dack/rd.sz Read the appropriately-sized (sz) memory value from the location specified by the 24-bit address READ_MEM.sz_WS Non-Intrusive No (0x31+4 x sz)/ad24/d/ss/rd.sz Read the appropriately-sized (sz) memory value from the location specified by the 24-bit address and report status READ_DBGTB Non-Intrusive Yes NOP READ_Rn (0x07)/dack/rd32/dack/rd32 Description Read the requested CPU register Read 64-bits of DBG trace buffer MC912ZVL Family Reference Manual, Rev. 2.48 142 NXP Semiconductors Background Debug Controller (S12ZBDCV2) Table 5-8. BDC Command Summary (continued) Command Mnemonic Command Classification ACK Command Structure READ_SAME.sz Non-Intrusive Yes (0x50+4 x sz)/dack/rd.sz Read from location. An initial READ_MEM defines the address, subsequent READ_SAME reads return content of same address READ_SAME.sz_WS Non-Intrusive No (0x51+4 x sz)/d/ss/rd.sz Read from location. An initial READ_MEM defines the address, subsequent READ_SAME reads return content of same address Always Available No 0x2D/rd16 SYNC_PC Non-Intrusive Yes 0x01/dack/rd24 WRITE_MEM.sz Non-Intrusive Yes (0x10+4 x sz)/ad24/wd.sz/dack WRITE_MEM.sz_WS Non-Intrusive No Active Background Yes (0x40+CRN)/wd32/dack WRITE_BDCCSR Always Available No 0x0D/wd16 ERASE_FLASH Always Available No 0x95/d Active Background Yes 0x09/dack READ_BDCCSR WRITE_Rn STEP1 (TRACE1) 1 2 Description Read the BDCCSR register Read current PC Write the appropriately-sized (sz) memory value to the location specified by the 24-bit address (0x11+4 x sz)/ad24/wd.sz/d/ss Write the appropriately-sized (sz) memory value to the location specified by the 24-bit address and report status Write the requested CPU register Write the BDCCSR register Mass erase internal flash Execute one CPU command. The SYNC command is a special operation which does not have a command code. The GO_UNTIL command is identical to the GO command if ACK is not enabled. 5.4.4.1 SYNC The SYNC command is unlike other BDC commands because the host does not necessarily know the correct speed to use for serial communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: 1. Ensures that the BKGD pin is high for at least 4 cycles of the slowest possible BDCSI clock without reset asserted. 2. Drives the BKGD pin low for at least 128 cycles of the slowest possible BDCSI clock. 3. Drives BKGD high for a brief speed-up pulse to get a fast rise time. (This speedup pulse is typically one cycle of the host clock which is as fast as the maximum target BDCSI clock). 4. Removes all drive to the BKGD pin so it reverts to high impedance. 5. Listens to the BKGD pin for the sync response pulse. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 143 Background Debug Controller (S12ZBDCV2) Upon detecting the sync request from the host (which is a much longer low time than would ever occur during normal BDC communications), the target: 1. Discards any incomplete command 2. Waits for BKGD to return to a logic high. 3. Delays 16 cycles to allow the host to stop driving the high speed-up pulse. 4. Drives BKGD low for 128 BDCSI clock cycles. 5. Drives a 1-cycle high speed-up pulse to force a fast rise time on BKGD. 6. Removes all drive to the BKGD pin so it reverts to high impedance. 7. Clears the OVRRUN flag (if set). The host measures the low time of this 128-cycle SYNC response pulse and determines the correct speed for subsequent BDC communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the serial protocol can easily tolerate this speed error. If the SYNC request is detected by the target, any partially executed command is discarded. This is referred to as a soft-reset, equivalent to a timeout in the serial communication. After the SYNC response, the target interprets the next negative edge (issued by the host) as the start of a new BDC command or the start of new SYNC request. A SYNC command can also be used to abort a pending ACK pulse. This is explained in Section 5.4.8, “Hardware Handshake Abort Procedure. 5.4.4.2 ACK_DISABLE Disable host/target handshake protocol Always Available 0x03 host  target D L Y Disables the serial communication handshake protocol. The subsequent commands, issued after the ACK_DISABLE command, do not execute the hardware handshake protocol. This command is not followed by an ACK pulse. 5.4.4.3 ACK_ENABLE Enable host/target handshake protocol Always Available 0x02 host  target D A C K Enables the hardware handshake protocol in the serial communication. The hardware handshake is implemented by an acknowledge (ACK) pulse issued by the target MCU in response to a host command. MC912ZVL Family Reference Manual, Rev. 2.48 144 NXP Semiconductors Background Debug Controller (S12ZBDCV2) The ACK_ENABLE command is interpreted and executed in the BDC logic without the need to interface with the CPU. An ACK pulse is issued by the target device after this command is executed. This command can be used by the host to evaluate if the target supports the hardware handshake protocol. If the target supports the hardware handshake protocol, subsequent commands are enabled to execute the hardware handshake protocol, otherwise this command is ignored by the target. Table 5-8 indicates which commands support the ACK hardware handshake protocol. For additional information about the hardware handshake protocol, refer to Section 5.4.7, “Serial Interface Hardware Handshake (ACK Pulse) Protocol,” and Section 5.4.8, “Hardware Handshake Abort Procedure.” 5.4.4.4 BACKGROUND Enter active background mode (if enabled) Non-intrusive 0x04 host  target D A C K Provided ENBDC is set, the BACKGROUND command causes the target MCU to enter active BDM as soon as the current CPU instruction finishes. If ENBDC is cleared, the BACKGROUND command is ignored. A delay of 16 BDCSI clock cycles is required after the BACKGROUND command to allow the target MCU to finish its current CPU instruction and enter active background mode before a new BDC command can be accepted. The host debugger must set ENBDC before attempting to send the BACKGROUND command the first time. Normally the host sets ENBDC once at the beginning of a debug session or after a target system reset. During debugging, the host uses GO commands to move from active BDM to application program execution and uses the BACKGROUND command or DBG breakpoints to return to active BDM. A BACKGROUND command issued during stop or wait modes cannot immediately force active BDM because the WAI instruction does not end until an interrupt occurs. For the detailed mode dependency description refer to Section 5.1.3.3, “Low-Power Modes. The host can recognize this pending BDM request condition because both NORESP and WAIT are set, but BDMACT is clear. Whilst in wait mode, with the pending BDM request, non-intrusive BDC commands are allowed. 5.4.4.5 DUMP_MEM.sz, DUMP_MEM.sz_WS DUMP_MEM.sz Read memory specified by debug address register, then increment address Non-intrusive MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 145 Background Debug Controller (S12ZBDCV2) DUMP_MEM.sz 0x32 host  target Data[7-0] D A C K 0x36 host  target D A C K 0x3A host  target D A C K target  host Data[15-8] Data[7-0] target  host target  host Data[31-24] Data[23-16] Data[15-8] Data[7-0] target  host target  host target  host target  host DUMP_MEM.sz_WS Read memory specified by debug address register with status, then increment address 0x33 host  target BDCCSRL D L Y 0x37 host  target D L Y 0x3B host  target D L Y target  host Non-intrusive Data[7-0] target  host BDCCSRL Data[15-8] Data[7-0] target  host target  host BDCCSRL Data[31-24] Data23-16] Data[15-8] target  host target  host target  host target  host target  host Data[7-0] target  host DUMP_MEM{_WS} is used with the READ_MEM{_WS} command to access large blocks of memory. An initial READ_MEM{_WS} is executed to set-up the starting address of the block and to retrieve the first result. The DUMP_MEM{_WS} command retrieves subsequent operands. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register. Subsequent DUMP_MEM{_WS} commands use this address, perform the memory read, increment it by the current operand size, and store the updated address in the temporary register. If the with-status option is specified, the BDCCSRL status byte is returned before the read data. This status byte reflects the state after the memory read was performed. If enabled, an ACK pulse is driven before the data bytes are transmitted. The effect of the access size and alignment on the next address to be accessed is explained in more detail in Section 5.4.5.2, “BDC Access Of Device Memory Mapped Resources”. MC912ZVL Family Reference Manual, Rev. 2.48 146 NXP Semiconductors Background Debug Controller (S12ZBDCV2) NOTE DUMP_MEM{_WS} is a valid command only when preceded by SYNC, NOP, READ_MEM{_WS}, or another DUMP_MEM{_WS} command. Otherwise, an illegal command response is returned, setting the ILLCMD bit. NOP can be used for inter-command padding without corrupting the address pointer. The size field (sz) is examined each time a DUMP_MEM{_WS} command is processed, allowing the operand size to be dynamically altered. The examples show the DUMP_MEM.B{_WS}, DUMP_MEM.W{_WS} and DUMP_MEM.L{_WS} commands. 5.4.4.6 FILL_MEM.sz, FILL_MEM.sz_WS FILL_MEM.sz Write memory specified by debug address register, then increment address Non-intrusive 0x12 Data[7-0] host  target host  target 0x16 Data[15-8] Data[7-0] host  target host  target host  target 0x1A Data[31-24] Data[23-16] Data[15-8] Data[7-0] host  target host  target host  target host  target host  target D A C K D A C K D A C K FILL_MEM.sz_WS Write memory specified by debug address register with status, then increment address Non-intrusive BDCCSRL 0x13 Data[7-0] host  target host  target 0x17 Data[15-8] Data[7-0] host  target host  target host  target D L Y target  host BDCCSRL D L Y target  host MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 147 Background Debug Controller (S12ZBDCV2) FILL_MEM.sz_WS 0x1B Data[31-24] Data[23-16] Data[15-8] Data[7-0] host  target host  target host  target host  target host  target BDCCSRL D L Y target  host FILL_MEM{_WS} is used with the WRITE_MEM{_WS} command to access large blocks of memory. An initial WRITE_MEM{_WS} is executed to set up the starting address of the block and write the first datum. If an initial WRITE_MEM{_WS} is not executed before the first FILL_MEM{_WS}, an illegal command response is returned. The FILL_MEM{_WS} command stores subsequent operands. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register. Subsequent FILL_MEM{_WS} commands use this address, perform the memory write, increment it by the current operand size, and store the updated address in the temporary register. If the with-status option is specified, the BDCCSRL status byte is returned after the write data. This status byte reflects the state after the memory write was performed. If enabled an ACK pulse is generated after the internal write access has been completed or aborted. The effect of the access size and alignment on the next address to be accessed is explained in more detail in Section 5.4.5.2, “BDC Access Of Device Memory Mapped Resources” NOTE FILL_MEM{_WS} is a valid command only when preceded by SYNC, NOP, WRITE_MEM{_WS}, or another FILL_MEM{_WS} command. Otherwise, an illegal command response is returned, setting the ILLCMD bit. NOP can be used for inter command padding without corrupting the address pointer. The size field (sz) is examined each time a FILL_MEM{_WS} command is processed, allowing the operand size to be dynamically altered. The examples show the FILL_MEM.B{_WS}, FILL_MEM.W{_WS} and FILL_MEM.L{_WS} commands. 5.4.4.7 GO Go Non-intrusive 0x08 host  target D A C K This command is used to exit active BDM and begin (or resume) execution of CPU application code. The CPU pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC. If any register (such as the PC) is altered by a BDC command whilst in BDM, the updated value is used when prefetching resumes. If enabled, an ACK is driven on exiting active BDM. If a GO command is issued whilst the BDM is inactive, an illegal command response is returned and the ILLCMD bit is set. MC912ZVL Family Reference Manual, Rev. 2.48 148 NXP Semiconductors Background Debug Controller (S12ZBDCV2) 5.4.4.8 GO_UNTIL Go Until Active Background 0x0C host  target D A C K This command is used to exit active BDM and begin (or resume) execution of application code. The CPU pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC. If any register (such as the PC) is altered by a BDC command whilst in BDM, the updated value is used when prefetching resumes. After resuming application code execution, if ACK is enabled, the BDC awaits a return to active BDM before driving an ACK pulse. timeouts do not apply when awaiting a GO_UNTIL command ACK. If a GO_UNTIL is not acknowledged then a SYNC command must be issued to end the pending GO_UNTIL. If a GO_UNTIL command is issued whilst BDM is inactive, an illegal command response is returned and the ILLCMD bit is set. If ACK handshaking is disabled, the GO_UNTIL command is identical to the GO command. 5.4.4.9 NOP No operation Active Background 0x00 host  target D A C K NOP performs no operation and may be used as a null command where required. 5.4.4.10 READ_Rn Read CPU register Active Background 0x60+CRN host  target Data [31-24] Data [23-16] D A C K target  host target  host Data [15-8] Data [7-0] target  host target  host This command reads the selected CPU registers and returns the 32-bit result. Accesses to CPU registers are always 32-bits wide, regardless of implemented register width. Bytes that are not implemented return zero. The register is addressed through the CPU register number (CRN). See Section 5.4.5.1, “BDC MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 149 Background Debug Controller (S12ZBDCV2) Access Of CPU Registers for the CRN address decoding. If enabled, an ACK pulse is driven before the data bytes are transmitted. If the device is not in active BDM, this command is illegal, the ILLCMD bit is set and no access is performed. 5.4.4.11 READ_MEM.sz, READ_MEM.sz_WS READ_MEM.sz Read memory at the specified address 0x30 Address[23-0] host  target host  target 0x34 Address[23-0] host  target host  target 0x38 Address[23-0] host  target host  target Non-intrusive Data[7-0] D A C K D A C K D A C K target  host Data[15-8] Data[7-0] target  host target  host Data[31-24] Data[23-16] Data[15-8] Data[7-0] target  host target  host target  host target  host READ_MEM.sz_WS Read memory at the specified address with status 0x31 Address[23-0] host  target host  target 0x35 Address[23-0] host  target host  target 0x39 Address[23-0] host  target host  target Non-intrusive BDCCSRL D L Y D L Y D L Y target  host Data[7-0] target  host BDCCSRL Data [15-8] Data [7-0] target  host target  host BDCCSRL Data[31-24] Data[23-16] Data [15-8] target  host target  host target  host target  host target  host Data [7-0] target  host Read data at the specified memory address. The address is transmitted as three 8-bit packets (msb to lsb) immediately after the command. The hardware forces low-order address bits to zero longword accesses to ensure these accesses are on 0-modulo-size alignments. Byte alignment details are described in Section 5.4.5.2, “BDC Access Of Device Memory Mapped Resources”. If the with-status option is specified, the BDCCSR status byte is MC912ZVL Family Reference Manual, Rev. 2.48 150 NXP Semiconductors Background Debug Controller (S12ZBDCV2) returned before the read data. This status byte reflects the state after the memory read was performed. If enabled, an ACK pulse is driven before the data bytes are transmitted. The examples show the READ_MEM.B{_WS}, READ_MEM.W{_WS} and READ_MEM.L{_WS} commands. 5.4.4.12 READ_DBGTB Read DBG trace buffer 0x07 host  target D A C K Non-intrusive TB Line [31-24] TB Line [23-16] TB Line [15-8] TB Line [7-0] target  host target  host target  host target  host D A C K TB Line [63-56] TB Line [55-48] TB Line [47-40] TB Line [39-32] target  host target  host target  host target  host This command is only available on devices, where the DBG module includes a trace buffer. Attempted use of this command on devices without a traace buffer return 0x00. Read 64 bits from the DBG trace buffer. Refer to the DBG module description for more detailed information. If enabled an ACK pulse is generated before each 32-bit longword is ready to be read by the host. After issuing the first ACK a timeout is still possible whilst accessing the second 32-bit longword, since this requires separate internal accesses. The first 32-bit longword corresponds to trace buffer line bits[31:0]; the second to trace buffer line bits[63:32]. If ACK handshaking is disabled, the host must wait 16 clock cycles (DLY) after completing the first 32-bit read before starting the second 32-bit read. 5.4.4.13 READ_SAME.sz, READ_SAME.sz_WS READ_SAME Read same location specified by previous READ_MEM{_WS} 0x54 host  target D A C K Data[15-8] Data[7-0] target  host target  host Non-intrusive READ_SAME_WS Read same location specified by previous READ_MEM{_WS} 0x55 host  target D L Y BDCCSRL Data [15-8] target  host target  host Non-intrusive Data [7-0] target  host MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 151 Background Debug Controller (S12ZBDCV2) Read from location defined by the previous READ_MEM. The previous READ_MEM command defines the address, subsequent READ_SAME commands return contents of same address. The example shows the sequence for reading a 16-bit word size. Byte alignment details are described in Section 5.4.5.2, “BDC Access Of Device Memory Mapped Resources”. If enabled, an ACK pulse is driven before the data bytes are transmitted. NOTE READ_SAME{_WS} is a valid command only when preceded by SYNC, NOP, READ_MEM{_WS}, or another READ_SAME{_WS} command. Otherwise, an illegal command response is returned, setting the ILLCMD bit. NOP can be used for inter-command padding without corrupting the address pointer. 5.4.4.14 READ_BDCCSR Read BDCCSR Status Register 0x2D D L Y host  target Always Available BDCCSR [15:8] BDCCSR [7-0] target  host target  host Read the BDCCSR status register. This command can be executed in any mode. 5.4.4.15 SYNC_PC Sample current PC 0x01 host  target D A C K Non-intrusive PC data[23– 16] PC data[15–8] PC data[7–0] target  host target  host target  host This command returns the 24-bit CPU PC value to the host. Unsuccessful SYNC_PC accesses return 0xEE for each byte. If enabled, an ACK pulse is driven before the data bytes are transmitted. The value of 0xEE is returned if a timeout occurs, whereby NORESP is set. This can occur if the CPU is executing the WAI instruction, or the STOP instruction with BDCCIS clear, or if a CPU access is delayed by EWAIT. If the CPU is executing the STOP instruction and BDCCIS is set, then SYNC_PC returns the PC address of the instruction following STOP in the code listing. This command can be used to dynamically access the PC for performance monitoring as the execution of this command is considerably less intrusive to the real-time operation of an application than a BACKGROUND/read-PC/GO command sequence. Whilst the BDC is not in active BDM, SYNC_PC returns the PC address of the instruction currently being executed by the CPU. In active BDM, SYNC_PC MC912ZVL Family Reference Manual, Rev. 2.48 152 NXP Semiconductors Background Debug Controller (S12ZBDCV2) returns the address of the next instruction to be executed on returning from active BDM. Thus following a write to the PC in active BDM, a SYNC_PC returns that written value. 5.4.4.16 WRITE_MEM.sz, WRITE_MEM.sz_WS WRITE_MEM.sz Write memory at the specified address Non-intrusive 0x10 Address[23-0] Data[7–0] host  target host  target host  target 0x14 Address[23-0] Data[15–8] Data[7–0] host  target host  target host  target host  target 0x18 Address[23-0] host  target host  target D A C K D A C K Data[31–24] Data[23–16] host  target Data[15–8] Data[7–0] host  target host  target host  target D A C K WRITE_MEM.sz_WS Write memory at the specified address with status Non-intrusive 0x11 Address[23-0] Data[7–0] host  target host  target host  target 0x15 Address[23-0] Data[15–8] Data[7–0] host  target host  target host  target host  target 0x19 Address[23-0] host  target host  target BDCCSRL D L Y target  host Data[31–24] Data[23–16] host  target host  target BDCCSRL D L Y target  host Data[15–8] Data[7–0] host  target host  target BDCCSRL D L Y target  host Write data to the specified memory address. The address is transmitted as three 8-bit packets (msb to lsb) immediately after the command. If the with-status option is specified, the status byte contained in BDCCSRL is returned after the write data. This status byte reflects the state after the memory write was performed. The examples show the WRITE_MEM.B{_WS}, WRITE_MEM.W{_WS}, and WRITE_MEM.L{_WS} commands. If enabled an ACK pulse is generated after the internal write access has been completed or aborted. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 153 Background Debug Controller (S12ZBDCV2) The hardware forces low-order address bits to zero longword accesses to ensure these accesses are on 0-modulo-size alignments. Byte alignment details are described in Section 5.4.5.2, “BDC Access Of Device Memory Mapped Resources”. 5.4.4.17 WRITE_Rn Write general-purpose CPU register 0x40+CRN Active Background Data [31–24] Data [23–16] Data [15–8] host  target host  target host  target Data [7–0] host  target host  target D A C K If the device is in active BDM, this command writes the 32-bit operand to the selected CPU general-purpose register. See Section 5.4.5.1, “BDC Access Of CPU Registers for the CRN details. Accesses to CPU registers are always 32-bits wide, regardless of implemented register width. If enabled an ACK pulse is generated after the internal write access has been completed or aborted. If the device is not in active BDM, this command is rejected as an illegal operation, the ILLCMD bit is set and no operation is performed. 5.4.4.18 WRITE_BDCCSR Write BDCCSR Always Available 0x0D host  target BDCCSR Data [15-8] BDCCSR Data [7-0] host  target host  target D L Y 16-bit write to the BDCCSR register. No ACK pulse is generated. Writing to this register can be used to configure control bits or clear flag bits. Refer to the register bit descriptions. 5.4.4.19 ERASE_FLASH Erase FLASH Always Available 0x95 host  target D L Y Mass erase the internal flash. This command can always be issued. On receiving this command twice in succession, the BDC sets the ERASE bit in BDCCSR and requests a flash mass erase. Any other BDC command following a single ERASE_FLASH initializes the sequence, such that thereafter the ERASE_FLASH must be applied twice in succession to request a mass erase. If 512 BDCSI clock cycles MC912ZVL Family Reference Manual, Rev. 2.48 154 NXP Semiconductors Background Debug Controller (S12ZBDCV2) elapse between the consecutive ERASE_FLASH commands then a timeout occurs, which forces a soft reset and initializes the sequence. The ERASE bit is cleared when the mass erase sequence has been completed. No ACK is driven. During the mass erase operation, which takes many clock cycles, the command status is indicated by the ERASE bit in BDCCSR. Whilst a mass erase operation is ongoing, Always-available commands can be issued. This allows the status of the erase operation to be polled by reading BDCCSR to determine when the operation is finished. The status of the flash array can be verified by subsequently reading the flash error flags to determine if the erase completed successfully. ERASE_FLASH can be aborted by a SYNC pulse forcing a soft reset. NOTE: Device Bus Frequency Considerations The ERASE_FLASH command requires the default device bus clock frequency after reset. Thus the bus clock frequency must not be changed following reset before issuing an ERASE_FLASH command. 5.4.4.20 STEP1 Step1 Active Background 0x09 host  target D A C K This command is used to step through application code. In active BDM this command executes the next CPU instruction in application code. If enabled an ACK is driven. If a STEP1 command is issued and the CPU is not halted, the command is ignored. Using STEP1 to step through a CPU WAI instruction is explained in Section 5.1.3.3.2, “Wait Mode. 5.4.5 BDC Access Of Internal Resources Unsuccessful read accesses of internal resources return a value of 0xEE for each data byte. This enables a debugger to recognize a potential error, even if neither the ACK handshaking protocol nor a status command is currently being executed. The value of 0xEE is returned in the following cases. • Illegal address access, whereby ILLACC is set • Invalid READ_SAME or DUMP_MEM sequence • Invalid READ_Rn command (BDM inactive or CRN incorrect) • Internal resource read with timeout, whereby NORESP is set MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 155 Background Debug Controller (S12ZBDCV2) 5.4.5.1 BDC Access Of CPU Registers The CRN field of the READ_Rn and WRITE_Rn commands contains a pointer to the CPU registers. The mapping of CRN to CPU registers is shown in Table 5-9. Accesses to CPU registers are always 32-bits wide, regardless of implemented register width. This means that the BDC data transmission for these commands is 32-bits long. The valid bits of the transfer are listed in the Valid Data Bits column. The other bits of the transmission are redundant. Attempted accesses of CPU registers using a CRN of 0xD,0xE or 0xF is invalid, returning the value 0xEE for each byte and setting the ILLACC bit. Table 5-9. CPU Register Number (CRN) Mapping CPU Register Valid Data Bits Command Opcode Command Opcode D0 [7:0] WRITE_D0 0x40 READ_D0 0x60 D1 [7:0] WRITE_D1 0x41 READ_D1 0x61 D2 [15:0] WRITE_D2 0x42 READ_D2 0x62 D3 [15:0] WRITE_D3 0x43 READ_D3 0x63 D4 [15:0] WRITE_D4 0x44 READ_D4 0x64 D5 [15:0] WRITE_D5 0x45 READ_D5 0x65 D6 [31:0] WRITE_D6 0x46 READ_D6 0x66 D7 [31:0] WRITE_D7 0x47 READ_D7 0x67 X [23:0] WRITE_X 0x48 READ_X 0x68 Y [23:0] WRITE_Y 0x49 READ_Y 0x69 SP [23:0] WRITE_SP 0x4A READ_SP 0x6A 5.4.5.2 PC [23:0] WRITE_PC 0x4B READ_PC 0x6B CCR [15:0] WRITE_CCR 0x4C READ_CCR 0x6C BDC Access Of Device Memory Mapped Resources The device memory map is accessed using READ_MEM, DUMP_MEM, WRITE_MEM, FILL_MEM and READ_SAME, which support different access sizes, as explained in the command descriptions. When an unimplemented command occurs during a DUMP_MEM, FILL_MEM or READ_SAME sequence, then that sequence is ended. Illegal read accesses return a value of 0xEE for each byte. After an illegal access FILL_MEM and READ_SAME commands are not valid, and it is necessary to restart the internal access sequence with READ_MEM or WRITE_MEM. An illegal access does not break a DUMP_MEM sequence. After read accesses that cause the RDINV bit to be set, DUMP_MEM and READ_SAME commands are valid, it is not necessary to restart the access sequence with a READ_MEM. The hardware forces low-order address bits to zero for longword accesses to ensure these accesses are realigned to 0-modulo-size alignments. Word accesses map to 2-bytes from within a 4-byte field as shown in Table 5-10. Thus if address bits [1:0] are both logic “1” the access is realigned so that it does not straddle the 4-byte boundary but accesses data from within the addressed 4-byte field. MC912ZVL Family Reference Manual, Rev. 2.48 156 NXP Semiconductors Background Debug Controller (S12ZBDCV2) Table 5-10. Field Location to Byte Access Mapping Address[1:0] Access Size 00 01 10 11 00 32-bit Data[31:24] Data[23:16] Data [15:8] Data [7:0] Note 01 32-bit Data[31:24] Data[23:16] Data [15:8] Data [7:0] Realigned 10 32-bit Data[31:24] Data[23:16] Data [15:8] Data [7:0] Realigned 11 32-bit Data[31:24] Data[23:16] Data [15:8] Data [7:0] Realigned 00 16-bit Data [15:8] Data [7:0] 01 16-bit 10 16-bit Data [15:8] Data [7:0] 11 16-bit Data [15:8] Data [7:0] 00 8-bit 01 8-bit 10 8-bit 11 8-bit Data [15:8] Data [7:0] Realigned Data [7:0] Data [7:0] Data [7:0] Data [7:0] Denotes byte that is not transmitted 5.4.5.2.1 FILL_MEM and DUMP_MEM Increments and Alignment FILL_MEM and DUMP_MEM increment the previously accessed address by the previous access size to calculate the address of the current access. On misaligned longword accesses, the address bits [1:0] are forced to zero, therefore the following FILL_MEM or DUMP_MEM increment to the first address in the next 4-byte field. This is shown in Table 5-11, the address of the first DUMP_MEM.32 following READ_MEM.32 being calculated from 0x004000+4. When misaligned word accesses are realigned, then the original address (not the realigned address) is incremented for the following FILL_MEM, DUMP_MEM command. Misaligned word accesses can cause the same locations to be read twice as shown in rows 6 and 7. The hardware ensures alignment at an attempted misaligned word access across a 4-byte boundary, as shown in row 7. The following word access in row 8 continues from the realigned address of row 7. d Table 5-11. Consecutive Accesses With Variable Size Row Command Address Address[1:0] 00 01 10 11 1 READ_MEM.32 0x004003 11 Accessed Accessed Accessed Accessed 2 DUMP_MEM.32 0x004004 00 Accessed Accessed Accessed Accessed 3 DUMP_MEM.16 0x004008 00 Accessed Accessed 4 DUMP_MEM.16 0x00400A 10 Accessed Accessed 5 DUMP_MEM.08 0x00400C 00 6 DUMP_MEM.16 0x00400D 01 7 DUMP_MEM.16 0x00400E 10 8 DUMP_MEM.16 0x004010 01 Accessed Accessed Accessed Accessed Accessed Accessed Accessed MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 157 Background Debug Controller (S12ZBDCV2) 5.4.5.2.2 READ_SAME Effects Of Variable Access Size READ_SAME uses the unadjusted address given in the previous READ_MEM command as a base address for subsequent READ_SAME commands. When the READ_MEM and READ_SAME size parameters differ then READ_SAME uses the original base address buts aligns 32-bit and 16-bit accesses, where those accesses would otherwise cross the aligned 4-byte boundary. Table 5-12 shows some examples of this. d Table 5-12. Consecutive READ_SAME Accesses With Variable Size Row 5.4.6 Command Base Address 00 01 10 11 1 READ_MEM.32 0x004003 Accessed Accessed Accessed Accessed 2 READ_SAME.32 — Accessed Accessed Accessed Accessed 3 READ_SAME.16 — Accessed Accessed 4 READ_SAME.08 — Accessed 5 READ_MEM.08 0x004000 Accessed 6 READ_SAME.08 — Accessed 7 READ_SAME.16 — Accessed Accessed 8 READ_SAME.32 — Accessed Accessed Accessed Accessed 9 READ_MEM.08 0x004002 Accessed 10 READ_SAME.08 — Accessed 11 READ_SAME.16 — Accessed Accessed 12 READ_SAME.32 — Accessed Accessed 13 READ_MEM.08 0x004003 Accessed 14 READ_SAME.08 — Accessed 15 READ_SAME.16 — 16 READ_SAME.32 — 17 READ_MEM.16 18 READ_SAME.08 19 20 Accessed Accessed Accessed Accessed Accessed Accessed Accessed 0x004001 Accessed Accessed — Accessed READ_SAME.16 — Accessed Accessed READ_SAME.32 — Accessed Accessed Accessed Accessed Accessed 21 READ_MEM.16 0x004003 22 READ_SAME.08 — 23 READ_SAME.16 — 24 READ_SAME.32 — Accessed Accessed Accessed Accessed Accessed Accessed Accessed Accessed Accessed BDC Serial Interface The BDC communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDC. The BDC serial interface uses an internal clock source, selected by the CLKSW bit in the BDCCSR register. This clock is referred to as the target clock in the following explanation. MC912ZVL Family Reference Manual, Rev. 2.48 158 NXP Semiconductors Background Debug Controller (S12ZBDCV2) The BDC serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per bit. The interface times out if during a command 512 clock cycles occur between falling edges from the host. The timeout forces the current command to be discarded. The BKGD pin is a pseudo open-drain pin and has a weak on-chip active pull-up that is enabled at all times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide brief drive-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases. The timing for host-to-target is shown in Figure 5-6 and that of target-to-host in Figure 5-7 and Figure 5-8. All cases begin when the host drives the BKGD pin low to generate a falling edge. Since the host and target operate from separate clocks, it can take the target up to one full clock cycle to recognize this edge; this synchronization uncertainty is illustrated in Figure 5-6. The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 5-6 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic requires the pin be driven high no later than eight target clock cycles after the falling edge for a logic 1 transmission. Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals. BDCSI clock (TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 10 CYCLES SYNCHRONIZATION UNCERTAINTY EARLIEST START OF NEXT BIT TARGET SENSES BIT LEVEL PERCEIVED START OF BIT TIME Figure 5-6. BDC Host-to-Target Serial Bit Timing Figure 5-7 shows the host receiving a logic 1 from the target system. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 159 Background Debug Controller (S12ZBDCV2) drive at the latest after 6 clock cycles, before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time. BDCSI clock (TARGET MCU) HOST DRIVE TO BKGD PIN TARGET MCU SPEEDUP PULSE HIGH-IMPEDANCE HIGH-IMPEDANCE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN Figure 5-7. BDC Target-to-Host Serial Bit Timing (Logic 1) Figure 5-8 shows the host receiving a logic 0 from the target. The host initiates the bit time but the target finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time. MC912ZVL Family Reference Manual, Rev. 2.48 160 NXP Semiconductors Background Debug Controller (S12ZBDCV2) BDCSI clock (TARGET MCU) HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE SPEEDUP PULSE TARGET MCU DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME BKGD PIN 10 CYCLES EARLIEST START OF NEXT BIT 10 CYCLES HOST SAMPLES BKGD PIN Figure 5-8. BDC Target-to-Host Serial Bit Timing (Logic 0) 5.4.7 Serial Interface Hardware Handshake (ACK Pulse) Protocol BDC commands are processed internally at the device core clock rate. Since the BDCSI clock can be asynchronous relative to the bus frequency, a handshake protocol is provided so the host can determine when an issued command has been executed. This section describes the hardware handshake protocol. The hardware handshake protocol signals to the host controller when a BDC command has been executed by the target. This protocol is implemented by a low pulse (16 BDCSI clock cycles) followed by a brief speedup pulse on the BKGD pin, generated by the target MCU when a command, issued by the host, has been successfully executed (see Figure 5-9). This pulse is referred to as the ACK pulse. After the ACK pulse has finished, the host can start the bit retrieval if the last issued command was a read command, or start a new command if the last command was a write command or a control command. BDCSI clock (TARGET MCU) TARGET TRANSMITS ACK PULSE HIGH-IMPEDANCE 16 CYCLES HIGH-IMPEDANCE 32 CYCLES SPEED UP PULSE MINIMUM DELAY FROM THE BDC COMMAND BKGD PIN EARLIEST START OF NEXT BIT 16th CYCLE OF THE LAST COMMAND BIT Figure 5-9. Target Acknowledge Pulse (ACK) MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 161 Background Debug Controller (S12ZBDCV2) The handshake protocol is enabled by the ACK_ENABLE command. The BDC sends an ACK pulse when the ACK_ENABLE command has been completed. This feature can be used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. Unlike the normal bit transfer, where the host initiates the transmission by issuing a negative edge on the BKGD pin, the serial interface ACK handshake pulse is initiated by the target MCU by issuing a negative edge on the BKGD pin. Figure 5-9 specifies the timing when the BKGD pin is being driven. The host must follow this timing constraint in order to avoid the risk of an electrical conflict at the BKGD pin. When the handshake protocol is enabled, the STEAL bit in BDCCSR selects if bus cycle stealing is used to gain immediate access. If STEAL is cleared, the BDC is configured for low priority bus access using free cycles, without stealing cycles. This guarantees that BDC accesses remain truly non-intrusive to not affect the system timing during debugging. If STEAL is set, the BDC gains immediate access, if necessary stealing an internal bus cycle. NOTE If bus steals are disabled then a loop with no free cycles cannot allow access. In this case the host must recognize repeated NORESP messages and then issue a BACKGROUND command to stop the target and access the data. Figure 5-10 shows the ACK handshake protocol without steal in a command level timing diagram. The READ_MEM.B command is used as an example. First, the 8-bit command code is sent by the host, followed by the address of the memory location to be read. The target BDC decodes the command. Then an internal access is requested by the BDC. When a free bus cycle occurs the READ_MEM.B operation is carried out. If no free cycle occurs within 512 core clock cycles then the access is aborted, the NORESP flag is set and the target generates a Long-ACK pulse. Having retrieved the data, the BDC issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved. After detecting the ACK pulse, the host initiates the data read part of the command. TARGET BKGD PIN READ_MEM.B ADDRESS[23–0] HOST HOST BYTE IS RETRIEVED TARGET NEW BDC COMMAND HOST TARGET BDC ISSUES THE ACK PULSE (NOT TO SCALE) BDC DECODES THE COMMAND MCU EXECUTES THE READ_MEM.B COMMAND Figure 5-10. Handshake Protocol at Command Level Alternatively, setting the STEAL bit configures the handshake protocol to make an immediate internal access, independent of free bus cycles. MC912ZVL Family Reference Manual, Rev. 2.48 162 NXP Semiconductors Background Debug Controller (S12ZBDCV2) The ACK handshake protocol does not support nested ACK pulses. If a BDC command is not acknowledged by an ACK pulse, the host needs to abort the pending command first in order to be able to issue a new BDC command. The host can decide to abort any possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol provides a mechanism in which a command, and its corresponding ACK, can be aborted. Commands With-Status do not generate an ACK, thus if ACK is enabled and a With-Status command is issued, the host must use the 512 cycle timeout to calculate when the data is ready for retrieval. 5.4.7.1 Long-ACK Hardware Handshake Protocol If a command results in an error condition, whereby a BDCCSRL flag is set, then the target generates a “Long-ACK” low pulse of 64 BDCSI clock cycles, followed by a brief speed pulse. This indicates to the host that an error has occurred. The host can subsequently read BDCCSR to determine the type of error. Whether normal ACK or Long-ACK, the ACK pulse is not issued earlier than 32 BDCSI clock cycles after the BDC command was issued. The end of the BDC command is assumed to be the 16th BDCSI clock cycle of the last bit. The 32 cycle minimum delay differs from the 16 cycle delay time with ACK disabled. If a BDC access request does not gain access within 512 core clock cycles, the request is aborted, the NORESP flag is set and a Long-ACK pulse is transmitted to indicate an error case. Following a STOP or WAI instruction, if the BDC is enabled, the first ACK, following stop or wait mode entry is a long ACK to indicate an exception. 5.4.8 Hardware Handshake Abort Procedure The abort procedure is based on the SYNC command. To abort a command that has not responded with an ACK pulse, the host controller generates a sync request (by driving BKGD low for at least 128 BDCSI clock cycles and then driving it high for one BDCSI clock cycle as a speedup pulse). By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol, see Section 5.4.4.1, “SYNC”, and assumes that the pending command and therefore the related ACK pulse are being aborted. After the SYNC protocol has been completed the host is free to issue new BDC commands. The host can issue a SYNC close to the 128 clock cycles length, providing a small overhead on the pulse length to assure the sync pulse is not misinterpreted by the target. See Section 5.4.4.1, “SYNC”. Figure 5-11 shows a SYNC command being issued after a READ_MEM, which aborts the READ_MEM command. Note that, after the command is aborted a new command is issued by the host. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 163 Background Debug Controller (S12ZBDCV2) READ_MEM.B CMD IS ABORTED BY THE SYNC REQUEST (NOT TO SCALE) BKGD PIN READ_MEM.B HOST ADDRESS[23-0] SYNC RESPONSE FROM THE TARGET (NOT TO SCALE) READ_BDCCSR TARGET HOST TARGET NEW BDC COMMAND HOST TARGET NEW BDC COMMAND BDC DECODES AND TRYS TO EXECUTE Figure 5-11. ACK Abort Procedure at the Command Level (Not To Scale) Figure 5-12 shows a conflict between the ACK pulse and the SYNC request pulse. The target is executing a pending BDC command at the exact moment the host is being connected to the BKGD pin. In this case, an ACK pulse is issued simultaneously to the SYNC command. Thus there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. As this is not a probable situation, the protocol does not prevent this conflict from happening. AT LEAST 128 CYCLES BDCSI clock (TARGET MCU) TARGET MCU DRIVES TO BKGD PIN ACK PULSE HIGH-IMPEDANCE ELECTRICAL CONFLICT HOST DRIVES SYNC TO BKGD PIN HOST AND TARGET DRIVE TO BKGD PIN SPEEDUP PULSE HOST SYNC REQUEST PULSE BKGD PIN 16 CYCLES Figure 5-12. ACK Pulse and SYNC Request Conflict 5.4.9 Hardware Handshake Disabled (ACK Pulse Disabled) The default state of the BDC after reset is hardware handshake protocol disabled. It can also be disabled by the ACK_DISABLE BDC command. This provides backwards compatibility with the existing host devices which are not able to execute the hardware handshake protocol. For host devices that support the hardware handshake protocol, true non-intrusive debugging and error flagging is offered. If the ACK pulse protocol is disabled, the host needs to use the worst case delay time at the appropriate places in the protocol. MC912ZVL Family Reference Manual, Rev. 2.48 164 NXP Semiconductors Background Debug Controller (S12ZBDCV2) If the handshake protocol is disabled, the access is always independent of free cycles, whereby BDC has higher priority than CPU. Since at least 2 bytes (command byte + data byte) are transferred over BKGD the maximum intrusiveness is only once every few hundred cycles. After decoding an internal access command, the BDC then awaits the next internal core clock cycle. The relationship between BDCSI clock and core clock must be considered. If the host retrieves the data immediately, then the BDCSI clock frequency must not be more than 4 times the core clock frequency, in order to guarantee that the BDC gains bus access within 16 the BDCSI cycle DLY period following an access command. If the BDCSI clock frequency is more than 4 times the core clock frequency, then the host must use a suitable delay time before retrieving data (see 5.5.1/5-166). Furthermore, for stretched read accesses to external resources via a device expanded bus (if implemented) the potential extra stretch cycles must be taken into consideration before attempting to obtain read data. If the access does not succeed before the host starts data retrieval then the NORESP flag is set but the access is not aborted. The NORESP state can be used by the host to recognize an unexpected access conflict due to stretched expanded bus accesses. Although the NORESP bit is set when an access does not succeed before the start of data retrieval, the access may succeed in following bus cycles if the internal access has already been initiated. 5.4.10 Single Stepping When a STEP1 command is issued to the BDC in active BDM, the CPU executes a single instruction in the user code and returns to active BDM. The STEP1 command can be issued repeatedly to step through the user code one instruction at a time. If an interrupt is pending when a STEP1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. In this case the stacking counts as one instruction. The device re-enters active BDM with the program counter pointing to the first instruction in the interrupt service routine. When stepping through the user code, the execution of the user code is done step by step but peripherals are free running. Some peripheral modules include a freeze feature, whereby their clocks are halted when the device enters active BDM. Timer modules typically include the freeze feature. Serial interface modules typically do not include the freeze feature. Hence possible timing relations between CPU code execution and occurrence of events of peripherals no longer exist. If the handshake protocol is enabled and BDCCIS is set then stepping over the STOP instruction causes the Long-ACK pulse to be generated and the BDCCSR STOP flag to be set. When stop mode is exited due to an interrupt the device enters active BDM and the PC points to the start of the corresponding interrupt service routine. Stepping can be continued. Stepping over a WAI instruction, the STEP1 command cannot be finished because active BDM cannot be entered after CPU starts to execute the WAI instruction. Stepping over the WAI instruction causes the BDCCSR WAIT and NORESP flags to be set and, if the handshake protocol is enabled, then the Long-ACK pulse is generated. Then the device enters wait mode, clears the BDMACT bit and awaits an interrupt to leave wait mode. In this time non-intrusive BDC commands are possible, although the STEP1 has actually not finished. When an interrupt occurs the device leaves wait mode, enters active BDM and the PC points to the start of the corresponding interrupt service routine. A further ACK related to stepping over the WAI is not generated. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 165 Background Debug Controller (S12ZBDCV2) 5.4.11 Serial Communication Timeout The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued. In this case, the target waits for a rising edge on BKGD in order to answer the SYNC request pulse. When the BDC detects the rising edge a soft reset is generated, whereby the current BDC command is discarded. If the rising edge is not detected, the target keeps waiting forever without any timeout limit. If a falling edge is not detected by the target within 512 clock cycles since the last falling edge, a timeout occurs and the current command is discarded without affecting memory or the operating mode of the MCU. This is referred to as a soft-reset. This timeout also applies if 512 cycles elapse between 2 consecutive ERASE_FLASH commands. The soft reset is disabled whilst the internal flash mass erase operation is pending completion. timeouts are also possible if a BDC command is partially issued, or data partially retrieved. Thus if a time greater than 512 BDCSI clock cycles is observed between two consecutive negative edges, a soft-reset occurs causing the partially received command or data retrieved to be discarded. The next negative edge at the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDC command, or the start of a SYNC request pulse. 5.5 5.5.1 Application Information Clock Frequency Considerations Read commands without status and without ACK must consider the frequency relationship between BDCSI and the internal core clock. If the core clock is slow, then the internal access may not have been carried out within the standard 16 BDCSI cycle delay period (DLY). The host must then extend the DLY period or clock frequencies accordingly. Taking internal clock domain synchronizers into account, the minimum number of BDCSI periods required for the DLY is expressed by: #DLY > 3(f(BDCSI clock) / f(core clock)) + 4 and the minimum core clock frequency with respect to BDCSI clock frequency is expressed by Minimum f(core clock) = (3/(#DLY cycles -4))f(BDCSI clock) For the standard 16 period DLY this yields f(core clock)>= (1/4)f(BDCSI clock) MC912ZVL Family Reference Manual, Rev. 2.48 166 NXP Semiconductors Chapter 6 Interrupt (S12ZINTV0) Table 6-1. Revision History Version Number Revision Date Effective Date V00.10 21 Feb 2012 all Corrected reset value for INT_CFADDR register V00.11 02 Jul 2012 all Removed references and functions related to XGATE V00.12 22 May 2013 all added footnote about availability of “Wake-up from STOP or WAIT by XIRQ with X bit set” feature 6.1 Description of Changes Introduction The S12ZINTV0 module decodes the priority of all system exception requests and provides the applicable vector for processing the exception to the CPU. The S12ZINTV0 module supports: • I-bit and X-bit maskable interrupt requests • One non-maskable unimplemented page1 op-code trap • One non-maskable unimplemented page2 op-code trap • One non-maskable software interrupt (SWI) • One non-maskable system call interrupt (SYS) • One non-maskable machine exception vector request • One spurious interrupt vector request • One system reset vector request Each of the I-bit maskable interrupt requests can be assigned to one of seven priority levels supporting a flexible priority scheme. The priority scheme can be used to implement nested interrupt capability where interrupts from a lower level are automatically blocked if a higher level interrupt is being processed. 6.1.1 Glossary The following terms and abbreviations are used in the document. Table 6-2. Terminology Term Meaning CCW Condition Code Register (in the S12Z CPU) DMA Direct Memory Access INT Interrupt IPL Interrupt Processing Level ISR Interrupt Service Routine MC9S12ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 167 Interrupt (S12ZINTV0) Table 6-2. Terminology Term MCU Micro-Controller Unit IRQ refers to the interrupt request associated with the IRQ pin XIRQ 6.1.2 • • • • • • • • • • • • • • 6.1.3 • • • Meaning refers to the interrupt request associated with the XIRQ pin Features Interrupt vector base register (IVBR) One system reset vector (at address 0xFFFFFC). One non-maskable unimplemented page1 op-code trap (SPARE) vector (at address vector base1 + 0x0001F8). One non-maskable unimplemented page2 op-code trap (TRAP) vector (at address vector base1 + 0x0001F4). One non-maskable software interrupt request (SWI) vector (at address vector base1 + 0x0001F0). One non-maskable system call interrupt request (SYS) vector (at address vector base1 + 0x00001EC). One non-maskable machine exception vector request (at address vector base1 + 0x0001E8. One spurious interrupt vector (at address vector base1 + 0x0001DC). One X-bit maskable interrupt vector request associated with XIRQ (at address vector base1 + 0x0001D8). One I-bit maskable interrupt vector request associated with IRQ (at address vector base1 + 0x0001D4). up to 113 additional I-bit maskable interrupt vector requests (at addresses vector base1 + 0x000010 .. vector base + 0x0001D0). Each I-bit maskable interrupt request has a configurable priority level. I-bit maskable interrupts can be nested, depending on their priority levels. Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or whenever XIRQ is asserted, even if X interrupt is masked. Modes of Operation Run mode This is the basic mode of operation. Wait mode In wait mode, the S12ZINTV0 module is capable of waking up the CPU if an eligible CPU exception occurs. Please refer to Section 6.5.3, “Wake Up from Stop or Wait Mode” for details. Stop Mode 1. The vector base is a 24-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as the upper 15 bits of the address) and 0x000 (used as the lower 9 bits of the address). MC912ZVL Family Reference Manual, Rev. 2.48 168 NXP Semiconductors Interrupt (S12ZINTV0) In stop mode, the S12ZINTV0 module is capable of waking up the CPU if an eligible CPU exception occurs. Please refer to Section 6.5.3, “Wake Up from Stop or Wait Mode” for details. 6.1.4 Block Diagram Figure 6-1 shows a block diagram of the S12ZINTV0 module. Peripheral Interrupt Requests Wake Up CPU Interrupt Requests One Set Per Channel (Up to 117 Channels) PRIOLVL2 PRIOLVL1 PRIOLVL0 Priority Level Filter PRIOLVLnPriority Level = configuration bits from the associated channel configuration register IVBR = Interrupt Vector Base IPL = Interrupt Processing Level Highest Pending IPL IVBR New IPL To CPU Non I Bit Maskable Channels Priority Decoder Vector Address Current IPL Figure 6-1. S12ZINTV0 Block Diagram 6.2 External Signal Description The S12ZINTV0 module has no external signals. 6.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the S12ZINTV0 module. 6.3.1 Module Memory Map Table 6-3 gives an overview over all S12ZINTV0 module registers. Table 6-3. S12ZINTV0 Memory Map Address Use Access MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 169 Interrupt (S12ZINTV0) Table 6-3. S12ZINTV0 Memory Map 6.3.2 0x000010–0x000011 Interrupt Vector Base Register (IVBR) R/W 0x000012–0x000016 RESERVED — 0x000017 Interrupt Request Configuration Address Register (INT_CFADDR) R/W 0x000018 Interrupt Request Configuration Data Register 0 (INT_CFDATA0) R/W 0x000019 Interrupt Request Configuration Data Register 1 (INT_CFDATA1) R/W 0x00001A Interrupt Request Configuration Data Register 2 (INT_CFDATA2 R/W 0x00001B Interrupt Request Configuration Data Register 3 (INT_CFDATA3) R/W 0x00001C Interrupt Request Configuration Data Register 4 (INT_CFDATA4) R/W 0x00001D Interrupt Request Configuration Data Register 5 (INT_CFDATA5) R/W 0x00001E Interrupt Request Configuration Data Register 6 (INT_CFDATA6) R/W 0x00001F Interrupt Request Configuration Data Register 7 (INT_CFDATA7) R/W Register Descriptions This section describes in address order all the S12ZINTV0 module registers and their individual bits. Address Register Name 0x000010 IVBR Bit 7 6 5 R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0x000019 INT_CFDATA1 R W 0x00001A INT_CFDATA2 R 1 Bit 0 0 INT_CFADDR[6:3] W 0x000018 INT_CFDATA0 R 2 IVB_ADDR[7:1] W 0x000017 INT_CFADDR R 3 IVB_ADDR[15:8] W 0x000011 4 W 0 0 PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] = Unimplemented or Reserved Figure 6-2. S12ZINTV0 Register Summary MC912ZVL Family Reference Manual, Rev. 2.48 170 NXP Semiconductors Interrupt (S12ZINTV0) Register Name Address 0x00001B INT_CFDATA3 R Bit 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 PRIOLVL[2:0] W 0x00001C INT_CFDATA4 R PRIOLVL[2:0] W 0x00001D INT_CFDATA5 R PRIOLVL[2:0] W 0x00001E INT_CFDATA6 R PRIOLVL[2:0] W 0x00001F INT_CFDATA7 R Bit 0 PRIOLVL[2:0] W = Unimplemented or Reserved Figure 6-2. S12ZINTV0 Register Summary 6.3.2.1 Interrupt Vector Base Register (IVBR) Address: 0x000010 15 14 13 12 11 10 R 8 7 6 5 4 3 2 1 1 1 1 1 1 1 1 1 1 0 0 IVB_ADDR[15:1] W Reset 9 1 1 1 1 1 1 0 Figure 6-3. Interrupt Vector Base Register (IVBR) Read: Anytime Write: Anytime Table 6-4. IVBR Field Descriptions Field Description 15–1 IVB_ADDR [15:1] Interrupt Vector Base Address Bits — These bits represent the upper 15 bits of all vector addresses. Out of reset these bits are set to 0xFFFE (i.e., vectors are located at 0xFFFE00–0xFFFFFF). Note: A system reset will initialize the interrupt vector base register with “0xFFFE” before it is used to determine the reset vector address. Therefore, changing the IVBR has no effect on the location of the reset vector (0xFFFFFC–0xFFFFFF). MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 171 Interrupt (S12ZINTV0) 6.3.2.2 Interrupt Request Configuration Address Register (INT_CFADDR) Address: 0x000017 7 R 6 0 4 3 INT_CFADDR[6:3] W Reset 5 0 0 0 0 1 2 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 6-4. Interrupt Configuration Address Register (INT_CFADDR) Read: Anytime Write: Anytime Table 6-5. INT_CFADDR Field Descriptions Field Description 6–3 Interrupt Request Configuration Data Register Select Bits — These bits determine which of the 128 INT_CFADDR[6:3] configuration data registers are accessible in the 8 register window at INT_CFDATA0–7. The hexadecimal value written to this register corresponds to the upper 4 bits of the vector number (multiply with 4 to get the vector address offset). If, for example, the value 0x70 is written to this register, the configuration data register block for the 8 interrupt vector requests starting with vector at address (vector base + (0x70*4 = 0x0001C0)) is selected and can be accessed as INT_CFDATA0–7. 6.3.2.3 Interrupt Request Configuration Data Registers (INT_CFDATA0–7) The eight register window visible at addresses INT_CFDATA0–7 contains the configuration data for the block of eight interrupt requests (out of 128) selected by the interrupt configuration address register (INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt configuration data register of the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt configuration data register of the vector with the highest address, respectively. Address: 0x000018 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 PRIOLVL[2:0] W Reset 1 0 0 11 = Unimplemented or Reserved Figure 6-5. Interrupt Request Configuration Data Register 0 (INT_CFDATA0) 1 Please refer to the notes following the PRIOLVL[2:0] description below. MC912ZVL Family Reference Manual, Rev. 2.48 172 NXP Semiconductors Interrupt (S12ZINTV0) Address: 0x000019 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 PRIOLVL[2:0] W Reset 1 0 0 11 = Unimplemented or Reserved Figure 6-6. Interrupt Request Configuration Data Register 1 (INT_CFDATA1) 1 Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x00001A R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 PRIOLVL[2:0] W Reset 1 0 0 11 = Unimplemented or Reserved Figure 6-7. Interrupt Request Configuration Data Register 2 (INT_CFDATA2) 1 Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x00001B R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 PRIOLVL[2:0] W Reset 1 0 0 11 = Unimplemented or Reserved Figure 6-8. Interrupt Request Configuration Data Register 3 (INT_CFDATA3) 1 Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x00001C R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 PRIOLVL[2:0] W Reset 1 0 0 11 = Unimplemented or Reserved Figure 6-9. Interrupt Request Configuration Data Register 4 (INT_CFDATA4) 1 Please refer to the notes following the PRIOLVL[2:0] description below. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 173 Interrupt (S12ZINTV0) Address: 0x00001D R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 PRIOLVL[2:0] W Reset 1 0 0 11 = Unimplemented or Reserved Figure 6-10. Interrupt Request Configuration Data Register 5 (INT_CFDATA5) 1 Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x00001E R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 PRIOLVL[2:0] W Reset 1 0 0 11 = Unimplemented or Reserved Figure 6-11. Interrupt Request Configuration Data Register 6 (INT_CFDATA6) 1 Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x00001F R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 PRIOLVL[2:0] W Reset 1 0 0 11 = Unimplemented or Reserved Figure 6-12. Interrupt Request Configuration Data Register 7 (INT_CFDATA7) 1 Please refer to the notes following the PRIOLVL[2:0] description below. Read: Anytime Write: Anytime MC912ZVL Family Reference Manual, Rev. 2.48 174 NXP Semiconductors Interrupt (S12ZINTV0) Table 6-6. INT_CFDATA0–7 Field Descriptions Field Description 2–0 Interrupt Request Priority Level Bits — The PRIOLVL[2:0] bits configure the interrupt request priority level of PRIOLVL[2:0] the associated interrupt request. Out of reset all interrupt requests are enabled at the lowest active level (“1”). Please also refer to Table 6-7 for available interrupt request priority levels. Note: Write accesses to configuration data registers of unused interrupt channels are ignored and read accesses return all 0s. For information about what interrupt channels are used in a specific MCU, please refer to the Device Reference Manual for that MCU. Note: When non I-bit maskable request vectors are selected, writes to the corresponding INT_CFDATA registers are ignored and read accesses return all 0s. The corresponding vectors do not have configuration data registers associated with them. Note: Write accesses to the configuration register for the spurious interrupt vector request (vector base + 0x0001DC) are ignored and read accesses return 0x07 (request is handled by the CPU, PRIOLVL = 7). Table 6-7. Interrupt Priority Levels Priority low high 6.4 PRIOLVL2 PRIOLVL1 PRIOLVL0 Meaning 0 0 0 Interrupt request is disabled 0 0 1 Priority level 1 0 1 0 Priority level 2 0 1 1 Priority level 3 1 0 0 Priority level 4 1 0 1 Priority level 5 1 1 0 Priority level 6 1 1 1 Priority level 7 Functional Description The S12ZINTV0 module processes all exception requests to be serviced by the CPU module. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below. 6.4.1 S12Z Exception Requests The CPU handles both reset requests and interrupt requests. The S12ZINTV0 module contains registers to configure the priority level of each I-bit maskable interrupt request which can be used to implement an interrupt priority scheme. This also includes the possibility to nest interrupt requests. A priority decoder is used to evaluate the relative priority of pending interrupt requests. 6.4.2 Interrupt Prioritization After system reset all I-bit maskable interrupt requests are configured to be enabled, are set up to be handled by the CPU and have a pre-configured priority level of 1. Exceptions to this rule are the non-maskable interrupt requests and the spurious interrupt vector request at (vector base + 0x0001DC) MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 175 Interrupt (S12ZINTV0) which cannot be disabled, are always handled by the CPU and have a fixed priority levels. A priority level of 0 effectively disables the associated I-bit maskable interrupt request. If more than one interrupt request is configured to the same interrupt priority level the interrupt request with the higher vector address wins the prioritization. The following conditions must be met for an I-bit maskable interrupt request to be processed. 1. The local interrupt enabled bit in the peripheral module must be set. 2. The setup in the configuration register associated with the interrupt request channel must meet the following conditions: a) The priority level must be set to non zero. b) The priority level must be greater than the current interrupt processing level in the condition code register (CCW) of the CPU (PRIOLVL[2:0] > IPL[2:0]). 3. The I-bit in the condition code register (CCW) of the CPU must be cleared. 4. There is no access violation interrupt request pending. 5. There is no SYS, SWI, SPARE, TRAP, Machine Exception or XIRQ request pending. NOTE All non I-bit maskable interrupt requests always have higher priority than I-bit maskable interrupt requests. If an I-bit maskable interrupt request is interrupted by a non I-bit maskable interrupt request, the currently active interrupt processing level (IPL) remains unaffected. It is possible to nest non I-bit maskable interrupt requests, e.g., by nesting SWI, SYS or TRAP calls. 6.4.2.1 Interrupt Priority Stack The current interrupt processing level (IPL) is stored in the condition code register (CCW) of the CPU. This way the current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The new IPL is copied to the CCW from the priority level of the highest priority active interrupt request channel which is configured to be handled by the CPU. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored from the stack by executing the RTI instruction. 6.4.3 Priority Decoder The S12ZINTV0 module contains a priority decoder to determine the relative priority for all interrupt requests pending for the CPU. A CPU interrupt vector is not supplied until the CPU requests it. Therefore, it is possible that a higher priority interrupt request could override the original exception which caused the CPU to request the vector. In this case, the CPU will receive the highest priority vector and the system will process this exception first instead of the original request. If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the CPU defaults to that of the spurious interrupt vector. MC912ZVL Family Reference Manual, Rev. 2.48 176 NXP Semiconductors Interrupt (S12ZINTV0) NOTE Care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not get processed at all or the result may be a spurious interrupt request (vector at address (vector base + 0x0001DC)). 6.4.4 Reset Exception Requests The S12ZINTV0 module supports one system reset exception request. The different reset types are mapped to this vector (for details please refer to the Clock and Power Management Unit module (CPMU)): 1. Pin reset 2. Power-on reset 3. Low-voltage reset 4. Clock monitor reset request 5. COP watchdog reset request 6.4.5 Exception Priority The priority (from highest to lowest) and address of all exception vectors issued by the S12ZINTV0 module upon request by the CPU are shown in Table 6-8. Generally, all non-maskable interrupts have higher priorities than maskable interrupts. Please note that between the four software interrupts (Unimplemented op-code trap page1/page2 requests, SWI request, SYS request) there is no real priority defined since they cannot occur simultaneously (the S12Z CPU executes one instruction at a time). Table 6-8. Exception Vector Map and Priority Vector Address1 0xFFFFFC 1 Source Pin reset, power-on reset, low-voltage reset, clock monitor reset, COP watchdog reset (Vector base + 0x0001F8) Unimplemented page1 op-code trap (SPARE) vector request (Vector base + 0x0001F4) Unimplemented page2 op-code trap (TRAP) vector request (Vector base + 0x0001F0) Software interrupt instruction (SWI) vector request (Vector base + 0x0001EC) System call interrupt instruction (SYS) vector request (Vector base + 0x0001E8) Machine exception vector request (Vector base + 0x0001E4) Reserved (Vector base + 0x0001E0) Reserved (Vector base + 0x0001DC) Spurious interrupt (Vector base + 0x0001D8) XIRQ interrupt request (Vector base + 0x0001D4) IRQ interrupt request (Vector base + 0x000010 .. Vector base + 0x0001D0) Device specific I-bit maskable interrupt sources (priority determined by the associated configuration registers, in descending order) 24 bits vector address based MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 177 Interrupt (S12ZINTV0) 6.4.6 Interrupt Vector Table Layout The interrupt vector table contains 128 entries, each 32 bits (4 bytes) wide. Each entry contains a 24-bit address (3 bytes) which is stored in the 3 low-significant bytes of the entry. The content of the most significant byte of a vector-table entry is ignored. Figure 6-13 illustrates the vector table entry format. Bits [31:24] [23:0] (unused) ISR Address Figure 6-13. Interrupt Vector Table Entry 6.5 6.5.1 Initialization/Application Information Initialization After system reset, software should: • Initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xFFFE00–0xFFFFFB). • Initialize the interrupt processing level configuration data registers (INT_CFADDR, INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels. It might be a good idea to disable unused interrupt requests. • Enable I-bit maskable interrupts by clearing the I-bit in the CCW. • Enable the X-bit maskable interrupt by clearing the X-bit in the CCW (if required). 6.5.2 Interrupt Nesting The interrupt request priority level scheme makes it possible to implement priority based interrupt request nesting for the I-bit maskable interrupt requests. • I-bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority, so that there can be up to seven nested I-bit maskable interrupt requests at a time (refer to Figure 6-14 for an example using up to three nested interrupt requests). I-bit maskable interrupt requests cannot be interrupted by other I-bit maskable interrupt requests per default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the I-bit in the CCW (CLI). After clearing the I-bit, I-bit maskable interrupt requests with higher priority can interrupt the current ISR. An ISR of an interruptible I-bit maskable interrupt request could basically look like this: • Service interrupt, e.g., clear interrupt flags, copy data, etc. • Clear I-bit in the CCW by executing the CPU instruction CLI (thus allowing interrupt requests with higher priority) • Process data • Return from interrupt by executing the instruction RTI MC912ZVL Family Reference Manual, Rev. 2.48 178 NXP Semiconductors Interrupt (S12ZINTV0) 0 Stacked IPL IPL in CCW 0 0 4 0 0 0 4 7 4 3 1 0 7 6 Processing Levels RTI L7 5 4 RTI 3 2 L3 (Pending) L4 1 L1 (Pending) 0 RTI RTI Reset Figure 6-14. Interrupt Processing Example 6.5.3 6.5.3.1 Wake Up from Stop or Wait Mode CPU Wake Up from Stop or Wait Mode Every I-bit maskable interrupt request which is configured to be handled by the CPU is capable of waking the MCU from stop or wait mode. Additionally machine exceptions can wake-up the MCU from stop or wait mode. To determine whether an I-bit maskable interrupts is qualified to wake up the CPU or not, the same settings as in normal run mode are applied during stop or wait mode: • If the I-bit in the CCW is set, all I-bit maskable interrupts are masked from waking up the MCU. • An I-bit maskable interrupt is ignored if it is configured to a priority level below or equal to the current IPL in CCW. The X-bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if the X-bit in CCW is set1. If the X-bit maskable interrupt request is used to wake-up the MCU with the X-bit in the CCW set, the associated ISR is not called. The CPU then resumes program execution with the instruction following the WAI or STOP instruction. This feature works following the same rules like any interrupt request, i.e. care must be taken that the X-bit maskable interrupt request used for wake-up remains active at least until the system begins execution of the instruction following the WAI or STOP instruction; otherwise, wake-up may not occur. 1. The capability of the XIRQ pin to wake-up the MCU with the X bit set may not be available if, for example, the XIRQ pin is shared with other peripheral modules on the device. Please refer to the Port Integration Module (PIM) section of the MCU reference manual for details. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 179 Interrupt (S12ZINTV0) MC912ZVL Family Reference Manual, Rev. 2.48 180 NXP Semiconductors Chapter 7 S12Z DebugLite (S12ZDBGV3) Table 7-1. Revision History Table Revision Number Revision Date Sections Affected 3.02 05.JUL.2012 Section 7.3.2.6, “Debug Event Flag Register (DBGEFR) 3.03 16.NOV.2012 Section 7.5.1, “Avoiding Unintended Breakpoint Re-triggering 3.04 19.DEC.2012 General Formatting corrections 3.05 19.APR.2013 General Specified DBGC1[0] reserved bit as read only 3.06 15.JUL.2013 Section 7.3.2, “Register Descriptions 7.1 Description Of Changes Removed ME2 flag from DBGEFR Modified step over breakpoint information Added explicit names to state control register bit fields Introduction The DBG module provides on-chip breakpoints with flexible triggering capability to allow non-intrusive debug of application software. The DBG module is optimized for the S12Z architecture and allows debugging of CPU module operations. Typically the DBG module is used in conjunction with the BDC module, whereby the user configures the DBG module for a debugging session over the BDC interface. Once configured the DBG module is armed and the device leaves active BDM returning control to the user program, which is then monitored by the DBG module. Alternatively the DBG module can be configured over a serial interface using SWI routines. 7.1.1 Glossary Table 7-2. Glossary Of Terms Term Definition COF Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt PC Program Counter MC9S12ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 181 S12Z DebugLite (S12ZDBGV3) Table 7-2. Glossary Of Terms Term Definition BDM Background Debug Mode. In this mode CPU application code execution is halted. Execution of BDC “active BDM” commands is possible. BDC Background Debug Controller WORD 16-bit data entity CPU S12Z CPU module 7.1.2 Overview The comparators monitor the bus activity of the CPU. A single comparator match or a series of matches can generate breakpoints. A state sequencer determines if the correct series of matches occurs. Similarly an external event can generate breakpoints. 7.1.3 • • • • Features Three comparators (A, B, and D) — Comparator A compares the full address bus and full 32-bit data bus — Comparator A features a data bus mask register — Comparators B and D compare the full address bus only — Each comparator can be configured to monitor PC addresses or addresses of data accesses — Each comparator can select either read or write access cycles — Comparator matches can force state sequencer state transitions Three comparator modes — Simple address/data comparator match mode — Inside address range mode, Addmin  Address Addmax — Outside address range match mode, Address Addminor Address  Addmax State sequencer control — State transitions forced by comparator matches — State transitions forced by software write to TRIG — State transitions forced by an external event The following types of breakpoints — CPU breakpoint entering active BDM on breakpoint (BDM) — CPU breakpoint executing SWI on breakpoint (SWI) — MC912ZVL Family Reference Manual, Rev. 2.48 182 NXP Semiconductors S12Z DebugLite (S12ZDBGV3) 7.1.4 Modes of Operation The DBG module can be used in all MCU functional modes. The DBG module can issue breakpoint requests to force the device to enter active BDM or an SWI ISR. The BDC BACKGROUND command is also handled by the DBG to force the device to enter active BDM. When the device enters active BDM through a BACKGROUND command with the DBG module armed, the DBG remains armed. 7.1.5 Block Diagram B EXTERNAL EVENT TRIG BUS INTERFACE CPU BUS COMPARATOR A COMPARATOR B COMPARATOR D COMPARATOR MATCH CONTROL REGISTERS MATCH0 MATCH1 STATE SEQUENCER AND EVENT CONTROL BREAKPOINT REQUESTS MATCH3 Figure 7-1. Debug Module Block Diagram 7.2 7.2.1 External Signal Description External Event Input The DBG module features an external event input signal, DBGEEV. The mapping of this signal to a device pin is specified in the device specific documentation. This function can be enabled and configured by the EEVE field in the DBGC1 control register. This signal is input only and allows an external event to force a state sequencer transition. With the external event function enabled, a falling edge at the external event pin constitutes an event. Rising edges have no effect. The maximum frequency of events is half the internal core bus frequency. The function is explained in the EEVE field description. NOTE Due to input pin synchronization circuitry, the DBG module sees external events 2 bus cycles after they occur at the pin. Thus an external event occurring less than 2 bus cycles before arming the DBG module is perceived to occur whilst the DBG is armed. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 183 S12Z DebugLite (S12ZDBGV3) When the device is in stop mode the synchronizer clocks are disabled and the external events are ignored. 7.3 7.3.1 Memory Map and Registers Module Memory Map A summary of the registers associated with the DBG module is shown in Figure 7-2. Detailed descriptions of the registers and bits are given in the subsections that follow. Address Name Bit 7 6 5 4 3 2 1 0x0100 DBGC1 ARM 0 TRIG reserved BDMBP BRKCPU reserved EEVE1 0x0101 DBGC2 R W 0 0 0 0 0 0 0x0102 Reserved R W 0 0 0 0 0 0 0 0 0x0103 Reserved R W 0 0 0 0 0 0 0 0 0x0104 Reserved R W 0 0 0 0 0 0 0 0 0x0105 Reserved R W 0 0 0 0 0 0 0 0 0x0106 Reserved R W 0 0 0 0 0 0 0 0 0x0107 DBGSCR1 R W C3SC1 C3SC0 0 0 C1SC1 C1SC0 C0SC1 C0SC0 0x0108 DBGSCR2 R W C3SC1 C3SC0 0 0 C1SC1 C1SC0 C0SC1 C0SC0 0x0109 DBGSCR3 R W C3SC1 C3SC0 0 0 C1SC1 C1SC0 C0SC1 C0SC0 0x010A DBGEFR R W 0 TRIGF 0 EEVF ME3 0 ME1 ME0 0x010B DBGSR R W 0 0 0 0 0 SSF2 SSF1 SSF0 0x010C0x010F Reserved R W 0 0 0 0 0 0 0 0 0x0110 DBGACTL R W 0 NDB INST RW RWE reserved COMPE R W 0 Bit 0 0 ABCM Figure 7-2. Quick Reference to DBG Registers MC912ZVL Family Reference Manual, Rev. 2.48 184 NXP Semiconductors S12Z DebugLite (S12ZDBGV3) Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x01110x0114 Reserved R W 0 0 0 0 0 0 0 0 0x0115 DBGAAH R W DBGAA[23:16] 0x0116 DBGAAM R W DBGAA[15:8] 0x0117 DBGAAL R W DBGAA[7:0] 0x0118 DBGAD0 R W Bit 31 30 29 28 27 26 25 Bit 24 0x0119 DBGAD1 R W Bit 23 22 21 20 19 18 17 Bit 16 0x011A DBGAD2 R W Bit 15 14 13 12 11 10 9 Bit 8 0x011B DBGAD3 R W Bit 7 6 5 4 3 2 1 Bit 0 0x011C DBGADM0 R W Bit 31 30 29 28 27 26 25 Bit 24 0x011D DBGADM1 R W Bit 23 22 21 20 19 18 17 Bit 16 0x011E DBGADM2 R W Bit 15 14 13 12 11 10 9 Bit 8 0x011F DBGADM3 R W Bit 7 6 5 4 3 2 1 Bit 0 0x0120 DBGBCTL R W 0 0 RW RWE reserved COMPE 0x01210x0124 Reserved R W 0 0 0 0 0 0 0x0125 DBGBAH R W DBGBA[23:16] 0x0126 DBGBAM R W DBGBA[15:8] 0x0127 DBGBAL R W DBGBA[7:0] 0x01280x012F Reserved R W 0 0 0 0 0 0 0 0 0x01300x013F Reserved R W 0 0 0 0 0 0 0 0 INST 0 0 0 Figure 7-2. Quick Reference to DBG Registers MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 185 S12Z DebugLite (S12ZDBGV3) Address Name Bit 7 6 0x0140 DBGDCTL 0x01410x0144 R W 0 0 Reserved R W 0 0 0x0145 DBGDAH R W DBGDA[23:16] 0x0146 DBGDAM R W DBGDA[15:8] 0x0147 DBGDAL R W DBGDA[7:0] 0x01480x017F Reserved R W 0 0 5 4 INST 0 0 0 0 0 3 2 1 Bit 0 RW RWE reserved COMPE 0 0 0 0 0 0 0 0 Figure 7-2. Quick Reference to DBG Registers 7.3.2 Register Descriptions This section consists of the DBG register descriptions in address order. When ARM is set in DBGC1, the only bits in the DBG module registers that can be written are ARM, and TRIG 7.3.2.1 Debug Control Register 1 (DBGC1) Address: 0x0100 7 0x0100 Reset 6 ARM 0 0 TRIG 0 5 4 3 2 1 reserved BDMBP BRKCPU reserved EEVE1 0 0 0 0 0 0 0 0 Figure 7-3. Debug Control Register (DBGC1) Read: Anytime Write: Bit 7 Anytime . An ongoing profiling session must be finished before DBG can be armed again. Bit 6 can be written anytime but always reads back as 0. Bits 5:0 anytime DBG is not armed. NOTE On a write access to DBGC1 and simultaneous hardware disarm from an internal event, the hardware disarm has highest priority, clearing the ARM bit and generating a breakpoint, if enabled. MC912ZVL Family Reference Manual, Rev. 2.48 186 NXP Semiconductors S12Z DebugLite (S12ZDBGV3) NOTE When disarming the DBG by clearing ARM with software, the contents of bits[5:0] are not affected by the write, since up until the write operation, ARM = 1 preventing these bits from being written. These bits must be cleared using a second write if required. Table 7-3. DBGC1 Field Descriptions Field Description 7 ARM Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by register writes and is automatically cleared when the state sequencer returns to State0 on completing a debugging session. On setting this bit the state sequencer enters State1. 0 Debugger disarmed. No breakpoint is generated when clearing this bit by software register writes. 1 Debugger armed 6 TRIG Immediate Trigger Request Bit — This bit when written to 1 requests an immediate transition to final state independent of comparator status. This bit always reads back a 0. Writing a 0 to this bit has no effect. 0 No effect. 1 Force state sequencer immediately to final state. 4 BDMBP Background Debug Mode Enable — This bit determines if a CPU breakpoint causes the system to enter Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDC is not enabled, then no breakpoints are generated. 0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint. 1 Breakpoint to BDM, if BDC enabled. Otherwise no breakpoint. 3 BRKCPU CPU Breakpoint Enable — The BRKCPU bit controls whether the debugger requests a breakpoint to CPU upon transitions to State0. Please refer to Section 7.4.5, “Breakpoints for further details. 0 Breakpoints disabled 1 Breakpoints enabled 1 EEVE1 7.3.2.2 External Event Enable — The EEVE1 bit enables the external event function. 0 External event function disabled. 1 External event is mapped to the state sequencer, replacing comparator channel 3 Debug Control Register2 (DBGC2) Address: 0x0101 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 1 ABCM W Reset 0 0 0 0 = Unimplemented or Reserved Figure 7-4. Debug Control Register2 (DBGC2) Read: Anytime. Write: Anytime the module is disarmed. This register configures the comparators for range matching. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 187 S12Z DebugLite (S12ZDBGV3) Table 7-4. DBGC2 Field Descriptions Field Description 1–0 ABCM[1:0] A and B Comparator Match Control — These bits determine the A and B comparator match mapping as described in Table 7-5. Table 7-5. ABCM Encoding 1 ABCM Description 00 Match0 mapped to comparator A match....... Match1 mapped to comparator B match. 01 Match0 mapped to comparator A/B inside range....... Match1 disabled. 10 Match0 mapped to comparator A/B outside range....... Match1 disabled. 11 Reserved1 Currently defaults to Match0 mapped to inside range: Match1 disabled 7.3.2.3 Debug State Control Register 1 (DBGSCR1) Address: 0x0107 7 R W Reset 6 C3SC1 C3SC0 0 0 5 4 0 0 0 0 3 2 1 0 C1SC1 C1SC0 C0SC1 C0SC0 0 0 0 0 Figure 7-6. Debug State Control Register 1 (DBGSCR1) Read: Anytime. Write: If DBG is not armed. The state control register 1 selects the targeted next state whilst in State1. The matches refer to the outputs of the comparator match control logic as depicted in Figure 7-1 and described in Section 7.3.2.8, “Debug Comparator A Control Register (DBGACTL)”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 7-7. DBGSCR1 Field Descriptions Field Description 1–0 C0SC[1:0] Channel 0 State Control. These bits select the targeted next state whilst in State1 following a match0. 3–2 C1SC[1:0] Channel 1 State Control. These bits select the targeted next state whilst in State1 following a match1. 7–6 C3SC[1:0] Channel 3 State Control. If EEVE !=10, these bits select the targeted next state whilst in State1 following a match3. If EEVE = 10, these bits select the targeted next state whilst in State1 following an external event. MC912ZVL Family Reference Manual, Rev. 2.48 188 NXP Semiconductors S12Z DebugLite (S12ZDBGV3) Table 7-8. State1 Match State Sequencer Transitions CxSC[1:0] Function 00 Match has no effect 01 Match forces sequencer to State2 10 Match forces sequencer to State3 11 Match forces sequencer to Final State In the case of simultaneous matches, the match on the higher channel number (3...0) has priority. 7.3.2.4 Debug State Control Register 2 (DBGSCR2) Address: 0x0108 7 R W Reset 6 C3SC1 C3SC0 0 0 5 4 0 0 0 0 3 2 1 0 C1SC1 C1SC0 C0SC1 C0SC0 0 0 0 0 Figure 7-7. Debug State Control Register 2 (DBGSCR2) Read: Anytime. Write: If DBG is not armed The state control register 2 selects the targeted next state whilst in State2. The matches refer to the outputs of the comparator match control logic as depicted in Figure 7-1 and described in Section 7.3.2.8, “Debug Comparator A Control Register (DBGACTL)”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 7-9. DBGSCR2 Field Descriptions Field Description 1–0 C0SC[1:0] Channel 0 State Control. These bits select the targeted next state whilst in State2 following a match0. 3–2 C1SC[1:0] Channel 1 State Control. These bits select the targeted next state whilst in State2 following a match1. 7–6 C3SC[1:0] Channel 3 State Control. If EEVE !=10, these bits select the targeted next state whilst in State2 following a match3. If EEVE =10, these bits select the targeted next state whilst in State2 following an external event. Table 7-10. State2 Match State Sequencer Transitions CxSC[1:0] Function 00 Match has no effect 01 Match forces sequencer to State1 10 Match forces sequencer to State3 11 Match forces sequencer to Final State In the case of simultaneous matches, the match on the higher channel number (3...0) has priority. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 189 S12Z DebugLite (S12ZDBGV3) 7.3.2.5 Debug State Control Register 3 (DBGSCR3) Address: 0x0109 R W Reset 7 6 C3SC1 C3SC0 0 0 5 4 0 0 0 0 3 2 1 0 C1SC1 C1SC0 C0SC1 C0SC0 0 0 0 0 Figure 7-8. Debug State Control Register 3 (DBGSCR3) Read: Anytime. Write: If DBG is not armed. The state control register three selects the targeted next state whilst in State3. The matches refer to the outputs of the comparator match control logic as depicted in Figure 7-1 and described in Section 7.3.2.8, “Debug Comparator A Control Register (DBGACTL)”. Comparators must be enabled by setting the comparator enable bit in the associated DBGxCTL control register. Table 7-11. DBGSCR3 Field Descriptions Field Description 1–0 C0SC[1:0] Channel 0 State Control. These bits select the targeted next state whilst in State3 following a match0. 3–2 C1SC[1:0] Channel 1 State Control. These bits select the targeted next state whilst in State3 following a match1. 7–6 C3SC[1:0] Channel 3 State Control. If EEVE !=10, these bits select the targeted next state whilst in State3 following a match3. If EEVE =10, these bits select the targeted next state whilst in State3 following an external event. Table 7-12. State3 Match State Sequencer Transitions CxSC[1:0] Function 00 Match has no effect 01 Match forces sequencer to State1 10 Match forces sequencer to State2 11 Match forces sequencer to Final State In the case of simultaneous matches, the match on the higher channel number (3....0) has priority. 7.3.2.6 Debug Event Flag Register (DBGEFR) Address: 0x010A R 7 6 5 4 3 2 1 0 0 TRIGF 0 EEVF ME3 0 ME1 ME0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 7-9. Debug Event Flag Register (DBGEFR) MC912ZVL Family Reference Manual, Rev. 2.48 190 NXP Semiconductors S12Z DebugLite (S12ZDBGV3) Read: Anytime. Write: Never DBGEFR contains flag bits each mapped to events whilst armed. Should an event occur, then the corresponding flag is set. With the exception of TRIGF, the bits can only be set when the ARM bit is set. The TRIGF bit is set if a TRIG event occurs when ARM is already set, or if the TRIG event occurs simultaneous to setting the ARM bit.All other flags can only be cleared by arming the DBG module. Thus the contents are retained after a debug session for evaluation purposes. A set flag does not inhibit the setting of other flags. Table 7-13. DBGEFR Field Descriptions Field Description 6 TRIGF TRIG Flag — Indicates the occurrence of a TRIG event during the debug session. 0 No TRIG event 1 TRIG event 4 EEVF External Event Flag — Indicates the occurrence of an external event during the debug session. 0 No external event 1 External event 3–0 ME[3:0] Match Event[3:0]— Indicates a comparator match event on the corresponding comparator channel. 7.3.2.7 Debug Status Register (DBGSR) Address: 0x010B R 7 6 5 4 3 2 1 0 0 0 0 0 0 SSF2 SSF1 SSF0 — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset POR = Unimplemented or Reserved Figure 7-10. Debug Status Register (DBGSR) Read: Anytime. Write: Never. Table 7-14. DBGSR Field Descriptions Field Description 2–0 SSF[2:0] State Sequencer Flag Bits — The SSF bits indicate the current State Sequencer state. During a debug session on each transition to a new state these bits are updated. If the debug session is ended by software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer before disarming. If a debug session is ended by an internal event, then the state sequencer returns to State0 and these bits are cleared to indicate that State0 was entered during the session. On arming the module the state sequencer enters State1 and these bits are forced to SSF[2:0] = 001. See Table 7-15. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 191 S12Z DebugLite (S12ZDBGV3) Table 7-15. SSF[2:0] — State Sequence Flag Bit Encoding 7.3.2.8 SSF[2:0] Current State 000 State0 (disarmed) 001 State1 010 State2 011 State3 100 Final State 101,110,111 Reserved Debug Comparator A Control Register (DBGACTL) Address: 0x0110 7 R 6 0 W Reset 5 NDB INST 0 0 0 4 0 0 3 2 1 0 RW RWE reserved COMPE 0 0 0 0 = Unimplemented or Reserved Figure 7-11. Debug Comparator A Control Register Read: Anytime. Write: If DBG not armed. Table 7-16. DBGACTL Field Descriptions Field Description 6 NDB Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator register value or when the data bus differs from the register value. This bit is ignored if the INST bit in the same register is set. 0 Match on data bus equivalence to comparator register contents 1 Match on data bus difference to comparator register contents 5 INST Instruction Select — This bit configures the comparator to compare PC or data access addresses. 0 Comparator compares addresses of data accesses 1 Comparator compares PC address 3 RW 2 RWE 0 COMPE Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated comparator. The RW bit is ignored if RWE is clear or INST is set. 0 Write cycle is matched 1 Read cycle is matched Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated comparator. This bit is ignored when INST is set. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Enable Bit — Determines if comparator is enabled 0 The comparator is not enabled 1 The comparator is enabled MC912ZVL Family Reference Manual, Rev. 2.48 192 NXP Semiconductors S12Z DebugLite (S12ZDBGV3) Table 7-17 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if INST is set, because matches based on opcodes reaching the execution stage are data independent. Table 7-17. Read or Write Comparison Logic Table 7.3.2.9 RWE Bit RW Bit RW Signal Comment 0 x 0 RW not used in comparison 0 x 1 RW not used in comparison 1 0 0 Write match 1 0 1 No match 1 1 0 No match 1 1 1 Read match Debug Comparator A Address Register (DBGAAH, DBGAAM, DBGAAL) Address: 0x0115, DBGAAH 23 22 21 R 19 18 17 16 DBGAA[23:16] W Reset 20 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 Address: 0x0116, DBGAAM 15 R DBGAA[15:8] W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 Address: 0x0117, DBGAAL 7 R DBGAA[7:0] W Reset 0 0 0 0 Figure 7-12. Debug Comparator A Address Register Read: Anytime. Write: If DBG not armed. Table 7-18. DBGAAH, DBGAAM, DBGAAL Field Descriptions Field Description 23–16 DBGAA [23:16] Comparator Address Bits [23:16]— These comparator address bits control whether the comparator compares the address bus bits [23:16] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one 15–0 DBGAA [15:0] Comparator Address Bits [15:0]— These comparator address bits control whether the comparator compares the address bus bits [15:0] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 193 S12Z DebugLite (S12ZDBGV3) 7.3.2.10 Debug Comparator A Data Register (DBGAD) Address: 0x0118, 0x0119, 0x011A, 0x011B 31 R W W 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Reset R 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Reset 0 0 0 0 0 0 0 Figure 7-13. Debug Comparator A Data Register (DBGAD) Read: Anytime. Write: If DBG not armed. This register can be accessed with a byte resolution, whereby DBGAD0, DBGAD1, DBGAD2, DBGAD3 map to DBGAD[31:0] respectively. Table 7-19. DBGAD Field Descriptions Field Description 31–16 Bits[31:16] (DBGAD0, DBGAD1) Comparator Data Bits — These bits control whether the comparator compares the data bus bits to a logic one or logic zero. The comparator data bits are only used in comparison if the corresponding data mask bit is logic 1. 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one 15–0 Bits[15:0] (DBGAD2, DBGAD3) Comparator Data Bits — These bits control whether the comparator compares the data bus bits to a logic one or logic zero. The comparator data bits are only used in comparison if the corresponding data mask bit is logic 1. 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one 7.3.2.11 Debug Comparator A Data Mask Register (DBGADM) Address: 0x011C, 0x011D, 0x011E, 0x011F 31 R W Reset R W Reset 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 0 0 0 0 0 0 0 Figure 7-14. Debug Comparator A Data Mask Register (DBGADM) Read: Anytime. MC912ZVL Family Reference Manual, Rev. 2.48 194 NXP Semiconductors S12Z DebugLite (S12ZDBGV3) Write: If DBG not armed. This register can be accessed with a byte resolution, whereby DBGADM0, DBGADM1, DBGADM2, DBGADM3 map to DBGADM[31:0] respectively. Table 7-20. DBGADM Field Descriptions Field Description 31–16 Bits[31:16] (DBGADM0, DBGADM1) Comparator Data Mask Bits — These bits control whether the comparator compares the data bus bits to the corresponding comparator data compare bits. 0 Do not compare corresponding data bit 1 Compare corresponding data bit 15-0 Bits[15:0] (DBGADM2, DBGADM3) Comparator Data Mask Bits — These bits control whether the comparator compares the data bus bits to the corresponding comparator data compare bits. 0 Do not compare corresponding data bit 1 Compare corresponding data bit 7.3.2.12 Debug Comparator B Control Register (DBGBCTL) Address: 0x0120 R 7 6 0 0 0 0 W Reset 5 INST 0 4 0 0 3 2 1 0 RW RWE reserved COMPE 0 0 0 0 = Unimplemented or Reserved Figure 7-15. Debug Comparator B Control Register Read: Anytime. Write: If DBG not armed. Table 7-21. DBGBCTL Field Descriptions Field1 5 INST 3 RW 2 RWE 0 COMPE 1 Description Instruction Select — This bit configures the comparator to compare PC or data access addresses. 0 Comparator compares addresses of data accesses 1 Comparator compares PC address Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated comparator. The RW bit is ignored if RWE is clear or INST is set. 0 Write cycle is matched 1 Read cycle is matched Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated comparator. This bit is ignored when INST is set. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Enable Bit — Determines if comparator is enabled 0 The comparator is not enabled 1 The comparator is enabled If the ABCM field selects range mode comparisons, then DBGACTL bits configure the comparison, DBGBCTL is ignored. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 195 S12Z DebugLite (S12ZDBGV3) Table 7-22 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if INST is set, as matches based on instructions reaching the execution stage are data independent. Table 7-22. Read or Write Comparison Logic Table 7.3.2.13 RWE Bit RW Bit RW Signal Comment 0 x 0 RW not used in comparison 0 x 1 RW not used in comparison 1 0 0 Write match 1 0 1 No match 1 1 0 No match 1 1 1 Read match Debug Comparator B Address Register (DBGBAH, DBGBAM, DBGBAL) Address: 0x0125, DBGBAH 23 22 21 R 19 18 17 16 DBGBA[23:16] W Reset 20 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 Address: 0x0126, DBGBAM 15 R DBGBA[15:8] W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 Address: 0x0127, DBGBAL 7 R DBGBA[7:0] W Reset 0 0 0 0 Figure 7-16. Debug Comparator B Address Register Read: Anytime. Write: If DBG not armed. Table 7-23. DBGBAH, DBGBAM, DBGBAL Field Descriptions Field Description 23–16 DBGBA [23:16] Comparator Address Bits [23:16]— These comparator address bits control whether the comparator compares the address bus bits [23:16] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one 15–0 DBGBA [15:0] Comparator Address Bits[15:0]— These comparator address bits control whether the comparator compares the address bus bits [15:0] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC912ZVL Family Reference Manual, Rev. 2.48 196 NXP Semiconductors S12Z DebugLite (S12ZDBGV3) 7.3.2.14 Debug Comparator D Control Register (DBGDCTL) Address: 0x0140 R 7 6 0 0 5 0 0 INST W Reset 4 0 0 0 3 2 1 0 RW RWE reserved COMPE 0 0 0 0 = Unimplemented or Reserved Figure 7-17. Debug Comparator D Control Register Read: Anytime. Write: If DBG not armed. Table 7-24. DBGDCTL Field Descriptions Field1 5 INST 3 RW 2 RWE 0 COMPE 1 Description Instruction Select — This bit configures the comparator to compare PC or data access addresses. 0 Comparator compares addresses of data accesses 1 Comparator compares PC address Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated comparator. The RW bit is ignored if RWE is clear or INST is set. 0 Write cycle is matched 1 Read cycle is matched Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated comparator. This bit is ignored if INST is set. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Enable Bit — Determines if comparator is enabled 0 The comparator is not enabled 1 The comparator is enabled If the CDCM field selects range mode comparisons, then DBGCCTL bits configure the comparison, DBGDCTL is ignored. Table 7-25 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if INST is set, because matches based on opcodes reaching the execution stage are data independent. Table 7-25. Read or Write Comparison Logic Table RWE Bit RW Bit RW Signal Comment 0 x 0 RW not used in comparison 0 x 1 RW not used in comparison 1 0 0 Write match 1 0 1 No match 1 1 0 No match 1 1 1 Read match MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 197 S12Z DebugLite (S12ZDBGV3) 7.3.2.15 Debug Comparator D Address Register (DBGDAH, DBGDAM, DBGDAL) Address: 0x0145, DBGDAH 23 22 21 R 19 18 17 16 DBGDA[23:16] W Reset 20 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 Address: 0x0146, DBGDAM 15 R DBGDA[15:8] W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 Address: 0x0147, DBGDAL 7 R DBGDA[7:0] W Reset 0 0 0 0 Figure 7-18. Debug Comparator D Address Register Read: Anytime. Write: If DBG not armed. Table 7-26. DBGDAH, DBGDAM, DBGDAL Field Descriptions Field Description 23–16 DBGDA [23:16] Comparator Address Bits [23:16]— These comparator address bits control whether the comparator compares the address bus bits [23:16] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one 15–0 DBGDA [15:0] Comparator Address Bits[15:0]— These comparator address bits control whether the comparator compares the address bus bits [15:0] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one 7.4 Functional Description This section provides a complete functional description of the DBG module. 7.4.1 DBG Operation The DBG module operation is enabled by setting ARM in DBGC1. When armed it can be used to generate breakpoints to the CPU. The DBG module is made up of comparators, control logic, and the state sequencer, Figure 7-1. The comparators monitor the bus activity of the CPU. Comparators can be configured to monitor opcode addresses (effectively the PC address) or data accesses. Comparators can be configured during data MC912ZVL Family Reference Manual, Rev. 2.48 198 NXP Semiconductors S12Z DebugLite (S12ZDBGV3) accesses to mask out individual data bus bits and to use R/W access qualification in the comparison. Comparators can be configured to monitor a range of addresses. When configured for data access comparisons, the match is generated if the address (and optionally data) of a data access matches the comparator value. Configured for monitoring opcode addresses, the match is generated when the associated opcode reaches the execution stage of the instruction queue, but before execution of that opcode. When a match with a comparator register value occurs, the associated control logic can force the state sequencer to another state (see Figure 7-19). The state sequencer can transition freely between the states 1, 2 and 3. On transition to Final State, a breakpoint can be generated and the state sequencer returns to state0, disarming the DBG. Independent of the comparators, state sequencer transitions can be forced by the external event input or by writing to the TRIG bit in the DBGC1 control register. 7.4.2 Comparator Modes The DBG contains three comparators, A, B, and D. Each comparator compares the address stored in DBGXAH, DBGXAM, and DBGXAL with the PC (opcode addresses) or selected address bus (data accesses). Furthermore, comparator A can compare the data buses to values stored in DBGXD3-0 and allow data bit masking. The comparators can monitor the buses for an exact address or an address range. The comparator configuration is controlled by the control register contents and the range control by the DBGC2 contents. The comparator control register also allows the type of data access to be included in the comparison through the use of the RWE and RW bits. The RWE bit controls whether the access type is compared for the associated comparator and the RW bit selects either a read or write access for a valid match. The INST bit in each comparator control register is used to determine the matching condition. By setting INST, the comparator matches opcode addresses, whereby the databus, data mask, RW and RWE bits are ignored. The comparator register must be loaded with the exact opcode address. The comparator can be configured to match memory access addresses by clearing the INST bit. Each comparator match can force a transition to another state sequencer state (see Section 7.4.3, “Events”). Once a successful comparator match has occurred, the condition that caused the original match is not verified again on subsequent matches. Thus if a particular data value is matched at a given address, this address may not contain that data value when a subsequent match occurs. Match[0, 1, 3] map directly to Comparators [A, B, D] respectively, except in range modes (see Section 7.3.2.2, “Debug Control Register2 (DBGC2)”). Comparator priority rules are described in the event priority section (Section 7.4.3.4, “Event Priorities”). MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 199 S12Z DebugLite (S12ZDBGV3) 7.4.2.1 Exact Address Comparator Match With range comparisons disabled, the match condition is an exact equivalence of address bus with the value stored in the comparator address registers. Qualification of the type of access (R/W) is also possible. Code may contain various access forms of the same address, for example a 16-bit access of ADDR[n] or byte access of ADDR[n+1] both access n+1. The comparators ensure that any access of the address defined by the comparator address register generates a match, as shown in the example of Table 7-27. Thus if the comparator address register contains ADDR[n+1] any access of ADDR[n+1] matches. This means that a 16-bit access of ADDR[n] or 32-bit access of ADDR[n-1] also match because they also access ADDR[n+1]. The right hand columns show the contents of DBGxA that would match for each access. Table 7-27. Comparator Address Bus Matches Access Address ADDR[n] ADDR[n+1] ADDR[n+2] ADDR[n+3] 32-bit ADDR[n] Match Match Match Match 16-bit ADDR[n] Match Match No Match No Match 16-bit ADDR[n+1] No Match Match Match No Match 8-bit ADDR[n] Match No Match No Match No Match If the comparator INST bit is set, the comparator address register contents are compared with the PC, the data register contents and access type bits are ignored. The comparator address register must be loaded with the address of the first opcode byte. 7.4.2.2 Address and Data Comparator Match Comparator A features data comparators, for data access comparisons. The comparators do not evaluate if accessed data is valid. Accesses across aligned 32-bit boundaries are split internally into consecutive accesses. The data comparator mapping to accessed addresses for the CPU is shown in Table 7-28, whereby the Address column refers to the lowest 2 bits of the lowest accessed address. This corresponds to the most significant data byte. Table 7-28. Comparator Data Byte Alignment Address[1:0] Data Comparator 00 DBGxD0 01 DBGxD1 10 DBGxD2 11 DBGxD3 The fixed mapping of data comparator bytes to addresses within a 32-bit data field ensures data matches independent of access size. To compare a single data byte within the 32-bit field, the other bytes within that field must be masked using the corresponding data mask registers. This ensures that any access of that byte (32-bit,16-bit or 8-bit) with matching data causes a match. If no bytes are masked then the data comparator always compares all 32-bits and can only generate a match on a 32-bit access with correct 32-bit data value. In this case, 8-bit or 16-bit accesses within the 32-bit field cannot generate a match even MC912ZVL Family Reference Manual, Rev. 2.48 200 NXP Semiconductors S12Z DebugLite (S12ZDBGV3) if the contents of the addressed bytes match because all 32-bits must match. In Table 7-29 the Access Address column refers to the address bits[1:0] of the lowest accessed address (most significant data byte). Table 7-29. Data Register Use Dependency On CPU Access Type Memory Address[2:0] Case Access Address Access Size 000 001 010 011 DBGxD0 DBGxD1 DBGxD2 DBGxD3 DBGxD1 DBGxD2 DBGxD3 DBGxD0 DBGxD2 DBGxD3 DBGxD0 DBGxD1 DBGxD3 DBGxD0 DBGxD1 1 00 32-bit 2 01 32-bit 3 10 32-bit 4 11 32-bit 5 00 16-bit 6 01 16-bit 7 10 16-bit 8 11 16-bit 9 00 8-bit 10 01 8-bit 11 10 8-bit 12 11 8-bit 13 00 8-bit DBGxD0 100 101 110 DBGxD2 DBGxD1 DBGxD1 DBGxD2 DBGxD2 DBGxD3 DBGxD3 DBGxD0 DBGxD0 DBGxD1 DBGxD2 DBGxD3 DBGxD0 Denotes byte that is not accessed. For a match of a 32-bit access with data compare, the address comparator must be loaded with the address of the lowest accessed byte. For Case1 Table 7-29 this corresponds to 000, for Case2 it corresponds to 001. To compare all 32-bits, it is required that no bits are masked. 7.4.2.3 Data Bus Comparison NDB Dependency The NDB control bit allows data bus comparators to be configured to either match on equivalence or on difference. This allows monitoring of a difference in the contents of an address location from an expected value. When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by clearing the corresponding mask bit, so that it is ignored in the comparison. A match occurs when all data bus bits with corresponding mask bits set are equivalent. If all mask register bits are clear, then a match is based on the address bus only, the data bus is ignored. When matching on a difference, mask bits can be cleared to ignore bit positions. A match occurs when any data bus bit with corresponding mask bit set is different. Clearing all mask bits, causes all bits to be ignored and prevents a match because no difference can be detected. In this case address bus equivalence does not cause a match. Bytes that are not accessed are ignored. Thus when monitoring a multi byte field for a difference, partial accesses of the field only return a match if a difference is detected in the accessed bytes. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 201 S12Z DebugLite (S12ZDBGV3) Table 7-30. NDB and MASK bit dependency 7.4.2.4 NDB DBGADM Comment 0 0 Do not compare data bus bit. 0 1 Compare data bus bit. Match on equivalence. 1 0 Do not compare data bus bit. 1 1 Compare data bus bit. Match on difference. Range Comparisons Range comparisons are accurate to byte boundaries. Thus for data access comparisons a match occurs if at least one byte of the access is in the range (inside range) or outside the range (outside range). For opcode comparisons only the address of the first opcode byte is compared with the range. When using the AB comparator pair for a range comparison, the data bus can be used for qualification by using the comparator A data and data mask registers. The DBGACTL RW and RWE bits can be used to qualify the range comparison on either a read or a write access. The corresponding DBGBCTL bits are ignored. The DBGACTL COMPE/INST bits are used for range comparisons. The DBGBCTL COMPE/INST bits are ignored in range modes. 7.4.2.4.1 Inside Range (CompA_Addr  address  CompB_Addr) In the Inside Range comparator mode, comparator pair A and B can be configured for range comparisons by the control register (DBGC2). The match condition requires a simultaneous valid match for both comparators. A match condition on only one comparator is not valid. 7.4.2.4.2 Outside Range (address < CompA_Addr or address > CompB_Addr) In the Outside Range comparator mode, comparator pair A and B can be configured for range comparisons. A single match condition on either of the comparators is recognized as valid. Outside range mode in combination with opcode address matches can be used to detect if opcodes are from an unexpected range. NOTE When configured for data access matches, an outside range match would typically occur at any interrupt vector fetch or register access. This can be avoided by setting the upper or lower range limit to $FFFFFF or $000000 respectively. Interrupt vector fetches do not cause opcode address matches. 7.4.3 Events Events are used as qualifiers for a state sequencer change of state. The state control register for the current state determines the next state for each event. An event can immediately initiate a transition to the next state sequencer state whereby the corresponding flag in DBGSR is set. MC912ZVL Family Reference Manual, Rev. 2.48 202 NXP Semiconductors S12Z DebugLite (S12ZDBGV3) 7.4.3.1 7.4.3.1.1 Comparator Match Events Opcode Address Comparator Match The comparator is loaded with the address of the selected instruction and the comparator control register INST bit is set. When the opcode reaches the execution stage of the instruction queue a match occurs just before the instruction executes, allowing a breakpoint immediately before the instruction boundary. The comparator address register must contain the address of the first opcode byte for the match to occur. Opcode address matches are data independent thus the RWE and RW bits are ignored. CPU compares are disabled when BDM becomes active. 7.4.3.1.2 Data Access Comparator Match Data access matches are generated when an access occurs at the address contained in the comparator address register. The match can be qualified by the access data and by the access type (read/write). The breakpoint occurs a maximum of 2 instructions after the access in the CPU flow. Note, if a COF occurs between access and breakpoint, the opcode address of the breakpoint can be elsewhere in the memory map. Opcode fetches are not classed as data accesses. Thus data access matches are not possible on opcode fetches. 7.4.3.2 External Event The DBGEEV input signal can force a state sequencer transition, independent of internal comparator matches. The DBGEEV is an input signal mapped directly to a device pin and configured by the EEVE field in DBGC1. The external events can change the state sequencer state. If configured to change the state sequencer state, then the external match is mapped to DBGSCRx bits C3SC[1:0]. The DBGEFR bit EEVF is set when an external event occurs. 7.4.3.3 Setting The TRIG Bit Independent of comparator matches it is possible to initiate a breakpoint by writing the TRIG bit in DBGC1 to a logic “1”. This forces the state sequencer into the Final State. the transition to Final State is followed immediately by a transition to State0. Breakpoints, if enabled, are issued on the transition to State0. 7.4.3.4 Event Priorities If simultaneous events occur, the priority is resolved according to Table 7-31. Lower priority events are suppressed. It is thus possible to miss a lower priority event if it occurs simultaneously with an event of a higher priority. The event priorities dictate that in the case of simultaneous matches, the match on the higher comparator channel number (3,1,0) has priority. If a write access to DBGC1 with the ARM bit position set occurs simultaneously to a hardware disarm from an internal event, then the ARM bit is cleared due to the hardware disarm. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 203 S12Z DebugLite (S12ZDBGV3) Table 7-31. Event Priorities Priority Source Action Highest TRIG Force immediately to final state DBGEEV Force to next state as defined by state control registers (EEVE=2’b10) Match3 Force to next state as defined by state control registers Match1 Force to next state as defined by state control registers Match0 Force to next state as defined by state control registers Lowest 7.4.4 State Sequence Control State 0 (Disarmed) ARM = 1 State1 Final State State2 State3 Figure 7-19. State Sequencer Diagram The state sequencer allows a defined sequence of events to provide a breakpoint. When the DBG module is armed by setting the ARM bit in the DBGC1 register, the state sequencer enters State1. Further transitions between the states are controlled by the state control registers and depend upon event occurrences (see Section 7.4.3, “Events). From Final State the only permitted transition is back to the disarmed State0. Transition between the states 1 to 3 is not restricted. Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state. If breakpoints are enabled, then an event based transition to State0 generates the breakpoint request. A transition to State0 resulting from writing “0” to the ARM bit does not generate a breakpoint request. 7.4.4.1 Final State When the Final State is reached the state sequencer returns to State0 immediately and the debug module is disarmed.If breakpoints are enabled, a breakpoint request is generated on transitions to State0. 7.4.5 Breakpoints Breakpoints can be generated by state sequencer transitions to State0. Transitions to State0 are forced by the following events MC912ZVL Family Reference Manual, Rev. 2.48 204 NXP Semiconductors S12Z DebugLite (S12ZDBGV3) • • • Through comparator matches via Final State. Through software writing to the TRIG bit in the DBGC1 register via Final State. Through the external event input (DBGEEV) via Final State. Breakpoints are not generated by software writes to DBGC1 that clear the ARM bit. 7.4.5.1 Breakpoints From Comparator Matches or External Events Breakpoints can be generated when the state sequencer transitions to State0 following a comparator match or an external event. 7.4.5.2 Breakpoints Generated Via The TRIG Bit When TRIG is written to “1”, the Final State is entered. In the next cycle TRIG breakpoints are possible even if the DBG module is disarmed. 7.4.5.3 7.4.5.3.1 DBG Breakpoint Priorities DBG Breakpoint Priorities And BDC Interfacing Breakpoint operation is dependent on the state of the S12ZBDC module. BDM cannot be entered from a breakpoint unless the BDC is enabled (ENBDC bit is set in the BDC). If BDM is already active, breakpoints are disabled. In addition, while executing a BDC STEP1 command, breakpoints are disabled. When the DBG breakpoints are mapped to BDM (BDMBP set), then if a breakpoint request, either from a BDC BACKGROUND command or a DBG event, coincides with an SWI instruction in application code, (i.e. the DBG requests a breakpoint at the next instruction boundary and the next instruction is an SWI) then the CPU gives priority to the BDM request over the SWI request. On returning from BDM, the SWI from user code gets executed. Breakpoint generation control is summarized in Table 7-32. Table 7-32. Breakpoint Mapping Summary BRKCPU BDMBP Bit (DBGC1[4]) BDC Enabled BDM Active Breakpoint Mapping 0 X X X No Breakpoint 1 0 X 0 Breakpoint to SWI 1 0 1 1 No Breakpoint 1 1 0 X No Breakpoint 1 1 1 0 Breakpoint to BDM 1 1 1 1 No Breakpoint MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 205 S12Z DebugLite (S12ZDBGV3) 7.5 7.5.1 Application Information Avoiding Unintended Breakpoint Re-triggering Returning from an instruction address breakpoint using an RTI or BDC GO command without PC modification, returns to the instruction that generated the breakpoint. If an active breakpoint or trigger still exists at that address, this can re-trigger, disarming the DBG. If configured for BDM breakpoints, the user must apply the BDC STEP1 command to increment the PC past the current instruction. If configured for SWI breakpoints, the DBG can be re configured in the SWI routine. If a comparator match occurs at an SWI vector address then a code SWI and DBG breakpoint SWI could occur simultaneously. In this case the SWI routine is executed twice before returning. 7.5.2 Breakpoints from other S12Z sources The DBG is neither affected by CPU BGND instructions, nor by BDC BACKGROUND commands. MC912ZVL Family Reference Manual, Rev. 2.48 206 NXP Semiconductors Chapter 8 ECC Generation Module (SRAM_ECCV2) Table 8-1. Revision History Table Rev. No. (Item No.) Date Sections Affected V01.00 26-Jul.-11 all Initial version V1 V02.00 10-May-12 all Initial version V2, added support for max access width of 2 byte 8.1 Substantial Change(s) Introduction The purpose of ECC logic is to detect and correct as much as possible memory data bit errors. These soft errors, mainly generated by alpha radiation, can occur randomly during operation. "Soft error" means that only the information inside the memory cell is corrupt; the memory cell itself is not damaged. A write access with correct data solves the issue. If the ECC algorithm is able to correct the data, then the system can use this corrected data without any issues. If the ECC algorithm is able to detect, but not correct the error, then the system is able to ignore the memory read data to avoid system malfunction. The ECC value is calculated based on an aligned 2 byte memory data word. Depending on the device integration, the maximum supported access width can be 2 or 4 bytes. Please see the device overview section for the information about the maximum supported access width on the device. In a system with a maximum access width of 2 bytes, a 2 byte access to a 2 byte aligned address is classed as an aligned access. If the system supports a 4-byte access width, then a 2-byte access to a 2 byte aligned address or a 4 byte access to a 4 byte aligned address are classed as aligned accesses. All other access types are classed as non-aligned accesses. A non-aligned write access requires a read-modify-write operation, for more details please see section The ECC algorithm is able to detect and correct single bit ECC errors. Double bit ECC errors will be detected but the system is not able to correct these errors. This kind of ECC code is called SECDED code. This ECC code requires 6 additional parity bits for each 2 byte data word. 8.1.1 Features The SRAM_ECC module provides the ECC logic for the system memory based on a SECDED algorithm. The SRAM_ECC module includes the following features: • SECDED ECC code – Single bit error detection and correction per 2 byte data word MC9S12ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 207 ECC Generation Module (SRAM_ECCV2) – Double bit error detection per 2 byte data word • Memory initialization function • Byte wide system memory write access • Automatic single bit ECC error correction for read and write accesses • Debug logic to read and write raw use data and ECC values 8.2 Memory Map and Register Definition This section provides a detailed description of all memory and registers for the SRAM_ECC module. 8.2.1 Register Summary Figure 8-1 shows the summary of all implemented registers inside the SRAM_ECC module. MC912ZVL Family Reference Manual, Rev. 2.48 208 NXP Semiconductors ECC Generation Module (SRAM_ECCV2) NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level. Address Offset Register Name 0x0000 ECCSTAT R 0x0001 ECCIE R 0x0002 ECCIF R 0x0003 - 0x0006 Reserved R 0x0007 ECCDPTRH R 0x0008 ECCDPTRM R 0x0009 ECCDPTRL R 0x000A - 0x000B Reserved R 0x000C ECCDDH R 0x000D ECCDDL R 0x000E ECCDE R 0x000F ECCDCMD R Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 RDY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W W W SBEEIE SBEEIF 0 W DPTR[23:16] W DPTR[15:8] W 0 DPTR[7:1] W 0 0 0 0 0 0 0 0 ECCDW ECCDR W DDATA[15:8] W DDATA[7:0] W 0 0 DECC[5:0] W W ECCDRR 0 0 0 0 0 = Unimplemented, Reserved, Read as zero Figure 8-1. SRAM_ECC Register Summary MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 209 ECC Generation Module (SRAM_ECCV2) 8.2.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field functions follow the register diagrams, in bit order. 8.2.2.1 ECC Status Register (ECCSTAT) Access: User read only1 Module Base + 0x00000 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RDY 0 0 0 0 0 0 0 0 W Reset 1 Read: Anytime Write: Never Figure 8-2. ECC Status Register (ECCSTAT) Table 8-2. ECCSTAT Field Description Field Description 0 RDY ECC Ready— Shows the status of the ECC module. 0 Internal SRAM initialization is ongoing, access to the SRAM is disabled 1 Internal SRAM initialization is done, access to the SRAM is enabled 8.2.2.2 ECC Interrupt Enable Register (ECCIE) Access: User read/write1 Module Base + 0x00001 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 SBEEIE 0 Read: Anytime Write: Anytime Figure 8-3. ECC Interrupt Enable Register (ECCIE) Table 8-3. ECCIE Field Description Field 0 SBEEIE Description Single bit ECC Error Interrupt Enable — Enables Single ECC Error interrupt. 0 Interrupt request is disabled 1 Interrupt will be requested whenever SBEEIF is set MC912ZVL Family Reference Manual, Rev. 2.48 210 NXP Semiconductors ECC Generation Module (SRAM_ECCV2) 8.2.2.3 ECC Interrupt Flag Register (ECCIF) Access: User read/write1 Module Base + 0x0002 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 SBEEIF 0 Read: Anytime Write: Anytime, write 1 to clear Figure 8-4. ECC Interrupt Flag Register (ECCIF) Table 8-4. ECCIF Field Description Field 0 SBEEIF Description Single bit ECC Error Interrupt Flag — The flag is set to 1 when a single bit ECC error occurs. 0 No occurrences of single bit ECC error since the last clearing of the flag 1 Single bit ECC error has occured since the last clearing of the flag MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 211 ECC Generation Module (SRAM_ECCV2) ECC Debug Pointer Register (ECCDPTRH, ECCDPTRM, ECCDPTRL) 8.2.2.4 Access: User read/write1 Module Base + 0x0007 7 6 5 4 R 3 2 1 0 0 0 0 0 DPTR[23:16] W Reset 0 0 0 0 Module Base + 0x0008 7 Access: User read/write 6 5 4 R 3 2 1 0 0 0 0 0 DPTR[15:8] W Reset 0 0 0 0 Module Base + 0x0009 7 Access: User read/write 6 5 R 3 2 1 0 0 0 0 0 0 DPTR[7:1] W Reset 4 0 0 0 0 = Unimplemented Figure 8-5. ECC Debug Pointer Register (ECCDPTRH, ECCDPTRM, ECCDPTRL) 1 Read: Anytime Write: Anytime Table 8-5. ECCDPTR Register Field Descriptions Field Description DPTR [23:0] ECC Debug Pointer — This register contains the system memory address which will be used for a debug access. Address bits not relevant for SRAM address space are not writeable, so the software should read back the pointer value to make sure the register contains the intended memory address. It is possible to write an address value to this register which points outside the system memory. There is no additional monitoring of the register content; therefore, the software must make sure that the address value points to the system memory space. MC912ZVL Family Reference Manual, Rev. 2.48 212 NXP Semiconductors ECC Generation Module (SRAM_ECCV2) ECC Debug Data (ECCDDH, ECCDDL) 8.2.2.5 Access: User read/write1 Module Base + 0x000C 7 6 5 4 R 3 2 1 0 0 0 0 0 DDATA[15:8] W Reset 0 0 0 0 Module Base + 0x000D 7 Access: User read/write 6 5 4 R 3 2 1 0 0 0 0 0 DDATA[7:0] W Reset 0 0 0 0 = Unimplemented Figure 8-6. ECC Debug Data (ECCDDH, ECCDDL) 1 Read: Anytime Write: Anytime Table 8-6. ECCDD Register Field Descriptions Field Description DDATA [23:0] 8.2.2.6 ECC Debug Raw Data — This register contains the raw data which will be written into the system memory during a debug write command or the read data from the debug read command. ECC Debug ECC (ECCDE) Access: User read/write1 Module Base + 0x000E R 7 6 0 0 0 0 5 4 3 Reset 1 0 0 0 0 DECC[5:0] W 1 2 0 0 0 Read: Anytime Write: Anytime Figure 8-7. ECC Debug ECC (ECCDE) Table 8-7. ECCDE Field Description Field Description 5:0 ECC Debug ECC — This register contains the raw ECC value which will be written into the system memory DECC[5:0] during a debug write command or the ECC read value from the debug read command. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 213 ECC Generation Module (SRAM_ECCV2) 8.2.2.7 ECC Debug Command (ECCDCMD) Access: User read/write1 Module Base + 0x000F 7 R W Reset 1 ECCDRR 0 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 1 0 ECCDW ECCDR 0 0 Read: Anytime Write: Anytime, in special mode only Figure 8-8. ECC Debug Command (ECCDCMD) Table 8-8. ECCDCMD Field Description Field Description 7 ECC Disable Read Repair Function— Writing one to this register bit will disable the automatic single bit ECC ECCDRR error repair function during read access; see also chapter 8.3.7, “ECC Debug Behavior”. 0 Automatic single ECC error repair function is enabled 1 Automatic single ECC error repair function is disabled 1 ECCDW ECC Debug Write Command — Writing one to this register bit will perform a debug write access, to the system memory. During this access the debug data word (DDATA) and the debug ECC value (DECC) will be written to the system memory address defined by DPTR. If the debug write access is done, this bit is cleared. Writing 0 has no effect. It is not possible to set this bit if the previous debug access is ongoing (ECCDW or ECCDR bit set). 0 ECCDR ECC Debug Read Command — Writing one to this register bit will perform a debug read access from the system memory address defined by DPTR. If the debug read access is done, this bit is cleared and the raw memory read data are available in register DDATA and the raw ECC value is available in register DECC. Writing 0 has no effect. If the ECCDW and ECCDR bit are set at the same time, then only the ECCDW bit is set and the Debug Write Command is performed. It is not possible to set this bit if the previous debug access is ongoing (ECCDW or ECCDR bit set). 8.3 Functional Description Depending on the system integration the max memory access width can be 4 byte, but the ECC value is generated based on an aligned 2 byte data word. Depending on the access type, the access is separated into different access cycles. Table 8-9 shows the different access types with the expected number of access cycles and the performed internal operations. Table 8-9. Memory access cycles Access type ECC error access cycle Internal operation Memory content Error indication Aligned write — 1 write to memory new data — MC912ZVL Family Reference Manual, Rev. 2.48 214 NXP Semiconductors ECC Generation Module (SRAM_ECCV2) Table 8-9. Memory access cycles Access type Non-aligned write read access 1 ECC error access cycle no 2 Internal operation Memory content Error indication read data from the memory old + new data — corrected + new data SBEEIF write old + new data to the memory read data from the memory single bit 2 double bit 2 no 1 single bit 11 double bit 1 write corrected + new data to the memory read data from the memory ignore write data unchanged machine exception read from memory unchanged - read data from the memory write corrected data back to memory corrected data SBEEIF read from memory unchanged data mark as invalid machine exception The next back to back read access to the memory will be delayed by one clock cycle The single bit ECC error generates an interrupt when enabled. The double bit ECC errors are reported by the SRAM_ECC module, but handled at MCU level. For more information, see the MMC description. 8.3.1 Aligned Memory Write Access During an aligned memory write access, no ECC check is performed. The internal ECC logic generates the new ECC value based on the write data and writes the data word together with the generated ECC value into the memory. 8.3.2 Non-aligned Memory Write Access Non-aligned write accesses are separated into a read-modify-write operation. During the first cycle, the logic reads the data from the memory and performs an ECC check. If no ECC errors were detected then the logic generates the new ECC value based on the read and write data and writes the new data word together with the new ECC value into the memory. If the module detects a single bit ECC error during the read cycle, then the logic generates the new ECC value based on the corrected read and new write read. In the next cycle, the new data word and the new ECC value are written into the memory. The SBEEIF bit is set. Hence, the single bit ECC error was corrected by the write access. Figure 8-9 shows an example of a 2 byte non-aligned memory write access. If the module detects a double bit ECC error during the read cycle, then the write access to the memory is blocked and the initiator module is informed about the error. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 215 ECC Generation Module (SRAM_ECCV2) . 2 byte use data ECC 2 byte use data read out data and correct if single bit ECC error was found 4 byte read data from system memory read out data and correct if single bit ECC error was found correct read data correct read data write data correct read data write data ECC write data ECC write data 2 byte write data correct read data ECC 4 byte write data to system memory Figure 8-9. 2 byte non-aligned write access 8.3.3 Memory Read Access During each memory read access an ECC check is performed. If the logic detects a single bit ECC error, then the module corrects the data, so that the access initiator module receives correct data. In parallel, the logic writes the corrected data back to the memory, so that this read access repairs the single bit ECC error. This automatic ECC read repair function is disabled by setting the ECCDRR bit. If a single bit ECC error was detected, then the SBEEIF flag is set. If the logic detects a double bit ECC error, then the data word is flagged as invalid, so that the access initiator module can ignore the data. 8.3.4 Memory Initialization To avoid spurious ECC error reporting, memory operations that allow a read before a first write (like the read-modify-write operation of the non-aligned access) require that the memory contains valid ECC values before the first read-modify-write access is performed. The ECC module provides logic to initialize the complete memory content with zero during the power up phase. During the initialization process the access to the SRAM is disabled and the RDY status bit is cleared. If the initialization process is done, SRAM access is possible and the RDY status bit is set. 8.3.5 Interrupt Handling This section describes the interrupts generated by the SRAM_ECC module and their individual sources. Vector addresses and interrupt priority are defined at the MCU level. MC912ZVL Family Reference Manual, Rev. 2.48 216 NXP Semiconductors ECC Generation Module (SRAM_ECCV2) Table 8-10. SRAM_ECC Interrupt Sources Module Interrupt Sources Single bit ECC error 8.3.6 Local Enable ECCIE[SBEEIE] ECC Algorithm The table below shows the equation for each ECC bit based on the 16 bit data word. Table 8-11. ECC Calculation 8.3.7 ECC bit Use data ECC[0] ~ ( ^ ( data[15:0] & 0x443F ) ) ECC[1] ~ ( ^ ( data[15:0] & 0x13C7 ) ) ECC[2] ~ ( ^ ( data[15:0] & 0xE1D1 ) ) ECC[3] ~ ( ^ ( data[15:0] & 0xEE60 ) ) ECC[4] ~ ( ^ ( data[15:0] & 0x3E8A ) ) ECC[5] ~ ( ^ ( data[15:0] & 0x993C ) ) ECC Debug Behavior For debug purposes, it is possible to read and write the uncorrected use data and the raw ECC value directly from the memory. For these debug accesses a register interface is available. The debug access is performed with the lowest priority; other memory accesses must be done before the debug access starts. If a debug access is requested during an ongoing memory initialization process, then the debug access is performed if the memory initialization process is done. If the ECCDRR bit is set, then the automatic single bit ECC error repair function for all read accesses is disabled. In this case a read access from a system memory location with single bit ECC error will produce correct data and the single bit ECC error is flagged by the SBEEIF, but the data inside the system memory are unchanged. By writing wrong ECC values into the system memory the debug access can be used to force single and double bit ECC errors to check the software error handling. It is not possible to set the ECCDW or ECCDR bit if the previous debug access is ongoing (ECCDW or ECCDR bit active). This ensures that the ECCDD and ECCDE registers contains consistent data. The software should read out the status of the ECCDW and ECCDR register bit before a new debug access is requested. 8.3.7.1 ECC Debug Memory Write Access Writing one to the ECCDW bit performs a debug write access to the memory address defined by register DPTR. During this access, the raw data DDATA and the ECC value DECC are written directly into the system memory. If the debug write access is done, the ECCDW register bit is cleared. The debug write MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 217 ECC Generation Module (SRAM_ECCV2) access is always a 2 byte aligned memory access, so that no ECC check is performed and no single or double bit ECC error indication is activated. 8.3.7.2 ECC Debug Memory Read Access Writing one to the ECCDR bit performs a debug read access from the memory address defined by register DPTR. If the ECCDR bit is cleared then the register DDATA contains the uncorrected read data from the memory. The register DECC contains the ECC value read from the memory. Independent of the ECCDRR register bit setting, the debug read access will not perform an automatic ECC repair during read access. During the debug read access no ECC check is performed, so that no single or double bit ECC error indication is activated. If the ECCDW and the ECCDR bits are set at the same time, then only the debug write access is performed. MC912ZVL Family Reference Manual, Rev. 2.48 218 NXP Semiconductors Chapter 9 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) Table 9-1. Revision History Rev. No. (Item No) V09.00 V09.01 V09.02 V09.03 9.1 Date (Submitted By) 8 Sept.2014 21 Oct. 2014 Sections Affected Substantial Change(s) • initial version for ZVL128, copied from ZVL32 • CPMUPROT register: added CPMUVREGCTL2 to list of protected registers • added CPMUVREGCTL2 register containing 5V/3V option Bit and respective trim values • • • • • • Improved Figure: Start up of clock system after Reset Improved Figure: Full stop mode using Oscillator Improved Figure: Enabling the external oscillator Improved Table: Trimming effect of ACLKTR Improved Table: Trimming effect of HTTR Register Description for CPMUHTCTL: Added note on how to compute VHT • Functional Description PBE Mode: Added Note that the clock system might stall if osc monitor reset disabled (OMRE=0) • Signal Descriptions: changed recommended resistor for BCTL pin to 1K 11 Nov. 2014 • Moved VREG5VEN bit to CPMUVREGCTL register 14 Nov. 2014 • Corrected typos Introduction This specification describes the function of the Clock, Reset and Power Management Unit (S12CPMU_UHV). • The Pierce oscillator (XOSCLCP) provides a robust, low-noise and low-power external clock source. It is designed for optimal start-up margin with typical crystal oscillators. • The Voltage regulator (VREGAUTO) operates from the range 6V to 18V. It provides all the required chip internal voltages and voltage monitors. • The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter. • The Internal Reference Clock (IRC1M) provides a 1MHz internal clock. MC9S12ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 219 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) 9.1.1 Features The Pierce Oscillator (XOSCLCP) contains circuitry to dynamically control current gain in the output amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity. • Supports crystals or resonators from 4MHz to 20MHz. • High noise immunity due to input hysteresis and spike filtering. • Low RF emissions with peak-to-peak swing limited dynamically • Transconductance (gm) sized for optimum start-up margin for typical crystals • Dynamic gain control eliminates the need for external current limiting resistor • Integrated resistor eliminates the need for external bias resistor • Low power consumption: Operates from internal 1.8V (nominal) supply, Amplitude control limits power • Optional oscillator clock monitor reset • Optional full swing mode for higher immunity against noise injection on the cost of higher power consumption and increased emission The Voltage Regulator (VREGAUTO) has the following features: • Input voltage range from 6 to 18V (nominal operating range) • Low-voltage detect (LVD) with low-voltage interrupt (LVI) • Power-on reset (POR) • Low-voltage reset (LVR) • On Chip Temperature Sensor and Bandgap Voltage measurement via internal ADC channel. • Voltage Regulator providing Full Performance Mode (FPM) and Reduced Performance Mode (RPM) • External ballast device support to reduce internal power dissipation • Capable of supplying both the MCU internally plus external components • Over-temperature interrupt The Phase Locked Loop (PLL) has the following features: • Highly accurate and phase locked frequency multiplier • Configurable internal filter for best stability and lock time • Frequency modulation for defined jitter and reduced emission • Automatic frequency lock detector • Interrupt request on entry or exit from locked condition • PLL clock monitor reset • Reference clock either external (crystal) or internal square wave (1MHz IRC1M) based. • PLL stability is sufficient for LIN communication in slave mode, even if using IRC1M as reference clock The Internal Reference Clock (IRC1M) has the following features: MC912ZVL Family Reference Manual, Rev. 2.48 220 NXP Semiconductors S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) • • Frequency trimming (A factory trim value for 1MHz is loaded from Flash Memory into the CPMUIRCTRIMH and CPMUIRCTRIML registers after reset, which can be overwritten by application if required) Temperature Coefficient (TC) trimming. (A factory trim value is loaded from Flash Memory into the IRCTRIM register to turn off TC trimming after reset. Application can trim the TC if required by overwriting the IRCTRIM register). Other features of the S12CPMU_UHV include • Oscillator clock monitor to detect loss of crystal • Autonomous periodical interrupt (API) • Bus Clock Generator — Clock switch to select either PLLCLK or external crystal/resonator based Bus Clock — PLLCLK divider to adjust system speed • System Reset generation from the following possible sources: — Power-on reset (POR) — Low-voltage reset (LVR) — COP system watchdog, COP reset on time-out, windowed COP — Loss of oscillation (Oscillator clock monitor fail) — Loss of PLL clock (PLL clock monitor fail) — External pin RESET MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 221 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) 9.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the S12CPMU_UHV. 9.1.2.1 Run Mode The voltage regulator is in Full Performance Mode (FPM). NOTE The voltage regulator is active, providing the nominal supply voltages with full current sourcing capability (see also Appendix for VREG electrical parameters). The features ACLK clock source, Low Voltage Interrupt (LVI), Low Voltage Reset (LVR) and Power-On Reset (POR) are available. The Phase Locked Loop (PLL) is on. The Internal Reference Clock (IRC1M) is on. The API is available. • • • PLL Engaged Internal (PEI) — This is the default mode after System Reset and Power-On Reset. — The Bus Clock is based on the PLLCLK. — After reset the PLL is configured for 50MHz VCOCLK operation. Post divider is 0x03, so PLLCLK is VCOCLK divided by 4, that is 12.5MHz and Bus Clock is 6.25MHz. The PLL can be re-configured for other bus frequencies. — The reference clock for the PLL (REFCLK) is based on internal reference clock IRC1M. PLL Engaged External (PEE) — The Bus Clock is based on the PLLCLK. — This mode can be entered from default mode PEI by performing the following steps: – Configure the PLL for desired bus frequency. – Program the reference divider (REFDIV[3:0] bits) to divide down oscillator frequency if necessary. – Enable the external oscillator (OSCE bit). – Wait for oscillator to start up (UPOSC=1) and PLL to lock (LOCK=1). PLL Bypassed External (PBE) — The Bus Clock is based on the Oscillator Clock (OSCCLK). — The PLLCLK is always on to qualify the external oscillator clock. Therefore it is necessary to make sure a valid PLL configuration is used for the selected oscillator frequency. — This mode can be entered from default mode PEI by performing the following steps: – Make sure the PLL configuration is valid for the selected oscillator frequency. MC912ZVL Family Reference Manual, Rev. 2.48 222 NXP Semiconductors S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) – Enable the external oscillator (OSCE bit). – Wait for oscillator to start up (UPOSC=1). – Select the Oscillator Clock (OSCCLK) as source of the Bus Clock (PLLSEL=0). — The PLLCLK is on and used to qualify the external oscillator clock. 9.1.2.2 Wait Mode For S12CPMU_UHV Wait Mode is the same as Run Mode. 9.1.2.3 Stop Mode Stop mode can be entered by executing the CPU STOP instruction. See device level specification for more details. The voltage regulator is in Reduced Performance Mode (RPM). NOTE The voltage regulator output voltage may degrade to a lower value than in Full Performance Mode (FPM), additionally the current sourcing capability is substantially reduced (see also Appendix for VREG electrical parameters). Only clock source ACLK is available and the Power On Reset (POR) circuitry is functional. The Low Voltage Interrupt (LVI) and Low Voltage Reset (LVR) are disabled. The API is available. The Phase Locked Loop (PLL) is off. The Internal Reference Clock (IRC1M) is off. Core Clock and Bus Clock are stopped. Depending on the setting of the PSTP and the OSCE bit, Stop Mode can be differentiated between Full Stop Mode (PSTP = 0 or OSCE=0) and Pseudo Stop Mode (PSTP = 1 and OSCE=1). In addition, the behavior of the COP in each mode will change based on the clocking method selected by COPOSCSEL[1:0]. • Full Stop Mode (PSTP = 0 or OSCE=0) External oscillator (XOSCLCP) is disabled. — If COPOSCSEL1=0: The COP and RTI counters halt during Full Stop Mode. After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK (PLLSEL=1). COP and RTI are running on IRCCLK (COPOSCSEL0=0, RTIOSCSEL=0). — If COPOSCSEL1=1: The clock for the COP is derived from ACLK (trimmable internal RC-Oscillator clock). During Full Stop Mode the ACLK for the COP can be stopped (COP static) or running (COP active) depending on the setting of bit CSAD. When bit CSAD is set the ACLK clock source for the MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 223 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) • COP is stopped during Full Stop Mode and COP continues to operate after exit from Full Stop Mode. For this COP configuration (ACLK clock source, CSAD set) a latency time (please refer to CSAD bit description for details) occurs when entering or exiting (Full, Pseudo) Stop Mode. When bit CSAD is clear the ACLK clock source is on for the COP during Full Stop Mode and COP is operating. During Full Stop Mode the RTI counter halts. After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK (PLLSEL=1). The COP runs on ACLK and RTI is running on IRCCLK (COPOSCSEL0=0, RTIOSCSEL=0). Pseudo Stop Mode (PSTP = 1 and OSCE=1) External oscillator (XOSCLCP) continues to run. — If COPOSCSEL1=0: If the respective enable bits are set (PCE=1 and PRE=1) the COP and RTI will continue to run with a clock derived from the oscillator clock. The clock configuration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged. — If COPOSCSEL1=1: If the respective enable bit for the RTI is set (PRE=1) the RTI will continue to run with a clock derived from the oscillator clock. The clock for the COP is derived from ACLK (trimmable internal RC-Oscillator clock). During Pseudo Stop Mode the ACLK for the COP can be stopped (COP static) or running (COP active) depending on the setting of bit CSAD. When bit CSAD is set the ACLK for the COP is stopped during Pseudo Stop Mode and COP continues to operate after exit from Pseudo Stop Mode. For this COP configuration (ACLK clock source, CSAD set) a latency time (please refer to CSAD bit description for details) occurs when entering or exiting (Pseudo, Full) Stop Mode. When bit CSAD is clear the ACLK clock source is on for the COP during Pseudo Stop Mode and COP is operating. The clock configuration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged. NOTE When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator tUPOSC before entering Pseudo Stop Mode. 9.1.2.4 Freeze Mode (BDM active) For S12CPMU_UHV Freeze Mode is the same as Run Mode except for RTI and COP which can be frozen in Active BDM Mode with the RSBCK bit in the CPMUCOP register. After exiting BDM Mode RTI and COP will resume its operations starting from this frozen status. Additionally the COP can be forced to the maximum time-out period in Active BDM Mode. For details please see also the RSBCK and CR[2:0] bit description field of Table 9-14 in Section 9.3.2.12, “S12CPMU_UHV COP Control Register (CPMUCOP) MC912ZVL Family Reference Manual, Rev. 2.48 224 NXP Semiconductors S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 225 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) 9.1.3 S12CPMU_UHV Block Diagram VSUP vsup monitor ADC VDDA VSSA VDDX VSSX VSS Low Voltage Detect VDDA Low Voltage Detect Voltage VDDX, VDD, VDDF Regulator LVRF 6V to 18V Power-On Detect (VREGAUTO) PORF PMRF BCTL LVIE Low Voltage Interrupt LVDS S12CPMU_UHV COP time-out COPRF OMRF osc monitor fail Power-On Reset System Reset Reset Generator PLL monitor fail RESET OSCCLK OSCCLK Monitor EXTAL Loop Controlled REFDIV[3:0] IRCTRIM[9:0] Pierce XTAL Oscillator (XOSCLCP) Internal Reference Reference 4MHz-20MHz Divider Clock (IRC1M) PSTP OSCMOD IRCCLK OSCCLK REFCLK FBCLK Phase locked Loop with internal Filter (PLL) Post Divider 1,2,.32 divide by 4 Divide by 2*(SYNDIV+1) ACLK CSAD divide by 2 IRCCLK COPOSCSEL1 SYNDIV[5:0] HTDS Watchdog OSCCLK COPOSCSEL0 UPOSC=0 clears LOCKIE Bus Clock PLL lock interrupt Autonomous API_EXTCLK Periodic Interrupt (API) divide by 2 ACLK APICLK APIE RTIE COP time-out to Reset Generator IRCCLK CPMUCOP HT Interrupt HTIE High Temperature Sense OSCCLK RTIOSCSEL API Interrupt RTI Interrupt Real Time Interrupt (RTI) RTICLK PCE ECLK2X (Core Clock) VCOCLK RC Osc. COPCLK COP ECLK divide by 2 (Bus Clock) PLLCLK VCOFRQ[1:0] UPOSC PLLSEL POSTDIV[4:0] REFFRQ[1:0] LOCK Oscillator status Interrupt OSCIE UPOSC UPOSC=0 sets PLLSEL bit OSCE Lock detect IRCCLK PRE CPMURTI Figure 9-1. Block diagram of S12CPMU_UHV MC912ZVL Family Reference Manual, Rev. 2.48 226 NXP Semiconductors S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) Figure 9-2 shows a block diagram of the XOSCLCP. OSCMOD Peak Detector Clock monitor fail Monitor + _ Gain Control OSCCLK VDD=1.8V VSS Rf Quartz Crystals EXTAL or Ceramic Resonators XTAL C1 C2 VSS VSS Figure 9-2. XOSCLCP Block Diagram MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 227 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) 9.2 Signal Description This section lists and describes the signals that connect off chip as well as internal supply nodes and special signals. 9.2.1 RESET Pin RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered. 9.2.2 EXTAL and XTAL These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. If XOSCLCP is enabled, the MCU internal OSCCLK_LCP is derived from the EXTAL input frequency. If OSCE=0, the EXTAL pin is pulled down by an internal resistor of approximately 200 k and the XTAL pin is pulled down by an internal resistor of approximately 700 k. NOTE NXP recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. The loop controlled circuit (XOSCLCP) is not suited for overtone resonators and crystals. 9.2.3 VSUP — Regulator Power Input Pin Pin VSUP is the power input of VREGAUTO. All currents sourced into the regulator loads flow through this pin. A suitable reverse battery protection network can be used to connect VSUP to the car battery supply network. 9.2.4 VDDA, VSSA — Regulator Reference Supply Pins Pins VDDA and VSSA,are used to supply the analog parts of the regulator. Internal precision reference circuits are supplied from these signals. An off-chip decoupling capacitor (220 nF(X7R ceramic)) between VDDA and VSSA is required and can improve the quality of this supply. VDDA has to be connected externally to VDDX. 9.2.5 VDDX, VSSX — Pad Supply Pins VDDX is the supply domain for the digital Pads. An off-chip decoupling capacitor (10F plus 220 nF(X7R ceramic)) between VDDX and VSSX is required. MC912ZVL Family Reference Manual, Rev. 2.48 228 NXP Semiconductors S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) This supply domain is monitored by the Low Voltage Reset circuit. VDDX has to be connected externally to VDDA. 9.2.6 BCTL — Base Control Pin for external PNP BCTL is the ballast connection for the on chip voltage regulator. It provides the base current of an external BJT (PNP) of the VDDX and VDDA supplies. An additional 1K resistor between emitter and base of the BJT is required. See the device specification if this pin is available on this device. 9.2.7 VSS — Core Logic Ground Pin VSS is the core logic supply return pin. It must be grounded. 9.2.8 VDD — Internal Regulator Output Supply (Core Logic) Node VDD is a device internal supply output of the voltage regulator that provides the power supply for the internal core logic. This supply domain is monitored by the Low Voltage Reset circuit and The Power On Reset circuit. 9.2.9 VDDF — Internal Regulator Output Supply (NVM Logic) Node VDDF is a device internal supply output of the voltage regulator that provides the power supply for the NVM logic. This supply domain is monitored by the Low Voltage Reset circuit. 9.2.10 API_EXTCLK — API external clock output pin This pin provides the signal selected via APIES and is enabled with APIEA bit. See the device specification if this clock output is available on this device and to which pin it might be connected. 9.2.11 TEMPSENSE — Internal Temperature Sensor Output Voltage Depending on the VSEL setting either the voltage level generated by the temperature sensor or the VREG bandgap voltage is driven to a special channel input of the ADC Converter. See device level specification for connectivity of ADC special channels. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 229 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) 9.3 Memory Map and Registers This section provides a detailed description of all registers accessible in the S12CPMU_UHV. 9.3.1 Module Memory Map The S12CPMU_UHV registers are shown in Figure 9-3. Address Offset Register Name 0x0000 RESERVED 0x0001 RESERVED CPMU VREGTRIM0 0x0002 RESERVED CPMU VREGTRIM1 0x0003 CPMURFLG 0x0004 CPMU SYNR 0x0005 CPMU REFDIV 0x0006 CPMU POSTDIV 0x0007 CPMUIFLG 0x0008 CPMUINT 0x0009 CPMUCLKS 0x000A CPMUPLL 0x000B CPMURTI 0x000C CPMUCOP 0x000D RESERVED CPMUTEST0 R Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 U U U U 0 0 U U U U U U PORF LVRF OMRF PMRF W R W R W R 0 W R W R W R 0 VCOFRQ[1:0] REFFRQ[1:0] 0 COPRF SYNDIV[5:0] 0 0 0 0 0 0 0 0 PLLSEL PSTP CSAD COP OSCSEL1 0 0 FM1 FM0 RTDEC RTR6 RTR5 WCOP RSBCK 0 0 0 REFDIV[3:0] POSTDIV[4:0] W R W R W R W R RTIF RTIE W R W R W R 0 LOCK 0 0 0 PRE PCE RTI OSCSEL COP OSCSEL0 0 0 0 0 RTR4 RTR3 RTR2 RTR1 RTR0 0 0 CR2 CR1 CR0 0 0 0 0 0 LOCKIF LOCKIE WRTMASK 0 OSCIF OSCIE UPOSC 0 W = Unimplemented or Reserved Figure 9-3. CPMU Register Summary MC912ZVL Family Reference Manual, Rev. 2.48 230 NXP Semiconductors S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) Address Offset Register Name 0x000E RESERVED CPMUTEST1 0x000F CPMU ARMCOP 0x0010 CPMU HTCTL 0x0011 CPMU LVCTL 0x0012 CPMU APICTL 0x0013 CPMUACLKTR 0x0014 CPMUAPIRH 0x0015 CPMUAPIRL 0x0016 RESERVED Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R 0 0 HTIE HTIF 0 0 0 LVIE LVIF 0 0 APIE APIF ACLKTR5 ACLKTR4 ACLKTR3 0 0 APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0 0 0 0 0 0 0 0 0 0 0 0 HTTR3 HTTR2 HTTR1 HTTR0 R W W R VSEL 0 HTE HTDS 0 0 LVDS APIES APIEA APIFE W R W R W R W R W R APICLK ACLKTR2 ACLKTR1 ACLKTR0 W 0x0017 CPMUHTTR 0x0018 CPMU IRCTRIMH 0x0019 CPMU IRCTRIML 0x001A CPMUOSC 0x001B CPMUPROT 0x001C RESERVED CPMUTEST2 0x001D CPMU VREGCTL 0x001E CPMUOSC2 0x001F RESERVED R W HTOE R W R W R IRCTRIM[9:8] IRCTRIM[7:0] W R 0 TCTRIM[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSCE 0 0 0 0 Reserved W R W R W R VREG5VEN W R 0 PROT 0 EXTXON INTXON OMRE OSCMOD 0 0 W = Unimplemented or Reserved Figure 9-3. CPMU Register Summary MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 231 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) 9.3.2 Register Descriptions This section describes all the S12CPMU_UHV registers and their individual bits. Address order is as listed in Figure 9-3 9.3.2.1 Reserved Register CPMUVREGTRIM0 NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV’s functionality. . Module Base + 0x0001 7 6 5 4 0 0 0 0 Reset 0 0 0 0 F Power on Reset 0 0 0 0 0 R 3 2 1 0 F F F 0 0 0 U W Note: After de-assert of System Reset a value is automatically loaded from the Flash memory. Figure 9-4. Reserved Register (CPMUVREGTRIM0) Read: Anytime Write: Only in Special Mode 9.3.2.2 Reserved Register CPMUVREGTRIM1 NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV’s functionality. . MC912ZVL Family Reference Manual, Rev. 2.48 232 NXP Semiconductors S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) Module Base + 0x0002 7 6 0 0 Reset 0 0 F F F F F F Power on Reset 0 0 0 0 0 0 0 0 1 0 OMRF PMRF Note 4 Note 5 R 5 4 3 2 U W 1 0 U Note: After de-assert of System Reset a value is automatically loaded from the Flash memory. Figure 9-5. Reserved Register (CPMUVREGTRIM1) Read: Anytime Write: Only in Special Mode 9.3.2.3 S12CPMU_UHV Reset Flags Register (CPMURFLG) This register provides S12CPMU_UHV reset flags. Module Base + 0x0003 7 R 0 W Reset 0 6 5 PORF LVRF Note 1 Note 2 4 0 0 3 COPRF Note 3 2 0 0 1. PORF is set to 1 when a power on reset occurs. Unaffected by System Reset. 2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by System Reset. Set by power on reset. 3. COPRF is set to 1 when COP reset occurs. Unaffected by System Reset. Cleared by power on reset. 4. OMRF is set to 1 when an oscillator clock monitor reset occurs. Unaffected by System Reset. Cleared by power on reset. 5. PMRF is set to 1 when a PLL clock monitor reset occurs. Unaffected by System Reset. Cleared by power on reset. = Unimplemented or Reserved Figure 9-6. S12CPMU_UHV Flags Register (CPMURFLG) Read: Anytime Write: Refer to each bit for individual write conditions MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 233 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) Table 9-2. CPMURFLG Field Descriptions Field Description 6 PORF Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Power on reset has not occurred. 1 Power on reset has occurred. 5 LVRF Low Voltage Reset Flag — LVRF is set to 1 when a low voltage reset occurs on the VDD, VDDF or VDDX domain. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Low voltage reset has not occurred. 1 Low voltage reset has occurred. 3 COPRF COP Reset Flag — COPRF is set to 1 when a COP (Computer Operating Properly) reset occurs. Refer to 9.5.5, “Computer Operating Properly Watchdog (COP) Reset and 9.3.2.12, “S12CPMU_UHV COP Control Register (CPMUCOP) for details.This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 COP reset has not occurred. 1 COP reset has occurred. 1 OMRF Oscillator Clock Monitor Reset Flag — OMRF is set to 1 when a loss of oscillator (crystal) clock occurs. Refer to9.5.3, “Oscillator Clock Monitor Reset for details.This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Loss of oscillator clock reset has not occurred. 1 Loss of oscillator clock reset has occurred. 0 PMRF PLL Clock Monitor Reset Flag — PMRF is set to 1 when a loss of PLL clock occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Loss of PLL clock reset has not occurred. 1 Loss of PLL clock reset has occurred. 9.3.2.4 S12CPMU_UHV Synthesizer Register (CPMUSYNR) The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency range. Module Base + 0x0004 7 R W Reset 6 5 4 3 VCOFRQ[1:0] 0 1 2 1 0 0 0 0 SYNDIV[5:0] 0 1 1 Figure 9-7. S12CPMU_UHV Synthesizer Register (CPMUSYNR) Read: Anytime Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime. Else write has no effect. NOTE Writing to this register clears the LOCK and UPOSC status bits. MC912ZVL Family Reference Manual, Rev. 2.48 234 NXP Semiconductors S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) f VCO = 2  f REF   SYNDIV + 1  If PLL has locked (LOCK=1) NOTE fVCO must be within the specified VCO frequency lock range. Bus frequency fbus must not exceed the specified maximum. The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK frequency as shown in Table 9-3. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufficient stability). Table 9-3. VCO Clock Frequency Selection 9.3.2.5 VCOCLK Frequency Ranges VCOFRQ[1:0] 32MHz = PWMPERx XX 0 Always low Counter = $00 and does not count. Resets The reset state of each individual bit is listed within the Section 17.3.2, “Register Descriptions” which details the registers and their bit-fields. All special functions or modes which are initialized during or just following reset are described within this section. • The 8-bit up/down counter is configured as an up counter out of reset. • All the channels are disabled and all the counters do not count. MC912ZVL Family Reference Manual, Rev. 2.48 506 NXP Semiconductors Pulse-Width Modulator (S12PWM8B8CV2) • • 17.6 For channels 0, 1, 4, and 5 the clock choices are clock A. For channels 2, 3, 6, and 7 the clock choices are clock B. Interrupts The PWM module has no interrupt. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 507 Pulse-Width Modulator (S12PWM8B8CV2) MC912ZVL Family Reference Manual, Rev. 2.48 508 NXP Semiconductors Chapter 18 Serial Communication Interface (S12SCIV6) Table 18-1. Revision History Version Number Revision Date 06.06 03/11/2013 fix typo of BDL reset value,Figure 18-4 fix typo of Table 18-2,Table 18-16,reword 18.4.4/18-527 06.07 09/03/2013 update Figure 18-14./18-524 Figure 18-16./18-528 Figure 18-20./18-533 update 18.4.4/18-527,more detail for two baud add note for Table 18-16./18-527 update Figure 18-2./18-512,Figure 18-12./18-522 06.08 10/14/2013 update Figure 18-4./18-513 18.3.2.9/18-522 18.1 Effective Date Author Description of Changes Introduction This block guide provides an overview of the serial communication interface (SCI) module. The SCI allows asynchronous serial communications with peripheral devices and other CPUs. 18.1.1 Glossary IR: InfraRed IrDA: Infrared Design Associate IRQ: Interrupt Request LIN: Local Interconnect Network LSB: Least Significant Bit MSB: Most Significant Bit NRZ: Non-Return-to-Zero RZI: Return-to-Zero-Inverted RXD: Receive Pin SCI : Serial Communication Interface TXD: Transmit Pin MC9S12ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 509 Serial Communication Interface (S12SCIV6) 18.1.2 Features The SCI includes these distinctive features: • Full-duplex or single-wire operation • Standard mark/space non-return-to-zero (NRZ) format • Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths • 16-bit baud rate selection • Programmable 8-bit or 9-bit data format • Separately enabled transmitter and receiver • Programmable polarity for transmitter and receiver • Programmable transmitter output parity • Two receiver wakeup methods: — Idle line wakeup — Address mark wakeup • Interrupt-driven operation with eight flags: — Transmitter empty — Transmission complete — Receiver full — Idle receiver input — Receiver overrun — Noise error — Framing error — Parity error — Receive wakeup on active edge — Transmit collision detect supporting LIN — Break Detect supporting LIN • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection 18.1.3 Modes of Operation The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait and stop modes. • Run mode • Wait mode • Stop mode MC912ZVL Family Reference Manual, Rev. 2.48 510 NXP Semiconductors Serial Communication Interface (S12SCIV6) 18.1.4 Block Diagram Figure 18-1 is a high level block diagram of the SCI module, showing the interaction of various function blocks. SCI Data Register RXD Data In Bus Clock Infrared Decoder Receive Shift Register Receive & Wakeup Control Receive Baud Rate Generator IDLE Receive RDRF/OR Interrupt Generation BRKD RXEDG BERR Data Format Control Transmit Baud Rate Generator Transmit Control 1/16 Transmit Shift Register SCI Interrupt Request Transmit TDRE Interrupt Generation TC Infrared Encoder Data Out TXD SCI Data Register Figure 18-1. SCI Block Diagram 18.2 External Signal Description The SCI module has a total of two external pins. 18.2.1 TXD — Transmit Pin The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high impedance anytime the transmitter is disabled. 18.2.2 RXD — Receive Pin The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high. This input is ignored when the receiver is disabled and should be terminated to a known voltage. 18.3 Memory Map and Register Definition This section provides a detailed description of all the SCI registers. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 511 Serial Communication Interface (S12SCIV6) 18.3.1 Module Memory Map and Register Definition The memory map for the SCI module is given below in Figure 18-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the SCI module and the address offset for each register. 18.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to a reserved register locations do not have any effect and reads of these locations return a zero. Details of register bit and field function follow the register diagrams, in bit order. Register Name 0x0000 SCIBDH1 W 0x0001 SCIBDL1 W 0x0002 SCICR11 R R R W 0x0000 SCIASR12 W 0x0001 SCIACR12 W 0x0002 SCIACR22 R R R W 0x0003 SCICR2 W 0x0004 SCISR1 W 0x0005 SCISR2 R R R W Bit 7 6 5 4 3 2 1 Bit 0 SBR15 SBR14 SBR13 SBR12 SBR11 SBR10 SBR9 SBR8 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0 0 0 0 BERRV BERRIF BKDIF 0 0 0 0 BERRIE BKDIE IREN TNP1 TNP0 0 0 BERRM1 BERRM0 BKDFE TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PF 0 0 TXPOL RXPOL BRK13 TXDIR RXEDGIF RXEDGIE AMAP 0 RAF = Unimplemented or Reserved Figure 18-2. SCI Register Summary (Sheet 1 of 2) MC912ZVL Family Reference Manual, Rev. 2.48 512 NXP Semiconductors Serial Communication Interface (S12SCIV6) Register Name 0x0006 SCIDRH 0x0007 SCIDRL Bit 7 R 6 R8 T8 W 5 4 3 0 0 0 2 1 Bit 0 Reserved Reserved Reserved R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero. 2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one. = Unimplemented or Reserved Figure 18-2. SCI Register Summary (Sheet 2 of 2) 18.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) Module Base + 0x0000 R W Reset 7 6 5 4 3 2 1 0 SBR15 SBR14 SBR13 SBR12 SBR11 SBR10 SBR9 SBR8 0 0 0 0 0 0 0 0 Figure 18-3. SCI Baud Rate Register (SCIBDH) Module Base + 0x0001 R W Reset 7 6 5 4 3 2 1 0 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0 1 0 0 0 0 0 0 Figure 18-4. SCI Baud Rate Register (SCIBDL) Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0. NOTE Those two registers are only visible in the memory map if AMAP = 0 (reset condition). The SCI baud rate register is used by to determine the baud rate of the SCI, and to control the infrared modulation/demodulation submodule. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 513 Serial Communication Interface (S12SCIV6) Table 18-2. SCIBDH and SCIBDL Field Descriptions Field Description SBR[15:0] SCI Baud Rate Bits — The baud rate for the SCI is determined by the bits in this register. The baud rate is calculated two different ways depending on the state of the IREN bit. The formulas for calculating the baud rate are: When IREN = 0 then, SCI baud rate = SCI bus clock / (SBR[15:0]) When IREN = 1 then, SCI baud rate = SCI bus clock / (2 x SBR[15:1]) Note: The baud rate generator is disabled after reset and not started until the TE bit or the RE bit is set for the first time. The baud rate generator is disabled when (SBR[15:4] = 0 and IREN = 0) or (SBR[15:5] = 0 and IREN = 1). Note: . User should write SCIBD by word access. The updated SCIBD may take effect until next RT clock start, write SCIBDH or SCIBDL separately may cause baud generator load wrong data at that time,if second write later then RT clock. 18.3.2.2 SCI Control Register 1 (SCICR1) Module Base + 0x0002 R W Reset 7 6 5 4 3 2 1 0 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0 0 0 0 0 0 0 0 Figure 18-5. SCI Control Register 1 (SCICR1) Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0. NOTE This register is only visible in the memory map if AMAP = 0 (reset condition). Table 18-3. SCICR1 Field Descriptions Field Description 7 LOOPS Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must be enabled to use the loop function. 0 Normal operation enabled 1 Loop operation enabled The receiver input is determined by the RSRC bit. 6 SCISWAI SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode. 0 SCI enabled in wait mode 1 SCI disabled in wait mode MC912ZVL Family Reference Manual, Rev. 2.48 514 NXP Semiconductors Serial Communication Interface (S12SCIV6) Table 18-3. SCICR1 Field Descriptions (continued) Field 5 RSRC 4 M Description Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register input. See Table 18-4. 0 Receiver input internally connected to transmitter output 1 Receiver input connected externally to transmitter Data Format Mode Bit — MODE determines whether data characters are eight or nine bits long. 0 One start bit, eight data bits, one stop bit 1 One start bit, nine data bits, one stop bit 3 WAKE Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received data character or an idle condition on the RXD pin. 0 Idle line wakeup 1 Address mark wakeup 2 ILT Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 0 Idle character bit count begins after start bit 1 Idle character bit count begins after stop bit 1 PE Parity Enable Bit — PE enables the parity function. When enabled, the parity function inserts a parity bit in the most significant bit position. 0 Parity function disabled 1 Parity function enabled 0 PT Parity Type Bit — PT determines whether the SCI generates and checks for even parity or odd parity. With even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. 0 Even parity 1 Odd parity Table 18-4. Loop Functions 18.3.2.3 LOOPS RSRC Function 0 x Normal operation 1 0 Loop mode with transmitter output internally connected to receiver input 1 1 Single-wire mode with TXD pin connected to receiver input SCI Alternative Status Register 1 (SCIASR1) Module Base + 0x0000 7 R W Reset RXEDGIF 0 6 5 4 3 2 0 0 0 0 BERRV 0 0 0 0 0 1 0 BERRIF BKDIF 0 0 = Unimplemented or Reserved Figure 18-6. SCI Alternative Status Register 1 (SCIASR1) Read: Anytime, if AMAP = 1 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 515 Serial Communication Interface (S12SCIV6) Write: Anytime, if AMAP = 1 Table 18-5. SCIASR1 Field Descriptions Field 7 RXEDGIF Description Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it. 0 No active receive on the receive input has occurred 1 An active edge on the receive input has occurred 2 BERRV Bit Error Value — BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1. 0 A low input was sampled, when a high was expected 1 A high input reassembled, when a low was expected 1 BERRIF Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it. 0 No mismatch detected 1 A mismatch has occurred 0 BKDIF 18.3.2.4 Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing a “1” to it. 0 No break signal was received 1 A break signal was received SCI Alternative Control Register 1 (SCIACR1) Module Base + 0x0001 7 R W Reset RXEDGIE 0 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 1 0 BERRIE BKDIE 0 0 = Unimplemented or Reserved Figure 18-7. SCI Alternative Control Register 1 (SCIACR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 18-6. SCIACR1 Field Descriptions Field Description 7 RXEDGIE Receive Input Active Edge Interrupt Enable — RXEDGIE enables the receive input active edge interrupt flag, RXEDGIF, to generate interrupt requests. 0 RXEDGIF interrupt requests disabled 1 RXEDGIF interrupt requests enabled MC912ZVL Family Reference Manual, Rev. 2.48 516 NXP Semiconductors Serial Communication Interface (S12SCIV6) Table 18-6. SCIACR1 Field Descriptions (continued) Field 1 BERRIE 0 BKDIE 18.3.2.5 Description Bit Error Interrupt Enable — BERRIE enables the bit error interrupt flag, BERRIF, to generate interrupt requests. 0 BERRIF interrupt requests disabled 1 BERRIF interrupt requests enabled Break Detect Interrupt Enable — BKDIE enables the break detect interrupt flag, BKDIF, to generate interrupt requests. 0 BKDIF interrupt requests disabled 1 BKDIF interrupt requests enabled SCI Alternative Control Register 2 (SCIACR2) Module Base + 0x0002 7 R W Reset 6 5 IREN TNP1 TNP0 0 0 0 4 3 0 0 0 0 2 1 0 BERRM1 BERRM0 BKDFE 0 0 0 = Unimplemented or Reserved Figure 18-8. SCI Alternative Control Register 2 (SCIACR2) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 18-7. SCIACR2 Field Descriptions Field 7 IREN 6:5 TNP[1:0] Description Infrared Enable Bit — This bit enables/disables the infrared modulation/demodulation submodule. 0 IR disabled 1 IR enabled Transmitter Narrow Pulse Bits — These bits enable whether the SCI transmits a 1/16, 3/16, 1/32 or 1/4 narrow pulse. See Table 18-8. 2:1 Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See Table 18-9. BERRM[1:0] 0 BKDFE Break Detect Feature Enable — BKDFE enables the break detect circuitry. 0 Break detect circuit disabled 1 Break detect circuit enabled Table 18-8. IRSCI Transmit Pulse Width TNP[1:0] Narrow Pulse Width 11 1/4 10 1/32 01 1/16 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 517 Serial Communication Interface (S12SCIV6) Table 18-8. IRSCI Transmit Pulse Width TNP[1:0] Narrow Pulse Width 00 3/16 Table 18-9. Bit Error Mode Coding 18.3.2.6 BERRM1 BERRM0 Function 0 0 Bit error detect circuit is disabled 0 1 Receive input sampling occurs during the 9th time tick of a transmitted bit (refer to Figure 18-19) 1 0 Receive input sampling occurs during the 13th time tick of a transmitted bit (refer to Figure 18-19) 1 1 Reserved SCI Control Register 2 (SCICR2) Module Base + 0x0003 R W Reset 7 6 5 4 3 2 1 0 TIE TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Figure 18-9. SCI Control Register 2 (SCICR2) Read: Anytime Write: Anytime Table 18-10. SCICR2 Field Descriptions Field 7 TIE Description Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests. 0 TDRE interrupt requests disabled 1 TDRE interrupt requests enabled 6 TCIE Transmission Complete Interrupt Enable Bit — TCIE enables the transmission complete flag, TC, to generate interrupt requests. 0 TC interrupt requests disabled 1 TC interrupt requests enabled 5 RIE Receiver Full Interrupt Enable Bit — RIE enables the receive data register full flag, RDRF, or the overrun flag, OR, to generate interrupt requests. 0 RDRF and OR interrupt requests disabled 1 RDRF and OR interrupt requests enabled 4 ILIE Idle Line Interrupt Enable Bit — ILIE enables the idle line flag, IDLE, to generate interrupt requests. 0 IDLE interrupt requests disabled 1 IDLE interrupt requests enabled MC912ZVL Family Reference Manual, Rev. 2.48 518 NXP Semiconductors Serial Communication Interface (S12SCIV6) Table 18-10. SCICR2 Field Descriptions (continued) Field Description 3 TE Transmitter Enable Bit — TE enables the SCI transmitter and configures the TXD pin as being controlled by the SCI. The TE bit can be used to queue an idle preamble. 0 Transmitter disabled 1 Transmitter enabled 2 RE Receiver Enable Bit — RE enables the SCI receiver. 0 Receiver disabled 1 Receiver enabled 1 RWU Receiver Wakeup Bit — Standby state 0 Normal operation. 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. 0 SBK Send Break Bit — Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits). 0 No break characters 1 Transmit break characters 18.3.2.7 SCI Status Register 1 (SCISR1) The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures require that the status register be read followed by a read or write to the SCI data register.It is permissible to execute other instructions between the two steps as long as it does not compromise the handling of I/O, but the order of operations is important for flag clearing. Module Base + 0x0004 R 7 6 5 4 3 2 1 0 TDRE TC RDRF IDLE OR NF FE PF 1 0 0 0 0 0 0 W Reset 1 = Unimplemented or Reserved Figure 18-10. SCI Status Register 1 (SCISR1) Read: Anytime Write: Has no meaning or effect MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 519 Serial Communication Interface (S12SCIV6) Table 18-11. SCISR1 Field Descriptions Field Description 7 TDRE Transmit Data Register Empty Flag — TDRE is set when the transmit shift register receives a byte from the SCI data register. When TDRE is 1, the transmit data register (SCIDRH/L) is empty and can receive a new value to transmit.Clear TDRE by reading SCI status register 1 (SCISR1), with TDRE set and then writing to SCI data register low (SCIDRL). 0 No byte transferred to transmit shift register 1 Byte transferred to transmit shift register; transmit data register empty 6 TC Transmit Complete Flag — TC is set low when there is a transmission in progress or when a preamble or break character is loaded. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted.When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL). TC is cleared automatically when data, preamble, or break is queued and ready to be sent. TC is cleared in the event of a simultaneous set and clear of the TC flag (transmission not complete). 0 Transmission in progress 1 No transmission in progress 5 RDRF Receive Data Register Full Flag — RDRF is set when the data in the receive shift register transfers to the SCI data register. Clear RDRF by reading SCI status register 1 (SCISR1) with RDRF set and then reading SCI data register low (SCIDRL). 0 Data not available in SCI data register 1 Received data available in SCI data register 4 IDLE Idle Line Flag — IDLE is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M =1) appear on the receiver input. Once the IDLE flag is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag.Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL). 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared 1 Receiver input has become idle Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag. 3 OR Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected. Clear OR by reading SCI status register 1 (SCISR1) with OR set and then reading SCI data register low (SCIDRL). 0 No overrun 1 Overrun Note: OR flag may read back as set when RDRF flag is clear. This may happen if the following sequence of events occurs: 1. After the first frame is received, read status register SCISR1 (returns RDRF set and OR flag clear); 2. Receive second frame without reading the first frame in the data register (the second frame is not received and OR flag is set); 3. Read data register SCIDRL (returns first frame and clears RDRF flag in the status register); 4. Read status register SCISR1 (returns RDRF clear and OR set). Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received. 2 NF Noise Flag — NF is set when the SCI detects noise on the receiver input. NF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1), and then reading SCI data register low (SCIDRL). 0 No noise 1 Noise MC912ZVL Family Reference Manual, Rev. 2.48 520 NXP Semiconductors Serial Communication Interface (S12SCIV6) Table 18-11. SCISR1 Field Descriptions (continued) Field Description 1 FE Framing Error Flag — FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register low (SCIDRL). 0 No framing error 1 Framing error 0 PF Parity Error Flag — PF is set when the parity enable bit (PE) is set and the parity of the received data does not match the parity type bit (PT). PF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low (SCIDRL). 0 No parity error 1 Parity error 18.3.2.8 SCI Status Register 2 (SCISR2) Module Base + 0x0005 7 R W Reset AMAP 0 6 5 0 0 0 0 4 3 2 1 TXPOL RXPOL BRK13 TXDIR 0 0 0 0 0 RAF 0 = Unimplemented or Reserved Figure 18-11. SCI Status Register 2 (SCISR2) Read: Anytime Write: Anytime Table 18-12. SCISR2 Field Descriptions Field Description 7 AMAP Alternative Map — This bit controls which registers sharing the same address space are accessible. In the reset condition the SCI behaves as previous versions. Setting AMAP=1 allows the access to another set of control and status registers and hides the baud rate and SCI control Register 1. 0 The registers labelled SCIBDH (0x0000),SCIBDL (0x0001), SCICR1 (0x0002) are accessible 1 The registers labelled SCIASR1 (0x0000),SCIACR1 (0x0001), SCIACR2 (0x00002) are accessible 4 TXPOL Transmit Polarity — This bit control the polarity of the transmitted data. In NRZ format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity. 0 Normal polarity 1 Inverted polarity MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 521 Serial Communication Interface (S12SCIV6) Table 18-12. SCISR2 Field Descriptions (continued) Field Description 3 RXPOL Receive Polarity — This bit control the polarity of the received data. In NRZ format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity. 0 Normal polarity 1 Inverted polarity 2 BRK13 Break Transmit Character Length — This bit determines whether the transmit break character is 10 or 11 bit respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit. 0 Break character is 10 or 11 bit long 1 Break character is 13 or 14 bit long 1 TXDIR Transmitter Pin Data Direction in Single-Wire Mode — This bit determines whether the TXD pin is going to be used as an input or output, in the single-wire mode of operation. This bit is only relevant in the single-wire mode of operation. 0 TXD pin to be used as an input in single-wire mode 1 TXD pin to be used as an output in single-wire mode 0 RAF Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character. 0 No reception in progress 1 Reception in progress 18.3.2.9 SCI Data Registers (SCIDRH, SCIDRL) Module Base + 0x0006 7 R R8 W Reset 0 6 T8 0 5 4 3 0 0 0 0 0 0 2 1 0 Reserved Reserved Reserved 0 0 0 = Unimplemented or Reserved Figure 18-12. SCI Data Registers (SCIDRH) Module Base + 0x0007 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Reset Figure 18-13. SCI Data Registers (SCIDRL) Read: Anytime; reading accesses SCI receive data register Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect MC912ZVL Family Reference Manual, Rev. 2.48 522 NXP Semiconductors Serial Communication Interface (S12SCIV6) NOTE The reserved bit SCIDRH[2:0] are designed for factory test purposes only, and are not intended for general user access. Writing to these bit is possible when in special mode and can alter the modules functionality. Table 18-13. SCIDRH and SCIDRL Field Descriptions Field Description SCIDRH 7 R8 Received Bit 8 — R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1). SCIDRH 6 T8 Transmit Bit 8 — T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1). SCIDRL 7:0 R[7:0] T[7:0] R7:R0 — Received bits seven through zero for 9-bit or 8-bit data formats T7:T0 — Transmit bits seven through zero for 9-bit or 8-bit formats NOTE If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.The same value is transmitted until T8 is rewritten In 8-bit data format, only SCI data register low (SCIDRL) needs to be accessed. When transmitting in 9-bit data format and using 8-bit write instructions, write first to SCI data register high (SCIDRH), then SCIDRL. 18.4 Functional Description This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspective in a number of subsections. Figure 18-14 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial communication between the CPU and remote devices, including other CPUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 523 Serial Communication Interface (S12SCIV6) R8 IREN SCI Data Register FE Ir_RXD SCRXD Receive and Wakeup Control R16XCLK Bus Clock Receive Shift Register PF RAF RE IDLE RWU RDRF LOOPS OR RSRC M Receive Baud Rate Generator IDLE ILIE RDRF/OR Infrared Receive Decoder RXD NF RIE TIE WAKE Data Format Control ILT PE SBR15:SBR0 TDRE TDRE TC PT SCI Interrupt Request TC TCIE TE Transmit Baud Rate Generator 16 Transmit Control LOOPS SBK RSRC T8 Transmit Shift Register RXEDGIE Active Edge Detect RXEDGIF BKDIF RXD SCI Data Register Break Detect BKDFE SCTXD BKDIE LIN Transmit BERRIF Collision Detect BERRIE R16XCLK Infrared Transmit Encoder BERRM[1:0] Ir_TXD TXD R32XCLK TNP[1:0] IREN Figure 18-14. Detailed SCI Block Diagram 18.4.1 Infrared Interface Submodule This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer specification defines a half-duplex infrared communication link for exchange data. The full standard includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 Kbits/s and 115.2 Kbits/s. The infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. The SCI transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse MC912ZVL Family Reference Manual, Rev. 2.48 524 NXP Semiconductors Serial Communication Interface (S12SCIV6) for every zero bit. No pulse is transmitted for every one bit. When receiving data, the IR pulses should be detected using an IR photo diode and transformed to CMOS levels by the IR receive decoder (external from the MCU). The narrow pulses are then stretched by the infrared submodule to get back to a serial bit stream to be received by the SCI.The polarity of transmitted pulses and expected receive pulses can be inverted so that a direct connection can be made to external IrDA transceiver modules that use active low pulses. The infrared submodule receives its clock sources from the SCI. One of these two clocks are selected in the infrared submodule in order to generate either 3/16, 1/16, 1/32 or 1/4 narrow pulses during transmission. The infrared block receives two clock sources from the SCI, R16XCLK and R32XCLK, which are configured to generate the narrow pulse width during transmission. The R16XCLK and R32XCLK are internal clocks with frequencies 16 and 32 times the baud rate respectively. Both R16XCLK and R32XCLK clocks are used for transmitting data. The receive decoder uses only the R16XCLK clock. 18.4.1.1 Infrared Transmit Encoder The infrared transmit encoder converts serial bits of data from transmit shift register to the TXD pin. A narrow pulse is transmitted for a zero bit and no pulse for a one bit. The narrow pulse is sent in the middle of the bit with a duration of 1/32, 1/16, 3/16 or 1/4 of a bit time. A narrow high pulse is transmitted for a zero bit when TXPOL is cleared, while a narrow low pulse is transmitted for a zero bit when TXPOL is set. 18.4.1.2 Infrared Receive Decoder The infrared receive block converts data from the RXD pin to the receive shift register. A narrow pulse is expected for each zero received and no pulse is expected for each one received. A narrow high pulse is expected for a zero bit when RXPOL is cleared, while a narrow low pulse is expected for a zero bit when RXPOL is set. This receive decoder meets the edge jitter requirement as defined by the IrDA serial infrared physical layer specification. 18.4.2 LIN Support This module provides some basic support for the LIN protocol. At first this is a break detect circuitry making it easier for the LIN software to distinguish a break character from an incoming data stream. As a further addition is supports a collision detection at the bit level as well as cancelling pending transmissions. 18.4.3 Data Format The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain low. See Figure 18-15 below. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 525 Serial Communication Interface (S12SCIV6) 8-Bit Data Format (Bit M in SCICR1 Clear) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Possible Parity Bit Bit 6 STOP Bit Bit 7 Next Start Bit Standard SCI Data Infrared SCI Data 9-Bit Data Format (Bit M in SCICR1 Set) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 POSSIBLE PARITY Bit Bit 6 Bit 7 Bit 8 STOP Bit NEXT START Bit Standard SCI Data Infrared SCI Data Figure 18-15. SCI Data Formats Each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit. Clearing the M bit in SCI control register 1 configures the SCI for 8-bit data characters. A frame with eight data bits has a total of 10 bits. Setting the M bit configures the SCI for nine-bit data characters. A frame with nine data bits has a total of 11 bits. Table 18-14. Example of 8-Bit Data Formats Start Bit Data Bits Address Bits Parity Bits Stop Bit 1 8 0 0 1 1 7 0 1 1 7 1 0 1 1 1 1 The address bit identifies the frame as an address character. See Section 18.4.6.6, “Receiver Wakeup”. When the SCI is configured for 9-bit data characters, the ninth data bit is the T8 bit in SCI data register high (SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it. A frame with nine data bits has a total of 11 bits. Table 18-15. Example of 9-Bit Data Formats Start Bit Data Bits Address Bits Parity Bits Stop Bit 1 9 0 0 1 1 8 0 1 1 8 1 0 1 1 1 1 The address bit identifies the frame as an address character. See Section 18.4.6.6, “Receiver Wakeup”. MC912ZVL Family Reference Manual, Rev. 2.48 526 NXP Semiconductors Serial Communication Interface (S12SCIV6) 18.4.4 Baud Rate Generation A 16-bit modulus counter in the two baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 65535 written to the SBR15:SBR0 bits determines the baud rate. The value from 0 to 4095 written to the SBR15:SBR4 bits determines the baud rate clock with SBR3:SBR0 for fine adjust. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL) for both transmit and receive baud generator. The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The receiver has an acquisition rate of 16 samples per bit time. Baud rate generation is subject to one source of error: • Integer division of the bus clock may not give the exact target frequency. Table 18-16 lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz. When IREN = 0 then, SCI baud rate = SCI bus clock / (SCIBR[15:0]) Table 18-16. Baud Rates (Example: Bus Clock = 25 MHz) 1 2 Bits SBR[15:0] Receiver1 Clock (Hz) Transmitter2 Clock (Hz) Target Baud Rate Error (%) 109 3669724.8 229,357.8 230,400 .452 217 1843318.0 115,207.4 115,200 .006 651 614439.3 38,402.5 38,400 .006 1302 307219.7 19,201.2 19,200 .006 2604 153,609.8 9600.6 9,600 .006 5208 76,804.9 4800.3 4,800 .006 10417 38,398.8 2399.9 2,400 .003 20833 19,200.3 1200.02 1,200 .00 41667 9599.9 600.0 600 .00 65535 6103.6 381.5 16x faster then baud rate divide 1/16 form transmit baud generator MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 527 Serial Communication Interface (S12SCIV6) 18.4.5 Transmitter Internal Bus Transmit baud generator SBR15:SBR4 16 SCI Data Registers Stop SBR3:SBR0 11-Bit Transmit Register H 8 7 6 5 4 3 2 1 0 TXPOL SCTXD L MSB M Start Bus Clock LOOP CONTROL TIE Break (All 0s) TDRE IRQ Parity Generation Preamble (All 1s) PT Shift Enable PE Load from SCIDR T8 To Receiver LOOPS RSRC TDRE TC IRQ TC Transmitter Control TCIE TE BER IRQ BERRIF TCIE SBK BERRM[1:0] Transmit Collision Detect SCTXD SCRXD (From Receiver) Figure 18-16. Transmitter Block Diagram 18.4.5.1 Transmitter Character Length The SCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When transmitting 9-bit data, bit T8 in SCI data register high (SCIDRH) is the ninth bit (bit 8). 18.4.5.2 Character Transmission To transmit data, the MCU writes the data bits to the SCI data registers (SCIDRH/SCIDRL), which in turn are transferred to the transmitter shift register. The transmit shift register then shifts a frame out through the TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. MC912ZVL Family Reference Manual, Rev. 2.48 528 NXP Semiconductors Serial Communication Interface (S12SCIV6) The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag by writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting out the first byte. To initiate an SCI transmission: 1. Configure the SCI: a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud rate generator. Remember that the baud rate generator is disabled when the baud rate is zero. Writing to the SCIBDH has no effect without also writing to SCIBDL. b) Write to SCICR1 to configure word length, parity, and other configuration bits (LOOPS,RSRC,M,WAKE,ILT,PE,PT). c) Enable the transmitter, interrupts, receive, and wake up as required, by writing to the SCICR2 register bits (TIE,TCIE,RIE,ILIE,TE,RE,RWU,SBK). A preamble or idle character will now be shifted out of the transmitter shift register. 2. Transmit Procedure for each byte: a) Poll the TDRE flag by reading the SCISR1 or responding to the TDRE interrupt. Keep in mind that the TDRE bit resets to one. b) If the TDRE flag is set, write the data to be transmitted to SCIDRH/L, where the ninth bit is written to the T8 bit in SCIDRH if the SCI is in 9-bit data format. A new transmission will not result until the TDRE flag has been cleared. 3. Repeat step 2 for each subsequent transmission. NOTE The TDRE flag is set when the shift register is loaded with the next data to be transmitted from SCIDRH/L, which happens, generally speaking, a little over half-way through the stop bit of the previous frame. Specifically, this transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the previous frame. Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic 1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. Hardware supports odd or even parity. When parity is enabled, the most significant bit (MSB) of the data character is the parity bit. The transmit data register empty flag, TDRE, in SCI status register 1 (SCISR1) becomes set when the SCI data register transfers a byte to the transmit shift register. The TDRE flag indicates that the SCI data register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE flag generates a transmitter interrupt request. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 529 Serial Communication Interface (S12SCIV6) When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle. If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE to go high after the last frame before clearing TE. To separate messages with preambles with minimum idle line time, use this sequence between messages: 1. Write the last byte of the first message to SCIDRH/L. 2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the transmit shift register. 3. Queue a preamble by clearing and then setting the TE bit. 4. Write the first byte of the second message to SCIDRH/L. 18.4.5.3 Break Characters Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCI control register 1 (SCICR1). As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame. The SCI recognizes a break character when there are 10 or 11(M = 0 or M = 1) consecutive zero received. Depending if the break detect feature is enabled or not receiving a break character has these effects on SCI registers. If the break detect feature is disabled (BKDFE = 0): • Sets the framing error flag, FE • Sets the receive data register full flag, RDRF • Clears the SCI data registers (SCIDRH/L) • May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF (see 3.4.4 and 3.4.5 SCI Status Register 1 and 2) If the break detect feature is enabled (BKDFE = 1) there are two scenarios1 The break is detected right from a start bit or is detected during a byte reception. • Sets the break detect interrupt flag, BKDIF • Does not change the data register full flag, RDRF or overrun flag OR • Does not change the framing error flag FE, parity error flag PE. • Does not clear the SCI data registers (SCIDRH/L) • May set noise flag NF, or receiver active flag RAF. 1. A Break character in this context are either 10 or 11 consecutive zero received bits MC912ZVL Family Reference Manual, Rev. 2.48 530 NXP Semiconductors Serial Communication Interface (S12SCIV6) Figure 18-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit, while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there will be no byte transferred to the receive buffer and the RDRF flag will not be modified. Also no framing error or parity error will be flagged from this transfer. In RXD_2 case, however the break signal starts later during the transmission. At the expected stop bit position the byte received so far will be transferred to the receive buffer, the receive data register full flag will be set, a framing error and if enabled and appropriate a parity error will be set. Once the break is detected the BRKDIF flag will be set. Start Bit Position Stop Bit Position BRKDIF = 1 RXD_1 Zero Bit Counter 1 2 3 4 5 6 7 8 9 10 . . . BRKDIF = 1 FE = 1 RXD_2 Zero Bit Counter 1 2 3 4 5 6 7 8 9 10 ... Figure 18-17. Break Detection if BRKDFE = 1 (M = 0) 18.4.5.4 Idle Characters An idle character (or preamble) contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle character that begins the first transmission initiated after writing the TE bit from 0 to 1. If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the frame currently being transmitted. NOTE When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current frame shifts out through the TXD pin. Setting TE after the stop bit appears on TXD causes data previously written to the SCI data register to be lost. Toggle the TE bit for a queued idle character while the TDRE flag is set and immediately before writing the next byte to the SCI data register. If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 531 Serial Communication Interface (S12SCIV6) 18.4.5.5 LIN Transmit Collision Detection This module allows to check for collisions on the LIN bus. LIN Physical Interface Synchronizer Stage Receive Shift Register Compare Bit Error RXD Pin LIN Bus Bus Clock Sample Point Transmit Shift Register TXD Pin Figure 18-18. Collision Detect Principle If the bit error circuit is enabled (BERRM[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the transmitted and the received data stream at a point in time and flag any mismatch. The timing checks run when transmitter is active (not idle). As soon as a mismatch between the transmitted data and the received data is detected the following happens: • The next bit transmitted will have a high level (TXPOL = 0) or low level (TXPOL = 1) • The transmission is aborted and the byte in transmit buffer is discarded. • the transmit data register empty and the transmission complete flag will be set • The bit error interrupt flag, BERRIF, will be set. • No further transmissions will take place until the BERRIF is cleared. 4 5 6 7 8 BERRM[1:0] = 0:1 9 10 11 12 13 14 15 0 Sampling End 3 Sampling Begin Input Receive Shift Register 2 Sampling End Output Transmit Shift Register 1 Sampling Begin 0 BERRM[1:0] = 1:1 Compare Sample Points Figure 18-19. Timing Diagram Bit Error Detection If the bit error detect feature is disabled, the bit error interrupt flag is cleared. NOTE The RXPOL and TXPOL bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt flag may be set incorrectly. MC912ZVL Family Reference Manual, Rev. 2.48 532 NXP Semiconductors Serial Communication Interface (S12SCIV6) 18.4.6 Receiver Internal Bus RXPOL Data Recovery Loop Control H 11-Bit Receive Shift Register 8 7 6 5 4 3 2 1 0 L All 1s SCRXD From TXD Pin or Transmitter Stop Receive Baud Generator MSB Bus Clock SCI Data Register SBR3:SBR0 Start SBR15:SBR4 RE RAF LOOPS RSRC FE M WAKE ILT PE PT RWU NF Wakeup Logic PE R8 Parity Checking Idle IRQ IDLE ILIE BRKDFE OR Break Detect Logic Active Edge Detect Logic RDRF/OR IRQ RDRF BRKDIF BRKDIE RXEDGIF RXEDGIE RIE Break IRQ RX Active Edge IRQ Figure 18-20. SCI Receiver Block Diagram 18.4.6.1 Receiver Character Length The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in SCI data register high (SCIDRH) is the ninth bit (bit 8). 18.4.6.2 Character Reception During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register is the read-only buffer between the internal data bus and the receive shift register. After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set, MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 533 Serial Communication Interface (S12SCIV6) indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request. 18.4.6.3 Data Sampling The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock (see Figure 18-21) is re-synchronized immediatelly at bus clock edge: • After every start bit • After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. Start Bit LSB RXD Samples 1 1 1 1 1 1 1 1 0 0 Start Bit Qualification 0 0 Start Bit Verification 0 0 0 Data Sampling RT4 RT3 RT2 RT1 RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT CLock Count RT1 RT Clock Reset RT Clock Figure 18-21. Receiver Data Sampling To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Figure 18-17 summarizes the results of the start bit verification samples. Table 18-17. Start Bit Verification RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag 000 Yes 0 001 Yes 1 010 Yes 1 011 No 0 100 Yes 1 101 No 0 110 No 0 111 No 0 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. MC912ZVL Family Reference Manual, Rev. 2.48 534 NXP Semiconductors Serial Communication Interface (S12SCIV6) To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 18-18 summarizes the results of the data bit samples. Table 18-18. Data Bit Recovery RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 NOTE The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit (logic 0). To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 18-19 summarizes the results of the stop bit samples. Table 18-19. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 In Figure 18-22 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 535 Serial Communication Interface (S12SCIV6) Start Bit LSB 0 0 0 0 0 0 RT10 1 RT9 RT1 1 RT8 RT1 1 RT7 0 RT1 1 RT1 1 RT5 1 RT1 Samples RT1 RXD 0 RT3 RT2 RT1 RT16 RT15 RT14 RT13 RT12 RT11 RT6 RT5 RT4 RT3 RT2 RT4 RT3 RT Clock Count RT2 RT Clock Reset RT Clock Figure 18-22. Start Bit Search Example 1 In Figure 18-23, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. Perceived Start Bit Actual Start Bit LSB 1 0 RT1 RT1 RT1 RT1 1 0 0 0 0 0 RT10 1 RT9 1 RT8 1 RT7 1 RT1 Samples RT1 RXD RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT16 RT15 RT14 RT13 RT12 RT11 RT6 RT5 RT4 RT3 RT Clock Count RT2 RT Clock Reset RT Clock Figure 18-23. Start Bit Search Example 2 In Figure 18-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. MC912ZVL Family Reference Manual, Rev. 2.48 536 NXP Semiconductors Serial Communication Interface (S12SCIV6) Perceived Start Bit LSB Actual Start Bit RT1 RT1 0 1 0 0 0 0 RT10 0 RT9 1 RT8 1 RT1 Samples RT7 1 RT1 RXD RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT16 RT15 RT14 RT13 RT12 RT11 RT6 RT5 RT4 RT3 RT Clock Count RT2 RT Clock Reset RT Clock Figure 18-24. Start Bit Search Example 3 Figure 18-25 shows the effect of noise early in the start bit time. Although this noise does not affect proper synchronization with the start bit time, it does set the noise flag. Perceived and Actual Start Bit LSB 1 1 1 1 1 1 1 1 1 0 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RXD Samples 1 0 RT3 RT2 RT1 RT16 RT15 RT14 RT13 RT12 RT11 RT9 RT10 RT8 RT7 RT6 RT5 RT4 RT3 RT Clock Count RT2 RT Clock Reset RT Clock Figure 18-25. Start Bit Search Example 4 Figure 18-26 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 537 Serial Communication Interface (S12SCIV6) Start Bit 0 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 0 1 1 0 0 0 0 0 0 0 0 RT1 1 RT1 1 RT1 1 RT1 1 RT1 1 RT1 1 RT1 1 RT1 1 RT7 1 RT1 Samples LSB No Start Bit Found RXD RT1 RT1 RT1 RT1 RT6 RT5 RT4 RT3 RT Clock Count RT2 RT Clock Reset RT Clock Figure 18-26. Start Bit Search Example 5 In Figure 18-27, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are ignored. Start Bit LSB 1 1 1 1 1 0 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 0 0 0 1 0 1 RT10 1 RT9 1 RT8 1 RT7 1 RT1 Samples RT1 RXD RT3 RT2 RT1 RT16 RT15 RT14 RT13 RT12 RT11 RT6 RT5 RT4 RT3 RT Clock Count RT2 RT Clock Reset RT Clock Figure 18-27. Start Bit Search Example 6 18.4.6.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error flag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE flag because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set. 18.4.6.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9, and RT10 stop bit samples are a logic zero. MC912ZVL Family Reference Manual, Rev. 2.48 538 NXP Semiconductors Serial Communication Interface (S12SCIV6) As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge within the frame. Re synchronization within frames will correct a misalignment between transmitter bit times and receiver bit times. 18.4.6.5.1 Slow Data Tolerance Figure 18-28 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. MSB Stop RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 Receiver RT Clock Data Samples Figure 18-28. Slow Data Let’s take RTr as receiver RT clock and RTt as transmitter RT clock. For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles +7 RTr cycles = 151 RTr cycles to start data sampling of the stop bit. With the misaligned character shown in Figure 18-28, the receiver counts 151 RTr cycles at the point when the count of the transmitting device is 9 bit times x 16 RTt cycles = 144 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: ((151 – 144) / 151) x 100 = 4.63% For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles to start data sampling of the stop bit. With the misaligned character shown in Figure 18-28, the receiver counts 167 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((167 – 160) / 167) X 100 = 4.19% 18.4.6.5.2 Fast Data Tolerance Figure 18-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 539 Serial Communication Interface (S12SCIV6) Stop Idle or Next Frame RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 Receiver RT Clock Data Samples Figure 18-29. Fast Data For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 9 RTr cycles = 153 RTr cycles to finish data sampling of the stop bit. With the misaligned character shown in Figure 18-29, the receiver counts 153 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: ((160 – 153) / 160) x 100 = 4.375% For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 9 RTr cycles = 169 RTr cycles to finish data sampling of the stop bit. With the misaligned character shown in Figure 18-29, the receiver counts 169 RTr cycles at the point when the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: ((176 – 169) /176) x 100 = 3.98% NOTE Due to asynchronous sample and internal logic, there is maximal 2 bus cycles between startbit edge and 1st RT clock, and cause to additional tolerance loss at worst case. The loss should be 2/SBR/10*100%, it is small.For example, for highspeed baud=230400 with 25MHz bus, SBR should be 109, and the tolerance loss is 2/109/10*100=0.18%, and fast data tolerance is 4.375%-0.18%=4.195%. 18.4.6.6 Receiver Wakeup To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2 (SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will still load the receive data into the SCIDRH/L registers, but it will not set the RDRF flag. The transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. MC912ZVL Family Reference Manual, Rev. 2.48 540 NXP Semiconductors Serial Communication Interface (S12SCIV6) The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark wakeup. 18.4.6.6.1 Idle Input line Wakeup (WAKE = 0) In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another idle character appears on the RXD pin. Idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. The idle character that wakes a receiver does not set the receiver idle bit, IDLE, or the receive data register full flag, RDRF. The idle line type bit, ILT, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. ILT is in SCI control register 1 (SCICR1). 18.4.6.6.2 Address Mark Wakeup (WAKE = 1) In this wakeup method, a logic 1 in the most significant bit (MSB) position of a frame clears the RWU bit and wakes up the SCI. The logic 1 in the MSB position marks a frame as an address frame that contains addressing information. All receivers evaluate the addressing information, and the receivers for which the message is addressed process the frames that follow.Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another address frame appears on the RXD pin. The logic 1 MSB of an address frame clears the receiver’s RWU bit before the stop bit is received and sets the RDRF flag. Address mark wakeup allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. NOTE With the WAKE bit clear, setting the RWU bit after the RXD pin has been idle can cause the receiver to wake up immediately. 18.4.7 Single-Wire Operation Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 541 Serial Communication Interface (S12SCIV6) Transmitter Receiver TXD RXD Figure 18-30. Single-Wire Operation (LOOPS = 1, RSRC = 1) Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).The TXDIR bit (SCISR2[1]) determines whether the TXD pin is going to be used as an input (TXDIR = 0) or an output (TXDIR = 1) in this mode of operation. NOTE In single-wire operation data from the TXD pin is inverted if RXPOL is set. 18.4.8 Loop Operation In loop operation the transmitter output goes to the receiver input. The RXD pin is disconnected from the SCI. Transmitter TXD Receiver RXD Figure 18-31. Loop Operation (LOOPS = 1, RSRC = 0) Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1). NOTE In loop operation data from the transmitter is not recognized by the receiver if RXPOL and TXPOL are not the same. 18.5 18.5.1 Initialization/Application Information Reset Initialization See Section 18.3.2, “Register Descriptions”. MC912ZVL Family Reference Manual, Rev. 2.48 542 NXP Semiconductors Serial Communication Interface (S12SCIV6) 18.5.2 18.5.2.1 Modes of Operation Run Mode Normal mode of operation. To initialize a SCI transmission, see Section 18.4.5.2, “Character Transmission”. 18.5.2.2 Wait Mode SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCICR1). • If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode. • If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE. If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The transmission or reception resumes when either an internal or external interrupt brings the CPU out of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and resets the SCI. 18.5.2.3 Stop Mode The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not affect the SCI register states, but the SCI bus clock will be disabled. The SCI operation resumes from where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI. The receive input active edge detect circuit is still active in stop mode. An active edge on the receive input can be used to bring the CPU out of stop mode. 18.5.3 Interrupt Operation This section describes the interrupt originated by the SCI block.The MCU must service the interrupt requests. Table 18-20 lists the eight interrupt sources of the SCI. Table 18-20. SCI Interrupt Sources Interrupt Source Local Enable TDRE SCISR1[7] TIE TC SCISR1[6] TCIE RDRF SCISR1[5] RIE OR SCISR1[3] IDLE SCISR1[4] Description Active high level. Indicates that a byte was transferred from SCIDRH/L to the transmit shift register. Active high level. Indicates that a transmit is complete. Active high level. The RDRF interrupt indicates that received data is available in the SCI data register. Active high level. This interrupt indicates that an overrun condition has occurred. ILIE Active high level. Indicates that receiver input has become idle. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 543 Serial Communication Interface (S12SCIV6) Table 18-20. SCI Interrupt Sources RXEDGIF SCIASR1[7] RXEDGIE BERRIF SCIASR1[1] BERRIE Active high level. Indicates that a mismatch between transmitted and received data in a single wire application has happened. BKDIF SCIASR1[0] BRKDIE Active high level. Indicates that a break character has been received. 18.5.3.1 Active high level. Indicates that an active edge (falling for RXPOL = 0, rising for RXPOL = 1) was detected. Description of Interrupt Operation The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and all the following interrupts, when generated, are ORed together and issued through that port. 18.5.3.1.1 TDRE Description The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a new byte can be written to the SCIDRH/L for transmission.Clear TDRE by reading SCI status register 1 with TDRE set and then writing to SCI data register low (SCIDRL). 18.5.3.1.2 TC Description The TC interrupt is set by the SCI when a transmission has been completed. Transmission is completed when all bits including the stop bit (if transmitted) have been shifted out and no data is queued to be transmitted. No stop bit is transmitted when sending a break character and the TC flag is set (providing there is no more data queued for transmission) when the break character has been shifted out. A TC interrupt indicates that there is no transmission in progress. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted. When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL).TC is cleared automatically when data, preamble, or break is queued and ready to be sent. 18.5.3.1.3 RDRF Description The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register. A RDRF interrupt indicates that the received data has been transferred to the SCI data register and that the byte can now be read by the MCU. The RDRF interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL). 18.5.3.1.4 OR Description The OR interrupt is set when software fails to read the SCI data register before the receive shift register receives the next frame. The newly acquired data in the shift register will be lost in this case, but the data already in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL). MC912ZVL Family Reference Manual, Rev. 2.48 544 NXP Semiconductors Serial Communication Interface (S12SCIV6) 18.5.3.1.5 IDLE Description The IDLE interrupt is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1) appear on the receiver input. Once the IDLE is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL). 18.5.3.1.6 RXEDGIF Description The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1. 18.5.3.1.7 BERRIF Description The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single wire application like LIN was detected. Clear BERRIF by writing a “1” to the SCIASR1 SCI alternative status register 1. This flag is also cleared if the bit error detect feature is disabled. 18.5.3.1.8 BKDIF Description The BKDIF interrupt is set when a break signal was received. Clear BKDIF by writing a “1” to the SCIASR1 SCI alternative status register 1. This flag is also cleared if break detect feature is disabled. 18.5.4 Recovery from Wait Mode The SCI interrupt request can be used to bring the CPU out of wait mode. 18.5.5 Recovery from Stop Mode An active edge on the receive input can be used to bring the CPU out of stop mode. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 545 Serial Communication Interface (S12SCIV6) MC912ZVL Family Reference Manual, Rev. 2.48 546 NXP Semiconductors Chapter 19 Serial Peripheral Interface (S12SPIV5) Table 19-1. Revision History Revision Number Revision Date Sections Affected V05.00 24 Mar 2005 19.3.2/19-551 19.1 Description of Changes - Added 16-bit transfer width feature. Introduction The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven. 19.1.1 19.1.2 Glossary of Terms SPI Serial Peripheral Interface SS Slave Select SCK Serial Clock MOSI Master Output, Slave Input MISO Master Input, Slave Output MOMI Master Output, Master Input SISO Slave Input, Slave Output Features The S12ZDBG includes these distinctive features: • Master mode and slave mode • Selectable 8 or 16-bit transfer width • Bidirectional mode • Slave select output • Mode fault error flag with CPU interrupt capability • Double-buffered data register • Serial clock with programmable polarity and phase • Control of SPI operation during wait mode 19.1.3 Modes of Operation The SPI functions in three modes: run, wait, and stop. MC9S12ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 547 Serial Peripheral Interface (S12SPIV5) • • • Run mode This is the basic mode of operation. Wait mode SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in run mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock generation turned off. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of data continues, so that the slave stays synchronized to the master. Stop mode The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of data continues, so that the slave stays synchronized to the master. For a detailed description of operating modes, please refer to Section 19.4.7, “Low Power Mode Options”. 19.1.4 Block Diagram Figure 19-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic. MC912ZVL Family Reference Manual, Rev. 2.48 548 NXP Semiconductors Serial Peripheral Interface (S12SPIV5) SPI 2 SPI Control Register 1 BIDIROE 2 SPI Control Register 2 SPC0 SPI Status Register SPIF MODF SPTEF Interrupt Control SPI Interrupt Request Baud Rate Generator Slave Control CPOL CPHA Phase + SCK In Slave Baud Rate Polarity Control Master Baud Rate Phase + SCK Out Polarity Control Master Control Counter Bus Clock Prescaler Clock Select SPPR 3 SPR MOSI MISO Port Control Logic SCK SS Baud Rate 3 Shift Clock Sample Clock Shifter SPI Baud Rate Register Data In LSBFE=1 LSBFE=0 MSB SPI Data Register LSBFE=1 LSBFE=0 LSBFE=0 LSB LSBFE=1 Data Out Figure 19-1. SPI Block Diagram 19.2 External Signal Description This section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. The S12ZDBG module has a total of four external pins. 19.2.1 MOSI — Master Out/Slave In Pin This pin is used to transmit data out of the SPI module when it is configured as a master and receive data when it is configured as slave. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 549 Serial Peripheral Interface (S12SPIV5) 19.2.2 MISO — Master In/Slave Out Pin This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master. 19.2.3 SS — Slave Select Pin This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place when it is configured as a master and it is used as an input to receive the slave select signal when the SPI is configured as slave. 19.2.4 SCK — Serial Clock Pin In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock. 19.3 Memory Map and Register Definition This section provides a detailed description of address space and registers used by the SPI. 19.3.1 Module Memory Map The memory map for the S12ZDBG is given in Figure 19-2. The address listed for each register is the sum of a base address and an address offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have no effect. Register Name Bit 7 6 5 4 3 2 1 Bit 0 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE MODFEN BIDIROE SPISWAI SPC0 SPR2 SPR1 SPR0 0x0000 SPICR1 R W 0x0001 SPICR2 R W 0 0x0002 SPIBR R W 0 0x0003 SPISR R W 0x0004 SPIDRH XFRW 0 0 0 SPPR2 SPPR1 SPPR0 SPIF 0 SPTEF MODF 0 0 0 0 R W R15 T15 R14 T14 R13 T13 R12 T12 R11 T11 R10 T10 R9 T9 R8 T8 0x0005 SPIDRL R W R7 T7 R6 T6 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 0x0006 Reserved R W = Unimplemented or Reserved Figure 19-2. SPI Register Summary MC912ZVL Family Reference Manual, Rev. 2.48 550 NXP Semiconductors Serial Peripheral Interface (S12SPIV5) Register Name 0x0007 Reserved Bit 7 6 5 4 3 2 1 Bit 0 R W = Unimplemented or Reserved Figure 19-2. SPI Register Summary 19.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. 19.3.2.1 SPI Control Register 1 (SPICR1) Module Base +0x0000 R W Reset 7 6 5 4 3 2 1 0 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0 0 0 0 0 1 0 0 Figure 19-3. SPI Control Register 1 (SPICR1) Read: Anytime Write: Anytime Table 19-2. SPICR1 Field Descriptions Field Description 7 SPIE SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set. 0 SPI interrupts disabled. 1 SPI interrupts enabled. 6 SPE SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset. 0 SPI disabled (lower power consumption). 1 SPI enabled, port pins are dedicated to SPI functions. 5 SPTIE SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set. 0 SPTEF interrupt disabled. 1 SPTEF interrupt enabled. 4 MSTR SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode. Switching the SPI from master to slave or vice versa forces the SPI system into idle state. 0 SPI is in slave mode. 1 SPI is in master mode. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 551 Serial Peripheral Interface (S12SPIV5) Table 19-2. SPICR1 Field Descriptions (continued) Field Description 3 CPOL SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Active-high clocks selected. In idle state SCK is low. 1 Active-low clocks selected. In idle state SCK is high. 2 CPHA SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock. 1 Sampling of data occurs at even edges (2,4,6,...) of the SCK clock. 1 SSOE Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by asserting the SSOE as shown in Table 19-3. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 LSBFE LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Data is transferred most significant bit first. 1 Data is transferred least significant bit first. Table 19-3. SS Input / Output Selection MODFEN 19.3.2.2 SSOE Master Mode Slave Mode 0 0 SS not used by SPI SS input 0 1 SS not used by SPI SS input 1 0 SS input with MODF feature SS input 1 1 SS is slave select output SS input SPI Control Register 2 (SPICR2) Module Base +0x0001 7 R 0 W Reset 0 6 XFRW 0 5 0 0 4 3 MODFEN BIDIROE 0 0 2 0 0 1 0 SPISWAI SPC0 0 0 = Unimplemented or Reserved Figure 19-4. SPI Control Register 2 (SPICR2) Read: Anytime Write: Anytime; writes to the reserved bits have no effect MC912ZVL Family Reference Manual, Rev. 2.48 552 NXP Semiconductors Serial Peripheral Interface (S12SPIV5) Table 19-4. SPICR2 Field Descriptions Field Description 6 XFRW Transfer Width — This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL becomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and SPIDRL form a 16-bit data register. Please refer to Section 19.3.2.4, “SPI Status Register (SPISR) for information about transmit/receive data handling and the interrupt flag clearing mechanism. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 8-bit Transfer Width (n = 8)1 1 16-bit Transfer Width (n = 16)1 4 MODFEN Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin configuration, refer to Table 19-3. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 SS port pin is not used by the SPI. 1 SS port pin with MODF feature. 3 BIDIROE Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0 set, a change of this bit will abort a transmission in progress and force the SPI into idle state. 0 Output buffer disabled. 1 Output buffer enabled. 1 SPISWAI SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode. 0 SPI clock operates normally in wait mode. 1 Stop SPI clock generation when in wait mode. 0 SPC0 1 Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in Table 19-5. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. n is used later in this document as a placeholder for the selected transfer width. Table 19-5. Bidirectional Pin Configurations Pin Mode SPC0 BIDIROE MISO MOSI Master Mode of Operation Normal 0 X Master In Master Out Bidirectional 1 0 MISO not used by SPI Master In 1 Master I/O Slave Mode of Operation Normal 0 X Slave Out Slave In Bidirectional 1 0 Slave In MOSI not used by SPI 1 Slave I/O MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 553 Serial Peripheral Interface (S12SPIV5) 19.3.2.3 SPI Baud Rate Register (SPIBR) Module Base +0x0002 7 R 0 W Reset 0 6 5 4 3 SPPR2 SPPR1 SPPR0 0 0 0 0 2 1 0 SPR2 SPR1 SPR0 0 0 0 0 = Unimplemented or Reserved Figure 19-5. SPI Baud Rate Register (SPIBR) Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 19-6. SPIBR Field Descriptions Field Description 6–4 SPPR[2:0] SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in Table 19-7. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state. 2–0 SPR[2:0] SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in Table 19-7. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state. The baud rate divisor equation is as follows: BaudRateDivisor = (SPPR + 1)  2(SPR + 1) Eqn. 19-1 The baud rate can be calculated with the following equation: Baud Rate = BusClock / BaudRateDivisor Eqn. 19-2 NOTE For maximum allowed baud rates, please refer to the SPI Electrical Specification in the Electricals chapter of this data sheet. Table 19-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 1 of 3) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 0 0 0 0 0 0 2 12.5 Mbit/s 0 0 0 0 0 1 4 6.25 Mbit/s 0 0 0 0 1 0 8 3.125 Mbit/s 0 0 0 0 1 1 16 1.5625 Mbit/s 0 0 0 1 0 0 32 781.25 kbit/s 0 0 0 1 0 1 64 390.63 kbit/s 0 0 0 1 1 0 128 195.31 kbit/s 0 0 0 1 1 1 256 97.66 kbit/s 0 0 1 0 0 0 4 6.25 Mbit/s MC912ZVL Family Reference Manual, Rev. 2.48 554 NXP Semiconductors Serial Peripheral Interface (S12SPIV5) Table 19-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 2 of 3) SPPR2 SPR0 Baud Rate Divisor SPPR1 SPPR0 SPR2 SPR1 Baud Rate 0 0 1 0 0 1 8 3.125 Mbit/s 0 0 1 0 1 0 16 1.5625 Mbit/s 0 0 1 0 1 1 32 781.25 kbit/s 0 0 1 1 0 0 64 390.63 kbit/s 0 0 1 1 0 1 128 195.31 kbit/s 0 0 1 1 1 0 256 97.66 kbit/s 0 0 1 1 1 1 512 48.83 kbit/s 0 1 0 0 0 0 6 4.16667 Mbit/s 0 1 0 0 0 1 12 2.08333 Mbit/s 0 1 0 0 1 0 24 1.04167 Mbit/s 0 1 0 0 1 1 48 520.83 kbit/s 0 1 0 1 0 0 96 260.42 kbit/s 0 1 0 1 0 1 192 130.21 kbit/s 0 1 0 1 1 0 384 65.10 kbit/s 0 1 0 1 1 1 768 32.55 kbit/s 0 1 1 0 0 0 8 3.125 Mbit/s 0 1 1 0 0 1 16 1.5625 Mbit/s 0 1 1 0 1 0 32 781.25 kbit/s 0 1 1 0 1 1 64 390.63 kbit/s 0 1 1 1 0 0 128 195.31 kbit/s 0 1 1 1 0 1 256 97.66 kbit/s 0 1 1 1 1 0 512 48.83 kbit/s 0 1 1 1 1 1 1024 24.41 kbit/s 1 0 0 0 0 0 10 2.5 Mbit/s 1 0 0 0 0 1 20 1.25 Mbit/s 1 0 0 0 1 0 40 625 kbit/s 1 0 0 0 1 1 80 312.5 kbit/s 1 0 0 1 0 0 160 156.25 kbit/s 1 0 0 1 0 1 320 78.13 kbit/s 1 0 0 1 1 0 640 39.06 kbit/s 1 0 0 1 1 1 1280 19.53 kbit/s 1 0 1 0 0 0 12 2.08333 Mbit/s 1 0 1 0 0 1 24 1.04167 Mbit/s 1 0 1 0 1 0 48 520.83 kbit/s 1 0 1 0 1 1 96 260.42 kbit/s 1 0 1 1 0 0 192 130.21 kbit/s 1 0 1 1 0 1 384 65.10 kbit/s 1 0 1 1 1 0 768 32.55 kbit/s 1 0 1 1 1 1 1536 16.28 kbit/s 1 1 0 0 0 0 14 1.78571 Mbit/s 1 1 0 0 0 1 28 892.86 kbit/s 1 1 0 0 1 0 56 446.43 kbit/s MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 555 Serial Peripheral Interface (S12SPIV5) Table 19-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 3 of 3) SPPR2 SPPR1 1 1 1 1 1 1 1 1 1 1 Baud Rate Divisor Baud Rate 1 112 223.21 kbit/s 0 224 111.61 kbit/s 0 1 448 55.80 kbit/s 1 0 896 27.90 kbit/s 1 1 1792 13.95 kbit/s 0 0 16 1.5625 Mbit/s 0 1 32 781.25 kbit/s 1 0 64 390.63 kbit/s 0 1 1 128 195.31 kbit/s 1 0 0 256 97.66 kbit/s 1 1 0 1 512 48.83 kbit/s 1 1 1 0 1024 24.41 kbit/s 1 1 1 1 2048 12.21 kbit/s SPR2 SPR1 SPR0 0 0 1 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 19.3.2.4 SPPR0 SPI Status Register (SPISR) Module Base +0x0003 R 7 6 5 4 3 2 1 0 SPIF 0 SPTEF MODF 0 0 0 0 0 0 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 19-6. SPI Status Register (SPISR) Read: Anytime Write: Has no effect Table 19-8. SPISR Field Descriptions Field 7 SPIF Description SPIF Interrupt Flag — This bit is set after received data has been transferred into the SPI data register. For information about clearing SPIF Flag, please refer to Table 19-9. 0 Transfer not yet complete. 1 New data copied to SPIDR. MC912ZVL Family Reference Manual, Rev. 2.48 556 NXP Semiconductors Serial Peripheral Interface (S12SPIV5) Table 19-8. SPISR Field Descriptions (continued) Field Description 5 SPTEF SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. For information about clearing this bit and placing data into the transmit data register, please refer to Table 19-10. 0 SPI data register not empty. 1 SPI data register empty. 4 MODF Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in Section 19.3.2.2, “SPI Control Register 2 (SPICR2)”. The flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to the SPI control register 1. 0 Mode fault has not occurred. 1 Mode fault has occurred. Table 19-9. SPIF Interrupt Flag Clearing Sequence XFRW Bit SPIF Interrupt Flag Clearing Sequence 0 Read SPISR with SPIF == 1 1 Read SPISR with SPIF == 1 then Read SPIDRL Byte Read SPIDRL 1 or then Byte Read SPIDRH 2 Byte Read SPIDRL or Word Read (SPIDRH:SPIDRL) 1 2 Data in SPIDRH is lost in this case. SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read of SPIDRL after reading SPISR with SPIF == 1. Table 19-10. SPTEF Interrupt Flag Clearing Sequence XFRW Bit SPTEF Interrupt Flag Clearing Sequence 0 Read SPISR with SPTEF == 1 then 1 Read SPISR with SPTEF == 1 Write to SPIDRL 1 Byte Write to SPIDRL 12 or then Byte Write to SPIDRH 13 Byte Write to SPIDRL 1 or Word Write to (SPIDRH:SPIDRL) 1 1 Any write to SPIDRH or SPIDRL with SPTEF == 0 is effectively ignored. Data in SPIDRH is undefined in this case. 3 SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by writing to SPIDRL after reading SPISR with SPTEF == 1. 2 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 557 Serial Peripheral Interface (S12SPIV5) 19.3.2.5 SPI Data Register (SPIDR = SPIDRH:SPIDRL) Module Base +0x0004 7 6 5 4 3 2 1 0 R R15 R14 R13 R12 R11 R10 R9 R8 W T15 T14 T13 T12 T11 T10 T9 T8 0 0 0 0 0 0 0 0 Reset Figure 19-7. SPI Data Register High (SPIDRH) Module Base +0x0005 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Reset Figure 19-8. SPI Data Register Low (SPIDRL) Read: Anytime; read data only valid when SPIF is set Write: Anytime The SPI data register is both the input and output register for SPI data. A write to this register allows data to be queued and transmitted. For an SPI configured as a master, queued data is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new data. Received data in the SPIDR is valid when SPIF is set. If SPIF is cleared and data has been received, the received data is transferred from the receive shift register to the SPIDR and SPIF is set. If SPIF is set and not serviced, and a second data value has been received, the second received data is kept as valid data in the receive shift register until the start of another transmission. The data in the SPIDR does not change. If SPIF is set and valid data is in the receive shift register, and SPIF is serviced before the start of a third transmission, the data in the receive shift register is transferred into the SPIDR and SPIF remains set (see Figure 19-9). If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of a third transmission, the data in the receive shift register has become invalid and is not transferred into the SPIDR (see Figure 19-10). MC912ZVL Family Reference Manual, Rev. 2.48 558 NXP Semiconductors Serial Peripheral Interface (S12SPIV5) Data A Received Data B Received Data C Received SPIF Serviced Receive Shift Register Data B Data A Data C SPIF SPI Data Register Data B Data A = Unspecified Data C = Reception in progress Figure 19-9. Reception with SPIF serviced in Time Data A Received Data B Received Data C Received Data B Lost SPIF Serviced Receive Shift Register Data B Data A Data C SPIF SPI Data Register Data A = Unspecified Data C = Reception in progress Figure 19-10. Reception with SPIF serviced too late 19.4 Functional Description The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or SPI operation can be interrupt driven. The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set, the four associated SPI port pins are dedicated to the SPI function as: • Slave select (SS) • Serial clock (SCK) • Master out/slave in (MOSI) • Master in/slave out (MISO) MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 559 Serial Peripheral Interface (S12SPIV5) The main element of the SPI system is the SPI data register. The n-bit1 data register in the master and the n-bit1 data register in the slave are linked by the MOSI and MISO pins to form a distributed 2n-bit1 register. When a data transfer operation is performed, this 2n-bit1 register is serially shifted n1 bit positions by the S-clock from the master, so data is exchanged between the master and the slave. Data written to the master SPI data register becomes the output data for the slave, and data read from the master SPI data register after a transfer operation is the input data from the slave. A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register. When a transfer is complete and SPIF is cleared, received data is moved into the receive data register. This data register acts as the SPI receive data register for reads and as the SPI transmit data register for writes. A common SPI data register address is shared for reading data from the read data buffer and for writing data to the transmit data register. The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1 (SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (see Section 19.4.3, “Transmission Formats”). The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI control register1 is set, master mode is selected, when the MSTR bit is clear, slave mode is selected. NOTE A change of CPOL or MSTR bit while there is a received byte pending in the receive shift register will destroy the received byte and must be avoided. 19.4.1 Master Mode The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI data register. If the shift register is empty, data immediately transfers to the shift register. Data begins shifting out on the MOSI pin under the control of the serial clock. • Serial clock The SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI baud rate register, control the baud rate generator and determine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCK pin, the baud rate generator of the master controls the shift register of the slave peripheral. • MOSI, MISO pin In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and BIDIROE control bits. • SS pin If MODFEN and SSOE are set, the SS pin is configured as slave select output. The SS output becomes low during each transmission and is high when the SPI is in idle state. 1. n depends on the selected transfer width, please refer to Section 19.3.2.2, “SPI Control Register 2 (SPICR2) MC912ZVL Family Reference Manual, Rev. 2.48 560 NXP Semiconductors Serial Peripheral Interface (S12SPIV5) If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error. If the SS input becomes low this indicates a mode fault error where another master tries to drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state. This mode fault error also sets the mode fault (MODF) flag in the SPI status register (SPISR). If the SPI interrupt enable bit (SPIE) is set when the MODF flag becomes set, then an SPI interrupt sequence is also requested. When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI control register 1 (see Section 19.4.3, “Transmission Formats”). NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, XFRW, MODFEN, SPC0, or BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in master mode will abort a transmission in progress and force the SPI into idle state. The remote slave cannot detect this, therefore the master must ensure that the remote slave is returned to idle state. 19.4.2 Slave Mode The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear. • Serial clock In slave mode, SCK is the SPI clock input from the master. • MISO, MOSI pin In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI control register 2. • SS pin The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is forced into idle state. The SS input also controls the serial data output pin, if SS is high (not selected), the serial data output pin is high impedance, and, if SS is low, the first bit in the SPI data register is driven out of the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is ignored and no internal shifting of the SPI shift register occurs. Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 561 Serial Peripheral Interface (S12SPIV5) NOTE When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line. As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the nth1 shift, the transfer is considered complete and the received data is transferred into the SPI data register. To indicate transfer is complete, the SPIF flag in the SPI status register is set. NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or BIDIROE with SPC0 set in slave mode will corrupt a transmission in progress and must be avoided. 19.4.3 Transmission Formats During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select line can be used to indicate multiple-master bus contention. MASTER SPI SLAVE SPI SHIFT REGISTER BAUD RATE GENERATOR MISO MISO MOSI MOSI SCK SCK SS VDD SHIFT REGISTER SS Figure 19-11. Master/Slave Transfer Block Diagram 1. n depends on the selected transfer width, please refer to Section 19.3.2.2, “SPI Control Register 2 (SPICR2) MC912ZVL Family Reference Manual, Rev. 2.48 562 NXP Semiconductors Serial Peripheral Interface (S12SPIV5) 19.4.3.1 Clock Phase and Polarity Controls Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity. The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats. Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. 19.4.3.2 CPHA = 0 Transfer Format The first edge on the SCK line is used to clock the first data bit of the slave into the master and the first data bit of the master into the slave. In some peripherals, the first bit of the slave’s data is available at the slave’s data out pin as soon as the slave is selected. In this format, the first SCK edge is issued a half cycle after SS has become low. A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the shift register, depending on LSBFE bit. After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered edges and shifted on even numbered edges. Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After 2n1 (last) SCK edges: • Data that was previously in the master SPI data register should now be in the slave data register and the data that was in the slave data register should be in the master. • The SPIF flag in the SPI status register is set, indicating that the transfer is complete. Figure 19-12 is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for CPOL = 0 and CPOL = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. 1. n depends on the selected transfer width, please refer to Section 19.3.2.2, “SPI Control Register 2 (SPICR2) MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 563 Serial Peripheral Interface (S12SPIV5) End of Idle State Begin 1 SCK Edge Number 2 3 4 5 6 7 8 Begin of Idle State End Transfer 9 10 11 12 13 14 15 16 Bit 1 Bit 6 LSB Minimum 1/2 SCK for tT, tl, tL MSB SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tT tL MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 tL = Minimum leading time before the first SCK edge tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time) tL, tT, and tI are guaranteed for the master mode and required for the slave mode. tI tL Figure 19-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0) MC912ZVL Family Reference Manual, Rev. 2.48 564 NXP Semiconductors Serial Peripheral Interface (S12SPIV5) End of Idle State SCK Edge Number Begin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Begin of Idle State End Transfer 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) MSB first (LSBFE = 0) LSB first (LSBFE = 1) tL tT tI tL MSB Bit 14Bit 13Bit 12Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Minimum 1/2 SCK LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10Bit 11 Bit 12Bit 13Bit 14 MSB for tT, tl, tL tL = Minimum leading time before the first SCK edge tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time) tL, tT, and tI are guaranteed for the master mode and required for the slave mode. Figure 19-13. SPI Clock Format 0 (CPHA = 0), with 16-Bit Transfer Width selected (XFRW = 1) In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the SPI data register is not transmitted; instead the last received data is transmitted. If the SS line is deasserted for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the SPI data register is transmitted. In master mode, with slave select output enabled the SS line is always deasserted and reasserted between successive transfers for at least minimum idle time. 19.4.3.3 CPHA = 1 Transfer Format Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, the second edge clocks data into the system. In this format, the first SCK edge is issued by setting the CPHA bit at the beginning of the n1-cycle transfer operation. The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first edge commands the slave to transfer its first data bit to the serial data input pin of the master. A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. 1. n depends on the selected transfer width, please refer to Section 19.3.2.2, “SPI Control Register 2 (SPICR2) MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 565 Serial Peripheral Interface (S12SPIV5) When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of n1 edges on the SCK line with data being latched on even numbered edges and shifting taking place on odd numbered edges. Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After 2n1 SCK edges: • Data that was previously in the SPI data register of the master is now in the data register of the slave, and data that was in the data register of the slave is in the master. • The SPIF flag bit in SPISR is set indicating that the transfer is complete. Figure 19-14 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. End of Idle State Begin SCK Edge Number 1 2 3 4 End Transfer 5 6 7 8 9 10 11 12 13 14 Begin of Idle State 15 16 SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tT tL MSB first (LSBFE = 0): LSB first (LSBFE = 1): MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 tI tL LSB Minimum 1/2 SCK for tT, tl, tL MSB tL = Minimum leading time before the first SCK edge, not required for back-to-back transfers tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers Figure 19-14. SPI Clock Format 1 (CPHA = 1), with 8-Bit Transfer Width selected (XFRW = 0) MC912ZVL Family Reference Manual, Rev. 2.48 566 NXP Semiconductors Serial Peripheral Interface (S12SPIV5) End of Idle State SCK Edge Number Begin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Begin of Idle State End Transfer 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tT tI tL Minimum 1/2 SCK for tT, tl, tL tL MSB first (LSBFE = 0) LSB first (LSBFE = 1) MSB Bit 14Bit 13Bit 12Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10Bit 11 Bit 12Bit 13Bit 14 MSB tL = Minimum leading time before the first SCK edge, not required for back-to-back transfers tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers Figure 19-15. SPI Clock Format 1 (CPHA = 1), with 16-Bit Transfer Width selected (XFRW = 1) The SS line can remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data line. • Back-to-back transfers in master mode In master mode, if a transmission has completed and new data is available in the SPI data register, this data is sent out immediately without a trailing and minimum idle time. The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one half SCK cycle after the last SCK edge. 19.4.4 SPI Baud Rate Generation Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate. The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2– SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Equation 19-3. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 567 Serial Peripheral Interface (S12SPIV5) BaudRateDivisor = (SPPR + 1)  2(SPR + 1) Eqn. 19-3 When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010, the module clock divisor becomes 8, etc. When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 19-7 for baud rate calculations for all bit conditions, based on a 25 MHz bus clock. The two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. The baud rate generator is activated only when the SPI is in master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease IDD current. NOTE For maximum allowed baud rates, please refer to the SPI Electrical Specification in the Electricals chapter of this data sheet. 19.4.5 19.4.5.1 Special Features SS Output The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device. The SS output is available only in master mode during normal SPI operation by asserting SSOE and MODFEN bit as shown in Table 19-3. The mode fault feature is disabled while SS output is enabled. NOTE Care must be taken when using the SS output feature in a multimaster system because the mode fault feature is not available for detecting system errors between masters. 19.4.5.2 Bidirectional Mode (MOMI or SISO) The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see Table 19-11). In this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI. MC912ZVL Family Reference Manual, Rev. 2.48 568 NXP Semiconductors Serial Peripheral Interface (S12SPIV5) Table 19-11. Normal Mode and Bidirectional Mode When SPE = 1 Master Mode MSTR = 1 Serial Out Normal Mode SPC0 = 0 MOSI MOSI Serial In SPI SPI Serial In Bidirectional Mode SPC0 = 1 Slave Mode MSTR = 0 MISO Serial Out SPI MOMI BIDIROE Serial In Serial Out MISO Serial In SPI BIDIROE Serial Out SISO The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output, serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift register. • The SCK is output for the master mode and input for the slave mode. • The SS is the input or output for the master mode, and it is always the input for the slave mode. • The bidirectional mode does not affect SCK and SS functions. NOTE In bidirectional master mode, with mode fault enabled, both data pins MISO and MOSI can be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode and MISO is not used by the SPI. If a mode fault occurs, the SPI is automatically switched to slave mode. In this case MISO becomes occupied by the SPI and MOSI is not used. This must be considered, if the MISO pin is used for another purpose. 19.4.6 Error Conditions The SPI has one error condition: • Mode fault error 19.4.6.1 Mode Fault Error If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation, the MODF bit in the SPI status register is set automatically, provided the MODFEN bit is set. In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 569 Serial Peripheral Interface (S12SPIV5) the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur in slave mode. If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So SCK, MISO, and MOSI pins are forced to be high impedance inputs to avoid any possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is forced into idle state. If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for SPI system configured in slave mode. The mode fault flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to SPI control register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again. NOTE If a mode fault error occurs and a received data byte is pending in the receive shift register, this data byte will be lost. 19.4.7 19.4.7.1 Low Power Mode Options SPI in Run Mode In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are disabled. 19.4.7.2 SPI in Wait Mode SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2. • If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode • If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode. – If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry. The transmission and reception resumes when the SPI exits wait mode. – If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SCK continues to be driven from the master. This keeps the slave synchronized to the master and the SCK. If the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the operation mode at the start of wait mode (i.e., if the slave is currently sending its SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). MC912ZVL Family Reference Manual, Rev. 2.48 570 NXP Semiconductors Serial Peripheral Interface (S12SPIV5) NOTE Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e., a SPIF interrupt will not be generated until exiting stop or wait mode). Also, the byte from the shift register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode. In slave mode, a received byte pending in the receive shift register will be lost when entering wait or stop mode. An SPIF flag and SPIDR copy is generated only if wait mode is entered or exited during a tranmission. If the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a SPIF nor a SPIDR copy will occur. 19.4.7.3 SPI in Stop Mode Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with the master. The stop mode is not dependent on the SPISWAI bit. 19.4.7.4 Reset The reset values of registers and signals are described in Section 19.3, “Memory Map and Register Definition”, which details the registers and their bit fields. • If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the data last received from the master before the reset. • Reading from the SPIDR after reset will always read zeros. 19.4.7.5 Interrupts The S12ZDBG only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following is a description of how the S12ZDBG makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent. The interrupt flags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request. 19.4.7.5.1 MODF MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see Table 19-3). After MODF is set, the current transfer is aborted and the following bit is changed: • MSTR = 0, The master bit in SPICR1 resets. The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing process which is described in Section 19.3.2.4, “SPI Status Register (SPISR)”. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 571 Serial Peripheral Interface (S12SPIV5) 19.4.7.5.2 SPIF SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does not clear until it is serviced. SPIF has an automatic clearing process, which is described in Section 19.3.2.4, “SPI Status Register (SPISR)”. 19.4.7.5.3 SPTEF SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process, which is described in Section 19.3.2.4, “SPI Status Register (SPISR)”. MC912ZVL Family Reference Manual, Rev. 2.48 572 NXP Semiconductors Chapter 20 Inter-Integrated Circuit (IICV3) Table 20-1. Revision History Revision Number Sections Affected Revision Date Description of Changes V01.03 28 Jul 2006 20.7.1.7/20-596 - Update flow-chart of interrupt routine for 10-bit address V01.04 17 Nov 2006 20.3.1.2/20-576 - Revise Table1-5 V01.05 14 Aug 2007 20.3.1.1/20-576 - Backward compatible for IBAD bit name 20.1 Introduction The inter-IC bus (IIC) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of connections between devices, and eliminates the need for an address decoder. This bus is suitable for applications requiring occasional communications over a short distance between a number of devices. It also provides flexibility, allowing additional devices to be connected to the bus for further expansion and system development. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF. 20.1.1 Features The IIC module has the following key features: • Compatible with I2C bus standard • Multi-master operation • Software programmable for one of 256 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • Start and stop signal generation/detection • Repeated start signal generation MC9S12ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 573 Inter-Integrated Circuit (IICV3) • • • • Acknowledge bit generation/detection Bus busy detection General Call Address detection Compliant to ten-bit address 20.1.2 Modes of Operation The IIC functions the same in normal, special, and emulation modes. It has two low power modes: wait and stop modes. 20.1.3 Block Diagram The block diagram of the IIC module is shown in Figure 20-1. IIC Registers Start Stop Arbitration Control Clock Control In/Out Data Shift Register Interrupt bus_clock SCL SDA Address Compare Figure 20-1. IIC Block Diagram 20.2 External Signal Description The IICV3 module has two external pins. 20.2.1 IIC_SCL — Serial Clock Line Pin This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification. MC912ZVL Family Reference Manual, Rev. 2.48 574 NXP Semiconductors Inter-Integrated Circuit (IICV3) 20.2.2 IIC_SDA — Serial Data Line Pin This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification. 20.3 Memory Map and Register Definition This section provides a detailed description of all memory and registers for the IIC module. 20.3.1 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Register Name 0x0000 IBAD 0x0001 IBFD 0x0002 IBCR R W R W R W 0x0003 IBSR W 0x0004 IBDR W 0x0005 IBCR2 R R R W Bit 7 6 5 4 3 2 1 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBEN IBIE MS/SL Tx/Rx TXAK 0 0 TCF IAAS IBB D7 D6 D5 GCEN ADTYPE 0 RSTA Bit 0 0 IBC0 IBSWAI 0 SRW D4 D3 D2 D1 D0 0 0 ADR10 ADR9 ADR8 IBAL IBIF RXAK = Unimplemented or Reserved Figure 20-2. IIC Register Summary MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 575 Inter-Integrated Circuit (IICV3) 20.3.1.1 IIC Address Register (IBAD) Module Base +0x0000 R W Reset 7 6 5 4 3 2 1 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-3. IIC Bus Address Register (IBAD) Read and write anytime This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not the address sent on the bus during the address transfer. Table 20-2. IBAD Field Descriptions Field Description 7:1 ADR[7:1] Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default mode of IIC bus is slave mode for an address match on the bus. 0 Reserved Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0. 20.3.1.2 IIC Frequency Divider Register (IBFD) Module Base + 0x0001 R W Reset 7 6 5 4 3 2 1 0 IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-4. IIC Bus Frequency Divider Register (IBFD) Read and write anytime Table 20-3. IBFD Field Descriptions Field Description 7:0 IBC[7:0] I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown in Table 20-4. MC912ZVL Family Reference Manual, Rev. 2.48 576 NXP Semiconductors Inter-Integrated Circuit (IICV3) Table 20-4. I-Bus Tap and Prescale Values IBC2-0 (bin) SCL Tap (clocks) SDA Tap (clocks) 000 5 1 001 6 1 010 7 2 011 8 2 100 9 3 101 10 3 110 12 4 111 15 4 Table 20-5. Prescale Divider Encoding IBC5-3 (bin) scl2start (clocks) scl2stop (clocks) scl2tap (clocks) tap2tap (clocks) 000 2 7 4 1 001 2 7 4 2 010 2 9 6 4 011 6 9 6 8 100 14 17 14 16 101 30 33 30 32 110 62 65 62 64 111 126 129 126 128 Table 20-6. Multiplier Factor IBC7-6 MUL 00 01 01 02 10 04 11 RESERVED The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown in the scl2tap column of Table 20-4, all subsequent tap points are separated by 2IBC5-3 as shown in the tap2tap column in Table 20-5. The SCL Tap is used to generated the SCL period and the SDA Tap is used to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time. IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the Table 20-6. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 577 Inter-Integrated Circuit (IICV3) SCL Divider SCL SDA Hold SDA SDA SCL Hold(stop) SCL Hold(start) SCL START condition STOP condition Figure 20-5. SCL Divider and SDA Hold The equation used to generate the divider values from the IBFD bits is: SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)} The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in Table 20-7. The equation used to generate the SDA Hold value from the IBFD bits is: SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3} The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is: SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap] SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap] Table 20-7. IIC Divider and Hold Values (Sheet 1 of 6) IBC[7:0] (hex) SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop) MUL=1 MC912ZVL Family Reference Manual, Rev. 2.48 578 NXP Semiconductors Inter-Integrated Circuit (IICV3) Table 20-7. IIC Divider and Hold Values (Sheet 2 of 6) IBC[7:0] (hex) SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 20/22 22/24 24/26 26/28 28/30 30/32 34/36 40/42 28/32 32/36 36/40 40/44 44/48 48/52 56/60 68/72 48 56 64 72 80 88 104 128 80 96 112 128 144 160 192 240 160 192 224 256 288 320 384 480 320 384 448 512 576 7 7 8 8 9 9 10 10 7 7 9 9 11 11 13 13 9 9 13 13 17 17 21 21 9 9 17 17 25 25 33 33 17 17 33 33 49 49 65 65 33 33 65 65 97 6 7 8 9 10 11 13 16 10 12 14 16 18 20 24 30 18 22 26 30 34 38 46 58 38 46 54 62 70 78 94 118 78 94 110 126 142 158 190 238 158 190 222 254 286 11 12 13 14 15 16 18 21 15 17 19 21 23 25 29 35 25 29 33 37 41 45 53 65 41 49 57 65 73 81 97 121 81 97 113 129 145 161 193 241 161 193 225 257 289 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 579 Inter-Integrated Circuit (IICV3) Table 20-7. IIC Divider and Hold Values (Sheet 3 of 6) IBC[7:0] (hex) SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop) 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 97 129 129 65 65 129 129 193 193 257 257 129 129 257 257 385 385 513 513 318 382 478 318 382 446 510 574 638 766 958 638 766 894 1022 1150 1278 1534 1918 321 385 481 321 385 449 513 577 641 769 961 641 769 897 1025 1153 1281 1537 1921 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 40 44 48 52 56 60 68 80 56 64 72 80 88 96 112 136 96 112 128 144 160 176 208 256 160 14 14 16 16 18 18 20 20 14 14 18 18 22 22 26 26 18 18 26 26 34 34 42 42 18 12 14 16 18 20 22 26 32 20 24 28 32 36 40 48 60 36 44 52 60 68 76 92 116 76 22 24 26 28 30 32 36 42 30 34 38 42 46 50 58 70 50 58 66 74 82 90 106 130 82 MUL=2 MC912ZVL Family Reference Manual, Rev. 2.48 580 NXP Semiconductors Inter-Integrated Circuit (IICV3) Table 20-7. IIC Divider and Hold Values (Sheet 4 of 6) IBC[7:0] (hex) SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop) 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 192 224 256 288 320 384 480 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 2560 3072 3584 4096 4608 5120 6144 7680 18 34 34 50 50 66 66 34 34 66 66 98 98 130 130 66 66 130 130 194 194 258 258 130 130 258 258 386 386 514 514 258 258 514 514 770 770 1026 1026 92 108 124 140 156 188 236 156 188 220 252 284 316 380 476 316 380 444 508 572 636 764 956 636 764 892 1020 1148 1276 1532 1916 1276 1532 1788 2044 2300 2556 3068 3836 98 114 130 146 162 194 242 162 194 226 258 290 322 386 482 322 386 450 514 578 642 770 962 642 770 898 1026 1154 1282 1538 1922 1282 1538 1794 2050 2306 2562 3074 3842 80 81 82 83 84 72 80 88 96 104 28 28 32 32 36 24 28 32 36 40 44 48 52 56 60 MUL=4 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 581 Inter-Integrated Circuit (IICV3) Table 20-7. IIC Divider and Hold Values (Sheet 5 of 6) IBC[7:0] (hex) SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop) 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 112 128 152 112 128 144 160 176 192 224 272 192 224 256 288 320 352 416 512 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 2560 3072 36 40 40 28 28 36 36 44 44 52 52 36 36 52 52 68 68 84 84 36 36 68 68 100 100 132 132 68 68 132 132 196 196 260 260 132 132 260 260 388 388 516 516 260 260 44 52 64 40 48 56 64 72 80 96 120 72 88 104 120 136 152 184 232 152 184 216 248 280 312 376 472 312 376 440 504 568 632 760 952 632 760 888 1016 1144 1272 1528 1912 1272 1528 64 72 84 60 68 76 84 92 100 116 140 100 116 132 148 164 180 212 260 164 196 228 260 292 324 388 484 324 388 452 516 580 644 772 964 644 772 900 1028 1156 1284 1540 1924 1284 1540 MC912ZVL Family Reference Manual, Rev. 2.48 582 NXP Semiconductors Inter-Integrated Circuit (IICV3) Table 20-7. IIC Divider and Hold Values (Sheet 6 of 6) IBC[7:0] (hex) SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop) B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF 3584 4096 4608 5120 6144 7680 5120 6144 7168 8192 9216 10240 12288 15360 516 516 772 772 1028 1028 516 516 1028 1028 1540 1540 2052 2052 1784 2040 2296 2552 3064 3832 2552 3064 3576 4088 4600 5112 6136 7672 1796 2052 2308 2564 3076 3844 2564 3076 3588 4100 4612 5124 6148 7684 Note:Since the bus frequency is speeding up,the SCL Divider could be expanded by it.Therefore,in the table,when IBC[7:0] is from $00 to $0F,the SCL Divider is revised by the format value1/value2.Value1 is the divider under the low frequency.Value2 is the divider under the high frequency.How to select the divider depends on the bus frequency.When IBC[7:0] is from $10 to $BF,the divider is not changed. 20.3.1.3 IIC Control Register (IBCR) Module Base + 0x0002 R W Reset 7 6 5 4 3 IBEN IBIE MS/SL Tx/Rx TXAK 0 0 0 0 0 2 1 0 0 RSTA 0 0 0 IBSWAI 0 = Unimplemented or Reserved Figure 20-6. IIC Bus Control Register (IBCR) Read and write anytime MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 583 Inter-Integrated Circuit (IICV3) Table 20-8. IBCR Field Descriptions Field Description 7 IBEN I-Bus Enable — This bit controls the software reset of the entire IIC bus module. 0 The module is reset and disabled. This is the power-on reset situation. When low the interface is held in reset but registers can be accessed 1 The IIC bus module is enabled.This bit must be set before any other IBCR bits have any effect If the IIC bus module is enabled in the middle of a byte transfer the interface behaves as follows: slave mode ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detected. Master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle may become corrupt. This would ultimately result in either the current bus master or the IIC bus module losing arbitration, after which bus operation would return to normal. 6 IBIE I-Bus Interrupt Enable 0 Interrupts from the IIC bus module are disabled. Note that this does not clear any currently pending interrupt condition 1 Interrupts from the IIC bus module are enabled. An IIC bus interrupt occurs provided the IBIF bit in the status register is also set. 5 MS/SL Master/Slave Mode Select Bit — Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START signal is generated on the bus, and the master mode is selected. When this bit is changed from 1 to 0, a STOP signal is generated and the operation mode changes from master to slave.A STOP signal should only be generated if the IBIF flag is set. MS/SL is cleared without generating a STOP signal when the master loses arbitration. 0 Slave Mode 1 Master Mode 4 Tx/Rx Transmit/Receive Mode Select Bit — This bit selects the direction of master and slave transfers. When addressed as a slave this bit should be set by software according to the SRW bit in the status register. In master mode this bit should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high. 0 Receive 1 Transmit 3 TXAK Transmit Acknowledge Enable — This bit specifies the value driven onto SDA during data acknowledge cycles for both master and slave receivers. The IIC module will always acknowledge address matches, provided it is enabled, regardless of the value of TXAK. Note that values written to this bit are only used when the IIC bus is a receiver, not a transmitter. 0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte data 1 No acknowledge signal response is sent (i.e., acknowledge bit = 1) 2 RSTA Repeat Start — Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration. 1 Generate repeat start cycle 1 Reserved — Bit 1 of the IBCR is reserved for future compatibility. This bit will always read 0. RESERVED 0 IBSWAI I Bus Interface Stop in Wait Mode 0 IIC bus module clock operates normally 1 Halt IIC bus module clock generation in wait mode Wait mode is entered via execution of a CPU WAI instruction. In the event that the IBSWAI bit is set, all clocks internal to the IIC will be stopped and any transmission currently in progress will halt.If the CPU were woken up by a source other than the IIC module, then clocks would restart and the IIC would resume MC912ZVL Family Reference Manual, Rev. 2.48 584 NXP Semiconductors Inter-Integrated Circuit (IICV3) from where was during the previous transmission. It is not possible for the IIC to wake up the CPU when its internal clocks are stopped. If it were the case that the IBSWAI bit was cleared when the WAI instruction was executed, the IIC internal clocks and interface would remain alive, continuing the operation which was currently underway. It is also possible to configure the IIC such that it will wake up the CPU via an interrupt at the conclusion of the current operation. See the discussion on the IBIF and IBIE bits in the IBSR and IBCR, respectively. 20.3.1.4 IIC Status Register (IBSR) Module Base + 0x0003 R 7 6 5 TCF IAAS IBB 1 0 0 W Reset 4 IBAL 0 3 2 0 SRW 0 0 1 IBIF 0 0 RXAK 0 = Unimplemented or Reserved Figure 20-7. IIC Bus Status Register (IBSR) This status register is read-only with exception of bit 1 (IBIF) and bit 4 (IBAL), which are software clearable. Table 20-9. IBSR Field Descriptions Field Description 7 TCF Data Transferring Bit — While one byte of data is being transferred, this bit is cleared. It is set by the falling edge of the 9th clock of a byte transfer. Note that this bit is only valid during or immediately following a transfer to the IIC module or from the IIC module. 0 Transfer in progress 1 Transfer complete 6 IAAS Addressed as a Slave Bit — When its own specific address (I-bus address register) is matched with the calling address or it receives the general call address with GCEN== 1,this bit is set.The CPU is interrupted provided the IBIE is set.Then the CPU needs to check the SRW bit and set its Tx/Rx mode accordingly.Writing to the I-bus control register clears this bit. 0 Not addressed 1 Addressed as a slave 5 IBB Bus Busy Bit 0 This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal is detected, IBB is cleared and the bus enters idle state. 1 Bus is busy 4 IBAL Arbitration Lost — The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost. Arbitration is lost in the following circumstances: 1.SDA sampled low when the master drives a high during an address or data transmit cycle. 2.SDA sampled low when the master drives a high during the acknowledge bit of a data receive cycle. 3.A start cycle is attempted when the bus is busy. 4.A repeated start cycle is requested in slave mode. 5.A stop condition is detected when the master did not request it. This bit must be cleared by software, by writing a one to it. A write of 0 has no effect on this bit. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 585 Inter-Integrated Circuit (IICV3) Table 20-9. IBSR Field Descriptions (continued) Field Description 3 Reserved — Bit 3 of IBSR is reserved for future use. A read operation on this bit will return 0. RESERVED 2 SRW Slave Read/Write — When IAAS is set this bit indicates the value of the R/W command bit of the calling address sent from the master This bit is only valid when the I-bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated. Checking this bit, the CPU can select slave transmit/receive mode according to the command of the master. 0 Slave receive, master writing to slave 1 Slave transmit, master reading from slave 1 IBIF I-Bus Interrupt — The IBIF bit is set when one of the following conditions occurs: — Arbitration lost (IBAL bit set) — Data transfer complete (TCF bit set) — Addressed as slave (IAAS bit set) It will cause a processor interrupt request if the IBIE bit is set. This bit must be cleared by software, writing a one to it. A write of 0 has no effect on this bit. 0 RXAK Received Acknowledge — The value of SDA during the acknowledge bit of a bus cycle. If the received acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. If RXAK is high, it means no acknowledge signal is detected at the 9th clock. 0 Acknowledge received 1 No acknowledge received 20.3.1.5 IIC Data I/O Register (IBDR) Module Base + 0x0004 R W Reset 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Figure 20-8. IIC Bus Data I/O Register (IBDR) In master transmit mode, when data is written to the IBDR a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates next byte data receiving. In slave mode, the same functions are available after an address match has occurred.Note that the Tx/Rx bit in the IBCR must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master receive is desired, then reading the IBDR will not initiate the receive. Reading the IBDR will return the last byte received while the IIC is configured in either master receive or slave receive modes. The IBDR does not reflect every byte that is transmitted on the IIC bus, nor can software verify that a byte has been written to the IBDR correctly by reading it back. In master transmit mode, the first byte of data written to IBDR following assertion of MS/SL is used for the address transfer and should com.prise of the calling address (in position D7:D1) concatenated with the required R/W bit (in position D0). MC912ZVL Family Reference Manual, Rev. 2.48 586 NXP Semiconductors Inter-Integrated Circuit (IICV3) 20.3.1.6 IIC Control Register 2(IBCR2) Module Base + 0x0005 R W Reset 7 6 GCEN ADTYPE 0 0 5 4 3 0 0 0 0 0 0 2 1 0 ADR10 ADR9 ADR8 0 0 0 Figure 20-9. IIC Bus Control Register 2(IBCR2) This register contains the variables used in general call and in ten-bit address. Read and write anytime Table 20-10. IBCR2 Field Descriptions Field Description General Call Enable. 0 General call is disabled. The module dont receive any general call data and address. 1 enable general call. It indicates that the module can receive address and any data. 7 GCEN 6 ADTYPE Address Type— This bit selects the address length. The variable must be configured correctly before IIC enters slave mode. 0 7-bit address 1 10-bit address 5,4,3 Reserved — Bit 5,4 and 3 of the IBCR2 are reserved for future compatibility. These bits will always read 0. RESERVED 2:0 ADR[10:8] 20.4 Slave Address [10:8] —These 3 bits represent the MSB of the 10-bit address when address type is asserted (ADTYPE = 1). Functional Description This section provides a complete functional description of the IICV3. 20.4.1 I-Bus Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. Logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer and STOP signal. They are described briefly in the following sections and illustrated in Figure 20-10. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 587 Inter-Integrated Circuit (IICV3) MSB SCL 1 DA LSB 2 3 4 5 6 7 8 MSB 9 ADR7ADR6ADR5ADR4 ADR3ADR2ADR1 R/W Start Signal MSB 1 3 4 5 6 7 8 Start Signal 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 Calling Address Read/ Ack Write Bit 1 XX 9 No Ack Bit MSB 9 ADR7ADR6ADR5ADR4ADR3ADR2ADR1 R/W DA 3 Data Byte LSB 2 2 Read/ Ack Write Bit Calling Address CL XXX LSB 1 LSB 3 2 4 5 6 7 8 9 ADR7ADR6ADR5ADR4ADR3ADR2ADR1 R/W Repeated Start Signal New Calling Address Read/ No Write Ack Bit Figure 20-10. IIC-Bus Transmission Signals 20.4.1.1 START Signal When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal.As shown in Figure 20-10, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. SDA SCL START Condition STOP Condition Figure 20-11. Start and Stop Conditions MC912ZVL Family Reference Manual, Rev. 2.48 588 NXP Semiconductors Inter-Integrated Circuit (IICV3) 20.4.1.2 Slave Address Transmission The first byte of data transfer immediately after the START signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave. If the calling address is 10-bit, another byte is followed by the first byte.Only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 20-10). No two slaves in the system may have the same address. If the IIC bus is master, it must not transmit an address that is equal to its own slave address. The IIC bus cannot be master and slave at the same time.However, if arbitration is lost during an address cycle the IIC bus will revert to slave mode and operate correctly even if it is being addressed by another master. 20.4.1.3 Data Transfer As soon as successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device. Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 20-10. There is one clock pulse on SCL for each data bit, the MSB being transferred first. Each data byte has to be followed by an acknowledge bit, which is signalled from the receiving device by pulling the SDA low at the ninth clock. So one complete data byte transfer needs nine clock pulses. If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave. The master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling. If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the SDA line for the master to generate STOP or START signal.Note in order to release the bus correctly,after no-acknowledge to the master,the slave must be immediately switched to receiver and a following dummy reading of the IBDR is necessary. 20.4.1.4 STOP Signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 20-10). The master can generate a STOP even if the slave has generated an acknowledge at which point the slave must release the bus. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 589 Inter-Integrated Circuit (IICV3) 20.4.1.5 Repeated START Signal As shown in Figure 20-10, a repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 20.4.1.6 Arbitration Procedure The Inter-IC bus is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. The relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration. 20.4.1.7 Clock Synchronization Because wire-AND logic is performed on SCL line, a high-to-low transition on SCL line affects all the devices connected on the bus. The devices start counting their low period and as soon as a device's clock has gone low, it holds the SCL line low until the clock high state is reached.However, the change of low to high in this device clock may not change the state of the SCL line if another device clock is within its low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (see Figure 20-11). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulled high. There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods.The first device to complete its high period pulls the SCL line low again. WAIT Start Counting High Period SCL1 SCL2 SCL Internal Counter Reset Figure 20-12. IIC-Bus Clock Synchronization MC912ZVL Family Reference Manual, Rev. 2.48 590 NXP Semiconductors Inter-Integrated Circuit (IICV3) 20.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 20.4.1.9 Clock Stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master has driven SCL low the slave can drive SCL low for the required period and then release it.If the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched. 20.4.1.10 Ten-bit Address A ten-bit address is indicated if the first 5 bits of the first address byte are 0x11110. The following rules apply to the first address byte. SLAVE ADDRESS R/W BIT DESCRIPTION 0000000 0 General call address 0000010 x Reserved for different bus format 0000011 x Reserved for future purposes 11111XX x Reserved for future purposes 11110XX x 10-bit slave addressing Figure 20-13. Definition of bits in the first byte. The address type is identified by ADTYPE. When ADTYPE is 0, 7-bit address is applied. Reversely, the address is 10-bit address.Generally, there are two cases of 10-bit address.See the Figure 20-14 and Figure 20-15. S Slave Add1st 7bits 11110+ADR10+ADR9 R/W 0 A1 Slave Add 2nd byte ADR[8:1] A2 Data A3 Figure 20-14. A master-transmitter addresses a slave-receiver with a 10-bit address S Slave Add1st 7bits 11110+ADR10+ADR9 R/W 0 A1 Slave Add 2nd byte ADR[8:1] A2 Sr Slave Add 1st 7bits 11110+ADR10+ADR9 R/W 1 A3 Data Figure 20-15. A master-receiver addresses a slave-transmitter with a 10-bit address. In the Figure 20-15, the first two bytes are the similar to Figure 20-14. After the repeated START(Sr),the first slave address is transmitted again, but the R/W is 1, meaning that the slave is acted as a transmitter. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 591 A4 Inter-Integrated Circuit (IICV3) 20.4.1.11 General Call Address To broadcast using a general call, a device must first generate the general call address($00), then after receiving acknowledge, it must transmit data. In communication, as a slave device, provided the GCEN is asserted, a device acknowledges the broadcast and receives data until the GCEN is disabled or the master device releases the bus or generates a new transfer. In the broadcast, slaves always act as receivers. In general call, IAAS is also used to indicate the address match. In order to distinguish whether the address match is the normal address match or the general call address match, IBDR should be read after the address byte has been received. If the data is $00, the match is general call address match. The meaning of the general call address is always specified in the first data byte and must be dealt with by S/W, the IIC hardware does not decode and process the first data byte. When one byte transfer is done, the received data can be read from IBDR. The user can control the procedure by enabling or disabling GCEN. 20.4.2 Operation in Run Mode This is the basic mode of operation. 20.4.3 Operation in Wait Mode IIC operation in wait mode can be configured. Depending on the state of internal bits, the IIC can operate normally when the CPU is in wait mode or the IIC clock generation can be turned off and the IIC module enters a power conservation state during wait mode. In the later case, any transmission or reception in progress stops at wait mode entry. 20.4.4 Operation in Stop Mode The IIC is inactive in stop mode for reduced power consumption. The STOP instruction does not affect IIC register states. 20.5 Resets The reset state of each individual bit is listed in Section 20.3, “Memory Map and Register Definition,” which details the registers and their bit-fields. 20.6 Interrupts IICV3 uses only one interrupt vector. Table 20-11. Interrupt Summary Interrupt Offset Vector Priority Source Description MC912ZVL Family Reference Manual, Rev. 2.48 592 NXP Semiconductors Inter-Integrated Circuit (IICV3) IIC Interrupt — — — IBAL, TCF, IAAS When either of IBAL, TCF or IAAS bits is set bits in IBSR may cause an interrupt based on arbitration register lost, transfer complete or address detect conditions Internally there are three types of interrupts in IIC. The interrupt service routine can determine the interrupt type by reading the status register. IIC Interrupt can be generated on 1. Arbitration lost condition (IBAL bit set) 2. Byte transfer condition (TCF bit set) 3. Address detect condition (IAAS bit set) The IIC interrupt is enabled by the IBIE bit in the IIC control register. It must be cleared by writing 0 to the IBF bit in the interrupt service routine. 20.7 Application Information 20.7.1 20.7.1.1 IIC Programming Examples Initialization Sequence Reset will put the IIC bus control register to its default status. Before the interface can be used to transfer serial data, an initialization procedure must be carried out, as follows: 1. Update the frequency divider register (IBFD) and select the required division ratio to obtain SCL frequency from system clock. 2. Update the ADTYPE of IBCR2 to define the address length, 7 bits or 10 bits. 3. Update the IIC bus address register (IBAD) to define its slave address. If 10-bit address is applied IBCR2 should be updated to define the rest bits of address. 4. Set the IBEN bit of the IIC bus control register (IBCR) to enable the IIC interface system. 5. Modify the bits of the IIC bus control register (IBCR) to select master/slave mode, transmit/receive mode and interrupt enable or not. 6. If supported general call, the GCEN in IBCR2 should be asserted. 20.7.1.2 Generation of START After completion of the initialization procedure, serial data can be transmitted by selecting the 'master transmitter' mode. If the device is connected to a multi-master bus system, the state of the IIC bus busy bit (IBB) must be tested to check whether the serial bus is free. If the bus is free (IBB=0), the start condition and the first byte (the slave address) can be sent. The data written to the data register comprises the slave calling address and the LSB set to indicate the direction of transfer required from the slave. The bus free time (i.e., the time between a STOP condition and the following START condition) is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 593 Inter-Integrated Circuit (IICV3) clock and the SCL period it may be necessary to wait until the IIC is busy after writing the calling address to the IBDR before proceeding with the following instructions. This is illustrated in the following example. An example of a program which generates the START signal and transmits the first byte of data (slave address) is shown below: CHFLAG BRSET IBSR,#$20,* ;WAIT FOR IBB FLAG TO CLEAR TXSTART BSET IBCR,#$30 ;SET TRANSMIT AND MASTER MODE;i.e. GENERATE START CONDITION MOVB CALLING,IBDR ;TRANSMIT THE CALLING ADDRESS, D0=R/W BRCLR IBSR,#$20,* ;WAIT FOR IBB FLAG TO SET IBFREE 20.7.1.3 Post-Transfer Software Response Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte communication is finished. The IIC bus interrupt bit (IBIF) is set also; an interrupt will be generated if the interrupt function is enabled during initialization by setting the IBIE bit. Software must clear the IBIF bit in the interrupt routine first. The TCF bit will be cleared by reading from the IIC bus data I/O register (IBDR) in receive mode or writing to IBDR in transmit mode. Software may service the IIC I/O in the main program by monitoring the IBIF bit if the interrupt function is disabled. Note that polling should monitor the IBIF bit rather than the TCF bit because their operation is different when arbitration is lost. Note that when an interrupt occurs at the end of the address cycle the master will always be in transmit mode, i.e. the address is transmitted. If master receive mode is required, indicated by R/W bit in IBDR, then the Tx/Rx bit should be toggled at this stage. During slave mode address cycles (IAAS=1), the SRW bit in the status register is read to determine the direction of the subsequent transfer and the Tx/Rx bit is programmed accordingly.For slave mode data cycles (IAAS=0) the SRW bit is not valid, the Tx/Rx bit in the control register should be read to determine the direction of the current transfer. The following is an example of a software response by a 'master transmitter' in the interrupt routine. ISR TRANSMIT BCLR BRCLR BRCLR BRSET MOVB IBSR,#$02 IBCR,#$20,SLAVE IBCR,#$10,RECEIVE IBSR,#$01,END DATABUF,IBDR 20.7.1.4 Generation of STOP ;CLEAR THE IBIF FLAG ;BRANCH IF IN SLAVE MODE ;BRANCH IF IN RECEIVE MODE ;IF NO ACK, END OF TRANSMISSION ;TRANSMIT NEXT BYTE OF DATA A data transfer ends with a STOP signal generated by the 'master' device. A master transmitter can simply generate a STOP signal after all the data has been transmitted. The following is an example showing how a stop condition is generated by a master transmitter. MC912ZVL Family Reference Manual, Rev. 2.48 594 NXP Semiconductors Inter-Integrated Circuit (IICV3) MASTX END EMASTX TST BEQ BRSET MOVB DEC BRA BCLR RTI TXCNT END IBSR,#$01,END DATABUF,IBDR TXCNT EMASTX IBCR,#$20 ;GET VALUE FROM THE TRANSMITING COUNTER ;END IF NO MORE DATA ;END IF NO ACK ;TRANSMIT NEXT BYTE OF DATA ;DECREASE THE TXCNT ;EXIT ;GENERATE A STOP CONDITION ;RETURN FROM INTERRUPT If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (TXAK) before reading the 2nd last byte of data. Before reading the last byte of data, a STOP signal must be generated first. The following is an example showing how a STOP signal is generated by a master receiver. MASR DEC BEQ MOVB DEC BNE BSET RXCNT ENMASR RXCNT,D1 D1 NXMAR IBCR,#$08 ENMASR NXMAR BRA BCLR MOVB RTI NXMAR IBCR,#$20 IBDR,RXBUF 20.7.1.5 Generation of Repeated START LAMAR ;DECREASE THE RXCNT ;LAST BYTE TO BE READ ;CHECK SECOND LAST BYTE ;TO BE READ ;NOT LAST OR SECOND LAST ;SECOND LAST, DISABLE ACK ;TRANSMITTING ;LAST ONE, GENERATE ‘STOP’ SIGNAL ;READ DATA AND STORE At the end of data transfer, if the master continues to want to communicate on the bus, it can generate another START signal followed by another slave address without first generating a STOP signal. A program example is as shown. RESTART BSET MOVB IBCR,#$04 CALLING,IBDR 20.7.1.6 Slave Mode ;ANOTHER START (RESTART) ;TRANSMIT THE CALLING ADDRESS;D0=R/W In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be tested to check if a calling of its own address has just been received. If IAAS is set, software should set the transmit/receive mode select bit (Tx/Rx bit of IBCR) according to the R/W command bit (SRW). Writing to the IBCR clears the IAAS automatically. Note that the only time IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred, interrupts resulting from subsequent data transfers will have IAAS cleared. A data transfer may now be initiated by writing information to IBDR, for slave transmits, or dummy reading from IBDR, in slave receive mode. The slave will drive SCL low in-between byte transfers, SCL is released when the IBDR is accessed in the required mode. In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the next byte of data. Setting RXAK means an 'end of data' signal from the master receiver, after which it must be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL line so that the master can generate a STOP signal. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 595 Inter-Integrated Circuit (IICV3) 20.7.1.7 Arbitration Lost If several masters try to engage the bus simultaneously, only one master wins and the others lose arbitration. The devices which lost arbitration are immediately switched to slave receive mode by the hardware. Their data output to the SDA line is stopped, but SCL continues to be generated until the end of the byte during which arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of this transfer with IBAL=1 and MS/SL=0. If one master attempts to start transmission while the bus is being engaged by another master, the hardware will inhibit the transmission; switch the MS/SL bit from 1 to 0 without generating STOP condition; generate an interrupt to CPU and set the IBAL to indicate that the attempt to engage the bus is failed. When considering these cases, the slave service routine should test the IBAL first and the software should clear the IBAL bit if it is set. MC912ZVL Family Reference Manual, Rev. 2.48 596 NXP Semiconductors Inter-Integrated Circuit (IICV3) Clear IBIF Master Mode ? Y TX Tx/Rx ? N RX Arbitration Lost ? Y N Last Byte Transmitted ? N RXAK=0 ? Clear IBAL Y Last Byte To Be Read Y ? N End Of Addr Cycle (Master Rx) ? N Write Next Byte To IBDR Y Y (Read) N Generate Stop Signal IAAS=1 ? 10-bit address? Y Data Transfer RX TX/RX ? 7-bit address transfer 10-bit address trans TX SRW=1 ? N (Write) Y Set TX Mode N ACK From Receiver ? N IBDR== 11110xx1? Y set RX Mode Read Data From IBDR And Store Tx Next Byte Write Data To IBDR Switch To Rx Mode Y N N 2nd Last Byte To Be Read ? Set TXAK =1 Y IAAS=1 ? N Y Y N set TX Mode Dummy Read From IBDR Set RX Mode Switch To Rx Mode Write Data To IBDR Dummy Read From IBDR Generate Stop Signal Read Data From IBDR And Store Dummy Read From IBDR Dummy Read From IBDR RTI Figure 20-16. Flow-Chart of Typical IIC Interrupt Routine MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 597 Inter-Integrated Circuit (IICV3) Caution:When IIC is configured as 10-bit address,the point of the data array in interrupt routine must be reset after it’s addressed. MC912ZVL Family Reference Manual, Rev. 2.48 598 NXP Semiconductors Chapter 21 LIN Physical Layer (S12LINPHYV2) Table 21-1. Revision History Table Rev. No. Date (Item No.) (Submitted By) V02.11 V02.12 V02.13 21.1 Sections Affected 19 Sep 2013 All 20 Sep 2013 Standby Mode 8 Oct 2013 All Substantial Change(s) - Removed preliminary note. - Fixed grammar and spelling throughout the document. - Clarified Standby mode behavior. - More grammar, spelling, and formating fixes throughout the document. Introduction The LIN (Local Interconnect Network) bus pin provides a physical layer for single-wire communication in automotive applications. The LIN Physical Layer is designed to meet the LIN Physical Layer 2.2 specification from LIN consortium. 21.1.1 Features The LIN Physical Layer module includes the following distinctive features: • Compliant with LIN Physical Layer 2.2 specification. • Compliant with the SAE J2602-2 LIN standard. • Standby mode with glitch-filtered wake-up. • Slew rate selection optimized for the baud rates: 10.4 kbit/s, 20 kbit/s and Fast Mode (up to 250 kbit/s). • Switchable 34 k/330 k pullup resistors (in shutdown mode, 330 konly • Current limitation for LIN Bus pin falling edge. • Overcurrent protection. • LIN TxD-dominant timeout feature monitoring the LPTxD signal. • Automatic transmitter shutdown in case of an overcurrent or TxD-dominant timeout. • Fulfills the OEM “Hardware Requirements for LIN (CAN and FlexRay) Interfaces in Automotive Applications” v1.3. The LIN transmitter is a low-side MOSFET with current limitation and overcurrent transmitter shutdown. A selectable internal pullup resistor with a serial diode structure is integrated, so no external pullup components are required for the application in a slave node. To be used as a master node, an external MC9S12ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 599 LIN Physical Layer (S12LINPHYV2) resistor of 1 k must be placed in parallel between VLINSUP and the LIN Bus pin, with a diode between VLINSUP and the resistor. The fall time from recessive to dominant and the rise time from dominant to recessive is selectable and controlled to guarantee communication quality and reduce EMC emissions. The symmetry between both slopes is guaranteed. 21.1.2 Modes of Operation The LIN Physical Layer can operate in the following four modes: 1. Shutdown Mode The LIN Physical Layer is fully disabled. No wake-up functionality is available. The internal pullup resistor is replaced by a high ohmic one (330 k) to maintain the LIN Bus pin in the recessive state. All registers are accessible. 2. Normal Mode The full functionality is available. Both receiver and transmitter are enabled. 3. Receive Only Mode The transmitter is disabled and the receiver is running in full performance mode. 4. Standby Mode The transmitter of the LIN Physical Layer is disabled. If the wake-up feature is enabled, the internal pullup resistor can be selected (330 k or 34 k). The receiver enters a low power mode and optionally it can pass wake-up events to the Serial Communication Interface (SCI). If the wake-up feature is enabled and if the LIN Bus pin is driven with a dominant level longer than tWUFR followed by a rising edge, the LIN Physical Layer sends a wake-up pulse to the SCI, which requests a wake-up interrupt. (This feature is only available if the LIN Physical Layer is routed to the SCI). 21.1.3 Block Diagram Figure 21-1 shows the block diagram of the LIN Physical Layer. The module consists of a receiver with wake-up control, a transmitter with slope and timeout control, a current sensor with overcurrent protection as well as a registers control block. MC912ZVL Family Reference Manual, Rev. 2.48 600 NXP Semiconductors LIN Physical Layer (S12LINPHYV2)
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- , * .* * *   Figure 21-1. S12ZDBG Block Diagram NOTE The external 220 pF capacitance between LIN and LGND is strongly recommended for correct operation. 21.2 External Signal Description This section lists and describes the signals that connect off chip as well as internal supply nodes and special signals. 21.2.1 LIN — LIN Bus Pin This pad is connected to the single-wire LIN data bus. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 601 LIN Physical Layer (S12LINPHYV2) 21.2.2 LGND — LIN Ground Pin This pin is the device LIN ground connection. It is used to sink currents related to the LIN Bus pin. A de-coupling capacitor external to the device (typically 220 pF, X7R ceramic) between LIN and LGND can further improve the quality of this ground and filter noise. 21.2.3 VLINSUP — Positive Power Supply External power supply to the chip. The VLINSUP supply mapping is described in device level documentation. 21.2.4 LPTxD — LIN Transmit Pin This pin can be routed to the SCI, LPDR1 register bit, an external pin, or other options. Please refer to the PIM chapter of the device specification for the available routing options. This input is only used in normal mode; in other modes the value of this pin is ignored. 21.2.5 LPRxD — LIN Receive Pin This pin can be routed to the SCI, an external pin, or other options. Please refer to the PIM chapter of the device specification for the available routing options. In standby mode this output is disabled, and sends only a short pulse in case the wake-up functionality is enabled and a valid wake-up pulse was received in the LIN Bus. 21.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the LIN Physical Layer. 21.3.1 Module Memory Map A summary of the registers associated with the S12ZDBG module is shown in Table 21-2. Detailed descriptions of the registers and bits are given in the subsections that follow. NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level. MC912ZVL Family Reference Manual, Rev. 2.48 602 NXP Semiconductors LIN Physical Layer (S12LINPHYV2) Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 0 0 LPE RXONLY LPWUE LPPUE Reserved Reserved LPSLR1 LPSLR0 0x0000 LPDR R W 0 0 0 0 0x0001 LPCR R W 0 0 0 0 Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved LPDT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0002 Reserved R Reserved W 0x0003 LPSLRM R LPDTDIS W 0x0004 Reserved R Reserved W 0x0005 LPSR R W 0x0006 LPIE R W LPDTIE LPOCIE 0x0007 LPIF R W LPDTIF LPOCIF LPDR1 LPDR0 Figure 21-2. Register Summary 21.3.2 Register Descriptions This section describes all the S12ZDBG registers and their individual bits. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 603 LIN Physical Layer (S12LINPHYV2) 21.3.2.1 Port LP Data Register (LPDR) Access: User read/write1 Module Base + Address 0x0000 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 LPDR1 1 0 LPDR0 1 = Unimplemented Figure 21-3. Port LP Data Register (LPDR) 1 Read: Anytime Write: Anytime Table 21-2. LPDR Field Description Field Description 1 LPDR1 Port LP Data Bit 1 — The S12ZDBG LPTxD input (see Figure 21-1) can be directly controlled by this register bit. The routing of the LPTxD input is done in the Port Inetrgation Module (PIM). Please refer to the PIM chapter of the device Reference Manual for more info. 0 LPDR0 Port LP Data Bit 0 — Read-only bit. The S12ZDBG LPRxD output state can be read at any time. 21.3.2.2 LIN Control Register (LPCR) Access: User read/write1 Module Base + Address 0x0001 R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 LPE RXONLY LPWUE LPPUE 0 0 0 0 = Unimplemented Figure 21-4. LIN Control Register (LPCR) 1 Read: Anytime Write: Anytime, Table 21-3. LPCR Field Description Field Description 3 LPE LIN Enable Bit — If set, this bit enables the LIN Physical Layer. 0 The LIN Physical Layer is in shutdown mode. None of the LIN Physical Layer functions are available, except that the bus line is held in its recessive state by a high ohmic (330k) resistor. All registers are normally accessible. 1 The LIN Physical Layer is not in shutdown mode. 2 RXONLY Receive Only Mode bit — This bit controls RXONLY mode. 0 The LIN Physical Layer is not in receive only mode. 1 The LIN Physical Layer is in receive only mode. MC912ZVL Family Reference Manual, Rev. 2.48 604 NXP Semiconductors LIN Physical Layer (S12LINPHYV2) Field Description 1 LPWUE LIN Wake-Up Enable — This bit controls the wake-up feature in standby mode. 0 In standby mode the wake-up feature is disabled. 1 In standby mode the wake-up feature is enabled. 0 LPPUE LIN Pullup Resistor Enable — Selects pullup resistor. 0 The pullup resistor is high ohmic (330 k). 1 The 34 kpullup is switched on (except if LPE=0 or when in standby mode with LPWUE=0) 21.3.2.3 Reserved Register Access: User read/write1 Module Base + Address 0x0002 R W Reset 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved x x x x x x x x = Unimplemented Figure 21-5. LIN Test register 1 Read: Anytime Write: Only in special mode NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special mode can alter the module’s functionality. Table 21-4. Reserved Register Field Description Field 7-0 Reserved 21.3.2.4 Description These reserved bits are used for test purposes. Writing to these bits can alter the module functionality. LIN Slew Rate Mode Register (LPSLRM) Access: User read/write1 Module Base + Address 0x0003 7 R W Reset LPDTDIS 0 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 1 0 LPSLR1 LPSLR0 0 0 = Unimplemented Figure 21-6. LIN Slew Rate Mode Register (LPSLRM) 1 Read: Anytime Write: Only in shutdown mode (LPE=0) MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 605 LIN Physical Layer (S12LINPHYV2) Table 21-5. LPSLRM Field Description Field Description 7 LPDTDIS TxD-dominant timeout disable Bit — This bit disables the TxD-dominant timeout feature. Disabling this feature is only recommended for using the LIN Physical Layer for other applications than LIN protocol. It is only writable in shutdown mode (LPE=0). 0 TxD-dominant timeout feature is enabled. 1 TxD-dominant timeout feature is disabled. 1-0 LPSLR[1:0] Slew-Rate Bits — Please see section Section 21.4.2, “Slew Rate and LIN Mode Selection for details on how the slew rate control works. These bits are only writable in shutdown mode (LPE=0). 00 Normal Slew Rate (optimized for 20 kbit/s). 01 Slow Slew Rate (optimized for 10.4 kbit/s). 10 Fast Mode Slew Rate (up to 250 kbit/s). This mode is not compliant with the LIN Protocol (LIN electrical characteristics like duty cycles, reference levels, etc. are not fulfilled). It is only meant to be used for fast data transmission. Please refer to section Section 21.4.2.2, “Fast Mode (not LIN compliant) for more details on fast mode.Please note that an external pullup resistor stronger than 1 k might be necessary for the range 100 kbit/s to 250 kbit/s. 11 Reserved . 21.3.2.5 Reserved Register Access: User read/write1 Module Base + Address 0x0004 R W Reset 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved x x x x x x x x = Unimplemented Figure 21-7. Reserved Register 1 Read: Anytime Write: Only in special mode NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special mode can alter the module’s functionality. Table 21-6. Reserved Register Field Description Field 7-0 Reserved Description These reserved bits are used for test purposes. Writing to these bits can alter the module functionality. MC912ZVL Family Reference Manual, Rev. 2.48 606 NXP Semiconductors LIN Physical Layer (S12LINPHYV2) 21.3.2.6 LIN Status Register (LPSR) Access: User read/write1 Module Base + Address 0x0005 R 7 6 5 4 3 2 1 0 LPDT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented Figure 21-8. LIN Status Register (LPSR) 1 Read: Anytime Write: Never, writes to this register have no effect Table 21-7. LPSR Field Description Field Description 7 LPDT LIN Transmitter TxD-dominant timeout Status Bit — This read-only bit signals that the LPTxD pin is still dominant after a TxD-dominant timeout. As long as the LPTxD is dominant after the timeout the LIN transmitter is shut down and the LPTDIF is set again after attempting to clear it. 0 If there was a TxD-dominant timeout, LPTxD has ceased to be dominant after the timeout. 1 LPTxD is still dominant after a TxD-dominant timeout. 21.3.2.7 LIN Interrupt Enable Register (LPIE) Access: User read/write1 Module Base + Address 0x0006 7 R W Reset 6 LPDTIE LPOCIE 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 21-9. LIN Interrupt Enable Register (LPIE) 1 Read: Anytime Write: Anytime MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 607 LIN Physical Layer (S12LINPHYV2) Table 21-8. LPIE Field Description Field Description 7 LPDTIE LIN transmitter TxD-dominant timeout Interrupt Enable — 0 Interrupt request is disabled. 1 Interrupt is requested if LPDTIF bit is set. 6 LPOCIE LIN transmitter Overcurrent Interrupt Enable — 0 Interrupt request is disabled. 1 Interrupt is requested if LPOCIF bit is set. 21.3.2.8 LIN Interrupt Flags Register (LPIF) Access: User read/write1 Module Base + Address 0x0007 7 R W Reset 6 LPDTIF LPOCIF 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 21-10. LIN Interrupt Flags Register (LPIF) 1 Read: Anytime Write: Writing ‘1’ clears the flags, writing a ‘0’ has no effect Table 21-9. LPIF Field Description Field Description 7 LPDTIF LIN Transmitter TxD-dominant timeout Interrupt Flag — LPDTIF is set to 1 when LPTxD is still dominant (0) after tTDLIM of the falling edge of LPTxD. For protection, the transmitter is disabled. This flag can only be cleared by writing a 1. Writing a 0 has no effect. Please make sure that LPDTIF=1 before trying to clear it. Clearing LPDTIF is not allowed if LPDTIF=0 already. If the LPTxD is still dominant after clearing the flag, the transmitter stays disabled and this flag is set again (see 21.4.4.2 TxD-dominant timeout Interrupt). If interrupt requests are enabled (LPDTIE= 1), LPDTIF causes an interrupt request. 0 No TxD-dominant timeout has occurred. 1 A TxD-dominant timeout has occurred. 6 LPOCIF LIN Transmitter Overcurrent Interrupt Flag — LPOCIF is set to 1 when an overcurrent event happens. For protection, the transmitter is disabled. This flag can only be cleared by writing a 1. Writing a 0 has no effect. Please make sure that LPOCIF=1 before trying to clear it. Clearing LPOCIF is not allowed if LPOCIF=0 already. If the overcurrent is still present or LPTxD is dominant after clearing the flag, the transmitter stays disabled and this flag is set again (see21.4.4.1 Overcurrent Interrupt). If interrupt requests are enabled (LPOCIE= 1), LPOCIF causes an interrupt request. 0 No overcurrent event has occurred. 1 Overcurrent event has occurred. MC912ZVL Family Reference Manual, Rev. 2.48 608 NXP Semiconductors LIN Physical Layer (S12LINPHYV2) 21.4 Functional Description 21.4.1 General The S12ZDBG module implements the physical layer of the LIN interface. This physical layer can be driven by the SCI (Serial Communication Interface) module or directly through the LPDR register. 21.4.2 Slew Rate and LIN Mode Selection The slew rate can be selected for Electromagnetic Compatibility (EMC) optimized operation at 10.4 kbit/s and 20 kbit/s as well as at fast baud rate (up to 250 kbit/s) for test and programming. The slew rate can be chosen with the bits LPSLR[1:0] in the LIN Slew Rate Mode Register (LPSLRM). The default slew rate corresponds to 20 kbit/s. The LIN Physical Layer can also be configured to be used for non-LIN applications (for example, to transmit a PWM pulse) by disabling the TxD-dominant timeout (LPDTDIS=1). Changing the slew rate (LPSLRM Register) during transmission is not allowed in order to avoid unwanted effects. To change the register, the LIN Physical Layer must first be disabled (LPE=0). Once it is updated the LIN Physical Layer can be enabled again. NOTE For 20 kbit/s and Fast Mode communication speeds, the corresponding slew rate MUST be set; otherwise, the communication is not guaranteed (violation of the specified LIN duty cycles). For 10.4 kbit/s, the 20 kbit/s slew rate can be set but the EMC performance is worse. The up to 250 kbit/s slew rate must be chosen ONLY for fast mode, not for any of the 10.4 kbit/s or 20 kbit/s LIN compliant communication speeds. 21.4.2.1 10.4 kbit/s and 20 kbit/s When the slew rate is chosen for 10.4 kbit/s or 20 kbit/s communication, a control loop is activated within the module to make the rise and fall times of the LIN bus independent from VLINSUP and the load on the bus. 21.4.2.2 Fast Mode (not LIN compliant) Choosing this slew rate allows baud rates up to 250 kbit/s by having much steeper edges (please refer to electricals). As for the 10.4 kbit/s and 20 kbit/s modes, the slope control loop is also engaged. This mode is used for fast communication only, and the LIN electricals are not supported (for example, the LIN duty cycles). A stronger external pullup resistor might be necessary to sustain communication speeds up to 250 kbit/s. The LIN signal (and therefore the receive LPRxD signal) might not be symmetrical for high baud rates with high loads on the bus. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 609 LIN Physical Layer (S12LINPHYV2) Please note that if the bit time is smaller than the parameter tOCLIM (please refer to electricals), then no overcurrent is reported nor does an overcurrent shutdown occur. However, the current limitation is always engaged in case of a failure. 21.4.3 Modes Figure 21-11 shows the possible mode transitions depending on control bits, stop mode, and error conditions. 21.4.3.1 Shutdown Mode The LIN Physical Layer is fully disabled. No wake-up functionality is available. The internal pullup resistor is high ohmic only (330 k) to maintain the LIN Bus pin in the recessive state. LPTxD is not monitored in this mode for a TxD-dominant timeout. All the registers are accessible. Setting LPE causes the module to leave the shutdown mode and to enter the normal mode or receive only mode (if RXONLY bit is set). Clearing LPE causes the module to leave the normal or receive only modes and go back to shutdown mode. 21.4.3.2 Normal Mode The full functionality is available. Both receiver and transmitter are enabled. The internal pullup resistor can be chosen to be high ohmic (330 k) if LPPUE = 0, or LIN compliant (34 k if LPPUE = 1. If RXONLY is set, the module leaves normal mode to enter receive only mode. If the MCU enters stop mode, the LIN Physical Layer enters standby mode. 21.4.3.3 Receive Only Mode Entering this mode disables the transmitter and immediately stops any on-going transmission. LPTxD is not monitored in this mode for a TxD-dominant timeout. The receiver is running in full performance mode in all cases. To return to normal mode, the RXONLY bit must be cleared. If the device enters stop mode, the module leaves receive only mode to enter standby mode. 21.4.3.4 Standby Mode with Wake-Up Feature The transmitter of the LIN Physical Layer is disabled and the receiver enters a low power mode. NOTE Before entering standby mode, ensure no transmissions are ongoing. If LPWUE is not set, no wake up feature is available and the standby mode has the same electrical properties as the shutdown mode. This allows a low-power consumption of the device in stop mode if the wake-up feature is not needed. MC912ZVL Family Reference Manual, Rev. 2.48 610 NXP Semiconductors LIN Physical Layer (S12LINPHYV2) If LPWUE is set the receiver is able to pass wake-up events to the SCI (Serial Communication Interface). If the LIN Physical Layer receives a dominant level longer than tWUFR followed by a rising edge, it sends a pulse to the SCI which can generate a wake-up interrupt. Once the device exits stop mode, the LIN Physical Layer returns to normal or receive only mode depending on the status of the RXONLY bit. NOTE Since the wake-up interrupt is requested by the SCI, the wake-up feature is not available if the SCI is not used. The internal pullup resistor is selectable only if LPWUE = 1 (wake-up enabled). If LPWUE = 0, the internal pullup resistor is not selectable and remains at 330 k regardless of the state of the LPPUE bit. If LPWUE = 1, selecting the 330 k pullup resistor (LPPUE = 0) reduces the current consumption in standby mode. NOTE When using the LIN wake-up feature in combination with other non-LIN device wake-up features (like a periodic time interrupt), some care must be taken. If the device leaves stop mode while the LIN bus is dominant, the LIN Physical Layer returns to normal or receive only mode and the LIN bus is re-routed to the RXD pin of the SCI and triggers the edge detection interrupt (if the interrupt’s priority of the hardware that awakes the MCU is less than the priority of the SCI interrupt, then the SCI interrupt will execute first). It is up to the software to decide what to do in this case because the LIN Physical Layer can not guarantee it was a valid wake-up pulse. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 611 LIN Physical Layer (S12LINPHYV2)
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 "!%%!  "!  "! #$"! Figure 21-11. LIN Physical Layer Mode Transitions MC912ZVL Family Reference Manual, Rev. 2.48 612 NXP Semiconductors LIN Physical Layer (S12LINPHYV2) 21.4.4 Interrupts The interrupt vector requested by the S12ZDBG is listed in Table 21-10. Vector address and interrupt priority is defined at the MCU level. The module internal interrupt sources are combined into a single interrupt request at the device level. Table 21-10. Interrupt Vectors Module Interrupt Source LIN Interrupt (LPI) 21.4.4.1 Module Internal Interrupt Source Local Enable LIN Txd-Dominant Timeout Interrupt (LPDTIF) LPDTIE = 1 LIN Overcurrent Interrupt (LPOCIF) LPOCIE = 1 Overcurrent Interrupt The transmitter is protected against overcurrent. In case of an overcurrent condition occurring within a time frame called tOCLIM starting from LPTxD falling edge, the current through the transmitter is limited (the transmitter is not shut down). The masking of an overcurrent event within the time frame tOCLIM is meant to avoid “false” overcurrent conditions that can happen during the discharging of the LIN bus. If an overcurrent event occurs out of this time frame, the transmitter is disabled and the LPOCIF flag is set. In order to re-enable the transmitter again, the following prerequisites must be met: 1) Overcurrent condition is over 2) LPTxD is recessive or the LIN Physical Layer is in shutdown or receive only mode for a minimum of a transmit bit time. To re-enable the transmitter then, the LPOCIF flag must be cleared (by writing a 1). NOTE Please make sure that LPOCIF=1 before trying to clear it. It is not allowed to try to clear LPOCIF if LPOCIF=0 already. After clearing LPOCIF, if the overcurrent condition is still present or the LPTxD pin is dominant while being in normal mode, the transmitter remains disabled and the LPOCIF flag is set again after a time to indicate that the attempt to re-enable has failed. This time is equal to: • minimum 1 IRC period (1 us) + 2 bus periods • maximum 2 IRC periods (2 us) + 3 bus periods If the bit LPOCIE is set in the LPIE register, an interrupt is requested. Figure 21-12 shows the different scenarios for overcurrent interrupt handling. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 613 LIN Physical Layer (S12LINPHYV2)
 
     

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# "#    !"#   $  % Figure 21-12. Overcurrent interrupt handling 21.4.4.2 TxD-dominant timeout Interrupt To protect the LIN bus from a network lock-up, the LIN Physical Layer implements a TxD-dominant timeout mechanism. When the LPTxD signal has been dominant for more than tDTLIM the transmitter is disabled and the LPDT status flag and the LPDTIF interrupt flag are set. In order to re-enable the transmitter again, the following prerequisites must be met: 1) TxD-dominant condition is over (LPDT=0) 2) LPTxD is recessive or the LIN Physical Layer is in shutdown or receive only mode for a minimum of a transmit bit time To re-enable the transmitter then, the LPDTIF flag must be cleared (by writing a 1). NOTE Please make sure that LPDTIF=1 before trying to clear it. It is not allowed to try to clear LPDTIF if LPDTIF=0 already. MC912ZVL Family Reference Manual, Rev. 2.48 614 NXP Semiconductors LIN Physical Layer (S12LINPHYV2) After clearing LPDTIF, if the TxD-dominant timeout condition is still present or the LPTxD pin is dominant while being in normal mode, the transmitter remains disabled and the LPDTIF flag is set after a time again to indicate that the attempt to re-enable has failed. This time is equal to: • minimum 1 IRC period (1 us) + 2 bus periods • maximum 2 IRC periods (2 us) + 3 bus periods If the bit LPDTIE is set in the LPIE register, an interrupt is requested. Figure 21-13 shows the different scenarios of TxD-dominant timeout interrupt handling.
  

 
     
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           ! "! Figure 21-13. TxD-dominant timeout interrupt handling MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 615 LIN Physical Layer (S12LINPHYV2) 21.5 21.5.1 Application Information Module Initialization The following steps should be used to configure the module before starting the transmission: 1. Set the slew rate in the LPSLRM register to the desired transmission baud rate. 2. When using the LIN Physical Layer for other purposes than LIN transmission, de-activate the dominant timeout feature in the LPSLRM register if needed. 3. In most cases, the internal pullup should be enabled in the LPCR register. 4. Route the desired source in the PIM module to the LIN Physical Layer. 5. Select the transmit mode (Receive only mode or Normal mode) in the LPCR register. 6. If the SCI is selected as source, activate the wake-up feature in the LPCR register if needed for the application (SCI active edge interrupt must also be enabled). 7. Enable the LIN Physical Layer in the LPCR register. 8. Wait for a minimum of a transmit bit. 9. Begin transmission if needed. NOTE It is not allowed to try to clear LPOCIF or LPDTIF if they are already cleared. Before trying to clear an error flag, always make sure that it is already set. 21.5.2 Interrupt handling in Interrupt Service Routine (ISR) Both interrupts (TxD-dominant timeout and overcurrent) represent a failure in transmission. To avoid more disturbances on the transmission line, the transmitter is de-activated in both cases. The interrupt subroutine must take care of clearing the error condition and starting the routine that re-enables the transmission. For that purpose, the following steps are recommended: 1. First, the cause of the interrupt must be cleared: — The overcurrent will be gone after the transmitter has been disabled. — The TxD-dominant timeout condition will be gone once the selected source for LPTxD has turned recessive. 2. Clear the corresponding enable bit (LPDTIE or LPOCIE) to avoid entering the ISR again until the flags are cleared. 3. Notify the application of the error condition (LIN Error handler) and leave the ISR. In the LIN Error handler, the following sequence is recommended: 1. Disable the LIN Physical Layer (LPCR) while re-configuring the transmission. — If the receiver must remain enabled, set the LIN Physical Layer into receive only mode instead. 2. Do all required configurations (SCI, etc.) to re-enable the transmission. 3. Wait for a transmit bit (this is needed to successfully re-enable the transmitter). MC912ZVL Family Reference Manual, Rev. 2.48 616 NXP Semiconductors LIN Physical Layer (S12LINPHYV2) 4. 5. 6. 7. Clear the error flag. Enable the interrupts again (LPDTIE and LPOCIE). Enable the LIN Physical Layer or leave the receive only mode (LPCR register). Wait for a minimum of a transmit bit before beginning transmission again. If there is a problem re-enabling the transmitter, then the error flag will be set again during step 3 and the ISR will be called again. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 617 LIN Physical Layer (S12LINPHYV2) MC912ZVL Family Reference Manual, Rev. 2.48 618 NXP Semiconductors Chapter 22 Flash Module (S12ZFTMRZ) Table 22-1. Revision History Revision Number Revision Date Sections Affected V02.03 12 Apr 2012 22.3/22-622 V02.04 17 May 2012 V02.05 11 Jul 2012 - Added explanation about when MGSTAT[1:0] bits are cleared, Section 22.3.2.7 - Added note about possibility of reading P-Flash and EEPROM simultaneously, Section 22.4.6 V02.06 18 Mar 2013 - Standardized nomenclature in references to memory sizes V02.07 24 May 2013 - Revised references to NVM Resource Area to improve readability V02.8 12 Jun 2013 - Changed MLOADU Section 22.4.7.12 and MLOADF Section 22.4.7.13 FCCOB1 to FCCOB2 V02.9 15 Oct 2014 Created memory-size independent version of this module description 22.1 Description of Changes Corrected many typo. Changed caution note 22.3.2.6/22-635 - Removed flag DFDIE Introduction The P-Flash (Program Flash) and EEPROM memory sizes are specified at device level (Reference Manual device overview chapter). The description in the following sections is valid for all P-Flash and EEPROM memory sizes. The Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory contents. The user interface to the memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is written to with the command, global address, data, and any required command parameters. The memory controller must complete the execution of a command before the FCCOB register can be written to with a new command. CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. MC9S12ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 619 It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory from the same block. Simultaneous P-Flash and EEPROM operations are discussed in Section 22.4.6. Both P-Flash and EEPROM memories are implemented with Error Correction Codes (ECC) that can resolve single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read by half-phrase, only one single bit fault in an aligned 4 byte half-phrase containing the byte or word accessed will be corrected. 22.1.1 Glossary Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. EEPROM Memory — The EEPROM memory constitutes the nonvolatile memory store for data. EEPROM Sector — The EEPROM sector is the smallest portion of the EEPROM memory that can be erased. The EEPROM sector consists of 4 bytes. NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters required for Flash command execution. Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double bit fault detection within each double word. P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications. P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased. Each P-Flash sector contains 512 bytes. Program IFR — Nonvolatile information register located in the P-Flash block that contains the Version ID, and the Program Once field. 22.1.2 22.1.2.1 • • • • Features P-Flash Features Derivatives featuring up to and including 128 KB of P-Flash include one P-Flash block Derivatives featuring more than 128 KB of P-Flash include two Flash blocks In each case the P-Flash sector size is 512 bytes Single bit fault correction and double bit fault detection within a 32-bit double word during read operations MC9S12ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 620 Flash Module (S12ZFTMRZ) • • • • Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phrase program operation Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 22.1.2.2 • • • • • • The EEPROM memory is composed of one Flash block divided into sectors of 4 bytes Single bit fault correction and double bit fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Protection scheme to prevent accidental program or erase of EEPROM memory Ability to program up to four words in a burst sequence 22.1.2.3 • • • EEPROM Features Other Flash Module Features No external high-voltage power supply required for Flash memory program and erase operations Interrupt generation on Flash command completion and Flash error detection Security mechanism to prevent unauthorized access to the Flash memory 22.1.3 Block Diagram The block diagrams of the Flash modules are shown in the following figures. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 621 Flash Module (S12ZFTMRZ) Figure 22-1. FTMRZ Block Diagram Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash sector 0 sector 1 Protection final sector Security Bus Clock CPU Clock Divider FCLK Memory Controller EEPROM sector 0 sector 1 final sector 22.2 External Signal Description The Flash module contains no signals that connect off-chip. 22.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. MC912ZVL Family Reference Manual, Rev. 2.48 622 NXP Semiconductors Flash Module (S12ZFTMRZ) CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed. If such action is attempted, the result of the write operation will be unpredictable. Writing to the Flash registers is allowed when the Flash is not busy executing commands (CCIF = 1) and during initialization right after reset, despite the value of flag CCIF in that case (refer to Section 22.6 for a complete description of the reset sequence). . Table 22-2. FTMRZ Memory Map Global Address (in Bytes) 0x0_0000 – 0x0_0FFF 1 22.3.1 Description Register Space 0x10_0000 – 0x1F_4000 EEPROM memory range. Allocation is device dependent. 0x1F_4000 – 0x1F_FFFF NVM Resource Area1 (see Figure 22-3) 0x80_0000 – 0xFD_FFFF P-Flash memory range (Hardblock 0S). Allocation is device dependent. 0xFE_0000 – 0xFF_FFFF P-Flash memory range (Hardblock 0N). Allocation is device dependent. See NVM Resource area description in Section 22.4.4 Module Memory Map The P-Flash memory is located between global addresses 0x80_0000 and 0xFF_FFFF. The P-Flash is high aligned from 0xFF_FFFF. Thus, for example, a 128 KB P-Flash extends from 0xFF_FFFF to 0xFE_0000. The flash configuration field is mapped to the same addresses independent of the P-Flash memory size, as shown in Figure 22-2. The FPROT register, described in Section 22.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. Three separate memory regions, one growing upward from global address 0xFF_8000 in the Flash memory (called the lower region), one growing downward from global address 0xFF_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection. The Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 22-3. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 623 Flash Module (S12ZFTMRZ) Table 22-3. Flash Configuration Field Global Address Size (Bytes) 0xFF_FE00-0xFF_FE07 8 Backdoor Comparison Key Refer to Section 22.4.7.11, “Verify Backdoor Access Key Command,” and Section 22.5.1, “Unsecuring the MCU using Backdoor Key Access” 0xFF_FE08-0xFF_FE091 2 Protection Override Comparison Key. Refer to Section 22.4.7.17, “Protection Override Command” 0xFF_FE0A-0xFF_FE0B1 2 Reserved 0xFF_FE0C1 1 P-Flash Protection byte. Refer to Section 22.3.2.9, “P-Flash Protection Register (FPROT)” 0xFF_FE0D1 1 EEPROM Protection byte. Refer to Section 22.3.2.10, “EEPROM Protection Register (DFPROT)” 0xFF_FE0E1 1 Flash Nonvolatile byte Refer to Section 22.3.2.11, “Flash Option Register (FOPT)” 0xFF_FE0F1 1 Flash Security byte Refer to Section 22.3.2.2, “Flash Security Register (FSEC)” 1 Description 0xFF_FE08-0xFF_FE0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0xFF_FE0A - 0xFF_FE0B reserved field should be programmed to 0xFF. MC912ZVL Family Reference Manual, Rev. 2.48 624 NXP Semiconductors Flash Module (S12ZFTMRZ) P-Flash START Flash Protected/Unprotected Region Size is device dependent 0xFF_8000 0xFF_8400 0xFF_8800 0xFF_9000 Protection Fixed End Flash Protected/Unprotected Lower Region 1, 2, 4, 8 KB 0xFF_A000 Flash Protected/Unprotected Region 8 KB (up to 29 KB) Protection Movable End 0xFF_C000 Protection Fixed End 0xFF_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 KB 0xFF_F000 0xFF_F800 P-Flash END = 0xFF_FFFF Flash Configuration Field 16 bytes (0xFF_FE00 - 0xFF_FE0F) Figure 22-2. P-Flash Memory Map With Protection Alignment MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 625 Flash Module (S12ZFTMRZ) Table 22-4. Program IFR Fields Global Address Size (Bytes) 0x1F_C000 – 0x1F_C007 8 Reserved 0x1F_C008 – 0x1F_C0B5 174 Reserved 0x1F_C0B6 – 0x1F_C0B7 2 Version ID1 0x1F_C0B8 – 0x1F_C0BF 8 Reserved 0x1F_C0C0 – 0x1F_C0FF 64 Program Once Field Refer to Section 22.4.7.6, “Program Once Command” 1 Field Description Used to track firmware patch versions, see Section 22.4.2 Table 22-5. Memory Controller Resource Fields (NVM Resource Area1) Global Address Size (Bytes) 0x1F_4000 – 0x1F_41FF 512 Reserved 0x1F_4200 – 0x1F_7FFF 15,872 Reserved 0x1F_8000 – 0x1F_97FF 6,144 Reserved 0x1F_9800 – 0x1F_BFFF 10,240 Reserved 0x1F_C000 – 0x1F_C0FF 256 P-Flash IFR (see Table 22-4) 0x1F_C100 – 0x1F_C1FF 256 Reserved. 0x1F_C200 – 0x1F_FFFF 15,872 Reserved. 1 Description See Section 22.4.4 for NVM Resources Area description. MC912ZVL Family Reference Manual, Rev. 2.48 626 NXP Semiconductors Flash Module (S12ZFTMRZ) 0x1F_4000 Reserved 512 bytes 0x1F_41FF Reserved 15872 bytes 0x1F_8000 Reserved 6 KB 0x1F_97FF Reserved 10 KB 0x1F_C000 P-Flash IFR 256 bytes 0x1F_C100 Reserved 16,128 bytes Figure 22-3. Memory Controller Resource Memory Map (NVM Resources Area) 22.3.2 Register Descriptions The Flash module contains a set of 24 control and status registers located between Flash module base + 0x0000 and 0x0017. In the case of the writable registers, the write accesses are forbidden during Flash command execution (for more detail, see Caution note in Section 22.3). A summary of the Flash module registers is given in Figure 22-4 with detailed descriptions in the following subsections. Address & Name 0x0000 FCLKDIV 0x0001 FSEC 0x0002 FCCOBIX 7 R 6 5 4 3 2 1 0 FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0 FDIVLD W R W R W Figure 22-4. FTMRZ Register Summary MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 627 Flash Module (S12ZFTMRZ) Address & Name 0x0003 FPSTAT 0x0004 FCNFG 0x0005 FERCNFG 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 DFPROT1 0x000A FOPT 0x000B FRSV1 0x000C FCCOB0HI 0x000D FCCOB0LO 0x000E FCCOB1HI 0x000F FCCOB1LO 0x0010 FCCOB2HI R 7 6 5 4 3 2 1 0 FPOVRD 0 0 0 0 0 0 WSTATAC K 0 ERSAREQ FDFD FSFD 0 0 0 ACCERR FPVIOL 0 W R W R CCIE 0 IGNSF WSTAT[1:0] 0 0 0 MGBUSY RSVD MGSTAT1 MGSTAT0 0 0 0 DFDF SFDIF FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 W R W R CCIF 0 0 0 W R W R W R FPOPEN RNV6 SFDIE DPOPEN DPS6 DPS5 DPS4 DPS3 DPS2 DPS1 DPS0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W R W R W R W R W R W R W Figure 22-4. FTMRZ Register Summary (continued) MC912ZVL Family Reference Manual, Rev. 2.48 628 NXP Semiconductors Flash Module (S12ZFTMRZ) Address & Name 0x0011 FCCOB2LO 0x0012 FCCOB3HI 0x0013 FCCOB3LO 0x0014 FCCOB4HI 0x0015 FCCOB4LO 0x0016 FCCOB5HI 0x0017 FCCOB5LO R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 = Unimplemented or Reserved Figure 22-4. FTMRZ Register Summary (continued) 1 Number of implemented DPS bits depends on EEPROM memory size. 22.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Offset Module Base + 0x0000 7 R FDIVLD W Reset 0 6 5 4 3 FDIVLCK 0 2 1 0 0 0 0 FDIV[5:0] 0 0 0 = Unimplemented or Reserved Figure 22-5. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 629 Flash Module (S12ZFTMRZ) CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). Table 22-6. FCLKDIV Field Descriptions Field 7 FDIVLD Description Clock Divider Loaded 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset 6 FDIVLCK Clock Divider Locked 0 FDIV field is open for writing 1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in normal mode. 5–0 FDIV[5:0] Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events during Flash program and erase algorithms. Table 22-7 shows recommended values for FDIV[5:0] based on the BUSCLK frequency. Please refer to Section 22.4.5, “Flash Command Operations,” for more information. Table 22-7. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) MIN1 MAX2 1.0 1.6 1.6 FDIV[5:0] BUSCLK Frequency (MHz) FDIV[5:0] MIN1 MAX2 0x00 26.6 27.6 0x1A 2.6 0x01 27.6 28.6 0x1B 2.6 3.6 0x02 28.6 29.6 0x1C 3.6 4.6 0x03 29.6 30.6 0x1D 4.6 5.6 0x04 30.6 31.6 0x1E 5.6 6.6 0x05 31.6 32.6 0x1F 6.6 7.6 0x06 32.6 33.6 0x20 7.6 8.6 0x07 33.6 34.6 0x21 8.6 9.6 0x08 34.6 35.6 0x22 9.6 10.6 0x09 35.6 36.6 0x23 10.6 11.6 0x0A 36.6 37.6 0x24 11.6 12.6 0x0B 37.6 38.6 0x25 12.6 13.6 0x0C 38.6 39.6 0x26 13.6 14.6 0x0D 39.6 40.6 0x27 14.6 15.6 0x0E 40.6 41.6 0x28 15.6 16.6 0x0F 41.6 42.6 0x29 16.6 17.6 0x10 42.6 43.6 0x2A 17.6 18.6 0x11 43.6 44.6 0x2B MC912ZVL Family Reference Manual, Rev. 2.48 630 NXP Semiconductors Flash Module (S12ZFTMRZ) Table 22-7. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) 1 2 22.3.2.2 MIN1 MAX 18.6 19.6 19.6 BUSCLK Frequency (MHz) FDIV[5:0] 2 FDIV[5:0] 1 2 MIN MAX 0x12 44.6 45.6 0x2C 20.6 0x13 45.6 46.6 0x2D 20.6 21.6 0x14 46.6 47.6 0x2E 21.6 22.6 0x15 47.6 48.6 0x2F 22.6 23.6 0x16 48.6 49.6 0x30 23.6 24.6 0x17 49.6 50.6 0x31 24.6 25.6 0x18 25.6 26.6 0x19 BUSCLK is Greater Than this value. BUSCLK is Less Than or Equal to this value. Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 22-6. Flash Security Register (FSEC) 1 Loaded from Flash configuration field, during reset sequence. All bits in the FSEC register are readable but not writable. During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the Flash configuration field at global address 0xFF_FE0F located in P-Flash memory (see Table 22-3) as indicated by reset condition F in Figure 22-6. If a double bit fault is detected while reading the P-Flash phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set to leave the Flash module in a secured state with backdoor key access disabled. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 631 Flash Module (S12ZFTMRZ) Table 22-8. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the KEYEN[1:0] Flash module as shown in Table 22-9. 5–2 RNV[5:2] Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements. 1–0 SEC[1:0] Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 22-10. If the Flash module is unsecured using backdoor key access, the SEC bits are forced to 10. Table 22-9. Flash KEYEN States KEYEN[1:0] 1 Status of Backdoor Key Access 00 DISABLED 01 DISABLED1 10 ENABLED 11 DISABLED Preferred KEYEN state to disable backdoor key access. Table 22-10. Flash Security States 1 SEC[1:0] Status of Security 00 SECURED 01 SECURED1 10 UNSECURED 11 SECURED Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 22.5. 22.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to indicate the amount of parameters loaded into the FCCOB registers for Flash memory operations. Offset Module Base + 0x0002 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 0 CCOBIX[2:0] W Reset 1 0 0 0 = Unimplemented or Reserved Figure 22-7. FCCOB Index Register (FCCOBIX) CCOBIX bits are readable and writable while remaining bits read 0 and are not writable. MC912ZVL Family Reference Manual, Rev. 2.48 632 NXP Semiconductors Flash Module (S12ZFTMRZ) Table 22-11. FCCOBIX Field Descriptions Field Description 2–0 CCOBIX[1:0] Common Command Register Index— The CCOBIX bits are used to indicate how many words of the FCCOB register array are being read or written to. See 22.3.2.13 Flash Common Command Object Registers (FCCOB),” for more details. 22.3.2.4 Flash Protection Status Register (FPSTAT) This Flash register holds the status of the Protection Override feature. Offset Module Base + 0x0003 R 7 6 5 4 3 2 1 0 FPOVRD 0 0 0 0 0 0 WSTATACK 0 0 0 0 0 0 0 1 W Reset = Unimplemented or Reserved Figure 22-8. Flash Protection Status Register (FPSTAT) All bits in the FPSTAT register are readable but are not writable. Table 22-12. FPSTAT Field Descriptions Field Description 7 FPOVRD Flash Protection Override Status — The FPOVRD bit indicates if the Protection Override feature is currently enabled. See Section 22.4.7.17, “Protection Override Command” for more details. 0 Protection is not overridden 1 Protection is overridden, contents of registers FPROT and/or DFPROT (and effective protection limits determined by their current contents) were determined during execution of command Protection Override 0 WSTATACK Wait-State Switch Acknowledge — The WSTATACK bit indicates that the wait-state configuration is effectively set according to the value configured on bits FCNFG[WSTAT] (see Section 22.3.2.5, “Flash Configuration Register (FCNFG)”). WSTATACK bit is cleared when a change in FCNFG[WSTAT] is requested by writing to those bits, and is set when the Flash has effectively switched to the new wait-state configuration. The application must check the status of WSTATACK bit to make sure it reads as 1 before changing the frequency setup (see Section 22.4.3, “Flash Block Read Access”). 0 Wait-State switch is pending, Flash reads are still happening according to the previous value of FCNFG[WSTAT] 1 Wait-State switch is complete, Flash reads are already working according to the value set on FCNFG[WSTAT] 22.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt, control generation of wait-states and forces ECC faults on Flash array read access from the CPU. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 633 Flash Module (S12ZFTMRZ) Offset Module Base + 0x0004 7 R W Reset CCIE 0 6 5 0 ERSAREQ 0 0 4 3 IGNSF 0 2 WSTAT[1:0] 0 0 1 0 FDFD FSFD 0 0 = Unimplemented or Reserved Figure 22-9. Flash Configuration Register (FCNFG) CCIE, IGNSF, WSTAT, FDFD, and FSFD bits are readable and writable, ERSAREQ bit is read only, and remaining bits read 0 and are not writable. Table 22-13. FCNFG Field Descriptions Field Description 7 CCIE Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command has completed. 0 Command complete interrupt disabled 1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 22.3.2.7) 5 ERSAREQ Erase All Request — Requests the Memory Controller to execute the Erase All Blocks command and release security. ERSAREQ is not directly writable but is under indirect user control. Refer to the Reference Manual for assertion of the soc_erase_all_req input to the FTMRZ module. 0 No request or request complete 1 Request to: a) run the Erase All Blocks command b) verify the erased state c) program the security byte in the Flash Configuration Field to the unsecure state d) release MCU security by setting the SEC field of the FSEC register to the unsecure state as defined in Table 22-8 of Section 22.3.2.2. The ERSAREQ bit sets to 1 when soc_erase_all_req is asserted, CCIF=1 and the Memory Controller starts executing the sequence. ERSAREQ will be reset to 0 by the Memory Controller when the operation is completed (see Section 22.4.7.7.1). 4 IGNSF Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see Section 22.3.2.8). 0 All single bit faults detected during array reads are reported 1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated 3–2 Wait State control bits — The WSTAT[1:0] bits define how many wait-states are inserted on each read access WSTAT[1:0] to the Flash as shown on Table 22-14.Right after reset the maximum amount of wait-states is set, to be later re-configured by the application if needed. Depending on the system operating frequency being used the number of wait-states can be reduced or disabled, please refer to the Data Sheet for details. For additional information regarding the procedure to change this configuration please see Section 22.4.3. The WSTAT[1:0] bits should not be updated while the Flash is executing a command (CCIF=0); if that happens the value of this field will not change and no action will take place. MC912ZVL Family Reference Manual, Rev. 2.48 634 NXP Semiconductors Flash Module (S12ZFTMRZ) Table 22-13. FCNFG Field Descriptions (continued) Field Description 1 FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations. The FDFD bit is cleared by writing a 0 to FDFD. 0 Flash array read operations will set the DFDF flag in the FERSTAT register only if a double bit fault is detected 1 Any Flash array read operation will force the DFDF flag in the FERSTAT register to be set (see Section 22.3.2.7) 0 FSFD Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. 0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected 1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 22.3.2.7) and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see Section 22.3.2.6) Table 22-14. Flash Wait-States control WSTAT[1:0] Wait-State configuration 00 ENABLED, maximum number of cycles1 01 reserved2 10 reserved2 11 DISABLED 1 Reset condition. For a target of 100MHz core frequency / 50MHz bus frequency the maximum number required is 1 cycle. 2 Value will read as 01 or 10, as written. In the current implementation the Flash will behave the same as 00 (wait-states enabled, maximum number of cycles). 22.3.2.6 Flash Error Configuration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. Offset Module Base + 0x0005 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 SFDIE 0 = Unimplemented or Reserved Figure 22-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 635 Flash Module (S12ZFTMRZ) Table 22-15. FERCNFG Field Descriptions Field Description 0 SFDIE Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault is detected during a Flash block read operation. 0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 22.3.2.8) 1 An interrupt will be requested whenever the SFDIF flag is set (see Section 22.3.2.8) 22.3.2.7 Flash Status Register (FSTAT) The FSTAT register reports the operational status of the Flash module. Offset Module Base + 0x0006 7 R W Reset CCIF 1 6 0 0 5 4 ACCERR FPVIOL 0 0 3 2 MGBUSY RSVD 0 0 1 0 MGSTAT[1:0] 01 01 = Unimplemented or Reserved Figure 22-11. Flash Status Register (FSTAT) 1 Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 22.6). CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. Table 22-16. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation. 0 Flash command in progress 1 Flash command has completed 5 ACCERR Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory caused by either a violation of the command write sequence (see Section 22.4.5.2) or issuing an illegal Flash command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR. 0 No access error detected 1 Access error detected 4 FPVIOL Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of P-Flash or EEPROM memory during a command write sequence. The FPVIOL bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected 1 Protection violation detected 3 MGBUSY Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller. 0 Memory Controller is idle 1 Memory Controller is busy executing a Flash command (CCIF = 0) MC912ZVL Family Reference Manual, Rev. 2.48 636 NXP Semiconductors Flash Module (S12ZFTMRZ) Table 22-16. FSTAT Field Descriptions (continued) Field 2 RSVD Description Reserved Bit — This bit is reserved and always reads 0. 1–0 Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. The MGSTAT bits are cleared automatically at the start of the execution of a Flash command. See Section 22.4.7, “Flash Command Description,” and Section 22.6, “Initialization” for details. 22.3.2.8 Flash Error Status Register (FERSTAT) The FERSTAT register reflects the error status of internal Flash operations. Offset Module Base + 0x0007 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 DFDF SFDIF 0 0 = Unimplemented or Reserved Figure 22-12. Flash Error Status Register (FERSTAT) All flags in the FERSTAT register are readable and only writable to clear the flag. Table 22-17. FERSTAT Field Descriptions Field Description 1 DFDF Double Bit Fault Detect Flag — The setting of the DFDF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The DFDF flag is cleared by writing a 1 to DFDF. Writing a 0 to DFDF has no effect on DFDF.2 0 No double bit fault detected 1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command running. See Section 22.4.3, “Flash Block Read Access” for details 0 SFDIF Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation. The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF. 0 No single bit fault detected 1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted while command running 1 In case of ECC errors the corresponding flag must be cleared for the proper setting of any further error, i.e. any new error will only be indicated properly when DFDF and/or SFDIF are clear at the time the error condition is detected. 2 There is a one cycle delay in storing the ECC DFDF and SFDIF fault flags in this register. At least one NOP is required after a flash memory read before checking FERSTAT for the occurrence of ECC errors. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 637 Flash Module (S12ZFTMRZ) 22.3.2.9 P-Flash Protection Register (FPROT) The FPROT register defines which P-Flash sectors are protected against program and erase operations. Offset Module Base + 0x0008 7 R W Reset FPOPEN F1 6 5 RNV6 F1 4 FPHDIS F1 3 FPHS[1:0] F1 2 1 FPLDIS F1 F1 0 FPLS[1:0] F1 F1 = Unimplemented or Reserved Figure 22-13. Flash Protection Register (FPROT) 1 Loaded from Flash configuration field, during reset sequence. The (unreserved) bits of the FPROT register are writable Normal Single Chip Mode with the restriction that the size of the protected region can only be increased see Section 22.3.2.9.1, “P-Flash Protection Restrictions,” and Table 22-22). All (unreserved) bits of the FPROT register are writable without restriction in Special Single Chip Mode. During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte in the Flash configuration field at global address 0xFF_FE0C located in P-Flash memory (see Table 22-3) as indicated by reset condition ‘F’ in Figure 22-13. To change the P-Flash protection that will be loaded during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected. Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. Table 22-18. FPROT Field Descriptions Field Description 7 FPOPEN Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or erase operations as shown in Table 22-19 for the P-Flash block. 0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits 1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits 6 RNV[6] Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements. 5 FPHDIS Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory ending with global address 0xFF_FFFF. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 4–3 FPHS[1:0] Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area in P-Flash memory as shown inTable 22-20. The FPHS bits can only be written to while the FPHDIS bit is set. MC912ZVL Family Reference Manual, Rev. 2.48 638 NXP Semiconductors Flash Module (S12ZFTMRZ) Table 22-18. FPROT Field Descriptions (continued) Field 2 FPLDIS 1–0 FPLS[1:0] Description Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory beginning with global address 0xFF_8000. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area in P-Flash memory as shown in Table 22-21. The FPLS bits can only be written to while the FPLDIS bit is set. Table 22-19. P-Flash Protection Function 1 Function1 FPOPEN FPHDIS FPLDIS 1 1 1 No P-Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P-Flash Memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges For range sizes, refer to Table 22-20 and Table 22-21. Table 22-20. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 00 0xFF_F800–0xFF_FFFF 2 KB 01 0xFF_F000–0xFF_FFFF 4 KB 10 0xFF_E000–0xFF_FFFF 8 KB 11 0xFF_C000–0xFF_FFFF 16 KB Table 22-21. P-Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 00 0xFF_8000–0xFF_83FF 1 KB 01 0xFF_8000–0xFF_87FF 2 KB 10 0xFF_8000–0xFF_8FFF 4 KB 11 0xFF_8000–0xFF_9FFF 8 KB All possible P-Flash protection scenarios are shown in Figure 22-14 . Although the protection scheme is loaded from the Flash memory at global address 0xFF_FE0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in normal single chip mode while providing as much protection as possible if reprogramming is not required. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 639 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 Scenario FLASH START FPLS[1:0] 0xFF_FFFF FPHS[1:0] 0xFF_8000 FPOPEN = 0 0xFF_8000 FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 Flash Module (S12ZFTMRZ) 0xFF_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 22-14. P-Flash Protection Scenarios MC912ZVL Family Reference Manual, Rev. 2.48 640 NXP Semiconductors Flash Module (S12ZFTMRZ) 22.3.2.9.1 P-Flash Protection Restrictions In Normal Single Chip mode the general guideline is that P-Flash protection can only be added and not removed. Table 22-22 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 22-22. P-Flash Protection Scenario Transitions To Protection Scenario1 From Protection Scenario 0 1 2 3 0 X X X X X 1 X 4 X X X X X X X X X X 6 X 7 1 X 6 7 X 3 5 5 X X 2 4 X X X X X X Allowed transitions marked with X, see Figure 22-14 for a definition of the scenarios. 22.3.2.10 EEPROM Protection Register (DFPROT) The DFPROT register defines which EEPROM sectors are protected against program and erase operations. Offset Module Base + 0x0009 7 R W Reset 6 5 4 2 1 0 F2 F2 F2 DPS[6:0]1 DPOPEN F2 3 F2 F2 F2 F2 = Unimplemented or Reserved Figure 22-15. EEPROM Protection Register (DFPROT) 1 2 The number of implemented DPS bits depends on the EEPROM memory size, as explained below. Loaded from Flash configuration field, during reset sequence. The (unreserved) bits of the DFPROT register are writable in Normal Single Chip mode with the restriction that protection can be added but not removed. Writes in Normal Single Chip mode must increase the DPS value and the DPOPEN bit can only be written from 1 (protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is irrelevant. All DPOPEN/DPS bit registers are writable without restriction in Special Single Chip Mode. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 641 Flash Module (S12ZFTMRZ) During the reset sequence, fields DPOPEN and DPS of the DFPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0xFF_FE0D located in P-Flash memory (see Table 22-3) as indicated by reset condition F in Table 22-24. To change the EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase containing the EEPROM protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the EEPROM memory fully protected. Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. Block erase of the EEPROM memory is not possible if any of the EEPROM sectors are protected. Table 22-23. DFPROT Field Descriptions Field Description 7 DPOPEN EEPROM Protection Control 0 Enables EEPROM memory protection from program and erase with protected address range defined by DPS bits 1 Disables EEPROM memory protection from program and erase 6–0 DPS[6:0] EEPROM Protection Size — The DPS bits determine the size of the protected area in the EEPROM memory as shown in Table 22-24 . Table 22-24. EEPROM Protection Address Range DPS[6:0] Global Address Range Protected Size 0000000 0x10_0000 – 0x10_001F 32 bytes 0000001 0x10_0000 – 0x10_003F 64 bytes 0000010 0x10_0000 – 0x10_005F 96 bytes 0000011 0x10_0000 – 0x10_007F 128 bytes 0000100 0x10_0000 – 0x10_009F 160 bytes The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increment . . 0001111 0x10_0000 – 0x10_01FF 512 bytes 0011111 0x10_0000 – 0x10_03FF 1K byte 0111111 0x10_0000 – 0x10_07FF 2K bytes 1111111 0x10_0000 – 0x10_0FFF 4K bytes The number of DPS bits depends on the size of the implemented EEPROM. The whole implemented EEPROM range can always be protected. Each DPS value increment increases the size of the protected range by 32-bytes. Thus to protect a 1 KB range DPS[4:0] must be set (protected range of 32 x 32 bytes). MC912ZVL Family Reference Manual, Rev. 2.48 642 NXP Semiconductors Flash Module (S12ZFTMRZ) 22.3.2.11 Flash Option Register (FOPT) The FOPT register is the Flash option register. Offset Module Base + 0x000A 7 6 5 4 R 2 1 0 F1 F1 F1 F1 NV[7:0] W Reset 3 F1 F1 F1 F1 = Unimplemented or Reserved Figure 22-16. Flash Option Register (FOPT) 1 Loaded from Flash configuration field, during reset sequence. All bits in the FOPT register are readable but can only be written in special mode. During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global address 0xFF_FE0E located in P-Flash memory (see Table 22-3) as indicated by reset condition F in Figure 22-16. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. Table 22-25. FOPT Field Descriptions Field 7–0 NV[7:0] Description Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device overview for proper use of the NV bits. 22.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing. Offset Module Base + 0x000B R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 22-17. Flash Reserved1 Register (FRSV1) All bits in the FRSV1 register read 0 and are not writable. 22.3.2.13 Flash Common Command Object Registers (FCCOB) The FCCOB is an array of six words. Byte wide reads and writes are allowed to the FCCOB registers. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 643 Flash Module (S12ZFTMRZ) Offset Module Base + 0x000C 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[15:8] W Reset 3 0 0 0 0 Figure 22-18. Flash Common Command Object 0 High Register (FCCOB0HI) Offset Module Base + 0x000D 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[7:0] W Reset 3 0 0 0 0 Figure 22-19. Flash Common Command Object 0 Low Register (FCCOB0LO) Offset Module Base + 0x000E 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[15:8] W Reset 3 0 0 0 0 Figure 22-20. Flash Common Command Object 1 High Register (FCCOB1HI) Offset Module Base + 0x000F 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[7:0] W Reset 3 0 0 0 0 Figure 22-21. Flash Common Command Object 1 Low Register (FCCOB1LO) Offset Module Base + 0x0010 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[15:8] W Reset 3 0 0 0 0 Figure 22-22. Flash Common Command Object 2 High Register (FCCOB2HI) MC912ZVL Family Reference Manual, Rev. 2.48 644 NXP Semiconductors Flash Module (S12ZFTMRZ) Offset Module Base + 0x0011 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[7:0] W Reset 3 0 0 0 0 Figure 22-23. Flash Common Command Object 2 Low Register (FCCOB2LO) Offset Module Base + 0x0012 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[15:8] W Reset 3 0 0 0 0 Figure 22-24. Flash Common Command Object 3 High Register (FCCOB3HI) Offset Module Base + 0x0013 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[7:0] W Reset 3 0 0 0 0 Figure 22-25. Flash Common Command Object 3 Low Register (FCCOB3LO) Offset Module Base + 0x0014 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[15:8] W Reset 3 0 0 0 0 Figure 22-26. Flash Common Command Object 4 High Register (FCCOB4HI) Offset Module Base + 0x0015 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[7:0] W Reset 3 0 0 0 0 Figure 22-27. Flash Common Command Object 4 Low Register (FCCOB4LO) MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 645 Flash Module (S12ZFTMRZ) Offset Module Base + 0x0016 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[15:8] W Reset 3 0 0 0 0 Figure 22-28. Flash Common Command Object 5 High Register (FCCOB5HI) Offset Module Base + 0x0017 7 6 5 4 R 2 1 0 0 0 0 0 CCOB[7:0] W Reset 3 0 0 0 0 Figure 22-29. Flash Common Command Object 5 Low Register (FCCOB5LO) 22.3.2.13.1 FCCOB - NVM Command Mode NVM command mode uses the FCCOB registers to provide a command code and its relevant parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes (as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array. The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 22-26. The return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller. The value written to the FCCOBIX field must reflect the amount of CCOB words loaded for command execution. Table 22-26 shows the generic Flash command format. The high byte of the first word in the CCOB array contains the command code, followed by the parameters for this specific Flash command. For details on the FCCOB settings required by each command, see the Flash command descriptions in Section 22.4.7. Table 22-26. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Register 000 FCCOB0 001 FCCOB1 010 FCCOB2 Byte FCCOB Parameter Fields (NVM Command Mode) HI FCMD[7:0] defining Flash command LO Global address [23:16] HI Global address [15:8] LO Global address [7:0] HI Data 0 [15:8] LO Data 0 [7:0] MC912ZVL Family Reference Manual, Rev. 2.48 646 NXP Semiconductors Flash Module (S12ZFTMRZ) Table 22-26. FCCOB - NVM Command Mode (Typical Usage) 22.4 CCOBIX[2:0] Register 011 FCCOB3 100 FCCOB4 101 FCCOB5 Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] Functional Description 22.4.1 Modes of Operation The module provides the modes of operation normal and special. The operating mode is determined by module-level inputs and affects the FCLKDIV, FCNFG, and DFPROT registers (see Table 22-28). 22.4.2 IFR Version ID Word The version ID word is stored in the IFR at address 0x1F_C0B6. The contents of the word are defined in Table 22-27. Table 22-27. IFR Version ID Fields • [15:4] [3:0] Reserved VERNUM VERNUM: Version number. The first version is number 0b_0001 with both 0b_0000 and 0b_1111 meaning ‘none’. 22.4.3 Flash Block Read Access If data read from the Flash block results in a double-bit fault ECC error (meaning that data is detected to be in error and cannot be corrected), the read data will be tagged as invalid during that access (please look into the Reference Manual for details). Forcing the DFDF status bit by setting FDFD (see Section 22.3.2.5) has effect only on the DFDF status bit value and does not result in an invalid access. To guarantee the proper read timing from the Flash array, the Flash will control (i.e. pause) the S12Z core accesses, considering that the MCU can be configured to fetch data at a faster frequency than the Flash MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 647 Flash Module (S12ZFTMRZ) block can support. Right after reset the Flash will be configured to run with the maximum amount of wait-states enabled; if the user application is setup to run at a slower frequency the control bits FCNFG[WSTAT] (see Section 22.3.2.5) can be configured by the user to disable the generation of wait-states, so it does not impose a performance penalty to the system if the read timing of the S12Z core is setup to be within the margins of the Flash block. For a definition of the frequency values where wait-states can be disabled please refer to the device electrical parameters. The following sequence must be followed when the transition from a higher frequency to a lower frequency is going to happen: • Flash resets with wait-states enabled; • system frequency must be configured to the lower target; • user writes to FNCNF[WSTAT] to disable wait-states; • user reads the value of FPSTAT[WSTATACK], the new wait-state configuration will be effective when it reads as 1; • user must re-write FCLKDIV to set a new value based on the lower frequency. The following sequence must be followed on the contrary direction, going from a lower frequency to a higher frequency: • user writes to FCNFG[WSTAT] to enable wait-states; • user reads the value of FPSTAT[WSTATACK], the new wait-state configuration will be effective when it reads as 1; • user must re-write FCLKDIV to set a new value based on the higher frequency; • system frequency must be set to the upper target. CAUTION If the application is going to require the frequency setup to change, the value to be loaded on register FCLKDIV will have to be updated according to the new frequency value. In this scenario the application must take care to avoid locking the value of the FCLKDIV register: bit FDIVLCK must not be set if the value to be loaded on FDIV is going to be re-written, otherwise a reset is going to be required. Please refer to Section 22.3.2.1, “Flash Clock Divider Register (FCLKDIV) and Section 22.4.5.1, “Writing the FCLKDIV Register. 22.4.4 Internal NVM resource IFR is an internal NVM resource readable by CPU. The IFR fields are shown in Table 22-4. The NVM Resource Area global address map is shown in Table 22-5. 22.4.5 Flash Command Operations Flash command operations are used to modify Flash memory contents. The next sections describe: MC912ZVL Family Reference Manual, Rev. 2.48 648 NXP Semiconductors Flash Module (S12ZFTMRZ) • • • How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from BUSCLK for Flash program and erase command operations The command write sequence used to set Flash command parameters and launch execution Valid Flash commands available for execution, according to MCU functional mode and MCU security state. 22.4.5.1 Writing the FCLKDIV Register Prior to issuing any Flash program or erase command after a reset, the user is required to write the FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz. Table 22-7 shows recommended values for the FDIV field based on BUSCLK frequency. NOTE Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash memory due to overstress. Setting FDIV too low can result in incomplete programming or erasure of the Flash memory cells. When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written, any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set. 22.4.5.2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see Section 22.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence. If CCIF is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the FCCOB register are ignored. 22.4.5.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. The CCOBIX bits in the FCCOBIX register must reflect the amount of words loaded into the FCCOB registers (see Section 22.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag will remain clear until the Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 22-30. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 649 Flash Module (S12ZFTMRZ) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no Read: FSTAT register yes FCCOB Availability Check CCIF Set? yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to indicate number of parameters to be loaded. Write to FCCOB register to load required command parameter. More Parameters? yes no Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 22-30. Generic Flash Command Write Sequence Flowchart MC912ZVL Family Reference Manual, Rev. 2.48 650 NXP Semiconductors Flash Module (S12ZFTMRZ) 22.4.5.3 Valid Flash Module Commands Table 22-28 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). + Table 22-28. Flash Commands by Mode and Security State Unsecured FCMD Command Secured NS1 SS2 NS3 SS4 0x01 Erase Verify All Blocks     0x02 Erase Verify Block     0x03 Erase Verify P-Flash Section    0x04 Read Once    0x06 Program P-Flash    0x07 Program Once    0x08 Erase All Blocks 0x09 Erase Flash Block    0x0A Erase P-Flash Sector    0x0B Unsecure Flash 0x0C Verify Backdoor Access Key  0x0D Set User Margin Level  0x0E Set Field Margin Level 0x10 Erase Verify EEPROM Section    0x11 Program EEPROM    0x12 Erase EEPROM Sector    0x13 Protection Override             1 Unsecured Normal Single Chip mode Unsecured Special Single Chip mode. 3 Secured Normal Single Chip mode. 4 Secured Special Single Chip mode. 2 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 651 Flash Module (S12ZFTMRZ) 22.4.5.4 P-Flash Commands Table 22-29 summarizes the valid P-Flash commands along with the effects of the commands on the P-Flash block and other resources within the Flash module. Table 22-29. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the DFPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a P-Flash (or EEPROM) block. An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. 0x0A Erase P-Flash Sector 0x0B Unsecure Flash 0x0C Verify Backdoor Access Key Supports a method of releasing MCU security by verifying a set of security keys. 0x0D Set User Margin Level Specifies a user margin read level for all P-Flash blocks. 0x0E Set Field Margin Level Specifies a field margin read level for all P-Flash blocks (special modes only). 0x13 Protection Override 22.4.5.5 Function on P-Flash Memory Verify that all P-Flash (and EEPROM) blocks are erased. Verify that a P-Flash block is erased. Verify that a given number of words starting at the address provided are erased. Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block that was previously programmed using the Program Once command. Program a phrase in a P-Flash block. Erase all bytes in a P-Flash sector. Supports a method of releasing MCU security by erasing all P-Flash (and EEPROM) blocks and verifying that all P-Flash (and EEPROM) blocks are erased. Supports a mode to temporarily override Protection configuration (for P-Flash and/or EEPROM) by verifying a key. EEPROM Commands Table 22-30 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. MC912ZVL Family Reference Manual, Rev. 2.48 652 NXP Semiconductors Flash Module (S12ZFTMRZ) Table 22-30. EEPROM Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block Function on EEPROM Memory Verify that all EEPROM (and P-Flash) blocks are erased. Verify that the EEPROM block is erased. 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the DFPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block. An erase of the full EEPROM block is only possible when DPOPEN bit in the DFPROT register is set prior to launching the command. 0x0B Unsecure Flash 0x0D Set User Margin Level Specifies a user margin read level for the EEPROM block. 0x0E Set Field Margin Level Specifies a field margin read level for the EEPROM block (special modes only). 0x10 Erase Verify EEPROM Section Verify that a given number of words starting at the address provided are erased. 0x11 Program EEPROM Program up to four words in the EEPROM block. 0x12 Erase EEPROM Sector Erase all bytes in a sector of the EEPROM block. 0x13 Protection Override 22.4.6 Supports a method of releasing MCU security by erasing all EEPROM (and P-Flash) blocks and verifying that all EEPROM (and P-Flash) blocks are erased. Supports a mode to temporarily override Protection configuration (for P-Flash and/or EEPROM) by verifying a key. Allowed Simultaneous P-Flash and EEPROM Operations Only the operations marked ‘OK’ in Table 22-31 are permitted to be run simultaneously on combined Program Flash and EEPROM blocks. Some operations cannot be executed simultaneously because certain hardware resources are shared by the two memories. The priority has been placed on permitting Program Flash reads while program and erase operations execute on the EEPROM, providing read (P-Flash) while write (EEPROM) functionality. Any attempt to access P-Flash and EEPROM simultaneously when it is not allowed will result in an illegal access that will trigger a machine exception in the CPU (see device information for details). Please note that during the execution of each command there is a period, before the operation in the Flash array actually starts, where reading is allowed and valid data is returned. Even if the simultaneous operation is marked as not allowed the Flash will report an illegal access only in the cycle the read collision actually happens, maximizing the time the array is available for reading. If more than one hardblock exists on a device, then read operations on one hardblock are permitted whilst program or erase operations are executed on the other hardblock. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 653 Flash Module (S12ZFTMRZ) Table 22-31. Allowed P-Flash and EEPROM Simultaneous Operations on a single hardblock EEPROM Program Flash Read Margin Read2 Program Sector Erase Read OK1 OK OK OK Mass Erase2 Margin Read2 Program Sector Erase Mass Erase3 OK 1 Strictly speaking, only one read of either the P-Flash or EEPROM can occur at any given instant, but the memory controller will transparently arbitrate P-Flash and EEPROM accesses giving uninterrupted read access whenever possible. 2 A ‘Margin Read’ is any read after executing the margin setting commands ‘Set User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified. See the Note on margin settings in Section 22.4.7.12 and Section 22.4.7.13. 3 The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ 22.4.7 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence. The ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be processed by the Memory Controller: • Starting any command write sequence that programs or erases Flash memory before initializing the FCLKDIV register • Writing an invalid command as part of the command write sequence • For additional possible errors, refer to the error handling table provided for each command If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation may return invalid data resulting in an illegal access (as described on Section 22.4.6). If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting any command write sequence (see Section 22.3.2.7). CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. 22.4.7.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and EEPROM blocks have been erased. MC912ZVL Family Reference Manual, Rev. 2.48 654 NXP Semiconductors Flash Module (S12ZFTMRZ) Table 22-32. Erase Verify All Blocks Command FCCOB Requirements Register FCCOB Parameters FCCOB0 0x01 Not required Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks operation has completed. If all blocks are not erased, it means blank check failed, both MGSTAT bits will be set. Table 22-33. Erase Verify All Blocks Command Error Handling Register Error Bit ACCERR FPVIOL FSTAT 22.4.7.2 Error Condition Set if CCOBIX[2:0] != 000 at command launch None MGSTAT1 Set if any errors have been encountered during the reador if blank check failed . MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. Table 22-34. Erase Verify Block Command FCCOB Requirements Register FCCOB Parameters FCCOB0 0x02 FCCOB1 Global address [23:16] to identify Flash block Global address [15:0] to identify Flash block Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that the selected P-Flash or EEPROM block is erased. The CCIF flag will set after the Erase Verify Block operation has completed.If the block is not erased, it means blank check failed, both MGSTAT bits will be set. Table 22-35. Erase Verify Block Command Error Handling Register Error Bit ACCERR FSTAT FPVIOL Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if an invalid global address [23:0] is supplied see Table 22-2) None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 655 Flash Module (S12ZFTMRZ) 22.4.7.3 Erase Verify P-Flash Section Command The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. Table 22-36. Erase Verify P-Flash Section Command FCCOB Requirements Register FCCOB Parameters FCCOB0 0x03 Global address [23:16] of a P-Flash block FCCOB1 Global address [15:0] of the first phrase to be verified FCCOB2 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. Table 22-37. Erase Verify P-Flash Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 22-28) ACCERR Set if an invalid global address [23:0] is supplied see Table 22-2) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT Set if the requested section crosses a the P-Flash address boundary FPVIOL 22.4.7.4 None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. Read Once Command The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of P-Flash. The Read Once field is programmed using the Program Once command described in Section 22.4.7.6. The Read Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 22-38. Read Once Command FCCOB Requirements Register FCCOB0 FCCOB Parameters 0x04 Not Required FCCOB1 Read Once phrase index (0x0000 - 0x0007) FCCOB2 Read Once word 0 value MC912ZVL Family Reference Manual, Rev. 2.48 656 NXP Semiconductors Flash Module (S12ZFTMRZ) Table 22-38. Read Once Command FCCOB Requirements Register FCCOB Parameters FCCOB3 Read Once word 1 value FCCOB4 Read Once word 2 value FCCOB5 Read Once word 3 value Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. 8 Table 22-39. Read Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if an invalid phrase index is supplied FSTAT 22.4.7.5 Set if command not available in current mode (see Table 22-28) FPVIOL None MGSTAT1 Set if any errors have been encountered during the read MGSTAT0 Set if any non-correctable errors have been encountered during the read Program P-Flash Command The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an embedded algorithm. CAUTION A P-Flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash phrase is not allowed. Table 22-40. Program P-Flash Command FCCOB Requirements Register FCCOB0 1 FCCOB Parameters 0x06 Global address [23:16] to identify P-Flash block FCCOB1 Global address [15:0] of phrase location to be programmed1 FCCOB2 Word 0 program value FCCOB3 Word 1 program value FCCOB4 Word 2 program value FCCOB5 Word 3 program value Global address [2:0] must be 000 MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 657 Flash Module (S12ZFTMRZ) Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. The CCIF flag will set after the Program P-Flash operation has completed. Table 22-41. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 22-28) ACCERR Set if an invalid global address [23:0] is supplied see Table 22-2) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 22.4.7.6 Set if the global address [17:0] points to a protected area MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Program Once Command The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in P-Flash. The Program Once reserved field can be read using the Read Once command as described in Section 22.4.7.4. The Program Once command must only be issued once since the nonvolatile information register in P-Flash cannot be erased. The Program Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 22-42. Program Once Command FCCOB Requirements CCOBIX[2:0] FCCOB0 FCCOB Parameters 0x07 Not Required FCCOB1 Program Once phrase index (0x0000 - 0x0007) FCCOB2 Program Once word 0 value FCCOB3 Program Once word 1 value FCCOB4 Program Once word 2 value FCCOB5 Program Once word 3 value Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with read back. The CCIF flag will remain clear, setting only after the Program Once operation has completed. The reserved nonvolatile information register accessed by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. MC912ZVL Family Reference Manual, Rev. 2.48 658 NXP Semiconductors Flash Module (S12ZFTMRZ) Table 22-43. Program Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch ACCERR Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed1 FSTAT FPVIOL 1 Set if command not available in current mode (see Table 22-28) None MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will be allowed to execute again on that same phrase. 22.4.7.7 Erase All Blocks Command The Erase All Blocks operation will erase the entire P-Flash and EEPROM memory space. Table 22-44. Erase All Blocks Command FCCOB Requirements Register FCCOB0 FCCOB Parameters 0x08 Not required Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All Blocks operation has completed. Table 22-45. Erase All Blocks Command Error Handling Register Error Bit ACCERR FPVIOL FSTAT 22.4.7.7.1 Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 22-28) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Erase All Pin The functionality of the Erase All Blocks command is also available in an uncommanded fashion from the soc_erase_all_req input pin on the Flash module. Refer to the Reference Manual for information on control of soc_erase_all_req. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 659 Flash Module (S12ZFTMRZ) The erase-all function requires the clock divider register FCLKDIV (see Section 22.3.2.1) to be loaded before invoking this function using soc_erase_all_req input pin. The FCLKDIV configuration for this feature is described at device level. If FCLKDIV is not properly set the erase-all operation will not execute and the ACCERR flag in FSTAT register will set. After the execution of the erase-all function the FCLKDIV register will be reset and the value of register FCLKDIV must be loaded before launching any other command afterwards. Before invoking the erase-all function using the soc_erase_all_req pin, the ACCERR and FPVIOL flags in the FSTAT register must be clear. When invoked from soc_erase_all_req the erase-all function will erase all P-Flash memory and EEPROM memory space regardless of the protection settings. If the post-erase verify passes, the routine will then release security by setting the SEC field of the FSEC register to the unsecure state (see Section 22.3.2.2). The security byte in the Flash Configuration Field will be programmed to the unsecure state (see Table 22-8). The status of the erase-all request is reflected in the ERSAREQ bit in the FCNFG register (see Section 22.3.2.5). The ERSAREQ bit in FCNFG will be cleared once the operation has completed and the normal FSTAT error reporting will be available as described inTable 22-46. At the end of the erase-all sequence Protection will remain configured as it was before executing the erase-all function. If the application requires programming P-Flash and/or EEPROM after the erase-all function completes, the existing protection limits must be taken into account. If protection needs to be disabled the user may need to reset the system right after completing the erase-all function. Table 22-46. Erase All Pin Error Handling Register FSTAT 22.4.7.8 Error Bit Error Condition ACCERR Set if command not available in current mode (see Table 22-28) MGSTAT1 Set if any errors have been encountered during the erase verify operation, or during the program verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the erase verify operation, or during the program verify operation Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or EEPROM block. Table 22-47. Erase Flash Block Command FCCOB Requirements Register FCCOB0 FCCOB1 FCCOB Parameters 0x09 Global address [23:16] to identify Flash block Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. MC912ZVL Family Reference Manual, Rev. 2.48 660 NXP Semiconductors Flash Module (S12ZFTMRZ) Table 22-48. Erase Flash Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 22-28) ACCERR Set if the supplied P-Flash address is not phrase-aligned or if the EEPROM address is not word-aligned FSTAT FPVIOL 22.4.7.9 Set if an invalid global address [23:0] is supplied Set if an area of the selected Flash block is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Erase P-Flash Sector Command The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector. Table 22-49. Erase P-Flash Sector Command FCCOB Requirements Register FCCOB0 FCCOB1 FCCOB Parameters 0x0A Global address [23:16] to identify P-Flash block to be erased Global address [15:0] anywhere within the sector to be erased. Refer to Section 22.1.2.1 for the P-Flash sector size. Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed. Table 22-50. Erase P-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if command not available in current mode (see Table 22-28) Set if an invalid global address [23:0] is supplied see Table 22-2) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL Set if the selected P-Flash sector is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 661 Flash Module (S12ZFTMRZ) 22.4.7.10 Unsecure Flash Command The Unsecure Flash command will erase the entire P-Flash and EEPROM memory space and, if the erase is successful, will release security. Table 22-51. Unsecure Flash Command FCCOB Requirements Register FCCOB0 FCCOB Parameters 0x0B Not required Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire P-Flash and EEPROM memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. If the erase verify is not successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security state. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag is set after the Unsecure Flash operation has completed. Table 22-52. Unsecure Flash Command Error Handling Register Error Bit ACCERR FSTAT FPVIOL Error Condition Set if CCOBIX[2:0] != 000 at command launch Set if command not available in current mode (see Table 22-28) Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 22.4.7.11 Verify Backdoor Access Key Command The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 22-9). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see Table 22-3). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 22-53. Verify Backdoor Access Key Command FCCOB Requirements Register FCCOB0 FCCOB Parameters 0x0C Not required FCCOB1 Key 0 FCCOB2 Key 1 FCCOB3 Key 2 FCCOB4 Key 3 MC912ZVL Family Reference Manual, Rev. 2.48 662 NXP Semiconductors Flash Module (S12ZFTMRZ) Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash configuration field with Key 0 compared to 0xFF_FE00, etc. If the backdoor keys match, security will be released. If the backdoor keys do not match, security is not released and all future attempts to execute the Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is set after the Verify Backdoor Access Key operation has completed. Table 22-54. Verify Backdoor Access Key Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 100 at command launch Set if an incorrect backdoor key is supplied ACCERR FSTAT Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see Section 22.3.2.2) Set if the backdoor key has mismatched since the last reset FPVIOL None MGSTAT1 None MGSTAT0 None 22.4.7.12 Set User Margin Level Command The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P-Flash or EEPROM block. Table 22-55. Set User Margin Level Command FCCOB Requirements Register FCCOB0 FCCOB Parameters 0x0D Global address [23:16] to identify Flash block FCCOB1 Global address [15:0] to identify Flash block FCCOB2 Margin level setting. Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply user margin levels to the P-Flash block only. Valid margin level settings for the Set User Margin Level command are defined in Table 22-56. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 663 Flash Module (S12ZFTMRZ) Table 22-56. Valid Set User Margin Level Settings 1 2 FCCOB2 Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 Read margin to the erased state Read margin to the programmed state Table 22-57. Set User Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch ACCERR FSTAT Set if command not available in current mode (see Table 22-28) Set if an invalid global address [23:0] is supplied see Table 22-2) Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None NOTE User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. 22.4.7.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of the P-Flash or EEPROM block. Table 22-58. Set Field Margin Level Command FCCOB Requirements Register FCCOB0 FCCOB Parameters 0x0E Global address [23:16] to identify Flash block FCCOB1 Global address [15:0] to identify Flash block FCCOB2 Margin level setting. Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the field margin level for the targeted block and then set the CCIF flag. MC912ZVL Family Reference Manual, Rev. 2.48 664 NXP Semiconductors Flash Module (S12ZFTMRZ) NOTE When the EEPROM block is targeted, the EEPROM field margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash field margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply field margin levels to the P-Flash block only. Valid margin level settings for the Set Field Margin Level command are defined in Table 22-59. Table 22-59. Valid Set Field Margin Level Settings 1 2 FCCOB2 Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 0x0003 Field Margin-1 Level1 0x0004 Field Margin-0 Level2 Read margin to the erased state Read margin to the programmed state Table 22-60. Set Field Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch ACCERR FSTAT Set if command not available in current mode (see Table 22-28) Set if an invalid global address [23:0] is supplied see Table 22-2) Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None CAUTION Field margin levels must only be used during verify of the initial factory programming. NOTE Field margin levels can be used to check that Flash memory contents have adequate margin for data retention at the normal level setting. If unexpected results are encountered when checking Flash memory contents at field margin levels, the Flash memory contents should be erased and reprogrammed. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 665 Flash Module (S12ZFTMRZ) 22.4.7.14 Erase Verify EEPROM Section Command The Erase Verify EEPROM Section command will verify that a section of code in the EEPROM is erased. The Erase Verify EEPROM Section command defines the starting point of the data to be verified and the number of words. Table 22-61. Erase Verify EEPROM Section Command FCCOB Requirements Register FCCOB Parameters FCCOB0 0x10 Global address [23:16] to identify the EEPROM block FCCOB1 Global address [15:0] of the first word to be verified FCCOB2 Number of words to be verified Upon clearing CCIF to launch the Erase Verify EEPROM Section command, the Memory Controller will verify the selected section of EEPROM memory is erased. The CCIF flag will set after the Erase Verify EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. Table 22-62. Erase Verify EEPROM Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 22-28) ACCERR Set if an invalid global address [23:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested section breaches the end of the EEPROM block FPVIOL None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. 22.4.7.15 Program EEPROM Command The Program EEPROM operation programs one to four previously erased words in the EEPROM block. The Program EEPROM operation will confirm that the targeted location(s) were successfully programmed upon completion. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. MC912ZVL Family Reference Manual, Rev. 2.48 666 NXP Semiconductors Flash Module (S12ZFTMRZ) Table 22-63. Program EEPROM Command FCCOB Requirements Register FCCOB0 FCCOB Parameters Global address [23:16] to identify the EEPROM block 0x11 FCCOB1 Global address [15:0] of word to be programmed FCCOB2 Word 0 program value FCCOB3 Word 1 program value, if desired FCCOB4 Word 2 program value, if desired FCCOB5 Word 3 program value, if desired Upon clearing CCIF to launch the Program EEPROM command, the user-supplied words will be transferred to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program EEPROM command launch determines how many words will be programmed in the EEPROM block. The CCIF flag is set when the operation has completed. Table 22-64. Program EEPROM Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] < 010 at command launch Set if CCOBIX[2:0] > 101 at command launch ACCERR Set if command not available in current mode (see Table 22-28) Set if an invalid global address [23:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested group of words breaches the end of the EEPROM block FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 22.4.7.16 Erase EEPROM Sector Command The Erase EEPROM Sector operation will erase all addresses in a sector of the EEPROM block. Table 22-65. Erase EEPROM Sector Command FCCOB Requirements Register FCCOB0 FCCOB1 FCCOB Parameters 0x12 Global address [23:16] to identify EEPROM block Global address [15:0] anywhere within the sector to be erased. See Section 22.1.2.2 for EEPROM sector size. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 667 Flash Module (S12ZFTMRZ) Upon clearing CCIF to launch the Erase EEPROM Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase EEPROM Sector operation has completed. Table 22-66. Erase EEPROM Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if command not available in current mode (see Table 22-28) Set if an invalid global address [23:0] is supplied see Table 22-2 Set if a misaligned word address is supplied (global address [0] != 0) FSTAT FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 22.4.7.17 Protection Override Command The Protection Override command allows the user to temporarily override the protection limits, either decreasing, increasing or disabling protection limits, on P-Flash and/or EEPROM, if the comparison key provided as a parameter loaded on FCCOB matches the value of the key previously programmed on the Flash Configuration Field (see Table 22-3). The value of the Protection Override Comparison Key must not be 16’hFFFF, that is considered invalid and if used as argument will cause the Protection Override feature to be disabled. Any valid key value that does not match the value programmed in the Flash Configuration Field will cause the Protection Override feature to be disabled. Current status of the Protection Override feature can be observed on FPSTAT FPOVRD bit (see Section 22.3.2.4, “Flash Protection Status Register (FPSTAT)). Table 22-67. Protection Override Command FCCOB Requirements Register FCCOB0 FCCOB Parameters 0x13 FCCOB1 Protection Update Selection [1:0] See Table 22-68 Comparison Key FCCOB2 reserved New FPROT value FCCOB3 reserved New DFPROT value Table 22-68. Protection Override selection description Protection Update Selection code [1:0] bit 0 Protection register selection Update P-Flash protection 0 - keep unchanged (do not update) 1 - update P-Flash protection with new FPROT value loaded on FCCOB MC912ZVL Family Reference Manual, Rev. 2.48 668 NXP Semiconductors Flash Module (S12ZFTMRZ) Table 22-68. Protection Override selection description Protection Update Selection code [1:0] Protection register selection bit 1 Update EEPROM protection 0 - keep unchanged (do not update) 1 - update EEPROM protection with new DFPROT value loaded on FCCOB If the comparison key successfully matches the key programmed in the Flash Configuration Field the Protection Override command will preserve the current values of registers FPROT and DFPROT stored in an internal area and will override these registers as selected by the Protection Update Selection field with the value(s) loaded on FCCOB parameters. The new values loaded into FPROT and/or DFPROT can reconfigure protection without any restriction (by increasing, decreasing or disabling protection limits). If the command executes successfully the FPSTAT FPOVRD bit will set. If the comparison key does not match the key programmed in the Flash Configuration Field, or if the key loaded on FCCOB is 16’hFFFF, the value of registers FPROT and DFPROT will be restored to their original contents before executing the Protection Override command and the FPSTAT FPOVRD bit will be cleared. If the contents of the Protection Override Comparison Key in the Flash Configuration Field is left in the erased state (i.e. 16’hFFFF) the Protection Override feature is permanently disabled. If the command execution is flagged as an error (ACCERR being set for incorrect command launch) the values of FPROT and DFPROT will not be modified. The Protection Override command can be called multiple times and every time it is launched it will preserve the current values of registers FPROT and DFPROT in a single-entry buffer to be restored later; when the Protection Override command is launched to restore FPROT and DFPROT these registers will assume the values they had before executing the Protection Override command on the last time. If contents of FPROT and/or DFPROT registers were modified by direct register writes while protection is overridden these modifications will be lost. Running Protection Override command to restore the contents of registers FPROT and DFPROT will not force them to the reset values. Table 22-69. Protection Override Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != (001, 010 or 011) at command launch. Set if command not available in current mode (see Table 22-28). ACCERR Set if protection is supposed to be restored (if key does not match or is invalid) and Protection Override command was not run previously (bit FPSTAT FPOVRD is 0), so there are no previous valid values of FPROT and DFPROT to be re-loaded. Set if Protection Update Selection[1:0] = 00 (in case of CCOBIX[2:0] = 010 or 011) FSTAT Set if Protection Update Selection[1:0] = 00, CCOBIX[2:0] = 001 and a valid comparison key is loaded as a command parameter. FPVIOL None MGSTAT1 None MGSTAT0 None MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 669 Flash Module (S12ZFTMRZ) 22.4.8 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 22-70. Flash Interrupt Sources Interrupt Source Flash Command Complete ECC Single Bit Fault on Flash Read Global (CCR) Mask Interrupt Flag Local Enable CCIF (FSTAT register) CCIE (FCNFG register) I Bit SFDIF (FERSTAT register) SFDIE (FERCNFG register) I Bit NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 22.4.8.1 Description of Flash Interrupt Operation The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the Flash command interrupt request. The Flash module uses the SFDIF flag in combination with the SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed description of the register bits involved, refer to Section 22.3.2.5, “Flash Configuration Register (FCNFG)”, Section 22.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 22.3.2.7, “Flash Status Register (FSTAT)”, and Section 22.3.2.8, “Flash Error Status Register (FERSTAT)”. The logic used for generating the Flash module interrupts is shown in Figure 22-31. CCIE CCIF Flash Command Interrupt Request SFDIE SFDIF Flash Error Interrupt Request Figure 22-31. Flash Module Interrupts Implementation 22.4.9 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 22.4.8, “Interrupts”). MC912ZVL Family Reference Manual, Rev. 2.48 670 NXP Semiconductors Flash Module (S12ZFTMRZ) 22.4.10 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. 22.5 Security The Flash module provides security information to the MCU. The Flash security state is defined by the SEC bits of the FSEC register (see Table 22-10). During reset, the Flash module initializes the FSEC register using data read from the security byte of the Flash configuration field at global address 0xFF_FE0F. The security state out of reset can be permanently changed by programming the security byte assuming that the MCU is starting from a mode where the necessary P-Flash erase and program commands are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset. The following subsections describe these security-related subjects: • Unsecuring the MCU using Backdoor Key Access • Unsecuring the MCU in Special Single Chip Mode using BDM • Mode and Security Effects on Flash Command Availability 22.5.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0xFF_FE00-0xFF_FE07). If the KEYEN[1:0] bits are in the enabled state (see Section 22.3.2.2), the Verify Backdoor Access Key command (see Section 22.4.7.11) allows the user to present four prospective keys for comparison to the keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC register (see Table 22-10) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash memory and EEPROM memory will not be available for read access and will return invalid data. The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 22.3.2.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 22.4.7.11 2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10 The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method to re-enable the Verify Backdoor Access Key command. The security as defined in the Flash security byte (0xFF_FE0F) is not changed by using the Verify Backdoor Access Key command sequence. The backdoor MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 671 Flash Module (S12ZFTMRZ) keys stored in addresses 0xFF_FE00-0xFF_FE07 are unaffected by the Verify Backdoor Access Key command sequence. The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection register, FPROT. After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is unsecured, the sector containing the Flash security byte can be erased and the Flash security byte can be reprogrammed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0xFF_FE00-0xFF_FE07 in the Flash configuration field. 22.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM A secured MCU can be unsecured in special single chip mode using an automated procedure described in Section 22.4.7.7.1, “Erase All Pin”. 22.5.3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 22-28. 22.6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the Flash Block Configuration Parameters, the FPROT and DFPROT protection registers, and the FOPT and FSEC registers. The initialization routine reverts to built-in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence. If a double bit fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set. CCIF is cleared throughout the initialization sequence. The Flash module holds off all CPU access for a portion of the initialization sequence. Flash reads are allowed once the hold is removed. Completion of the initialization sequence is marked by setting CCIF high which enables user commands. If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC912ZVL Family Reference Manual, Rev. 2.48 672 NXP Semiconductors Appendix A MCU Electrical Specifications Table A-1. Revision History Table Revision Number Revision Date Description Of Changes 0.20 8 October 2014 • change Thermal Resistance data for 48pin LQFP packages based on the latest simulation results 0.21 7 January 2015 • specified parameter IBCTLMAX in Table B-1 0.22 8 April 2015 • removed stop current for 150C, added values for 85C,105C and 125C, Table A-16 • added operation condition for temperature option “C” and “V”, Table A-6 • specified parameter Analog Input Matching in Table F-1 • update LINPHY electrical parameter Appendix D, “LINPHY Electrical Specifications 0.23 16 April 2015 • minor updates based on review feedback 0.24 29 April 2015 • • • • 0.25 13 May 2015 • correct wrong ACMP and DAC Electricals supply range 0.30 03 June 2015 • Added section A.1.9, “ADC Calibration Configuration • Added Table A-11., “3.3V I/O Characteristics (Junction Temperature From –40C To +175C) 0.40 27 October 2015 • updated Thermal Package Characteristics for ZVL(A)128/96/64, Table A-9 0.41 16 February 2016 • added the latest characterization data, updated: Table A-11 Table A-19, Table A-21, Table A-9, Table A-9, Table F-1, Table J-1 0.50 14 March 2016 • added the latest characterization data, updated: Table A-11, Table A-19 • change voltage specification for MC9S12ZVL128/96/64 analog modules to VDDX3%: 0.60 31 March 2016 • update VBG output voltage and VBG voltage distribution specification: Table B-1 0.70 18 April 2016 • correct min VDDX specification for MC9S12ZVL128/96/64 device: Table B-1 0.80 20 June 2016 • update Table A-19, add missing stop current for 85C and 105C, correct stop value for 125C • update Table I-2, set ACMP input offset to 25mV added thermal package characteristics for ZVL128 device added current supply tables for ZVL128 devices added the Electrical Specification for new module DAC, ACMP, PGA added 3.3V Electrical Specification for DAC, BATS MC9S12ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 673 MCU Electrical Specifications Table A-1. Revision History Table A.1 Revision Number Revision Date 0.90 08 August 2017 1.0 12 September 2017 Description Of Changes • added 175C parameters • update current injection consideration, section Section C.1.1.4 Current Injection • added 175C Run and Wait current parameters 1.1 10 October 2017 • added Pin input leakage values for Pins PAD0 and PAD1 at 150C < TJ < 175C, Table A-10 • added Pin input leakage values for Pins PP1,PP3,PP5 and PP7 at 150C < TJ < 175C, Table A-10 • changed typical Reduced Performance Mode VDDX Voltage to 5.0V, Table B-1 1.2 19 October 2017 • correct max value for Input leakage current on PP1, PP3, PP5 and PP7 for 150C < TJ < 175C on Table A-10 1.21 24 October 2017 • fixed minor bug in this revision history to make sure all updates are correct documented 1.22 28 March 2018 • Added Note to Table A-6 item 7d • VSUP max 28.5V for 1h over lifetime. Changed Section Table A-6., “Operating Conditions • Added W Temperature Option to Appendix N, “Ordering Information" • Changed footnote 7 and 8 in Table B-1., “Voltage Regulator Electrical Characteristics". 1.23 29 March 2018 • Changed footnote 5 Table A-6 1.24 9 Jul 2018 1.25 23 Aug 2018 • Added items 7, 8, 9 and 10 to Table A-19 and Table A-18 • Changed item 1 Table A-6 VSUP min 3.5V 1.26 12 Nov 2018 • Removed items 7, 8, 9 and 10 from Table A-19 and Table A-18 • Added footnote 2 to Table A-19 and Table A-18 1.27 19 Nov 2018 • Corrected Footnote 1 in Table A-6 1.28 12 Dec 2018 • Corrected Footnote 1 in Table A-6 VSUP max 28.5V for 1h over lifetime. 1.29 18 Mar 2019 • Removed Note above Table E-3 • Added EXTXON and INTXON settings to Table A-14 • Added Thermal resistance data for 32QFN-EP to Table A-9 • Added , “Date Codes for fully trimmed ACLK Parts" General This supplement contains the most accurate electrical information for the MC9S12ZVL-Family available at the time of publication. This introduction is intended to give an overview on several common topics like power supply, current injection etc. MC912ZVL Family Reference Manual, Rev. 2.48 674 NXP Semiconductors MCU Electrical Specifications Table A-2. Power Supplies Mnemonic Nominal Voltage Description VSS 0V Ground pin for 1.8V core supply voltage generated by on chip voltage regulator VDDX 5.0 V 5V power supply output for I/O drivers generated by on chip voltage regulator if VREG5VEN is set VDDX 3.3 V 3.3V power supply output for I/O drivers generated by on chip voltage regulator if VREG5VEN is cleared VSSX1 0V Ground pin for I/O drivers VSSX2 0V Ground pin for I/O drivers VDDA 5.0 V 5V Power supply for the analog-to-digital converter and for the reference circuit of the internal voltage regulator if VREG5VEN is set VDDA 3.3 V 3.3V Power supply for the analog-to-digital converter and for the reference circuit of the internal voltage regulator if VREG5VEN is cleared VSSA 0V Ground pin for VDDA analog supply LGND 0V Ground pin for LIN physical interface VSUP 12V/18V External power supply for voltage regulator NOTE VDDA is connected to VDDX pins by diodes for ESD protection such that VDDX must not exceed VDDA by more than a diode voltage drop. VSSA and VSSX are connected by anti-parallel diodes for ESD protection. A.1.1 Pins There are 4 groups of functional pins. A.1.1.1 General Purpose I/O Pins (GPIO) The I/O pins have a level in the VDDX/VDDA range of 5V. This class of pins is comprised of all port I/O pins, BKGD and the RESET pins. A.1.1.2 High Voltage Pins These consist of the LIN and the BCTL pin. These pins are intended to interface to external components operating in the automotive battery range. They have nominal voltages above the standard 5V I/O voltage range. A.1.1.3 Oscillator If the external oscillator is enabled, the EXTAL and XTAL pins have an operating range of 1.8V. If the designated EXTAL and XTAL pins are configured for external oscillator operation then these pins have a nominal voltage of 1.8V. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 675 MCU Electrical Specifications A.1.1.4 TEST This pin is used for production testing only. The TEST pin must be tied to ground in all applications. A.1.2 Current Injection Power supply must maintain regulation within operating VDDX or VDD range during instantaneous and operating maximum current conditions. Figure A-1 shows a 5V GPIO pad driver and the on chip voltage regulator with VDDX output. It shows also the power and ground pins VSUP, VDDX, VSSX and VSSA. Px represents any 5V GPIO pin. Assume Px is configured as an input. The pad driver transistors P1 and N1 are switched off (high impedance). If the voltage Vin on Px is greater than VDDX a positive injection current Iin will flow through diode D1 into VDDX node. If this injection current Iin is greater than ILoad, the internal power supply VDDX may go out of regulation. Ensure the external VDDX load will shunt current greater than maximum injection current. This is the greatest risk when the MCU is not consuming power; e.g., if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. Figure A-1. Current Injection on GPIO Port if Vin > VDDX VSUP Voltage Regulator VBG + _ ISUP P2 Pad Driver IDDX VDDX ILoad C Load Iin P1 D1 Iin N1 Px Vin > VDDX VSSX VSSA MC912ZVL Family Reference Manual, Rev. 2.48 676 NXP Semiconductors MCU Electrical Specifications A.1.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation outside these ranges is not guaranteed. Stress beyond these limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level. Table A-3. Absolute Maximum Ratings1 Num 1 2 3 4 5 6 Rating Symbol Min Max Unit 1 Voltage regulator and LINPHY supply voltage VSUP -0.3 42 V 2 DC voltage on LIN VLIN -32 42 V 3 Voltage Regulator Ballast Connection VBCTL -0.3 42 V 4 Supplies VDDA, VDDX VVDDACX -0.3 6 V 5 Voltage difference VDDX to VDDA2 VDDX –0.3 0.3 V 6 Voltage difference VSSX to VSSA VSSX –0.3 0.3 V 7 Digital I/O input voltage VIN –0.3 6.0 V 8 HVI PL0 input voltage VLx –27 42.0 V 9 EXTAL, XTAL 3 VILV –0.3 2.16 V 10 TEST input VTEST –0.3 10.0 V 11 Instantaneous maximum current Single pin limit for all digital I/O pins4 I –25 +25 mA 12 Continuous current on LIN ILIN ± 200 5 mA 13 Instantaneous maximum current on PP7 IPP7 –80 +25 mA 14 Instantaneous maximum current on PP1, PP36 and PP56 IPP135 –30 +80 mA 15 Instantaneous maximum current Single pin limit for EXTAL, XTAL IDL –25 +25 mA 16 Storage temperature range T –65 155 C D stg Beyond absolute maximum ratings device might be damaged. VDDX and VDDA must be shorted EXTAL, XTAL pins configured for external oscillator operation only All digital I/O pins are internally clamped to VSSX and VDDX, or VSSA and VDDA. The current on the LIN pin is internally limited. Therefore, it should not be possible to reach the 200mA anyway. only applicable for PP3 and PP5 if pin VSSX2 is available A.1.4 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade integrated circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM) and the Charged-Device Model. MC912ZVL Family Reference Manual, Rev. 2.48 NXP Semiconductors 677 MCU Electrical Specifications A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-4. ESD and Latch-up Test Conditions Model Human Body ChargedDevice Spec Description JESD22-A114 JESD22-C101 Symbol Value Unit Series Resistance R 1500  Storage Capacitance C 100 pF Number of Pulse per pin positive negative - 1 1 Series Resistance R 0  Storage Capacitance C 4 pF Latch-up for 5V GPIO’s Minimum Input Voltage Limit -2.5 V Maximum Input Voltage Limit +7.5 V Latch-up for LIN Minimum Input Voltage Limit -7 V Maximum Input Voltage Limit +27 V Max Unit - KV Table A-5. ESD Protection and Latch-up Characteristics Num Symbol Min Human Body Model (HBM): -LIN vs LGND -PL0 -all other pins VHBM VHBM VHBM +/-6 +/-4 +/-2 2 Charged-Device Model (CDM): Corner Pins VCDM +/-750 - V 3 Charged-Device Model (CDM): all other pins VCDM +/-500 - V 4 Direct Contact Discharge IEC61000-4-2 with and with out 220pF capacitor (R=330, C=150pF): LIN vs LGND VESDIEC +/-6 - KV Latch-up Current of 5V GPIO’s at T=125C positive negative ILAT +100 -100 - mA Latch-up Current at 27C positive negative ILAT +200 -200 - mA 1 5 6 Rating MC912ZVL Family Reference Manual, Rev. 2.48 678 NXP Semiconductors MCU Electrical Specifications A.1.5 Operating Conditions This section describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE Please refer to the temperature rating of the device with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.6, “Power Dissipation and Thermal Characteristics”. Table A-6. Operating Conditions Num 3 4 5 Min Typ Max Unit Voltage regulator and LINPHY supply voltage VSUP 3.5 12 401 V 2 Voltage difference VDDX to VDDA VDDX -0.1 — 0.1 V 3 Voltage difference VSSX to VSSA VSSX -0.3 — 0.3 V 4 Oscillator fosc 4 — 20 MHz fbus 3 — 32 25 MHz fWSTAT — — 25 MHz 6 2 Symbol 1 5 1 Rating 2 Bus frequency TJ  150C 150C < TJ < 175C (option W only) Bus frequency without wait states 7a Operating junction temperature range Operating ambient temperature range4 (option C) TJ TA –40 –40 — — 105 85 C 7b Operating junction temperature range Operating ambient temperature range4 (option V) TJ TA –40 –40 — — 125 105 C 7c Operating junction temperature range Operating ambient temperature range4 (option M) TJ TA –40 –40 — — 150 125 C 7d5 Operating junction temperature range Operating ambient temperature range4 (option W) T J TA –40 –40 — — 175 150 C Normal operating range is 5.5 V - 18 V. Continuous operation at 40 V is not allowed. Only Transient Conditions (Load Dump) single pulse tmax