SAF7118EH/V1/G,557

SAF7118 Multistandard video decoder with adaptive comb filter and component video input Rev. 04 — 4 July 2008 Product data sheet 1. General description The SAF7118 is a video capture device that, due to its improved comb filter performance, is suitable for various applications such as in-car video reception, in-car entertainment or in-car navigation. The SAF7118 is a combination of a four-channel analog preprocessing circuit including source selection, anti-aliasing filter and Analog-to-Digital Converter (ADC) with succeeding decimation filters from 27 MHz to 13.5 MHz data rate. Each preprocessing channel comes with an automatic clamp and gain control. The SAF7118 combines a Clock Generation Circuit (CGC), a digital multistandard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and downscaling and a brightness, contrast and saturation control circuit. It is a highly integrated circuit for desktop video and similar applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the color of PAL, SECAM and NTSC signals into ITU 601 compatible color component values. The SAF7118 accepts CVBS or S-video (Y/C) as analog inputs from TV or VCR sources, including weak and distorted signals as well as baseband component signals Y-PB-PR or RGB. An expansion port (X port) for digital video (bidirectional half duplex, D1 compatible) is also supported to connect to MPEG or a video phone codec. At the so called image port (I port) the SAF7118 supports 8-bit or 16-bit wide output data with auxiliary reference data for interfacing to VGA controllers. The target application for the SAF7118 is to capture and scale video images, to be provided as a digital video stream through the image port of a VGA controller, for capture to system memory, or just to provide digital baseband video to any picture improvement processing. The SAF7118 also provides a means for capturing the serially coded data in the Vertical Blanking Interval (VBI) data. Two principal functions are available: 1. To capture raw video samples, after interpolation to the required output data rate, via the scaler 2. A versatile data slicer (data recovery) unit The SAF7118 also incorporates field-locked audio clock generation. This function ensures that there is always the same number of audio samples associated with a field, or a set of fields. This prevents the loss of synchronization between video and audio during capture or playback. All of the ADCs may be used to digitize a Vestigial Side Band (VSB) signal for subsequent decoding; a dedicated output port and a selectable VSB clock input is provided. SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter The circuit is I2C-bus controlled (full write/read capability for all programming registers, bit rate up to 400 kbit/s). 2. Features 2.1 Video acquisition/clock n Up to sixteen analog CVBS, split as desired (all of the CVBS inputs optionally can be used to convert e.g. VSB signals) n Up to eight analog Y + C inputs, split as desired n Up to four analog component inputs, with embedded or separate sync, split as desired n Four on-chip anti-aliasing filters in front of the ADCs n Automatic Clamp Control (ACC) for CVBS, Y and C (or VSB) and component signals n Switchable white peak control n Four 9-bit low noise CMOS ADCs running at twice the oversampling rate (27 MHz) n Fully programmable static gain or Automatic Gain Control (AGC), matching to the particular signal properties n On-chip line-locked clock generation in accordance with “ITU 601” n Requires only one crystal (32.11 MHz or 24.576 MHz) for all standards n Horizontal and vertical sync detection 2.2 Video decoder n Digital Phase-Locked Loop (PLL) for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade VTR n Automatic detection of any supported color standard n Luminance and chrominance signal processing for PAL B, G, D, H, I and N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM n Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation, also with VTR signals u Increased luminance and chrominance bandwidth for all PAL and NTSC standards u Reduced cross color and cross luminance artefacts n PAL delay line for correcting PAL phase errors n Brightness Contrast Saturation (BCS) adjustment, separately for composite and baseband signals n User programmable sharpness control n Detection of copy-protected signals according to the Macrovision standard, indicating level of protection n Independent gain and offset adjustment for raw data path 2.3 Component video processing n n n n RGB component inputs Y-PB-PR component inputs Fast blanking between CVBS and synchronous component inputs Digital RGB to Y-CB-CR matrix SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 2 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 2.4 Video scaler n Horizontal and vertical downscaling and upscaling to randomly sized windows n Horizontal and vertical scaling range: variable zoom to 1⁄64 (icon) (it should be noted that the H and V zoom are restricted by the transfer data rates) n Anti-alias and accumulating filter for horizontal scaling n Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing (6-bit phase accuracy) n Horizontal phase correct up and downscaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width) n Two independent programming sets for scaler part, to define two ‘ranges’ per field or sequences over frames n Fieldwise switching between decoder part and expansion port (X port) input n Brightness, contrast and saturation controls for scaled outputs 2.5 VBI data decoder and slicer n Versatile VBI data decoder, slicer, clock regeneration and byte synchronization e.g. for World Standard Teletext (WST), North American Broadcast Text System (NABTS), closed caption, Wide Screen Signalling (WSS), etc. 2.6 Audio clock generation n Generation of a field-locked audio master clock to support a constant number of audio clocks per video field n Generation of an audio serial and left/right (channel) clock signal 2.7 Digital I/O interfaces n Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status information supporting RTC level 3.1 (refer to document “RTC Functional Specification” for details) n Bidirectional expansion port (X port) with half duplex functionality (D1), 8-bit Y-CB-CR: u Output from decoder part, real-time and unscaled u Input to scaler part, e.g. video from MPEG decoder (extension to 16-bit possible) n Video image port (I port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own clock), or slave mode (external clock), with auxiliary timing and handshake signals n Discontinuous data streams supported n 32-word × 4-byte FIFO register for video output data n 28-word × 4-byte FIFO register for decoded VBI data output n Scaled 4 : 2 : 2, 4 : 1 : 1, 4 : 2 : 0, 4 : 1 : 0 Y-CB-CR output n Scaled 8-bit luminance only and raw CVBS data output n Sliced, decoded VBI data output 2.8 Miscellaneous n Power-on control n 5 V tolerant digital inputs and I/O ports SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 3 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter n Software controlled power saving standby modes supported n Programming via serial I2C-bus, full read back ability by an external controller, bit rate up to 400 kbit/s n Boundary scan test circuit complies with the “IEEE Std. 1149.b1 - 1994”. 3. Applications n n n n General industrial video applications In-car TV reception In-car entertainment In-car navigation platforms 4. Quick reference data Table 1. Quick reference data Symbol Parameter Min Typ Max Unit VDDD digital supply voltage 3.0 3.3 3.6 V VDDA analog supply voltage 3.1 3.3 3.5 V Tamb ambient temperature −40 - +85 °C - 1105 1350 mW Ptot(A+D) [1] Conditions total power dissipation analog and digital part component mode [1] 8-bit image port output mode, expansion port is 3-stated. 5. Ordering information Table 2. Ordering information Type number Package Name Description Version SAF7118EH HBGA156 plastic thermal enhanced ball grid array package; 156 balls; body 15 × 15 × 1.15 mm; heatsink SOT807-1 SAF7118H QFP160 plastic quad flat package; 160 leads (lead length 1.6 mm); body 28 × 28 × 3.4 mm; high stand-off height SOT322-2 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 4 of 175 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x AD PORT DNC0 to DNC20 CONTROL SDA I2C-BUS REGISTER MAP CR ANALOG INPUT CONTROL RAW CB C CR COMB FILTER Y S ANALOG4 and ADC4 CHROMINANCE PROCESSING LUMINANCE PROCESSING S Y-CB-CR SAF7118 Y S S ICLK IDQ ITRDY ITRI VBI DATA SLICER SYNCHRONIZATION CB-CR CB-CR VIDEO/TEXT ARBITER Y-CB-CR, S POWER-ON CONTROL POWER SUPPLY VSSD VDDA Block diagram VIDEO CLOCK GPO CRYSTAL X PORT H PORT AUDIO CLOCK BOUNDARY SCAN VDD(xtal) LLC2 RTS0 RTCO XTALI XRDY XCLK AMXCLK ALRCLK TDO TMS XRH XTRI TRST VSS(xtal) VDDD LLC mbl751 RTS1 XTALO XTOUT XPD[7:0] XDQ AMCLK ASCLK TDI TCK HPD[7:0] XRV SAF7118 5 of 175 © NXP B.V. 2008. All rights reserved. VSSA Fig 1. IGP1 IGP0 IGPV IGPH IPD[7:0] S AOUT AGNDA TEXT FIFO RAW Y-CB-CR OUTPUT FORMATTER I PORT ANALOG3 and ADC3 COMPONENTS PROCESSING VIDEO FIFO AI31 AI32 AI33 AI34 AI3D B VERTICAL SCALING HORIZONTAL FINE (PHASE) SCALING ANALOG2 and ADC2 G SCALER EVENT CONTROLLER Y CB FIR PREFILTER PRESCALER BCS SCALER AI21 AI22 AI23 AI24 AI2D FAST SWITCH DELAY R DECODER OUTPUT CONTROL ANALOG1 and ADC1 Multistandard video decoder with adaptive comb filter Rev. 04 — 4 July 2008 AI11 AI12 AI13 AI14 AI1D AGND INT_A SECOND TASK I2C-BUS REGISTER MAP SCALER FSW AI41 AI42 AI43 AI44 AI4D SCL FIRST TASK I2C-BUS REGISTER MAP SCALER LINE FIFO BUFFER EXMCLR CE NXP Semiconductors CLKEXT 6. Block diagram SAF7118_4 Product data sheet RES ADP[8:0] SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 7. Pinning information 7.1 Pinning ball A1 index area A B C D E F G H J K L M N P 121 160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 120 SAF7118H 80 81 41 40 001aae326 SAF7118EH 001aab338 Transparent top view Fig 2. Pin configuration (QFP160) Table 3. Fig 3. Pin allocation table Pin Symbol Pin Symbol Pin Symbol Pin Symbol A2 XTOUT A3 XTALO A4 VSS(xtal) A5 TDO A6 XRDY A7 XCLK A8 XPD0 A9 XPD2 A10 XPD4 A11 XPD6 A12 DNC5 A13 DNC3 B1 AI41 B2 DNC6 B3 VDD(xtal) B4 XTALI B5 TDI B6 TCK B7 XDQ B8 XPD1 B9 XPD3 B10 XPD5 B11 XTRI B12 DNC4 B13 DNC7 B14 DNC8 C1 VSSA4 C2 AGND C3 DNC9 C4 DNC10 C5 VDDD13 C6 TRST C7 XRH C8 VDDD12 C9 VDDD11 C10 VDDD10 C11 XPD7 C12 DNC11 C13 DNC12 C14 DNC2 D1 AI43 D2 AI42 D3 AI4D D4 VDDA4 D5 VSSD13 D6 TMS D7 VSSD12 D8 XRV D9 VSSD11 D10 VSSD10 D11 VSSD9 D12 VDDD9 D13 DNC1 D14 HPD0 E1 E2 E3 E4 E11 HPD1 E12 HPD3 F2 AI31 VSSA3 AI44 E14 HPD4 F1 F3 F4 F11 VSSD8 F12 VDDD8 G2 AI33 VDDA3 AI3D VDDA4A E13 HPD2 F14 HPD6 G1 G3 G4 G11 VSSD7 G12 IPD1 H2 AI22 AI21 AI34 AI32 F13 HPD5 G13 HPD7 G14 IPD0 H1 H3 H4 H11 IPD2 VSSA2 VDDA2 SAF7118_4 Product data sheet Pin configuration (HBGA156) AI2D VDDA3A AI23 H12 VDDD7 © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 6 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 3. Pin Pin allocation table …continued Pin Symbol Pin Symbol H13 IPD4 Symbol H14 IPD3 Pin Symbol J1 VDDA2A J2 AI11 J3 AI24 J4 VSSA1 J11 VSSD6 J12 VDDD6 J13 IPD6 J14 IPD5 K1 AI12 K2 AI13 K3 AI1D K4 VDDA1 K11 IPD7 K12 IGPH K13 IGP1 K14 IGPV L1 VDDA1A L2 AGNDA L3 AI14 L4 VSSD1 L5 VSSD2 L6 ADP6 L7 ADP3 L8 VSSD3 L9 VSSD4 L10 RTCO L11 VSSD5 L12 ITRI L13 IDQ L14 IGP0 M1 AOUT M2 VSSA0 M3 VDDA0 M4 VDDD1 M5 VDDD2 M6 ADP7 M7 ADP2 M8 VDDD3 M9 VDDD4 M10 RTS0 M11 VDDD5 M12 AMXCLK M13 FSW M14 ICLK N1 DNC13 N2 DNC14 N3 DNC15 N4 CE N5 LLC2 N6 CLKEXT N7 ADP5 N8 ADP0 N9 SCL N10 RTS1 N11 ASCLK N12 ITRDY N13 DNC16 N14 DNC17 P2 DNC18 P3 EXMCLR P4 LLC P5 RES P6 ADP8 P7 ADP4 P8 ADP1 P9 INT_A P10 SDA P11 AMCLK P12 ALRCLK P13 DNC0 7.2 Pin description Table 4. Symbol Pin description Pin Type[1] Description QFP160 HBGA156 DNC6 1 B2 O do not connect, reserved for future extensions and for testing AI41 2 B1 I analog input 41 AGND 3 C2 P analog ground VSSA4 4 C1 P ground for analog inputs AI4x AI42 5 D2 I analog input 42 AI4D 6 D3 I differential input for ADC channel 4 (pins AI41 to AI44) AI43 7 D1 I analog input 43 VDDA4 8 D4 P analog supply voltage for analog inputs AI4x (3.3 V) VDDA4A 9 E2 P analog supply voltage for analog inputs AI4x (3.3 V) AI44 10 E1 I analog input 44 AI31 11 E3 I analog input 31 VSSA3 12 E4 P ground for analog inputs AI3x AI32 13 F2 I analog input 32 AI3D 14 F1 I differential input for ADC channel 3 (pins AI31 to AI34) AI33 15 F3 I analog input 33 VDDA3 16 F4 P analog supply voltage for analog inputs AI3x (3.3 V) VDDA3A 17 G2 P analog supply voltage for analog inputs AI3x (3.3 V) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 7 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 4. Symbol Pin description …continued Pin Type[1] Description QFP160 HBGA156 AI34 18 G1 I analog input 34 AI21 19 G4 I analog input 21 VSSA2 20 H3 P ground for analog inputs AI2x AI22 21 G3 I analog input 22 AI2D 22 H1 I differential input for ADC channel 2 (pins AI24 to AI21) AI23 23 H2 I analog input 23 VDDA2 24 H4 P analog supply voltage for analog inputs AI2x (3.3 V) VDDA2A 25 J1 P analog supply voltage for analog inputs AI2x (3.3 V) AI24 26 J3 I analog input 24 AI11 27 J2 I analog input 11 VSSA1 28 J4 P ground for analog inputs AI1x AI12 29 K1 I analog input 12 AI1D 30 K3 I differential input for ADC channel 1 (pins AI14 to AI11) AI13 31 K2 I analog input 13 VDDA1 32 K4 P analog supply voltage for analog inputs AI1x (3.3 V) VDDA1A 33 L1 P analog supply voltage for analog inputs AI1x (3.3 V) AI14 34 L3 I analog input 14 AGNDA 35 L2 P analog signal ground AOUT 36 M1 O analog test output (do not connect) VDDA0 37 M3 P analog supply voltage (3.3 V) for internal clock generation circuit VSSA0 38 M2 P ground for internal Clock Generation Circuit (CGC) DNC13 39 N1 NC do not connect, reserved for future extensions and for testing DNC14 40 N2 I/pu do not connect, reserved for future extensions and for testing DNC18 41 P2 I/O do not connect, reserved for future extensions and for testing DNC15 42 N3 I/pd do not connect, reserved for future extensions and for testing EXMCLR 43 P3 I/pd external mode clear (with internal pull-down) CE 44 N4 I/pu Chip Enable (CE) or reset input (with internal pull-up) VDDD1 45 M4 P digital supply voltage 1 (peripheral cells) LLC 46 P4 O line-locked system clock output (27 MHz nominal) VSSD1 47 L4 P digital ground 1 (peripheral cells) LLC2 48 N5 O line-locked 1⁄2 clock output (13.5 MHz nominal) RES 49 P5 O reset output (active LOW) VDDD2 50 M5 P digital supply voltage 2 (core) VSSD2 51 L5 P digital ground 2 (core; substrate connection) CLKEXT 52 N6 I external clock input intended for analog-to-digital conversion of VSB signals (36 MHz) ADP8 53 P6 O MSB of direct analog-to-digital converted output data (VSB) ADP7 54 M6 O MSB − 1 of direct analog-to-digital converted output data (VSB) ADP6 55 L6 O MSB − 2 of direct analog-to-digital converted output data (VSB) ADP5 56 N7 O MSB − 3 of direct analog-to-digital converted output data (VSB) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 8 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 4. Symbol Pin description …continued Pin Type[1] Description QFP160 HBGA156 ADP4 57 P7 O MSB − 4 of direct analog-to-digital converted output data (VSB) ADP3 58 L7 O MSB − 5 of direct analog-to-digital converted output data (VSB) VDDD3 59 M8 P digital supply voltage 3 (peripheral cells) ADP2 60 M7 O MSB − 6 of direct analog-to-digital converted output data (VSB) ADP1 61 P8 O MSB − 7 of direct analog-to-digital converted output data (VSB) ADP0 62 N8 O LSB of direct analog-to-digital converted output data (VSB) VSSD3 63 L8 P digital ground 3 (peripheral cells) INT_A 64 P9 O/od I2C-bus interrupt flag (LOW if any enabled status bit has changed) VDDD4 65 M9 P digital supply voltage 4 (core) SCL 66 N9 I(/O) serial clock input (I2C-bus) with inactive output path VSSD4 67 L9 P digital ground 4 (core) SDA 68 P10 I/O/od serial data input/output (I2C-bus) RTS0 69 M10 O real-time status or sync information, controlled by subaddresses 11h and 12h; see Section 10.2.18 and Section 10.2.19 RTS1 70 N10 O real-time status or sync information, controlled by subaddresses 11h and 12h; see Section 10.2.18 and Section 10.2.19 RTCO 71 L10 O/st/pd real-time control output; contains information about actual system clock frequency, field rate, odd/even sequence, decoder status, subcarrier frequency and phase and PAL sequence (see document “RTC Functional Description”, available on request); the RTCO pin is enabled via I2C-bus bit RTCE; see Table 35[2][3] AMCLK 72 P11 O audio master clock output, up to 50 % of crystal clock VDDD5 73 M11 P digital supply voltage 5 (peripheral cells) ASCLK 74 N11 O audio serial clock output ALRCLK 75 P12 O/st/pd audio left/right clock output; can be strapped to supply via a 3.3 kΩ resistor to indicate that the default 24.576 MHz crystal (pin ALRCLK = LOW; internal pull-down) has been replaced by a 32.110 MHz crystal (pin ALRCLK = HIGH)[2][4] AMXCLK 76 M12 I audio master external clock input ITRDY 77 N12 I/pu target ready input for image port data DNC0 78 P13 I/pu do not connect, reserved for future extensions and for testing: scan input DNC16 79 N13 NC do not connect, reserved for future extensions and for testing DNC17 80 N14 NC do not connect, reserved for future extensions and for testing DNC19 81 - NC do not connect, reserved for future extensions and for testing DNC20 82 - NC do not connect, reserved for future extensions and for testing FSW 83 M13 I/pd fast switch (blanking) with internal pull-down inserts component inputs into CVBS signal ICLK 84 M14 I/O clock output signal for image port, or optional asynchronous back-end clock input IDQ 85 L13 O output data qualifier for image port (optional: gated clock output) ITRI 86 L12 I(/O) image port output control signal, affects all input port pins inclusive ICLK, enable and active polarity is under software control (bits IPE in subaddress 87h); output path used for testing: scan output SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 9 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 4. Symbol IGP0 Pin description …continued Pin QFP160 HBGA156 87 L14 Type[1] Description O general purpose output signal 0; image port (controlled by subaddresses 84h and 85h) VSSD5 88 L11 P digital ground 5 (peripheral cells) IGP1 89 K13 O general purpose output signal 1; image port (controlled by subaddresses 84h and 85h) IGPV 90 K14 O multi purpose vertical reference output signal; image port (controlled by subaddresses 84h and 85h) IGPH 91 K12 O multi purpose horizontal reference output signal; image port (controlled by subaddresses 84h and 85h) IPD7 92 K11 O MSB of image port data output IPD6 93 J13 O MSB − 1 of image port data output IPD5 94 J14 O MSB − 2 of image port data output VDDD6 95 J12 P digital supply voltage 6 (core) VSSD6 96 J11 P digital ground 6 (core) IPD4 97 H13 O MSB − 3 of image port data output IPD3 98 H14 O MSB − 4 of image port data output IPD2 99 H11 O MSB − 5 of image port data output IPD1 100 G12 O MSB − 6 of image port data output VDDD7 101 H12 P digital supply voltage 7 (peripheral cells) IPD0 102 G14 O LSB of image port data output HPD7 103 G13 I/O MSB of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port VSSD7 104 G11 P digital ground 7 (peripheral cells) HPD6 105 F14 I/O MSB − 1 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port VDDD8 106 F12 P digital supply voltage 8 (core) HPD5 107 F13 I/O MSB − 2 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port VSSD8 108 F11 P digital ground 8 (core) HPD4 109 E14 I/O MSB − 3 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port HPD3 110 E12 I/O MSB − 4 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port HPD2 111 E13 I/O MSB − 5 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port HPD1 112 E11 I/O MSB − 6 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port HPD0 113 D14 I/O LSB of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port VDDD9 114 D12 P digital supply voltage 9 (peripheral cells) DNC1 115 D13 I/pu do not connect, reserved for future extensions and for testing: scan input DNC2 116 C14 I/pu do not connect, reserved for future extensions and for testing: scan input SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 10 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 4. Symbol Pin description …continued Pin Type[1] Description QFP160 HBGA156 DNC7 117 B13 NC do not connect, reserved for future extensions and for testing DNC8 118 B14 NC do not connect, reserved for future extensions and for testing DNC11 119 C12 NC do not connect, reserved for future extensions and for testing DNC12 120 C13 NC do not connect, reserved for future extensions and for testing DNC21 121 - NC do not connect, reserved for future extensions and for testing DNC22 122 - NC do not connect, reserved for future extensions and for testing DNC3 123 A13 I/pu do not connect, reserved for future extensions and for testing: scan input DNC4 124 B12 O do not connect, reserved for future extensions and for testing: scan output DNC5 125 A12 I/pu do not connect, reserved for future extensions and for testing: scan input XTRI 126 B11 I X port output control signal, affects all X port pins (XPD7 to XPD0, XRH, XRV, XDQ and XCLK), enable and active polarity is under software control (bits XPE in subaddress 83h) XPD7 127 C11 I/O MSB of expansion port data XPD6 128 A11 I/O MSB − 1 of expansion port data VSSD9 129 D11 P digital ground 9 (peripheral cells) XPD5 130 B10 I/O MSB − 2 of expansion port data XPD4 131 A10 I/O MSB − 3 of expansion port data VDDD10 132 C10 P digital supply voltage 10 (core) VSSD10 133 D10 P digital ground 10 (core) XPD3 134 B9 I/O MSB − 4 of expansion port data XPD2 135 A9 I/O MSB − 5 of expansion port data VDDD11 136 C9 P digital supply voltage 11 (peripheral cells) VSSD11 137 D9 P digital ground 11 (peripheral cells) XPD1 138 B8 I/O MSB − 6 of expansion port data XPD0 139 A8 I/O LSB of expansion port data XRV 140 D8 I/O vertical reference I/O expansion port XRH 141 C7 I/O horizontal reference I/O expansion port VDDD12 142 C8 P digital supply voltage 12 (core) XCLK 143 A7 I/O clock I/O expansion port XDQ 144 B7 I/O data qualifier for expansion port VSSD12 145 D7 P digital ground 12 (core) XRDY 146 A6 O task flag or ready signal from scaler, controlled by XRQT TRST 147 C6 I/pu test reset input (active LOW), for boundary scan test (with internal pull-up)[5][6][7] TCK 148 B6 I/pu test clock for boundary scan test[5] TMS 149 D6 I/pu test mode select input for boundary scan test or scan test[5] TDO 150 A5 O test data output for boundary scan test[5] VDDD13 151 C5 P digital supply voltage 13 (peripheral cells) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 11 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 4. Symbol Pin description …continued Pin Type[1] Description QFP160 HBGA156 TDI 152 B5 I/pu test data input for boundary scan test[5] VSSD13 153 D5 P digital ground 13 (peripheral cells) VSS(xtal) 154 A4 P ground for crystal oscillator XTALI 155 B4 I input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection of external oscillator with TTL compatible square wave clock signal XTALO 156 A3 O 24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL clock input of XTALI is used VDD(xtal) 157 B3 P supply voltage for crystal oscillator XTOUT 158 A2 O crystal oscillator output signal; auxiliary signal DNC9 159 C3 NC do not connect, reserved for future extensions and for testing DNC10 160 C4 NC do not connect, reserved for future extensions and for testing [1] I = input, O = output, P = power, NC = not connected, st = strapping, pu = pull-up, pd = pull-down, od = open-drain. [2] Pin strapping is done by connecting the pin to the supply via a 3.3 kΩ resistor. During the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping resistor is necessary (internal pull-down). [3] Pin RTCO operates as I2C-bus slave address pin; RTCO = 0 slave address 42h/43h (default); RTCO = 1 slave address 40h/41h. [4] Pin ALRCLK = LOW for 24.576 MHz crystal (default); pin ALRCLK = HIGH for 32.110 MHz crystal. [5] In accordance with the “IEEE1149.1” standard the pads TDI, TMS, TCK and TRST are input pads with an internal pull-up transistor and TDO is a 3-state output pad. [6] For board design without boundary scan implementation connect the TRST pin to ground. [7] This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 12 of 175 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin[1] NXP Semiconductors SAF7118_4 Product data sheet Table 5. 8-bit/16-bit and alternative pin function configurations Symbol Input 8-bit input modes Output I/O configuration programming bits 8-bit output modes 16-bit output modes (only for I2C-bus programming) Alternative output functions XPD7 to D1 data C11, A11, B10, input A10, B9, A9, B8, A8 XPD0 (127, 128, 130, 131, 134, 135, 138, 139) Y data input - D1 decoder output - - XCODE[92h[3]], XPE[1:0] 83h[1:0] + pin XTRI A7 (143) XCLK clock input - gated clock input decoder clock output - - XPE[1:0] 83h[1:0] + pin XTRI, XPCK[1:0] 83h[5:4], XCKS[92h[0]] B7 (144) XDQ data qualifier input - data qualifier output (HREF and VREF gate) - XDQ[92h[1]], XPE[1:0] 83h[1:0] + pin XTRI A6 (146) XRDY input ready output - active task A/B flag - - - XRQT[83h[2]], XPE[1:0] 83h[1:0] + pin XTRI C7 (141) XRH horizontal reference input - - decoder horizontal reference output - XDH[92h[2]], XPE[1:0] 83h[1:0] + pin XTRI D8 (140) XRV vertical reference input - - decoder vertical reference output - XDV[1:0] 92h[5:4], XPE[1:0] 83h[1:0] + pin XTRI B11 (126) XTRI output enable input - - - - - XPE[1:0] 83h[1:0] HPD7 to G13, F14, F13, HPD0 E14, E12, E13, E11, D14 (103, 105, 107, 109 to 113) CB-CR data input - - CB-CR scaler output - ICODE[93h[7]], ISWP[1:0] 85h[7:6], I8_16[93h[6]], IPE[1:0] 87h[1:0] + pin ITRI K11, J13, J14, H13, IPD7 to IPD0 H14, H11, G12, G14 (92 to 94, 97 to 99, 100, 102) - - - D1 scaler output Y scaler output - ICODE[93h[7]], ISWP[1:0] 85h[7:6], I8_16[93h[6]], IPE[1:0] 87h[1:0] + pin ITRI M14 (84) ICLK - - - clock output - clock input ICKS[1:0] 80h[1:0], IPE[1:0] 87h[1:0] + pin ITRI L13 (85) IDQ - - - data qualifier output - gated clock output ICKS[3:2] 80h[3:2], IDQP[85h[0]], IPE[1:0] 87h[1:0] + pin ITRI SAF7118 13 of 175 © NXP B.V. 2008. All rights reserved. Alternative input functions Multistandard video decoder with adaptive comb filter Rev. 04 — 4 July 2008 16-bit input modes (only for I2C-bus programming) xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin[1] 8-bit/16-bit and alternative pin function configurations …continued Symbol Input Output 8-bit input modes 16-bit input modes (only for I2C-bus programming) Alternative input functions 8-bit output modes 16-bit output modes (only for I2C-bus programming) Alternative output functions I/O configuration programming bits ITRDY - - - target ready input - - - K12 (91) IGPH - - - H gate output - extended H gate, horizontal pulses IDH[1:0] 84h[1:0], IRHP[85h[1]], IPE[1:0] 87h[1:0] + pin ITRI K14 (90) IGPV - - - V gate output - V-sync, IDV[1:0] 84h[3:2], vertical pulses IRVP[85h[2]], IPE[1:0] 87h[1:0] + pin ITRI K13 (89) IGP1 - - - general purpose - - IDG1[1:0] 84h[5:4], IG1P[85h[3]], IPE[1:0] 87h[1:0] + pin ITRI L14 (87) IGP0 - - - general purpose - - IDG0[1:0] 84h[7:6], IG0P[85h[4]], IPE[1:0] 87h[1:0] + pin ITRI L12 (86) ITRI - - - output enable input - - [1] Pin numbers for QFP160 in parenthesis. SAF7118 14 of 175 © NXP B.V. 2008. All rights reserved. Multistandard video decoder with adaptive comb filter Rev. 04 — 4 July 2008 N12 (77) - NXP Semiconductors SAF7118_4 Product data sheet Table 5. SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8. Functional description 8.1 Decoder 8.1.1 Analog input processing The SAF7118 offers sixteen analog signal inputs, four analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit CMOS ADC with a Decimation Filter (DF); see Figure 5 and Figure 6. The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. The characteristic is shown in Figure 4. During the vertical blanking period gain and clamping control are frozen. mgd138 6 V 0 (dB) −6 −12 −18 −24 −30 −36 −42 0 2 4 6 8 10 12 14 f (MHz) Fig 4. Anti-alias filter mbl753 6 G (dB) 0 −6 −12 −18 −24 −30 −36 −42 −48 0 2 4 6 8 10 12 14 f (MHz) Fig 5. Decimation filter SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 15 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter TEST SELECTOR AND BUFFER AOUT DIGITAL TEST SELECTOR AOSL[2:0] AI44 AI43 AI42 AI41 AI4D SOURCE SWITCH ANALOG AMPLIFIER DAC9 CLAMP CIRCUIT ANTI-ALIAS FILTER ADP[8:0] DOSL[1:0] ADPE BYPASS SWITCH ADC4 FUSE[1:0] AI34 AI33 AI32 AI31 AI3D SOURCE SWITCH ANALOG AMPLIFIER DAC9 CLAMP CIRCUIT ANTI-ALIAS FILTER BYPASS SWITCH ADC3 FUSE[1:0] AI24 AI23 AI22 AI21 AI2D SOURCE SWITCH ANALOG AMPLIFIER DAC9 CLAMP CIRCUIT ANTI-ALIAS FILTER BYPASS SWITCH ADC2 FUSE[1:0] AI14 AI13 AI12 AI11 AI1D ANALOG AMPLIFIER DAC9 CLAMP CIRCUIT SOURCE SWITCH ANTI-ALIAS FILTER BYPASS SWITCH ADC1 FUSE[1:0] MODE CONTROL CLAMP CONTROL GAIN CONTROL GLIMB HSY GLIMT WIPA SLTCA MODE[5:0] ANTI-ALIAS CONTROL HOLDG GAFIX WPOFF GUDL[1:0] GAI[48:40] GAI[38:30] HLNRS UPTCV REFA VERTICAL BLANKING CONTROL VBSL 9 9 9 9 DF DF DF DF ANALOG CONTROL CROSS MULTIPLEXER 9 CVBS/Y Fig 6. 9 CHROMA 9 R/R - Y 9 G/Y 9 B/B - Y 9 9 AD2/4BYP AD1/3BYP mbl758 Analog input processing using the SAF7118 as differential front-end with 9-bit ADC 8.1.1.1 Clamping The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the four ADC channels are fixed for luminance (120), chrominance (256) and for component inputs as component Y (32), components PB and PR (256) or components RGB (32). Clamping time in normal use is set with the HCL pulse on the back porch of the video signal. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 16 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.1.1.2 Gain control The gain control circuit receives (via the I2C-bus) the static gain levels for the four analog amplifiers or controls one of these amplifiers automatically via a built-in Automatic Gain Control (AGC) as part of the Analog Input COntrol (AICO). The AGC for luminance is used to amplify a CVBS or Y signal to the required signal amplitude, matched to the ADCs input voltage range. Component inputs are gain adjusted manually at a fixed gain. The AGC active time is the sync bottom of the video signal. Signal (white) peak control limits the gain at signal overshoots. The flow charts (see Figure 9 and Figure 10) show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control. TV line analog line blanking 511 GAIN CLAMP 120 1 HCL HSY Fig 7. mhb726 Analog line with clamp (HCL) and gain range (HSY) analog input level +3 dB 0 dB controlled ADC input level maximum range 9 dB 0 dB (1 V (p-p) 18/56 Ω) −6 dB minimum mhb325 Fig 8. Automatic gain range SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 17 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter ANALOG INPUT gain AMPLIFIER 9 DAC ANTI-ALIAS FILTER ADC 9 1 NO ACTION 0 VBLK 1 LUMA/CHROMA DECODER 0 HOLDG 1 0 X 1 0 0 510 1 1 1 0 496 +1 / F > 510 X=1 X=0 1 0 HSY +1 / L +/− 0 +1 / LLC2 −1 / LLC2 −1 / LLC2 GAIN ACCUMULATOR (18 BITS) STOP ACTUAL GAIN VALUE 9-BIT (AGV) [−3/+6 dB] 1 0 X 1 0 HSY 1 AGV Y UPDATE 0 FGV GAIN VALUE 9-BIT mhb728 X = system variable Y = |AGV − FGV| > GUDL GUDL = gain update level (adjustable) VBLK = vertical blanking pulse HSY = horizontal sync pulse AGV = actual gain value FGV = frozen gain value Fig 9. Gain flow chart SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 18 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter ANALOG INPUT ADC 1 NO BLANKING ACTIVE VBLK 0 0 HCL 1 0 0 − CLAMP NO CLAMP + GAIN < SBOT HSY 1 − GAIN 0 1 > WIPE 0 slow + GAIN fast − GAIN mgc647 WIPE = white peak level (510) SBOT = sync bottom level (1) CLL = clamp level [120 for CVBS, Y(C), S; 256 for C(Y), PB-PR; 32 for RGB, Y] HSY = horizontal sync pulse HCL = horizontal clamp pulse Fig 10. Clamp and gain flow chart SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 19 of 175 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Y DELAY COMPENSATION SUBTRACTOR CHR QUADRATURE MODULATOR CB-CR INTERPOLATION LOW-PASS 3 LUBW CVBS-IN or CHR-IN QUADRATURE DEMODULATOR LOW-PASS 1 DOWNSAMPLING CB-CR ADAPTIVE COMB FILTER CB-CR SET_RAW CCOMB SET_VBI YCOMB LDEL BYPS LDEL YCOMB CHROMINANCE INCREMENT DELAY SET_RAW SET_VBI LUFI[3:0] CSTD[2:0] YDEL[2:0] LOW-PASS 2 CHBW SECAM PROCESSING Y/CVBS DBRI[7:0] DCON[7:0] DSAT[7:0] RAWG[7:0] RAWO[7:0] COLO BRIGHTNESS CONTRAST SATURATION CONTROL RAW DATA GAIN AND OFFSET CONTROL CB-CR CHROMINANCE INCREMENT DTO RESET SUBCARRIER INCREMENT GENERATION AND DIVIDER SUBCARRIER GENERATION 1 HUEC[7:0] CDTO CSTD[2:0] 20 of 175 © NXP B.V. 2008. All rights reserved. Fig 11. Chrominance and luminance processing FCTC ACGC CGAIN[6:0] IDEL[3:0] CODE CHROMA GAIN CONTROL CB-CR ADJUSTMENT BRIG[7:0] CONT[7:0] SATN[7:0] PAL DELAY LINE SECAM RECOMBINATION SET_RAW SET_VBI DCVF mhb729 fH / 2 switch signal CB-CR-OUT HREF-OUT SAF7118 RTCO PHASE DEMODULATOR AMPLITUDE DETECTOR BURST GATE ACCUMULATOR LOOP FILTER SET_RAW SET_VBI Y-OUT/ CVBS OUT Multistandard video decoder with adaptive comb filter Rev. 04 — 4 July 2008 LCBW[2:0] SUBCARRIER GENERATION 2 LUMINANCE-PEAKING OR LOW-PASS, Y-DELAY ADJUSTMENT 8.1.2 Chrominance and luminance processing LDEL YCOMB NXP Semiconductors SAF7118_4 Product data sheet CVBS-IN or Y-IN SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.1.2.1 Chrominance path The 9-bit CVBS or chrominance input signal is fed to the input of a quadrature demodulator, where it is multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 1 (0° and 90° phase relationship to the demodulator axis). The frequency is dependent on the chosen color standard. The time-multiplexed output signals of the multipliers are low-pass filtered (low-pass 1). Eight characteristics are programmable via LCBW2 to LCBW0 to achieve the desired bandwidth for the color difference signals (PAL and NTSC) or the 0° and 90° FM signals (SECAM). The chrominance low-pass 1 characteristic also influences the grade of cross luminance reduction during horizontal color transients (large chrominance bandwidth means strong suppression of cross luminance). If the Y-comb filter is disabled by YCOMB = 0 the filter influences directly the width of the chrominance notch within the luminance path (a large chrominance bandwidth means wide chrominance notch resulting in a lower luminance bandwidth). The low-pass filtered signals are fed to the adaptive comb filter block. The chrominance components are separated from the luminance via a two-line vertical stage (four lines for PAL standards) and a decision logic between the filtered and the non-filtered output signals. This block is bypassed for SECAM signals. The comb filter logic can be enabled independently for the succeeding luminance and chrominance processing by YCOMB (subaddress 09h, bit D6) and/or CCOMB (subaddress 0Eh, bit D0). It is always bypassed during VBI or raw data lines programmable by the LCRn registers (subaddresses 41h to 57h); see Section 8.3. The separated CB-CR components are further processed by a second filter stage (low-pass 2) to modify the chrominance bandwidth without influencing the luminance path. Its characteristic is controlled by CHBW (subaddress 10h, bit D3). For the complete transfer characteristic of low-passes 1 and 2, see Figure 12 and Figure 13. The SECAM processing (bypassed for QAM standards) contains the following blocks: • Baseband ‘bell’ filters to reconstruct the amplitude and phase equalized 0° and 90° FM signals • Phase demodulator and differentiator (FM-demodulation) • De-emphasis filter to compensate the pre-emphasized input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM switch signal) The succeeding chrominance gain control block amplifies or attenuates the CB-CR signal according to the required ITU 601/656 levels. It is controlled by the output signal from the amplitude detection circuit within the burst processing block. The burst processing block provides the feedback loop of the chrominance PLL and contains the following: • • • • Burst gate accumulator Color identification and color killer Comparison nominal/actual burst amplitude (PAL/NTSC standards only) Loop filter chrominance gain control (PAL/NTSC standards only) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 21 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter • Loop filter chrominance PLL (only active for PAL/NTSC standards) • PAL/SECAM sequence detection, H / 2-switch generation The increment generation circuit produces the Discrete Time Oscillator (DTO) increment for both subcarrier generation blocks. It contains a division by the increment of the line-locked clock generator to create a stable phase-locked sine signal under all conditions (e.g. for non-standard signals). The PAL delay line block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC color standards the delay line can be used as an additional vertical filter. If desired, it can be switched off by DCVF = 1. It is always disabled during VBI or raw data lines programmable by the LCRn registers (subaddresses 41h to 57h); see Section 8.3. The embedded line delay is also used for SECAM recombination (cross-over switches). SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 22 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb533 3 V (dB) 0 −3 −6 −9 −12 (1) −15 (2) −18 (3) −21 (4) −24 −27 −30 −33 −36 −39 −42 −45 (1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. −48 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz) 3 V (dB) 0 −3 −6 −9 −12 −15 (5) −18 (6) −21 (7) −24 (8) −27 −30 −33 −36 −39 −42 −45 (5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111. −48 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz) Fig 12. Transfer characteristics of the chrominance low-pass at CHBW = 0 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 23 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb534 3 V (dB) 0 −3 −6 −9 −12 (1) −15 (2) −18 (3) −21 (4) −24 −27 −30 −33 −36 −39 −42 −45 (1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. −48 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz) 3 V (dB) 0 −3 −6 −9 −12 −15 (5) −18 (6) −21 (7) −24 (8) −27 −30 −33 −36 −39 −42 −45 (5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111. −48 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz) Fig 13. Transfer characteristics of the chrominance low-pass at CHBW = 1 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 24 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.1.2.2 Luminance path The rejection of the chrominance components within the 9-bit CVBS or Y input signal is achieved by subtracting the remodulated chrominance signal from the CVBS input. The comb filtered CB-CR components are interpolated (upsampled) by the low-pass 3 block. Its characteristic is controlled by LUBW (subaddress 09h, bit D4) to modify the width of the chrominance ‘notch’ without influencing the chrominance path. The programmable frequency characteristics available, in conjunction with the LCBW2 to LCBW0 settings, can be seen in Figure 14 to Figure 17. It should be noted that these frequency curves are only valid for Y-comb disabled filter mode (YCOMB = 0). In comb filter mode the frequency response is flat. The center frequency of the notch is automatically adapted to the chosen color standard. The interpolated CB-CR samples are multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 2. This second DTO is locked to the first subcarrier generator by an increment delay circuit matched to the processing delay, which is different for PAL and NTSC standards according to the chosen comb filter algorithm. The two modulated signals are finally added to build the remodulated chrominance signal. The frequency characteristic of the separated luminance signal can be further modified by the succeeding luminance filter block. It can be configured as peaking (resolution enhancement) or low-pass block by LUFI3 to LUFI0 (subaddress 09h, bits D3 to D0). The 16 resulting frequency characteristics can be seen in Figure 18. The LUFI3 to LUFI0 settings can be used as a user programmable sharpness control. The luminance filter block also contains the adjustable Y-delay part; programmable by YDEL2 to YDEL0 (subaddress 11h, bits D2 to D0). SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 25 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb535 3 V (dB) 0 −3 −6 −9 −12 −15 −18 −21 (1) (2) (3) (4) −24 −27 −30 −33 −36 −39 −42 −45 (1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. −48 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) 3 V (dB) 0 −3 −6 −9 −12 −15 −18 −21 −24 (5) (6) (7) (8) −27 −30 −33 −36 −39 −42 −45 (5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111. −48 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) Fig 14. Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at LUBW = 0 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 26 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb536 3 V (dB) 0 −3 −6 −9 (1) −12 (2) −15 (3) −18 (4) −21 −24 −27 −30 −33 −36 −39 −42 −45 (1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. −48 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) 3 V (dB) 0 −3 −6 −9 −12 −15 −18 −21 −24 (5) (6) (7) (8) −27 −30 −33 −36 −39 −42 −45 (5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111. −48 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) Fig 15. Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at LUBW = 1 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 27 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb537 3 V (dB) 0 −3 −6 −9 −12 (1) −15 (2) −18 (3) −21 (4) −24 −27 −30 −33 −36 −39 −42 −45 (1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. −48 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) 3 V (dB) 0 −3 −6 −9 −12 (5) −15 (6) −18 (7) −21 (8) −24 −27 −30 −33 −36 −39 −42 −45 (5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111. −48 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) Fig 16. Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at LUBW = 0 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 28 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb538 3 V (dB) 0 −3 −6 −9 −12 (1) −15 (2) −18 (3) −21 (4) −24 −27 −30 −33 −36 −39 −42 −45 (1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. −48 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) 3 V (dB) 0 −3 −6 −9 −12 (5) −15 (6) −18 (7) −21 (8) −24 −27 −30 −33 −36 −39 −42 −45 (5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111. −48 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) Fig 17. Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at LUBW = 1 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 29 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb539 9 V (dB) 8 (1) (2) (3) (4) (5) (6) (7) (8) 7 6 5 4 3 (1) LUFI[3:0] = 0001. (2) LUFI[3:0] = 0010. (3) LUFI[3:0] = 0011. (4) LUFI[3:0] = 0100. (5) LUFI[3:0] = 0101. (6) LUFI[3:0] = 0110. (7) LUFI[3:0] = 0111. (8) LUFI[3:0] = 0000. 2 1 0 −1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 f (MHz) 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 f (MHz) 6.0 3 V (dB) 0 −3 −6 (9) (10) (11) (12) (13) (14) (15) (16) −9 −12 −15 −18 −21 −24 (9) LUFI[3:0] = 1000. (10) LUFI[3:0] = 1001. (11) LUFI[3:0] = 1010. (12) LUFI[3:0] = 1011. (13) LUFI[3:0] = 1100. (14) LUFI[3:0] = 1101. (15) LUFI[3:0] = 1110. (16) LUFI[3:0] = 1111. −27 −30 −33 −36 −39 0 0.5 1.0 1.5 Fig 18. Transfer characteristics of the luminance peaking/low-pass filter (sharpness) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 30 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.1.2.3 Brightness Contrast Saturation (BCS) control and decoder output levels The resulting Y (CVBS) and CB-CR signals are fed to the BCS block, which contains the following functions: • Chrominance saturation control by DSAT7 to DSAT0 • Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to DBRI0 • Raw data (CVBS) gain and offset adjustment by RAWG7 to RAWG0 and RAWO7 to RAWO0 • Limiting Y-CB-CR or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil “ITU Recommendation 601/656”. +255 +235 +128 white LUMINANCE 100 % +255 +240 blue 100 % +255 +240 red 100 % +212 blue 75 % +212 red 75 % +128 colorless +128 colorless CB-COMPONENT +16 0 black CR-COMPONENT +44 yellow 75 % +44 cyan 75 % +16 0 yellow 100 % +16 0 cyan 100 % 001aac241 001aac480 001aac481 “ITU Recommendation 601/656” digital levels with default BCS (decoder) settings DCON[7:0] = 44h, DBRI[7:0] = 80h and DSAT[7:0] = 40h. Equations for modification to the Y-CB-CR levels via BCS control I2C-bus bytes DBRI, DCON and DSAT. DCON Luminance: Y OUT = Int ------------------ × ( Y – 128 ) + DBRI 68 DSAT Chrominance: ( C R C B ) OUT = Int --------------- × (C R,C B – 128) + 128 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with “ITU Recommendation 601/656”. a. Y output range. b. CB output range. c. CR output range. Fig 19. Y-CB-CR range for scaler input and X port output SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 31 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter +255 +255 +209 white +199 LUMINANCE +71 +60 white LUMINANCE black black shoulder +60 SYNC 1 black shoulder = black SYNC sync bottom 1 sync bottom 001aac245 001aac244 CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128. Equation for modification of the raw data levels via bytes RAWG and RAWO: RAWG CVBS OUT = Int ----------------- × ( CVBS nom – 128 ) + RAWO 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with “ITU Recommendation 601/656”. a. Sources containing 7.5 IRE black level offset (e.g. NTSC M). b. Sources not containing black level offset. Fig 20. CVBS (raw data) range for scaler input, data slicer and X port output 8.1.3 Synchronization The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is further reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The loop filter signal drives an oscillator to generate the Line Frequency COntrol (LFCO) signal; see Figure 21. The detection of ‘pseudo syncs’ as part of the Macrovision copy protection standard is also achieved within the synchronization circuit. The result is reported as flag COPRO within the decoder status byte at subaddress 1Fh. 8.1.4 Clock generation circuit The internal CGC generates all clock signals required for the video input processor. The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency: • 6.75 MHz = 429 × fH (50 Hz), or • 6.75 MHz = 432 × fH (60 Hz) The LFCO signal is multiplied by a factor of 2 and 4 in the internal PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the output clock signals. The rectangular output clocks have a 50 % duty factor. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 32 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 6. Decoder clock frequencies Clock Frequency (MHz) XTALO 24.576 or 32.110 LLC 27 LLC2 13.5 LLC4 (internal) 6.75 LLC8 (virtual) 3.375 LFCO BAND-PASS FC = LLC / 4 ZERO CROSS DETECTION PHASE DETECTION LOOP FILTER OSCILLATOR DIVIDER 1/2 DIVIDER 1/2 LLC LLC2 mhb330 Fig 21. Block diagram of the clock generation circuit 8.1.5 Power-on reset and CE input A missing clock, insufficient digital or analog VDDA0 supply voltages (below 2.8 V) will start the reset sequence; all outputs are forced to 3-state (see Figure 22). The indicator output RES is LOW for approximately 128 LLC after the internal reset and can be applied to reset other circuits of the digital TV system. It is possible to force a reset by pulling the CE input to ground. After the rising edge of CE and sufficient power supply voltage, the outputs LLC, LLC2 and SDA return from 3-state to active, while the other signals have to be activated via programming. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 33 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter POC VDDA POC VDDD ANALOG DIGITAL POC LOGIC POC DELAY CLOCK PLL LLC CE RES RESINT CLK0 CE XTALO LLCINT RESINT LLC RES (internal reset) some ms 20 µs to 200 µs PLL delay < 1 ms 896 LLC digital delay 128 LLC 001aad709 POC = Power-on control CE = chip enable input XTALO = crystal oscillator output LLCINT = internal system clock RESINT = internal reset LLC = line-locked clock output RES = reset output Fig 22. Power-on control circuit SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 34 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter VDDD = 3.3 V VDDA = 3.3 V CE(1) > 5 ms > 1 µs(3) > 1 ms start I2C-bus initialization all supplies stable(2) 001aag748 (1) CE raises with digital 3.3 V supply voltage (pulled up to this supply voltage) (2) The order of the supplies has no meaning (3) Optional reset pulse can be applied any time after minimum 5 ms when all supplies are stable Fig 23. CE raises with digital 3.3 V supply voltage VDDD = 3.3 V VDDA = 3.3 V > 5 ms CE(1) > 1 µs(3) > 1 ms start I2C-bus initialization all supplies stable(2) 001aag749 (1) CE keeps LOW during power-up (e.g. pulled down by external reset circuitry) (2) The order of the supplies has no meaning (3) A reset pulse has to be applied after minimum 5 ms subsequent to CE LOW-to-HIGH transition Fig 24. CE keeps LOW during power-up 8.2 Component video processing FSW DELAY FSW Y G/Y B/CB RGB/Y-CB-CR CB MATRIX CR R/CR DOWNFORMATTER and Y BCS and COMPONENT CB-CR DELAY bypass BCS Y to X-port MIXER CB-CR Y-CB-CR decoder mhb731 Fig 25. Component video processing SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 35 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.2.1 RGB-to-(Y-CB-CR) matrix The matrix converts the RGB signals from the analog-to-digital converters/downsamplers to the Y-CB-CR representation. The input and output word widths are 9 bits. The matrix has a gain factor of 1. The block provides a delay compensated bypass for component input signals. The matrix is represented by the following equations: • Y = 0.299 × R + 0.587 × G + 0.114 × B • CB = 0.5772 × (B − Y) • CR = 0.7296 × (R − Y) 8.2.2 Downformatter The block mainly consists of 2 parts: the color difference signal downsampler and the Y-path. The color difference signals are first passed through low-pass filters which reduce alias effects due to the lower data rate. The ITU sampling scheme requires that both color difference samples fit to the first Y sample of the current time slot. Thus the CR signal is delayed by 1 clock before it is fed to the multiplexer. The switch signal defines the data multiplex phase at the output: a ‘0’ marks the first clock of a time slot, this is a CB sample. The output is fed through a register, so that the multiplexer runs with the opposite phase. The delay compensation for the Y signal already provides most of the registers required for a small high-pass filter. It can be used to compensate high frequency losses in the analog part. It provides 2 dB gain at 6.75 MHz. The Y high-pass filter frequency response is shown in Figure 28. The DC gain of the filter is 1, so a limiter is required at the filter output. The current implementation clips at the maximum values of 0 and 511. The entire filter can be controlled by the I2C-bus bit CMFI in subaddress 29h. LOW-PASS CR D Q 0 D Q (CR-CB)OUT 1 LOW-PASS CB switch delay compensation n HIGH-PASS Y D bypass Q YOUT mhb732 CMFI Fig 26. Downformatter block diagram SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 36 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb788 4 Z (dB) 3 2 1 0 −1 0 2 4 6 8 f (MHz) Fig 27. CB-CR low-pass filter frequency response mhb787 2 Z (dB) 0 −20 −40 −60 0 2 4 6 f (MHz) 8 Fig 28. Y high-pass filter frequency response 8.2.3 Component video BCS control The resulting Y and CB-CR signals are fed to the Component BCS (CBCS) block, which contains the following functions: • Chrominance saturation control by CSAT7 to CSAT0 • Luminance contrast and brightness control by CCON7 to CCON0 and CBRI7 to CBRI0 • Limiting Y-CB-CR or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil “ITU Recommendation 601/656”. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 37 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter +255 +235 +128 white LUMINANCE 100 % +255 +240 blue 100 % +255 +240 red 100 % +212 blue 75 % +212 red 75 % +128 colorless +128 colorless CB-COMPONENT +16 0 black CR-COMPONENT +44 yellow 75 % +44 cyan 75 % +16 0 yellow 100 % +16 0 cyan 100 % 001aac241 001aac480 001aac481 “ITU Recommendation 601/656” digital levels with default CBCS (decoder) settings CCON[7:0] = 44h, CBRI[7:0] = 80h and CSAT[7:0] = 40h. Equations for modification to the Y-CB-CR levels via CBCS control I2C-bus bytes CBRI, CCON and CSAT. CCON 68 Luminance: Y OUT = Int ----------------- × ( Y – 128 ) + CBRI CSAT Chrominance: ( C B C R ) OUT = Int --------------- × (C B,C R – 128) + 128 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with “ITU Recommendation 601/656”. a. Y output range. b. CB output range. c. CR output range. Fig 29. Components Y-CB-CR range 8.3 Decoder output formatter The output interface block of the decoder part contains the ITU 656 formatter for the expansion port data output XPD7 to XPD0 (for a detailed description see Section 9.5.1) and the control circuit for the signals needed for the internal paths to the scaler and data slicer part. It also controls the selection of the reference signals for the RT port (RTCO, RTS0 and RTS1) and the expansion port (XRH, XRV and XDQ). The generation of the decoder data type control signals SET_RAW and SET VBI is also done within this block. These signals are decoded from the requested data type for the scaler input and/or the data slicer, selectable by the control registers LCR2 to LCR24 (see Section 10; subaddresses 41h to 57h). For each LCR value from 2 to 23 the data type can be programmed individually; LCR2 to LCR23 refer to line numbers. The selection in LCR24 values is valid for the rest of the corresponding field. The upper nibble contains the value for field 1 (odd), the lower nibble for field 2 (even). The relationship between LCR values and line numbers can be adjusted via VOFF8 to VOFF0, located in subaddresses 5Bh (bit D4) and 5Ah (bits D7 to D0) and FOFF subaddress 5Bh (bit D7). The recommended values are VOFF[8:0] = 03h for 50 Hz sources (with FOFF = 0) and VOFF[8:0] = 06h for 60 Hz sources (with FOFF = 1), to accommodate line number conventions as used for PAL, SECAM and NTSC standards; see Figure 30 and Figure 31. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 38 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 7. Data formats at decoder output Data type number Data type Decoder output data format 0 teletext EuroWST, CCST raw 1 European closed caption raw 2 Video Programming Service (VPS) raw 3 wide screen signalling bits raw 4 US teletext (WST) raw 5 US closed caption (line 21) raw 6 video component signal, VBI region Y-CB-CR 4 : 2 : 2 7 CVBS data raw 8 teletext raw 9 VITC/EBU time codes (Europe) raw 10 VITC/SMPTE time codes (USA) raw 11 reserved raw 12 US NABTS raw 13 MOJI (Japanese) raw 14 Japanese format switch (L20/22) raw 15 video component signal, active video region Y-CB-CR 4 : 2 : 2 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 39 of 175 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 521 LINE NUMBER (2nd FIELD) 259 522 523 524 525 1 2 active video 260 261 262 263 264 active video LINE NUMBER (1st FIELD) 10 LINE NUMBER (2nd FIELD) 273 LCR 10 11 12 4 5 265 2 13 14 15 16 17 6 7 8 serration pulses 266 267 equalization pulses 24 LCR 3 equalization pulses 268 4 18 269 270 20 271 6 21 7 8 22 23 nominal VBI lines F1 274 275 276 277 278 279 12 13 14 15 9 24 25 active video 280 281 282 283 284 285 286 nominal VBI lines F2 11 272 equalization pulses 5 19 9 equalization pulses serration pulses 3 NXP Semiconductors SAF7118_4 Product data sheet LINE NUMBER (1st FIELD) 287 288 active video 16 17 18 19 20 21 22 23 24 001aad425 Rev. 04 — 4 July 2008 Vertical line offset, VOFF[8:0] = 06h (subaddresses 5Bh[4] and 5Ah[7:0]); horizontal pixel offset, HOFF[10:0] = 347h (subaddresses 5Bh[2:0] and 59h[7:0]); FOFF = 1 (subaddress 5Bh[7]) Fig 30. Relationship of LCR to line numbers in 525 lines/60 Hz systems 621 LINE NUMBER (2nd FIELD) 309 622 623 624 active video 625 1 equalization pulses 310 311 active video 312 2 313 314 equalization pulses 6 LINE NUMBER (2nd FIELD) 319 LCR 6 7 8 9 10 11 12 315 316 14 15 16 17 18 317 318 equalization pulses 2 13 5 3 19 20 4 21 22 5 23 nominal VBI lines F1 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 nominal VBI lines F2 7 8 9 10 11 12 13 14 15 24 25 active video 337 338 active video 16 17 18 19 20 21 22 23 24 001aad426 Vertical line offset, VOFF[8:0] = 03h (subaddresses 5Bh[4] and 5Ah[7:0]); horizontal pixel offset, HOFF[10:0] = 347h (subaddresses 5Bh[2:0] and 59h[7:0]); FOFF = 0 (subaddress 5Bh[7]) Fig 31. Relationship of LCR to line numbers in 625 lines/50 Hz systems SAF7118 40 of 175 © NXP B.V. 2008. All rights reserved. LINE NUMBER (1st FIELD) 4 equalization pulses serration pulses 24 LCR 3 serration pulses Multistandard video decoder with adaptive comb filter LINE NUMBER (1st FIELD) SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 622 309 ITU counting single field counting 623 310 624 311 625 312 1 1 2 2 3 3 4 4 5 5 6 6 7 7 22 22 ... ... 23 23 CVBS HREF F_ITU656 V123 (1) VSTO [8:0] = 134h VGATE FID VSTA [8:0] = 15h (a) 1st field ITU counting single field counting 309 309 310 310 311 311 312 312 313 313 314 1 315 2 316 3 317 4 318 5 319 6 335 22 ... ... 336 23 CVBS HREF F_ITU656 V123 (1) VSTO [8:0] = 134h VGATE FID (b) 2nd field VSTA [8:0] = 15h mhb540 (1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to Table 8. For further information see Table 56, Table 57 and Table 58. Fig 32. Vertical timing diagram for 50 Hz/625 line systems Table 8. Control signals Name RTS0 RTS1 XRH XRV HREF X X X - F_ITU656 - - - X V123 X X - X VGATE X X - - FID X X - - SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 41 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter ITU counting single field counting 525 262 1 1 3 3 2 2 4 4 5 5 6 6 7 7 8 8 9 9 10 10 21 21 ... ... 22 22 CVBS HREF F_ITU656 V123 (1) VSTO [8:0] = 101h VGATE FID VSTA [8:0] = 011h (a) 1st field ITU counting single field counting 262 262 263 263 264 1 265 2 266 3 267 4 268 5 269 6 270 7 271 8 272 9 284 21 ... ... 285 22 CVBS HREF F_ITU656 V123 (1) VSTO [8:0] = 101h VGATE FID (b) 2nd field VSTA [8:0] = 011h mhb541 (1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to Table 8. For further information see Table 56, Table 57 and Table 58. Fig 33. Vertical timing diagram for 60 Hz/525 line systems SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 42 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter burst CVBS input processing delay ADC to expansion port: 140 × 1 / LLC expansion port data output sync clipped HREF (50 Hz) 12 × 2 / LLC 144 × 2 / LLC 720 × 2 / LLC CREF 50 Hz CREF2 5 × 2 / LLC 2 × 2 / LLC HS (50 Hz) programming range 108 (step size: 8 / LLC) −107 0 HREF (60 Hz) 16 × 2 / LLC 720 × 2 / LLC 138 × 2 / LLC CREF 60 Hz CREF2 1 × 2 / LLC 2 × 2 / LLC HS (60 Hz) programming range (step size: 8 / LLC) 107 0 −106 mhb542 The signals HREF, HS, CREF2 and CREF are available on pins RTS0 and/or RTS1 (see Table 56 and Table 57); their polarity can be inverted via RTP0 and/or RTP1. The signals HREF and HS are available on pin XRH (see Table 58). Fig 34. Horizontal timing diagram (50/60 Hz) 8.4 Scaler The High Performance video Scaler (HPS) is based on the system as implemented in previous products, but with some aspects enhanced. Vertical upsampling is supported and the processing pipeline buffer capacity is enhanced, to allow more flexible video stream timing at the image port, discontinuous transfers, and handshake. The internal data flow from block to block is discontinuous dynamically, due to the scaling process. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 43 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter The flow is controlled by internal data valid and data request flags (internal handshake signalling) between the sub-blocks; therefore the entire scaler acts as a pipeline buffer. Depending on the actual programmed scaling parameters the effective buffer can exceed to an entire line. The access/bandwidth requirements to the VGA frame buffer are reduced significantly. The high performance video scaler in the SAF7118 has the following major blocks: • Acquisition control (horizontal and vertical timer) and task handling (the region/field/frame based processing) • Prescaler, for horizontal downscaling by an integer factor, combined with appropriate band limiting filters, especially anti-aliasing for CIF format • Brightness, saturation, contrast control for scaled output data • Line buffer, with asynchronous read and write, to support vertical upscaling (e.g. for videophone application, converting 240 into 288 lines, Y-CB-CR 4 : 2 : 2) • Vertical scaling, with phase accurate Linear Phase Interpolation (LPI) for zoom and downscale, or phase accurate ACcumulation Mode (ACM) for large downscaling ratios and better alias suppression • Variable Phase Delay (VPD), operates as horizontal phase accurate interpolation for arbitrary non-integer scaling ratios, supporting conversion between square and rectangular pixel sampling • Output formatter for scaled Y-CB-CR 4 : 2 : 2, Y-CB-CR 4 : 1 : 1 and Y only (format also used for raw data) • FIFO, 32-bit wide, with 64 pixel capacity in Y-CB-CR formats • Output interface, 8-bit or 16-bit (only if extended by H port) data pins wide, synchronous or asynchronous operation, with stream events on discrete pins, or coded in the data stream The overall H and V zooming (HV_zoom) is restricted by the input/output data rate relationships. With a safety margin of 2 % for running in and running out, the maximum T_input_field - T_v_blanking HV_zoom is equal to: 0.98 × ----------------------------------------------------------------------------------------------------------------------------in_pixel × in_lines × out_cycle_per_pix × T_out_clk For example: 1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit data at 13.5 MHz data rate, 1 cycle per pixel; output: 8-bit data at 27 MHz, 2 cycles per pixel; the maximum 20 ms – 24 × 64 µs HV_zoom is equal to: 0.98 × ----------------------------------------------------- = 1.18 720 × 288 × 2 × 37 ns 2. Input from X port: 60 Hz, 720 pixel, 240 lines, 8-bit data at 27 MHz data rate (ITU 656), 2 cycles per pixel; output via I + H port: 16-bit data at 27 MHz clock, 1 cycle per pixel; the maximum HV_zoom is equal to: 16.666 ms – 22 × 64 µs 0.98 × --------------------------------------------------------- = 2.34 720 × 240 × 1 × 37 ns SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 44 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter The video scaler receives its input signal from the video decoder or from the expansion port (X port). It gets 16-bit Y-CB-CR 4 : 2 : 2 input data at a continuous rate of 13.5 MHz from the decoder. Discontinuous data stream can be accepted from the expansion port (X port), normally 8-bit wide ITU 656 such as Y-CB-CR data, accompanied by a pixel qualifier on XDQ. The input data stream is sorted into two data paths, one for luminance (or raw samples) and one for time-multiplexed chrominance CB and CR samples. An Y-CB-CR 4 : 1 : 1 input format is converted to 4 : 2 : 2 for the horizontal prescaling and vertical filter scaling operation. The scaler operation is defined by two programming pages A and B, representing two different tasks, that can be applied field alternating or to define two regions in a field (e.g. with different scaling range, factors and signal source during odd and even fields). Each programming page contains control: • • • • For signal source selection and formats For task handling and trigger conditions For input and output acquisition window definition For H-prescaler, V-scaler and H-phase scaling Raw VBI data is handled as a specific input format and needs its own programming page (equals own task). In VBI pass through operation the processing of prescaler and vertical scaling has to be set to no-processing, however, the horizontal fine scaling VPD can be activated. Upscaling (oversampling, zooming), free of frequency folding, up to a factor of 3.5 can be achieved, as required by some software data slicing algorithms. These raw samples are transported through the image port as valid data and can be output as Y only format. The lines are framed by SAV and EAV codes. 8.4.1 Acquisition control and task handling (subaddresses 80h, 90h, 91h, 94h to 9Fh and C4h to CFh) The acquisition control receives horizontal and vertical synchronization signals from the decoder section or from the X port. The acquisition window is generated via pixel and line counters at the appropriate places in the data path. From X port only qualified pixels and lines (lines with qualified pixel) are counted. The acquisition window parameters are as follows: • Signal source selection regarding input video stream and formats from the decoder, or from X port (programming bits SCSRC[1:0] 91h[5:4] and FSC[2:0] 91h[2:0]) Remark: The input of raw VBI data from the internal decoder should be controlled via the decoder output formatter and the LCR registers; see Section 8.3 • Vertical offset defined in lines of the video source, parameter YO[11:0] 99h[3:0] 98h[7:0] • Vertical length defined in lines of the video source, parameter YS[11:0] 9Bh[3:0] 9Ah[7:0] SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 45 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter • Vertical length defined in number of target lines, as a result of vertical scaling, parameter YD[11:0] 9Fh[3:0] 9Eh[7:0] • Horizontal offset defined in number of pixels of the video source, parameter XO[11:0] 95h[3:0] 94h[7:0] • Horizontal length defined in number of pixels of the video source, parameter XS[11:0] 97h[3:0] 96h[7:0] • Horizontal destination size, defined in target pixels after fine scaling, parameter XD[11:0] 9Dh[3:0] 9Ch[7:0] The source start offset (XO11 to XO0 and YO11 to YO0) opens the acquisition window, and the target size (XD11 to XD0 and YD11 to YD0) closes the window, however the window is cut vertically if there are less output lines than expected. The trigger events for the pixel and line counts are the horizontal and vertical reference edges as defined in subaddress 92h. The task handling is controlled by subaddress 90h; see Section 8.4.1.2. 8.4.1.1 Input field processing The trigger event for the field sequence detection from external signals (X port) are defined in subaddress 92h. From the X port the state of the scalers H reference signal at the time of the V reference edge is taken as field sequence identifier FID. For example, if the falling edge of the XRV input signal is the reference and the state of XRH input is logic 0 at that time, the detected field ID is logic 0. The bits XFDV[92h[7]] and XFDH[92h[6]] define the detection event and state of the flag from the X port. For the default setting of XFDV and XFDH at ‘00’ the state of the H-input at the falling edge of the V-input is taken. The scaler directly gets a corresponding field ID information from the SAF7118 decoder path. The FID flag is used to determine whether the first or second field of a frame is going to be processed within the scaler and it is used as trigger condition for the task handling (see bits STRC[1:0] 90h[1:0]). According to ITU 656, when FID is at logic 0 means first field of a frame. To ease the application, the polarities of the detection results on the X port signals and the internal decoder ID can be changed via XFDH. As the V-sync from the decoder path has a half line timing (due to the interlaced video signal), but the scaler processing only knows about full lines, during 1st fields from the decoder the line count of the scaler possibly shifts by one line, compared to the 2nd field. This can be compensated for by switching the V-trigger event, as defined by XDV0, to the opposite V-sync edge or by using the vertical scalers phase offsets. The vertical timing of the decoder can be seen in Figure 32 and Figure 33. As the H and V reference events inside the ITU 656 data stream (from X port) and the real-time reference signals from the decoder path are processed differently, the trigger events for the input acquisition also have to be programmed differently. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 46 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 9. XDV1 92h[5] Processing trigger and start XDV0 92h[4] XDH 92h[2] Description Internal decoder: The processing triggers at the falling edge of the V123 pulse [see Figure 32 (50 Hz) and Figure 33 (60 Hz)], and starts earliest with the rising edge of the decoder HREF at line number: 8.4.1.2 0 1 0 4/7 (50/60 Hz, 1st field), respectively 3/6 (50/60 Hz, 2nd field) (decoder count) 0 0 0 2/5 (50/60 Hz, 1st field), respectively 2/5 (50/60 Hz, 2nd field) (decoder count) 0 0 0 External ITU 656 stream: The processing starts earliest with SAV at line number 23 (50 Hz system), respectively line 20 (60 Hz system) (according to ITU 656 count) Task handling The task handler controls the switching between the two programming register sets. It is controlled by subaddresses 90h and C0h. A task is enabled via the global control bits TEA[80h[4]] and TEB[80h[5]]. The handler is then triggered by events, which can be defined for each register set. In the event of a programming error the task handling and the complete scaler can be reset to the initial states by setting the software reset bit SWRST[88h[5]] to logic 0. Especially if the programming registers, related acquisition window and scale are reprogrammed while a task is active, a software reset must be performed after programming. Contrary to the disabling/enabling of a task, which is evaluated at the end of a running task, when SWRST is at logic 0 it sets the internal state machines directly to their idle states. The start condition for the handler is defined by bits STRC[1:0] 90h[1:0] and means: start immediately, wait for next V-sync, next FID at logic 0 or next FID at logic 1. The FID is evaluated, if the vertical and horizontal offsets are reached. When RPTSK[90h[2]] is at logic 1 the actual running task is repeated (under the defined trigger conditions), before handing control over to the alternate task. To support field rate reduction, the handler is also enabled to skip fields (bits FSKP[2:0] 90h[5:3]) before executing the task. A TOGGLE flag is generated (used for the correct output field processing), which changes state at the beginning of a task, every time a task is activated; examples are given in Section 8.4.1.3. Remarks: • To activate a task the start condition must be fulfilled and the acquisition window offsets must be reached. For example, in case of ‘start immediately’, and two regions are defined for one field, the offset of the lower region must be greater than (offset + length) of the upper region, if not, the actual counted H and V position at the end of the upper task is beyond the programmed offsets and the processing will ‘wait for next V’. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 47 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter • Basically the trigger conditions are checked, when a task is activated. It is important to realize, that they are not checked while a task is inactive. So you can not trigger to next logic 0 or logic 1 with overlapping offset and active video ranges between the tasks (e.g. task A STRC[1:0] = 2, YO[11:0] = 310 and task B STRC[1:0] = 3, YO[11:0] = 310 results in output field rate of 50⁄3 Hz). • After power-on or software reset (via SWRST[88h[5]]) task B gets priority over task A. 8.4.1.3 Output field processing As a reference for the output field processing, two signals are available for the back-end hardware. These signals are the input field ID from the scaler source and a TOGGLE flag, which shows that an active task is used an odd (1, 3, 5...) or even (2, 4, 6...) number of times. Using a single or both tasks and reducing the field or frame rate with the task handling function, the TOGGLE information can be used to reconstruct an interlaced scaled picture at a reduced frame rate. The TOGGLE flag isn’t synchronized to the input field detection, as it is only dependent on the interpretation of this information by the external hardware, whether the output of the scaler is processed correctly; see Section 8.4.3. With OFIDC = 0, the scalers input field ID is available as output field ID on bit D6 of SAV and EAV, respectively on pin IGP0 (IGP1), if FID output is selected. When OFIDC[90h[6]] = 1, the TOGGLE information is available as output field ID on bit D6 of SAV and EAV, respectively on pin IGP0 (IGP1), if FID output is selected. Additionally the bit D7 of SAV and EAV can be defined via CONLH[90h[7]]. CONLH[90h[7]] = 0 (default) sets D7 to logic 1, a logic 1 inverts the SAV/EAV bit D7. So it is possible to mark the output of both tasks by different SAV/EAV codes. This bit can also be seen as ‘task flag’ on pins IGP0 (IGP1), if TASK output is selected. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 48 of 175 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors SAF7118_4 Product data sheet Table 10. Examples for field processing Subject Field sequence frame/field Example 1[1] Example 2[2][3] Example 3[2][4][5] Example 4[2][4][6] 1/1 1/2 2/1 1/1 1/2 2/1 2/2 1/1 1/2 2/1 2/2 3/1 3/2 1/1 1/2 2/1 2/2 3/1 3/2 Processed by task A A A B A B A B B A B B A B B A B B A State of detected ITU 656 FID 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TOGGLE flag 1 0 1 1 1 0 0 1 0 1 1 0 0 0[7] 1 1 1[7] 0 0 1 1 1[7] 0 0 Bit D6 of SAV/EAV byte 0 1 0 0 1 0 1 1 0 1 1 0 0 0[7] Required sequence conversion at the vertical scaler[8] UP↓ UP LO↓ LO UP↓ UP UP↓ UP LO↓ LO UP↓ UP LO↓ LO UP↓ LO LO↓ UP UP↓ LO LO↓ LO UP↓ UP LO↓ UP UP↓ UP LO↓ LO UP↓ LO LO↓ LO UP↓ UP LO↓ UP Output[9] O O O O O O O O O O O O O NO O O NO O O Single task every field; OFIDC = 0; subaddress 90h at 40h; TEB[80h[5]] = 0. [2] Tasks are used to scale to different output windows, priority on task B after SWRST. [3] Both tasks at 1⁄2 frame rate; OFIDC = 0; subaddresses 90h at 43h and C0h at 42h. [4] In examples 3 and 4 the association between input FID and tasks can be flipped, dependent on which time the SWRST is de-asserted. [5] Task B at 2⁄3 frame rate constructed from neighboring motion phases; task A at 1⁄3 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90h at 41h and C0h at 45h. [6] Task A and B at 1⁄3 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90h at 41h and C0h at 49h. [7] State of prior field. [8] It is assumed that input/output FID = 0 (= upper lines); UP = upper lines; LO = lower lines. [9] O = data output; NO = no output. SAF7118 49 of 175 © NXP B.V. 2008. All rights reserved. Multistandard video decoder with adaptive comb filter Rev. 04 — 4 July 2008 [1] SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.4.2 Horizontal scaling The overall horizontal required scaling factor has to be split into a binary and a rational value according to the equation: output pixel H-scale ratio = ---------------------------input pixel 1 1024 H-scale ratio = --------------------------- × ----------------------------XPSC[5:0] XSCY[12:0] where the parameter of prescaler XPSC[5:0] = 1 to 63 and the parameter of VPD phase interpolation XSCY[12:0] = 300 to 8191 (0 to 299 are only theoretical values). For example, 1⁄3.5 is to split in 1⁄4 × 1.14286. The binary factor is processed by the prescaler, the arbitrary non-integer ratio is achieved via the variable phase delay VPD circuitry, called horizontal fine scaling. The latter calculates horizontally interpolated new samples with a 6-bit phase accuracy, which relates to less than 1 ns jitter for regular sampling scheme. Prescaler and fine scaler create the horizontal scaler of the SAF7118. Using the accumulation length function of the prescaler (XACL[5:0] A1h[5:0]), application and destination dependent (e.g. scale for display or for a compression machine), a compromise between visible bandwidth and alias suppression can be determined. 8.4.2.1 Horizontal prescaler (subaddresses A0h to A7h and D0h to D7h) The prescaling function consists of an FIR anti-alias filter stage and an integer prescaler, which creates an adaptive prescale dependent low-pass filter to balance sharpness and aliasing effects. The FIR prefilter stage implements different low-pass characteristics to reduce alias for downscales in the range of 1 to 1⁄2. A CIF optimized filter is built-in, which reduces artefacts for CIF output formats (to be used in combination with the prescaler set to 1⁄ scale); see Table 11. 2 The function of the prescaler is defined by: • An integer prescaling ratio XPSC[5:0] A0h[5:0] (equals 1 to 63), which covers the integer downscale range 1 to 1⁄63 • An averaging sequence length XACL[5:0] A1h[5:0] (equals 0 to 63); range 1 to 64 • A DC gain renormalization XDCG[2:0] A2h[2:0]; 1 down to 1⁄128 • The bit XC2_1[A2h[3]], which defines the weighting of the incoming pixels during the averaging process: – XC2_1 = 0 ⇒ 1 + 1...+ 1 + 1 – XC2_1 = 1 ⇒ 1 + 2...+ 2 + 1 The prescaler creates a prescale dependent FIR low-pass, with up to (64 + 7) filter taps. The parameter XACL[5:0] can be used to vary the low-pass characteristic for a given integer prescale of 1⁄XPSC[5:0]. The user can therefore decide between signal bandwidth (sharpness impression) and alias. Npix_in Equation for XPSC[5:0] calculation is: XPSC[5:0] = lower integer of ---------------------Npix_out SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 50 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Where: • The range is 1 to 63 (value 0 is not allowed) • Npix_in = number of input pixel, and • Npix_out = number of desired output pixel over the complete horizontal scaler The use of the prescaler results in a XACL[5:0] and XC2_1 dependent gain amplification. The amplification can be calculated according to the equation: DC gain = (XC2_1 + 1) × XACL[5:0] + (1 − XC2_1) It is recommended to use sequence lengths and weights, which results in a 2N DC gain 1 amplification, as these amplitudes can be renormalized by the XDCG[2:0] controlled -----N2 shifter of the prescaler. The renormalization range of XDCG[2:0] is 1, 1⁄2 down to 1⁄128. Other amplifications have to be normalized by using the following BCS control circuitry. In these cases the prescaler has to be set to an overall gain of ≤ 1, e.g. for an accumulation sequence of ‘1 + 1 + 1’ (XACL[5:0] = 2 and XC2_1 = 0), XDCG[2:0] must be set to ‘010’, this equals 1⁄4 and the BCS has to amplify the signal to 4⁄3 (SATN[7:0] and CONT[7:0] value = lower integer of 4⁄3 × 64). The use of XACL[5:0] is XPSC[5:0] dependent. XACL[5:0] must be < 2 × XPSC[5:0]. XACL[5:0] can be used to find a compromise between bandwidth (sharpness) and alias effects. Remark: Due to bandwidth considerations XPSC[5:0] and XACL[5:0] can be chosen differently to the previously mentioned equations or Table 12, as the H-phase scaling is able to scale in the range from zooming up by factor 3 to downscaling by a factor of 1024⁄ 8191. Figure 37 and Figure 38 show some resulting frequency characteristics of the prescaler. Table 12 shows the recommended prescaler programming. Other programmings, other than given in Table 12, may result in better alias suppression, but the resulting DC gain amplification needs to be compensated by the BCS control, according to the equation: XDCG[2:0] 2 CONT[7:0] = SATN[7:0] = low integer of -------------------------------DC gain × 64 Where: • 2XDCG[2:0] ≥ DC gain • DC gain = (XC2_1 + 1) × XACL[5:0] + (1 − XC2_1) For example, if XACL[5:0] = 5, XC2_1 = 1, then the DC gain = 10 and the required XDCG[2:0] = 4. The horizontal source acquisition timing and the prescaling ratio is identical for both the luminance path and chrominance path, but the FIR filter settings can be defined differently in the two channels. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 51 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Fade-in and fade-out of the filters is achieved by copying an original source sample each as first and last pixel after prescaling. Figure 35 and Figure 36 show the frequency characteristics of the selectable FIR filters. Table 11. FIR prefilter functions PFUV[1:0] A2h[7:6] and PFY[1:0] A2h[5:4] Luminance filter coefficients Chrominance coefficients 00 bypassed bypassed 01 121 121 10 −1 1 1.75 4.5 1.75 1 −1 3 8 10 8 3 11 12221 12221 mhb543 6 3 V (dB) 0 −3 −6 −9 −12 −15 (1) PFY[1:0] = 01. (2) PFY[1:0] = 10. (3) PFY[1:0] = 11. (1) (2) (3) −18 −21 −24 −27 −30 −33 −36 −39 −42 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 f_sig/f_clock Fig 35. Luminance prefilter characteristic mhb544 6 3 V (dB) 0 −3 −6 −9 −12 −15 (1) PFUV[1:0] = 01. (2) PFUV[1:0] = 10. (3) PFUV[1:0] = 11. (1) (2) (3) −18 −21 −24 −27 −30 −33 −36 −39 −42 0 0.025 0.05 0.075 0.10 0.125 0.15 0.175 0.20 0.225 0.25 f_sig/f_clock Fig 36. Chrominance prefilter characteristic SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 52 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb545 6 3 V (dB) 0 −3 −6 −9 −12 −15 (5) (4) (3) (2) (1) −18 −21 −24 −27 −30 −33 −36 −39 −42 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 f_sig/f_clock 1 XACL + 1 XC2_1 = 0; Zero’s at f = n × ------------------------- with XACL = (1), (2), (3), (4) or (5) Fig 37. Examples for prescaler filter characteristics: effect of increasing XACL[5:0] mhb546 6 3 V (dB) 0 −3 −6 −9 −12 −15 (1) XC2_1 = 0 and XACL[5:0] = 1. (2) XC2_1 = 1 and XACL[5:0] = 2. (3) XC2_1 = 0 and XACL[5:0] = 3. (4) XC2_1 = 1 and XACL[5:0] = 4. (5) XC2_1 = 0 and XACL[5:0] = 7. (6) XC2_1 = 1 and XACL[5:0] = 8. 3 dB at 0.25 6 dB at 0.33 (6) (5) (4) 0.1 0.15 (3) (2) (1) −18 −21 −24 −27 −30 −33 −36 −39 −42 0 0.05 0.2 0.25 0.3 0.35 0.4 0.45 0.5 f_sig/f_clock Fig 38. Examples for prescaler filter characteristics: setting XC2_1 = 1 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 53 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 12. XACL[5:0] example of usage Prescale ratio XPSC Recommended values [5:0] For lower bandwidth requirements XACL[5:0] XC2_1 XDCG[2:0] FIR prefilter For higher bandwidth requirements PFY[1:0]/ PFUV[1:0] XACL[5:0] XC2_1 XDCG[2:0] 1 1 0 0 0 0 1⁄ 2 2 2 1 2 1 (1 2 1) × 1⁄ 3 3 4 1⁄ [1] 4 (1 1) × 1 3 1⁄ 4 4 7 5 8 3 4 1⁄ [1] 8 1 (1 2 2 2 1) × 4 7 (1 2 2 2 2 2 2 2 1) × 1⁄16[1] 1⁄ 6 6 8 1 (1 2 2 2 2 2 2 2 1) × 1⁄ 7 7 8 8 4 7 1⁄ [1] 16 1 15 0 9 1⁄ 10 10 15 0 1 0 to 2 0 2 2 3 2 3 2 3 3 3 3 4 3 4 3 4 3 1 1⁄ [1] 8 0 0 (1 1 1 1 1 1 1 1) × 4 7 1⁄ [1] 8 0 (1 1 1 1 1 1 1 1) × 1⁄8[1] 4 (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) × 1⁄ 9 0 (1 1 1 1 1 1 1 1) × 1⁄8[1] (1 2 2 2 2 2 2 2 1) × 1⁄16[1] 1⁄ 8 0 to 2 (1 1 1 1) × 1⁄4[1] 0 (1 1 1 1 1 1 1 1) × 1⁄ 5 0 1⁄ [1] 2 3 (1 2 2 2 1) × 1⁄8[1] 0 8 1⁄ [1] 16 4 1 (1 2 2 2 2 2 2 2 1) × 8 1⁄ [1] 16 1 (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) × 1⁄16[1] (1 2 2 2 2 2 2 2 1) × 1⁄16[1] 16 8 1 5 (1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1) × 1⁄ [1] 32 1 (1 2 2 2 2 2 2 2 1) × 1⁄ [1] 16 1⁄ 13 13 16 1 5 16 1 5 3 1⁄ 15 15 31 0 5 16 1 5 3 1⁄ 16 16 32 1 6 16 1 5 3 1⁄ 19 19 32 1 6 32 1 6 3 1⁄ 31 31 32 1 6 32 1 6 3 1⁄ 32 32 63 1 7 32 1 6 3 1⁄ 35 35 63 1 7 63 1 7 3 [1] Resulting FIR function. 8.4.2.2 Horizontal fine scaling (variable phase delay filter; subaddresses A8h to AFh and D8h to DFh) The horizontal fine scaling (VPD) should operate at scaling ratios between 1⁄2 and 2 (0.8 and 1.6), but can also be used for direct scaling in the range from 1⁄7.999 to (theoretical) zoom 3.5 (restriction due to the internal data path architecture), without prescaler. In combination with the prescaler a compromise between sharpness impression and alias can be found. This is signal source and application dependent. For the luminance channel a filter structure with 10 taps is implemented, and for the chrominance a filter with 4 taps. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 54 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Luminance and chrominance scale increments (XSCY[12:0] A9h[4:0] A8h[7:0] and XSCC[12:0] ADh[4:0] ACh[7:0]) are defined independently, but must be set in a 2 : 1 relationship in the actual data path implementation. The phase offsets XPHY[7:0] AAh[7:0] and XPHC[7:0] AEh[7:0] can be used to shift the sample phases slightly. XPHY[7:0] and XPHC[7:0] covers the phase offset range 7.999T to 1⁄32T. The phase offsets should also be programmed in a 2 : 1 ratio. The underlying phase controlling DTO has a 13-bit resolution. According the equations: Npix_in 1 XSCY[12:0] XSCY[12:0] = 1024 × --------------------------- × ---------------------- and XSCC[12:0] = ----------------------------XPSC[5:0] Npix_out 2 the VPD covers the scale range from 0.125 to zoom 3.5. VPD acts equivalent to a polyphase filter with 64 possible phases. In combination with the prescaler, it is possible to get very accurate samples from a highly anti-aliased integer downscaled input picture. 8.4.3 Vertical scaling The vertical scaler of the SAF7118 consists of a line FIFO buffer for line repetition and the vertical scaler block, which implements the vertical scaling on the input data stream in 2 different operational modes from theoretical zoom by 64 down to icon size 1⁄64. The vertical scaler is located between the BCS and horizontal fine scaler, so that the BCS can be used to compensate the DC gain amplification of the ACM mode (see Section 8.4.3.2) as the internal RAMs are only 8-bit wide. 8.4.3.1 Line FIFO buffer (subaddresses 91h, B4h and C1h, E4h) The line FIFO buffer is a dual ported RAM structure for 768 pixels, with asynchronous write and read access. The line buffer can be used for various functions, but not all functions may be available simultaneously. The line buffer can buffer a complete unscaled active video line or more than one shorter lines (only for non-mirror mode), for selective repetition for vertical zoom-up. For zooming up 240 lines to 288 lines e.g., every fourth line is requested (read) twice from the vertical scaling circuitry for calculation. For conversion of a 4 : 2 : 0 or 4 : 1 : 0 input sampling scheme (MPEG, video phone, Indeo YUV-9) to ITU like sampling scheme 4 : 2 : 2, the chrominance line buffer is read twice or four times, before being refilled again by the source. It has to be preserved by means of the input acquisition window definition, so that the processing starts with a line containing luminance and chrominance information for 4 : 2 : 0 and 4 : 1 : 0 input. The bits FSC[2:1] 91h[2:1] define the distance between the Y/C lines. In the event of 4 : 2 : 2 and 4 : 1 : 1 FSC2 and FSC1 have to be set to ‘00’. The line buffer can also be used for mirroring, i.e. for flipping the image left to right, for the vanity picture in video phone applications (bit YMIR[B4h[4]]). In mirror mode only one active prescaled line can be held in the FIFO at a time. The line buffer can be utilized as an excessive pipeline buffer for discontinuous and variable rate transfer conditions at the expansion port or image port. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 55 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.4.3.2 Vertical scaler (subaddresses B0h to BFh and E0h to EFh) Vertical scaling of any ratio from 64 (theoretical zoom) to 1⁄63 (icon) can be applied. The vertical scaling block consists of another line delay, and the vertical filter structure, that can operate in two different modes; Linear Phase Interpolation (LPI) and accumulation (ACM) mode. These are controlled by YMODE[B4h[0]]: • LPI mode: In LPI mode (YMODE = 0) two neighboring lines of the source video stream are added together, but weighted by factors corresponding to the vertical position (phase) of the target output line relative to the source lines. This linear interpolation has a 6-bit phase resolution, which equals 64 intra line phases. It interpolates between two consecutive input lines only. LPI mode should be applied for scaling ratios around 1 (down to 1⁄2), it must be applied for vertical zooming. • ACM mode: The vertical Accumulation (ACM) mode (YMODE = 1) represents a vertical averaging window over multiple lines, sliding over the field. This mode also generates phase correct output lines. The averaging window length corresponds to the scaling ratio, resulting in an adaptive vertical low-pass effect, to greatly reduce aliasing artefacts. ACM can be applied for downscales only from ratio 1 down to 1⁄64. ACM results in a scale dependent DC gain amplification, which has to be precorrected by the BCS control of the scaler part. The phase and scale controlling DTO calculates in 16-bit resolution, controlled by parameters YSCY[15:0] B1h[7:0] B0h[7:0] and YSCC[15:0] B3h[7:0] B2h[7:0], continuously over the entire field. A start offset can be applied to the phase processing by means of the parameters YPY3[7:0] to YPY0[7:0] in BFh[7:0] to BCh[7:0] and YPC3[7:0] to YPC0[7:0] in BBh[7:0] to B8h[7:0]. The start phase covers the range of 255⁄32 to 1⁄32 lines offset. By programming appropriate, opposite, vertical start phase values (subaddresses B8h to BFh and E8h to EFh) depending on odd or even field ID of the source video stream and A or B page cycle, frame ID conversion and field rate conversion are supported (i.e. de-interlacing, re-interlacing). Figure 39 and Figure 40 and Table 13 and Table 14 describe the use of the offsets. Remark: The vertical start phase, as well as scaling ratio are defined independently for the luminance and chrominance channel, but must be set to the same values in the actual implementation for accurate 4 : 2 : 2 output processing. The vertical processing communicates on its input side with the line FIFO buffer. The scale related equations are: • Scaling increment calculation for ACM and LPI mode, downscale and zoom: Nline_in YSCY[15:0] and YSCC[15:0] = lower integer of  1024 × -----------------------  Nline_out • BCS value to compensate DC gain in ACM mode (contrast and saturation have to be set): CONT[7:0] A5h[7:0] respectively SATN[7:0] A6h[7:0] = Nline_out lower integer of  ----------------------- × 64 , or = lower integer of  Nline_in  SAF7118_4 Product data sheet 1024  ---------------------------× 64  YSCY[15:0] © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 56 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.4.3.3 Use of the vertical phase offsets As described in Section 8.4.1.3, the scaler processing may run randomly over the interlaced input sequence. Additionally the interpretation and timing between ITU 656 field ID and real-time detection by means of the state of H-sync at the falling edge of V-sync may result in different field ID interpretation. A vertically scaled interlaced output also gets a larger vertical sampling phase error, if the interlaced input fields are processed, without regard to the actual scale at the starting point of operation Figure 39. For correct interlaced processing the vertical scaler must be used with respect to the interlace properties of the input signal and, if required, for conversion of the field sequences. Four events should be considered, they are illustrated in Figure 40. scaled output, no phase offset unscaled input field 1 field 2 field 1 scaled output, with phase offset field 2 field 1 field 2 correct scale dependent position scale dependent start offset mismatched vertical line distances mhb547 Fig 39. Basic problem of interlaced vertical scaling (example: downscale 3⁄5) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 57 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter field 1 field 2 field 1 field 2 field 1 field 2 upper lower case UP-UP case LO-LO case UP-LO case LO-UP B A C D mhb548 1024 32 Offset = ------------ = 32 = 1 line shift 1 2 A = --- input line shift = 16 1 2 1 2 YSCY[15:0] 64 B = --- input line shift + --- scale increment = ----------------------------- + 16 1 2 YSCY[15:0] 64 C = --- scale increment = ----------------------------D = no offset = 0 Fig 40. Derivation of the phase related equations (example: interlace vertical scaling down to 3⁄5, with field conversion) In Table 13 and Table 14 PHO is a usable common phase offset. It should be noted that the equations of Figure 40 produce an interpolated output, also for the unscaled case, as the geometrical reference position for all conversions is the position of the first line of the lower field; see Table 13. If there is no need for UP-LO and LO-UP conversion and the input field ID is the reference for the back-end operation, then it is UP-LO = UP-UP and LO-UP = LO-LO and the 1⁄2 line phase shift (PHO + 16) that can be skipped. This case is listed in Table 14. The SAF7118 supports 4 phase offset registers per task and component (luminance and chrominance). The value of 20h represents a phase shift of one line. The registers are assigned to the following events; e.g. subaddresses B8h to BBh: • • • • B8h: 00 = input field ID 0, task status bit D0 (toggle status; see Section 8.4.1.3) B9h: 01 = input field ID 0, task status bit D1 BAh: 10 = input field ID 1, task status bit D0 BBh: 11 = input field ID 1, task status bit D1 Depending on the input signal (interlaced or non-interlaced) and the task processing 50 Hz or field reduced processing with one or two tasks (see examples in Section 8.4.1.3), other combinations may also be possible, but the basic equations are the same. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 58 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 13. Examples for vertical phase offset usage: global equations Input field under processing Output field interpretation Upper input lines upper output lines UP-UP PHO + 16 Upper input lines lower output lines YSCY[15:0] PHO + ----------------------------- + 16 64 Lower input lines upper output lines LO-UP PHO Lower input lines lower output lines YSCY[15:0] PHO + ----------------------------64 Table 14. Used abbreviation UP-LO LO-LO Vertical phase offset usage; assignment of the phase offsets Detected input field ID Task status bit Vertical phase offset Case Equation to be used 0 = upper lines 0 YPY0[7:0] and YPC0[7:0] case 1[1] UP-UP (PHO) case 2[2] UP-UP 3[3] UP-LO case 0 = upper lines 1 = lower lines 1 = lower lines 1 0 1 YPY1[7:0] and YPC1[7:0] YPY2[7:0] and YPC2[7:0] YPY3[7:0] and YPC3[7:0] case 1 UP-UP (PHO) case 2 UP-LO case 3 UP-UP case 1 YSCY[15:0] LO-LO  PHO + ----------------------------- – 16   64 case 2 LO-UP case 3 LO-LO case 1 YSCY[15:0] LO-LO  PHO + ----------------------------- – 16   64 case 2 LO-LO case 3 LO-UP [1] Case 1: OFIDC[90h[6]] = 0; scaler input field ID as output ID; back-end interprets output field ID at logic 0 as upper output lines. [2] Case 2: OFIDC[90h[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 0 as upper output lines. [3] Case 3: OFIDC[90h[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 1 as upper output lines. SAF7118_4 Product data sheet Equation for phase offset calculation (decimal values) © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 59 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.5 VBI data decoder and capture (subaddresses 40h to 7Fh) The SAF7118 contains a versatile VBI data decoder. The circuitry recovers the actual clock phase during the clock run-in period, slices the data bits with the selected data rate, and groups them into bytes. The result is buffered into a dedicated VBI data FIFO with a capacity of 2 × 56 bytes (2 × 14 double words). The clock frequency, signal source, field frequency and accepted error count must be defined in subaddress 40h. The supported VBI data standards are shown in Table 15. For lines 2 to 24 of a field, per VBI line, 1 of 16 standards can be selected (LCR24_[7:0] to LCR2_[7:0] in 57h[7:0] to 41h[7:0]: 23 × 2 × 4 bit programming bits). The definition for line 24 is valid for the rest of the corresponding field, normally no text data (video data) should be selected there (LCR24_[7:0] = FFh) to stop the activity of the VBI data slicer during active video. To adjust the slicers processing to the input signal source, there are offsets in the horizontal and vertical direction available: parameters HOFF[10:0] 5Bh[2:0] 59h[7:0], VOFF[8:0] 5Bh[4] 5Ah[7:0] and FOFF[5Bh[7]]. Contrary to the scalers counting, the slicers offsets define the position of the H and V trigger events related to the processed video field. The trigger events are the falling edge of HREF and the falling edge of V123 from the decoder processing part. The relationship of these programming values to the input signal and the recommended values are given in Figure 30 and Figure 31. Table 15. Data types supported by the data slicer block DT[3:0] 62h[3:0] Standard type Data rate (Mbit/s) Framing Code (FC) FC window Hamming check 0000 teletext EuroWST, CCST 6.9375 27h WST625 always 0001 European closed caption 0.500 001 CC625 0010 VPS 5 9951h VPS 0011 wide screen signalling bits 5 1E 3C1Fh WSS 0100 US teletext (WST) 5.7272 27h WST525 0101 US closed caption (line 21) 0.503 001 CC525 0110 (video data selected) 5 none disable 0111 (raw data selected) 5 none disable 1000 teletext 6.9375 programmable general text 1001 VITC/EBU time codes (Europe) 1.8125 programmable VITC625 1010 VITC/SMPTE time codes (USA) 1.7898 programmable VITC525 1011 reserved 1100 US NABTS 5.7272 programmable NABTS SAF7118_4 Product data sheet always optional optional © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 60 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 15. Data types supported by the data slicer block …continued DT[3:0] 62h[3:0] Standard type Data rate (Mbit/s) Framing Code (FC) FC window 1101 MOJI (Japanese)[1] 5.7272 programmable (A7h) Japtext 1110 Japanese format switch (L20/22) 5 programmable open 1111 no sliced data transmitted 5 (video data selected) none disable [1] Hamming check See errata information in Section 19.6. 8.6 Image port output formatter (subaddresses 84h to 87h) The output interface consists of a FIFO for video and for sliced text data, an arbitration circuit, which controls the mixed transfer of video and sliced text data over the I port and a decoding and multiplexing unit, which generates the 8-bit or 16-bit wide output data stream and the accompanied reference and supporting information. The clock for the output interface can be derived from an internal clock, decoder, expansion port, or an externally provided clock which is appropriate for e.g. VGA and frame buffer. The clock can be up to 33 MHz. The scaler provides the following video related timing reference events (signals), which are available on pins as defined by subaddresses 84h and 85h: • • • • • • • Output field ID Start and end of vertical active video range Start and end of active video line Data qualifier or gated clock Actually activated programming page (if CONLH is used) Threshold controlled FIFO filling flags (empty, full and filled) Sliced data marker The discontinuous data stream at the scaler output is accompanied by a data valid flag (or data qualifier), or is transported via a gated clock. Clock cycles with invalid data on the I port data bus (including the HPD pins in 16-bit output mode) are marked with code 00h. The output interface also arbitrates the transfer between scaled video data and sliced text data over the I port output. The bits VITX1 and VITX0 (subaddress 86h) are used to control the arbitration. As a further operation the serialization of the internal 32-bit double words to 8-bit or optional 16-bit output, as well as the insertion of the extended ITU 656 codes (SAV/EAV for video data, ANC or SAV/EAV codes for sliced text data) are done here. For handshake with the VGA controller, or other memory or bus interface circuitry, programmable FIFO flags are provided; see Section 8.6.2. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 61 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.6.1 Scaler output formatter (subaddresses 93h and C3h) The output formatter organizes the packing into the output FIFO. The following formats are available: Y-CB-CR 4 : 2 : 2, Y-CB-CR 4 : 1 : 1, Y-CB-CR 4 : 2 : 0, Y-CB-CR 4 : 1 : 0 and Y only (e.g. for raw samples). The formatting is controlled by FSI[2:0] 93h[2:0], FOI[1:0] 93h[4:3] and FYSK[93h[5]]. The data formats are defined on double words, or multiples, and are similar to the video formats as recommended for PCI multimedia applications (compares to SAA7146A), but planar formats are not supported. FSI[2:0] defines the horizontal packing of the data, FOI[1:0] defines how many Y only lines are expected, before a Y/C line will be formatted. If FYSK is set to logic 0 preceding Y only lines will be skipped, and the output will always start with a Y/C line. Additionally the output formatter limits the amplitude range of the video data (controlled by ILLV[85h[5]]); see Table 18. Table 16. Byte stream for different output formats Output format Byte sequence for 8-bit output modes Y-CB-CR 4 : 2 : 2 CB0 Y0 CR0 Y1 CB2 Y2 CR2 Y3 CB4 Y4 CR4 Y5 CB6 Y6 Y-CB-CR 4 : 1 : 1 CB0 Y0 CR0 Y1 CB4 Y2 CR4 Y3 Y4 Y5 Y6 CB8 Y8 Y only Y0 Y2 Y4 Y6 Y8 Y9 Y10 Y11 Y12 Y13 Table 17. Y1 Y3 Y5 Y7 Y7 Explanation to Table 16 Name Explanation CBn CB (B − Y) color difference component, pixel number n = 0, 2, 4 to 718 Yn Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719 CRn CR (R − Y) color difference component, pixel number n = 0, 2, 4 to 718 Table 18. Limiting range on I port Limit step ILLV[85h[5]] Valid range Suppressed codes (hexadecimal value) Decimal value Hexadecimal value Lower range Upper range 0 1 to 254 01 to FE 00 FF 1 8 to 247 08 to F7 00 to 07 F8 to FF 8.6.2 Video FIFO (subaddress 86h) The video FIFO at the scaler output contains 32 double words. That corresponds to 64 pixels in 16-bit Y-CB-CR 4 : 2 : 2 format. But as the entire scaler can act as a pipeline buffer, the actual available buffer capacity for the image port is much higher, and can exceed beyond a video line. The image port, and the video FIFO, can operate with the video source clock (synchronous mode) or with an externally provided clock (asynchronous and burst mode), as appropriate for the VGA controller or attached frame buffer. The video FIFO provides 4 internal flags, reporting to what extent the FIFO is actually filled. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 62 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter These are: • The FIFO Almost Empty (FAE) flag • The FIFO Combined Flag (FCF) or FIFO filled, which is set at almost full level and reset, with hysteresis, only after the level crosses below the almost empty mark • The FIFO Almost Full (FAF) flag • The FIFO Overflow (FOVL) flag The trigger levels for FAE and FAF are programmable by FFL[1:0] 86h[3:2] (16, 24, 28, full) and FEL[1:0] 86h[1:0] (16, 8, 4, empty). The state of this flag can be seen on pins IGP0 or IGP1. The pin mapping is defined by subaddresses 84h and 85h; see Section 9.6. 8.6.3 Text FIFO The data of the internal VBI data slicer is collected in the text FIFO before the transmission over the I port is requested (normally before the video window starts). It is partitioned into two FIFO sections. A complete line is filled into the FIFO before a data transfer is requested. So normally, one line of text data is ready for transfer, while the next text line is collected. Thus sliced text data is delivered as a block of qualified data, without any qualification gaps in the byte stream of the I port. The decoded VBI data is collected in the dedicated VBI data FIFO. After the capture of a line has been completed, the FIFO can be streamed through the image port, preceded by a header, giving line number and standard. The VBI data period can be signalled via the sliced data flag on pin IGP0 or IGP1. The decoded VBI data is lead by the ITU ancillary data header (DID[5:0] 5Dh[5:0] at value < 3Eh) or by SAV/EAV codes selectable by DID[5:0] at value 3Eh or 3Fh. Pin IGP0 or IGP1 is set if the first byte of the ANC header is valid on the I port bus. It is reset if an SAV occurs. So it may frame multiple lines of text data output, in the event that the video processing starts with a distance of several video lines to the region of text data. Valid sliced data from the text FIFO is available on the I port as long as the IGP0 or IGP1 flag is set and the data qualifier is active on pin IDQ. The decoded VBI data is presented in two different data formats, controlled by bit RECODE. • RECODE = 1: values 00h and FFh will be recoded to even parity values 03h and FCh • RECODE = 0: values 00h and FFh may occur in the data stream as detected 8.6.4 Video and text arbitration (subaddress 86h) Sliced text data and scaled video data are transferred over the same bus, the I port. The mixed transfer is controlled by an arbitration circuit. If the video data is transferred without any interrupt and the video FIFO does not need to buffer any output pixel, the text data is inserted after the end of a scaled video line, normally during the blanking interval of the video. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 63 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.6.5 Data stream coding and reference signal generation (subaddresses 84h, 85h and 93h) As H and V reference signals are logic 1, active gate signals are generated, which frame the transfer of the valid output data. As an alternative to the gates, H and V trigger pulses are generated on the rising edges of the gates. Due to the dynamic FIFO behavior of the complete scaler path, the output signal timing has no fixed timing relationship to the real-time input video stream. So fixed propagation delays, in terms of clock cycles, related to the analog input cannot be defined. The data stream is accompanied by a data qualifier. Additionally invalid data cycles are marked with code 00h. If ITU 656 like codes are not required, they can be suppressed in the output stream. As a further option, it is possible to provide the scaler with an external gating signal on pin ITRDY. Thereby making it possible to hold the data output for a certain time and to get valid output data in bursts of a guaranteed length. The sketched reference signals and events can be mapped to the I port output pins IDQ, IGPH, IGPV, IGP0 and IGP1. For flexible use the polarities of all the outputs can be modified. The default polarity for the qualifier and reference signals is logic 1 (active). Table 19 shows the relevant and supported SAV and EAV coding. Table 19. SAV/EAV codes on I port Event description SAV/EAV codes on I port[1] (hexadecimal) MSB[2] of SAV/EAV byte = 0 MSB[2] Comment of SAV/EAV byte = 1 Field ID = 0 Field ID = 1 Field ID = 0 Field ID = 1 0E 49 80 C7 HREF = active; VREF = active Previous pixel was LAST pixel of 13 any active line, but not the last 54 9D DA HREF = inactive; VREF = active Next pixel is FIRST pixel of any V-blanking line 25 62 AB EC HREF = active; VREF = inactive Previous pixel was LAST pixel of 38 the last active line or of any V-blanking line 7F B6 F1 HREF = inactive; VREF = inactive Next pixel is FIRST pixel of any active line No valid data, don’t capture and 00 don’t increment pointer IDQ pin inactive [1] The leading byte sequence is: FFh-00h-00h. [2] The MSB of the SAV/EAV code byte is controlled by: a) Scaler output data: task A ⇒ MSB = CONLH[90h[7]]; task B ⇒ MSB = CONLH[C0h[7]]. b) VBI data slicer output data: DID[5:0] 5Dh[5:0] = 3Eh ⇒ MSB = 1; DID[5:0] 5Dh[5:0] = 3Fh ⇒ MSB = 0 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 64 of 175 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx timing reference code ... FF FF 00 00 00 00 EAV 00 00 internal header SAV SDID DC IDI1 sliced data IDI2 D1_3 D1_4 D2_1 and filling data ... DDC_3 DDC_4 D1_1 D1_2 ANC header 00 FF internal header FF DID SDID DC IDI1 BC timing reference code invalid data FF 00 00 00 EAV 00 ANC data output is only filled up to the double word boundary sliced data IDI2 D1_3 D1_4 ... DDC_3 DDC_4 CS CS BC 00 00 NXP Semiconductors SAF7118_4 Product data sheet ... invalid data or end of raw VBI line ... mhb549 ... ANC header active for DID (subaddress 5Dh) < 3Eh Fig 41. Sliced data formats on the I port in 8-bit mode Table 20. Explanation to Figure 41 Explanation SAV start of active data; see Table 21 SDID sliced data identification: NEP[1], EP[2], SDID5 to SDID0, freely programmable via I2C-bus subaddress 5Eh, D5 to D0, e.g. to be used as source identifier DC double word count: NEP[1], EP[2], DC5 to DC0. DC describes the number of succeeding 32-bit words: For SAV/EAV mode DC is fixed to 11 double words (byte value 4Bh) For ANC mode it is: DC = 1⁄4(C + n), where C = 2 (the two data identification bytes IDI1 and IDI2) and n = number of decoded bytes according to the chosen text standard It should be noted that the number of valid bytes inside the stream can be seen in the BC byte. IDI1 internal data identification 1: OP[3], FID (field 1 = 0, field 2 = 1), line number 8 to line number 3 = double word 1 byte 1; see Table 21 IDI2 internal data identification 2: OP[3], line number 2 to line number 0, data type 3 to data type 0 = double word 1 byte 2; see Table 21 Dn_m double word number n, byte number m DDC_4 last double word byte 4; remark: for SAV/EAV framing DC is fixed to 0Bh, missing data bytes are filled up; the fill value is A0h CS the check sum byte, the check sum is accumulated from the SAV (respectively DID) byte to the DDC_4 byte BC number of valid sliced bytes counted from the IDI1 byte EAV end of active data; see Table 21 NEP = inverted EP (bit D7); for EP see Table note 2. [2] EP = even parity (bit D6) of bits D5 to D0. [3] OP = odd parity (bit D7) of bits D6 to D0. SAF7118 65 of 175 © NXP B.V. 2008. All rights reserved. [1] Multistandard video decoder with adaptive comb filter Rev. 04 — 4 July 2008 Name SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 21. Bytes stream of the data slicer Nick Comment name D7 D6 D5 D4 D3 D2 D1 D0 DID, SAV, EAV subaddress 5Dh = 00h NEP[1] EP[2] 0 1 0 FID[3] I1[4] I0[4] subaddress 5Dh D5 = 1 NEP[1] EP[2] 0 D4[5Dh] D3[5Dh] D2[5Dh] D1[5Dh] D0[5Dh] subaddress 5Dh D5 = 3Eh[5] 1 FID[3] V[6] H[7] P3 P2 P1 P0 subaddress 5Dh D5 = 3Fh[5] 0 FID[3] V[6] H[7] P3 P2 P1 P0 SDID programmable via subaddress 5Eh NEP[1] EP[2] D5[5Eh] D4[5Eh] D3[5Eh] D2[5Eh] D1[5Eh] D0[5Eh] DC[8] NEP[1] EP[2] DC5 DC4 DC3 DC2 DC1 DC0 IDI1 OP[9] FID[3] LN8[10] LN7[10] LN6[10] LN5[10] LN4[10] LN3[10] IDI2 OP[9] LN2[10] LN1[10] LN0[10] DT3[11] DT2[11] DT1[11] DT0[11] check sum byte CS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 valid byte count OP[9] 0 CNT5[12] CNT4[12] CNT3[12] CNT2[12] CNT1[12] CNT0[12] CS BC [1] NEP = inverted EP; for EP see Table note 2. [2] EP = even parity of bits D5 to D0. [3] FID = 0: field 1; FID = 1: field 2. [4] I1 = 0 and I0 = 0: before line 1; I1 = 0 and I0 = 1: lines 1 to 23; I1 = 1 and I0 = 0: after line 23; I1 = 1 and I0 = 1: line 24 to end of field. [5] Subaddress 5Dh at 3Eh and 3Fh are used for ITU 656 like SAV/EAV header generation; recommended value. [6] V = 0: active video; V = 1: blanking. [7] H = 0: start of line; H = 1: end of line. [8] DC = data count in double words according to the data type. [9] OP = odd parity of bits D6 to D0. [10] LN = line number. [11] DT = data type according to table. [12] CNT = counter. 8.7 Audio clock generation (subaddresses 30h to 3Fh) The SAF7118 incorporates the generation of a field-locked audio clock as an auxiliary function for video capture. An audio sample clock, that is locked to the field frequency, ensures that there is always the same predefined number of audio samples associated with a field, or a set of fields. This ensures synchronous playback of audio and video after digital recording (e.g. capture to hard disk), MPEG or other compression, or non-linear editing. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 66 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.7.1 Master audio clock The audio clock is synthesized from the same crystal frequency as the line-locked video clock is generated. The master audio clock is defined by the parameters: • Audio master Clocks Per Field, ACPF[17:0] 32h[1:0] 31h[7:0] 30h[7:0] according to audio frequency the equation: ACPF[17:0] = round  --------------------------------------  field frequency  • Audio master Clocks Nominal Increment, ACNI[21:0] 36h[5:0] 35h[7:0] 34h[7:0] audio frequency 23 according to the equation: ACNI[21:0] = round  ----------------------------------------- × 2   crystal frequency  See Table 22 for examples. Remark: For standard applications the synthesized audio clock AMCLK can be used directly as master clock and as input clock for port AMXCLK (short cut) to generate ASCLK and ALRCLK. For high-end applications it is recommended to use an external analog PLL circuit to enhance the performance of the generated audio clock. Table 22. Programming examples for audio master clock generation XTALO (MHz) Field (Hz) ACPF Decimal ACNI Hex Decimal Hex AMCLK = 256 × 48 kHz (12.288 MHz) 32.11 24.576 50 245760 3 C000 3210190 30 FBCE 59.94 205005 3 20CD 3210190 30 FBCE 50 - - - - 59.94 - - - - 3 7200 2949362 2D 00F2 AMCLK = 256 × 44.1 kHz (11.2896 MHz) 32.11 24.576 50 225792 59.94 188348 2 DFBC 2949362 2D 00F2 50 225792 3 7200 3853517 3A CCCD 59.94 188348 2 DFBC 3853 517 3A CCCD AMCLK = 256 × 32 kHz (8.192 MHz) 32.11 24.576 50 163840 2 8000 2140127 20 A7DF 59.94 136670 2 15DE 2140127 20 A7DF 50 163840 2 8000 2796203 2A AAAB 59.94 136670 2 15DE 2796203 2A AAAB SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 67 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.7.2 Signals ASCLK and ALRCLK Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for channel-select. The frequencies of these signals are defined by the following parameters: f ( SDIV + 1 ) × 2 AMXCLK • SDIV[5:0] 38h[5:0] according to the equation: f ASCLK = -----------------------------------⇒ f AMXCLK SDIV[5:0] = ------------------–1 2f ASCLK f LRDIV × 2 ASCLK • LRDIV[5:0] 39h[5:0] according to the equation: f ALRCLK = -------------------------⇒ f ASCLK LRDIV[5:0] = -------------------2f ALRCLK See Table 23 for examples. Table 23. Programming examples for ASCLK/ALRCLK clock generation AMXCLK (MHz) ASCLK (kHz) SDIV Hex ALRCLK (kHz) LRDIV Decimal Decimal Hex 12.288 1536 3 03 48 16 10 768 7 07 8 08 1411.2 3 03 2822.4 1 01 1024 3 03 2048 1 01 11.2896 8.192 44.1 32 16 10 32 10 16 10 32 10 8.7.3 Other control signals Further control signals are available to define reference clock edges and vertical references; see Table 24. Table 24. Control signals for reference clock edges and vertical references Signal Description APLL[3Ah[3]] Audio PLL mode 0 = PLL closed 1 = PLL open AMVR[3Ah[2]] Audio Master clock Vertical Reference 0 = internal V 1 = external V LRPH[3Ah[1]] ALRCLK phase 0 = invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK 1 = don’t invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK SCPH[3Ah[0]] ASCLK phase 0 = invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK 1 = don’t invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 68 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 9. Input/output interfaces and ports The SAF7118 has 5 different I/O interfaces: • Analog video input interface, for analog CVBS and/or Y and C input signals and/or component video signals • • • • • Audio clock port Digital real-time signal port (RT port) Digital video expansion port (X port), for unscaled digital video input and output Digital image port (I port) for scaled video data output and programming Digital host port (H port) for extension of the image port or expansion port from 8-bit to 16-bit 9.1 Analog terminals The SAF7118 has 16 analog inputs AI41 to AI44, AI31 to AI34, AI21 to AI24 and AI11 to AI14 for composite video CVBS or S-video Y/C signal pairs or component video input signals RGB plus separate sync (or Y-PB-PR plus separate sync). Component signals with e.g. sync-on-Y or sync-on-green are also supported; they are fed to two ADC channels, one for the video contents, the other for sync conversion. Additionally, there are four differential reference inputs, which must be connected to ground via a capacitor equivalent to the decoupling capacitors at the 16 inputs. There are no peripheral components required other than these decoupling capacitors and 18 Ω/56 Ω termination resistors, one set per connected input signal; see application example in Figure 92. Four anti-alias filters are integrated. Clamp and gain control for the four ADCs are also integrated. An analog video output (pin AOUT) is provided for testing purposes. Table 25. Analog pin description Symbol Pin[1] AI11 to AI14 J2, K1, K2 and L3 I (27, 29, 31 and 34) AI21 to AI24 G4, G3, H2 and J3 (19, 21, 23 and 26) AI31 to AI34 E3, F2, F3 and G1 (11, 13, 15 and 18) AI41 to AI44 B1, D2, D1 and E1 (2, 5, 7 and 10) AOUT M1 (36) O analog video output, for test purposes AI1D, AI2D, AI3D and AI4D K3, H1, F1 and D3 (30, 22, 14 and 6) I analog reference pins for differential ADC operation; connect to ground via 47 nF [1] I/O Description MODE5 to analog video signal inputs, e.g. 16 CVBS signals or eight Y/C pairs, MODE0 or four RGB plus separate sync (or Y-PB-PR plus separate sync) signal groups can be connected simultaneously to this device; many combinations are possible; see Figure 50 to Figure 90 AOSL2 to AOSL0 Pin numbers for QFP160 in parenthesis. SAF7118_4 Product data sheet Bit © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 69 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 9.2 Audio clock signals The SAF7118 also synchronizes the audio clock and sampling rate to the video frame rate, via a very slow PLL. This ensures that the multimedia capture and compression processes always gather the same predefined number of samples per video frame. An audio master clock AMCLK and two divided clocks ASCLK and ALRCLK are generated: • ASCLK: can be used as audio serial clock • ALRCLK: audio left/right channel clock The ratios are programmable; see Section 8.7. Table 26. Audio clock pin description Symbol Pin[1] I/O Description Bit AMCLK P11 (72) O audio master clock output ACPF[17:0] 32h[1:0] 31h[7:0] 30h[7:0] and ACNI[21:0] 36h[5:0] 35h[7:0] 34h[7:0] AMXCLK M12 (76) I external audio master clock input for the clock division circuit, can be directly connected to output AMCLK for standard applications ASCLK N11 (74) O serial audio clock output, can be synchronized to rising or falling edge of AMXCLK SDIV[5:0] 38h[5:0] and SCPH[3Ah[0]] ALRCLK P12 (75) O audio channel (left/right) clock output, can be synchronized to rising or falling edge of ASCLK LRDIV[5:0] 39h[5:0] and LRPH[3Ah[1]] [1] Pin numbers for QFP160 in parenthesis. 9.3 Clock and real-time synchronization signals For the generation of the line-locked video (pixel) clock LLC, and of the frame-locked audio serial bit clock, a crystal accurate frequency reference is required. An oscillator is built-in for fundamental or third harmonic crystals. The supported crystal frequencies are 32.11 MHz or 24.576 MHz (defined during reset by strapping pin ALRCLK). Alternatively pin XTALI can be driven from an external single-ended oscillator. The crystal oscillation can be propagated as a clock to other ICs in the system via pin XTOUT. The Line-Locked Clock (LLC) is the double pixel clock of nominal 27 MHz. It is locked to the selected video input, generating baseband video pixels according to “ITU recommendation 601”. In order to support interfacing circuits, a direct pixel clock (LLC2) is also provided. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 70 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter The pins for line and field timing reference signals are RTCO, RTS1 and RTS0. Various real-time status information can be selected for the RTS pins. The signals are always available (output) and reflect the synchronization operation of the decoder part in the SAF7118. The function of the RTS1 and RTS0 pins can be defined by bits RTSE1[3:0] 12h[7:4] and RTSE0[3:0] 12h[3:0]. Table 27. Clock and real-time synchronization signals Symbol Pin[1] I/O Description Bit Crystal oscillator XTALI B4 I (155) input for crystal oscillator or reference clock - XTALO A3 O (156) output of crystal oscillator - XTOUT A2 O (158) reference (crystal) clock output drive (optional) XTOUTE[14h[3]] Real-time signals (RT port) LLC P4 (46) O line-locked clock, nominal 27 MHz, double pixel clock locked to the selected video input signal - LLC2 N5 (48) O line-locked pixel clock, nominal 13.5 MHz - RTCO L10 (71) O real-time control output, transfers real-time status information supporting RTC level 3.1 (see document “RTC Functional Description”, available on request) RTS0 M10 (69) O real-time status information line 0, can be programmed to carry various real-time information; see Table 56 RTSE0[3:0] 12h[3:0] RTS1 N10 (70) O real-time status information line 1, can be programmed to carry various real-time information; see Table 57 RTSE1[3:0] 12h[7:4] [1] Pin numbers for QFP160 in parenthesis. 9.4 Interrupt handling 9.4.1 Interrupt flags The pin INT_A is an open-drain output (active LOW). All flags can be independently enabled. For the default setting all flags are disabled after reset. For the description of interrupt mask registers; see Section 10.4. 9.4.1.1 Power state PRDON: a power fail has been detected during normal operation, the device needs re-programming. 9.4.1.2 Video decoder INTL: interlaced/non-interlaced source detected. HLCK: horizontal PLL state changed (locked ↔ unlocked). HLVLN: vertical lock state changed (locked ↔ unlocked). SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 71 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter FIDT: detected field frequency has changed (50 Hz ↔ 60 Hz). RDCAP: ready for capture (true ↔ false). DCSTD[1:0]: detected color standard has changed or color lost. COPRO, COLSTR and TYPE3: various levels of copy protection have changed. 9.4.1.3 VBI data slicer VPSV: VPS identification found or lost. PPV: PALplus identification found or lost. CCV: Closed caption identification found or lost. 9.4.1.4 Scaler ERROF: scaler output formatting error detected. 9.4.2 Status reading conditions The status information read after an interrupt will always be the LATEST state, that means the status will not be ‘frozen’ when an interrupt is being generated. Therefore, if there is a long time between interrupt generation and status reading, the original trigger condition might have been overridden by the present state. 9.4.3 Erasing conditions The status flags are grouped into four 8-bit registers. The interrupt flag will only be cleared on a read access to the status register in which the signal is located which caused the interrupt. This implies that it is sufficient to clear the interrupt by reading only those registers which have been enabled by their corresponding masks. Priority: If a new trigger condition occurs at the SAME time (clock) on which a status is being read, the flag will NOT be cleared. 9.5 Video expansion port (X port) The expansion port is intended for transporting video streams image data from other digital video circuits such as MPEG encoder/decoder and video phone codec, to the image port (I port). The expansion port consists of two groups of signals/pins: • 8-bit data, I/O, regularly components video Y-CB-CR 4 : 2 : 2, i.e. CB-Y-CR-Y, byte serial, exceptionally raw video samples (e.g. ADC test); in input mode the data bus can be extended to 16-bit by pins HPD7 to HPD0 • Clock, synchronization and auxiliary signals, accompanying the data stream, I/O As output, these are direct copies of the decoder signals. The data transfers through the expansion port represent a single D1 port, with half duplex mode. The SAV and EAV codes may be inserted optionally for data input (controlled by bit XCODE[92h[3]]). The input/output direction is switched for complete fields only. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 72 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 28. Signals dedicated to the expansion port Symbol Pin[1] I/O Description Bit I/O XPD7 to C11, A11, XPD0 B10, A10, B9, A9, B8 and A8 (127, 128, 130, 131, 134, 135, 138 and 139) X port data: in output mode controlled by OFTS[2:0] 13h[2:0], decoder section, data format see Table 29; 91h[7:0] and in input mode Y-CB-CR 4 : 2 : 2 serial input C1h[7:0] data or luminance part of a 16-bit Y-CB-CR 4 : 2 : 2 input XCLK A7 (143) I/O clock at expansion port: if output, then copy of LLC; as input normally a double pixel clock of up to 32 MHz or a gated clock (clock gated with a qualifier) XCKS[92h[0]] XDQ B7 (144) I/O data valid flag of the expansion port input (qualifier): if output, then decoder (HREF and VGATE) gate; see Figure 34 - XRDY A6 (146) O data request flag = ready to receive, to work with optional buffer in external device, to prevent internal buffer overflow; second function: input related task flag A/B XRQT[83h[2]] XRH C7 (141) I/O horizontal reference signal for the X port: XRHS[13h[6]], as output: HREF or HS from the decoder XFDH[92h[6]] and (see Figure 34); as input: a reference edge XDH[92h[2]] for horizontal input timing and a polarity for input field ID detection can be defined XRV D8 (140) I/O vertical reference signal for the X port: as XRVS[1:0] 13h[5:4], output: V123 or field ID from the decoder XFDV[92h[7]] and (see Figure 32 and Figure 33); as input: a XDV[1:0] 92h[5:4] reference edge for vertical input timing and for input field ID detection can be defined XTRI B11 (126) I port control: switches X port input 3-state [1] XPE[1:0] 83h[1:0] Pin numbers for QFP160 in parenthesis. 9.5.1 X port configured as output If data output is enabled at the expansion port, then the data stream from the decoder is presented. The data format of the 8-bit data bus is dependent on the chosen data type, selectable by the line control registers LCR2 to LCR24; see Table 7. In contrast to the image port, the sliced data format is not available on the expansion port. Instead, raw CVBS samples are always transferred if any sliced data type is selected. Some details of data types on the expansion port are as follows: • Active video (data type 15): contains component Y-CB-CR 4 : 2 : 2 signal, 720 active pixels per line. The amplitude and offsets are programmable via DBRI7 to DBRI0, DCON7 to DCON0, DSAT7 to DSAT0, OFFU1, OFFU0, OFFV1 and OFFV0. The nominal levels are illustrated in Figure 19. • Test line (data type 6): is similar to the active video format, with some constraints within the data processing: – Adaptive chrominance comb filter, vertical filter (chrominance comb filter for NTSC standards, PAL phase error correction) within the chrominance processing are disabled SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 73 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter – Adaptive luminance comb filter, peaking and chrominance trap are bypassed within the luminance processing This data type is defined for future enhancements. It could be activated for lines containing standard test signals within the vertical blanking period. Currently the most sources do not contain test lines. The nominal levels are illustrated in Figure 19. • Raw samples (data types 0 to 5 and 7 to 14): CB-CR samples are similar to data type 6, but CVBS samples are transferred instead of processed luminance samples within the Y time slots. The amplitude and offset of the CVBS signal is programmable via RAWG7 to RAWG0 and RAWO7 to RAWO0; see Section 10, Table 63 and Table 64. The nominal levels are illustrated in Figure 20. The relationship of LCR programming to line numbers is described in Section 8.3, Figure 30 and Figure 31. The data type selections by LCR are overruled by setting OFTS2 = 1 (subaddress 13h bit D2). This setting is mainly intended for device production test. The VPO-bus carries the upper or lower 8 bits of the two ADCs depending on the OFTS[1:0] 13h[1:0] settings; see Table 58. The input configuration is done via MODE[5:0] 02h[5:0] settings; see Table 40. If a Y/C mode is selected, the expansion port carries the multiplexed output signals of both ADCs, and in CVBS mode the output of only one ADC. No timing reference codes are generated in this mode. Remark: The LSBs (bit D0) of the ADCs are also available on pin RTS0; see Table 56. The SAV/EAV timing reference codes define the start and end of valid data regions. The ITU-blanking code sequence ‘- 80 - 10 - 80 - 10 -...’ is transmitted during the horizontal blanking period between EAV and SAV. The position of the F-bit is constant in accordance with ITU 656; see Table 31 and Table 32. The V-bit can be generated in two different ways (see Table 31 and Table 32) controlled via OFTS1 and OFTS0; see Table 58. The F and V bits change synchronously with the EAV code. Table 29. Data format on the expansion port Timing reference 720 pixels Y-CB-CR 4 : 2 : 2 data[2] code (Hex)[1] Blanking period ... 80 10 FF 00 00 SAV CB0 Y0 CR0 Y1 CB2 Y2 ... CR718 Timing reference Blanking code (Hex)[1] period Y719 FF 00 00 EAV 80 10 ... [1] The generation of the timing reference codes can be suppressed by setting OFTS[2:0] to 010; see Table 58. In this event the code sequence is replaced by the standard ‘- 80 - 10 -’ blanking values. [2] If raw samples or sliced data are selected by the line control registers (LCR2 to LCR24), the Y samples are replaced by CVBS samples. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 74 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 30. SAV/EAV format on expansion port XPD7 to XPD0 Bit Symbol 7 6 Description logic 1 F field bit 1st field: F = 0 2nd field: F = 1 for vertical timing see Table 31 and Table 32 5 V vertical blanking bit VBI: V = 1 active video: V = 0 for vertical timing see Table 31 and Table 32 4 H format H = 0 in SAV format H = 1 in EAV format 3 to 0 P[3:0] Table 31. 525 lines/60 Hz vertical timing Line number reserved; evaluation not recommended (protection bits according to ITU-R BT 656) F (ITU 656) V OFTS[2:0] = 000 (ITU 656) OFTS[2:0] = 001 according to selected VGATE position type via VSTA and VSTO (subaddresses 15h to 17h); see Table 60 to Table 62 1 to 3 1 1 4 to 19 0 1 20 0 0 21 0 0 22 to 261 0 0 262 0 0 263 0 0 264 and 265 0 1 266 to 282 1 1 283 1 0 284 1 0 285 to 524 1 0 525 1 0 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 75 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 32. 625 lines/50 Hz vertical timing Line number F (ITU 656) V OFTS[2:0] = 000 (ITU 656) OFTS[1:0] = 10 according to selected VGATE position type via VSTA and VSTO (subaddresses 15h to 17h); see Table 60 to Table 62 1 to 22 0 1 23 0 0 24 to 309 0 0 310 0 0 311 and 312 0 1 313 to 335 1 1 336 1 0 337 to 622 1 0 623 1 0 624 and 625 1 1 9.5.2 X port configured as input If the data input mode is selected at the expansion port, then the scaler can select its input data stream from the on-chip video decoder, or from the expansion port (controlled by bit SCSRC[1:0] 91h[5:4]). Byte serial Y-CB-CR 4 : 2 : 2, or subsets for other sampling schemes, or raw samples from an external ADC may be input (see also bits FSC[2:0] 91h[2:0]). The input stream must be accompanied by an external clock (XCLK), qualifier XDQ and reference signals XRH and XRV. Instead of the reference signal, embedded SAV and EAV codes according to ITU 656 are also accepted. The protection bits are not evaluated. XRH and XRV carry the horizontal and vertical synchronization signals for the digital video stream through the expansion port. The field ID of the input video stream is carried in the phase (edge) of XRV and state of XRH, or directly as FS (frame sync, odd/even signal) on the XRV pin (controlled by XFDV[92h[7]], XFDH[92h[6]] and XDV[1:0] 92h[5:4]). The trigger events on XRH (rising/falling edge) and XRV (rising/falling/both edges) for the scalers acquisition window are defined by XDV[1:0] 92h[5:4] and XDH[92h[2]]. The signal polarity of the qualifier can also be defined (bit XDQ[92h[1]]). Alternatively to a qualifier, the input clock can be applied to a gated clock (clock gated with a data qualifier, controlled by bit XCKS[92h[0]]). In this event, all input data will be qualified. As the VBI data slicer may have different requirements for its input reference signals from X port XRV, XRH, XDQ, XCLK and XPD7 to XPD0, a second set of parameters is available for defining the meaning of the X port input signals and polarities for the VBI data slicer input path. These bits are defined in subaddresses 81h and 82h. 9.6 Image port (I port) The image port transfers data from the scaler as well as from the VBI data slicer, if selected (maximum 33 MHz). The reference clock is available at the ICLK pin, as an output, or as an input (maximum 33 MHz). As output, ICLK is derived from the line-locked decoder or expansion port input clock. The data stream from the scaler output is normally discontinuous. Therefore valid data during a clock cycle is accompanied by a data qualifying (data valid) flag on pin IDQ. For pin constrained applications the IDQ pin can be programmed to function as a gated clock output (bit ICKS2[80h[2]]). SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 76 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter The data formats at the image port are defined in double words of 32 bits (4 bytes), such as the related FIFO structures. However the physical data stream at the image port is only 16-bit or 8-bit wide; in 16-bit mode data pins HPD7 to HPD0 are used for chrominance data. The four bytes of the double words are serialized in words or bytes. Available formats are as follows: • • • • Y-CB-CR 4 : 2 : 2 Y-CB-CR 4 : 1 : 1 Raw samples Decoded VBI data For handshake with the receiving VGA controller, or other memory or bus interface circuitry, F, H and V reference signals and programmable FIFO flags are provided. The information is provided on pins IGP0, IGP1, IGPH and IGPV. The functionality on these pins is controlled via subaddresses 84h and 85h. VBI data is collected over an entire line in its own FIFO, and transferred as an uninterrupted block of bytes. Decoded VBI data can be signed by the VBI flag on pin IGP0 or IGP1. As scaled video data and decoded VBI data may come from different and asynchronous sources, an arbitration scheme is needed. Normally the VBI data slicer has priority. The image port consists of the pins and/or signals, as listed in Table 33. For pin constrained applications, or interfaces, the relevant timing and data reference signals can also get encoded into the data stream. Therefore the corresponding pins do not need to be connected. The minimum image port configuration requires 9 pins only, i.e. 8 pins for data including codes, and 1 pin for clock or gated clock. The inserted codes are defined in close relationship to the ITU-R BT.656 (D1) recommendation, where possible. The following deviations from “ITU 656 recommendation” are implemented at the SAF7118 image port interface: • SAV and EAV codes are only present in those lines, where data is to be transferred, i.e. active video lines, or VBI raw samples, no codes for empty lines • There may be more or less than 720 pixels between SAV and EAV • Data content and the number of clock cycles during horizontal and vertical blanking is undefined, and may not be constant • Data stream may be interleaved with not-valid data codes, 00h, but SAV and EAV 4-byte codes are not interleaved with not-valid data codes • There may be an irregular pattern of not-valid data, or IDQ, and as a result, CB-Y-CR-Y is not in a fixed phase to a regular clock divider • VBI raw sample streams are enveloped with SAV and EAV, like normal video • Decoded VBI data is transported as Ancillary (ANC) data, two modes: – Direct decoded VBI data bytes (8-bit) are directly placed in the ANC data field, 00h and FFh codes may appear in data block (violation to ITU-R BT.656) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 77 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter – Recoded VBI data bytes (8-bit) directly placed in ANC data field, 00h and FFh codes will be recoded to even parity codes 03h and FCh to suppress invalid ITU-R BT.656 codes There are no empty cycles in the ancillary code and its data field. The data codes 00h and FFh are suppressed (changed to 01h or FEh respectively) in the active video stream, as well as in the VBI raw sample stream (VBI pass-through). Optionally, the number range can be further limited. Table 33. Signals dedicated to the image port Symbol Pin[1] I/O Description Bit IPD7 to IPD0 I/O K11, J13, J14, H13, H14, H11, G12 and G14 (92 to 94, 97 to 100 and 102) I port data ICODE[93h[7]], ISWP[1:0] 85h[7:6] and IPE[1:0] 87h[1:0] ICLK M14 (84) I/O continuous reference clock at image port, can be input or output, as output decoder LLC or XCLK from X port ICKS[1:0] 80h[1:0] and IPE[1:0] 87h[1:0] IDQ L13 (85) O data valid flag at image port, qualifier, with programmable polarity; secondary function: gated clock ICKS2[80h[2]], IDQP[85h[0]] and IPE[1:0] 87h[1:0] IGPH K12 (91) O horizontal reference output signal, copy of IDH[1:0] 84h[1:0], IRHP[85h[1]] and the H gate signal of the scaler, with programmable polarity; alternative function: IPE[1:0] 87h[1:0] HRESET pulse IGPV K14 (90) O vertical reference output signal, copy of the IDV[1:0] 84h[3:2], IRVP[85h[2]] and V gate signal of the scaler, with programmable polarity; alternative function: IPE[1:0] 87h[1:0] VRESET pulse IGP1 K13 (89) O general purpose output signal for I port IDG12[86h[4]], IDG1[1:0] 84h[5:4], IG1P[85h[3]] and IPE[1:0] 87h[1:0] IGP0 L14 (87) O general purpose output signal for I port IDG02[86h[5]], IDG0[1:0] 84h[7:6], IG0P[85h[4]] and IPE[1:0] 87h[1:0] ITRDY N12 (77) I target ready input signals - ITRI L12 (86) I port control, switches I port into 3-state IPE[1:0] 87h[1:0] [1] Pin numbers for QFP160 in parenthesis. 9.7 Host port for 16-bit extension of video data I/O (H port) The H port pins HPD can be used for extension of the data I/O paths to 16-bit. The I port has functional priority. If I8_16[93h[6]] is set to logic 1 the output drivers of the H port are enabled depending on the I port enable control. For I8_16 = 0, the HPD output is disabled. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 78 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 34. Signals dedicated to the host port Symbol Pin[1] I/O I/O HPD7 to G13, F14, HPD0 F13, E14, E12, E13, E11 and D14 (103, 105, 107 and 109 to 113) [1] Description Bit 16-bit extension for digital I/O (chrominance IPE[1:0] 87h[1:0], component) ITRI[8Fh[6]] and I8_16[93h[6]] Pin numbers for QFP160 in parenthesis. 9.8 Basic input and output timing diagrams I port and X port 9.8.1 I port output timing The following diagrams illustrate the output timing via the I port. IGPH and IGPV are logic 1 active gate signals. If reference pulses are programmed, these pulses are generated on the rising edge of the logic 1 active gates. Valid data is accompanied by the output data qualifier on pin IDQ. In addition invalid cycles are marked with output code 00h. The IDQ output pin may be defined to be a gated clock output signal (ICLK AND internal IDQ). 9.8.2 X port input timing At the X port the input timing requirements are the same as those for the I port output. But different to those below: • It is not necessary to mark invalid cycles with a 00h code • No constraints on the input qualifier (can be a random pattern) • XCLK may be a gated clock (XCLK AND external XDQ) Remark: All timings illustrated in Figure 42 to Figure 48 are given for an uninterrupted output stream (no handshake with the external hardware). ICLK IDQ IPD [ 7:0 ] 00 FF 00 00 SAV 00 CB Y CR Y 00 CB Y CR Y 00 IGPH mhb550 Fig 42. Output timing I port for serial 8-bit data at start of a line (ICODE = 1) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 79 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter ICLK IDQ IPD [ 7:0 ] CB 00 Y CR Y 00 CB Y CR Y 00 IGPH mhb551 Fig 43. Output timing I port for serial 8-bit data at start of a line (ICODE = 0) ICLK IDQ IPD [ 7:0 ] 00 CB Y CR Y 00 CB Y CR Y 00 FF 00 00 EAV 00 IGPH mhb552 Fig 44. Output timing I port for serial 8-bit data at end of a line (ICODE = 1) ICLK IDQ IPD [ 7:0 ] 00 CB Y CR Y 00 CB Y CR Y 00 IGPH mhb553 Fig 45. Output timing I port for serial 8-bit data at end of a line (ICODE = 0) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 80 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter ICLK IDQ IPD [ 7:0 ] 00 FF 00 00 Y0 Y1 00 Y2 Y3 Yn−1 Yn 00 FF 00 00 HPD [ 7:0 ] 00 00 SAV 00 CB CR 00 CB CR CB CR 00 00 EAV 00 IGPH mhb554 Fig 46. Output timing for 16-bit data output via I port and H port with codes (ICODE = 1), timing is like 8-bit output, but packages of 2 bytes per valid cycle IDQ IGPH IGPV mhb555 Fig 47. H gate and V gate output timing ICLK IDQ IPD [ 7:0 ] 00 00 FF FF DID HPD [ 7:0 ] 00 FF 00 00 SAV SDID XX YY ZZ CS BC 00 00 00 BC FF 00 00 EAV sliced data flag on IGP0 or IGP1 mhb733 Fig 48. Output timing for sliced VBI data in 8-bit serial output mode (dotted graphs for SAV/EAV mode) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 81 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10. I2C-bus description The SAF7118 supports the ‘fast mode’ I2C-bus specification extension (data rate up to 400 kbit/s). 10.1 I2C-bus format S SLAVE ADDRESS W ACK-s ACK-s SUBADDRESS ACK-s DATA data transferred (n bytes + acknowledge) P mhb339 a. Write procedure. S SLAVE ADDRESS W ACK-s SUBADDRESS ACK-s Sr SLAVE ADDRESS R ACK-s DATA ACK-m data transferred (n bytes + acknowledge) P mhb340 b. Read procedure (combined). Fig 49. I2C-bus format Table 35. Description of I2C-bus format Code Description S START condition Sr repeated START condition SLAVE ADDRESS W 0100 0010 (42h, default) or 0100 0000 (40h)[1] SLAVE ADDRESS R 0100 0011 (43h, default) or 0100 0001 (41h)[1] ACK-s acknowledge generated by the slave ACK-m acknowledge generated by the master SUBADDRESS subaddress byte; see Table 36 and Table 37 DATA data byte; see Table 37; if more than one byte DATA is transmitted the subaddress pointer is automatically incremented P STOP condition [1] If pin RTCO strapped to supply voltage via a 3.3 kΩ resistor. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 82 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 36. Subaddress description and access Subaddress Description Access (read/write) 00h chip version read only F0h to FFh reserved - Video decoder: 01h to 1Fh 01h to 05h front-end part read and write 06h to 19h decoder part read and write 1Ah to 1Dh reserved - 1Eh and 1Fh video decoder status bytes read only Component processing and interrupt masking: 20h to 2Fh 20h to 22h reserved - 23h to 25h analog input control read and write 26h to 28h reserved - 29h to 2Ch component control read and write 2Dh to 2Fh interrupt mask read and write Audio clock generation: 30h to 3Fh 30h to 3Ah audio clock generator read and write 3Bh to 3Fh reserved - General purpose VBI data slicer: 40h to 7Fh 40h to 5Eh VBI data slicer read and write 5Fh reserved - 60h to 62h VBI data slicer status read only 63h to 7Fh reserved - X port, I port and the scaler: 80h to EFh 80h to 8Fh task independent global settings read and write 90h to BFh task A definition read and write C0h to EFh task B definition read and write SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 83 of 175 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors SAF7118_4 Product data sheet Table 37. I2C-bus receiver/transmitter overview Register function Subaddress D7 D6 D5 D4 D3 D2 D1 D0 00h ID7 ID6 ID5 ID4 - - - - Increment delay 01h [1] WPOFF GUDL1 GUDL0 IDEL3 IDEL2 IDEL1 IDEL0 Analog input control 1 02h FUSE1 FUSE0 MODE5 MODE4 MODE3 MODE2 MODE1 MODE0 Analog input control 2 03h [1] HLNRS VBSL CPOFF HOLDG GAFIX GAI28 GAI18 Analog input control 3 04h GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10 Analog input control 4 05h GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20 Horizontal sync start 06h HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 Horizontal sync stop 07h HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 Sync control 08h AUFD FSEL FOET HTC1 HTC0 HPLL VNOI1 VNOI0 Luminance control 09h BYPS YCOMB LDEL LUBW LUFI3 LUFI2 LUFI1 LUFI0 Luminance brightness control 0Ah DBRI7 DBRI6 DBRI5 DBRI4 DBRI3 DBRI2 DBRI1 DBRI0 Luminance contrast control 0Bh DCON7 DCON6 DCON5 DCON4 DCON3 DCON2 DCON1 DCON0 Chrominance saturation control 0Ch DSAT7 DSAT6 DSAT5 DSAT4 DSAT3 DSAT2 DSAT1 DSAT0 Chrominance hue control 0Dh HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0 Chrominance control 1 0Eh CDTO CSTD2 CSTD1 CSTD0 DCVF FCTC AUTO0 CCOMB Chrominance gain control 0Fh ACGC CGAIN6 CGAIN5 CGAIN4 CGAIN3 CGAIN2 CGAIN1 CGAIN0 Chip version: register 00h Chip version (read only) Video decoder: registers 01h to 1Fh Front-end part: registers 01h to 05h Decoder part: registers 06h to 1Fh 10h OFFU1 OFFU0 OFFV1 OFFV0 CHBW LCBW2 LCBW1 LCBW0 Mode/delay control 11h COLO RTP1 HDEL1 HDEL0 RTP0 YDEL2 YDEL1 YDEL0 RT signal control 12h RTSE13 RTSE12 RTSE11 RTSE10 RTSE03 RTSE02 RTSE01 RTSE00 RT/X port output control 13h RTCE XRHS XRVS1 XRVS0 HLSEL OFTS2 OFTS1 OFTS0 14h CM99 UPTCV AOSL1 AOSL0 XTOUTE AUTO1 APCK1 APCK0 VGATE start, FID change 15h VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0 VGATE stop 16h VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0 Miscellaneous, VGATE configuration and MSBs 17h LLCE LLC2E LATY2 LATY1 LATY0 VGPS VSTO8 VSTA8 Raw data gain control 18h RAWG7 RAWG6 RAWG5 RAWG4 RAWG3 RAWG2 RAWG1 RAWG0 Raw data offset control 19h RAWO7 RAWO6 RAWO5 RAWO4 RAWO3 RAWO2 RAWO1 RAWO0 SAF7118 84 of 175 © NXP B.V. 2008. All rights reserved. Analog/ADC/compatibility control Multistandard video decoder with adaptive comb filter Rev. 04 — 4 July 2008 Chrominance control 2 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx I2C-bus receiver/transmitter overview …continued Register function Subaddress D7 D6 D5 D4 D3 D2 D1 D0 1Ah to 1Dh [1] [1] [1] [1] [1] [1] [1] [1] Status byte 1 video decoder (read only) 1Eh - HLCK SLTCA GLIMT GLIMB WIPA DCSTD1 DCSTD0 Status byte 2 video decoder (read only) 1Fh INTL HLVLN FIDT - TYPE3 COLSTR COPRO RDCAP Reserved NXP Semiconductors SAF7118_4 Product data sheet Table 37. Component processing and interrupt masking part: registers 20h to 2Fh [1] [1] [1] [1] [1] [1] [1] [1] Analog input control 5 23h AOSL2 ADPE EXCLK REFA [1] EXMCE GAI48 GAI38 Analog input control 6 24h GAI37 GAI36 GAI35 GAI34 GAI33 GAI32 GAI31 GAI30 Analog input control 7 25h GAI47 GAI46 GAI45 GAI44 GAI43 GAI42 GAI41 GAI40 Reserved 26h to 28h [1] [1] [1] [1] [1] [1] [1] [1] Component delay 29h FSWE FSWI FSWDL1 FSWDL0 CMFI CPDL2 CPDL1 CPDL0 Component brightness control 2Ah CBRI7 CBRI6 CBRI5 CBRI4 CBRI3 CBRI2 CBRI1 CBRI0 Component contrast control 2Bh CCON7 CCON6 CCON5 CCON4 CCON3 CCON2 CCON1 CCON0 Component saturation control 2Ch CSAT7 CSAT6 CSAT5 CSAT4 CSAT3 CSAT2 CSAT1 CSAT0 2Dh [1] [1] [1] MVPSV MPPV MCCV [1] MERROF Interrupt mask 2 2Eh [1] MHLCK [1] [1] [1] [1] MDCSTD1 MDCSTD0 Interrupt mask 3 2Fh MINTL MHLVLN MFIDT [1] MTYPE3 MCOLSTR MCOPRO MRDCAP 30h ACPF7 ACPF6 ACPF5 ACPF4 ACPF3 ACPF2 ACPF0 31h ACPF15 ACPF14 ACPF13 ACPF12 ACPF11 ACPF10 ACPF9 ACPF8 32h [1] [1] [1] [1] [1] [1] ACPF17 ACPF16 Reserved 33h [1] [1] [1] [1] [1] [1] [1] [1] Audio master clock nominal increment 34h ACNI7 ACNI6 ACNI5 ACNI4 ACNI3 ACNI2 ACNI1 ACNI0 35h ACNI15 ACNI14 ACNI13 ACNI12 ACNI11 ACNI10 ACNI9 ACNI8 36h [1] [1] ACNI21 ACNI20 ACNI19 ACNI18 ACNI17 ACNI16 Reserved 37h [1] [1] [1] [1] [1] [1] [1] [1] Clock ratio AMXCLK to ASCLK 38h [1] [1] SDIV5 SDIV4 SDIV3 SDIV2 SDIV1 SDIV0 Clock ratio ASCLK to ALRCLK 39h [1] [1] LRDIV5 LRDIV4 LRDIV3 LRDIV2 LRDIV1 LRDIV0 Audio clock generator basic setup 3Ah [1] [1] [1] [1] APLL AMVR LRPH SCPH 3Bh to 3Fh [1] [1] [1] [1] [1] [1] [1] [1] Interrupt mask 1 Audio clock generator part: registers 30h to 3Fh Audio master clock cycles per field 85 of 175 © NXP B.V. 2008. All rights reserved. Reserved ACPF1 SAF7118 20h to 22h Multistandard video decoder with adaptive comb filter Rev. 04 — 4 July 2008 Reserved xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx I2C-bus receiver/transmitter overview …continued Register function Subaddress D7 D6 D5 D4 D3 D2 D1 D0 NXP Semiconductors SAF7118_4 Product data sheet Table 37. General purpose VBI data slicer part: registers 40h to 7Fh Slicer control 1 40h [1] HAM_N FCE HUNT_N [1] [1] [1] [1] LCR2 to LCR24 (n = 2 to 24) 41h to 57h LCRn_7 LCRn_6 LCRn_5 LCRn_4 LCRn_3 LCRn_2 LCRn_1 LCRn_0 Programmable framing code 58h FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 Horizontal offset for slicer 59h HOFF7 HOFF6 HOFF5 HOFF4 HOFF3 HOFF2 HOFF1 HOFF0 Vertical offset for slicer 5Ah VOFF7 VOFF6 VOFF5 VOFF4 VOFF3 VOFF2 VOFF1 VOFF0 VOFF8 [1] HOFF10 HOFF9 HOFF8 RECODE Reserved (for testing) 5Ch [1] [1] [1] [1] [1] [1] [1] [1] Header and data identification (DID) code control 5Dh FVREF [1] DID5 DID4 DID3 DID2 DID1 DID0 Sliced data identification (SDID) code 5Eh [1] [1] SDID5 SDID4 SDID3 SDID2 SDID1 SDID0 Reserved 5Fh [1] [1] [1] [1] [1] [1] [1] [1] Slicer status byte 0 (read only) 60h - FC8V FC7V VPSV PPV CCV - - Slicer status byte 1 (read only) 61h - - F21_N LN8 LN7 LN6 LN5 LN4 Slicer status byte 2 (read only) 62h LN3 LN2 LN1 LN0 DT3 DT2 DT1 DT0 63h to 7Fh [1] [1] [1] [1] [1] [1] [1] [1] 80h [1] SMOD TEB TEA ICKS3 ICKS2 ICKS1 ICKS0 Reserved 81h and 82h [1] [1] [1] [1] [1] [1] [1] [1] X port I/O enable and output clock phase control 83h [1] [1] XPCK1 XPCK0 [1] XRQT XPE1 XPE0 I port signal definitions 84h IDG01 IDG00 IDG11 IDG10 IDV1 IDV0 IDH1 IDH0 I port signal polarities 85h ISWP1 ISWP0 ILLV IG0P IG1P IRVP IRHP IDQP I port FIFO flag control and arbitration 86h VITX1 VITX0 IDG02 IDG12 FFL1 FFL0 FEL1 FEL0 [1] IPE1 IPE0 Reserved X port, I port and the scaler part: registers 80h to EFh Task independent global settings: 80h to 8Fh Global control 1 86 of 175 © NXP B.V. 2008. All rights reserved. I port I/O enable, output clock and gated 87h clock phase control IPCK3 IPCK2 IPCK1 IPCK0 [1] Power save/ADC port control 88h DOSL1 DOSL0 SWRST DPROG SLM3 [1] SLM1 SLM0 Reserved 89h to 8Eh [1] [1] [1] [1] [1] [1] [1] [1] Status information scaler part 8Fh XTRI ITRI FFIL FFOV PRDON ERROF FIDSCI FIDSCO SAF7118 FOFF Multistandard video decoder with adaptive comb filter Rev. 04 — 4 July 2008 Field offset and MSBs for horizontal and 5Bh vertical offset [1] xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx I2C-bus receiver/transmitter overview …continued Register function Subaddress D7 D6 D5 D4 D3 D2 D1 D0 NXP Semiconductors SAF7118_4 Product data sheet Table 37. Task A definition: registers 90h to BFh Basic settings and acquisition window definition Task handling control 90h CONLH OFIDC FSKP2 FSKP1 FSKP0 RPTSK STRC1 STRC0 X port formats and configuration 91h CONLV HLDFV SCSRC1 SCSRC0 SCRQE FSC2 FSC1 FSC0 X port input reference signal definition 92h XFDV XFDH XDV1 XDV0 XCODE XDH XDQ XCKS I port output formats and configuration 93h ICODE I8_16 FYSK FOI1 FOI0 FSI2 FSI1 FSI0 Horizontal input window start Horizontal input window length Vertical input window start Horizontal output window length Vertical output window length XO7 XO6 XO5 XO4 XO3 XO2 XO1 XO0 [1] [1] [1] [1] XO11 XO10 XO9 XO8 96h XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0 97h [1] [1] [1] [1] XS11 XS10 XS9 XS8 98h YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 99h [1] [1] [1] [1] YO11 YO10 YO9 YO8 9Ah YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0 9Bh [1] [1] [1] [1] YS11 YS10 YS9 YS8 9Ch XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 9Dh [1] [1] [1] [1] XD11 XD10 XD9 XD8 9Eh YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0 9Fh [1] [1] [1] [1] YD11 YD10 YD9 YD8 A0h [1] [1] XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0 Accumulation length A1h [1] [1] XACL5 XACL4 XACL3 XACL2 XACL1 XACL0 Prescaler DC gain and FIR prefilter control A2h PFUV1 PFUV0 PFY1 PFY0 XC2_1 XDCG2 XDCG1 XDCG0 Reserved A3h [1] [1] [1] [1] [1] [1] [1] [1] Luminance brightness control A4h BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 Luminance contrast control A5h CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 FIR filtering and prescaling Horizontal prescaling A6h SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 Reserved A7h [1] [1] [1] [1] [1] [1] [1] [1] SAF7118 87 of 175 © NXP B.V. 2008. All rights reserved. Chrominance saturation control Multistandard video decoder with adaptive comb filter Rev. 04 — 4 July 2008 Vertical input window length 94h 95h xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx I2C-bus receiver/transmitter overview …continued Register function Subaddress D7 D6 D5 D4 D3 D2 D1 D0 XSCY4 XSCY3 XSCY2 XSCY1 XSCY0 NXP Semiconductors SAF7118_4 Product data sheet Table 37. Horizontal phase scaling Horizontal luminance scaling increment A8h XSCY7 XSCY6 XSCY5 [1] [1] A9h [1] XSCY12 XSCY11 XSCY10 XSCY9 XSCY8 Horizontal luminance phase offset AAh XPHY7 XPHY6 XPHY5 XPHY4 XPHY3 XPHY2 XPHY1 XPHY0 Reserved ABh [1] [1] [1] [1] [1] [1] [1] [1] Horizontal chrominance scaling increment ACh XSCC7 XSCC6 XSCC5 XSCC4 XSCC3 XSCC2 XSCC1 XSCC0 ADh [1] [1] [1] XSCC12 XSCC11 XSCC10 XSCC9 XSCC8 Horizontal chrominance phase offset AEh XPHC7 XPHC6 XPHC5 XPHC4 XPHC3 XPHC2 XPHC1 XPHC0 Reserved AFh [1] [1] [1] [1] [1] [1] [1] [1] Vertical scaling Vertical luminance scaling increment YSCY7 YSCY6 YSCY5 YSCY4 YSCY3 YSCY2 YSCY1 YSCY0 YSCY15 YSCY14 YSCY13 YSCY12 YSCY11 YSCY10 YSCY9 YSCY8 B2h YSCC7 YSCC6 YSCC5 YSCC4 YSCC3 YSCC2 YSCC1 YSCC0 B3h YSCC15 YSCC14 YSCC13 YSCC12 YSCC11 YSCC10 YSCC9 YSCC8 Vertical scaling mode control B4h [1] [1] [1] YMIR [1] [1] [1] YMODE Reserved B5h to B7h [1] [1] [1] [1] [1] [1] [1] [1] Vertical chrominance phase offset ‘00’ B8h YPC07 YPC06 YPC05 YPC04 YPC03 YPC02 YPC01 YPC00 Vertical chrominance phase offset ‘01’ B9h YPC17 YPC16 YPC15 YPC14 YPC13 YPC12 YPC11 YPC10 Vertical chrominance phase offset ‘10’ BAh YPC27 YPC26 YPC25 YPC24 YPC23 YPC22 YPC21 YPC20 Vertical chrominance phase offset ‘11’ BBh YPC37 YPC36 YPC35 YPC34 YPC33 YPC32 YPC31 YPC30 Vertical luminance phase offset ‘00’ BCh YPY07 YPY06 YPY05 YPY04 YPY03 YPY02 YPY01 YPY00 Vertical luminance phase offset ‘01’ BDh YPY17 YPY16 YPY15 YPY14 YPY13 YPY12 YPY11 YPY10 Vertical luminance phase offset ‘10’ BEh YPY27 YPY26 YPY25 YPY24 YPY23 YPY22 YPY21 YPY20 Vertical luminance phase offset ‘11’ BFh YPY37 YPY36 YPY35 YPY34 YPY33 YPY32 YPY31 YPY30 Vertical chrominance scaling increment Task B definition registers C0h to EFh Task handling control C0h CONLH OFIDC FSKP2 FSKP1 FSKP0 RPTSK STRC1 STRC0 X port formats and configuration C1h CONLV HLDFV SCSRC1 SCSRC0 SCRQE FSC2 FSC1 FSC0 Input reference signal definition C2h XFDV XFDH XDV1 XDV0 XCODE XDH XDQ XCKS I port formats and configuration C3h ICODE I8_16 FYSK FOI1 FOI0 FSI2 FSI1 FSI0 SAF7118 88 of 175 © NXP B.V. 2008. All rights reserved. Basic settings and acquisition window definition Multistandard video decoder with adaptive comb filter Rev. 04 — 4 July 2008 B0h B1h xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx I2C-bus receiver/transmitter overview …continued Register function Subaddress Horizontal input window start C4h XO7 C5h [1] Horizontal input window length Vertical input window start Vertical input window length Horizontal output window length Vertical output window length D7 D6 D5 D4 D3 D2 D1 D0 XO6 XO5 XO4 XO3 XO2 XO1 XO0 [1] [1] [1] XO11 XO10 XO9 XO8 C6h XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0 C7h [1] [1] [1] [1] XS11 XS10 XS9 XS8 C8h YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 C9h [1] [1] [1] [1] YO11 YO10 YO9 YO8 CAh YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0 CBh [1] [1] [1] [1] YS11 YS10 YS9 YS8 CCh XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 CDh [1] [1] [1] [1] XD11 XD10 XD9 XD8 Rev. 04 — 4 July 2008 CEh YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0 CFh [1] [1] [1] [1] YD11 YD10 YD9 YD8 D0h [1] [1] XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0 Accumulation length D1h [1] [1] XACL5 XACL4 XACL3 XACL2 XACL1 XACL0 Prescaler DC gain and FIR prefilter control D2h PFUV1 PFUV0 PFY1 PFY0 XC2_1 XDCG2 XDCG1 XDCG0 Reserved D3h [1] [1] [1] [1] [1] [1] [1] [1] Luminance brightness control D4h BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 Luminance contrast control D5h CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 Chrominance saturation control D6h SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 D7h [1] [1] [1] [1] [1] [1] [1] [1] NXP Semiconductors SAF7118_4 Product data sheet Table 37. FIR filtering and prescaling Horizontal prescaling Horizontal phase scaling Horizontal luminance scaling increment D8h D9h Horizontal luminance phase offset XSCY7 XSCY6 XSCY5 XSCY4 XSCY3 XSCY2 XSCY1 XSCY0 [1] [1] [1] XSCY12 XSCY11 XSCY10 XSCY9 XSCY8 XPHY7 XPHY6 XPHY5 XPHY4 XPHY3 XPHY2 XPHY1 XPHY0 Reserved DBh [1] [1] [1] [1] [1] [1] [1] [1] Horizontal chrominance scaling increment DCh XSCC7 XSCC6 XSCC5 XSCC4 XSCC3 XSCC2 XSCC1 XSCC0 DDh [1] [1] [1] XSCC12 XSCC11 XSCC10 XSCC9 XSCC8 Horizontal chrominance phase offset DEh XPHC7 XPHC6 XPHC5 XPHC4 XPHC3 XPHC2 XPHC1 XPHC0 DFh [1] [1] [1] [1] [1] [1] [1] [1] Reserved SAF7118 89 of 175 © NXP B.V. 2008. All rights reserved. DAh Multistandard video decoder with adaptive comb filter Reserved xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx I2C-bus receiver/transmitter overview …continued Register function Subaddress D7 D6 D5 D4 D3 D2 D1 D0 E0h YSCY7 YSCY6 YSCY5 YSCY4 YSCY3 YSCY2 YSCY1 YSCY0 E1h YSCY15 YSCY14 YSCY13 YSCY12 YSCY11 YSCY10 YSCY9 YSCY8 E2h YSCC7 YSCC6 YSCC5 YSCC4 YSCC3 YSCC2 YSCC1 YSCC0 E3h YSCC15 YSCC14 YSCC13 YSCC12 YSCC11 YSCC10 YSCC9 YSCC8 E4h [1] [1] [1] YMIR [1] [1] [1] YMODE Reserved E5h to E7h [1] [1] [1] [1] [1] [1] [1] [1] Vertical chrominance phase offset ‘00’ E8h YPC07 YPC06 YPC05 YPC04 YPC03 YPC02 YPC01 YPC00 Vertical chrominance phase offset ‘01’ E9h YPC17 YPC16 YPC15 YPC14 YPC13 YPC12 YPC11 YPC10 Vertical chrominance phase offset ‘10’ EAh YPC27 YPC26 YPC25 YPC24 YPC23 YPC22 YPC21 YPC20 Vertical chrominance phase offset ‘11’ EBh YPC37 YPC36 YPC35 YPC34 YPC33 YPC32 YPC31 YPC30 Vertical luminance phase offset ‘00’ ECh YPY07 YPY06 YPY05 YPY04 YPY03 YPY02 YPY01 YPY00 Vertical luminance phase offset ‘01’ EDh YPY17 YPY16 YPY15 YPY14 YPY13 YPY12 YPY11 YPY10 Vertical luminance phase offset ‘10’ EEh YPY27 YPY26 YPY25 YPY24 YPY23 YPY22 YPY21 YPY20 Vertical luminance phase offset ‘11’ EFh YPY37 YPY36 YPY35 YPY34 YPY33 YPY32 YPY31 YPY30 NXP Semiconductors SAF7118_4 Product data sheet Table 37. Vertical scaling Vertical luminance scaling increment Vertical chrominance scaling increment Vertical scaling mode control All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements. SAF7118 90 of 175 © NXP B.V. 2008. All rights reserved. Multistandard video decoder with adaptive comb filter Rev. 04 — 4 July 2008 [1] SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.2 I2C-bus details 10.2.1 Subaddress 00h Table 38. Chip Version (CV) identification; 00h[7:4]; read only register Function Logic levels Chip Version (CV) ID7 ID6 ID5 ID4 CV3 CV2 CV1 CV0 10.2.2 Subaddress 01h The programming of the horizontal increment delay is used to match internal processing delays to the delay of the ADC. Use recommended position only. Table 39. Horizontal increment delay; 01h[6:0] Bit Description Symbol Value Function white peak control off WPOFF[1] 0 white peak control active (ADC signal is attenuated, if nominal luminance output white level is exceeded) 1 white peak control disabled 00 off 01 ±1 LSB 10 ±2 LSB 11 ±3 LSB 1111 no update 1110 minimum delay 0111 recommended position 0000 maximum delay D6 D[5:4] D[3:0] [1] update hysteresis for 9-bit gain; see Figure 9 increment delay GUDL[1:0] IDEL[3:0] HLNRS = 1 should not be used in combination with WPOFF = 0. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 91 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.2.3 Subaddress 02h Table 40. Analog input control 1 (AICO1); 02h[7:0][1] Bit Description Symbol Value Function D[7:6] analog function select; see Figure 4 and Figure 6 FUSE[1:0] 00 amplifier plus anti-alias filter bypassed 01 amplifier plus anti-alias filter bypassed 10 amplifier active 11 amplifier plus anti-alias filter active 00 0000 Mode 00: CVBS (automatic gain) from AI11; see Figure 50 00 0001 Mode 01: CVBS (automatic gain) from AI12; see Figure 51 00 0010 Mode 02: CVBS (automatic gain) from AI21; see Figure 52 00 0011 Mode 03: CVBS (automatic gain) from AI22; see Figure 53 00 0100 Mode 04: CVBS (automatic gain) from AI23; see Figure 54 00 0101 Mode 05: CVBS (automatic gain) from AI24; see Figure 55 00 0110 Mode 06: Y (automatic gain) from AI11 + C (gain adjustable via GAI28 to GAI20) from AI21[2]; see Figure 56 00 0111 Mode 07: Y (automatic gain) from AI12 + C (gain adjustable via GAI28 to GAI20) from AI22[2]; see Figure 57 00 1000 Mode 08: Y (automatic gain) from AI11 + C (gain adapted to Y gain) from AI21[2]; see Figure 58 00 1001 Mode 09: Y (automatic gain) from AI12 + C (gain adapted to Y gain) from AI22[2]; see Figure 59 00 1010 Mode 0A: Y (automatic gain) from AI13 + C (gain adjustable via GAI28 to GAI20) from AI23[2]; see Figure 60 00 1011 Mode 0B: Y (automatic gain) from AI14 + C (gain adjustable via GAI28 to GAI20) from AI24[2]; see Figure 61 00 1100 Mode 0C: Y (automatic gain) from AI13 + C (gain adapted to Y gain) from AI23[2]; see Figure 62 00 1101 Mode 0D: Y (automatic gain) from AI14 + C (gain adapted to Y gain) from AI24[2]; see Figure 63 CVBS modes 1 D[5:0] mode selection MODE[5:0] Y + C modes 1 D[5:0] mode selection MODE[5:0] SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 92 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 40. Analog input control 1 (AICO1); 02h[7:0][1] …continued Bit Description Symbol Value Function MODE[5:0] 00 1110 Mode 0E: CVBS (automatic gain) from AI13; see Figure 64 00 1111 Mode 0F: CVBS (automatic gain) from AI14; see Figure 65 01 0000 Mode 10: CVBS (automatic gain) from AI31; see Figure 66 01 0001 Mode 11: CVBS (automatic gain) from AI32; see Figure 67 01 0010 Mode 12: CVBS (automatic gain) from AI41; see Figure 68 01 0011 Mode 13: CVBS (automatic gain) from AI42; see Figure 69 01 0100 Mode 14: CVBS (automatic gain) from AI43; see Figure 70 01 0101 Mode 15: CVBS (automatic gain) from AI44; see Figure 71 01 0110 Mode 16: Y (automatic gain) from AI31 + C (gain adjustable via GAI28 to GAI20) from AI41[2]; see Figure 72 01 0111 Mode 17: Y (automatic gain) from AI32 + C (gain adjustable via GAI28 to GAI20) from AI42[2]; see Figure 73 01 1000 Mode 18: Y (automatic gain) from AI31 + C (gain adapted to Y gain) from AI41[2]; see Figure 74 01 1001 Mode 19: Y (automatic gain) from AI32 + C (gain adapted to Y gain) from AI42[2]; see Figure 75 01 1010 Mode 1A: Y (automatic gain) from AI33 + C (gain adjustable via GAI28 to GAI20) from AI43[2]; see Figure 76 01 1011 Mode 1B: Y (automatic gain) from AI34 + C (gain adjustable via GAI28 to GAI20) from AI44[2]; see Figure 77 01 1100 Mode 1C: Y (automatic gain) from AI33 + C (gain adapted to Y gain) from AI43[2]; see Figure 78 01 1101 Mode 1D: Y (automatic gain) from AI34 + C (gain adapted to Y gain) from AI44[2]; see Figure 79 01 1110 Mode 1E: CVBS (automatic gain) from AI33; see Figure 80 01 1111 Mode 1F: CVBS (automatic gain) from AI34; see Figure 81 CVBS modes 2 D[5:0] mode selection Y + C modes 2 D[5:0] mode selection MODE[5:0] CVBS modes 3 D[5:0] mode selection MODE[5:0] SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 93 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 40. Analog input control 1 (AICO1); 02h[7:0][1] …continued Bit Description Symbol Value Function MODE[5:0] 10 0000 Mode 20: SY-PB-PR (automatic gain for sync channel only) from AI11, AI21, AI31, AI41; see Figure 82 10 0001 Mode 21: SY-PB-PR (automatic gain for sync channel only) from AI12, AI22, AI32, AI42; see Figure 83 10 0010 to 10 1101 reserved 10 1110 Mode 2E: SY-PB-PR (automatic gain for sync channel only) from AI13, AI23, AI33, AI43; see Figure 84 10 1110 Mode 2F: SY-PB-PR (automatic gain for sync channel only) from AI14, AI24, AI34, AI44; see Figure 85 11 0000 Mode 30: SRGB (automatic gain for sync channel only) from AI11, AI21, AI31, AI41; see Figure 86 11 0001 Mode 31: SRGB (automatic gain for sync channel only) from AI12, AI22, AI32, AI42; see Figure 87 11 0010 to 11 1101 reserved 11 1110 Mode 3E: SRGB (automatic gain for sync channel only) from AI13, AI23, AI33, AI43; see Figure 90 11 1111 Mode 3F: SRGB (automatic gain for sync channel only) from AI14, AI24, AI34, AI44; see Figure 92 Y-PB-PR modes D[5:0] mode selection RGB modes D[5:0] mode selection MODE[5:0] SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 94 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 40. Analog input control 1 (AICO1); 02h[7:0][1] …continued Bit Description Symbol Value Function MODE[5:0] 00 0000 Mode 00: input AI11; REFA = 1, DOSL = 0, GAFIX = 1 00 0001 Mode 01: input AI12; REFA = 1, DOSL = 0, GAFIX = 1 00 1110 Mode 0E: input AI13; REFA = 1, DOSL = 0, GAFIX = 1 00 1111 Mode 0F: input AI14; REFA = 1, DOSL = 0, GAFIX = 1 00 0010 Mode 02: input AI21; REFA = 1, DOSL = 1, GAFIX = 1 00 0011 Mode 03: input AI22; REFA = 1, DOSL = 1, GAFIX = 1 00 0100 Mode 04: input AI23; REFA = 1, DOSL = 1, GAFIX = 1 00 0101 Mode 05: input AI24; REFA = 1, DOSL = 1, GAFIX = 1 01 0000 Mode 10: input AI31; REFA = 1, DOSL = 2, GAFIX = 1 01 0001 Mode 11: input AI32; REFA = 1, DOSL = 2, GAFIX = 1 01 1110 Mode 1E: input AI33; REFA = 1, DOSL = 2, GAFIX = 1 01 1111 Mode 1F: input AI34; REFA = 1, DOSL = 2, GAFIX = 1 01 0010 Mode 12: input AI41; REFA = 1, DOSL = 3, GAFIX = 1 01 0011 Mode 13: input AI42; REFA = 1, DOSL = 3, GAFIX = 1 01 0100 Mode 14: input AI43; REFA = 1, DOSL = 3, GAFIX = 1 01 0101 Mode 15: input AI44; REFA = 1, DOSL = 3, GAFIX = 1 VSB modes; see Figure 90 D[5:0] mode selection [1] Always refer to Table 70, usage of bits FSWE and FSWI. [2] To take full advantage of the Y/C modes 06 to 0D and 16 to 1D the I2C-bus bit BYPS (subaddress 09h, bit D7) should be set to logic 1 (full luminance bandwidth). SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 95 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter AI11 AI12 AI13 AI14 AD1 CHROMA AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 LUMA G B AD4 R MUX AI11 AI12 AI13 AI14 AD1 LUMA CHROMA AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 G B R MUX mhb738 Fig 50. Mode 00 CVBS1 AI11 AI12 AI13 AI14 AD1 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 Fig 51. Mode 01 CVBS2 LUMA CHROMA AI21 AI22 AI23 AI24 G B AD4 mhb739 R MUX AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AD1 LUMA CHROMA AD2 G AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 B R MUX mhb740 Fig 52. Mode 02 CVBS3 SAF7118_4 Product data sheet mhb741 Fig 53. Mode 03 CVBS4 © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 96 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter AI11 AI12 AI13 AI14 AD1 CHROMA AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 LUMA G B AD4 R MUX AI11 AI12 AI13 AI14 AD1 LUMA CHROMA AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 G B R MUX mhb743 mhb742 Fig 54. Mode 04 CVBS5 AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 AD1 Fig 55. Mode 05 CVBS6 LUMA CHROMA AD2 G AD3 B AD4 R MUX mhb744 Fig 56. Mode 06 YC1 (gain → GAI2 level) SAF7118_4 Product data sheet AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AD1 LUMA CHROMA AD2 G AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 B R MUX mhb745 Fig 57. Mode 07 YC2 (gain → GAI2 level) © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 97 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 AD1 LUMA CHROMA AD2 G AD3 B AD4 R MUX AD1 LUMA CHROMA AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 G B R MUX mhb746 mhb747 Fig 58. Mode 08 YC1 (gain adapted to Y gain) Fig 59. Mode 09 YC2 (gain adapted to Y gain) AI11 AI12 AI13 AI14 AD1 LUMA CHROMA AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 G B AD4 R MUX mhb748 Fig 60. Mode 0A YC3 (gain → GAI2 level) SAF7118_4 Product data sheet AI11 AI12 AI13 AI14 AI11 AI12 AI13 AI14 AD1 LUMA CHROMA AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 G B R MUX mhb749 Fig 61. Mode 0B YC4 (gain → GAI2 level) © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 98 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter AI11 AI12 AI13 AI14 AD1 CHROMA AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 LUMA G B AD4 R MUX AI11 AI12 AI13 AI14 AD1 LUMA CHROMA AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 G B R MUX mhb750 mhb751 Fig 62. Mode 0C YC3 (gain adapted to Y gain) Fig 63. Mode 0D YC4 (gain adapted to Y gain) AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 AD1 LUMA CHROMA AD2 G AD3 B AD4 R MUX AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AD1 LUMA CHROMA AD2 G AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 B R MUX mhb753 mhb752 Fig 64. Mode 0E CVBS7 SAF7118_4 Product data sheet Fig 65. Mode 0F CVBS8 © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 99 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter AI11 AI12 AI13 AI14 AD1 CHROMA AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 LUMA G B AD4 R MUX AI11 AI12 AI13 AI14 AD1 LUMA CHROMA AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 G B R MUX mhb754 Fig 66. Mode 10 CVBS9 AI11 AI12 AI13 AI14 AD1 AI21 AI22 AI23 AI24 AD2 Fig 67. Mode 11 CVBS10 LUMA CHROMA G AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 mhb755 B R MUX AI11 AI12 AI13 AI14 AD1 AI21 AI22 AI23 AI24 AD2 LUMA CHROMA G AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 B R MUX mhb756 Fig 68. Mode 12 CVBS11 SAF7118_4 Product data sheet mhb757 Fig 69. Mode 13 CVBS12 © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 100 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter AI11 AI12 AI13 AI14 AD1 CHROMA AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 LUMA G B AD4 R MUX AI11 AI12 AI13 AI14 AD1 LUMA CHROMA AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 G B R MUX mhb758 Fig 70. Mode 14 CVBS13 AI11 AI12 AI13 AI14 AD1 AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 Fig 71. Mode 15 CVBS14 LUMA CHROMA G AD3 B AD4 R MUX mhb760 Fig 72. Mode 16 YC5 (gain → GAI2 level) SAF7118_4 Product data sheet mhb759 AI11 AI12 AI13 AI14 AD1 AI21 AI22 AI23 AI24 AD2 LUMA CHROMA G AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 B R MUX mhb761 Fig 73. Mode 17 YC6 (gain → GAI2 level) © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 101 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter AI11 AI12 AI13 AI14 AD1 CHROMA AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 LUMA G B AD4 R MUX AI11 AI12 AI13 AI14 AD1 LUMA CHROMA AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 G B R MUX mhb763 mhb762 Fig 74. Mode 18 YC5 (gain adapted to Y gain) AI11 AI12 AI13 AI14 AD1 CHROMA AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 LUMA G B AD4 R MUX mhb764 Fig 76. Mode 1A YC7 (gain → GAI2 level) SAF7118_4 Product data sheet Fig 75. Mode 19 YC6 (gain adapted to Y gain) AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AD1 LUMA CHROMA AD2 G AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 B R MUX mhb765 Fig 77. Mode 1B YC8 (gain → GAI2 level) © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 102 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 AD1 LUMA CHROMA AD2 G AD3 B AD4 R MUX AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AD1 LUMA CHROMA AD2 G AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 B R MUX mhb766 Fig 78. Mode 1C YC7 (gain adapted to Y gain) AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 AD1 LUMA CHROMA AD2 G AD3 B AD4 R MUX mhb767 Fig 79. Mode 1D YC8 (gain adapted to Y gain) AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AD1 LUMA CHROMA AD2 G AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 B R MUX mhb768 Fig 80. Mode 1E CVBS15 SAF7118_4 Product data sheet mhb769 Fig 81. Mode 1F CVBS16 © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 103 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 AD1 SYNC (LUMA) (CHROMA) AD2 Y AD3 CB AD4 CR MUX AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AD1 SYNC (LUMA) (CHROMA) AD2 Y AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 CB CR MUX mhb770 Fig 82. Mode 20 SY-PB-PR1 AI11 AI12 AI13 AI14 AD1 AI21 AI22 AI23 AI24 AD2 Fig 83. Mode 21 SY-PB-PR2 SYNC (LUMA) (CHROMA) Y AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 mhb771 CB CR MUX AI11 AI12 AI13 AI14 AD1 AI21 AI22 AI23 AI24 AD2 SYNC (LUMA) (CHROMA) Y AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 CB CR MUX mhb772 Fig 84. Mode 2E SY-PB-PR3 SAF7118_4 Product data sheet mhb773 Fig 85. Mode 2F SY-PB-PR4 © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 104 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AI31 AI32 AI33 AI34 AI41 AI42 AI43 AI44 AD1 SYNC (LUMA) (CHROMA) AD2 G AD3 B AD4 R MUX AI11 AI12 AI13 AI14 AI21 AI22 AI23 AI24 AD1 SYNC (LUMA) (CHROMA) AD2 G AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 B R MUX mhb774 Fig 86. Mode 30 SRGB1 AI11 AI12 AI13 AI14 AD1 AI21 AI22 AI23 AI24 AD2 Fig 87. Mode 31 SRGB2 SYNC (LUMA) (CHROMA) G AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 mhb775 B R MUX AI11 AI12 AI13 AI14 AD1 AI21 AI22 AI23 AI24 AD2 SYNC (LUMA) (CHROMA) G AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 B R MUX mhb776 Fig 88. Mode 3E SRGB3 SAF7118_4 Product data sheet mhb777 Fig 89. Mode 3F SRGB4 © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 105 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter AI11 AI12 AI13 AI14 AD1 AI21 AI22 AI23 AI24 AD2 AI31 AI32 AI33 AI34 AD3 AI41 AI42 AI43 AI44 AD4 ADP [8:0] DOSL [1:0] MUX mhb778 Fig 90. VSB modes (use CVBS modes with REFA = 1, DOSL = 0 to 3 and GAFIX = 1) 10.2.4 Subaddress 03h Table 41. Analog input control 2 (AICO2); 03h[6:0] Bit Description Symbol Value Function D6 HL not reference select HLNRS 0 normal clamping if decoder is in unlocked state 1 reference select if decoder is in unlocked state D5 AGC hold during vertical blanking period VBSL 0 short vertical blanking (AGC disabled during equalization and serration pulses); recommended setting 1 long vertical blanking (AGC disabled from start of pre-equalization pulses until start of active video (line 22 for 60 Hz, line 24 for 50 Hz) 0 color peak control active (AD signal is attenuated, if maximum input level is exceeded, avoids clipping effects on screen) 1 color peak off 0 AGC active 1 AGC integration hold (freeze) 0 automatic gain controlled by MODE5 to MODE0 1 gain is user programmable via GAI[17:10] and GAI[27:20] D4 color peak off CPOFF D3 automatic gain control integration HOLDG D2 gain control fix GAFIX D1 static gain control channel 2 sign bit GAI28 see Table 43 D0 static gain control channel 1 sign bit GAI18 see Table 42 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 106 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.2.5 Subaddress 04h Table 42. Analog input control 3 (AICO3): static gain control channel 1; 03h[0] and 04h[7:0] Decimal value Gain (dB) Sign bit 03h[0] Control bits D7 to D0 GAI18 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10 0... −3 0 0 0 0 0 0 0 0 0 ...144 0 0 1 0 0 1 0 0 0 0 145... 0 0 1 0 0 1 0 0 0 1 ...511 +6 1 1 1 1 1 1 1 1 1 10.2.6 Subaddress 05h Table 43. Analog input control 4 (AICO4); static gain control channel 2; 03h[1] and 05h[7:0] Decimal value Gain (dB) Sign bit 03h[1] Control bits D7 to D0 GAI28 GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20 0... −3 0 0 0 0 0 0 0 0 0 ...144 0 0 1 0 0 1 0 0 0 0 145... 0 0 1 0 0 1 0 0 0 1 ...511 +6 1 1 1 1 1 1 1 1 1 10.2.7 Subaddress 06h Table 44. Horizontal sync start; 06h[7:0] Delay time (step size = 8 / LLC) Control bits D7 to D0 −128...−109 (50 Hz) forbidden (outside available central counter range) HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 −128...−108 (60 Hz) −108 (50 Hz)... 1 0 0 1 0 1 0 0 −107 (60 Hz)... 1 0 0 1 0 1 0 1 ...108 (50 Hz) 0 1 1 0 1 1 0 0 ...107 (60 Hz) 0 1 1 0 1 0 1 1 109...127 (50 Hz) forbidden (outside available central counter range) 108...127 (60 Hz) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 107 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.2.8 Subaddress 07h Table 45. Horizontal sync stop; 07h[7:0] Delay time (step size = 8 / LLC) Control bits D7 to D0 −128...−109 (50 Hz) forbidden (outside available central counter range) HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 −128...−108 (60 Hz) −108 (50 Hz)... 1 0 0 1 0 1 0 0 −107 (60 Hz)... 1 0 0 1 0 1 0 1 ...108 (50 Hz) 0 1 1 0 1 1 0 0 ...107 (60 Hz) 0 1 1 0 1 0 1 1 109...127 (50 Hz) forbidden (outside available central counter range) 108...127 (60 Hz) 10.2.9 Subaddress 08h Table 46. Sync control; 08h[7:0] Bit Description Symbol Value Function D7 automatic field detection AUFD 0 field state directly controlled via FSEL 1 automatic field detection; recommended setting 0 50 Hz, 625 lines 1 60 Hz, 525 lines 0 ODD/EVEN signal toggles only with interlaced source 1 ODD/EVEN signal toggles fieldwise even if source is non-interlaced 00 TV mode, recommended for poor quality TV signals only; do not use for new applications 01 VTR mode, recommended if a deflection control circuit is directly connected to the SAF7118 10 reserved 11 fast locking mode; recommended setting 0 PLL closed 1 PLL open; horizontal frequency fixed D6 field selection; active if AUFD = 0 FSEL D5 forced ODD/EVEN toggle FOET D[4:3] D2 D[1:0] horizontal time constant selection horizontal PLL vertical noise reduction HTC[1:0] HPLL VNOI[1:0] 00 normal mode; recommended setting 01 fast mode, applicable for stable sources only; automatic field detection (AUFD) must be disabled 10 free running mode 11 vertical noise reduction bypassed SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 108 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.2.10 Subaddress 09h Table 47. Luminance control; 09h[7:0] Bit Description Symbol Value Function D7 chrominance trap/comb filter bypass BYPS 0 chrominance trap or luminance comb filter active; default for CVBS mode 1 chrominance trap or luminance comb filter bypassed; default for S-video mode disabled (= chrominance trap enabled, if BYPS = 0) D6 adaptive luminance comb filter YCOMB 0 1 active, if BYPS = 0 D5 processing delay in non comb filter mode LDEL 0 processing delay is equal to internal pipelining delay; recommended setting 1 one (NTSC standards) or two (PAL standards) video lines additional processing delay 0 small remodulation bandwidth (narrow chroma notch ⇒ higher luminance bandwidth) 1 large remodulation bandwidth (wider chroma notch ⇒ smaller luminance bandwidth) 0001 resolution enhancement filter 8.0 dB at 4.1 MHz 0010 resolution enhancement filter 6.8 dB at 4.1 MHz 0011 resolution enhancement filter 5.1 dB at 4.1 MHz 0100 resolution enhancement filter 4.1 dB at 4.1 MHz 0101 resolution enhancement filter 3.0 dB at 4.1 MHz 0110 resolution enhancement filter 2.3 dB at 4.1 MHz 0111 resolution enhancement filter 1.6 dB at 4.1 MHz 0000 plain 1000 low-pass filter 2 dB at 4.1 MHz 1001 low-pass filter 3 dB at 4.1 MHz 1010 low-pass filter 3 dB at 3.3 MHz; 4 dB at 4.1 MHz 1011 low-pass filter 3 dB at 2.6 MHz; 8 dB at 4.1 MHz 1100 low-pass filter 3 dB at 2.4 MHz; 14 dB at 4.1 MHz 1101 low-pass filter 3 dB at 2.2 MHz; notch at 3.4 MHz 1110 low-pass filter 3 dB at 1.9 MHz; notch at 3.0 MHz 1111 low-pass filter 3 dB at 1.7 MHz; notch at 2.5 MHz D4 D[3:0] remodulation bandwidth for luminance; see Figure 14 to Figure 17 LUBW sharpness control, luminance filter characteristic; see Figure 18 LUFI[3:0] 10.2.11 Subaddress 0Ah Table 48. Luminance brightness control: decoder part; 0Ah[7:0] Offset Control bits D7 to D0 DBRI7 DBRI6 DBRI5 DBRI4 DBRI3 DBRI2 DBRI1 DBRI0 255 (bright) 1 1 1 1 1 1 1 1 128 (ITU level) 1 0 0 0 0 0 0 0 0 (dark) 0 0 0 0 0 0 0 0 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 109 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.2.12 Subaddress 0Bh Table 49. Luminance contrast control: decoder part; 0Bh[7:0] Gain Control bits D7 to D0 DCON7 DCON6 DCON5 DCON4 DCON3 DCON2 DCON1 DCON0 1.984 (maximum) 0 1 1 1 1 1 1 1 1.063 (ITU level) 0 1 0 0 0 1 0 0 1.0 0 1 0 0 0 0 0 0 0 (luminance off) 0 0 0 0 0 0 0 0 −1 (inverse luminance) 1 1 0 0 0 0 0 0 −2 (inverse luminance) 1 0 0 0 0 0 0 0 10.2.13 Subaddress 0Ch Table 50. Chrominance saturation control: decoder part; 0Ch[7:0] Gain Control bits D7 to D0 DSAT7 DSAT6 DSAT5 DSAT4 DSAT3 DSAT2 DSAT1 DSAT0 1.984 (maximum) 0 1 1 1 1 1 1 1 1.0 (ITU level) 0 1 0 0 0 0 0 0 0 (color off) 0 0 0 0 0 0 0 0 −1 (inverse chrominance) 1 1 0 0 0 0 0 0 −2 (inverse chrominance) 1 0 0 0 0 0 0 0 10.2.14 Subaddress 0Dh Table 51. Chrominance hue control; 0Dh[7:0] Hue phase (deg) Control bits D7 to D0 HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0 +178.6... 0 1 1 1 1 1 1 1 ...0... 0 0 0 0 0 0 0 0 ...−180 1 0 0 0 0 0 0 0 10.2.15 Subaddress 0Eh Table 52. Bit Chrominance control 1; 0Eh[7:0] Description Symbol Value Function 50 Hz/625 lines D7 clear DTO CDTO 60 Hz/525 lines 0 disabled 1 Every time CDTO is set, the internal subcarrier DTO phase is reset to 0° and the RTCO output generates a logic 0 at time slot 68 (see document “RTC Functional Description”, available on request). So an identical subcarrier phase can be generated by an external device (e.g. an encoder); if a DTO reset is programmed via CDTO it has always to be executed in the following way: 1. Set CDTO = 0 2. Set CDTO = 1 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 110 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 52. Bit Description D[6:4] D[6:4] D3 D2 14h[2] and 0Eh[1] D0 [1] Chrominance control 1; 0Eh[7:0] …continued color standard selection in non AUTO mode Symbol CSTD[2:0] CSTD[2:0] color standard selection in AUTO mode (AUTO mode is selected, if either AUTO0 or AUTO1 is set; see below) Value Function 50 Hz/625 lines 60 Hz/525 lines 000 PAL BGDHI (4.43 MHz) NTSC M (3.58 MHz) 001 NTSC 4.43 (50 Hz) PAL 4.43 (60 Hz) 010 Combination-PAL N (3.58 MHz) NTSC 4.43 (60 Hz) 011 NTSC N (3.58 MHz) PAL M (3.58 MHz) 100 reserved NTSC-Japan (3.58 MHz) 101 SECAM reserved 110 reserved; do not use 111 reserved; do not use 000 preferred standard[1] is PAL BGDHI (4.43 MHz) 001 reserved; do not use 010 reserved; do not use 011 reserved; do not use 100 preferred standard[1] is PAL BGDHI (4.43 MHz) preferred standard[1] is NTSC-Japan (3.58 MHz, no 7.5 IRE offset) 101 preferred standard[1] is SECAM preferred standard[1] is NTSC M (3.58 MHz) 110 reserved; do not use preferred standard[1] is NTSC M (3.58 MHz) 111 reserved; do not use disable chrominance vertical DCVF filter and PAL phase error correction 0 chrominance vertical filter and PAL phase error correction on (during active video lines) 1 chrominance vertical filter and PAL phase error correction permanently off fast color time constant 0 nominal time constant 1 fast time constant for special applications (high quality input source, fast chroma lock required, automatic standard detection off) 00 disabled 01 active, filter settings and sharpness control are preset to default values according to the detected standard and mode; recommended setting 10 active, filter settings are preset to default values according to the detected standard and mode 11 active, but no filter presets 0 disabled 1 active automatic chrominance standard detection control FCTC AUTO[1:0] adaptive chrominance comb CCOMB filter The meaning of ‘preferred standard’ is, that the internal search machine will always give priority to the selected standard, thus the recognition time for these standards is kept short. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 111 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.2.16 Subaddress 0Fh Table 53. Chrominance gain control; 0Fh[7:0] Bit Description D7 automatic chrominance gain ACGC control D[6:0] chrominance gain value (if ACGC is set to logic 1) Symbol CGAIN[6:0] Value Function 0 on; recommended setting 1 programmable gain via CGAIN6 to CGAIN0; need to be set for SECAM standard 000 0000 minimum gain (0.5) 010 0100 nominal gain (1.125) 111 1111 maximum gain (7.5) 10.2.17 Subaddress 10h Table 54. Chrominance control 2; 10h[7:0] Bit Description Symbol Value Function D[7:6] fine offset adjustment B − Y component OFFU[1:0] 00 0 LSB 01 1⁄ 4 LSB 10 1⁄ 2 LSB 11 3⁄ 4 LSB 00 0 LSB 01 1⁄ 4 LSB 10 1⁄ 2 LSB 11 3⁄ 4 LSB 0 small 1 wide 000 smallest chrominance bandwidth/largest luminance bandwidth ... ... to ... 111 largest chrominance bandwidth/smallest luminance bandwidth D[5:4] D3 D[2:0] fine offset adjustment R − Y component OFFV[1:0] CHBW chrominance bandwidth; see Figure 12 and Figure 13 combined luminance/chrominance bandwidth adjustment; see Figure 12 to Figure 18 LCBW[2:0] 10.2.18 Subaddress 11h Table 55. Mode/delay control; 11h[7:0] Bit Description Symbol Value Function D7 color on COLO 0 automatic color killer enabled; recommended setting 1 color forced on D6 polarity of RTS1 output signal RTP1 0 non-inverted 1 inverted fine position of HS (steps in 2 / LLC) HDEL[1:0] 00 0 01 1 10 2 11 3 0 non-inverted 1 inverted D[5:4] D3 polarity of RTS0 output signal RTP0 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 112 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 55. Mode/delay control; 11h[7:0] …continued Bit Description Symbol Value Function D[2:0] luminance delay compensation (steps in 2 / LLC) YDEL[2:0] 100 −4... 000 ...0... 011 ...3 10.2.19 Subaddress 12h Table 56. RT signal control: RTS0 output; 12h[3:0] The polarity of any signal on RTS0 can be inverted via RTP0[11h[3]]. RTS0 output RTSE03 RTSE02 RTSE01 RTSE00 3-state 0 0 0 0 Constant LOW 0 0 0 1 CREF (13.5 MHz toggling pulse; see Figure 34) 0 0 1 0 CREF2 (6.75 MHz toggling pulse; see Figure 34) 0 0 1 1 HL; horizontal lock indicator[1]: 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 HREF, horizontal reference signal; indicates 720 pixels valid data 1 on the expansion port. The positive slope marks the beginning of a new active line. HREF is also generated during the vertical blanking interval (see Figure 34). 0 0 0 HS: 1 0 0 1 HQ; HREF gated with VGATE 1 0 1 0 Reserved 1 0 1 1 V123; vertical sync (see vertical timing diagrams Figure 32 and Figure 33) 1 1 0 0 VGATE; programmable via VSTA[8:0] 17h[0] 15h[7:0], VSTO[8:0] 17h[1] 16h[7:0] and VGPS[17h[2]] 1 1 0 1 LSBs of the 9-bit ADCs 1 1 1 0 FID; position programmable via VSTA[8:0] 17h[0] 15h[7:0]; see vertical timing diagrams Figure 32 and Figure 33 1 1 1 1 HL = 0: unlocked HL = 1: locked VL; vertical and horizontal lock: VL = 0: unlocked VL = 1: locked DL; vertical and horizontal lock and color detected: DL = 0: unlocked DL = 1: locked Reserved Programmable width in LLC8 steps via HSB[7:0] 06h[7:0] and HSS[7:0] 07h[7:0] Fine position adjustment in LLC2 steps via HDEL[1:0] 11h[5:4] (see Figure 34) [1] Function of HL is selectable via HLSEL[13h[3]]: HLSEL = 0: HL is standard horizontal lock indicator. HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable time base e.g. VCRs). SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 113 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 57. RT signal control: RTS1 output; 12h[7:4] The polarity of any signal on RTS1 can be inverted via RTP1[11h[6]]. RTS1 output RTSE13 RTSE12 RTSE11 RTSE10 3-state 0 0 0 0 Constant LOW 0 0 0 1 CREF (13.5 MHz toggling pulse; see Figure 34) 0 0 1 0 CREF2 (6.75 MHz toggling pulse; see Figure 34) 0 0 1 1 indicator[1]: 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 HREF, horizontal reference signal; indicates 720 pixels valid data 1 on the expansion port. The positive slope marks the beginning of a new active line. HREF is also generated during the vertical blanking interval (see Figure 34). 0 0 0 HS: 1 0 0 1 HQ; HREF gated with VGATE 1 0 1 0 Reserved 1 0 1 1 V123; vertical sync; see vertical timing diagrams Figure 32 and Figure 33 1 1 0 0 VGATE; programmable via VSTA[8:0] 17h[0] 15h[7:0], VSTO[8:0] 17h[1] 16h[7:0] and VGPS[17h[2]] 1 1 0 1 Reserved 1 1 1 0 FID; position programmable via VSTA[8:0] 17h[0] 15h[7:0]; see vertical timing diagrams Figure 32 and Figure 33 1 1 1 1 HL; horizontal lock HL = 0: unlocked HL = 1: locked VL; vertical and horizontal lock: VL = 0: unlocked VL = 1: locked DL; vertical and horizontal lock and color detected: DL = 0: unlocked DL = 1: locked Reserved Programmable width in LLC8 steps via HSB[7:0] 06h[7:0] and HSS[7:0] 07h[7:0] Fine position adjustment in LLC2 steps via HDEL[1:0] 11h[5:4] (see Figure 34) [1] Function of HL is selectable via HLSEL[13h[3]]: HLSEL = 0: HL is standard horizontal lock indicator. HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable time base e.g. VCRs). SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 114 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.2.20 Subaddress 13h Table 58. RT/X port output control; 13h[7:0] Bit Description Symbol Value Function D7 RTCO output enable RTCE 0 3-state 1 enabled D6 X port XRH output selection XRHS 0 HREF; see Figure 34 1 HS: Programmable width in LLC8 steps via HSB[7:0] 06h[7:0] and HSS[7:0] 07h[7:0] Fine position adjustment in LLC2 steps via HDEL[1:0] 11h[5:4] (see Figure 34) D[5:4] D3 D[2:0] X port XRV output selection XRVS[1:0] horizontal lock indicator selection HLSEL XPD7 to XPD0 (port output format selection); see Section 9.5 OFTS[2:0] 00 V123 (see Figure 32 and Figure 33) 01 ITU 656 related field ID (see Figure 32 and Figure 33) 10 inverted V123 11 inverted ITU 656 related field ID 0 copy of inverted HLCK status bit (default) 1 fast horizontal lock indicator (for special applications only) 000 ITU 656 001 ITU 656 like format with modified field blanking according to VGATE position (programmable via VSTA[8:0] 17h[0] 15h[7:0], VSTO[8:0] 17h[1] 16h[7:0] and VGPS[17h[2]]) 010 Y-CB-CR 4 : 2 : 2 8-bit format (no SAV/EAV codes inserted) 011 reserved 100 multiplexed AD2/AD1 or AD4/AD3 bypass (bits D8 to D1) dependent on mode settings (see Section 10.2.3); if two ADCs are selected AD2/AD4 is output at CREF = 1 and AD1/AD3 is output at CREF = 0 101 multiplexed AD2/AD1 or AD4/AD3 bypass (bits D7 to D0) dependent on mode settings (see Section 10.2.3); if two ADCs are selected AD2/AD4 is output at CREF = 1 and AD1/AD3 is output at CREF = 0 110 reserved 111 multiplexed ADC MSB/LSB bypass dependent on mode settings; only one ADC should be selected at a time; ADx8 to ADx1 are outputs at CREF = 1 and ADx7 to ADx0 are outputs at CREF = 0 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 115 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.2.21 Subaddress 14h Table 59. Analog/ADC/auto/compatibility control; 14h[7:0] Bit Description Symbol Value Function D7 compatibility bit for SAA7199 CM99 0 off (default) 1 on (to be set only if SAA7199 is used for re-encoding in conjunction with RTCO active) 0 horizontal update (once per line) 1 vertical update (once per field) D6 23h[7] and 14h[5:4] D3 update time interval for AGC value UPTCV analog test select AOSL[2:0] XTOUT output enable XTOUTE D2 automatic chrominance standard detection control 1 AUTO1 D[1:0] ADC sample clock phase delay APCK[1:0] 000 AOUT connected to ground 001 AOUT connected to input AD1 010 AOUT connected to input AD2 011 AOUT connected to input AD3 100 AOUT connected to input AD4 101 reserved 110 reserved 111 AOUT connected to internal test point BPFOUT 0 XTOUT 3-stated 1 XTOUT enabled see Section 10.2.15 00 application dependent 01 application dependent 10 application dependent 11 application dependent 10.2.22 Subaddress 15h Table 60. VGATE start; FID polarity change; 17h[0] and 15h[7:0] Start of VGATE pulse (LOW-to-HIGH transition) and polarity change of FID pulse, VGPS = 0; see Figure 32 and Figure 33. Field 50 Hz 60 Hz Frame Decimal line value counting MSB 17h[0] Control bits D7 to D0 VSTA8 VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0 312 1 0 0 1 1 1 0 0 0 0... 0 0 0 0 0 0 0 0 0 ...310 1 0 0 1 1 0 1 1 1 262 1 0 0 0 0 0 1 1 0 0... 0 0 0 0 0 0 0 0 0 ...260 1 0 0 0 0 0 1 0 1 1st 1 2nd 314 1st 2 2nd 315 1st 312 2nd 625 1st 4 2nd 267 1st 5 2nd 268 1st 265 2nd 3 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 116 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.2.23 Subaddress 16h Table 61. VGATE stop; 17h[1] and 16h[7:0] Stop of VGATE pulse (HIGH-to-LOW transition), VGPS = 0; see Figure 32 and Figure 33. Field 50 Hz 60 Hz Frame Decimal line value counting MSB 17h[1] 1st 1 312 1 0 0 1 1 1 0 0 0 2nd 314 1st 2 0... 0 0 0 0 0 0 0 0 0 2nd 315 1st 312 ...310 1 0 0 1 1 0 1 1 1 2nd 625 262 1 0 0 0 0 0 1 1 0 0... 0 0 0 0 0 0 0 0 0 ...260 1 0 0 0 0 0 1 0 1 1st 4 2nd 267 1st 5 2nd 268 1st 265 2nd 3 Control bits D7 to D0 VSTO8 VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0 10.2.24 Subaddress 17h Table 62. Miscellaneous/VGATE MSBs; 17h[7:0] Bit Description Symbol Value Function D7 LLC output enable LLCE 0 enable 1 3-state D6 LLC2 output enable LLC2E 0 enable 1 3-state 000 reserved 001 one field 010 two fields 011 three fields; recommended setting ... ... to ... 111 seven fields 0 VGATE position according to Table 60 and Table 61 1 VGATE occurs one line earlier during field 2 D[5:3] D2 standard detection search loop latency alternative VGATE position LATY[2:0] VGPS D1 MSB VGATE stop VSTO8 see Table 61 D0 MSB VGATE start VSTA8 see Table 60 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 117 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.2.25 Subaddress 18h Table 63. Raw data gain control; RAWG[7:0] 18h[7:0]; see Figure 20 Gain Control bits D7 to D0 RAWG7 RAWG6 RAWG5 RAWG4 RAWG3 RAWG2 RAWG1 RAWG0 255 (double amplitude) 0 1 1 1 1 1 1 1 128 (nominal level) 0 1 0 0 0 0 0 0 0 (off) 0 0 0 0 0 0 0 0 10.2.26 Subaddress 19h Table 64. Raw data offset control; RAWO[7:0] 19h[7:0]; see Figure 20 Offset Control bits D7 to D0 RAWO7 RAWO6 RAWO5 RAWO4 RAWO3 RAWO2 RAWO1 RAWO0 −128 LSB 0 0 0 0 0 0 0 0 0 LSB 1 0 0 0 0 0 0 0 +128 LSB 1 1 1 1 1 1 1 1 10.2.27 Subaddress 1Eh Table 65. Status byte 1 video decoder; 1Eh[6:0]; read only register Bit Description I2C-bus control bit Value Function D6 status bit for locked horizontal frequency HLCK 0 locked 1 unlocked D5 D4 D3 D2 D[1:0] slow time constant active in WIPA mode SLTCA gain value for active luminance channel is limited; maximum (top) GLIMT gain value for active luminance channel is limited; minimum (bottom) GLIMB white peak loop is activated WIPA detected color standard DCSTD[1:0] SAF7118_4 Product data sheet 0 not active 1 active 0 not active 1 active 0 not active 1 active 0 not active 1 active 00 no color (black-white) 01 NTSC 10 PAL 11 SECAM © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 118 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.2.28 Subaddress 1Fh Table 66. Status byte 2 video decoder; 1Fh[7:5] and 1Fh[3:0]; read only register Bit Description I2C-bus control bit D7 status bit for interlace detection INTL status bit for horizontal and vertical loop HLVLN identification bit for detected field frequency FIDT Macrovision encoded color stripe burst type 3 (4 line version) detected TYPE3 Macrovision encoded color stripe burst detected (any type) COLSTR copy protected source detected according to Macrovision version up to 7.01 COPRO ready for capture (all internal loops locked) RDCAP D6 D5 D3 D2 D1 D0 Value Function 0 non-interlaced 1 interlaced 0 both loops locked 1 unlocked 0 50 Hz 1 60 Hz 0 not active 1 active 0 not active 1 active 0 not active 1 active 0 not active 1 active 10.3 Programming register RGB/Y-PB-PR component input processing 10.3.1 Subaddress 23h Table 67. Analog input control 5 (AICO5); 23h[7:4] and 23h[2:0] Bit Description Symbol Value D7 analog output select AOSL2 see Table 59 D6 AD port output enable ADPE 0 AD port is set to 3-state 1 AD port is enabled D5 ADC clock selector EXCLK 0 all ADCs are clocked by the internal generated line-locked clock 1 all ADCs are clocked by the external input clock on CLKEXT 0 clamping is dependent on HLNRS[03h[6]] 1 reference selection (input signal is pulled into ADC range) D4 D2 clamping/reference selection for all ADCs REFA enable external source switch EXMCE indicator input EXMCLR Function 0 disabled 1 enabled (any slope on EXMCLR input will reset the internal gain control loop) D1 static gain control channel 2 sign bit GAI48 see Table 69 D0 static gain control channel 1 sign bit GAI38 see Table 68 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 119 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.3.2 Subaddress 24h Table 68. Analog input control 6 (AICO6): static gain control channel 3; 23h[0] and 24h[7:0] Decimal value Gain (dB) Sign bit 23h[0] Control bits D7 to D0 GAI38 GAI37 GAI36 GAI35 GAI34 GAI33 GAI32 GAI31 GAI30 0... −3 0 0 0 0 0 0 0 0 0 ...144 0 0 1 0 0 1 0 0 0 0 145... 0 0 1 0 0 1 0 0 0 1 ...511 +6 1 1 1 1 1 1 1 1 1 GAI41 GAI40 10.3.3 Subaddress 25h Table 69. Decimal value Analog input control 7 (AICO7): static gain control channel 4; 23h[1] and 25h[7:0] Gain (dB) Sign bit 23h[1] Control bits D7 to D0 GAI48 GAI47 GAI46 GAI45 GAI44 GAI43 GAI42 0... −3 0 0 0 0 0 0 0 0 0 ...144 0 0 1 0 0 1 0 0 0 0 145... 0 0 1 0 0 1 0 0 0 1 ...511 +6 1 1 1 1 1 1 1 1 1 10.3.4 Subaddress 29h Table 70. Component delay/fast switch control; 29h[7:0] Bit Description Symbol Value Function D7 fast switch enable FSWE 0 disabled 1 pixelwise switching between decoded CVBS signal and component input signal is enabled (should only be used for component sources synchronous to CVBS input) 0 FSW = 0: decoded CVBS signal, FSW = 1: component signal 1 FSW = 1: decoded CVBS signal, FSW = 0: component signal 0 for modes 00h to 1Fh 1 for modes 20h to 3Fh D6 fast switch input polarity if FSWE = 1 FSWI static selection if FSWE = 0 D[5:4] D3 fast switch input delay adjustment relative to component input signal component luminance peaking FSWDL[1:0] CMFI 00 0 pixel (default) 01 +1 pixel 10 −2 pixel 11 −1 pixel 0 disabled 1 enabled (+1.5 dB at 5 MHz) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 120 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 70. Component delay/fast switch control; 29h[7:0] …continued Bit Description Symbol Value Function D[2:0] component input delay adjustment relative to decoded CVBS signal CPDL[2:0] 000 0 pixel (default) 001 +4 pixel 010 +8 pixel 011 +12 pixel 100 −16 pixel 101 −12 pixel 110 −8 pixel 111 −4 pixel 10.3.5 Subaddress 2Ah Table 71. Luminance brightness control component part; 2Ah[7:0] Offset Control bits D7 to D0 255 (bright) CBRI7 CBRI6 CBRI5 CBRI4 CBRI3 CBRI2 CBRI1 CBRI0 1 1 1 1 1 1 1 1 128 (ITU level) 1 0 0 0 0 0 0 0 0 (dark) 0 0 0 0 0 0 0 0 10.3.6 Subaddress 2Bh Table 72. Luminance contrast control component part; 2Bh[7:0] Gain Control bits D7 to D0 CCON7 CCON6 CCON5 CCON4 CCON3 CCON2 CCON1 CCON0 1.984 (maximum) 0 1 1 1 1 1 1 1 1.0 (ITU level) 0 1 0 0 0 0 0 0 0 (luminance off) 0 0 0 0 0 0 0 0 −1.0 (inverse luminance) 1 1 0 0 0 0 0 0 −2.0 (inverse luminance) 1 0 0 0 0 0 0 0 10.3.7 Subaddress 2Ch Table 73. Chrominance saturation control component part; 2Ch[7:0] Gain Control bits D7 to D0 CSAT7 CSAT6 CSAT5 CSAT4 CSAT3 CSAT2 CSAT1 CSAT0 1.984 (maximum) 0 1 1 1 1 1 1 1 1.0 (ITU level) 0 1 0 0 0 0 0 0 0 (color off) 0 0 0 0 0 0 0 0 −1.0 (inverse chrominance) 1 1 0 0 0 0 0 0 −2.0 (inverse chrominance) 1 0 0 0 0 0 0 0 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 121 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.4 Interrupt mask registers See also Section 9.4. 10.4.1 Subaddress 2Dh Table 74. Interrupt mask 1; 2Dh[4:2] and 2Dh[1] Bit Description Symbol D4 interrupt enable ‘VPS signal detected/lost’ (corresponding flag: 60h[4]) MVPSV D3 D2 D0 interrupt enable ‘PALplus detected/lost’ (corresponding flag: 60h[3]) MPPV interrupt enable ‘closed caption detected/lost’ (corresponding flag: 60h[2]) MCCV interrupt enable ‘error output formatter’ (corresponding flag: 8Fh[2]) MERROF Value Function 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 10.4.2 Subaddress 2Eh Table 75. Interrupt mask 2; 2Eh[6] and 2Eh[1:0] Bit Description Symbol Value Function D6 interrupt enable ‘horizontal PLL locked/unlocked’ (corresponding flag: 1Eh[6]) MHLCK 0 disabled 1 enabled D1 interrupt enable ‘color standard changed 1’ (corresponding flag: 1Eh[1]) MDCSTD1 0 disabled 1 enabled D0 interrupt enable ‘color standard changed 0’ (corresponding flag: 1Eh[0]) MDCSTD0 0 disabled 1 enabled Value Function 10.4.3 Subaddress 2Fh Table 76. Interrupt mask 3; 2Fh[7:5] and 2Fh[3:0] Bit Description Symbol D7 interrupt enable ‘interlaced/non-interlaced source’ (corresponding flag: 1Fh[7]) MINTL interrupt enable ‘horizontal and vertical lock reached/lost’ (corresponding flag: 1Fh[6]) MHLVLN interrupt enable ‘field frequency has changed’ (corresponding flag: 1Fh[5]) MFIDT interrupt enable ‘color stripe type 3 burst detected/lost’ (corresponding flag: 1Fh[3]) MTYPE3 interrupt enable ‘color stripe burst (any type) detected/lost’ (corresponding flag: 1Fh[2]) MCOLSTR interrupt enable ‘copy protected signal found/lost’ (corresponding flag: 1Fh[1]) MCOPRO interrupt enable ‘ready for capture/not ready’ (corresponding flag: 1Fh[0]) MRDCAP D6 D5 D3 D2 D1 D0 SAF7118_4 Product data sheet 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled 0 disabled 1 enabled © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 122 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.5 Programming register audio clock generation See equations in Section 8.7 and examples in Table 22 and Table 23. 10.5.1 Subaddresses 30h to 32h Table 77. Audio master clock (AMCLK) cycles per field Subaddress Control bits D7 to D0 30h ACPF7 ACPF6 ACPF5 ACPF4 ACPF3 ACPF2 ACPF1 ACPF0 31h ACPF15 ACPF14 ACPF13 ACPF12 ACPF11 ACPF10 ACPF9 ACPF8 32h - - - - - - ACPF17 ACPF16 10.5.2 Subaddresses 34h to 36h Table 78. Audio master clock (AMCLK) nominal increment Subaddress Control bits D7 to D0 34h ACNI7 ACNI6 ACNI5 ACNI4 ACNI3 ACNI2 ACNI1 ACNI0 35h ACNI15 ACNI14 ACNI13 ACNI12 ACNI11 ACNI10 ACNI9 ACNI8 36h - - ACNI21 ACNI20 ACNI19 ACNI18 ACNI17 ACNI16 SDIV2 SDIV1 SDIV0 LRDIV1 LRDIV0 10.5.3 Subaddress 38h Table 79. Clock ratio audio master clock (AMXCLK) to serial bit clock (ASCLK) Subaddress Control bits D7 to D0 38h - - SDIV5 SDIV4 SDIV3 10.5.4 Subaddress 39h Table 80. Clock ratio serial bit clock (ASCLK) to channel select clock (ALRCLK) Subaddress Control bits D7 to D0 39h - - LRDIV5 LRDIV4 LRDIV3 LRDIV2 10.5.5 Subaddress 3Ah Table 81. Audio clock control; 3Ah[3:0] Bit Description Symbol D3 audio PLL modes APLL D2 D1 D0 audio master clock vertical reference ALRCLK phase ASCLK phase AMVR LRPH SCPH Value 0 PLL active, AMCLK is field-locked 1 PLL open, AMCLK is free-running 0 vertical reference pulse is taken from internal decoder 1 vertical reference is taken from XRV input (expansion port) 0 ALRCLK edges triggered by falling edges of ASCLK 1 ALRCLK edges triggered by rising edges of ASCLK 0 ASCLK edges triggered by falling edges of AMCLK 1 ASCLK edges triggered by rising edges of AMCLK SAF7118_4 Product data sheet Function © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 123 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.6 Programming register VBI data slicer 10.6.1 Subaddress 40h Table 82. Slicer control 1; 40h[6:4] Bit Description Symbol Value Function D6 Hamming check HAM_N 0 Hamming check for 2 bytes after framing code, dependent on data type (default) 1 no Hamming check D5 framing code error FCE 0 one framing code error allowed 1 no framing code errors allowed 0 amplitude searching active (default) 1 amplitude searching stopped D4 amplitude searching HUNT_N 10.6.2 Subaddresses 41h to 57h Table 83. Line control register; LCR2 to LCR24 (41h to 57h) See Section 8.3 and Section 8.5. Name Description Framing code D[7:4] (41h to 57h) D[3:0] (41h to 57h) DT[3:0] 62h[3:0] (field 1) DT[3:0] 62h[3:0] (field 2) WST625 teletext EuroWST, CCST 27h 0000 0000 CC625 European closed caption 001 0001 0001 VPS video programming service 9951h 0010 0010 WSS wide screen signalling bits 1E 3C1Fh 0011 0011 WST525 US teletext (WST) 27h 0100 0100 CC525 US closed caption (line 21) 001 0101 0101 Test line video component signal, VBI region - 0110 0110 Intercast raw data - 0111 0111 General text teletext programmable 1000 1000 VITC625 VITC/EBU time codes (Europe) programmable 1001 1001 VITC525 VITC/SMPTE time codes (USA) programmable 1010 1010 Reserved reserved - 1011 1011 NABTS US NABTS - 1100 1100 Japtext MOJI (Japanese) programmable (A7h) 1101 1101 JFS Japanese format switch (L20/22) programmable 1110 1110 Active video video component signal, active video region (default) - 1111 1111 10.6.3 Subaddress 58h Table 84. Programmable framing code; slicer set 58h[7:0] According to Table 15 and Table 83. Framing code for programmable data types Control bits D7 to D0 Default value FC[7:0] = 40h SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 124 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.6.4 Subaddress 59h Table 85. Horizontal offset for slicer; slicer set 59h and 5Bh Horizontal offset Control bits 5Bh[2:0] Control bits 59h[7:0] Recommended value HOFF[10:8] = 3h HOFF[7:0] = 47h 10.6.5 Subaddress 5Ah Table 86. Vertical offset for slicer; slicer set 5Ah and 5Bh Vertical offset Control bit 5Bh[4] Control bits 5Ah[7:0] VOFF8 VOFF[7:0] Minimum value 0 0 00h Maximum value 312 1 38h Value for 50 Hz 625 lines input 0 03h Value for 60 Hz 525 lines input 0 06h 10.6.6 Subaddress 5Bh Table 87. Field offset, and MSBs for horizontal and vertical offsets; slicer set 5Bh[7:6] See Section 10.6.4 and Section 10.6.5 for HOFF[10:8] 5Bh[2:0] and VOFF8[5Bh[4]]. Bit Description Symbol Value Function D7 field offset FOFF 0 no modification of internal field indicator (default for 50 Hz 625 lines input sources) 1 invert field indicator (default for 60 Hz 525 lines input sources) 0 leave data unchanged (default) 1 convert 00h and FFh data bytes into 03h and FCh D6 recode RECODE 10.6.7 Subaddress 5Dh Table 88. Header and data identification (DID; ITU 656) code control; slicer set 5Dh[7:0] Bit Description Symbol Value Function D7 field ID and V-blank selection for text output (F and V reference selection) FVREF 0 F and V output of slicer is LCR table dependent 1 F and V output is taken from decoder real-time signals EVEN_ITU and VBLNK_ITU default; DID[5:0] = 00h DID[5:0] 00 0000 ANC header framing; see Figure 41 and Table 21 special cases of DID programming DID[5:0] 11 1110 DID[5:0] = 3Eh SAV/EAV framing, with FVREF = 1 11 1111 DID[5:0] = 3Fh SAV/EAV framing, with FVREF = 0 D[5:0] 10.6.8 Subaddress 5Eh Table 89. Sliced data identification (SDID) code; slicer set 5Eh[5:0] Bit Description Symbol Value Function D[5:0] SDID codes SDID[5:0] 00h default SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 125 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.6.9 Subaddress 60h Table 90. Slicer status byte 0; 60h[6:2]; read only register Bit Description Symbol Value Function D6 framing code valid FC8V 0 no framing code (0 error) in the last frame detected 1 framing code with 0 error detected 0 no framing code (1 error) in the last frame detected 1 framing code with 1 error detected 0 no VPS in the last frame 1 VPS detected 0 no PALplus in the last frame 1 PALplus detected 0 no closed caption in the last frame 1 closed caption detected D5 framing code valid FC7V D4 VPS valid VPSV D3 PALplus valid PPV D2 closed caption valid CCV 10.6.10 Subaddresses 61h and 62h Table 91. Slicer status byte 1; 61h[5:0] and slicer status byte 2; 62h[7:0]; read only registers Subaddress Bit Symbol Description 61h D5 F21_N field ID as seen by the VBI slicer; for field 1: D5 = 0 D[4:0] LN[8:4] line number D[7:4] LN[3:0] line number D[3:0] DT[3:0] data type; according to Table 15 62h 10.7 Programming register interfaces and scaler part 10.7.1 Subaddress 80h Table 92. Global control 1; global set 80h[6:4][1] SWRST moved to subaddress 88h[5]. Task enable control Control bits D6 to D4 SMOD TEB TEA Task of register set A is disabled X X 0 Task of register set A is enabled X X 1 Task of register set B is disabled X 0 X Task of register set B is enabled X 1 X The scaler window defines the F and V timing of the scaler output 0 X X VBI data slicer defines the F and V timing of the scaler output 1 X X [1] X = don’t care. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 126 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 93. Global control 1; global set 80h[3:0][1] I port and scaler back-end clock selection Control bits D3 to D0 ICKS3 ICKS2 ICKS1 ICKS0 ICLK output and back-end clock is line-locked clock LLC from decoder X X 0 0 ICLK output and back-end clock is XCLK from X port X X 0 1 ICLK output is LLC and back-end clock is LLC2 clock X X[2] 1 0 Back-end clock is the ICLK input X X 1 1 IDQ pin carries the data qualifier X 0 X X IDQ pin carries a gated back-end clock (DQ AND CLK) X 1 X X IDQ generation only for valid data 0 X X X IDQ qualifies valid data inside the scaling region and all data outside the 1 scaling region X X X [1] X = don’t care. [2] Although the ICLK I/O is independent of ICKS2 and ICKS3, this selection can only be used if ICKS2 = 1. 10.7.2 Subaddresses 83h to 87h Table 94. X port I/O enable and output clock phase control; global set 83h[5:4] Output clock phase control Control bits D5 and D4 XPCK1 XPCK0 XCLK default output phase, recommended value 0 0 XCLK output inverted 0 1 XCLK phase shifted by approximately 3 ns 1 0 XCLK output inverted and shifted by approximately 3 ns 1 1 Table 95. X port I/O enable and output clock phase control; global set 83h[2:0][1] X port I/O enable Control bits D2 to D0 XRQT XPE1 XPE0 X port output is disabled by software X 0 0 X port output is enabled by software X 0 1 X port output is enabled by pin XTRI at logic 0 X 1 0 X port output is enabled by pin XTRI at logic 1 X 1 1 XRDY output signal is A/B task flag from event handler (A = 1) 0 X X XRDY output signal is ready signal from scaler path (XRDY = 1 means the SAF7118 is ready to receive data) 1 X X [1] X = don’t care. Table 96. I port signal definitions; global set 84h[7:6] and 86h[5] I port signal definitions Control bits 86h[5] 84h[7:6] IDG02 IDG01 IDG00 IGP0 is output field ID, as defined by OFIDC[90h[6]] 0 0 0 IGP0 is A/B task flag, as defined by CONLH[90h[7]] 0 0 1 IGP0 is sliced data flag, framing the sliced VBI data at the I port 0 1 0 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 127 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 96. I port signal definitions; global set 84h[7:6] and 86h[5] …continued I port signal definitions Control bits IGP0 is set to logic 0 (default polarity) 86h[5] 84h[7:6] IDG02 IDG01 IDG00 0 1 1 IGP0 is the output FIFO almost filled flag 1 0 0 IGP0 is the output FIFO overflow flag 1 0 1 IGP0 is the output FIFO almost full flag, level to be programmed in subaddress 86h 1 1 0 IGP0 is the output FIFO almost empty flag, level to be programmed in subaddress 86h 1 1 1 Table 97. I port signal definitions; global set 84h[5:4] and 86h[4] I port signal definitions Control bits 86h[4] 84h[5:4] IDG12 IDG11 IDG10 IGP1 is output field ID, as defined by OFIDC[90h[6]] 0 0 0 IGP1 is A/B task flag, as defined by CONLH[90h[7]] 0 0 1 IGP1 is sliced data flag, framing the sliced VBI data at the I port 0 1 0 IGP1 is set to logic 0 (default polarity) 0 1 1 IGP1 is the output FIFO almost filled flag 1 0 0 IGP1 is the output FIFO overflow flag 1 0 1 IGP1 is the output FIFO almost full flag, level to be programmed in subaddress 86h 1 1 0 IGP1 is the output FIFO almost empty flag, level to be programmed in subaddress 86h 1 1 1 Table 98. I port output signal definitions; global set 84h[3:0][1] I port output signal definitions Control bits D3 to D0 IDV1 IDV0 IDH1 IDH0 IGPH is a H gate signal, framing the scaler output X X 0 0 IGPH is an extended H gate (framing H gate during scaler output and scaler input H reference outside the scaler window) X X 0 1 IGPH is a horizontal trigger pulse, on active going edge of H gate X X 1 0 IGPH is a horizontal trigger pulse, on active going edge of extended H gate X X 1 1 IGPV is a V gate signal, framing scaled output lines 0 0 X X IGPV is the V reference signal from scaler input 0 1 X X IGPV is a vertical trigger pulse, derived from V gate 1 0 X X IGPV is a vertical trigger pulse derived from input V reference 1 1 X X [1] X = don’t care. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 128 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 99. X port signal definitions text slicer; global set 85h[7:5][1] X port signal definitions text slicer Control bits D7 to D5 ISWP1 ISWP0 ILLV Video data limited to range 1 to 254 X X 0 Video data limited to range 8 to 247 X X 1 Double word byte swap, influences serial output timing D0 D1 D2 D3 ⇒ FF 00 00 SAV CB0 Y0 CR0 Y1 0 0 X D1 D0 D3 D2 ⇒ 00 FF SAV 00 Y0 CB0 Y1 CR0 0 1 X D2 D3 D0 D1 ⇒ 00 SAV FF 00 CR0 Y1 CB0 Y0 1 0 X D3 D2 D1 D0 ⇒ SAV 00 00 FF Y1 CR0 Y0 CB0 1 1 X [1] X = don’t care. Table 100. I port reference signal polarities; global set 85h[4:0][1] I port reference signal polarities Control bits D4 to D0 IG0P IG1P IRVP IRHP IDQP IDQ at default polarity (1 = active) X X X X 0 IDQ is inverted X X X X 1 IGPH at default polarity (1 = active) X X X 0 X IGPH is inverted X X X 1 X IGPV at default polarity (1 = active) X X 0 X X IGPV is inverted X X 1 X X IGP1 at default polarity X 0 X X X IGP1 is inverted X 1 X X X IGP0 at default polarity 0 X X X X IGP0 is inverted 1 X X X X [1] X = don’t care. Table 101. I port FIFO flag control and arbitration; global set 86h[7:4][1] Function Control bits D7 to D4 VITX1 VITX0 IDG02 IDG12 X X X 0 X X X 1 X X 0 X X X 1 X I port data output inhibited 0 0 X X Only video data is transferred 0 1 X X Only text data is transferred (no EAV, SAV will occur) 1 0 X X Text and video data is transferred, text has priority 1 1 X X See subaddress 84h: IDG11 and IDG10 See subaddress 84h: IDG01 and IDG00 I port signal definitions [1] X = don’t care. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 129 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 102. I port FIFO flag control and arbitration; global set 86h[3:0][1] I port FIFO flag control and arbitration Control bits D3 to D0 FFL1 FFL0 FEL1 FEL0 < 16 double words X X 0 0 < 8 double words X X 0 1 < 4 double words X X 1 0 0 double words X X 1 1 ≥ 16 double words 0 0 X X ≥ 24 double words 0 1 X X FAE FIFO flag almost empty level FAF FIFO flag almost full level [1] ≥ 28 double words 1 0 X X 32 double words 1 1 X X X = don’t care. Table 103. I port I/O enable, output clock and gated clock phase control; global set 87h[7:4][1] Output clock and gated clock phase control Control bits D7 to D4 IPCK3[2] IPCK2[2] IPCK1 IPCK0 X X 0 0 clock cycle ⇒ recommended for ICKS1 = 1 and X ICLK phase shifted by ICKS0 = 0 (subaddress 80h) X 0 1 ICLK phase shifted by approximately 3 ns X X 1 0 clock cycle + approximately ICLK phase shifted by 3 ns ⇒ alternatively to setting ‘01’ X X 1 1 IDQ = gated clock default output phase 0 0 X X 0 1 X X ICLK default output phase 1⁄ 2 1⁄ 2 IDQ = gated clock phase shifted by gated clock output 1⁄ 2 clock cycle ⇒ recommended for IDQ = gated clock phase shifted by approximately 3 ns 1 0 X X IDQ = gated clock phase shifted by 1⁄2 clock cycle + approximately 3 ns ⇒ alternatively to setting ‘01’ 1 1 X X [1] X = don’t care. [2] IPCK3 and IPCK2 only affect the gated clock (subaddress 80h, bit ICKS2 = 1). Table 104. I port I/O enable, output clock and gated clock phase control; global set 87h[1:0] I port I/O enable Control bits D1 and D0 IPE1 IPE0 I port output is disabled by software 0 0 I port output is enabled by software 0 1 I port output is enabled by pin ITRI at logic 0 1 0 I port output is enabled by pin ITRI at logic 1 1 1 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 130 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.7.3 Subaddress 88h Table 105. ADC port control; global set 88h[7:4][1] ADC port output control/start-up control Control bits D7 to D4 DPROG = 0 after reset DOSL1 DOSL0 SWRST[2] DPROG X X X 0 X DPROG = 1 can be used to assign that the device has been programmed; this bit can be monitored in the scalers status byte, bit PRDON; if DPROG was set to logic 1 and PRDON status bit shows a logic 0 a power-up or start-up fail has occurred X X 1 Scaler path is reset to its idle state, software reset X X 0 X Scaler is switched back to operation X X 1 X Digitized ADC1 signal is fed to port ADP[8:0] 0 0 X X Digitized ADC2 signal is fed to port ADP[8:0] 0 1 X X Digitized ADC3 signal is fed to port ADP[8:0] 1 0 X X Digitized ADC4 signal is fed to port ADP[8:0] 1 1 X X [1] X = don’t care. [2] Bit SWRST is now located here. Table 106. Power save control; global set 88h[3] and 88h[1:0][1] Power save control Control bits D3, D1 and D0 SLM3 SLM1 SLM0 X X 0 Decoder and VBI slicer are in Power-down mode; scaler only operates, if X scaler input and ICLK source is the X port (refer to subaddresses 80h and 91h/C1h) X 1 Scaler is in operational mode X 0 X Scaler is in Power-down mode; scaler in power-down stops I port output X 1 X Audio clock generation active 0 X X Audio clock generation in power-down and output disabled 1 X X Decoder and VBI slicer are in operational mode [1] X = don’t care. 10.7.4 Subaddress 8Fh Table 107. Status information scaler part; 8Fh[7:0]; read only register Bit I2C-bus status bit Function[1] D7 XTRI status on input pin XTRI, if not used for 3-state control, usable as hardware flag for software use D6 ITRI status on input pin ITRI, if not used for 3-state control, usable as hardware flag for software use D5 FFIL status of the internal ‘FIFO almost filled’ flag D4 FFOV status of the internal ‘FIFO overflow’ flag D3 PRDON copy of bit DPROG, can be used to detect power-up and start-up fails SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 131 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 107. Status information scaler part; 8Fh[7:0]; read only register …continued Bit I2C-bus status bit Function[1] D2 ERROF error flag of scalers output formatter, normally set, if the output processing needs to be interrupted, due to input/output data rate conflicts, e.g. if output data rate is much too low and all internal FIFO capacity used D1 FIDSCI status of the field sequence ID at the scalers input D0 FIDSCO status of the field sequence ID at the scalers output, scaler processing dependent [1] Status information is unsynchronized and shows the actual status at the time of I2C-bus read. 10.7.5 Subaddresses 90h and C0h Table 108. Task handling control; register set A [90h[7:6]] and B [C0h[7:6]][1] Event handler control Control bits D7 and D6 CONLH OFIDC Output field ID is field ID from scaler input X 0 Output field ID is task status flag, which changes every time a selected task is activated (not synchronized to input field ID) X 1 Scaler SAV/EAV byte bit D7 and task flag = 1, default 0 X Scaler SAV/EAV byte bit D7 and task flag = 0 1 X [1] X = don’t care. Table 109. Task handling control; register set A [90h[5:3]] and B [C0h[5:3]] Event handler control Control bits D5 to D3 Active task is carried out directly FSKP2 FSKP1 FSKP0 0 0 0 1 field is skipped before active task is carried out 0 0 1 ... fields are skipped before active task is carried out ... ... ... 6 fields are skipped before active task is carried out 1 1 0 7 fields are skipped before active task is carried out 1 1 1 Table 110. Task handling control; register set A [90h[2:0]] and B [C0h[2:0]][1] Event handler control Control bits D2 to D0 RPTSK STRC1 STRC0 Event handler triggers immediately after finishing a task X 0 0 Event handler triggers with next V-sync X 0 1 Event handler triggers with field ID = 0 X 1 0 Event handler triggers with field ID = 1 X 1 1 If active task is finished, handling is taken over by the next task 0 X X Active task is repeated once, before handling is taken over by the next task 1 X X [1] X = don’t care. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 132 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.7.6 Subaddresses 91h to 93h Table 111. X port formats and configuration; register set A [91h[7:3]] and B [C1h[7:3]][1] Scaler input format and configuration source selection Control bits D7 to D3 CONLV HLDFV SCSRC1 SCSRC0 SCRQE Only if XRQT[83h[2]] = 1: scaler input source reacts on SAF7118 request X X X X 0 Scaler input source is a continuous data stream, which cannot be interrupted (must be logic 1, if SAF7118 decoder part is source of scaler or XRQT[83h[2]] = 0) X X X X 1 Scaler input source is data from decoder, data type is provided according to Table 15 X X 0 0 X Scaler input source is Y-CB-CR data from X port X X 0 1 X Scaler input source is raw digital CVBS from selected analog channel, for backward compatibility only, further use is not recommended X X 1 0 X Scaler input source is raw digital CVBS (or 16-bit Y + CB-CR, if no 16-bit outputs are active) from X port X X 1 1 X SAV/EAV code bits D6 and D5 (F and V) may change between SAV and EAV X 0 X X X SAV/EAV code bits D6 and D5 (F and V) are synchronized to scalers output line start X 1 X X X SAV/EAV code bit D5 (V) and V gate on pin IGPV as generated by the internal processing; see Figure 47 0 X X X X SAV/EAV code bit D5 (V) and V gate are inverted 1 X X X X [1] X = don’t care. Table 112. X port formats and configuration; register set A [91h[2:0]] and B [C1h[2:0]][1] Scaler input format and configuration format control Control bits D2 to D0 FSC2[2] FSC1[2] FSC0 Input is Y-CB-CR 4 : 2 : 2 like sampling scheme X X 0 Input is Y-CB-CR 4 : 1 : 1 like sampling scheme X X 1 Chroma is provided every line, default 0 0 X Chroma is provided every 2nd line 0 1 X Chroma is provided every 3rd line 1 0 X Chroma is provided every 4th line 1 1 X [1] X = don’t care. [2] FSC2 and FSC1 only to be used, if X port input source does not provide chroma information for every input line. X port input stream must contain dummy chroma bytes. Table 113. X port input reference signal definitions; register set A [92h[7:4]] and B [C2h[7:4]][1] X port input reference signal definitions Control bits D7 to D4 XFDV XFDH XDV1 XDV0 Rising edge of XRV input and decoder V123 is vertical reference X X X 0 Falling edge of XRV input and decoder V123 is vertical reference X X X 1 XRV is a V-sync or V gate signal X X 0 X SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 133 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 113. X port input reference signal definitions; register set A [92h[7:4]] and B [C2h[7:4]][1] …continued X port input reference signal definitions Control bits D7 to D4 XFDV XFDH XDV1 XDV0 X X 1 X X port field ID is state of XRH at reference edge on XRV (defined by X XFDV) 0 X X Field ID (decoder and X port field ID) is inverted X 1 X X Reference edge for field detection is falling edge of XRV 0 X X X Reference edge for field detection is rising edge of XRV 1 X X X XRV is a frame sync, V pulses are generated internally on both edges of FS input [1] X = don’t care. Table 114. X port input reference signal definitions; register set A [92h[3:0]] and B [C2h[3:0]][1] X port input reference signal definitions Control bits D3 to D0 XCODE XDH XDQ XCKS XCLK input clock and XDQ input qualifier are needed X X X 0 Data rate is defined by XCLK only, no XDQ signal used X X X 1 Data are qualified at XDQ input at logic 1 X X 0 X Data are qualified at XDQ input at logic 0 X X 1 X Rising edge of XRH input is horizontal reference X 0 X X Falling edge of XRH input is horizontal reference X 1 X X Reference signals are taken from XRH and XRV 0 X X X Reference signals are decoded from EAV and SAV 1 X X X [1] X = don’t care. Table 115. I port output format and configuration; register set A [93h[7:5]] and B [C3h[7:5]][1] I port output formats and configuration Control bits D7 to D5 ICODE I8_16 FYSK All lines will be output X X 0 Skip the number of leading Y only lines, as defined by FOI1 and FOI0 X X 1 Double words are transferred byte wise, see subaddress 85h bits ISWP1 and ISWP0 X 0 X Double words are transferred 16-bit word wise via IPD and HPD, see subaddress 85h bits ISWP1 and ISWP0 X 1 X No ITU 656 like SAV/EAV codes are available 0 X X ITU 656 like SAV/EAV codes are inserted in the output data stream, 1 framed by a qualifier X X [1] X = don’t care. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 134 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 116. I port output format and configuration; register set A [93h[4:0]] and B [C3h[4:0]][1] I port output formats and configuration Control bits D4 to D0 FOI1 FOI0 FSI2 FSI1 FSI0 4 : 2 : 2 double word formatting X X 0 0 0 4 : 1 : 1 double word formatting X X 0 0 1 4 : 2 : 0, only every 2nd line Y + CB-CR output, in between Y only output X X 0 1 0 4 : 1 : 0, only every 4th line Y + CB-CR output, in between Y only output X X 0 1 1 Y only X X 1 0 0 Not defined X X 1 0 1 Not defined X X 1 1 0 Not defined X X 1 1 1 No leading Y only line, before 1st Y + CB-CR line is output 0 0 X X X 1 leading Y only line, before 1st Y + CB-CR line is output 0 1 X X X 2 leading Y only lines, before 1st Y + CB-CR line is output 1 0 X X X 3 leading Y only lines, before 1st Y + CB-CR line is output 1 1 X X X [1] X = don’t care. 10.7.7 Subaddresses 94h to 9Bh Table 117. Horizontal input window start; register set A [94h[7:0]; 95h[3:0]] and B [C4h[7:0]; C5h[3:0]] Horizontal input acquisition window Control bits definition offset in X (horizontal) A [95h[3:0]] and direction[1] B [C5h[3:0]] A [94h[7:0]] and B [C4h[7:0]] XO11 XO10 XO9 XO8 XO7 XO6 XO5 XO4 XO3 XO2 XO1 XO0 A minimum of ‘2’ should be kept, due to a line counting mismatch 0 0 0 0 0 0 0 0 0 0 1 0 Odd offsets are changing the CB-CR sequence in the output stream to CR-CB sequence 0 0 0 0 0 0 0 0 0 0 1 1 Maximum possible pixel offset = 4095 1 1 1 1 1 1 1 1 1 1 1 1 [1] Reference for counting are luminance samples. Table 118. Horizontal input window length; register set A [96h[7:0]; 97h[3:0]] and B [C6h[7:0]; C7h[3:0]] Horizontal input acquisition window Control bits definition input window length in A [97h[3:0]] and X (horizontal) direction[1] B [C7h[3:0]] A [96h[7:0]] and B [C6h[7:0]] XS11 XS10 XS9 XS8 XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0 No output 0 0 0 0 0 0 0 0 0 0 0 0 Odd lengths are allowed, but will be rounded up to even lengths 0 0 0 0 0 0 0 0 0 0 0 1 Maximum possible number of input pixels = 4095 1 1 1 1 1 1 1 1 1 1 1 1 [1] Reference for counting are luminance samples. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 135 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 119. Vertical input window start; register set A [98h[7:0]; 99h[3:0]] and B [C8h[7:0]; C9h[3:0]] Vertical input acquisition window definition offset in Y (vertical) direction[1] Control bits A [99h[3:0]] and B [C9h[3:0]] A [98h[7:0]] and B [C8h[7:0]] YO11 YO10 YO9 YO8 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 Line offset = 0 0 0 0 0 0 0 0 0 0 0 0 0 Line offset = 1 0 0 0 0 0 0 0 0 0 0 0 1 Maximum line offset = 4095 1 1 1 1 1 1 1 1 1 1 1 1 [1] For trigger condition: STRC[1:0] 90h[1:0] = 00; YO + YS > (number of input lines per field − 2), will result in field dropping. Other trigger conditions: YO > (number of input lines per field − 2), will result in field dropping. Table 120. Vertical input window length; register set A [9Ah[7:0]; 9Bh[3:0]] and B [CAh[7:0]; CBh[3:0]] Vertical input acquisition window definition input window length in Y (vertical) direction[1] Control bits A [9Bh[3:0]] and B [CBh[3:0]] A [9Ah[7:0]] and B [CAh[7:0]] YS11 YS10 YS9 YS8 YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0 No input lines 0 0 0 0 0 0 0 0 0 0 0 0 1 input line 0 0 0 0 0 0 0 0 0 0 0 1 Maximum possible number of input lines = 4095 1 1 1 1 1 1 1 1 1 1 1 1 [1] For trigger condition: STRC[1:0] 90h[1:0] = 00; YO + YS > (number of input lines per field − 2), will result in field dropping. Other trigger conditions: YS > (number of input lines per field − 2), will result in field dropping. 10.7.8 Subaddresses 9Ch to 9Fh Table 121. Horizontal output window length; register set A [9Ch[7:0]; 9Dh[3:0]] and B [CCh[7:0]; CDh[3:0]] Horizontal output acquisition window definition number of desired output pixels in X (horizontal) direction[1] Control bits A [9Dh[3:0]] and B [CDh[3:0]] A [9Ch[7:0]] and B [CCh[7:0]] XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 No output 0 0 0 0 0 0 0 0 0 0 0 0 Odd lengths are allowed, but will be filled up to even lengths 0 0 0 0 0 0 0 0 0 0 0 1 Maximum possible number of input pixels = 4095[2] 1 1 1 1 1 1 1 1 1 1 1 1 [1] Reference for counting are luminance samples. [2] If the desired output length is greater than the number of scaled output pixels, the last scaled pixel is repeated. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 136 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 122. Vertical output window length; register set A [9Eh[7:0]; 9Fh[3:0]] and B [CEh[7:0]; CFh[3:0]] Vertical output acquisition window Control bits definition number of desired output A [9Fh[3:0]] and lines in Y (vertical) direction B [CFh[3:0]] A [9Eh[7:0]] and B [CEh[7:0]] YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0 No output 0 0 0 0 0 0 0 0 0 0 0 0 1 pixel 0 0 0 0 0 0 0 0 0 0 0 1 Maximum possible number of output lines = 4095[1] 1 1 1 1 1 1 1 1 1 1 1 1 [1] If the desired output length is greater than the number of scaled output lines, the processing is cut. 10.7.9 Subaddresses A0h to A2h Table 123. Horizontal prescaling; register set A [A0h[5:0]] and B [D0h[5:0]] Horizontal integer prescaling ratio (XPSC) Control bits D5 to D0 XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0 Not allowed 0 0 0 0 0 0 Downscale = 1 0 0 0 0 0 1 0 0 0 0 1 0 ... ... ... ... ... ... 1 1 1 1 1 1 Downscale = 1⁄ 2 ... Downscale = 1⁄ 63 Table 124. Accumulation length; register set A [A1h[5:0]] and B [D1h[5:0]] Horizontal prescaler accumulation sequence length (XACL) Control bits D5 to D0 XACL5 XACL4 XACL3 XACL2 XACL1 XACL0 Accumulation length = 1 0 0 0 0 0 0 Accumulation length = 2 0 0 0 0 0 1 ... ... ... ... ... ... ... Accumulation length = 64 1 1 1 1 1 1 Table 125. Prescaler DC gain and FIR prefilter control; register set A [A2h[7:4]] and B [D2h[7:4]][1] FIR prefilter control Luminance FIR filter bypassed H_y(z) = 1⁄ 4 (1 2 1) H_y(z) = 1⁄8 (−1 1 1.75 4.5 1.75 1 −1) H_y(z) = 1⁄ 8 (1 2 2 2 1) Chrominance FIR filter bypassed H_uv(z) = 1⁄ 4 (1 2 1) H_uv(z) = 1⁄32 (3 8 10 8 3) H_uv(z) = [1] 1⁄ 8 (1 2 2 2 1) Control bits D7 to D4 PFUV1 PFUV0 PFY1 PFY0 X X 0 0 X X 0 1 X X 1 0 X X 1 1 0 0 X X 0 1 X X 1 0 X X 1 1 X X X = don’t care. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 137 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 126. Prescaler DC gain and FIR prefilter control; register set A [A2h[3:0]] and B [D2h[3:0]][1] Prescaler DC gain Control bits D3 to D0 XC2_1 XDCG2 XDCG1 XDCG0 Prescaler output is renormalized by gain factor = 1 X 0 0 0 Prescaler output is renormalized by gain factor = 1⁄2 X 0 0 1 Prescaler output is renormalized by gain factor = 1⁄4 X 0 1 0 Prescaler output is renormalized by gain factor = 1⁄ 8 X 0 1 1 Prescaler output is renormalized by gain factor = 1⁄ 16 X 1 0 0 Prescaler output is renormalized by gain factor = 1⁄32 X 1 0 1 Prescaler output is renormalized by gain factor = 1⁄ 64 X 1 1 0 Prescaler output is renormalized by gain factor = 1⁄ 128 X 1 1 1 Weighting of all accumulated samples is factor ‘1’; e.g. XACL = 4 ⇒ sequence 1 + 1 + 1 + 1 + 1 0 X X X Weighting of samples inside sequence is factor ‘2’; e.g. XACL = 4 ⇒ sequence 1 + 2 + 2 + 2 + 1 1 X X X [1] X = don’t care. 10.7.10 Subaddresses A4h to A6h Table 127. Luminance brightness control; register set A [A4h[7:0]] and B [D4h[7:0]] Luminance brightness control Control bits D7 to D0 BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 Value = 0 0 0 0 0 0 0 0 0 Nominal value = 128 1 0 0 0 0 0 0 0 Value = 255 1 1 1 1 1 1 1 1 Table 128. Luminance contrast control; register set A [A5h[7:0]] and B [D5h[7:0]] Luminance contrast control Control bits D7 to D0 CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 Gain = 0 0 0 0 0 0 0 0 0 Gain = 1⁄64 0 0 0 0 0 0 0 1 Nominal gain = 64 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Gain = 127⁄ 64 Table 129. Chrominance saturation control; register set A [A6h[7:0]] and B [D6h[7:0]] Chrominance saturation control Control bits D7 to D0 SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 Gain = 0 0 0 0 0 0 0 0 0 1⁄ 64 0 0 0 0 0 0 0 1 Nominal gain = 64 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Gain = Gain = 127⁄ 64 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 138 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.7.11 Subaddresses A8h to AEh Table 130. Horizontal luminance scaling increment; register set A [A8h[7:0]; A9h[7:0]] and B [D8h[7:0]; D9h[7:0]] Horizontal luminance scaling increment Control bits A [A9h[7:4]] B [D9h[7:4]] A [A9h[3:0]] B [D9h[3:0]] A [A8h[7:4]] B [D8h[7:4]] A [A8h[3:0]] B [D8h[3:0]] XSCY[15:12][1] XSCY[11:8] XSCY[7:4] XSCY[3:0] (theoretical) 0000 0000 0000 0000 Scale = 1024⁄294, lower limit defined by data path structure 0000 0001 0010 0110 Scale = 1024⁄1023 zoom 0000 0011 1111 1111 Scale = 1, equals 1024 0000 0100 0000 0000 Scale = 1024⁄1025 downscale 0000 0100 0000 0001 1111 1111 1111 Scale = zoom Scale = [1] 1024⁄ 1 1024⁄ 8191 downscale 0001 Bits XSCY[15:13] are reserved and are set to logic 0. Table 131. Horizontal luminance phase offset; register set A [AAh[7:0]] and B [DAh[7:0]] Horizontal luminance phase offset Control bits D7 to D0 XPHY7 XPHY6 XPHY5 Offset = 0 0 0 0 0 0 0 0 0 Offset = 1⁄32 pixel 0 0 0 0 0 0 0 1 Offset = 32⁄32 = 1 pixel 0 0 1 0 0 0 0 0 255⁄ 32 1 1 1 1 1 1 1 1 Offset = pixel XPHY4 XPHY3 XPHY2 XPHY1 XPHY0 Table 132. Horizontal chrominance scaling increment; register set A [ACh[7:0]; ADh[7:0]] and B [DCh[7:0]; DDh[7:0]] Horizontal chrominance scaling increment This value must be set to the luminance value 1⁄ XSCY[15:0] 2 [1] Control bits A [ADh[7:4]] B [DDh[7:4]] A [ADh[3:0]] B [DDh[3:0]] A [ACh[7:4]] B [DCh[7:4]] A [ACh[3:0]] B [DCh[3:0]] XSCC[15:12][1] XSCC[11:8] XSCC[7:4] XSCC[3:0] 0000 0000 0000 0000 0000 0000 0000 0001 0001 1111 1111 1111 Bits XSCC[15:13] are reserved and are set to logic 0. Table 133. Horizontal chrominance phase offset; register set A [AEh[7:0]] and B [DEh[7:0]] Horizontal chrominance phase offset Control bits D7 to D0 XPHC7 XPHC6 XPHC5 XPHC4 XPHC3 XPHC2 XPHC1 XPHC0 This value must be set to 1⁄ XPHY[7:0] 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 139 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 10.7.12 Subaddresses B0h to BFh Table 134. Vertical luminance scaling increment; register set A [B0h[7:0]; B1h[7:0]] and B [E0h[7:0]; E1h[7:0]] Vertical luminance scaling Control bits increment A [B1h[7:4]] B [E1h[7:4]] A [B1h[3:0]] B [E1h[3:0]] A [B0h[7:4]] B [E0h[7:4]] A [B0h[3:0]] B [E0h[3:0]] YSCY[15:12] YSCY[11:8] YSCY[7:4] YSCY[3:0] 0000 0000 0000 0001 Scale = 1024⁄1023 zoom 0000 0011 1111 1111 Scale = 1, equals 1024 0000 0100 0000 0000 downscale 0000 0100 0000 0001 1111 1111 1111 Scale = zoom 1024⁄ 1 (theoretical) Scale = 1024⁄ 1025 Scale = 1⁄ 63.999 downscale 1111 Table 135. Vertical chrominance scaling increment; register set A [B2h[7:0]; B3h[7:0]] and B [E2h[7:0]; E3h[7:0]] Vertical chrominance scaling increment Control bits YSCC[15:12] YSCC[11:8] YSCC[7:4] YSCC[3:0] This value must be set to the luminance value YSCY[15:0] 0000 0000 0000 0001 1111 1111 1111 1111 A [B3h[7:4]] B [E3h[7:4]] A [B3h[3:0]] B [E3h[3:0]] A [B2h[7:4]] B [E2h[7:4]] A [B2h[3:0]] B [E2h[3:0]] Table 136. Vertical scaling mode control; register set A [B4h[4 and 0]] and B [E4h[4 and 0]][1] Vertical scaling mode control Control bits D4 and D0 YMIR YMODE Vertical scaling performs linear interpolation between lines X 0 Vertical scaling performs higher order accumulating interpolation, better alias suppression X 1 No mirroring 0 X Lines are mirrored 1 X [1] X = don’t care. Table 137. Vertical chrominance phase offset ‘00’; register set A [B8h[7:0]] and B [E8h[7:0]] Vertical chrominance phase offset Control bits D7 to D0 YPC07 YPC06 YPC05 YPC04 YPC03 YPC02 YPC01 YPC00 Offset = 0 0 0 0 0 0 0 0 0 Offset = 32⁄32 = 1 line 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 Offset = 255⁄ 32 lines SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 140 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 138. Vertical luminance phase offset ‘00’; register set A [BCh[7:0]] and B [ECh[7:0]] Vertical luminance phase offset Control bits D7 to D0 YPY07 YPY06 YPY05 YPY04 YPY03 YPY02 YPY01 YPY00 Offset = 0 0 0 0 0 0 0 0 0 Offset = 32⁄32 = 1 line 0 0 1 0 0 0 0 0 Offset = 255⁄32 lines 1 1 1 1 1 1 1 1 11. Programming start setup 11.1 Decoder part The given values force the following behavior of the SAF7118 decoder part: • The analog input AI11 expects an NTSC M, PAL B, D, G, H and I or SECAM signal in CVBS format; analog anti-alias filter and AGC active • • • • • Automatic field detection enabled Standard ITU 656 output format enabled on expansion (X) port Contrast, brightness and saturation control in accordance with ITU standards Adaptive comb filter for luminance and chrominance activated Pins LLC, LLC2, XTOUT, RTS0, RTS1 and RTCO are set to 3-state Table 139. Decoder part start setup values for the three main standards Subaddress Register function (hexadecimal) Bit name[1] 00 chip version ID7 to ID4 read only 01 increment delay X, WPOFF, GUDL1, GUDL0 and IDEL3 to IDEL0 47 47 47 02 analog input control 1 FUSE1, FUSE0 and MODE5 to MODE0 C0 C0 C0 03 analog input control 2 X, HLNRS, VBSL, CPOFF, HOLDG, 10 GAFIX, GAI28 and GAI18 10 10 04 analog input control 3 GAI17 to GAI10 90 90 90 05 analog input control 4 GAI27 to GAI20 90 90 90 06 horizontal sync start HSB7 to HSB0 EB EB EB 07 horizontal sync stop HSS7 to HSS0 E0 E0 E0 08 sync control AUFD, FSEL, FOET, HTC1, HTC0, HPLL, VNOI1 and VNOI0 98 98 98 09 luminance control BYPS, YCOMB, LDEL, LUBW and LUFI3 to LUFI0 40 40 1B 0A luminance brightness control DBRI7 to DBRI0 80 80 80 0B luminance contrast control DCON7 to DCON0 44 44 44 0C chrominance saturation control DSAT7 to DSAT0 40 40 40 0D chrominance hue control HUEC7 to HUEC0 00 00 00 0E chrominance control 1 CDTO, CSTD2 to CSTD0, DCVF, FCTC, AUTO0 and CCOMB 89 81 D0 NTSC M SAF7118_4 Product data sheet Values (hexadecimal) PAL B, D, SECAM G, H and I © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 141 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 139. Decoder part start setup values for the three main standards …continued Subaddress Register function (hexadecimal) Bit name[1] 0F chrominance gain control 10 Values (hexadecimal) NTSC M PAL B, D, SECAM G, H and I ACGC and CGAIN6 to CGAIN0 2A 2A 80 chrominance control 2 OFFU1, OFFU0, OFFV1, OFFV0, CHBW and LCBW2 to LCBW0 0E 06 00 11 mode/delay control COLO, RTP1, HDEL1, HDEL0, RTP0 and YDEL2 to YDEL0 00 00 00 12 RT signal control RTSE13 to RTSE10 and RTSE03 to RTSE00 00 00 00 13 RT/X port output control RTCE, XRHS, XRVS1, XRVS0, HLSEL and OFTS2 to OFTS0 00 00 00 14 analog/ADC/compatibility control CM99, UPTCV, AOSL1, AOSL0, XTOUTE, AUTO1, APCK1 and APCK0 00 00 00 15 VGATE start, FID change VSTA7 to VSTA0 11 11 11 16 VGATE stop VSTO7 to VSTO0 FE FE FE 17 miscellaneous, VGATE configuration and MSBs LLCE, LLC2E, LATY2 to LATY0, VGPS, VSTO8 and VSTA8 C0 C0 C0 18 raw data gain control RAWG7 to RAWG0 40 40 40 19 raw data offset control RAWO7 to RAWO0 80 80 80 1A to 1D reserved X, X, X, X, X, X, X, X 00 00 00 1E status byte 1 video decoder -, HLCK, SLTCA, GLIMT, GLIMB, WIPA, DCSTD1 and DCSTD0 read only 1F status byte 2 video decoder INTL, HLVLN, FIDT, -, TYPE3, COLSTR, COPRO and RDCAP read only [1] All X values must be set to logic 0. 11.2 Component video part and interrupt mask The given values force the following behavior of the SAF7118 component video part: • The analog inputs AI11, AI21, AI31 and AI41 expect an RGBS signal; analog anti-alias filters and AGC for the sync channel active • For other settings see decoder part (Section 11.1) Table 140. Component video part and interrupt mask start setup values Subaddress Register function (hexadecimal) Bit name[1] Values (hexadecimal) 23 analog input control 5 AOSL2, ADPE, EXCLK, REFA, X, EXMCE, GAI48 and GAI38 00 24 analog input control 6 GAI37 to GAI30 90 25 analog input control 7 GAI47 to GAI40 90 26 to 28 reserved X, X, X, X, X, X, X, X 00 29 component delay FSWE, FSWI, FSWDL1, FSWDL0, CMFI, CPDL2 to CPDL0 40 2A component brightness control CBRI7 to CBRI0 80 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 142 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 140. Component video part and interrupt mask start setup values …continued Subaddress Register function (hexadecimal) Bit name[1] Values (hexadecimal) 2B component contrast control CCON7 to CCON0 40 2C component saturation control CSAT7 to CSAT0 47 2D interrupt mask 1 X, X, X, MVPSV, MPPV, MCCV, X and MERROF 00 2E interrupt mask 2 X, MHLCK, X, X, X, X, MDCSTD1 and MDCSTD0 00 2F interrupt mask 3 MINTL, MHLVLN, MFIDT, X, MTYPE3, MCOLSTR, MCOPRO and MRDCAP 00 [1] All X values must be set to logic 0. 11.3 Audio clock generation part The given values force the following behavior of the SAF7118 audio clock generation part: • Used crystal is 24.576 MHz • Expected field frequency is 59.94 Hz (e.g. NTSC M standard) • Generated audio master clock frequency at pin AMCLK is 256 × 44.1 kHz = 11.2896 MHz • AMCLK is externally connected to AMXCLK [short-cut between pins P11 (72) and M12 (76)] • ASCLK = 32 × 44.1 kHz = 1.4112 MHz • ALRCLK is 44.1 kHz Table 141. Audio clock part setup values Subaddress Register function (hexadecimal) Bit name[1] Values (binary) 30 audio master clock cycles per field; bits D7 to D0 ACPF7 to ACPF0 1 0 1 1 1 1 0 0 BC 31 audio master clock cycles per field; bits D15 to D8 ACPF15 to ACPF8 1 1 0 1 1 1 1 1 DF 32 audio master clock cycles per field; bits D17 and D16 X, X, X, X, X, X, ACPF17 and ACPF16 0 0 0 0 0 0 1 0 02 33 reserved X, X, X, X, X, X, X, X 0 0 0 0 0 0 0 0 00 34 audio master clock nominal increment; bits D7 to D0 ACNI7 to ACNI0 1 1 0 0 1 1 0 1 CD 35 audio master clock nominal increment; bits D15 to D8 ACNI15 to ACNI8 1 1 0 0 1 1 0 0 CC 36 audio master clock nominal increment; bits D21 to D16 X, X, ACNI21 to ACNI16 0 0 1 1 1 0 1 0 3A 37 reserved X, X, X, X, X, X, X, X 0 0 0 0 0 0 0 0 00 38 clock ratio AMXCLK to ASCLK X, X, SDIV5 to SDIV0 0 0 0 0 0 0 1 1 03 39 clock ratio ASCLK to ALRCLK X, X, LRDIV5 to LRDIV0 0 0 0 1 0 0 0 0 10 3A audio clock generator basic setup X, X, X, X, APLL, AMVR, LRPH, SCPH 0 0 0 0 0 0 0 0 00 3B to 3F reserved X, X, X, X, X, X, X, X 0 0 0 0 0 0 0 0 00 [1] Start 7 6 5 4 3 2 1 0 (hexadecimal) All X values must be set to logic 0. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 143 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 11.4 Data slicer and data type control part The given values force the following behavior of the SAF7118 VBI data slicer part: • Closed captioning data are expected at line 21 of field 1 (60 Hz/525 line system) • All other lines are processed as active video • Sliced data are framed by ITU 656 like SAV/EAV sequence (DID[5:0] = 3Eh ⇒ MSB of SAV/EAV = 1) Table 142. Data slicer start setup values Subaddress Register function (hexadecimal) Bit name[1] 40 slicer control 1 X, HAM_N, FCE, HUNT_N, X, X, 0 1 0 0 0 0 0 0 40 X, X 41 to 53 line control register 2 to 20 LCRn_7 to LCRn_0 (n = 2 to 20) 1 1 1 1 1 1 1 1 FF 54 line control register 21 LCR21_7 to LCR21_0 0 1 0 1 1 1 1 1 5F 55 to 57 line control register 22 to 24 LCRn_7 to LCRn_0 (n = 22 to 24) 1 1 1 1 1 1 1 1 FF 58 programmable framing code FC7 to FC0 0 0 0 0 0 0 0 0 00 59 horizontal offset for slicer HOFF7 to HOFF0 0 1 0 0 0 1 1 1 47 5A vertical offset for slicer VOFF7 to VOFF0 0 0 0 0 0 1 1 0 06[2] 5B field offset and MSBs for horizontal and vertical offset FOFF, RECODE, X, VOFF8, X, HOFF10 to HOFF8 1 0 0 0 0 0 1 1 83[2] 5C reserved X, X, X, X, X, X, X, X 0 0 0 0 0 0 0 0 00 5D header and data identification code control FVREF, X, DID5 to DID0 0 0 1 1 1 1 1 0 3E 5E sliced data identification code X, X, SDID5 to SDID0 0 0 0 0 0 0 0 0 00 5F reserved X, X, X, X, X, X, X, X 0 0 0 0 0 0 0 0 00 60 slicer status byte 0 -, FC8V, FC7V, VPSV, PPV, CCV, read only register -, - 61 slicer status byte 1 -, -, F21_N, LN8 to LN4 read only register 62 slicer status byte 2 LN3 to LN0, DT3 to DT0 read only register [1] All X values must be set to logic 0. [2] Changes for 50 Hz/625 line systems: subaddress 5Ah = 03h and subaddress 5Bh = 03h. SAF7118_4 Product data sheet Values (binary) Start 7 6 5 4 3 2 1 0 (hexadecimal) © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 144 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 11.5 Scaler and interfaces Table 143 shows some examples for the scaler programming with: • prsc = prescale ratio • fisc = fine scale ratio • vsc = vertical scale ratio number of input pixel The ratio is defined as: -----------------------------------------------------number of output pixel In the following settings the VBI data slicer is inactive. To activate the VBI data slicer, VITX[1:0] 86h[7:6] has to be set to ‘11’. Depending on the VBI data slicer settings, the sliced VBI data is inserted after the end of the scaled video lines, if the regions of VBI data slicer and scaler overlaps. To compensate the running-in of the vertical scaler, the vertical input window lengths are extended by 2 lines to 290 lines, respectively 242 lines for XS, but the scaler increment calculations are done with 288 lines, respectively 240 lines. 11.5.1 Trigger condition For trigger condition STRC[1:0] 90h[1:0] not equal to ‘00’. If the value of (YO + YS) is greater than or equal to 262 (NTSC), respectively 312 (PAL) the output field rate is reduced to 30 Hz, respectively 25 Hz. Horizontal and vertical offsets (XO and YO) have to be used to adjust the displayed video in the display window. As this adjustment is application dependent, the listed values are only dummy values. 11.5.2 Maximum zoom factor The maximum zoom factor is dependent on the back-end data rate and therefore back-end clock and data format dependent (8-bit or 16-bit output). The maximum horizontal zoom is limited to approximately 3.5, due to internal data path restrictions. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 145 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 11.5.3 Examples Table 143. Example of configurations Example number Scaler source and reference events Input window (pixel) Output window (pixel) Scale ratios 1 analog input to 8-bit I port output, with SAV/EAV codes, 720 × 240 8-bit serial byte stream decoder output at X port; acquisition trigger at falling edge vertical and rising edge horizontal reference signal; H and V gates on IGPH and IGPV, IGP0 = VBI sliced data flag, IGP1 = FIFO almost full, level ≥ 24, IDQ qualifier logic 1 active 720 × 240 prsc = 1; fisc = 1; vsc = 1 2 analog input to 16-bit output, without SAV/EAV codes, Y on I port, CB-CR on H port and decoder output at X port; acquisition trigger at falling edge vertical and rising edge horizontal reference signal; H and V-pulses on IGPH and IGPV, output FID on IGP0, IGP1 fixed to logic 1, IDQ qualifier logic 0 active 704 × 288 768 × 288 prsc = 1; fisc = 0.91667; vsc = 1 3 720 × 240 X port input 8-bit with SAV/EAV codes, no reference signals on XRH and XRV, XCLK as gated clock; field detection and acquisition trigger on different events; acquisition triggers at rising edge vertical and rising edge horizontal; I port output 8-bit with SAV/EAV codes like example number 1 352 × 288 prsc = 2; fisc = 1.022; vsc = 0.8333 4 X port and H port for 16-bit Y-CB-CR 4 : 2 : 2 input (if no 720 × 288 16-bit output selected); XRH and XRV as references; field detection and acquisition trigger at falling edge vertical and rising edge horizontal; I port output 8-bit with SAV/EAV codes, but Y only output 200 × 80 prsc = 2; fisc = 1.8; vsc = 3.6 Table 144. Scaler and interface configuration example I2C-bus address (hex) Main functionality Example 1 Example 2 Example 3 Example 4 Hex Dec Hex Dec Hex Dec Hex Dec Global settings 80 task enable, IDQ and back-end clock definition 10 - 10 - 10 - 10 - 83 XCLK output phase and X port output enable 01 - 01 - 00 - 00 - 84 IGPH, IGPV, IGP0 and IGP1 output definition A0 - C5 - A0 - A0 - 85 signal polarity control and I port byte swapping 10 - 09 - 10 - 10 - 86 FIFO flag thresholds and video/text arbitration 45 - 40 - 45 - 45 - 87 ICLK and IDQ output phase and I port enable 01 - 01 - 01 - 01 - 88 power save control and software reset F0 - F0 - F0 - F0 - Task A: scaler input configuration and output format settings 90 task handling 00 - 00 - 00 - 00 - 91 scaler input source and format definition 08 - 08 - 18 - 38 - 92 reference signal definition at scaler input 10 - 10 - 10 - 10 - 93 I port output formats and configuration 80 - 40 - 80 - 84 - SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 146 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 144. Scaler and interface configuration example …continued I2C-bus address (hex) Main functionality Example 1 Example 2 Example 3 Example 4 Hex Hex Hex Hex Dec Dec Dec Dec Input and output window definition 94 horizontal input offset (XO) 95 96 horizontal input (source) window length (XS) 97 98 vertical input offset (YO) 99 9A vertical input (source) window length (YS) 9B 9C horizontal output (destination) window length (XD) 9D 9E vertical output (destination) window length (YD) 9F 10 16 10 16 10 16 10 16 00 - 00 - 00 - 00 - D0 720 C0 704 D0 720 D0 720 02 - 02 - 02 - 02 - 0A 10 0A 10 0A 10 0A 10 00 - 00 - 00 - 00 - F2 242 22 290 F2 242 22 290 00 - 01 - 00 - 01 - D0 720 00 768 60 352 C8 200 02 - 03 - 01 - 00 - F0 240 20 288 20 288 50 80 00 - 01 - 01 - 00 - Prefiltering and prescaling A0 integer prescale (value ‘00’ not allowed) 01 - 01 - 02 - 02 - A1 accumulation length for prescaler 00 - 00 - 02 - 03 - A2 FIR prefilter and prescaler DC normalization 00 - 00 - AA - F2 - A4 scaler brightness control 80 128 80 128 80 128 80 128 A5 scaler contrast control 40 64 40 64 40 64 11 17 A6 scaler saturation control 40 64 40 64 40 64 11 17 Horizontal phase scaling A8 horizontal scaling increment for luminance A9 00 1024 AA 938 18 1048 34 1844 04 - 03 - 04 - 07 - AA horizontal phase offset luminance 00 - 00 - 00 - 00 - AC horizontal scaling increment for chrominance 00 512 D5 469 0C 524 9A 922 02 - 01 - 02 - 03 - 00 - 00 - 00 - 00 - 00 1024 00 1024 55 853 66 3686 04 - - - 0E - 00 1024 00 1024 55 853 66 3686 04 - 04 - 03 - 0E - - 00 - 00 - 01 - AD AE horizontal phase offset chrominance Vertical scaling B0 vertical scaling increment for luminance B1 B2 vertical scaling increment for chrominance B3 04 03 B4 vertical scaling mode control 00 B8 to BF vertical phase offsets luminance and chrominance (need to be used for interlace correct scaled output) start with B8 to BF at 00h, if there are no problems with the interlaced scaled output optimize according to Section 8.4.3.2 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 147 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 12. Limiting values Table 145. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All ground pins connected together and grounded (0 V); all supply pins connected together. Symbol Parameter Conditions Min Max Unit VDDD digital supply voltage −0.5 +4.6 V VDDA analog supply voltage −0.5 +4.6 V Vi(A) input voltage at analog inputs −0.5 +4.6 V Vi(n) input voltage at pins XTALI, SDA and SCL −0.5 VDDD + 0.5 V Vi(D) input voltage at digital inputs or I/O pins −0.5 +4.6 V −0.5 +5.5 V outputs in 3-state outputs in 3-state [1] ∆VSS voltage difference between VSSA(n) and VSSD(n) - 100 mV Tstg storage temperature −65 +150 °C Tamb ambient temperature Vesd electrostatic discharge voltage −40 +85 °C human body model [2] - ±2000 V machine model [3] - ±200 V [1] Condition for maximum voltage at digital inputs or I/O pins: 3.0 V < VDDD < 3.6 V. [2] Class 2 according to JESD22-A114-B. [3] Class B according to EIA/JESD22-A115-A. 13. Thermal characteristics Table 146. Thermal characteristics Symbol Parameter Conditions Rth(j-a) thermal resistance from junction to ambient SAF7118EH SAF7118H [1] Unit in free air [1] 29 K/W in free air [1] 25 K/W The overall Rth(j-a) value can vary depending on the board layout. To minimize the effective Rth(j-a) all power and ground pins must be connected to the power and ground layers directly. An ample copper area directly under the SAF7118 with a number of through-hole plating, connected to the ground layer (four-layer board: second layer), can also reduce the effective Rth(j-a). Please do not use any solder-stop varnish under the chip. In addition the usage of soldering glue with a high thermal conductance after curing is recommended. SAF7118_4 Product data sheet Typ © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 148 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 14. Characteristics Table 147. Characteristics VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = −40 °C to +85 °C (typical values measured at Tamb = 25 °C); timings and levels refer to drawings and conditions illustrated in Figure 91; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 3.0 3.3 3.6 V - 85 - mA Supplies VDDD digital supply voltage IDDD digital supply current PD power dissipation digital part - 280 - mW VDDA analog supply voltage 3.1 3.3 3.5 V IDDA analog supply current CVBS mode - 75 - mA Y/C mode - 130 - mA X port 3-state; 8-bit I port AOSL1 and AOSL0 = 0 component mode PA power dissipation analog part - 250 - mA CVBS mode - 248 - mW Y/C mode - 430 - mW component mode - 825 - mW total power dissipation analog and digital part CVBS mode [1] - 533 - mW Y/C mode [1] - 710 - mW component mode [1] - 1105 1350 mW Ptot(A+D)(pd) total power dissipation analog and digital part in Power-down mode CE pulled down to ground - 5 - mW Ptot(A+D)(ps) total power dissipation analog and digital part in Power-save mode I2C-bus controlled via subaddress 88h = 0Fh - 75 - mW Ptot(A+D) Analog part Iclamp clamping current VI = 1 V DC - ±8 - µA Vi(p-p) input voltage (peak-to-peak value) for normal video levels 1 V (p-p), −3 dB termination 18/56 Ω and AC coupling required; coupling capacitor is 47 nF - 0.7 - V |Zi| input impedance clamping current off 200 - - kΩ Ci input capacitance - - 10 pF αcs channel crosstalk - - −50 dB fi < 5 MHz SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 149 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 147. Characteristics …continued VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = −40 °C to +85 °C (typical values measured at Tamb = 25 °C); timings and levels refer to drawings and conditions illustrated in Figure 91; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 9-bit analog-to-digital converters B analog bandwidth at −3 dB - 7 - MHz φdiff differential phase amplifier plus anti-alias filter bypassed - 2 - deg Gdiff differential gain amplifier plus anti-alias filter bypassed - 2 - % fclk(ADC) ADC clock frequency 25.4 - 28.6 MHz LEdc(d) DC differential linearity error - 0.7 - LSB LEdc(i) DC integral linearity error - 1 - LSB ∆GADC ADC gain inequality [2] - 3 - % - +0.3VDD(I2C) V deviation   maximum - – 1 × 100  ---------------------------------------------minimum deviation Digital inputs VIL(SCL,SDA) LOW-level input voltage pins SDA and SCL [3] −0.5 VIH(SCL,SDA) HIGH-level input voltage pins SDA and SCL [3] 0.7VDD(I2C) - VDD(I2C) + 0.5 V VIL(XTALI) LOW-level CMOS input voltage pin XTALI −0.3 - +0.8 V VIH(XTALI) HIGH-level CMOS input voltage pin XTALI 2.0 - VDDD + 0.3 V VIL(n) LOW-level input voltage all other inputs −0.3 - +0.8 V VIH(n) HIGH-level input voltage all other inputs 2.0 - 5.5 V ILI input leakage current - - 1 µA ILI/O I/O leakage current Ci input capacitance - - 10 µA I/O at high-impedance - - 8 pF SDA at 3 mA sink current - - 0.4 V Digital outputs[4] VOL(SDA) LOW-level output voltage pin SDA VOL(clk) LOW-level output voltage for clocks 0 - 0.6 V VOH(clk) HIGH-level output voltage for clocks 2.4 - VDDD + 0.5 V SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 150 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 147. Characteristics …continued VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = −40 °C to +85 °C (typical values measured at Tamb = 25 °C); timings and levels refer to drawings and conditions illustrated in Figure 91; unless otherwise specified. Symbol Parameter VOL(n) VOH(n) Conditions Min Typ Max Unit LOW-level output voltage all other digital outputs 0 - 0.4 V HIGH-level output voltage all other digital outputs 2.4 - VDDD + 0.5 V 15 - 50 pF Clock output timing (LLC and LLC2)[5] CL output load capacitance Tcy cycle time pin LLC 35 - 39 ns pin LLC2 70 - 78 ns δ duty factors for tLLCH/tLLC and tLLC2H/tLLC2 CL = 40 pF 40 - 60 % tr rise time LLC and LLC2 0.2 V to VDDD − 0.2 V - - 5 ns tf fall time LLC and LLC2 VDDD − 0.2 V to 0.2 V - - 5 ns td(LLC-LLC2) delay time between measured at 1.5 V; LLC and LLC2 CL = 25 pF output −4 - +8 ns nominal line frequency 50 Hz field - 15625 - Hz 60 Hz field - 15734 - Hz - - 5.7 % PAL BGHI - 4433619 - Hz NTSC M - 3579545 - Hz PAL M - 3575612 - Hz PAL N - 3582056 - Hz ±400 - - Hz Horizontal PLL fhor(nom) ∆fhor/fhor(nom) permissible static deviation Subcarrier PLL fsc(nom) ∆fsc nominal subcarrier frequency lock-in range Crystal oscillator for 32.11 MHz[6] fxtal(nom) nominal frequency - 32.11 - MHz ∆fxtal(nom) permissible nominal frequency deviation - - ±70 10−6 ∆fxtal(nom)(T) permissible nominal frequency deviation with temperature - - ±30 10−6 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 151 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 147. Characteristics …continued VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = −40 °C to +85 °C (typical values measured at Tamb = 25 °C); timings and levels refer to drawings and conditions illustrated in Figure 91; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Crystal specification (X1) Tamb(X1) ambient temperature −40 - +85 °C CL load capacitance 8 - - pF Rs series resonance resistor - 40 80 Ω C1 motional capacitance - 1.5 ± 20 % - fF C0 parallel capacitance - 4.3 ± 20 % - pF Crystal oscillator for 24.576 MHz[6] fxtal(nom) nominal frequency - 24.576 - MHz ∆fxtal(nom) permissible nominal frequency deviation - - ±50 10−6 ∆fxtal(nom)(T) permissible nominal frequency deviation with temperature - - ±20 10−6 Crystal specification (X1) Tamb(X1) ambient temperature −40 - +85 °C CL load capacitance 8 - - pF Rs series resonance resistor - 40 80 Ω C1 motional capacitance - 1.5 ± 20 % - fF C0 parallel capacitance - 3.5 ± 20 % - pF Clock input timing (XCLK) Tcy cycle time 31 - 45 ns δ duty factors for tLLCH/tLLC 40 50 60 % tr rise time - - 5 ns tf fall time - - 5 ns Data and control signal input timing X port, related to XCLK input tSU;DAT input data setup time 10 - - ns tHD;DAT input data hold time 6 - - ns Clock output timing CL output load capacitance 15 - 50 pF Tcy cycle time 35 - 39 ns SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 152 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 147. Characteristics …continued VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = −40 °C to +85 °C (typical values measured at Tamb = 25 °C); timings and levels refer to drawings and conditions illustrated in Figure 91; unless otherwise specified. Symbol Parameter δ duty factors for tXCLKH/tXCLKL tr rise time tf fall time Conditions Min Typ Max Unit 35 - 65 % 0.6 V to 2.6 V - - 5 ns 2.6 V to 0.6 V - - 5 ns Data and control signal output timing X port, related to XCLK output (for XPCK[1:0]83h[5:4] = 00 is CL output load capacitance tOHD;DAT output data hold time tPD propagation delay from positive edge of XCLK output default)[5] 15 - 50 pF CL = 15 pF 4 - - ns CL = 15 pF - - 19 ns 15 - 50 pF Control signal output timing RT port, related to LLC output CL output load capacitance tOHD;DAT output hold time CL = 15 pF 4 - - ns tPD propagation delay from positive edge of LLC output CL = 15 pF - - 19 ns ICLK output timing CL output load capacitance 15 - 50 pF Tcy cycle time 31 - 45 ns δ duty factors for tICLKH/tICLKL 35 - 65 % tr rise time 0.6 V to 2.6 V - - 5 ns tf fall time 2.6 V to 0.6 V - - 5 ns Data and control signal output timing I port, related to ICLK output (for IPCK[1:0] 87h[5:4] = 00 is default) CL output load capacitance at all outputs tOHD;DAT output data hold time to(d) output delay time 15 - 50 pF CL = 15 pF 4 - - ns CL = 15 pF - - 19 ns 31 - 100 ns ICLK input timing cycle time Tcy [1] 8-bit image port output mode, expansion port is 3-stated. [2] ADC1 is not taken into account, since component video is always converted by ADC2, ADC3 and ADC4. [3] VDD(I2C) is the supply voltage of the I2C-bus. For VDD(I2C) = 3.3 V then VIL(SCL,SDA)(max) = 1 V; for VDD(I2C) = 5 V then VIL(SCL,SDA)(max) = 1.5 V. For VDD(I2C) = 3.3 V then VIH(SCL,SDA)(min) = 2.3 V; for VDD(I2C) = 5 V then VIH(SCL,SDA)(min) = 3.5 V. [4] The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); CL = 50 pF. [5] The effects of rise and fall times are included in the calculation of tOHD;DAT and tPD. Timings and levels refer to drawings and conditions illustrated in Figure 91. [6] The crystal oscillator drive level is typical 0.28 mW. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 153 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Tcy t XCLKH 2.4 V clock input XCLK 1.5 V 0.6 V t SU;DAT tf tr t HD;DAT 2.0 V data and control inputs (X port) not valid 0.8 V t SU;DAT t HD;DAT 2.0 V input XDQ 0.8 V t o(d) t OHD;DAT 2.4 V data and control outputs X port, I port 0.6 V t X(I)CLKL t X(I)CLKH 2.6 V clock outputs LLC, LLC2, XCLK, ICLK and ICLK input 1.5 V 0.6 V tf tr mhb735 Fig 91. Data input/output timing diagram (X port, RT port and I port) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 154 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 15. Application information VDDD BAT83 150 pF VDDD 680 Ω VDDD or VSSD for I2C-bus slave address strapping 4.7 kΩ ∆t 680 Ω FB VDDD or VSSD for crystal strapping boundary 4.7 kΩ AMCLK scan(1) audio clock AMXCLK TRST I2C-bus port BF840 AI13 S AI14 56 Ω (3×) AI1D AGND 18 Ω (4×) AI21 VSB1 AI22 VSB2 AI23 G AI24 YS AI2D 56 Ω (4×) 18 Ω (4×) AI31 Y1 AI32 Y2 AI33 B AI34 PB AI3D 56 Ω (4×) AGNDA 18 Ω (4×) AI41 C1 AI42 C2 AI43 R PR AI44 AI4D 56 Ω (4×) EXMCLR AOUT AOUT P12 N11 P10 SCL INT_A CE N9 P9 N4 M13 RES L10 M10 K1 N5 K2 P4 L3 K3 B11 C2 D8 G4 C7 G3 A6 H2 B7 J3 E3 SAF7118EH F2 G13, F14, F13, E14, E12, E13, E11, D14 F3 L12 G1 K13 F1 L14 L2 K14 B1 K12 D2 N12 D1 L13 RTS1 RTS0 LLC2 LLC XTRI XRV XRH XRDY XDQ D3 M2, J4, H3, E4, C1 M3, K4, H4, F4, D4 L1, J1, G2, E2 L5, L9, J11, F11, D10, D7 M5, M9, J12, F12, C10, C8 VSSA0 VDDA0 VDDA1A VSSD2 VSSD4 to to to VSSA4 VDDA4 VDDA4A V SSD6 VSSD8 VSSD10 VSSD12 VDDD2 VDDD4 VDDD6 VDDD8 VDDD10 VDDD12 DGND VDDD L4, L8, L11, G11, D11, D9, D5 M4, M8, M11, H12, D12, C9, C5 VSSD1 VSSD3 VSSD5 VSSD7 VSSD9 VSSD11 VSSD13 DGND 100 nF 100 nF ITRI IGP1 IGP0 IGPV IGPH ITRDY IDQ CLKEXT N6 P6, M6, L6, N7, P7, ADP[8:0] L7, M7, P8, N8 A4 VDDD1 VDDD3 VDDD5 VDDD7 VDDD9 VDDD11 VDDD13 DGND HPD[7:0] ICLK M14 K11, J13, J14, H13, IPD[7:0] H14, H11, G12, G14 E1 M1 RTCO XCLK A7 XPD[7:0] C11, A11, B10, A10, B9, A9, B8, A8 H1 P3 4.7 kΩ P5 N10 J2 AGND VDDA P11 real-time CVBS2 M12 expansion port AI12 ALRCLK ASCLK SDA D6 host port CVBS1 AI11 B6 B3 A2 A3 VDD(xtal) 18 Ω (3×) 47 nF TCK TMS C6 VSS(xtal) FSW DGND B5 scaled image port A5 AD port TDO TDI 75 Ω B4 XTALO XTALI 24.576 MHz (3rd harmonic) XTOUT 10 µH 10 µF DGND 10 µF AGND 2.2 µH 100 nF 100 nF 0 Ω 100 nF 100 nF 100 nF 100 nF DGND AGND 10 pF 10 pF 1 nF coa025 (1) For board design without boundary scan implementation this pin should be connected to ground. Fig 92. Application example with 24.576 MHz crystal (HBGA156 package) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 155 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter VDDD VDDD or VSSD for crystal strapping VDDD 680 Ω BAT83 150 pF ∆t 680 Ω FB VDDD or VSSD for I2C-bus slave address strapping 4.7 kΩ AMCLK boundary scan(1) AMXCLK TRST 4.7 kΩ audio clock I2C-bus port BF840 AI13 S AI14 AI1D 56 Ω (3×) AGND 18 Ω (4×) AI21 VSB1 AI22 VSB2 AI23 G AI24 YS AI2D 56 Ω (4×) 18 Ω (4×) AI31 Y1 AI32 Y2 AI33 B AI34 PB AI3D 56 Ω (4×) AGNDA 18 Ω (4×) AI41 C1 AI42 C2 AI43 R AI44 PR AI4D 56 Ω (4×) EXMCLR AOUT AOUT 72 75 74 68 SCL INT_A CE 66 64 44 83 RES 71 70 27 69 29 48 31 46 34 30 126 3 140 19 141 21 146 23 144 26 11 SAF7118H 13 103, 105, 107, 109, 110, 111, 112, 113 15 86 18 89 14 87 35 90 2 91 5 77 7 85 RTS1 RTS0 LLC2 LLC XTRI XRV XRH XRDY XDQ 6 38, 28, 20, 12, 4 37, 32, 24, 16, 8 51, 67, 96, 108, 133, 145 33, 25, 17, 9 VSSA0 VDDA0 VDDA1A to VSSA4 to VDDA4 to VDDA4A AGND VDDA VSSD2 VSSD4 VSSD6 VSSD8 VSSD10 VSSD12 50, 65, 95, 106, 132, 142 VDDD2 VDDD4 VDDD6 VDDD8 VDDD10 VDDD12 DGND VDDD 47, 63, 88, 104, 129, 137, 153 VSSD1 VSSD3 VSSD5 VSSD7 VSSD9 VSSD11 VSSD13 45, 59, 73, 101, 114, 136, 151 VDDD1 VDDD3 VDDD5 VDDD7 VDDD9 VDDD11 VDDD13 DGND DGND 100 nF 100 nF HPD[7:0] ITRI IGP1 IGP0 IGPV IGPH ITRDY IDQ ICLK 84 92, 93, 94, 97, IPD[7:0] 98, 99, 100, 102 10 36 RTCO XCLK 143 XPD[7:0] 127, 128, 130, 131, 134, 135, 138, 139 22 43 4.7 kΩ 49 real-time CVBS2 76 expansion port AI12 ALRCLK ASCLK SDA 149 host port AI11 CVBS1 148 CLKEXT 52 53, 54, 55, 56, 57, ADP[8:0] 58, 60, 61, 62 154 157 158 156 VSS(xtal) 47 nF TCK TMS 147 VDD(xtal) FSW DGND 18 Ω (3×) 152 scaled image port 150 AD port TDO TDI 75 Ω 155 XTALO XTALI 24.576 MHz (3rd harmonic) XTOUT 10 µH 10 µF DGND 10 µF AGND 2.2 µH 100 nF 100 nF 0 Ω 100 nF 100 nF 100 nF 100 nF DGND AGND 10 pF 10 pF 1 nF mbl757 (1) For board design without boundary scan implementation this pin should be connected to ground. Fig 93. Application example with 24.576 MHz crystal (QFP160 package) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 156 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter SAF7118 B4(155) A3(156) XTALI XTALO B4(155) A3(156) XTALI 32.11 MHz 4.7 µH SAF7118 SAF7118 XTALO B4(155) 15 pF 33 pF XTALO 32.11 MHz 32.11 MHz 15 pF A3(156) XTALI 10 pF 33 pF 10 pF 1 nF mbl754 a. With 3rd harmonic quartz. Crystal load = 8 pF. b. With fundamental quartz. Crystal load = 20 pF. SAF7118 B4(155) A3(156) XTALO B4(155) A3(156) XTALI 24.576 MHz 18 pF SAF7118 SAF7118 XTALI 4.7 µH c. With fundamental quartz. Crystal load = 8 pF. XTALO 39 pF A3(156) XTALI XTALO 24.576 MHz 24.576 MHz 18 pF B4(155) 15 pF 39 pF 15 pF 1 nF mbl755 d. With 3rd harmonic quartz. Crystal load = 8 pF. e. With fundamental quartz. Crystal load = 20 pF. SAF7118 SAF7118 B4(155) A3(156) XTALI f. With fundamental quartz. Crystal load = 8 pF. XTALO B4(155) A3(156) XTALI XTALO 32.11 MHz or 24.576 MHz Rs n.c. G clock mbl756 g. With direct clock. h. With fundamental quartz and restricted drive level. When Pdrive of the internal oscillator is too high a resistance Rs can be placed in series with the output of the oscillator XTALO. Note: The decreased crystal amplitude results in a lower drive level but on the other hand the jitter performance will decrease. Fig 94. Oscillator application (pin numbers for QFP160 in parenthesis) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 157 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 16. Test information 16.1 Boundary scan test The SAF7118 has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAF7118 follows the “IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture” set by the Joint Test Action Group (JTAG). The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO). The Boundary Scan Test (BST) functions BYPASS, EXTEST, SAMPLE, CLAMP and IDCODE are all supported; see Table 148. Details about the JTAG BST-TEST can be found in specification “IEEE Std. 1149.1”. A file containing the detailed Boundary Scan Description Language (BSDL) description of the SAF7118 is available on request. Table 148. BST instructions supported by the SAF7118 Instruction Description BYPASS This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO when no test operation of the component is required. EXTEST This mandatory instruction allows testing of off-chip circuitry and board level interconnections. SAMPLE This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. CLAMP This optional instruction is useful for testing when not all ICs have BST. This instruction addresses the bypass register while the boundary scan register is in external test mode. IDCODE This optional instruction will provide information on the components manufacturer, part number and version number. 16.1.1 Initialization of boundary scan circuit The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW. 16.1.2 Device identification codes A device identification register is specified in “IEEE Std. 1149.1b-1994”. It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 158 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between pins TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit D31 is the most significant bit (nearest to TDI) and bit D0 is the least significant bit (nearest to TDO); see Figure 95. MSB 31 TDI LSB 28 27 nnnn 4-bit version code 12 11 0111 0001 0001 1000 16-bit part number 1 000 0001 0101 11-bit manufacturer identification 0 1 TDO mhb734 Fig 95. 32 bits of identification code SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 159 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 17. Package outline HBGA156: plastic thermal enhanced ball grid array package; 156 balls; body 15 x 15 x 1.15 mm; heatsink SOT807-1 B D A D1 ball A1 index area A2 A j E1 E A1 detail X C e1 e ∅v M C A B b 1/2 e P N M L K J H G F E D C B A shape optional (4×) y1 C y ∅w M C e heatsink e2 1/2 e 1 2 3 4 5 6 7 8 9 10 11 12 13 14 X 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b D D1 E E1 e e1 e2 j v w y y1 mm 1.75 0.5 0.3 1.25 1.05 0.6 0.4 15.2 14.8 13.2 12.8 15.2 14.8 13.2 12.8 1 13 13 8 10 0.3 0.1 0.15 0.35 OUTLINE VERSION SOT807-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 03-03-06 MS-034 Fig 96. Package outline SOT807-1 (HBGA156) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 160 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter QFP160: plastic quad flat package; 160 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height SOT322-2 c y X A 120 121 81 80 ZE e E HE A A2 (A 3) A1 θ wM Lp bp L pin 1 index detail X 41 160 1 40 ZD wM bp e v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 4.07 0.50 0.25 3.6 3.2 0.25 0.38 0.22 0.23 0.13 28.1 27.9 28.1 27.9 0.65 HD HE 31.45 31.45 30.95 30.95 L Lp v w y 1.6 1.03 0.73 0.3 0.13 0.1 Z D(1) Z E (1) 1.5 1.1 1.5 1.1 θ o 7 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT322-2 135E12 MS-022 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 97. Package outline SOT322-2 (QFP160) SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 161 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 18.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 162 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 98) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 149 and 150 Table 149. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 150. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 98. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 163 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 98. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 19. Appendix 19.1 Issue 1: Bit ICKS3 = 1 (I2C-bus control signal, bit D3 of subaddress 80h) drives image port output clock ICLK to 3-state Background (how it should work): The control signal ICKS[3:0] is intended to be used to switch the image port clock I/O into different operating modes. ICKS[1:0] = 11b should 3-state the ICLK output (for using the pin as external back-end clock input). ICKS3 influences the generation of the data qualifier; see Table 93. Anomaly description: ICKS3 is erroneously connected to the 3-state control block instead of ICKS[1:0]. Impact: 1. ICKS[1:0] = 11b does not switch ICLK to 3-state 2. If ICKS3 needs to be used according to the extended function on IDQ (see Table 93) the ICLK output will be 3-stated and cannot be used anymore Workaround: 1. If external ICLK is required, ICKS3 has to be set to logic 1 in addition to ICKS[1:0] = 11b 2. Use pin LLC as reference clock instead of ICLK, if ICKS3 needs to be programmed to logic 1 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 164 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 19.2 Issue 2: Forced odd/even toggle option, enabled by bit FOET = 1 (I2C-bus control signal, bit D5 of subaddress 08h) does not work properly Background (how it should work): Setting FOET = 1 is intended to make the odd/even output signal toggle fieldwise even if the video source is of non-interlace type. Anomaly description: Although with a non-interlaced input the odd/even output signal toggles as desired, the odd/even output signal might be just inverted (50 % likelihood), when the input signal is changed to interlaced when FOET = 1. Impact: It cannot be assured that the generated odd/even sequence fits to the field sequence of an interlaced input signal with activated FOET. Thus, in a succeeding processing, the two field sequence of interlaced video could be swapped, resulting in a jaggy picture. Workaround: A continuous read on bit INTL (I2C-bus control signal, bit D7 of subaddress 1Fh) recognizes interlaced signals (FOET = 1 not allowed) and non-interlaced signals (FOET = 1 is allowed) and FOET must be programmed depending on the state of INTL. Alternatively, it always should be FOET = 0. 19.3 Issue 3: Errors with horizontal lock when using bit HLNRS (I2C-bus control signal, bit D6 of subaddress 03h) Background (how it should work): If horizontal lock is not possible because of very special input signals (like 250 kHz black and white bars), HLNRS = 1 should enable to clamp to a mid range level (0.5 V) of the input signal and a fast time constant AGC should increase signal amplitude to ADC input range in order to force the horizontal PLL to lock. After horizontal PLL locking, AGC will be switched to normal AGC time constant and a digitally controlled clamp circuit replaces the ‘clamp to a mid range level’ function automatically. Anomaly description: With HLNRS = 1, HOLDG = 0 and GAFIX = 0 in combination with unlocked horizontal PLL, the video AGC is frozen to a small gain value. Impact: With gain reduced to a worst case minimum of −3 dB, it might happen that the digital sync slicing threshold never is being reached and thus the horizontal PLL never gets locked. Workaround: HLNRS never should be set to logic 1 when the AGC is activated. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 165 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 19.4 Issue 4: Erase condition for interrupt pin INT_A Background (how it should work): The status flags are grouped into four 8-bit registers. The interrupt flag is to be cleared on a read access to a status register, comprising the event that caused the interrupt. This implies that it would be sufficient to clear the interrupt by reading only those registers which have been enabled by their corresponding masks. Anomaly description: Three of the four register addresses for clearing the interrupt flag are wrong; see Table 151. Table 151. Status bytes Address to be read Correct Implemented 1Eh 0Eh (incorrect) 1Fh 0Fh (incorrect) 60h 5Fh (incorrect) 8Fh 8Fh (correct) Impact: Output pin INT_A cannot be cleared by reading the corresponding addresses in three of four cases. Workaround: To clear the interrupt flag, an additional read cycle to the implemented addresses is required, e.g. to read register 1Eh and clear interrupt flag, read register 1Eh and register 0Eh. 19.5 Issue 5: Odd/even detection might become unreliable with signals from video tape recorders Background (how it should work): The odd/even detection is a flag, available on a pin, to indicate the interlace of a video signal; this should be independent of the type of input signal. Anomaly description: If a signal originated from a VTR suffers from phase errors greater than 16 µs, the odd/even detection might be set onto a wrong phase, thus interrupting the actual odd/even sequence of the input signal. Impact: If the generated odd/even flag is being used in a succeeding signal processing, this processing could eventually be upset due to incorrect detection. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 166 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Workaround: It should be avoided to use the detected odd/even information whenever it cannot be assured that the input signal is of stable time base. 19.6 Issue 6: Slicing of MOJI VBI data leads to unexpected results Background (how it should work): SAF7118 incorporates a versatile VBI data slicer, for various data types, including MOJI. The sliced data is provided as video stream at the image port. The entire VBI data packet counts 56 bytes, including the leading SAV and trailing EAV sequence. The detailed values for SAV and EAV codes depend on odd/even field identification and on some programmable device settings. SAV is followed by an internal 4-byte header, indicating actual data type and line number in byte IDI1 and IDI2, among other status information. The data packet is closed by an EAV sequence, preceded by byte count and check sum byte. To maintain a constant and fix length of the VBI data packets, the remaining space between actual sliced data and check sum is filled up with stuffing bytes of value A0. For MOJI data standard (35 sliced data bytes are generated), there should be no general difference in data handling compared to e.g. WST625. Anomaly description: Under certain conditions, erroneous and meaningless bytes are inserted between internal header and actual sliced data. These faulty bytes are mostly logic 0, but can be different values, too (see Figure 99). The problem might also occur with VBI data standards of similar data rate, e.g. NABTS. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 167 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Erroneous case A Erroneous case B 2 00 3 AB/EC SAV AB/EC SAV AB/EC SAV 4 programmable SDID programmable SDID programmable SDID 5 0B fix DC 0B fix DC 0B 6 id IDI1 id IDI1 id 7 id IDI2 id IDI2 id 8 data byte 1 ZZ error ZZ error 9 data byte 2 ZZ error ZZ error data byte 3 data byte 1 ZZ error data byte 2 data byte 1 data byte 3 data byte 2 data byte 3 44 45 data data data byte 35 data data A0 stuff data data A0 A0 46 A0 47 A0 48 A0 49 A0 50 XX CS = check sum 51 25h BC = byte count 52 FF 53 00 54 00 55 B6/F1 data byte 35 data A0 stuff data A0 A0 A0 bytes A0 37d A0 A0 A0 bytes XX CS = check sum A7h BC = byte count packet trailer FF 00 00 EAV A0 39d internal header sliced data bytes for MOJI: 35 bytes BC = byte count internal header sliced data bytes for MOJI: 35 bytes internal header data IDI1 IDI2 byte 35 44(DC) − 40(BC) = 4 stuff-bytes 43 data fix DC stuff bytes XX CS = check sum A8h BC = byte count 40d FF B6/F1 00 00 EAV B6/F1 packet trailer 42 data data 44(DC) − 39(BC) = 5 stuff-bytes 41 data 00 packet trailer 40 data BC = byte count 13 data sliced data bytes for MOJI: 35 bytes 12 data 44(DC) − 37(BC) = 7 stuff-bytes 11 00 00 packet header 00 00 FF packet header 1 10 FF packet header FF DC = 0Bh = 11d double words = 44 bytes (according to ITU-ANC) 0 BC = byte count Nominal MOJI data structure CLK # EAV 001aah989 Fig 99. Erroneous case table Impact: A succeeding signal processing relying on correct headers of sliced data in accordance with MOJI will be upset by the erroneous bytes, resulting in wrong character display. SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 168 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Workaround: Such error can be detected and corrected through software post-processing, by investigating the actual byte count value BC for each data packet: The entire data packet must be captured in some intermediate memory accessible to software. (The SAV and EAV sequences may get dropped, i.e. not stored in memory. At least 48 bytes have to be captured). The last byte before the SAV sequence contains the BC = byte count of ‘payload’, which is counted from IDI1 byte to last actual sliced data byte. The BC byte is coded with 6 bits count value in the 2 lower bits, and complemented with an odd parity bit in the MSB. Table 152. BC byte description 7 6 5 4 3 2 1 0 OP 0 5 4 3 2 1 0 Odd parity fix 32 16 0 BC = byte count of payload, bit value 8 4 2 1 In nominal case those BC are 2 bytes more than the real MOJI byte count, i.e. 37d, BC byte nominal = 25h. In the event of insertion of erroneous bytes, the fault bytes are counted like payload, resulting to an unexpectedly increased BC number, BC byte unequal 25h. Recommended procedure: 1. Capture VBI sliced data packet 2. Get BC byte, i.e. last byte before EAV sequence 3. Suppress MSB (parity bit), remain payload byte count BC 4. Whenever BC unequals 37d, exactly (BC − 37d) erroneous bytes from capture must be removed, directly following the IDI2 byte. That means: a. If BC = 37d, then no error go to 5 b. If BC = 39d, then remove 2 erroneous bytes after internal header go to 5 c. If BC = 40d, then remove 3 erroneous bytes after internal header go to 5 5. MOJI data bytes are the 35 bytes following internal header, either if no error occurred or after the erroneous bytes have been removed Alternative procedure: This approach is applicable only if it is true, that the first real MOJI byte per line is always non-zero. 1. Capture VBI sliced data packet 2. Parse through data set, find internal header (by counting) 3. After internal header, skip zero bytes until first non-zero byte 4. MOJI data bytes are the 35 bytes beginning with that first non-zero byte SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 169 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 19.7 Issue 7: NTSC-Japan offset compensation does not work as specified in Y/C mode Background (how it should work): The difference between NTSC M and NTSC-Japan is the non-existing 7.5 IRE offset in Japan. The offset should automatically change by setting the preferred standard to NTSC-Japan instead of NTSC M via CSTD[2:0] = 100. Anomaly description: The offset adaption does not work in Y/C mode (BYPS = 1), however it does work in CVBS mode. Impact: The picture is too dark and picture content below +5 IRE is limited. Workaround: 1. Set decoder brightness (DBRI[7:0]) to 80h (drawback: ‘super black levels’ below −3 IRE are clipped) or 2. Set decoder to raw data mode by the LCRn registers and use RAWO[7:0] and RAWG[7:0] to adapt the levels For detail see Table 153. Table 153. Register setting Line control register Subaddress Value LCR22 55h DDh LCR23 56h DDh LCR24 57h DDh RAWG[7:0] 18h 66h RAWO[7:0] 19h 77h 20. Abbreviations Table 154. Abbreviations Acronym Description AV Audio Video CIF Common Intermediate Format CMOS Complementary Metal-Oxide Semiconductor CVBS Color Video Blanking Signal DB Difference Blue DR Difference Red DVD Digital Versatile Disc EAV End of Active Video FIFO First In First Out FIR Finite Impulse Response SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 170 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 154. Abbreviations …continued Acronym Description HCL Horizontal CLamp I2C-bus Inter IC bus LLC Line-Locked Clock LSB Least Significant Bit MSB Most Significant Bit NTSC National Television Standards Committee PAL Phase Alternating Line PC Personal Computer QAM Quadrature Amplitude Modulation RGB Red Green Blue RGBS Red Green Blue Sync RT Real-Time RTC Real-Time Clock SAV Start of Active Video SECAM SEquentiel Couleur Avec Memoire SRGB Sync Red Green Blue SY-PB-PR SYnc luma - Blue component - Red component TTL Transistor-Transistor-Logic VCO Voltage-Controlled Oscillator VCR Video Cassette Recorder VPO Video POrt VTR Video Tape Recorder 21. Revision history Table 155. Revision history Document ID Release date Data sheet status Change notice Supersedes SAF7118_4 20080704 Product data sheet - SAF7118_3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • Legal texts have been adapted to the new company name where appropriate. Section 8.1.5: added Figure 23 and Figure 24 Section 19 has been added Section 20 has been added SAF7118_3 20060216 Product data sheet - SAF7118_2 SAF7118_2 (9397 750 13496) 20040722 Product specification - SAF7118H_1 SAF7118H_1 (9397 750 10473) 20030103 Product specification - - SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 171 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 22. Legal information 22.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 22.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 22.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 22.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 23. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 172 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 24. Contents 1 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3 4 5 6 7 7.1 7.2 8 8.1 8.1.1 8.1.1.1 8.1.1.2 8.1.2 8.1.2.1 8.1.2.2 8.1.2.3 8.1.3 8.1.4 8.1.5 8.2 8.2.1 8.2.2 8.2.3 8.3 8.4 8.4.1 8.4.1.1 8.4.1.2 8.4.1.3 8.4.2 8.4.2.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Video acquisition/clock . . . . . . . . . . . . . . . . . . . 2 Video decoder. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Component video processing . . . . . . . . . . . . . . 2 Video scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 VBI data decoder and slicer . . . . . . . . . . . . . . . 3 Audio clock generation . . . . . . . . . . . . . . . . . . . 3 Digital I/O interfaces . . . . . . . . . . . . . . . . . . . . . 3 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . 15 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Analog input processing . . . . . . . . . . . . . . . . . 15 Clamping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chrominance and luminance processing . . . . 20 Chrominance path . . . . . . . . . . . . . . . . . . . . . 21 Luminance path . . . . . . . . . . . . . . . . . . . . . . . 25 Brightness Contrast Saturation (BCS) control and decoder output levels. . . . . . . . . . . . . . . . 31 Synchronization . . . . . . . . . . . . . . . . . . . . . . . 32 Clock generation circuit . . . . . . . . . . . . . . . . . 32 Power-on reset and CE input . . . . . . . . . . . . . 33 Component video processing . . . . . . . . . . . . . 35 RGB-to-(Y-CB-CR) matrix . . . . . . . . . . . . . . . . 36 Downformatter . . . . . . . . . . . . . . . . . . . . . . . . 36 Component video BCS control . . . . . . . . . . . . 37 Decoder output formatter . . . . . . . . . . . . . . . . 38 Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Acquisition control and task handling (subaddresses 80h, 90h, 91h, 94h to 9Fh and C4h to CFh) . . . . . . . . . . . . . . . . . . . . . . . 45 Input field processing . . . . . . . . . . . . . . . . . . . 46 Task handling . . . . . . . . . . . . . . . . . . . . . . . . . 47 Output field processing . . . . . . . . . . . . . . . . . . 48 Horizontal scaling . . . . . . . . . . . . . . . . . . . . . . 50 Horizontal prescaler (subaddresses A0h to A7h and D0h to D7h). . . . . . . . . . . . . . 50 8.4.2.2 8.4.3 8.4.3.1 8.4.3.2 8.4.3.3 8.5 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.7 8.7.1 8.7.2 8.7.3 9 9.1 9.2 9.3 9.4 9.4.1 9.4.1.1 9.4.1.2 9.4.1.3 9.4.1.4 9.4.2 9.4.3 9.5 9.5.1 9.5.2 9.6 9.7 9.8 9.8.1 Horizontal fine scaling (variable phase delay filter; subaddresses A8h to AFh and D8h to DFh). . . . . . . . . . . . . . . . . . . . . . . Vertical scaling . . . . . . . . . . . . . . . . . . . . . . . . Line FIFO buffer (subaddresses 91h, B4h and C1h, E4h) . . . . . . . . . . . . . . . . . . . . . . . . Vertical scaler (subaddresses B0h to BFh and E0h to EFh) . . . . . . . . . . . . . . . . . . . . . . . Use of the vertical phase offsets . . . . . . . . . . VBI data decoder and capture (subaddresses 40h to 7Fh) . . . . . . . . . . . . . . Image port output formatter (subaddresses 84h to 87h) . . . . . . . . . . . . . . Scaler output formatter (subaddresses 93h and C3h). . . . . . . . . . . . . Video FIFO (subaddress 86h) . . . . . . . . . . . . Text FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video and text arbitration (subaddress 86h) . . . . . . . . . . . . . . . . . . . . . . Data stream coding and reference signal generation (subaddresses 84h, 85h and 93h) . . . . . . . . . Audio clock generation (subaddresses 30h to 3Fh) . . . . . . . . . . . . . . Master audio clock . . . . . . . . . . . . . . . . . . . . . Signals ASCLK and ALRCLK. . . . . . . . . . . . . Other control signals . . . . . . . . . . . . . . . . . . . Input/output interfaces and ports . . . . . . . . . Analog terminals . . . . . . . . . . . . . . . . . . . . . . Audio clock signals. . . . . . . . . . . . . . . . . . . . . Clock and real-time synchronization signals . Interrupt handling . . . . . . . . . . . . . . . . . . . . . . Interrupt flags . . . . . . . . . . . . . . . . . . . . . . . . . Power state . . . . . . . . . . . . . . . . . . . . . . . . . . Video decoder . . . . . . . . . . . . . . . . . . . . . . . . VBI data slicer . . . . . . . . . . . . . . . . . . . . . . . . Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status reading conditions. . . . . . . . . . . . . . . . Erasing conditions . . . . . . . . . . . . . . . . . . . . . Video expansion port (X port) . . . . . . . . . . . . X port configured as output . . . . . . . . . . . . . . X port configured as input . . . . . . . . . . . . . . . Image port (I port) . . . . . . . . . . . . . . . . . . . . . Host port for 16-bit extension of video data I/O (H port) . . . . . . . . . . . . . . . . Basic input and output timing diagrams I port and X port . . . . . . . . . . . . . . . . . . . . . . . I port output timing . . . . . . . . . . . . . . . . . . . . . 54 55 55 56 57 60 61 62 62 63 63 64 66 67 68 68 69 69 70 70 71 71 71 71 72 72 72 72 72 73 76 76 78 79 79 continued >> SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 173 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 9.8.2 X port input timing. . . . . . . . . . . . . . . . . . . . . . 79 10 I2C-bus description . . . . . . . . . . . . . . . . . . . . . 82 10.1 I2C-bus format. . . . . . . . . . . . . . . . . . . . . . . . . 82 10.2 I2C-bus details . . . . . . . . . . . . . . . . . . . . . . . . 91 10.2.1 Subaddress 00h . . . . . . . . . . . . . . . . . . . . . . . 91 10.2.2 Subaddress 01h . . . . . . . . . . . . . . . . . . . . . . . 91 10.2.3 Subaddress 02h . . . . . . . . . . . . . . . . . . . . . . . 92 10.2.4 Subaddress 03h . . . . . . . . . . . . . . . . . . . . . . 106 10.2.5 Subaddress 04h . . . . . . . . . . . . . . . . . . . . . . 107 10.2.6 Subaddress 05h . . . . . . . . . . . . . . . . . . . . . . 107 10.2.7 Subaddress 06h . . . . . . . . . . . . . . . . . . . . . . 107 10.2.8 Subaddress 07h . . . . . . . . . . . . . . . . . . . . . . 108 10.2.9 Subaddress 08h . . . . . . . . . . . . . . . . . . . . . . 108 10.2.10 Subaddress 09h . . . . . . . . . . . . . . . . . . . . . . 109 10.2.11 Subaddress 0Ah . . . . . . . . . . . . . . . . . . . . . . 109 10.2.12 Subaddress 0Bh . . . . . . . . . . . . . . . . . . . . . . 110 10.2.13 Subaddress 0Ch . . . . . . . . . . . . . . . . . . . . . . 110 10.2.14 Subaddress 0Dh . . . . . . . . . . . . . . . . . . . . . . 110 10.2.15 Subaddress 0Eh . . . . . . . . . . . . . . . . . . . . . . 110 10.2.16 Subaddress 0Fh . . . . . . . . . . . . . . . . . . . . . . 112 10.2.17 Subaddress 10h . . . . . . . . . . . . . . . . . . . . . . 112 10.2.18 Subaddress 11h . . . . . . . . . . . . . . . . . . . . . . 112 10.2.19 Subaddress 12h . . . . . . . . . . . . . . . . . . . . . . 113 10.2.20 Subaddress 13h . . . . . . . . . . . . . . . . . . . . . . 115 10.2.21 Subaddress 14h . . . . . . . . . . . . . . . . . . . . . . 116 10.2.22 Subaddress 15h . . . . . . . . . . . . . . . . . . . . . . 116 10.2.23 Subaddress 16h . . . . . . . . . . . . . . . . . . . . . . 117 10.2.24 Subaddress 17h . . . . . . . . . . . . . . . . . . . . . . 117 10.2.25 Subaddress 18h . . . . . . . . . . . . . . . . . . . . . . 118 10.2.26 Subaddress 19h . . . . . . . . . . . . . . . . . . . . . . 118 10.2.27 Subaddress 1Eh . . . . . . . . . . . . . . . . . . . . . . 118 10.2.28 Subaddress 1Fh . . . . . . . . . . . . . . . . . . . . . . 119 10.3 Programming register RGB/Y-PB-PR component input processing. . . . . . . . . . . . . 119 10.3.1 Subaddress 23h . . . . . . . . . . . . . . . . . . . . . . 119 10.3.2 Subaddress 24h . . . . . . . . . . . . . . . . . . . . . . 120 10.3.3 Subaddress 25h . . . . . . . . . . . . . . . . . . . . . . 120 10.3.4 Subaddress 29h . . . . . . . . . . . . . . . . . . . . . . 120 10.3.5 Subaddress 2Ah . . . . . . . . . . . . . . . . . . . . . . 121 10.3.6 Subaddress 2Bh . . . . . . . . . . . . . . . . . . . . . . 121 10.3.7 Subaddress 2Ch . . . . . . . . . . . . . . . . . . . . . . 121 10.4 Interrupt mask registers . . . . . . . . . . . . . . . . 122 10.4.1 Subaddress 2Dh . . . . . . . . . . . . . . . . . . . . . . 122 10.4.2 Subaddress 2Eh . . . . . . . . . . . . . . . . . . . . . . 122 10.4.3 Subaddress 2Fh . . . . . . . . . . . . . . . . . . . . . . 122 10.5 Programming register audio clock generation. . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.5.1 Subaddresses 30h to 32h. . . . . . . . . . . . . . . 123 10.5.2 Subaddresses 34h to 36h. . . . . . . . . . . . . . . 123 10.5.3 Subaddress 38h . . . . . . . . . . . . . . . . . . . . . . 123 10.5.4 10.5.5 10.6 10.6.1 10.6.2 10.6.3 10.6.4 10.6.5 10.6.6 10.6.7 10.6.8 10.6.9 10.6.10 10.7 10.7.1 10.7.2 10.7.3 10.7.4 10.7.5 10.7.6 10.7.7 10.7.8 10.7.9 10.7.10 10.7.11 10.7.12 11 11.1 11.2 11.3 11.4 11.5 11.5.1 11.5.2 11.5.3 12 13 14 15 16 16.1 16.1.1 16.1.2 17 18 18.1 18.2 18.3 Subaddress 39h . . . . . . . . . . . . . . . . . . . . . . Subaddress 3Ah. . . . . . . . . . . . . . . . . . . . . . Programming register VBI data slicer. . . . . . Subaddress 40h . . . . . . . . . . . . . . . . . . . . . . Subaddresses 41h to 57h . . . . . . . . . . . . . . Subaddress 58h . . . . . . . . . . . . . . . . . . . . . . Subaddress 59h . . . . . . . . . . . . . . . . . . . . . . Subaddress 5Ah. . . . . . . . . . . . . . . . . . . . . . Subaddress 5Bh. . . . . . . . . . . . . . . . . . . . . . Subaddress 5Dh . . . . . . . . . . . . . . . . . . . . . Subaddress 5Eh. . . . . . . . . . . . . . . . . . . . . . Subaddress 60h . . . . . . . . . . . . . . . . . . . . . . Subaddresses 61h and 62h . . . . . . . . . . . . . Programming register interfaces and scaler part . . . . . . . . . . . . . . . . . . . . . . . Subaddress 80h . . . . . . . . . . . . . . . . . . . . . . Subaddresses 83h to 87h . . . . . . . . . . . . . . Subaddress 88h . . . . . . . . . . . . . . . . . . . . . . Subaddress 8Fh. . . . . . . . . . . . . . . . . . . . . . Subaddresses 90h and C0h. . . . . . . . . . . . . Subaddresses 91h to 93h . . . . . . . . . . . . . . Subaddresses 94h to 9Bh . . . . . . . . . . . . . . Subaddresses 9Ch to 9Fh . . . . . . . . . . . . . . Subaddresses A0h to A2h . . . . . . . . . . . . . . Subaddresses A4h to A6h . . . . . . . . . . . . . . Subaddresses A8h to AEh . . . . . . . . . . . . . . Subaddresses B0h to BFh . . . . . . . . . . . . . . Programming start setup . . . . . . . . . . . . . . . Decoder part . . . . . . . . . . . . . . . . . . . . . . . . Component video part and interrupt mask. . Audio clock generation part . . . . . . . . . . . . . Data slicer and data type control part . . . . . Scaler and interfaces . . . . . . . . . . . . . . . . . . Trigger condition. . . . . . . . . . . . . . . . . . . . . . Maximum zoom factor . . . . . . . . . . . . . . . . . Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . Test information. . . . . . . . . . . . . . . . . . . . . . . Boundary scan test . . . . . . . . . . . . . . . . . . . Initialization of boundary scan circuit . . . . . . Device identification codes. . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . 123 123 124 124 124 124 125 125 125 125 125 126 126 126 126 127 131 131 132 133 135 136 137 138 139 140 141 141 142 143 144 145 145 145 146 148 148 149 155 158 158 158 158 160 162 162 162 162 continued >> SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 4 July 2008 174 of 175 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 18.4 19 19.1 19.2 19.3 19.4 19.5 19.6 19.7 20 21 22 22.1 22.2 22.3 22.4 23 24 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Appendix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Issue 1: Bit ICKS3 = 1 (I2C-bus control signal, bit D3 of subaddress 80h) drives image port output clock ICLK to 3-state . . . . Issue 2: Forced odd/even toggle option, enabled by bit FOET = 1 (I2C-bus control signal, bit D5 of subaddress 08h) does not work properly . . . . . . . . . . . . . . . . . . . . . Issue 3: Errors with horizontal lock when using bit HLNRS (I2C-bus control signal, bit D6 of subaddress 03h). . . . . . . . . . . . . . . Issue 4: Erase condition for interrupt pin INT_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Issue 5: Odd/even detection might become unreliable with signals from video tape recorders . . . . . . . . . . . . . . . . . . . Issue 6: Slicing of MOJI VBI data leads to unexpected results . . . . . . . . . . . . . . . . . . . . Issue 7: NTSC-Japan offset compensation does not work as specified in Y/C mode. . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 164 164 165 165 166 166 167 170 170 171 172 172 172 172 172 172 173 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 July 2008 Document identifier: SAF7118_4 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NXP: SAF7118H/V1,557