SC16C654BIBM,151

SC16C654B/654DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoder Rev. 02 — 20 June 2005 Product data sheet 1. General description The SC16C654B/654DB is a Quad Universal Asynchronous Receiver and Transmitter (QUART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s. It comes with an Intel or Motorola interface. The SC16C654B/654DB is pin compatible with the ST16C654 and TL16C754 and it will power-up to be functionally equivalent to the 16C454. Programming of control registers enables the added features of the SC16C654B/654DB. Some of these added features are the 64-byte receive and transmit FIFOs, automatic hardware or software flow control and infrared encoding/decoding. The selectable auto-flow control feature significantly reduces software overload and increases system efficiency while in FIFO mode by automatically controlling serial data flow using RTS output and CTS input signals. The SC16C654B/654DB also provides DMA mode data transfers through FIFO trigger levels and the TXRDY and RXRDY signals. (TXRDY and RXRDY signals are not available in the HVQFN48 package.) On-board status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows on-board diagnostics. The SC16C654B/654DB operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature range, and is available in plastic PLCC68, LQFP64, HVQFN48 and LFBGA64 packages. On the HVQFN48 package, only channel C has all the modem pins. Channel A and channel B have only RTS and CTS pins, and channel D does not have any modem pin. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 4 channel UART 5 V, 3.3 V and 2.5 V operation Industrial temperature range (−40 °C to +85 °C) SC16C654B is pin and software compatible with the industry-standard ST16C454/554, ST16C654, ST68C454/554, TL16C554 SC16C654DB is pin and software compatible with ST16C654D, and software compatible with ST16C454/554, ST68C454/554, TL16C554 Up to 5 Mbit/s data rate at 5 V and 3.3 V and 3 Mbit/s at 2.5 V 5 V tolerant inputs 64-byte transmit FIFO 64-byte receive FIFO with error flags Automatic software (Xon/Xoff)/hardware (RTS/CTS) flow control Programmable Xon/Xoff characters SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Software selectable baud rate generator Four selectable Receive and Transmit FIFO interrupt trigger levels Standard modem interface or infrared (IrDA) encoder/decoder interface Sleep mode Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break) Transmit, Receive, Line Status, and Data Set interrupts independently controlled Fully programmable character formatting: ◆ 5, 6, 7, or 8-bit characters ◆ Even, Odd, or No Parity formats ◆ 1, 11⁄2, or 2-stop bit ◆ Baud generation (DC to 5 Mbit/s) False start-bit detection Complete status reporting capabilities 3-state output TTL drive capabilities for bi-directional data bus and control bus Line break generation and detection Internal diagnostic capabilities: ◆ Loop-back controls for communications link fault isolation Prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, CD). 3. Ordering information Table 1: Ordering information Type number Package Name Description Version SC16C654BIA68 PLCC68 plastic leaded chip carrier; 68 leads SOT188-2 SC16C654BIB64 LQFP64 plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm SOT314-2 SC16C654BIBM LQFP64 plastic low profile quad flat package; 64 leads; body 7 × 7 × 1.4 mm SOT414-1 SC16C654BIBS HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 6 × 6 × 0.85 mm SOT778-3 SC16C654BIEC LFBGA64 plastic low profile fine-pitch ball grid array package; 64 balls; body 6 × 6 × 1.05 mm SOT686-1 SC16C654DBIB64 LQFP64 plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm SOT314-2 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 2 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 4. Block diagram SC16C654B/654DB D0 to D7 IOR IOW RESET TRANSMIT FIFO REGISTERS DATA BUS AND CONTROL LOGIC TRANSMIT SHIFT REGISTER FLOW CONTROL LOGIC REGISTER SELECT LOGIC IR ENCODER RECEIVE FIFO REGISTERS INTERCONNECT BUS LINES AND CONTROL SIGNALS A0 to A2 CSA to CSD TXA to TXD RECEIVE SHIFT REGISTER FLOW CONTROL LOGIC RXA to RXD IR DECODER 16/68 INTA to INTD TXRDY RXRDY DTRA to DTRD RTSA to RTSD INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR MODEM CONTROL LOGIC CTSA to CTSD RIA to RID CDA to CDD DSRA to DSRD INTSEL 002aaa871 XTAL1 XTAL2 CLKSEL Fig 1. Block diagram of SC16C654B/654DB (16 mode) 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 3 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs SC16C654B/654DB D0 to D7 R/W RESET TRANSMIT FIFO REGISTERS DATA BUS AND CONTROL LOGIC TRANSMIT SHIFT REGISTER A0 to A4 CS REGISTER SELECT LOGIC INTERCONNECT BUS LINES AND CONTROL SIGNALS FLOW CONTROL LOGIC TXA to TXD IR ENCODER RECEIVE FIFO REGISTERS RECEIVE SHIFT REGISTER FLOW CONTROL LOGIC RXA to RXD IR DECODER 16/68 IRQ TXRDY RXRDY DTRA to DTRD RTSA to RTSD INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR MODEM CONTROL LOGIC CTSA to CTSD RIA to RID CDA to CDD DSRA to DSRD 002aaa872 XTAL1 XTAL2 CLKSEL Fig 2. Block diagram of SC16C654B/654DB (68 mode) 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 4 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 5. Pinning information D3 1 61 CDD D4 2 62 RID D5 3 63 RXD D6 4 64 VCC D7 5 65 INTSEL GND 6 66 D0 RXA 7 67 D1 RIA 8 68 D2 CDA 9 5.1 Pinning DSRA 10 60 DSRD CTSA 11 59 CTSD DTRA 12 58 DTRD VCC 13 57 GND RTSA 14 56 RTSD INTA 15 55 INTD CSA 16 54 CSD TXA 17 53 TXD SC16C654BIA68 16 mode IOW 18 TXB 19 52 IOR 51 TXC CSB 20 50 CSC INTB 21 49 INTC RTSB 22 48 RTSC GND 23 47 VCC CDC 43 RIC 42 RXC 41 GND 40 TXRDY 39 RESET 37 RXRDY 38 XTAL2 36 XTAL1 35 A0 34 A1 33 A2 32 16/68 31 CLKSEL 30 44 DSRC RXB 29 45 CTSC DSRB 26 RIB 28 46 DTRC CTSB 25 CDB 27 DTRB 24 002aaa873 Fig 3. Pin configuration for PLCC68 (16 mode) 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 5 of 58 SC16C654B/654DB Philips Semiconductors D3 1 61 CDD D4 2 62 RID D5 3 63 RXD D6 4 64 VCC D7 5 65 n.c. GND 6 66 D0 RXA 7 67 D1 RIA 8 68 D2 CDA 9 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs DSRA 10 60 DSRD CTSA 11 59 CTSD DTRA 12 58 DTRD VCC 13 57 GND RTSA 14 56 RTSD IRQ 15 55 n.c. CS 16 54 n.c. TXA 17 53 TXD SC16C654BIA68 68 mode R/W 18 TXB 19 52 n.c. 51 TXC A3 20 50 A4 n.c. 21 49 n.c. RTSB 22 48 RTSC GND 23 47 VCC CDC 43 RIC 42 RXC 41 GND 40 TXRDY 39 RESET 37 RXRDY 38 XTAL2 36 XTAL1 35 A0 34 A1 33 A2 32 16/68 31 CLKSEL 30 44 DSRC RXB 29 45 CTSC DSRB 26 RIB 28 46 DTRC CTSB 25 CDB 27 DTRB 24 002aaa874 Fig 4. Pin configuration for PLCC68 (68 mode) 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 6 of 58 SC16C654B/654DB Philips Semiconductors 49 CDD 50 RID 51 RXD 52 VCC 53 D0 54 D1 55 D2 56 D3 57 D4 58 D5 59 D6 60 D7 61 GND 62 RXA 63 RIA 64 CDA 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs DSRA 1 48 DSRD CTSA 2 47 CTSD DTRA 3 46 DTRD VCC 4 45 GND RTSA 5 44 RTSD INTA 6 43 INTD CSA 7 TXA 8 IOW 9 42 CSD SC16C654BIB64 SC16C654BIBM SC16C654DBIB64 41 TXD 40 IOR DSRC 32 CDC 31 RIC 30 RXC 29 GND 28 RESET 27 XTAL2 26 XTAL1 25 33 CTSC A0 24 CTSB 16 A1 23 35 VCC 34 DTRC A2 22 DTRB 15 VCC 21 36 RTSC GND 14 RXB 20 37 INTC RTSB 13 RIB 19 38 CSC INTB 12 CDB 18 39 TXC CSB 11 DSRB 17 TXB 10 002aaa875 Fig 5. Pin configuration for LQFP64 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 7 of 58 SC16C654B/654DB Philips Semiconductors 37 GND 38 RXD 39 D0 40 D1 41 D2 42 D3 43 D4 44 D5 45 D6 46 D7 terminal 1 index area 47 GND 48 RXA 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs CTSA 1 36 INTD VCC 2 35 CSD RTSA 3 34 TXD INTA 4 33 IOR CSA 5 TXA 6 IOW 7 TXB 8 29 RTSC CSB 9 28 VCC 32 TXC 31 CSC SC16C654BIBS 16 mode 30 INTC RXC 22 RIC 23 CDC 24 39 D0 38 RXD 37 GND GND 21 RESET 20 XTAL2 19 XTAL1 18 A0 17 A1 16 25 DSRC A2 15 26 CTSC CTSB 12 RXB 13 27 DTRC RTSB 11 16/68 14 INTB 10 002aab568 Transparent top view 40 D1 41 D2 42 D3 43 D4 44 D5 45 D6 46 D7 terminal 1 index area 47 GND 48 RXA Fig 6. Pin configuration for HVQFN48 (16 mode) CTSA 1 36 n.c. VCC 2 35 CSD RTSA 3 34 TXD IRQ 4 33 IOR CS 5 TXA 6 R/W 7 TXB 8 29 RTSC A3 9 28 VCC 32 TXC 31 A4 SC16C654BIBS 68 mode 30 n.c. CDC 24 RIC 23 RXC 22 GND 21 RESET 20 XTAL2 19 XTAL1 18 A0 17 A1 16 25 DSRC A2 15 26 CTSC CTSB 12 RXB 13 27 DTRC RTSB 11 16/68 14 n.c. 10 002aab565 Transparent top view Fig 7. Pin configuration for HVQFN48 (68 mode) 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 8 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs ball A1 index area SC16C654BIEC 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K 002aab566 Transparent top view Fig 8. Pin configuration for LFBGA64 1 2 3 4 5 6 7 8 9 10 A CDA RIA RXA D7 D5 D3 D1 VCC RID CDD B DSRA VCC GND D6 D4 D2 D0 RXD DSRD CTSD C CTSA RTSA DTRD RTSD D DTRA INTA GND INTD E CSA TXA CSD TXD F IOW TXB IOR TXC G CSB INTB CSC INTC H GND RTSB RTSC VCC J DTRB CTSB RIB VCC A1 XTAL1 RESET RXC CDC DTRC K DSRB CDB RXB A2 A0 XTAL2 GND RIC DSRC CTSC 002aab567 Fig 9. Ball mapping for LFBGA64 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 9 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 5.2 Pin description Table 2: Pin description Symbol Pin Type Description PLCC68 LQFP64 HVQFN48 LFBGA6 4 16/68 31 - 14 - I 16/68 Interface type select (input with internal pull-up). This input provides the 16 (Intel) or 68 (Motorola) bus interface type select. The functions of IOR, IOW, INTA to INTD, and CSA to CSD are re-assigned with the logical state of this pin. When this pin is a logic 1, the 16 mode interface (16C654) is selected. When this pin is a logic 0, the 68 mode interface (68C654) is selected. When this pin is a logic 0, IOW is re-assigned to R/W, RESET is re-assigned to RESET, IOR is not used, and INTA to INTD are connected in a wire-OR configuration. The wire-OR outputs are connected internally to the open-drain IRQ signal output. This pin is not available on 64-pin packages which operate in the 16 mode only. A0 34 24 17 K5 I Address 0 select bit. Internal registers address selection in 16 and 68 modes. A1 33 23 16 J5 I Address 1 select bit. Internal registers address selection in 16 and 68 modes. A2 32 22 15 K4 I Address 2 select bit. Internal registers address selection in 16 and 68 modes. A3 20 - 9 - I A4 50 - 31 - Address 3, Address 4 select bits. When the 68 mode is selected, these pins are used to address or select individual UARTs (providing CS is a logic 0). In the 16 mode, these pins are re-assigned as chip selects, see CSB and CSC. These pins are not available on 64-pin packages which operate in the 16 mode only. CDA 9 64 - A1 I CDB 27 18 - K2 CDC 43 31 24 J9 Carrier Detect (active LOW). These inputs are associated with individual UART channels A through D. A logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. CDD 61 49 - A10 CLKSEL 30 - - - I Clock Select. The 1× or 4× pre-scalable clock is selected by this pin. The 1× clock is selected when CLKSEL is a logic 1 (connected to VCC) or the 4× is selected when CLKSEL is a logic 0 (connected to GND). MCR[7] can override the state of this pin following reset or initialization (see MCR[7]). This pin is not available on 64-pin packages which provide MCR[7] selection only. CS 16 - 5 - I Chip Select (active LOW). In the 68 mode, this pin functions as a multiple channel chip enable. In this case, all four UARTs (A to D) are enabled when the CS pin is a logic 0. An individual UART channel is selected by the data contents of address bits A[3:4]. when the 16 mode is selected (68-pin devices), this pin functions as CSA (see definition under CSA, CSB). This pin is not available on 64-pin packages which operate in the 16 mode only. 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 10 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 2: Pin description …continued Symbol Pin Type Description PLCC68 LQFP64 HVQFN48 LFBGA6 4 CSA 16 7 5 E1 CSB 20 11 9 G1 CSC 50 38 31 G9 CSD 54 42 35 E9 CTSA 11 2 1 C1 CTSB 25 16 12 J2 CTSC 45 33 26 K10 CTSD 59 47 - B10 I Chip Select A, B, C, D (active LOW). This function is associated with the 16 mode only, and for individual channels ‘A’ through ‘D’. When in 16 mode, these pins enable data transfers between the user CPU and the SC16C654B/654DB for the channel(s) addressed. Individual UART sections (A, B, C, D) are addressed by providing a logic 0 on the respective CSA to CSD pin. When the 68 mode is selected, the functions of these pins are re-assigned. 68 mode functions are described under their respective name/pin headings. I Clear to Send (active LOW). These inputs are associated with individual UART channels A through D. A logic 0 on the CTS pin indicates the modem or data set is ready to accept transmit data from the SC16C654B/654DB. Status can be tested by reading MSR[4]. This pin only affects the transmit or receive operations when Auto CTS function is enabled via the Enhanced Feature Register EFR[7] for hardware flow control operation. D0 to D2, 66 to 68 53 to 55, 39 to 41, D3 to D7 , 1 to 5 56 to 60 42 to 46 B7, A7, B6, A6, B5, A5, B4, A4 I/O Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. DSRA 10 1 - B1 I DSRB 26 17 - K1 DSRC 44 32 25 K9 DSRD 60 48 - B9 Data Set Ready (active LOW). These inputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. This pin has no effect on the UART’s transmit or receive operation. DTRA 12 3 - D1 O DTRB 24 15 - J1 DTRC 46 34 27 J10 DTRD 58 46 - C9 Data Terminal Ready (active LOW). These outputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates that the SC16C654B/654DB is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. This pin has no effect on the UART’s transmit or receive operation. GND 6, 23, 40, 57 14, 28, 45, 61 21, 37, 47 B3, K7, H1, D9 I Signal and power ground. O Interrupt A, B, C, D (active HIGH). This function is associated with the 16 mode only. These pins provide individual channel interrupts INTA to INTD. INTA to INTD are enabled when MCR[3] is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. When the 68 mode is selected, the functions of these pins are re-assigned. 68 mode functions are described under their respective name/pin headings. INTA 15 6 4 D2 INTB 21 12 10 G2 INTC 49 37 30 G10 INTD 55 43 36 D10 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 11 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 2: Pin description …continued Symbol Pin Type Description PLCC68 LQFP64 HVQFN48 LFBGA6 4 INTSEL 65 - - - I Interrupt Select (active HIGH, with internal pull-down). This function is associated with the 16 mode only. When the 16 mode is selected, this pin can be used in conjunction with MCR[3] to enable or disable the 3-state interrupts, INTA to INTD, or override MCR[3] and force continuous interrupts. Interrupt outputs are enabled continuously by making this pin a logic 1. Making this pin a logic 0 allows MCR[3] to control the 3-state interrupt output. In this mode, MCR[3] is set to a logic 1 to enable the 3-state outputs. This pin is disabled in the 68 mode. Due to pin limitations on the 64-pin packages, this pin is not available. To cover this limitation, the SC16C654DBIB64 version operates in the continuous interrupt enable mode by bonding this pin to VCC internally. The SC16C654BIB64 operates with MCR[3] control by bonding this pin to GND. IOR 52 40 33 F9 I Input/Output Read strobe (active LOW). This function is associated with the 16 mode only. A logic 0 transition on this pin will load the contents of an internal register defined by address bits A[0:2] onto the SC16C654B/654DB data bus (D[0:7]) for access by external CPU. This pin is disabled in the 68 mode. IOW 18 9 7 F1 I Input/Output Write strobe (active LOW). This function is associated with the 16 mode only. A logic 0 transition on this pin will transfer the contents of the data bus (D[0:7]) from the external CPU to an internal register that is defined by address bits A[0:2]. When the 68 mode is selected (PLCC68), this pin functions as R/W (see definition under R/W). IRQ 15 - 4 - O Interrupt Request or Interrupt ‘A’. This function is associated with the 68 mode only. In the 68 mode, interrupts from UART channels A-D are wire-ORed internally to function as a single IRQ interrupt. This pin transitions to a logic 0 (if enabled by the interrupt enable register) whenever a UART channel(s) requires service. Individual channel interrupt status can be determined by addressing each channel through its associated internal register, using CS and A[3:4]. In the 68 mode, and external pull-up resistor must be connected between this pin and VCC. The function of this pin changes to INTA when operating in the 16 mode (see definition under INTA). n.c. 21, 49, 52, 54, 55, 65 - - - - not connected RESET, RESET 37 27 20 J7 I Reset. In the 16 mode, a logic 1 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See Section 7.11 “SC16C654B/654DB external reset conditions” for initialization details.) When 16/68 is a logic 0 (68 mode), this pin functions similarly, but as an inverted reset interface signal, RESET. 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 12 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 2: Pin description …continued Symbol Pin Type Description PLCC68 LQFP64 HVQFN48 LFBGA6 4 RIA 8 63 - A2 RIB 28 19 - J3 RIC 42 30 23 K8 RID 62 50 - A9 RTSA 14 5 3 C2 RTSB 22 13 11 H2 RTSC 48 36 29 H9 RTSD 56 44 - C10 R/W 18 - 7 - I Ring Indicator (active LOW). These inputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt. O Request to Send (active LOW). These outputs are associated with individual UART channels, A through D. A logic 0 on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this pin to a logic 0, indicating data is available. After a reset this pin will be set to a logic 1. This pin only affects the transmit and receive operations when Auto RTS function is enabled via the Enhanced Feature Register (EFR[6]) for hardware flow control operation. I Read/Write strobe. This function is associated with the 68 mode only. This pin provides the combined functions for Read or Write strobes. Logic 1 = Read from UART register selected by CS and A[0:4]. Logic 0 = Write to UART register selected by CS and A[0:4]. RXA 7 62 48 A3 I Receive data input RXA-RXD. These inputs are associated with individual serial channel data to the SC16C654B/654DB. The RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the RX input pin is disabled and TX data is connected to the UART RX input internally. RXB 29 20 13 K3 RXC 41 29 22 J8 RXD 63 51 38 B8 RXRDY 38 - - - O Receive Ready (active LOW). This function is associated with 68-pin package only. RXRDY contains the wire-ORed status of all four receive channel FIFOs, RXRDYA-RXRDYD. A logic 0 indicates receive data ready status, that is, the RHR is full, or the FIFO has one or more RX characters available for unloading. This pin goes to a logic 1 when the FIFO/RHR is empty, or when there are no more characters available in either the FIFO or RHR. Individual channel RX status is read by examining individual internal registers via CS and A[0:4] pin functions. TXA 17 8 6 E2 O 10 8 F2 51 39 32 F10 53 41 34 E10 Transmit data A, B, C, D. These outputs are associated with individual serial transmit channel data from the SC16C654B/654DB. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the TX output pin is disabled and TX data is internally connected to the UART RX input. TXB 19 TXC TXD 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 13 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 2: Pin description …continued Symbol Pin Type Description PLCC68 LQFP64 HVQFN48 LFBGA6 4 TXRDY 39 - - - O Transmit Ready (active LOW). This function is associated with the 68-pin package only. TXRDY contains the wire-ORed status of all four transmit channel FIFOs, TXRDYA-TXRDYD. A logic 0 indicates a buffer ready status, that is, at least one location is empty and available in one of the TX channels (A to D). This pin goes to a logic 1 when all four channels have no more empty locations in the TX FIFO or THR. Individual channel TX status can be read by examining individual internal registers via CS and A[0:4] pin functions. VCC 13, 47, 64 4, 21, 35, 52 2, 28 A8, B2, J4, H10 I Power supply inputs. XTAL1 35 25 18 J6 I Crystal or external clock input. Functions as a crystal input or as an external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit; see Figure 10. Alternatively, an external clock can be connected to this pin to provide custom data rates; see Section 6.9 “Programmable baud rate generator”. XTAL2 36 26 19 K6 O Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal oscillator output or buffered clock output. 6. Functional description The SC16C654B/654DB provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character. Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex, especially when manufactured on a single integrated silicon chip. The SC16C654B/654DB represents such an integration with greatly enhanced features. The SC16C654B/654DB is fabricated with an advanced CMOS process to achieve low drain power and high speed requirements. The SC16C654B/654DB is an upward solution that provides 64 bytes of transmit and receive FIFO memory, instead of 16 bytes provided in the 16C554, or none in the 16C454. The SC16C654B/654DB is designed to work with high speed modems and shared network environments that require fast data processing time. Increased performance is realized in the SC16C654B/654DB by the larger transmit and receive FIFOs. This allows the external processor to handle more networking tasks within a given time. For example, the SC16C554 with a 16-byte FIFO unloads 16 bytes of receive data in 1.53 ms. (This example uses a character length of 11 bits, including start/stop bits at 115.2 kbit/s.) This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However, with the 64-byte FIFO in the SC16C654B/654DB, the data buffer will not require unloading/loading for 6.1 ms. This increases the service interval, giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 14 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs time. In addition, the four selectable levels of FIFO trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data throughput performance, especially when operating in a multi-channel environment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The SC16C654B/654DB combines the package interface modes of the 16C454/554 and 68C454/554 series on a single integrated chip. The 16 mode interface is designed to operate with the Intel-type of microprocessor bus, while the 68 mode is intended to operate with Motorola and other popular microprocessors. Following a reset, the SC16C654B/654DB is downward compatible with the 16C454/554 or the 68C454/554, dependent on the state of the interface mode selection pin, 16/68. The SC16C654B/654DB is capable of operation to 1.5 Mbit/s with a 24 MHz crystal and up to 5 Mbit/s with an external clock input (at 3.3 V and 5 V; at 2.5 V the max speed is 3 Mbit/s). With a crystal of 14.7464 MHz, and through a software option, the user can select data rates up to 460.8 kbit/s or 921.6 kbit/s, 8 times faster than the 16C554. The rich feature set of the SC16C654B/654DB is available through internal registers. Automatic hardware/software flow control, selectable transmit and receive FIFO trigger levels, selectable TX and RX baud rates, infrared encoder/decoder interface, modem interface controls, and a sleep mode are all standard features. MCR[5] provides a facility for turning off (Xon) software flow control with any incoming (RX) character. In the 16 mode, INTSEL and MCR[3] can be configured to provide a software controlled or continuous interrupt capability. Due to pin limitations of the 64-pin package, this feature is offered by two different LQFP64 packages. The SC16C654DB operates in the continuous interrupt enable mode by bonding INTSEL to VCC internally. The SC16C654B operates in conjunction with MCR[3] by bonding INTSEL to GND internally. The PLCC68 SC16C654B package offers a clock select pin to allow system/board designers to preset the default baud rate table. The CLKSEL pin selects the 1× or 4× pre-scalable baud rate generator table during initialization, but can be overridden following initialization by MCR[7]. 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 15 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 6.1 Interface options Two user interface modes are selectable for the PLCC68 package. These interface modes are designated as the ‘16 mode’ and the ‘68 mode’. This nomenclature corresponds to the early 16C454/554 and 68C454/554 package interfaces respectively. 6.1.1 The 16 mode interface The 16 mode configures the package interface pins for connection as a standard 16 series (Intel) device and operates similar to the standard CPU interface available on the 16C454/554. In the 16 mode (pin 16/68 = logic 1), each UART is selected with individual chip select (CSx) pins, as shown in Table 3. Table 3: Serial port channel selection, 16 mode interface CSA CSB CSC CSD UART channel 1 1 1 1 none 0 1 1 1 A 1 0 1 1 B 1 1 0 1 C 1 1 1 0 D 6.1.2 The 68 mode interface The 68 mode configures the package interface pins for connection with Motorola, and other popular microprocessor bus types. The interface operates similar to the 68C454/554. In this mode, the SC16C654B/654DB decodes two additional addresses, A3-A4, to select one of the four UART ports. The A[3:4] address decode function is used only when in the 68 mode (16/68 = logic 0), and is shown in Table 4. Table 4: Serial port channel selection, 68 mode interface CS A4 A3 UART channel 1 n/a n/a none 0 0 0 A 0 0 1 B 0 1 0 C 0 1 1 D 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 16 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 6.2 Internal registers The SC16C654B/654DB provides 17 internal registers for monitoring and control. These registers are shown in Table 5. Twelve registers are similar to those already available in the standard 16C554. These registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user accessible scratchpad register (SPR). Beyond the general 16C554 features and capabilities, the SC16C654B/654DB offers an enhanced feature register set (EFR, Xon/Xoff1-2) that provides on-board hardware/software flow control. Register functions are more fully described in the following paragraphs. Table 5: A2 Internal registers decoding A1 A0 Read mode Write mode General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR) [1] 0 0 0 Receive Holding Register Transmit Holding Register 0 0 1 Interrupt Enable Register Interrupt Enable Register 0 1 0 Interrupt Status Register FIFO Control Register 0 1 1 Line Control Register Line Control Register 1 0 0 Modem Control Register Modem Control Register 1 0 1 Line Status Register n/a 1 1 0 Modem Status Register n/a 1 1 1 Scratchpad Register Scratchpad Register Baud rate register set (DLL/DLM) [2] 0 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 0 1 MSB of Divisor Latch MSB of Divisor Latch Enhanced register set (EFR, Xon/off 1-2) [3] 0 1 0 Enhanced Feature Register Enhanced Feature Register 1 0 0 Xon1 word Xon1 word 1 0 1 Xon2 word Xon2 word 1 1 0 Xoff1 word Xoff1 word 1 1 1 Xoff2 word Xoff2 word [1] [2] [3] These registers are accessible only when LCR[7] is a logic 0. These registers are accessible only when LCR[7] is a logic 1. Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to ‘BFh’. 6.3 FIFO operation The 64-byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit 0. With SC16C554 devices, the user can set the receive trigger level, but not the transmit trigger level. The SC16C654B/654DB provides independent trigger levels for both receiver and transmitter. To remain compatible with SC16C554, the transmit interrupt trigger level is set to 8 following a reset. It should be noted that the user can set the transmit trigger levels by writing to the FCR register, but activation will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 17 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached. (For a description of this timing, see Section 6.4 “Hardware flow control”.) Table 6: RX trigger levels Selected trigger level (characters) INT pin activation Negate RTS or send Xoff (characters) Assert RTS or send Xon (characters) 8 8 16 0 16 16 56 8 56 56 60 16 60 60 60 56 6.4 Hardware flow control When automatic hardware flow control is enabled, the SC16C654B/654DB monitors the CTS pin for a remote buffer overflow indication and controls the RTS pin for local buffer overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the SC16C654B/654DB will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS input returns to a logic 0, indicating more data may be sent. With the Auto RTS function enabled, an interrupt is generated when the receive FIFO reaches the programmed trigger level. The RTS pin will not be forced to a logic 1 (RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the programmed trigger. However, under the above described conditions, the SC16C654B/654DB will continue to accept data until the receive FIFO is full. Remark: Hardware flow control is not supported on channel D in the HVQFN48 package. 6.5 Software flow control When software flow control is enabled, the SC16C654B/654DB compares one or two sequential receive data characters with the programmed Xon/Xoff or Xoff1,2 character value(s). If received character(s) match the programmed values, the SC16C654B/654DB will halt transmission (TX) as soon as the current character(s) has completed transmission. When a match occurs, the receive ready (if enabled via Xoff IER[5]) flags will be set and the interrupt output pin (if receive interrupt is enabled) will be activated. Following a suspension due to a match of the Xoff characters’ values, the SC16C654B/654DB will monitor the receive data stream for a match to the Xon1,2 character value(s). If a match is found, the SC16C654B/654DB will resume operation and clear the flags (ISR[4]). The SC16C654B/654DB offers a special Xon mode via MCR[5]. The initialized default setting of MCR[5] is a logic 0. In this state, Xoff and Xon will operate as defined above. Setting MCR[5] to a logic 1 sets a special operational mode for the Xon function. In this case, Xoff operates normally, however, transmission (Xon) will resume with the next character received, that is, a match is declared simply by the receipt of an incoming (RX) character. 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 18 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset, the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff characters and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected, the SC16C654B/654DB compares two consecutive receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO. In the event that the receive buffer is overfilling and flow control needs to be executed, the SC16C654B/654DB automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. The SC16C654B/654DB sends the Xoff1,2 characters as soon as received data passes the programmed trigger level. To clear this condition, the SC16C654B/654DB will transmit the programmed Xon1,2 characters as soon as receive data drops below the programmed trigger level. 6.6 Special feature software flow control A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit character is detected, it will be placed on the user-accessible data stack along with normal incoming RX data. This condition is selected in conjunction with EFR[0:3]. Note that software flow control should be turned off when using this special mode by setting EFR[0:3] to a logic 0. The SC16C654B/654DB compares each incoming receive character with Xoff2 data. If a match exists, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate detection of a special character. Although the Internal Register Table (Table 8) shows each X-Register with eight bits of character information, the actual number of bits is dependent on the programmed word length. Line Control Register bits LCR[0:1] define the number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length selected by LCR[0:1] also determine the number of bits that will be used for the special character comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive character. 6.7 Xon any feature A special feature is provided to return the Xoff flow control to the inactive state following its activation. In this mode, any RX character received will return the Xoff flow control to the inactive state so that transmissions may be resumed with a remote buffer. This feature is more fully defined in Section 6.5 “Software flow control”. 6.8 Hardware/software and time-out interrupts Three special interrupts have been added to monitor the hardware and software flow control. The interrupts are enabled by IER[5:7]. Care must be taken when handling these interrupts. Following a reset, the transmitter interrupt is enabled, the SC16C654B/654DB will issue an interrupt to indicate that the Transmit Holding Register is empty. This interrupt must be serviced prior to continuing operations. The LSR register provides the current singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have lowest interrupt priority. A condition can exist where a higher priority interrupt may mask the lower priority CTS/RTS interrupt(s). Only after servicing the higher pending interrupt will the lower priority CTS/TRS interrupt(s) be reflected in the status register. Servicing the interrupt without investigating further interrupt conditions can result in data errors. 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 19 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs When two interrupt conditions have the same priority, it is important to service these interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case, the SC16C654B/654DB FIFO may hold more characters than the programmed trigger level. Following the removal of a data byte, the user should re-check LSR[0] for additional characters. A Receive Time Out will not occur if the receive FIFO is empty. The time-out counter is reset at the center of each stop bit received or each time the receive holding register (RHR) is read. The actual time-out value is 4 character time. In the 16 mode for the PLCC68 package, the system/board designer can optionally provide software controlled 3-state interrupt operation. This is accomplished by INTSEL and MCR[3]. When INTSEL interface pin is left open or made a logic 0, MCR[3] controls the 3-state interrupt outputs, INTA to INTD. When INTSEL is a logic 1, MCR[3] has no effect on the INTA to INTD outputs, and the package operates with interrupt outputs enabled continuously. 6.9 Programmable baud rate generator The SC16C654B/654DB supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s. A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator is capable of accepting an input clock up to 80 MHz (for 3.3 V and 5 V operation), as required for supporting a 5 Mbit/s data rate. The SC16C654B/654DB can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal (parallel resonant/22 pF to 33 pF load) is connected externally between the XTAL1 and XTAL2 pins; see Figure 10. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates; see Table 7. XTAL1 XTAL2 X1 1.8432 MHz C1 22 pF XTAL1 XTAL2 X1 1.8432 MHz C2 33 pF C1 22 pF 1.5 kΩ C2 47 pF 002aaa870 Fig 10. Crystal oscillator connection The generator divides the input 16× clock by any divisor from 1 to (216 − 1). The SC16C654B/654DB divides the basic external clock by 16. Further division of this 16× clock provides two table rates to support low and high data rate applications using the same system design. After a hardware reset and during initialization, the 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 20 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs SC16C654B/654DB sets the default baud rate table according to the state of the CLKSEL pin. A logic 1 on CLKSEL will set the 1× clock default, whereas logic 0 will set the 4× clock default table. Following the default clock rate selection during initialization, the rate tables can be changed by the internal register MCR[7]. Setting MCR[7] to a logic 1 when CLKSEL is a logic 1 provides an additional divide-by-4, whereas setting MCR[7] to a logic 0 only divides by 1; see Table 7 and Figure 11. Customized baud rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator. Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 7 shows the two selectable baud rate tables available when using a 7.3728 MHz crystal. Table 7: Baud rate generator programming table using a 7.3728 MHz clock Output baud rate User 16× clock divisor HEX DLM program value (HEX) DLL program value (HEX) MCR[7] = 1 MCR[7] = 0 Decimal 50 200 2304 900 09 00 300 600 1200 384 180 01 80 2400 192 C0 00 C0 1200 4800 96 60 00 60 2400 9600 48 30 00 30 4800 19.2 k 24 18 00 18 9600 38.4 k 12 0C 00 0C 19.2 k 76.8 k 6 06 00 06 38.4 k 153.6 k 3 03 00 03 57.6 k 230.4 k 2 02 00 02 115.2 k 460.8 k 1 01 00 01 DIVIDE-BY-1 LOGIC XTAL1 XTAL2 MCR[7] = 0 CLOCK OSCILLATOR LOGIC BAUD RATE GENERATOR LOGIC DIVIDE-BY-4 LOGIC BAUDOUT MCR[7] = 1 002aaa208 Fig 11. Baud rate generator circuitry 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 21 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 6.10 DMA operation The SC16C654B/654DB FIFO trigger level provides additional flexibility to the user for block mode operation. LSR[5:6] provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA mode is de-activated (DMA Mode 0), the SC16C654B/654DB activates the interrupt output pin for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1), the user takes the advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the preset trigger level. In this mode, the SC16C654B/654DB sets the interrupt output pin when characters in the transmit FIFOs are below the transmit trigger level, or the characters in the receive FIFOs are above the receive trigger level. Remark: DMA operation is not supported in the HVQFN48 package option. 6.11 Sleep mode The SC16C654B/654DB is designed to operate with low power consumption. A special sleep mode is included to further reduce power consumption when the chip is not being used. With EFR[4] and IER[4] enabled (set to a logic 1), the SC16C654B/654DB enters the sleep mode, but resumes normal operation when a start bit is detected, a change of state on any of the modem input pins RX, RI, CTS, DSR, CD, or a transmit data is provided by the user. If the sleep mode is enabled and the SC16C654B/654DB is awakened by one of the conditions described above, it will return to the sleep mode automatically after the last character is transmitted or read by the user. In any case, the sleep mode will not be entered while an interrupt(s) is pending. The SC16C654B/654DB will stay in the sleep mode of operation until it is disabled by setting IER[4] to a logic 0. 6.12 Loop-back mode The internal loop-back capability allows on-board diagnostics. In the loop-back mode, the normal modem interface pins are disconnected and reconfigured for loop-back internally. MCR[0:3] register bits are used for controlling loop-back diagnostic testing. In the loop-back mode, OP1 and OP2 in the MCR register (bits 2:3) control the modem RI and CD inputs, respectively. MCR signals DTR and RTS (bits 0:1) are used to control the modem DSR and CTS inputs, respectively. The transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally; see Figure 12. The CTS, DSR, CD, and RI are disconnected from their normal modem control input pins, and instead are connected internally to RTS, DTR, OP2 and OP1. Loop-back test data is entered into the transmit holding register via the user data bus interface, D[0:7]. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loop-back connection. The receive UART converts the serial data back into parallel data that is then made available at the user data interface D[0:7]. The user optionally compares the received data to the initial transmitted data for verifying error-free operation of the UART TX/RX circuits. In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. However, the interrupts can only be read using lower four bits of the Modem Status Register (MSR[0:3]) instead of the four Modem Status Register bits 4:7. The interrupts are still controlled by the IER. 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 22 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs SC16C654B/654DB TXA to TXD DATA BUS AND CONTROL LOGIC REGISTER SELECT LOGIC INTERCONNECT BUS LINES AND CONTROL SIGNALS FLOW CONTROL LOGIC A0 to A2 CSA to CSD TRANSMIT SHIFT REGISTER RECEIVE FIFO REGISTERS FLOW CONTROL LOGIC IR ENCODER MCR[4] = 1 D0 to D7 IOR IOW RESET TRANSMIT FIFO REGISTERS RECEIVE SHIFT REGISTER RXA to RXD IR DECODER RTSA to RTSD CTSA to CTSD DTRA to DTRD MODEM CONTROL LOGIC INTA to INTD TXRDY RXRDY INTERRUPT CONTROL LOGIC DSRA to DSRD OP1A to OP1D CLOCK AND BAUD RATE GENERATOR RIA to RID OP2A to OP2D CDA to CDD 002aaa876 XTAL1 XTAL2 Fig 12. Internal loop-back mode diagram 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 23 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7. Register descriptions Table 8 details the assigned bit functions for the SC16C654B/654DB internal registers. The assigned bit functions are more fully defined in Section 7.1 through Section 7.11. Table 8: SC16C654B/654DB internal registers A2 A1 A0 Register Default [1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Sleep mode [3] modem status interrupt receive transmit line status holding interrupt register receive holding register Set [2] General Register 0 0 0 RHR XX 0 0 0 THR XX bit 7 0 0 1 IER 00 RTS Xoff CTS interrupt interrupt interrupt [3] [3] [3] 0 1 0 FCR 00 RCVR trigger (MSB) RCVR trigger (LSB) TX TX trigger DMA trigger (LSB) [3] mode (MSB) [3] select [4] XMIT RCVR FIFO reset FIFO reset FIFO enable 0 1 0 ISR 01 FIFOs enabled FIFOs enabled INT priority bit 4 INT priority bit 2 INT priority bit 1 INT priority bit 0 INT status 0 1 1 LCR 00 divisor latch enable set break set parity even parity parity enable stop bits word length bit 1 word length bit 0 1 0 0 MCR 00 Clock select [3] IR Xon enable [3] Any [3] loop back OP2, INTx OP1 enable RTS DTR 1 0 1 LSR 60 FIFO data error trans. empty trans. holding empty break interrupt framing error parity error overrun error receive data ready 1 1 0 MSR X0 CD RI DSR CTS ∆CD ∆RI ∆DSR ∆CTS 1 1 1 SPR FF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Special Register INT priority bit 3 Set [5] 0 0 0 DLL XX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 DLM XX bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Enhanced Register Set [6] 0 1 0 EFR 00 Auto CTS Auto RTS Special char. select Cont-3 Tx, Cont-2 Tx, Cont-1 Enable IER[4:7], Rx Control Rx Control Tx, Rx Control ISR[4:5], FCR[4:5], MCR[5:7] Cont-0 Tx, Rx Control 1 0 0 Xon-1 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 0 1 Xon-2 00 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 1 1 0 Xoff-1 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 1 1 Xoff-2 00 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 [1] The value shown represents the register’s initialized HEX value; X = not applicable. [2] These registers are accessible only when LCR[7] = 0. [3] These bits are only accessible when EFR[4] is set. [4] This function is not supported in the HVQFN48 package; TXRDY and RXRDY are removed. [5] The Special Register set is accessible only when LCR[7] is set to a logic 1. [6] Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to ‘BFh’. 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 24 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR. Note that a write operation can be performed when the THR empty flag is set (logic 0 = FIFO full; logic 1 = at least one FIFO location available). The serial receive section also contains an 8-bit Receive Holding Register (RHR). Receive data is removed from the SC16C654B/654DB and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16× clock rate. After 71⁄2 clocks, the start bit time should be shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. Receiver status codes will be posted in the LSR. 7.2 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the INTA to INTD output pins in the 16 mode, or on wire-OR IRQ output pin in the 68 mode. Table 9: Interrupt Enable Register bits description Bit Symbol Description 7 IER[7] CTS interrupt. logic 0 = disable the CTS interrupt (normal default condition) logic 1 = enable the CTS interrupt. The SC16C654B/654DB issues an interrupt when the CTS pin transitions from a logic 0 to a logic 1. 6 IER[6] RTS interrupt. logic 0 = disable the RTS interrupt (normal default condition) logic 1 = enable the RTS interrupt. The SC16C654B/654DB issues an interrupt when the RTS pin transitions from a logic 0 to a logic 1. 5 IER[5] Xoff interrupt. logic 0 = disable the software flow control, receive Xoff interrupt (normal default condition) logic 1 = enable the software flow control, receive Xoff interrupt. See Section 6.5 “Software flow control” for details. 4 IER[4] Sleep mode. logic 0 = disable Sleep mode (normal default condition) logic 1 = enable Sleep mode. See Section 6.11 “Sleep mode” for details. 3 IER[3] Modem Status Interrupt. logic 0 = disable the modem status register interrupt (normal default condition) logic 1 = enable the modem status register interrupt 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 25 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 9: Interrupt Enable Register bits description …continued Bit Symbol Description 2 IER[2] Receive Line Status interrupt. logic 0 = disable the receiver line status interrupt (normal default condition) logic 1 = enable the receiver line status interrupt 1 IER[1] Transmit Holding Register interrupt. This interrupt will be issued whenever the THR is empty, and is associated with LSR[1]. logic 0 = disable the transmitter empty interrupt (normal default condition) logic 1 = enable the transmitter empty interrupt 0 IER[0] Receive Holding Register interrupt. This interrupt will be issued when the FIFO has reached the programmed trigger level, or is cleared when the FIFO drops below the trigger level in the FIFO mode of operation. logic 0 = disable the receiver ready interrupt (normal default condition) logic 1 = enable the receiver ready interrupt 7.2.1 IER versus Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level. • FIFO status will also be reflected in the user accessible ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. • The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0:3] enables the SC16C654B/654DB in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR, either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). • • • • • LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO. LSR[1:4] will provide the type of errors encountered, if any. LSR[5] will indicate when the transmit FIFO is empty. LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty. LSR[7] will indicate any FIFO data errors. 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 26 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. 7.3.1 DMA mode 7.3.1.1 Mode 0 (FCR bit 3 = 0) Set and enable the interrupt for each single transmit or receive operation, and is similar to the 16C454 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty transmit space is available in the Transmit Holding Register (THR). Receive Ready (RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with a character. 7.3.1.2 Mode 1 (FCR bit 3 = 1) Set and enable the interrupt in a block mode operation. The transmit interrupt is set when the transmit FIFO is below the programmed trigger level. TXRDY remains a logic 0 as long as one empty FIFO location is available. The receive interrupt is set when the receive FIFO fills to the programmed trigger level. However, the FIFO continues to fill regardless of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill level is above the programmed trigger level. 7.3.2 FIFO mode Table 10: FIFO Control Register bits description Bit Symbol Description 7:6 FCR[7] (MSB), RCVR trigger. These bits are used to set the trigger level for the receive FCR[6] (LSB) FIFO interrupt. An interrupt is generated when the number of characters in the FIFO equals the programmed trigger level. However, the FIFO will continue to be loaded until it is full. Refer to Table 11. 5:4 FCR[5] (MSB), TX trigger. FCR[4] (LSB) These bits are used to set the trigger level for the transmit FIFO interrupt. The SC16C654B/654DB will issue a transmit empty interrupt when the number of characters in FIFO drops below the selected trigger level. Refer to Table 12. 3 FCR[3] DMA mode select. logic 0 = set DMA mode ‘0’ (normal default condition) logic 1 = set DMA mode ‘1’ Transmit operation in mode ‘0’: When the SC16C654B/654DB is in the 16C454 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no characters in the transmit FIFO or transmit holding register, the TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after the first character is loaded into the transmit holding register. Receive operation in mode ‘0’: When the SC16C654B/654DB is in mode ‘0’ (FCR[0] = logic 0), or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is at least one character in the receive FIFO, the RXRDY pin will be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there are no more characters in the receiver. 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 27 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 10: FIFO Control Register bits description …continued Bit Symbol Description 3 (cont.) FCR[3] (continued) Transmit operation in mode ‘1’: When the SC16C654B/654DB is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 when the trigger level has been reached. Receive operation in mode ‘1’: When the SC16C654B/654DB is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached, or a Receive Time-Out has occurred, the RXRDY pin will go to a logic 0. Once activated, it will go to a logic 1 after there are no more characters in the FIFO. 2 FCR[2] XMIT FIFO reset. logic 0 = no FIFO transmit reset (normal default condition) logic 1 = clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. 1 FCR[1] RCVR FIFO reset. logic 0 = no FIFO receive reset (normal default condition) logic 1 = clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. 0 FCR[0] FIFO enable. logic 0 = disable the transmit and receive FIFO (normal default condition) logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’ when other FCR bits are written to, or they will not be programmed. Table 11: RX trigger levels FCR[7] FCR[6] RX FIFO trigger level 0 0 08 0 1 16 1 0 56 1 1 60 Table 12: TX trigger levels FCR[5] FCR[4] TX FIFO trigger level (# of characters) 0 0 08 0 1 16 1 0 32 1 1 56 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 28 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.4 Interrupt Status Register (ISR) The SC16C654B/654DB provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is cleared. However, it should be noted that only the current pending interrupt is cleared by the read. A lower level interrupt may be seen after re-reading the interrupt status bits. Table 13 “Interrupt source” shows the data values (bits 0:5) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels. Table 13: Interrupt source Priority level ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt 1 0 0 0 1 1 0 LSR (Receiver Line Status Register) 2 0 0 0 1 0 0 RXRDY (Receive Data Ready) 2 0 0 1 1 0 0 RXRDY (Receive Data time-out) 3 0 0 0 0 1 0 TXRDY (Transmitter Holding Register Empty) 4 0 0 0 0 0 0 MSR (Modem Status Register) 5 0 1 0 0 0 0 RXRDY (Received Xoff signal)/Special character 6 1 0 0 0 0 0 CTS, RTS change of state Table 14: Interrupt Status Register bits description Bit Symbol Description 7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFO is not being used. They are set to a logic 1 when the FIFOs are enabled. logic 0 or cleared = default condition 5:4 ISR[5:4] INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1. ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5] indicates that CTS, RTS have been generated. Note that once set to a logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received. logic 0 or cleared = default condition 3:1 ISR[3:1] INT priority bits 2:0. These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3; see Table 13. Logic 0 or cleared = default condition. 0 ISR[0] INT status. logic 0 = an interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine logic 1 = no interrupt pending (normal default condition) 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 29 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 15: Line Control Register bits description Bit Symbol Description 7 LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhance Feature mode enable. logic 0 = divisor latch disabled (normal default condition) logic 1 = divisor latch and enhanced feature register enabled 6 LCR[6] Set break. When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR[6] to a logic 0. logic 0 = no TX break condition (normal default condition) logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the remote receiver to a line break condition 5 LCR[5] Set parity. If the parity bit is enabled, LCR[5] selects the forced parity format. Programs the parity conditions; see Table 16. logic 0 = parity is not forced (normal default condition) LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1 for the transmit and receive data LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0 for the transmit and receive data 4 LCR[4] Even parity. If the parity bit is enabled with LCR[3] set to a logic 1, LCR[4] selects the even or odd parity format. logic 0 = odd parity is generated by forcing an odd number of logic 1s in the transmitted data. The receiver must be programmed to check the same format (normal default condition). logic 1 = even parity is generated by forcing an even number of logic 1s in the transmitted data. The receiver must be programmed to check the same format. 3 LCR[3] Parity enable. Parity or no parity can be selected via this bit. logic 0 = no parity (normal default condition) logic 1 = a parity bit is generated during the transmission, receiver checks the data and parity for transmission errors 2 LCR[2] Stop bits. The length of stop bit is specified by this bit in conjunction with the programmed word length; see Table 17. logic 0 or cleared = default condition 1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received; see Table 18. logic 0 or cleared = default condition 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 30 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 16: LCR[5] parity selection LCR[5] LCR[4] LCR[3] Parity selection X X 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 forced parity ‘1’ 1 1 1 forced parity ‘0’ Table 17: LCR[2] stop bit length LCR[2] Word length Stop bit length (bit times) 0 5, 6, 7, 8 1 1 5 11⁄2 1 6, 7, 8 2 Table 18: LCR[1:0] word length LCR[1] LCR[0] Word length 0 0 5 0 1 6 1 0 7 1 1 8 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 19: Modem Control Register bits description Bit Symbol Description 7 MCR[7] Clock select. logic 0 = divide-by-1. The input clock (crystal or external) is divided by 16 and then presented to the Programmable Baud Rate Generator (BGR) without further modification, that is, divide-by-1. (normal default condition). logic 1 = divide-by-4. The divide-by-1 clock described in MCR[7] = a logic 0, if further divided by four. Also see Section 6.9 “Programmable baud rate generator”. 6 MCR[6] IR enable. logic 0 = enable the standard modem receive and transmit input/output interface (normal default condition) logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/inputs are routed to the infrared encoder/decoder. The data input and output levels will conform to the IrDA infrared interface requirement. As such, while in this mode, the infrared TX output will be a logic 0 during idle data conditions. 5 MCR[5] Xon Any. logic 0 = disable Xon Any function (for 16C554 compatibility) (normal default condition) logic 1 = enable Xon Any function. In this mode, any RX character received will enable Xon 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 31 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 19: Modem Control Register bits description …continued Bit Symbol Description 4 MCR[4] Loop-back. Enable the local loop-back mode (diagnostics). In this mode the transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI are disconnected from the SC16C654B/654DB I/O pins. Internally the modem data and control pins are connected into a loop-back data configuration; see Figure 12. In this mode, the receiver and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts’ sources are switched to the lower four bits of the Modem Control. Interrupts continue to be controlled by the IER register. logic 0 = disable loop-back mode (normal default condition) logic 1 = enable local loop-back mode (diagnostics) 3 MCR[3] OP2, INTx enable. Used to control the modem CD signal in the loop-back mode. logic 0 = forces INTA-INTD outputs to the 3-state mode during the 16 mode (normal default condition). In the loop-back mode, sets OP2 (CD) internally to a logic 1. logic 1 = forces the INTA-INTD outputs to the active mode during the 16 mode. In the loop-back mode, sets OP2 (CD) internally to a logic 0. 2 MCR[2] OP1. This bit is used in the Loop-back mode only. In the loop-back mode, this bit is used to write the state of the modem RI interface signal via OP1. 1 MCR[1] RTS logic 0 = force RTS output to a logic 1 (normal default condition) logic 1 = force RTS output to a logic 0 Automatic RTS may be used for hardware flow control by enabling EFR[6]. See Table 22. 0 MCR[0] DTR logic 0 = force DTR output to a logic 1 (normal default condition) logic 1 = force DTR output to a logic 0 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 32 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C654B/654DB and the CPU. Table 20: Line Status Register bits description Bit Symbol Description 7 LSR[7] FIFO data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current FIFO data. This bit is cleared when LSR register is read. 6 LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. It is reset to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode, this bit is set to ‘1’ whenever the transmit FIFO and transmit shift register are both empty. 5 LSR[5] THR empty. This bit is the Transmit Holding Register Empty indicator. This bit indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to CPU when the THR interrupt enable is set. The THR bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. The bit is reset to a logic 0 concurrently with the loading of the transmitter holding register by the CPU. In the FIFO mode, this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO. 4 LSR[4] Break interrupt. logic 0 = no break condition (normal default condition) logic 1 = the receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. 3 LSR[3] Framing error. logic 0 = no framing error (normal default condition) logic 1 = framing error. The receive character did not have a valid stop bit(s). In the FIFO mode, this error is associated with the character at the top of the FIFO. 2 LSR[2] Parity error. logic 0 = no parity error (normal default condition) logic 1 = parity error. The receive character does not have correct parity information and is suspect. In the FIFO mode, this error is associated with the character at the top of the FIFO. 1 LSR[1] Overrun error. logic 0 = no overrun error (normal default condition) logic 1 = overrun error. A data overrun error occurred in the receive shift register. This happens when additional data arrives while the FIFO is full. In this case, the previous data in the shift register is overwritten. Note that under this condition, the data byte in the receive shift register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error. 0 LSR[0] Receive data ready. logic 0 = no data in receive holding register or FIFO (normal default condition) logic 1 = data has been received and is saved in the receive holding register or FIFO 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 33 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C654B/654DB is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register. Table 21: Modem Status Register bits description Bit Symbol Description 7 MSR[7] CD (active HIGH, logical 1). Normally this bit is the complement of the CD input. In the loop-back mode this bit is equivalent to the OP2 bit in the MCR register. 6 MSR[6] RI (active HIGH, logical 1). Normally this bit is the complement of the RI input. In the loop-back mode this bit is equivalent to the OP1 bit in the MCR register. 5 MSR[5] DSR (active HIGH, logical 1). Normally this bit is the complement of the DSR input. In loop-back mode this bit is equivalent to the DTR bit in the MCR register. 4 MSR[4] CTS. CTS functions as hardware flow control signal input if it is enabled via EFR[7]. The transmit holding register flow control is enabled/disabled by MSR[4]. Flow control (when enabled) allows starting and stopping the transmissions based on the external modem CTS signal. A logic 1 at the CTS pin will stop SC16C654B/654DB transmissions as soon as current character has finished transmission. Normally MSR[4] is the complement of the CTS input. However, in the loop-back mode, this bit is equivalent to the RTS bit in the MCR register. 3 MSR[3] ∆CD [1] logic 0 = no CD change (normal default condition) logic 1 = the CD input to the SC16C654B/654DB has changed state since the last time it was read. A modem Status Interrupt will be generated. 2 MSR[2] ∆RI [1] logic 0 = no RI change (normal default condition) logic 1 = the RI input to the SC16C654B/654DB has changed from a logic 0 to a logic 1. A modem Status Interrupt will be generated. 1 MSR[1] ∆DSR [1] logic 0 = no DSR change (normal default condition) logic 1 = the DSR input to the SC16C654B/654DB has changed state since the last time it was read. A Modem Status Interrupt will be generated. 0 MSR[0] ∆CTS [1] logic 0 = no CTS change (normal default condition) logic 1 = the CTS input to the SC16C654B/654DB has changed state since the last time it was read. A Modem Status Interrupt will be generated. [1] Whenever any MSR bit 0:3 is set to logic 1, a Modem Status Interrupt will be generated. 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 34 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.9 Scratchpad Register (SPR) The SC16C654B/654DB provides a temporary data register to store 8 bits of user information. 7.10 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential numbers. Table 22: Enhanced Feature Register bits description Bit Symbol Description 7 EFR[7] Auto CTS. Automatic CTS Flow Control. logic 0 = automatic CTS flow control is disabled (normal default condition) logic 1 = enable Automatic CTS flow control. Transmission will stop when CTS goes to a logical 1. Transmission will resume when the CTS pin returns to a logical 0. 6 EFR[6] Auto RTS. Automatic RTS may be used for hardware flow control by enabling EFR[6]. When Auto RTS is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS will go to a logic 1 at the next trigger level. RTS will return to a logic 0 when data is unloaded below the next lower trigger level. The state of this register bit changes with the status of the hardware flow control. RTS functions normally when hardware flow control is disabled. logic 0 = automatic RTS flow control is disabled (normal default condition) logic 1 = enable Automatic RTS flow control 5 EFR[5] Special Character Detect. logic 0 = special character detect disabled (normal default condition) logic 1 = special character detect enabled. The SC16C654B/654DB compares each incoming receive character with Xoff2 data. If a match exists, the received data will be transferred to FIFO and ISR[4] will be set to indicate detection of special character. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. When this feature is enabled, the normal software flow control must be disabled (EFR[3:0] must be set to a logic 0). 4 EFR[4] Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and MCR[7:5] can be modified and latched. After modifying any bits in the enhanced registers, EFR[4] can be set to a logic 0 to latch the new values. This feature prevents existing software from altering or overwriting the SC16C654B/654DB enhanced functions. logic 0 = disable (normal default condition) logic 1 = enable 3:0 EFR[3:0] Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition. Combinations of software flow control can be selected by programming these bits. See Table 23. 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 35 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Software flow control functions [1] Table 23: Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software flow controls 0 0 X X no transmit flow control 1 0 X X transmit Xon1/Xoff1 0 1 X X transmit Xon2/Xoff2 1 1 X X transmit Xon1 and Xon2/Xoff1 and Xoff2 X X 0 0 no receive flow control X X 1 0 receiver compares Xon1/Xoff1 X X 0 1 receiver compares Xon2/Xoff2 1 0 1 1 transmit Xon1/Xoff1 receiver compares Xon1 and Xon2, Xoff1 and Xoff2 0 1 1 1 transmit Xon2/Xoff2 receiver compares Xon1 and Xon2/Xoff1 and Xoff2 1 1 1 1 transmit Xon1 and Xon2/Xoff1 and Xoff2 receiver compares Xon1 and Xon2/Xoff1 and Xoff2 [1] When using software flow control the Xon/Xoff characters cannot be used for data transfer. 7.11 SC16C654B/654DB external reset conditions Table 24: Reset state for registers Register Reset state IER IER[7:0] = 0 ISR ISR[7:1] = 0; ISR[0] = 1 LCR LCR[7:0] = 0 MCR MCR[7:0] = 0 LSR LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0 MSR MSR[7:4] = input signals; MSR[3:0] = 0 FCR FCR[7:0] = 0 EFR EFR[7:0] = 0 Table 25: Reset state for outputs Output Reset state TXA, TXB, TXC, TXD HIGH RTSA, RTSB, RTSC, RTSD HIGH DTRA, DTRB, DTRC, DTRD HIGH RXRDY HIGH TXRDY LOW 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 36 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 8. Limiting values Table 26: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VCC supply voltage Max Unit - 7 V Vn voltage at any pin GND − 0.3 VCC + 0.3 V Tamb ambient temperature −40 +85 °C Tstg storage temperature −65 +150 °C Ptot(pack) total power dissipation per package - 500 mW 9397 750 14965 Product data sheet Min © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 37 of 58 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Parameter Conditions VCC = 2.5 V Min Typ VCC = 3.3 V Max Min Typ VCC = 5.0 V Max Min Typ Unit Max −0.3 - 0.45 −0.3 - 0.6 −0.5 - 0.6 V VIH(CK) HIGH-level clock input voltage 1.8 - VCC 2.4 - VCC 3.0 - VCC V VIL LOW-level input voltage (except XTAL1 clock) −0.3 - 0.65 −0.3 - 0.8 −0.5 - 0.8 V VIH HIGH-level input voltage (except XTAL1 clock) 1.6 - - 2.0 - - 2.2 - - V VOL LOW-level output voltage on all outputs [1] IOL = 5 mA (data bus) - - - - - - - - 0.4 V IOL = 4 mA (other outputs) - - - - - 0.4 - - - V IOL = 2 mA (data bus) - - 0.4 - - - - - - V IOL = 1.6 mA (other outputs) - - 0.4 - - - - - - V IOH = −5 mA (data bus) - - - - - - 2.4 - - V IOH = −1 mA (other outputs) - - - 2.0 - - - - - V IOH = −800 µA (data bus) 1.85 - - - - - - - - V IOH = −400 µA (other outputs) 1.85 - - - - - - - - V VOH HIGH-level output voltage 38 of 58 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ILIL LOW-level input leakage current - - ±10 - - ±10 - - ±10 µA ICL clock leakage - - ±30 - - ±30 - - ±30 µA ICC supply current - - 4.5 - - 6 - - 6 mA - 200 - - 200 - - 200 - µA - - 5 - - 5 - - 5 pF 500 - - 500 - - 500 - - kΩ f = 5 MHz current [2] ICCsleep sleep Ci input capacitance Rpu(int) internal pull-up resistance [3] [1] Except XTAL2, VOL = 1 V typical. [2] When using crystal oscillator. The use of an external clock will increase the sleep current. [3] Refer to Table 2 “Pin description” on page 10 for a listing of pins having internal pull-up resistors. SC16C654B/654DB LOW-level clock input voltage 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Rev. 02 — 20 June 2005 VIL(CK) Philips Semiconductors Symbol 9. Static characteristics 9397 750 14965 Product data sheet Table 27: Static characteristics Tamb = −40 °C to +85 °C; tolerance of VCC = ± 10 %, unless otherwise specified. SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 10. Dynamic characteristics Table 28: Dynamic characteristics Tamb = −40 °C to +85 °C; tolerance of VCC = ± 10 %, unless otherwise specified. Symbol Parameter Conditions VCC = 2.5 V Min t1w, t2w clock pulse duration fXTAL oscillator/clock frequency t6s VCC = 3.3 V Max Min VCC = 5.0 V Max Min Max 10 - 6 - - 48 - 80 address setup time 0 - 0 - t6h address hold time 0 - 0 - t7d IOR delay from chip select t7w IOR strobe width t7h chip select hold time from IOR t9d read cycle delay 25 pF load 20 - 20 - 20 - ns t12d delay from IOR to data 25 pF load - 77 - 26 - 23 ns t12h data disable time 25 pF load - 15 - 15 - 15 ns t13d IOW delay from chip select 10 - 10 - 10 - ns t13w IOW strobe width 20 - 20 - 15 - ns t13h chip select hold time from IOW 0 - 0 - 0 - ns t15d write cycle delay 25 - 25 - 20 - ns t16s data setup time 20 - 20 - 15 - ns t16h data hold time 15 - 5 - 5 - ns t17d delay from IOW to output 25 pF load - 100 - 33 - 29 ns t18d delay to set interrupt from Modem input 25 pF load - 100 - 24 - 23 ns t19d delay to reset interrupt from IOR 25 pF load - 100 - 24 - 23 ns t20d delay from stop to set interrupt - 1TRCLK - 1TRCLK - 1TRCLK ns t21d delay from IOR to reset interrupt t22d t23d [1] [2] 25 pF load - ns 80 MHz 0 - ns 0 - ns 10 - 10 - 10 - ns 77 - 26 - 23 - ns 0 - 0 - 0 - ns [3] 25 pF load 6 Unit [3] [3] - 100 - 29 - 28 ns delay from start to set interrupt - 100 - 45 - 40 ns delay from IOW to transmit start 8TRCLK 24TRCLK 8TRCLK 24TRCLK 8TRCLK 24TRCLK [3] [3] [3] [3] [3] [3] t24d delay from IOW to reset interrupt - 100 - 45 - 40 ns t25d delay from stop to set RXRDY - 1TRCLK - 1TRCLK - 1TRCLK ns t26d delay from IOR to reset RXRDY - 100 - 45 - 40 ns t27d delay from IOW to set TXRDY - 100 - 45 - 40 ns [3] 9397 750 14965 Product data sheet [3] ns [3] © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 39 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 28: Dynamic characteristics …continued Tamb = −40 °C to +85 °C; tolerance of VCC = ± 10 %, unless otherwise specified. Symbol Parameter Conditions VCC = 2.5 V Min t28d delay from start to reset TXRDY - Max 8TRCLK Min - [3] address setup time t30s VCC = 3.3 V [1] 25 pF load VCC = 5.0 V Max 8TRCLK Min - [3] Unit Max 8TRCLK ns [3] 10 - 10 - 10 - ns 90 - 26 - 23 - ns 15 - 15 - 15 - ns t30w chip select strobe width t30h address hold time t30d read cycle delay 25 pF load 20 - 20 - 20 - ns t31d delay from CS to data 25 pF load - 90 - 26 - 23 ns t31h data disable time 25 pF load - 15 - 15 - 15 ns t32s write strobe setup time 10 - 10 - 10 - ns t32h write strobe hold time 10 - 10 - 10 - ns t32d write cycle delay 25 - 25 - 20 - ns t33s data setup time 20 - 15 - 15 - ns t33h data hold time 15 - 5 - 5 - ns 40 - 40 - ns tRESET RESET pulse width 200 - N baud rate divisor 1 (216 − 1) 1 (216 − 1) 1 [1] Applies to external clock, crystal oscillator max 24 MHz. [2] Maximum frequency = ------- [3] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches. (216 − 1) 1 t 3w 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 40 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 10.1 Timing diagrams A0 to A4 t30s t30h t30w t30d CS t31h t32s R/W t31d D0 to D7 002aaa210 Fig 13. General read timing in 68 mode A0 to A4 t30s t30w t30h CS t32s t32h t32d R/W t33s t33h D0 to D7 002aaa211 Fig 14. General write timing in 68 mode 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 41 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs t6h valid address A0 to A2 t13h t6s active CS t13d t15d t13w IOW active t16s D0 to D7 t16h data 002aaa171 Fig 15. General write timing in 16 mode t6h valid address A0 to A2 t7h t6s active CS t7d t9d t7w IOR active t12h t12d D0 to D7 data 002aaa172 Fig 16. General read timing in 16 mode 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 42 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs active IOW t17d RTS DTR change of state change of state CD CTS DSR change of state t18d INT change of state t18d active active active t19d active IOR active active t18d change of state RI 002aaa352 Fig 17. Modem input/output timing t2w t1w EXTERNAL CLOCK 002aaa112 t3w 1 f XTAL = ------t 3w Fig 18. External clock timing 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 43 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs start bit RX parity bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 5 data bits 6 data bits t20d 7 data bits active INT t21d active IOR 16 baud rate clock 002aaa113 Fig 19. Receive timing start bit RX parity bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 t25d active data ready RXRDY t26d active IOR 002aab063 Fig 20. Receive ready timing in non-FIFO mode 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 44 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs start bit D0 RX parity bit data bits (0 to 7) D1 D2 D3 D4 D5 D6 stop bit D7 first byte that reaches the trigger level t25d active data ready RXRDY t26d active IOR 002aab064 Fig 21. Receive ready timing in FIFO mode start bit TX parity bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 5 data bits 6 data bits 7 data bits active transmitter ready INT t22d t24d t23d IOW active active 16 baud rate clock 002aaa116 Fig 22. Transmit timing 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 45 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs start bit D0 TX IOW parity bit data bits (0 to 7) D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 active t28d D0 to D7 byte #1 t27d TXRDY active transmitter ready transmitter not ready 002aab062 Fig 23. Transmit ready timing in non-FIFO mode start bit data bits (0 to 7) D0 TX parity bit D1 D2 D3 D4 D5 D6 stop bit D7 5 data bits 6 data bits 7 data bits IOW active t28d D0 to D7 byte #16 t27d TXRDY FIFO full 002aab061 Fig 24. Transmit ready timing in FIFO mode (DMA mode ‘1’) 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 46 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs UART frame start data bits 0 TX data 1 0 1 0 stop 0 1 1 0 1 IrDA TX data 1/ bit time 2 bit time 3/ bit time 16 002aaa212 Fig 25. Infrared transmit timing IrDA RX data bit time RX data 0 to 1 16× clock delay 0 1 0 1 start 0 0 data bits 1 1 0 1 stop UART frame 002aaa213 Fig 26. Infrared receive timing 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 47 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 11. Package outline PLCC68: plastic leaded chip carrier; 68 leads SOT188-2 eD eE y X 60 A 44 43 Z E 61 bp b1 w M 68 1 E HE pin 1 index A e A4 A1 (A 3) β 9 Lp 27 k detail X 10 26 e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 UNIT A D(1) E(1) e A3 eD eE HD bp b1 max. min. 4.57 4.19 mm inches 0.81 0.66 HE k 23.62 23.62 25.27 25.27 1.22 24.33 24.33 1.27 22.61 22.61 25.02 25.02 1.07 24.13 24.13 0.51 0.25 3.3 0.53 0.33 0.180 0.02 0.165 0.01 0.13 0.021 0.032 0.958 0.958 0.05 0.013 0.026 0.950 0.950 0.93 0.89 0.93 0.89 Lp v w y 1.44 1.02 0.18 0.18 0.1 ZD(1) ZE(1) max. max. 2.16 β 2.16 45 o 0.995 0.995 0.048 0.057 0.007 0.007 0.004 0.085 0.085 0.985 0.985 0.042 0.040 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT188-2 112E10 MS-018 EDR-7319 EUROPEAN PROJECTION ISSUE DATE 99-12-27 01-11-14 Fig 27. Package outline SOT188-2 (PLCC68) 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 48 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 wM θ bp pin 1 index 64 Lp L 17 detail X 16 1 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 10.1 9.9 0.5 HD HE 12.15 12.15 11.85 11.85 L Lp v w y 1 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 θ 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT314-2 136E10 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 28. Package outline SOT314-2 (LQFP64) 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 49 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs LQFP64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm SOT414-1 c y X 48 A 33 49 32 ZE e A A2 E HE (A 3) A1 wM θ bp pin 1 index Lp L 64 17 1 detail X 16 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.15 0.05 1.45 1.35 0.25 0.23 0.13 0.20 0.09 7.1 6.9 7.1 6.9 0.4 9.15 8.85 9.15 8.85 1 0.75 0.45 0.2 0.08 0.08 Z D (1) Z E (1) 0.64 0.36 0.64 0.36 θ o 7 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT414-1 136E06 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-20 Fig 29. Package outline SOT414-1 (LQFP64) 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 50 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 6 x 6 x 0.85 mm A B D SOT778-3 terminal 1 index area E A A1 c detail X C e1 e v w b 1/2 e 13 M M y1 C C A B C y 24 L 25 12 e e2 Eh 1/2 e 1 terminal 1 index area 36 48 37 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.25 0.15 0.2 6.1 5.9 3.95 3.65 6.1 5.9 3.95 3.65 0.4 4.4 4.4 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT778-3 --- --- --- EUROPEAN PROJECTION ISSUE DATE 04-06-16 04-06-23 Fig 30. Package outline SOT778-3 (HVQFN48) 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 51 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs LFBGA64: plastic low profile fine-pitch ball grid array package; 64 balls; body 6 x 6 x 1.05 mm D SOT686-1 A B ball A1 index area A A2 E A1 detail X e1 C e 1/2 e y y1 C ∅v M C A B b ∅w M C K J e H G F e2 E D 1/2 e C B A ball A1 index area 1 2 3 4 5 6 7 8 9 10 X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b D E e e1 e2 v w y y1 mm 1.5 0.3 0.2 1.20 0.95 0.35 0.25 6.1 5.9 6.1 5.9 0.5 4.5 4.5 0.15 0.05 0.08 0.1 OUTLINE VERSION SOT686-1 REFERENCES IEC JEDEC JEITA --- --- EUROPEAN PROJECTION ISSUE DATE 02-03-11 Fig 31. Package outline SOT686-1 (LFBGA64) 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 52 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 12. Soldering 12.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 12.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: • below 225 °C (SnPb process) or below 245 °C (Pb-free process) – for all BGA, HTSSON..T and SSOP..T packages – for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 12.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 53 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 12.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C. 12.5 Package related soldering information Table 29: Suitability of surface mount IC packages for wave and reflow soldering methods Package [1] Soldering method Wave Reflow [2] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable [4] suitable PLCC [5], SO, SOJ suitable suitable not recommended [5] [6] suitable SSOP, TSSOP, VSO, VSSOP not recommended [7] suitable CWQCCN..L [8], PMFP [9], WQCCN..L [8] not suitable LQFP, QFP, TQFP [1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. [3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 9397 750 14965 Product data sheet not suitable © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 54 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. [6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. [9] Hot bar soldering or manual soldering is suitable for PMFP packages. 13. Abbreviations Table 30: Abbreviations Acronym Description BRG Baud Rate Generator CPU Central Processing Unit DMA Direct Memory Access FIFO First-In, First-Out ISDN Integrated Service Digital Network LSB Least Significant Bit MSB Most Significant Bit QUART 4-channel (Quad) Universal Asynchronous Receiver and Transmitter UART Universal Asynchronous Receiver and Transmitter 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 55 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 14. Revision history Table 31: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes SC16C654B_654DB_2 20050620 Product data sheet - 9397 750 14965 SC16C654B_654DB_1 Modifications: • Section 1 “General description”: – 2nd paragraph: added 6th sentence. – 3rd paragraph: added HVQFN48 and LFBGA64 package options, and added second sentence. • Table 1 “Ordering information”: added HVQFN48, LFBGA64, and LQFP64 (SOT414-1) package options. • • Figure 5 “Pin configuration for LQFP64”: added SC16C654BIBM option • • Table 2 “Pin description”: added columns for HVQFN48 and LFBGA64 package types • • • Section 6.4 “Hardware flow control”: added ‘Remark’ following second paragraph. • Added Figure 6 “Pin configuration for HVQFN48 (16 mode)”, Figure 7 “Pin configuration for HVQFN48 (68 mode)”, Figure 8 “Pin configuration for LFBGA64” and Figure 9 “Ball mapping for LFBGA64”. moved Section 6.1.1 “The 16 mode interface” (was Section 6.2) and Section 6.1.2 “The 68 mode interface” (was Section 6.3) to be sub-sections of Section 6.1 “Interface options” Section 6.10 “DMA operation”: added ‘Remark’ following first paragraph. Table 8 “SC16C654B/654DB internal registers”: added (new) Table note 4 and its reference at FCR[3]. Table 27 “Static characteristics”: – descriptive line following title: changed ‘VCC = 2.5 V, 3.3 V or 5.0 V ± 10 %,’ to ‘tolerance of VCC ± 10 %;’ – added ‘VCC = ‘ to the limits’ column headings • Table 28 “Dynamic characteristics”: – descriptive line following title: changed ‘VCC = 2.5 V, 3.3 V or 5.0 V ± 10 %,’ to ‘tolerance of VCC ± 10 %;’ – added ‘VCC = ‘ to the limits’ column headings – baud rate divisor Max. columns: changed ‘216 − 1 TRCLK’ to ‘(216 − 1)’; deleted ‘ns’ from Unit column (N is a number). SC16C654B_654DB_1 • Section 11 “Package outline”: added Figure 29 “Package outline SOT414-1 (LQFP64)”, Figure 30 “Package outline SOT778-3 (HVQFN48)”, and Figure 31 “Package outline SOT686-1 (LFBGA64)”. • • Added Section 13 “Abbreviations” on page 55 Section 18 “Trademarks” re-written. 20050209 Product data sheet - 9397 750 14965 Product data sheet 9397 750 13115 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 56 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 15. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18. Trademarks 17. Disclaimers Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 19. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 20 June 2005 57 of 58 SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 20. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.1.1 6.1.2 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 7 7.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional description . . . . . . . . . . . . . . . . . . 14 Interface options . . . . . . . . . . . . . . . . . . . . . . . 16 The 16 mode interface . . . . . . . . . . . . . . . . . . 16 The 68 mode interface . . . . . . . . . . . . . . . . . . 16 Internal registers. . . . . . . . . . . . . . . . . . . . . . . 17 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 17 Hardware flow control . . . . . . . . . . . . . . . . . . . 18 Software flow control . . . . . . . . . . . . . . . . . . . 18 Special feature software flow control . . . . . . . 19 Xon any feature . . . . . . . . . . . . . . . . . . . . . . . 19 Hardware/software and time-out interrupts. . . 19 Programmable baud rate generator . . . . . . . . 20 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 22 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Loop-back mode . . . . . . . . . . . . . . . . . . . . . . . 22 Register descriptions . . . . . . . . . . . . . . . . . . . 24 Transmit (THR) and Receive (RHR) Holding Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 Interrupt Enable Register (IER) . . . . . . . . . . . 25 7.2.1 IER versus Receive FIFO interrupt mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2.2 IER versus Receive/Transmit FIFO polled mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3 FIFO Control Register (FCR) . . . . . . . . . . . . . 27 7.3.1 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3.1.1 Mode 0 (FCR bit 3 = 0) . . . . . . . . . . . . . . . . . . 27 7.3.1.2 Mode 1 (FCR bit 3 = 1) . . . . . . . . . . . . . . . . . . 27 7.3.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.4 Interrupt Status Register (ISR) . . . . . . . . . . . . 29 7.5 Line Control Register (LCR) . . . . . . . . . . . . . . 30 7.6 Modem Control Register (MCR) . . . . . . . . . . . 31 7.7 Line Status Register (LSR) . . . . . . . . . . . . . . . 33 7.8 Modem Status Register (MSR). . . . . . . . . . . . 34 7.9 Scratchpad Register (SPR) . . . . . . . . . . . . . . 35 7.10 Enhanced Feature Register (EFR) . . . . . . . . . 35 7.11 SC16C654B/654DB external reset conditions 36 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 37 9 Static characteristics. . . . . . . . . . . . . . . . . . . . 38 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 39 10.1 11 12 12.1 12.2 12.3 12.4 12.5 13 14 15 16 17 18 19 Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . 41 48 53 53 53 53 54 54 55 56 57 57 57 57 57 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 20 June 2005 Document number: 9397 750 14965 Published in The Netherlands