SC16C852LIB

SC16C852L 1.8 V dual UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface Rev. 03 — 18 January 2008 Product data sheet 1. General description The SC16C852L is a 1.8 V, low power, dual channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s. The SC16C852L is pin compatible with the SC16C652B. SC16C852L can be programmed to operate in extended mode (see Section 6.2) where additional advanced UART features are available. The SC16C852L UART provides enhanced UART functions with 128-byte FIFOs, modem control interface, DMA mode data transfer, and IrDA encoder/decoder. The DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDY and RXRDY signals. On-board status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by software to meet specific user requirements. An internal loopback capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC16C852L with Intel (16 mode) or Motorola (68 mode) bus host interface operates at 1.8 V and is available in plastic LQFP48, TFBGA36 and very small (Micro-UART) HVQFN32 packages. 2. Features I I I I I I I I I I I I I I I I Dual channel high performance UART Intel or Motorola bus interface selectable using 16/68 pin 1.8 V operation Up to 5 Mbit/s data rate 128-byte transmit FIFO to reduce the bandwidth requirement of the external CPU 128-byte receive FIFO with error flags to reduce the bandwidth requirement of the external CPU 128 programmable Receive and Transmit FIFO interrupt trigger levels 128 Receive and Transmit FIFO reporting levels (level counters) Automatic software (Xon/Xoff) and hardware (RTS/CTS or DTR/DSR) flow control Industrial temperature range (−40 °C to +85 °C) Pin, function, and software compatible to SC16C652B in LQFP48 package 128 hardware and software trigger levels Automatic 9-bit mode (RS-485) address detection Automatic RS-485 driver turn-around with programmable delay Dual channel concurrent write UART software reset NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder I High resolution clock prescaler, from 0 to 15 with granularity of 1⁄16 to allow non-standard UART clock to be used I Programmable Xon/Xoff characters I Software selectable baud rate generator I Support IrDA version 1.0 (up to 115.2 kbit/s) I Standard modem interface or infrared IrDA encoder/decoder interface I Enhanced Sleep mode and low power feature I Modem control functions (CTS, RTS, DSR, DTR, RI, CD) I Independent transmitter and receiver enable/disable I Pb-free, RoHS compliant packages offered 3. Ordering information Table 1. Ordering information Package Name SC16C852LIB LQFP48 Description plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm Version SOT313-2 SOT617-1 SOT912-1 Type number SC16C852LIBS HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 × 5 × 0.85 mm SC16C852LIET TFBGA36 plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 × 3.5 × 0.8 mm SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 2 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 4. Block diagram SC16C852L TRANSMIT FIFO REGISTER DATA BUS AND CONTROL LOGIC FLOW CONTROL LOGIC IR ENCODER TRANSMIT SHIFT REGISTER TXA, TXB D0 to D7 IOR IOW RESET INTERCONNECT BUS LINES AND CONTROL SIGNALS RECEIVE FIFO REGISTER RECEIVE SHIFT REGISTER RXA, RXB A0 to A2 CSA CSB REGISTER SELECT LOGIC FLOW CONTROL LOGIC IR DECODER LOWPWR POWERDOWN CONTROL DTRA, DTRB RTSA, RTSB OP2A, OP2B MODEM CONTROL LOGIC INTA, INTB TXRDYA, TXRDYB RXRDYA, RXRDYB INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR CTSA, CTSB RIA, RIB CDA, CDB DSRA, DSRB 002aac403 XTAL1 XTAL2 Fig 1. Block diagram of SC16C852L (16 mode) SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 3 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder SC16C852L TRANSMIT FIFO REGISTER D0 to D7 R/W RESET DATA BUS AND CONTROL LOGIC FLOW CONTROL LOGIC IR ENCODER TRANSMIT SHIFT REGISTER TXA, TXB INTERCONNECT BUS LINES AND CONTROL SIGNALS RECEIVE FIFO REGISTER RECEIVE SHIFT REGISTER RXA, RXB A0 to A3 CS REGISTER SELECT LOGIC FLOW CONTROL LOGIC IR DECODER LOWPWR POWERDOWN CONTROL DTRA, DTRB RTSA, RTSB OP2A, OP2B MODEM CONTROL LOGIC IRQ TXRDYA, TXRDYB RXRDYA, RXRDYB INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR CTSA, CTSB RIA, RIB CDA, CDB DSRA, DSRB 002aac182 XTAL1 XTAL2 Fig 2. Block diagram of SC16C852L (68 mode) SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 4 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 5. Pinning information 5.1 Pinning 25 CTSA 24 RESET 23 RTSA 22 INTA 21 INTB 20 A0 19 A1 18 A2 17 16 XTAL1 10 XTAL2 11 IOW 12 VSS 13 IOR 14 RTSB 15 CTSB 16 25 CTSA 24 RESET 23 RTSA 22 IRQ 21 n.c. 20 A0 19 A1 18 A2 17 68 XTAL1 10 XTAL2 11 R/W 12 VSS 13 VDD 14 RTSB 15 CTSB 16 9 002aac629 002aac179 32 D5 31 D4 30 D3 29 D2 28 D1 28 D1 D6 D7 RXB RXA TXA TXB CSA CSB 1 2 3 4 5 6 7 8 9 SC16C852LIBS (16 mode) LOWPWR Transparent top view a. 16 mode 26 VDD 32 D5 31 D4 30 D3 29 D2 D6 D7 RXB RXA TXA TXB CS A3 1 2 3 4 5 6 7 8 SC16C852LIBS (68 mode) LOWPWR Transparent top view b. 68 mode Fig 3. Pin configuration for HVQFN32 SC16C852L_3 27 D0 terminal 1 index area 27 D0 terminal 1 index area 26 VDD © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 5 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 43 TXRDYA 39 DSRA 38 CTSA 40 CDA 42 VDD 41 RIA D5 D6 D7 RXB RXA TXRDYB TXA TXB OP2B 1 2 3 4 5 6 7 8 9 37 n.c. 36 RESET 35 DTRB 34 DTRA 33 RTSA 32 OP2A 31 RXRDYA 30 INTA 29 INTB 28 A0 27 A1 26 A2 25 n.c. 16 24 37 n.c. 36 RESET 35 DTRB 34 DTRA 33 RTSA 32 OP2A 31 RXRDYA 30 IRQ 29 n.c. 28 A0 27 A1 26 A2 25 n.c. 68 24 002aac628 002aac178 46 D2 48 D4 47 D3 45 D1 CDB 16 SC16C852LIB (16 mode) CSA 10 CSB 11 LOWPWR 12 XTAL1 13 XTAL2 14 IOW 15 VSS 17 RXRDYB 18 IOR 19 DSRB 20 RIB 21 RIB 21 40 CDA RTSB 22 39 DSRA RTSB 22 CTSB 23 CTSB 23 38 CTSA a. 16 mode 43 TXRDYA RXRDYB 18 44 D0 42 VDD VDD 19 D5 D6 D7 RXB RXA TXRDYB TXA TXB OP2B 1 2 3 4 5 6 7 8 9 SC16C852LIB (68 mode) CS 10 A3 11 LOWPWR 12 XTAL1 13 XTAL2 14 RW 15 CDB 16 VSS 17 DSRB 20 b. 68 mode Fig 4. Pin configuration for LQFP48 SC16C852L_3 41 RIA 45 D1 48 D4 47 D3 46 D2 44 D0 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 6 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder ball A1 index area 1 A B C D E F SC16C852LIET 2 3 4 5 6 002aad386 Transparent top view Fig 5. Pin configuration for TFBGA36 1 A B C D E F D4 D5 D7 RXA TXB CSB 2 D2 D3 RXB TXA CSA XTAL1 3 D0 D1 D6 LOWPWR XTAL2 IOW 4 n.c. n.c. VDD VSS n.c. IOR 5 CTSA n.c. INTA A0 CTSB RTSB 6 RESET RTSA INTB A1 A2 16 002aad387 a. 16 mode 1 A B C D E F D4 D5 D7 RXA TXB A3 2 D2 D3 RXB TXA CS XTAL1 3 D0 D1 D6 LOWPWR XTAL2 R/W 4 n.c. n.c. VDD VSS n.c. VDD 5 CTSA n.c. IRQ A0 CTSB RTSB 6 RESET RTSA n.c. A1 A2 68 002aad388 b. 68 mode Fig 6. TFBGA36 ball mapping (transparent top view) SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 7 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 5.2 Pin description Table 2. Symbol A0 A1 A2 CDA CDB Pin description Pin LQFP48 28 27 26 40 16 HVQFN32 TFBGA36 20 19 18 D5 D6 E6 I I I I I Address 0 select bit. Internal register address selection. Address 1 select bit. Internal register address selection. Address 2 select bit. Internal register address selection. Carrier Detect (active LOW). These inputs are associated with individual UART channels A through B. A logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. When 16/68 pin is at logic 1 (or unconnected), this input is chip select for channel A. When 16/68 pin is at logic 0, this input becomes the chip select for both channels (Motorola mode). CSB/A3 11 8 F1 I When 16/68 pin is at logic 1 (or unconnected), this input is chip select for channel B. When 16/68 pin is at logic 0, this input becomes the address line A3 which is used for channel selection; a logic 0 selects channel A and a logic 1 selects channel B. CTSA CTSB 38 23 25 16 A5 E5 I I Clear to Send (active LOW). These inputs are associated with individual UART channels, A through B. A logic 0 on the CTSx pin indicates the modem or data set is ready to accept transmit data from the SC16C852L. Status can be tested by reading MSR[4]. Data Set Ready (active LOW). These inputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. Status can be tested by reading MSR[5]. Data Terminal Ready (active LOW). These outputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates that the SC16C852L is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Type Description CSA/CS 10 7 E2 I DSRA DSRB 39 20 - - I DTRA DTRB 34 35 - - O D0 D1 D2 D3 D4 D5 D6 D7 44 45 46 47 48 1 2 3 27 28 29 30 31 32 1 2 A3 B3 A2 B2 A1 B1 C3 C1 I/O I/O I/O I/O I/O I/O I/O I/O SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 8 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder Table 2. Symbol INTA/IRQ Pin description …continued Pin LQFP48 30 HVQFN32 TFBGA36 22 C5 O When 16/68 pin is at logic 1 or unconnected, this output becomes channel A interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTA is set to the active mode and OP2A output to a logic 0 when MCR[3] is set to a logic 1. INTA is set to the 3-state mode and OP2A is set to a logic 1 when MCR[3] is set to a logic 0. When 16/68 pin is at logic 0, this output becomes device interrupt output (active LOW, open-drain). An external pull-up resistor to VDD is required. Type Description INTB/n.c. 29 21 C6 O When 16/68 pin is at logic 1 or unconnected, this output becomes channel B interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTB is set to the active mode and OP2B output to a logic 0 when MCR[3] is set to a logic 1. INTB is set to the 3-state mode and OP2B is set to a logic 1 when MCR[3] is set to a logic 0. When 16/68 pin is at logic 0, this output is not used. When 16/68 pin is at logic 1, this input becomes the read strobe (active LOW). When 16/68 pin is at logic 0, this input pin is not used and should be connected to VDD. When 16/68 pin is at logic 1 or unconnected, this input becomes the write strobe (active LOW). When 16/68 pin is at logic 0, this input becomes read strobe when it is at logic HIGH, and write strobe when it is at logic LOW. IOR/VDD 19 14 F4 I IOW/R/W 15 12 F3 I OP2A OP2B 32 9 - - O O Output 2 (user-defined). This function is associated with individual channels, A through B. The state at these pin(s) are defined by the user and through MCR register bit 3. INTA, INTB are set to the active mode and OP2 to logic 0 when MCR[3] is set to a logic 1. INTA, INTB are set to the 3-state mode and OP2 to a logic 1 when MCR[3] is set to a logic 0 (see Table 21 “Modem Control Register bits description”, bit 3). Since these bits control both the INTA, INTB operation and OP2 outputs, only one function should be used at one time, INT or OP2. Master Reset. When 16/68 pin is at logic 1 or unconnected, this input becomes the RESET pin (active HIGH). When 16/68 pin is at logic LOW, this input pin becomes RESET (active LOW). (See Section 7.23 “SC16C852L external reset condition and software reset” for initialization details.) RESET/ RESET 36 24 A6 I RIA RIB 41 21 - - I I Ring Indicator (active LOW). These inputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt if modem status interrupt is enabled. Request to Send (active LOW). These outputs are associated with individual UART channels, A through B. A logic 0 on the RTSx pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this pin to a logic 0, indicating data is available. After a reset this pin will be set to a logic 1. RTSA RTSB 33 22 23 15 B6 F5 O O SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 9 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder Table 2. Symbol RXA RXB Pin description …continued Pin LQFP48 5 4 HVQFN32 TFBGA36 4 3 D1 C2 I I Receive data A, B. These inputs are associated with individual serial channel data to the SC16C852L receive input circuits, A through B. The RX signal will be a logic 1 during reset, idle (no data), or when not receiving data. During the local loopback mode, the RXA/RXB input pin is disabled and TX data is connected to the UART RX input, internally. Receive Ready A, B (active LOW). This function provides the RX FIFO/RHR status for individual receive channels (A to B). RXRDY is primarily intended for monitoring DMA mode 1 transfers for the receive data FIFOs. A logic 0 indicates there is a receive data to read/upload, that is, receive ready status with one or more RX characters available in the FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed trigger level has not been reached. This signal can also be used for single mode transfers (DMA mode 0). Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC16C852L. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loopback mode, the TXA/TXB output pin is disabled and TX data is internally connected to the UART RX input. Transmit Ready A, B (active LOW). These outputs provide the TX FIFO/THR status for individual transmit channels (A to B). TXRDY is primarily intended for monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual channel’s TXRDYA, TXRDYB buffer ready status is indicated by logic 0, that is, at lease one location is empty and available in the FIFO or THR. This pin goes to a logic 1 (DMA mode 1) when there are no more empty locations in the FIFO or THR. This signal can also be used for single mode transfers (DMA mode 0). Power supply input. Signal and power ground. Crystal or external clock input. Functions as a crystal input or as an external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit. Alternatively, an external clock can be connected to this pin to provide custom data rates (see Section 6.9 “Programmable baud rate generator”). See Figure 8. Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal oscillator output or buffered clock output. Should be left open if an external clock is connected to XTAL1. Type Description RXRDYA RXRDYB 31 18 - - O O TXA TXB 7 8 5 6 D2 E1 O O TXRDYA TXRDYB 43 6 - - O O VDD VSS XTAL1 42 17 13 26 13[1] 10 C4 D4 F2 I I I XTAL2 14 11 E3 O SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 10 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder Table 2. Symbol Pin description …continued Pin LQFP48 HVQFN32 TFBGA36 9 D3 I Low Power. When asserted (active HIGH), the device immediately goes into low power mode. The oscillator is shut-off and some host interface pins are isolated from the host’s bus to reduce power consumption. The device only returns to normal mode when the LOWPWR pin is de-asserted. On the negative edge of a de-asserting LOWPWR signal, the device is automatically reset and all registers return to their default reset states. This pin has an internal pull-down resistor, therefore, it can be left unconnected. Bus select. Intel or Motorola bus select. When 16/68 pin is at logic 1 or left unconnected (internally pulled-up) the device will operate in Intel bus type of interface. When 16/68 pin is at logic 0, the device will operate in Motorola bus type of interface. Type Description LOWPWR 12 16/68 24 17 F6 I n.c. 25, 37 - A4, B4, B5, E4 - not connected [1] HVQFN32 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region. 6. Functional description The SC16C852L provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex, especially when manufactured on a single integrated silicon chip. The SC16C852L represents such an integration with greatly enhanced features. The SC16C852L is fabricated with an advanced CMOS process. The SC16C852L is an upward solution to the SC16C652B that provides a dual UART capability with 128 bytes of transmit and receive FIFO memory, instead of 32 bytes for the SC16C652 and 16 bytes in the SC16C2550. The SC16C852L is designed to work with high speed modems and shared network environments that require fast data processing time. Increased performance is realized in the SC16C852L by the transmit and receive FIFOs. This allows the external processor to handle more networking tasks within a given time. In addition, the four selectable receive and transmit FIFO trigger interrupt levels are provided in SC16C652 mode, or 128 programmable levels are provided in the extended mode for maximum data throughput performance especially when operating in a multi-channel environment (see Section 6.2 “Extended mode (128-byte FIFO)”). The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU and increases performance. A low power pin (LOWPWR) is provided to further reduce power consumption by isolating the host bus interface. SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 11 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder The SC16C852L is capable of operation up to 5 Mbit/s with an external 80 MHz clock. With a crystal, the SC16C852L is capable of operation up to 1.5 Mbit/s. The rich feature set of the SC16C852L is available through internal registers. These features are: selectable and programmable receive and transmit FIFO trigger levels, selectable TX and RX baud rates, and modem interface controls, and are all standard features. Following a power-on reset, an external reset, or a software reset, the SC16C852L is software compatible with the previous generation, SC16C2550, SC16C652B, and ST16C2450. 6.1 UART A-B functions The UART provides the user with the capability to bidirectionally transfer information between an external CPU, the SC16C852L package, and an external serial device. A logic 0 (LOW) on chip select pins CSA and/or CSB allows the user to configure, send data, and/or receive data via UART channels A, B. Individual channel select functions are shown in Table 3 and Table 4. Table 3. Serial port selection (Intel interface) H = HIGH; L = LOW. Chip Select CSA = H, CSB = H CSA = L CSB = L Function none UART channel A UART channel B Table 4. Serial port selection (Motorola interface) H = HIGH; L = LOW. Chip Select CS = H CS = L, A3 = L CS = L, A3 = H Function none UART channel A UART channel B 6.2 Extended mode (128-byte FIFO) The device is in the extended mode when any of these four registers contains any value other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL. SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 12 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 6.3 Internal registers The SC16C852L provides two sets of internal registers (A and B) consisting of 25 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in Table 5. Table 5. A2 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 0 1 1 1 [1] [2] [3] [4] [5] [6] SC16C852L_3 Internal registers decoding A0 0 1 0 1 0 1 0 1 0 1 1 0 0 0 1 0 1 0 0 0 1 0 0 0 1 Read mode Receive Holding Register Interrupt Enable Register Interrupt Status Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratchpad Register (DLL/DLM)[2] LSB of Divisor Latch MSB of Divisor Latch n/a n/a Enhanced Feature Register Xon1 word Xon2 word Xoff1 word Xoff2 word Transmit FIFO Interrupt Level Receive FIFO Interrupt Level Flow Control Count High Flow Control Count Low Clock Prescaler RS-485 turn-around Timer LSB of Divisor Latch MSB of Divisor Latch (TXLVLCNT/RXLVLCNT)[3] Transmit FIFO Level Count Receive FIFO Level Count Enhanced Feature Register Xon1 word Xon2 word Xoff1 word Xoff2 word Transmit FIFO Interrupt Level Receive FIFO Interrupt Level Flow Control Count High Flow Control Count Low Clock Prescaler RS-485 turn-around Timer Write mode Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register Extra Feature Control Register (EFCR) n/a Scratchpad Register A1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 1 1 0 1 1 General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)[1] Baud rate register set Second special register set Enhanced feature register set (EFR, Xon1/Xon2, Xoff1/Xoff2)[4] First extra feature register set (TXINTLVL/RXINTLVL, FLWCNTH/FLWCNTL)[5] Second extra feature register set (CLKPRES, RS485TIME, AFCR2, AFCR1)[6] Additional Feature Control Register 2 Additional Feature Control Register 2 Additional Feature Control Register 1 Additional Feature Control Register 1 These registers are accessible only when LCR[7] is a logic 0. These registers are accessible only when LCR[7] is a logic 1. Second special registers are accessible only when EFCR[0] = 1. Enhanced feature registers are only accessible when LCR = 0xBF. First extra feature registers are only accessible when EFCR[2:1] = 01b. Second extra feature registers are only accessible when EFCR[2:1] = 10b. © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 13 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 6.4 FIFO operation 6.4.1 32-byte FIFO mode When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the ‘First extra feature register set’ are empty (0x00) the transmit and receive trigger levels are set by FCR[7:4]. In this mode the transmit and receive trigger levels are backward compatible to the SC16C652B (see Table 6), and the FIFO sizes are 32 entries. The transmit and receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]). It should be noted that the user can set the transmit trigger levels by writing to the FCR, but activation will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU (see Section 6.8). Please refer to Table 13 and Table 14 for the setting of FCR[7:4]. Table 6. FCR[7:6] 00 01 10 11 Interrupt trigger level and flow control mechanism FCR[5:4] 00 01 10 11 INTA/INTB pin activation RX 8 16 24 28 TX 16 8 24 30 Negate RTS or send Xoff 8 16 24 28 Assert RTS or send Xon 0 7 15 23 6.4.2 128-byte FIFO mode When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘first extra feature register set’ contains any value other than 0x00, the transmit and receive trigger levels are set by TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the transmit FIFO, and the transmit trigger levels can be set to any value between 1 and 128 with granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive trigger levels can be set to any value between 1 and 128 with granularity of 1. When the effective FIFO size changes (that is, when FCR[0] toggles or when the combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will be lost). 6.5 Hardware flow control When automatic hardware flow control is enabled, the SC16C852L monitors the CTSA/CTSB pin for a remote buffer overflow indication and controls the RTSA/RTSB pin for local buffer overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C852L will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTSx input returns to a logic 0, indicating more data may be sent. When AFCR1[2] is set to logic 1 then the function of CTSA/CTSB pin is mapped to the DSRA/DSRB pin, and the function of RTSA/RTSB is mapped to DTRA/DTRB pin. DSRx and DTRx pins will behave as described above for CTS and RTS. SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 14 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder With the automatic hardware flow control function enabled, an interrupt is generated when the receive FIFO reaches the programmed trigger level. The RTSx (or DTRx) pin will not be forced to a logic 1 (RTS off), until the receive FIFO reaches the next trigger level. However, the RTSx (or DTRx) pin will return to a logic 0 after the receive buffer (FIFO) is unloaded to the next trigger level below the programmed trigger level. Under the above described conditions, the SC16C852L will continue to accept data until the receive FIFO is full. When the TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL in the ‘first extra feature register set’ are all zeroes, the hardware and software flow control trigger levels are set by FCR[7:4]; see Table 6. When the TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘first extra feature register set’ contain any value other than 0x00, the hardware and software flow control trigger levels are set by FLWCNTH and FLWCNTL. The content in FLWCNTH determines how many bytes are in the receive FIFO before RTS (or DTR) is de-asserted or Xoff is sent. The content in FLWCNTL determines how many bytes are in the receive FIFO before RTS (or DTR) is asserted, or Xon is sent. In 128-byte FIFO mode, hardware and software flow control trigger levels can be set to any value between 1 and 128 in granularity of 1. The value of FLWCNTH should always be greater than FLWCNTL. The UART does not check for this condition automatically, and if this condition is not met, spurious operation of the device might occur. When using FLWCNTH and FLWCNTL, these registers must be initialized to proper values before hardware or software flow control is enabled via the EFR register. 6.6 Software flow control When software flow control is enabled, the SC16C852L compares one or two sequentially received data characters with the programmed Xon or Xoff character value(s). If the received character(s) match the programmed Xoff values, the SC16C852L will halt transmission (TX) as soon as the current character(s) has completed transmission. When a match occurs, ISR bit 4 will be set (if enabled via IER[5]) and the interrupt output pin (if receive interrupt is enabled) will be activated. Following a suspension due to a match of the Xoff characters’ values, the SC16C852L will monitor the receive data stream for a match to the Xon1/Xon2 character value(s). If a match is found, the SC16C852L will resume operation and clear the flags (ISR[4]). Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset, the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff characters and suspend/resume transmissions (see Table 26). When double 8-bit Xon/Xoff characters are selected, the SC16C852L compares two consecutive receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control mechanisms, flow control characters are not placed (stacked) in the receive FIFO. When using software flow control, the Xon/Xoff characters cannot be used for data transfer. In the event that the receive buffer is overfilling, the SC16C852L automatically sends an Xoff character (when enabled) via the serial TX output to the remote UART. The SC16C852L sends the Xoff1/Xoff2 characters as soon as the number of received data in SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 15 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder the receive FIFO passes the programmed trigger level. To clear this condition, the SC16C852L will transmit the programmed Xon1/Xon2 characters as soon as the number of characters in the receive FIFO drops below the programmed trigger level. 6.7 Special character detect A special character detect feature is provided to detect an 8-bit character when EFR[5] is set. When an 8-bit character is detected, it will be placed on the user-accessible data stack along with normal incoming RX data. This condition is selected in conjunction with EFR[3:0] (see Table 26). Note that software flow control should be turned off when using this special mode by setting EFR[3:0] to all zeroes. The SC16C852L compares each incoming receive character with Xoff2 data. If a match occurs, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate detection of a special character. Although Table 10 “SC16C852L internal registers” shows Xon1, Xon2, Xoff1, Xoff2 with eight bits of character information, the actual number of bits is dependent on the programmed word length. Line Control Register bits LCR[1:0] define the number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length selected by LCR[1:0] also determines the number of bits that will be used for the special character comparison. Bit 0 in Xon1, Xon2, Xoff1, Xoff2 corresponds with the LSB bit for the received character. 6.8 Interrupt priority and time-out interrupts The interrupts are enabled by IER[7:0]. Care must be taken when handling these interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C852L will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to continuing operations. The ISR indicates the current singular highest priority interrupt only. A condition can exist where a higher priority interrupt masks the lower priority interrupt(s) (see Table 15). Only after servicing the higher pending interrupt will the lower priority interrupt(s) be reflected in the status register. Servicing the interrupt without investigating further interrupt conditions can result in data errors. Receive Data Ready and Receive Time-Out have the same interrupt priority (when enabled by IER[0]), and it is important to serve these interrupts correctly. The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case, the SC16C852L FIFO may hold more characters than the programmed trigger level. Following the removal of a data byte, the user should re-check LSR[0] to see if there are any additional characters. A Receive Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the center of each stop bit received or each time the Receive Holding Register (RHR) is read. The actual time-out value is 4 character time, including data information length, start bit, parity bit, and the size of stop bit, that is, 1×, 1.5×, or 2× bit times. SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 16 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 6.9 Programmable baud rate generator The SC16C852L UART contains a programmable rational baud rate generator that takes any clock input and divides it by a divisor in the range between 1 and (216 − 1). The SC16C852L offers the capability of dividing the input frequency by rational divisor. The fractional part of the divisor is controlled by the CLKPRES register in the ‘first extra feature register set’. f XTAL1 baud rate = ------------------------------------------------------------------M  N + ----- MCR [ 7 ] × 16 ×  16 where: N is the integer part of the divisor in DLL and DLM registers; M is the fractional part of the divisor in CLKPRES register; fXTAL1 is the clock frequency at XTAL1 pin. Prescaler = 1 when MCR[7] is set to 0. Prescaler = 4 when MCR[7] is set to 1. (1) CLKPRES [3:0] DIVIDE-BY-1 XTAL1 XTAL2 OSCILLATOR DIVIDE-BY-4 MCR[7] = 1 002aac645 MCR[7] = 0 BAUD RATE GENERATOR (DLL, DLM) transmitter and receiver clock Fig 7. Prescalers and baud rate generator block diagram A single baud rate generator is provided for the transmitter and receiver. The programmable Baud Rate Generator is capable of operating with a frequency of up to 80 MHz. To obtain maximum data rate, it is necessary to use full rail swing on the clock input. The SC16C852L can be configured for internal or external clock operation. For internal clock operation, an industry standard crystal is connected externally between the XTAL1 and XTAL2 pins (see Figure 8). Alternatively, an external clock can be connected to the XTAL1 pin (see Figure 9) to clock the internal baud rate generator for standard or custom rates (see Table 7). The generator divides the input 16× clock by any divisor from 1 to (216 − 1). The SC16C852L divides the basic external clock by 16. The baud rate is configured via the CLKPRES, DLL and DLM internal register functions. Customized baud rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of the baud rate generator. Programming the baud rate generator registers CLKPRES, DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 7 shows the selectable baud rate table available when using a 1.8432 MHz external clock input when MCR[7] = 0, and CLKPRES = 0x00. SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 17 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder XTAL1 XTAL2 XTAL1 XTAL2 1.5 kΩ X1 1.8432 MHz X1 1.8432 MHz C1 22 pF C2 33 pF C1 22 pF C2 47 pF 002aaa870 Fig 8. Crystal oscillator connection XTAL1 fXTAL1 100 pF XTAL2 002aac630 If fXTAL1 frequency is greater than 50 MHz, then a DC blocking capacitor is required. XTAL2 pin should be left unconnected when an external clock is used. Fig 9. External clock connection Table 7. Output baud rate (bit/s) 50 75 110 150 300 600 1.2 k 2.4 k 3.6 k 4.8 k 7.2 k 9.6 k 19.2 k 38.4 k 57.6 k 115.2 k Baud rate generator programming table using a 1.8432 MHz clock when MCR[7] = 0 and CLKPRES[3:0] = 0 Output 16× clock divisor (decimal) 2304 1536 1047 768 384 192 96 48 32 24 16 12 6 3 2 1 Output 16× clock divisor (hexadecimal) 900 600 417 300 180 C0 60 30 20 18 10 0C 06 03 02 01 DLM program value (hexadecimal) 09 06 04 03 01 00 00 00 00 00 00 00 00 00 00 00 DLL program value (hexadecimal) 00 00 17 00 80 C0 60 30 20 18 10 0C 06 03 02 01 SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 18 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 6.10 DMA operation The SC16C852L FIFO trigger level provides additional flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDYA/RXRDYB and TXRDYA/TXRDYB output pins. Table 8 and Table 9 show this. Table 8. Effect of DMA mode on state of RXRDYA/RXRDYB pin DMA mode 0-to-1 transition when FIFO empties 1-to-0 transition when FIFO reaches trigger level, or time-out occurs[1] Non-DMA mode 1 = FIFO empty 0 = at least 1 byte in FIFO [1] Receive FIFO becomes full at 32 bytes when in normal mode. When TXINTLVL or RXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00 (extended mode), then the receive FIFO becomes full at 128 bytes. Table 9. Effect of DMA mode on state of TXRDYA/TXRDYB pin DMA mode 0-to-1 transition when FIFO becomes full[1] 1-to-0 transition when FIFO has at least one empty location Non-DMA mode 1 = at least 1 byte in FIFO 0 = FIFO empty [1] Transmit FIFO becomes full at 32 bytes when in normal mode. When TXINTLVL or RXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00 (extended mode), then the transmit FIFO becomes full at 128 bytes. 6.11 Loopback mode The internal loopback capability allows on-board diagnostics. In the Loopback mode, the normal modem interface pins are disconnected and reconfigured for loopback internally (see Figure 10). MCR[3:0] register bits are used for controlling loopback diagnostic testing. In the Loopback mode, the transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally. The CTS, DSR, CD, and RI are disconnected from their normal modem control input pins, and instead are connected internally to RTS, DTR, MCR[3] (OP2A/OP2B) and MCR[2] (OP1A/OP1B). Loopback test data is entered into the transmit holding register via the user data bus interface, D[7:0]. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loopback connection. The receive UART converts the serial data back into parallel data that is then made available at the user data interface D[7:0]. The user optionally compares the received data to the initial transmitted data for verifying error-free operation of the UART TX/RX circuits. In this mode, the interrupt pin is 3-stated, therefore, the software must use the polling method (see Section 7.2.2) to send and receive data. SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 19 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder SC16C852L TRANSMIT FIFO REGISTERS D0 to D7 IOR IOW RESET DATA BUS AND CONTROL LOGIC FLOW CONTROL LOGIC IR ENCODER TRANSMIT SHIFT REGISTER TXA, TXB INTERCONNECT BUS LINES AND CONTROL SIGNALS RECEIVE FIFO REGISTERS RECEIVE SHIFT REGISTER MCR[4] = 1 RXA, RXB A0 to A2 CSA CSB REGISTER SELECT LOGIC FLOW CONTROL LOGIC IR DECODER RTSA, RTSB LOWPWR POWERDOWN CONTROL MODEM CONTROL LOGIC CTSA, CTSB DTRA, DTRB DSRA, DSRB (OP1A, OP1B) INTA, INTB TXRDYA, TXRDYB RXRDYA, RXRDYB INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR RIA, RIB (OP2A, OP2B) CDA, CDB 002aac404 XTAL1 XTAL2 Fig 10. Internal Loopback mode diagram SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 20 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 6.12 Sleep mode Sleep mode is an enhanced feature of the SC16C852L UART. It is enabled when EFR[4], the enhanced functions bit, is set and when IER[4] of both channels are set. 6.12.1 Conditions to enter Sleep mode Sleep mode is entered when: • Modem input pins are not toggling. • The serial data input line, RXA or RXB, is idle for 4 character time (logic HIGH) and AFCR1[4] is logic 0. When AFCR1[4] is logic 1 the device will go to sleep regardless of the state of the RXA/RXB pin (see Section 7.21 for the description of AFCR1 bit 4). • The TX FIFO and TX shift register are empty. • There are no interrupts pending. • The RX FIFO is empty. In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are clocked using these clocks, the power consumption is greatly reduced. Remark: Writing to the divisor latches, DLL and DLM, to set the baud clock, must not be done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4] before writing to DLL or DLM. 6.12.2 Conditions to resume normal operation SC16C852L resumes normal operation by any of the following: • Receives a start bit on RXA/RXB pin. • Data is loaded into transmit FIFO. • A change of state on any of the modem input pins If the device is awakened by one of the conditions described above, it will return to the Sleep mode automatically after all the conditions described in Section 6.12.1 are met. The device will stay in Sleep mode until it is disabled by setting any channel’s IER bit 4 to a logic 0. When the SC16C852L is in Sleep mode and the host data bus (D[7:0], A[2:0], IOW, IOR, CSA, CSB) remains in steady state, either HIGH or LOW, the Sleep mode supply current will be in the µA range as specified in Table 38 “Static characteristics”. If any of these signals is toggling or floating then the sleep current will be higher. 6.13 Low power feature A Low power feature is provided by the SC16C852L to prevent the switching of the host data bus from influencing the sleep current. When the pin LOWPWR is activated (logic HIGH), the device immediately and unconditionally goes into Low power mode. All clocks are stopped and most host interface pins are isolated to reduce power consumption. The device only returns to normal mode when the LOWPWR pin is de-asserted. The pin can be left unconnected because it has an internal pull-down resistor. SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 21 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 6.14 RS-485 features 6.14.1 Auto RS-485 RTS control Normally the RTSA/RTSB pin is controlled by MCR bit 1, or if hardware flow control is enabled, the logic state of the RTSx pin is controlled by the hardware flow control circuitry. AFCR2 register bit 4 will take the precedence over the other two modes; once this bit is set, the transmitter will control the state of the RTSx pin. The transmitter automatically asserts the RTSx pin (logic 0) once the host writes data to the transmit FIFO, and de-asserts RTSx pin (logic 1) once the last bit of the data has been transmitted. To use the auto RS-485 RTS mode the software would have to disable the hardware flow control function. 6.14.2 RS-485 RTS inversion AFCR2[5] reverses the polarity of the RTSx pin if the UART is in auto RS-485 RTS mode. When the transmitter has data to be sent it will de-asserts the RTSx pin (logic 1), and when the last bit of the data has been sent out the transmitter asserts the RTSx pin (logic 0). 6.14.3 Auto 9-bit mode (RS-485) AFCR2[0] is used to enable the 9-bit mode (Multi-drop or RS-485 mode). In this mode of operation, a ‘master’ station transmits an address character followed by data characters for the addressed ‘slave’ stations. The slave stations examine the received data and interrupt the controller if the received character is an address character (parity bit = 1). To use the automatic 9-bit mode, the software would have to disable the hardware and software flow control functions. 6.14.3.1 Normal Multi-drop mode The 9-bit Mode in AFCR2[0] is enabled, but not Special Character Detect (EFR[5]). The receiver is set to Force Parity 0 (LCR[5:3] = 111) in order to detect address bytes. With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an address byte is received (parity bit = 1). This address byte will cause the UART to set the parity error. The UART will generate a line status interrupt (IER bit 2 must be set to ‘1’ at this time), and at the same time puts this address byte in the RX FIFO. After the controller examines the byte it must make a decision whether or not to enable the receiver; it should enable the receiver if the address byte addresses its ID address, and must not enable the receiver if the address byte does not address its ID address. If the controller enables the receiver, the receiver will receive the subsequent data until being disabled by the controller after the controller has received a complete message from the ‘master’ station. If the controller does not disable the receiver after receiving a message from the ‘master’ station, the receiver will generate a parity error upon receiving another address byte. The controller then determines if the address byte addresses its ID address, if it is not, the controller then can disable the receiver. If the address byte addresses the ‘slave’ ID address, the controller takes no further action, and the receiver will receive the subsequent data. SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 22 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 6.14.3.2 Auto address detection If Special Character Detect is enabled (EFR[5] is set and the Xoff2 register contains the address byte) the receiver will try to detect an address byte that matches the programmed character in the Xoff2 register. If the received byte is a data byte or an address byte that does not match the programmed character in the Xoff2 register, the receiver will discard these data. Upon receiving an address byte that matches the Xoff2 character, the receiver will be automatically enabled if not already enabled, and the address character is pushed into the RX FIFO along with the parity bit (in place of the parity error bit). The receiver also generates a line status interrupt (IER[2] must be set to ‘1’ at this time). The receiver will then receive the subsequent data from the ‘master’ station until being disabled by the controller after having received a message from the ‘master’ station. If another address byte is received and this address byte does not match the Xoff2 character, the receiver will be automatically disabled and the address byte is ignored. If the address byte matches the Xoff2 character, the receiver will put this byte in the RX FIFO along with the parity bit in the parity error bit (LSR bit 2). 7. Register descriptions Table 10 details the assigned bit functions for the SC16C852L internal registers. The assigned bit functions are more fully defined in Section 7.1 through Section 7.23. SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 23 of 63 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 03 — 18 January 2008 © NXP B.V. 2008. All rights reserved. SC16C852L_3 NXP Semiconductors Table 10. SC16C852L internal registers Default[1] XX XX 00 Bit 7 bit 7 bit 7 CTS interrupt[3] Bit 6 bit 6 bit 6 RTS interrupt[3] Bit 5 bit 5 bit 5 Xoff interrupt[3] Bit 4 bit 4 bit 4 Sleep mode[3] Bit 3 bit 3 bit 3 modem status interrupt DMA mode select INT priority bit 2 parity enable OP2/INT enable framing error reserved Bit 2 bit 2 bit 2 receive line status interrupt XMIT FIFO reset INT priority bit 1 stop bits (OP1) parity error Bit 1 bit 1 bit 1 transmit holding register interrupt Bit 0 bit 0 bit 0 receive holding register interrupt R/W R W R/W set[2] A2 A1 A0 Register General register 0 0 0 0 0 0 0 0 1 RHR THR IER 0 1 0 FCR 00 RCVR trigger (MSB) FIFOs enabled divisor latch enable clock select[3] FIFO data error reserved RCVR trigger (LSB) FIFOs enabled set break TX trigger (MSB)[3] INT priority bit 4 set parity TX trigger (LSB)[3] INT priority bit 3 even parity loopback break interrupt reserved RCVR FIFO FIFOs reset enable INT priority bit 0 word length bit 1 RTS overrun error INT status word length bit 0 DTR W 0 0 1 1 1 1 1 0 0 0 0 1 0 1 1 ISR LCR MCR LSR EFCR 01 00 00 60 00 R R/W R/W 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder IRDA enable reserved THR and TSR empty reserved THR empty reserved receive data R ready W Enable extra Enable extra Enable feature bit 1 feature bit 0 TXLVLCNT/ RXLVLCNT ∆RI bit 2 bit 2 bit 10 bit 2 bit 2 ∆DSR bit 1 bit 1 bit 9 bit 1 bit 1 ∆CTS bit 0 bit 0 bit 8 bit 0 bit 0 1 1 0 0 0 1 1 1 0 0 1 0 0 1 0 1 1 0 MSR SPR set[4] DLL DLM TXLVLCNT RXLVLCNT X0 FF XX XX set[6] 00 00 CD bit 7 bit 7 bit 15 bit 7 bit 7 RI bit 6 bit 6 bit 14 bit 6 bit 6 DSR bit 5 bit 5 bit 13 bit 5 bit 5 CTS bit 4 bit 4 bit 12 bit 4 bit 4 ∆CD bit 3 bit 3 bit 11 bit 3 bit 3 R R/W R/W R/W R R Special register Second special register SC16C852L 24 of 63 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 10. SC16C852L internal registers …continued Default[1] set[5] 00 Auto CTS Auto RTS special character select Enable IER[7:4], ISR[5:4], FCR[5:4], MCR[7:5] bit 4 bit 12 bit 4 bit 12 bit 4 bit 4 bit 4 bit 4 reserved bit 4 Cont-3 TX, RX Control Cont-2 TX, RX Control Cont-1 TX, RX Control Cont-0 TX, RX Control R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W Product data sheet Rev. 03 — 18 January 2008 © NXP B.V. 2008. All rights reserved. SC16C852L_3 NXP Semiconductors A2 A1 A0 Register Enhanced feature register 0 1 0 EFR 1 1 1 1 0 1 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 1 Xon1 Xon2 Xoff1 Xoff2 TXINTLVL RXINTLVL FLWCNTH FLWCNTL CLKPRES 00 00 00 00 set[7] 0x00 0x00 0x00 0x00 bit 7 bit 15 bit 7 bit 15 bit 7 bit 7 bit 7 bit 7 reserved bit 7 reserved Concurrent Write bit 6 bit 14 bit 6 bit 14 bit 6 bit 6 bit 6 bit 6 reserved bit 6 reserved reserved bit 5 bit 13 bit 5 bit 13 bit 5 bit 5 bit 5 bit 5 reserved bit 5 bit 3 bit 11 bit 3 bit 11 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 2 bit 10 bit 2 bit 10 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 Transmitter Disable RTS/CTS mapped to DTR/DSR bit 1 bit 9 bit 1 bit 9 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 Receiver Disable Software Reset bit 0 bit 8 bit 0 bit 8 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W First extra feature register 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder Second extra feature register set[8] RS485TIME 0x00 AFCR2 AFCR1 0x00 0x00 RS485 RTS Auto RS485 RS485 Invert RTS RTS/DTR reserved Sleep RXLow reserved 9-bit Enable R/W TSR Interrupt R/W [1] [2] [3] [4] [5] [6] [7] [8] The value shown represents the register’s initialized hexadecimal value; X = not applicable. Accessible only when LCR[7] is logic 0, and EFCR[2:1] are logic 0. This bit is only accessible when EFR[4] is set. Baud rate registers accessible only when LCR[7] is logic 1. Enhanced feature register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to 0xBF, and EFCR[2:1] are logic 0. Second special registers are accessible only when EFCR[0] = 1, and EFCR[2:1] are logic 0. First extra feature register set is only accessible when EFCR[2:1] = 01b. Second extra feature register set is only accessible when EFCR[2:1] = 10b. SC16C852L 25 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the transmit FIFO. The THR empty flag in the LSR will be set to a logic 1 when the transmit FIFO is empty or when data is transferred to the TSR. The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a Receive Serial Shift Register (RSR). Receive data is removed from the SC16C852L receive FIFO by reading the RHR. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16× clock rate. After 71⁄2 clocks, the start bit time should be shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. Receiver status codes will be posted in the LSR. 7.2 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the INTA, INTB output pins. Table 11. Bit 7 Interrupt Enable Register bits description CTS interrupt. logic 0 = disable the CTS interrupt (normal default condition) logic 1 = enable the CTS interrupt. The SC16C852L issues an interrupt when the CTSA/CTSB pin transitions from a logic 0 to a logic 1. 6 IER[6] RTS interrupt. logic 0 = disable the RTS interrupt (normal default condition) logic 1 = enable the RTS interrupt. The SC16C852L issues an interrupt when the RTSA/RTSB pin transitions from a logic 0 to a logic 1. 5 IER[5] Xoff interrupt. logic 0 = disable the software flow control, receive Xoff interrupt (normal default condition) logic 1 = enable the receive Xoff interrupt 4 IER[4] Sleep mode. logic 0 = disable Sleep mode (normal default condition) logic 1 = enable Sleep mode 3 IER[3] Modem Status Interrupt. This interrupt will be issued whenever there is a modem status change as reflected in MSR[3:0]. logic 0 = disable the modem status register interrupt (normal default condition) logic 1 = enable the modem status register interrupt 2 IER[2] Receive Line Status interrupt. This interrupt will be issued whenever a receive data error condition exists as reflected in LSR[4:1]. logic 0 = disable the receiver line status interrupt (normal default condition) logic 1 = enable the receiver line status interrupt Symbol Description IER[7] SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 26 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder Interrupt Enable Register bits description …continued Transmit Holding Register interrupt. In the non-FIFO mode, this interrupt will be issued whenever the THR is empty, and is associated with LSR[5]. In the FIFO modes, this interrupt will be issued whenever the FIFO is empty. logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt (normal default condition) logic 1 = enable the TXRDY (ISR level 3) interrupt Table 11. Bit 1 Symbol Description IER[1] 0 IER[0] Receive Holding Register interrupt. In the non-FIFO mode, this interrupt will be issued when the RHR has data, or is cleared when the RHR is empty. In the FIFO mode, this interrupt will be issued when the FIFO has reached the programmed trigger level or is cleared when the FIFO drops below the trigger level. logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal default condition) logic 1 = enable the RXRDY (ISR level 2) interrupt 7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation When the receive FIFO is enabled (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU when the receive FIFO has reached the programmed trigger level. It will be cleared when the receive FIFO drops below the programmed trigger level. • Receive FIFO status will also be reflected in the user accessible ISR register when the receive FIFO trigger level is reached. Both the ISR register receive status bit and the interrupt will be cleared when the FIFO drops below the trigger level. • The receive data ready bit (LSR[0]) is set as soon as a character is transferred from the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty. • When the Transmit FIFO and interrupts are enabled, an interrupt is generated when the transmit FIFO is empty due to the unloading of the data by the TSR and UART for transmission via the transmission media. The interrupt is cleared either by reading the ISR, or by loading the THR with new data characters. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, setting IER[3:0] puts the SC16C852L in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). • • • • • LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO. LSR[4:1] will provide the type of receive errors, or a receive break, if encountered. LSR[5] will indicate when the transmit FIFO is empty. LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty. LSR[7] will show if any FIFO data errors occurred. SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 27 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode. 7.3.1 DMA mode 7.3.1.1 Mode 0 (FCR bit 3 = 0) In this mode, Transmit Ready (TXRDY) will go to a logic 0 whenever the FIFO (THR, if FIFO is not enabled) is empty. Receive Ready (RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with a character. 7.3.1.2 Mode 1 (FCR bit 3 = 1) In this mode, the Transmit Ready (TXRDY) is set when the transmit FIFO is below the programmed trigger level. The Receive Ready (RXRDY) is set when the receive FIFO fills to the programmed trigger level. However, the FIFO continues to fill regardless of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill level is above the programmed trigger level. 7.3.2 FIFO mode Table 12. Bit 7:6 FIFO Control Register bits description Description Receive trigger level in 32-byte FIFO mode[1]. These bits are used to set the trigger levels for receive FIFO interrupt and flow control. The SC16C852L will issue a receive ready interrupt when the number of characters in the receive FIFO reaches the selected trigger level. Refer to Table 13. 5:4 FCR[5:4] Transmit trigger level in 32-byte FIFO mode[2]. These bits are used to set the trigger level for the transmit FIFO interrupt and flow control. The SC16C852L will issue a transmit empty interrupt when the number of characters in FIFO drops below the selected trigger level. Refer to Table 14. 3 FCR[3] DMA mode select. logic 0 = set DMA mode ‘0’ (normal default condition) logic 1 = set DMA mode ‘1’ Transmit operation in mode ‘0’: When the SC16C852L is in the non-FIFO mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no characters in the transmit FIFO, the TXRDYA/TXRDYB pin will be a logic 0. Once active, the TXRDYA/TXRDYB pin will go to a logic 1 after the first character is loaded into the transmit holding register. Receive operation in mode ‘0’: When the SC16C852L is in non-FIFO mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is at least one character in the receive FIFO, the RXRDYA/RXRDYB pin will be a logic 0. Once active, the RXRDYA/RXRDYB pin will go to a logic 1 when there are no more characters in the receiver. Symbol FCR[7:6] SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 28 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder FIFO Control Register bits description …continued Description Transmit operation in mode ‘1’: When the SC16C852L is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYA/TXRDYB pin will be a logic 1 when the transmit FIFO is completely full; see Section 6.10 “DMA operation”. It will be a logic 0 when the trigger level has been reached. Receive operation in mode ‘1’: When the SC16C852L is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached, or a Receive Time-Out has occurred, the RXRDYA/RXRDYB pin will go to a logic 0. Once activated, it will go to a logic 1 after there are no more characters in the FIFO. Table 12. Bit 3 (cont.) Symbol 2 FCR[2] XMIT FIFO reset. logic 0 = no FIFO transmit reset (normal default condition) logic 1 = clears the contents of the transmit FIFO and resets the FIFO counter logic. This bit will return to a logic 0 after clearing the FIFO. 1 FCR[1] RCVR FIFO reset. logic 0 = no FIFO receive reset (normal default condition) logic 1 = clears the contents of the receive FIFO and resets the FIFO counter logic. This bit will return to a logic 0 after clearing the FIFO. 0 FCR[0] FIFO enable. logic 0 = disable the transmit and receive FIFO (normal default condition) logic 1 = enable the transmit and receive FIFO [1] [2] For 128-byte FIFO mode, refer to Section 7.16, Section 7.17, Section 7.18. For 128-byte FIFO mode, refer to Section 7.15, Section 7.17, Section 7.18. Table 13. FCR[7] 0 0 1 1 [1] RCVR trigger levels FCR[6] 0 1 0 1 RX FIFO trigger level (bytes) in 32-byte FIFO mode[1] 8 16 24 28 When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see Section 6.4 “FIFO operation”). Table 14. FCR[5] 0 0 1 1 [1] TX FIFO trigger levels FCR[4] 0 1 0 1 TX FIFO trigger level (bytes) in 32-byte FIFO mode[1] 16 8 24 30 When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see Section 6.4 “FIFO operation”). SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 29 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 7.4 Interrupt Status Register (ISR) The SC16C852L provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced. A lower level interrupt may be seen after servicing the higher level interrupt and re-reading the interrupt status bits. Table 15 “Interrupt source” shows the data values (bits 5:0) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels. Table 15. Interrupt source ISR[4] 0 0 0 0 0 1 0 ISR[3] 0 0 1 0 0 0 0 ISR[2] 1 1 1 0 0 0 0 ISR[1] 1 0 0 1 0 0 0 ISR[0] 0 0 0 0 0 0 0 Source of the interrupt LSR (Receiver Line Status Register) RXRDY (Received Data Ready) RXRDY (Receive Data time-out) TXRDY (Transmitter Holding Register Empty) MSR (Modem Status Register) RXRDY (Received Xoff signal)/ Special character CTS, RTS change of state Priority ISR[5] level 1 2 2 3 4 5 6 Table 16. Bit 7:6 0 0 0 0 0 0 1 Interrupt Status Register bits description Description FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being used in the non-FIFO mode. They are set to a logic 1 when the FIFOs are enabled in the SC16C852L mode. logic 0 or cleared = default condition INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1. ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5] indicates that CTS, RTS have been generated. Note that once set to a logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received. logic 0 or cleared = default condition INT priority bits 2:0. These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see Table 15). logic 0 or cleared = default condition INT status. logic 0 = an interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine logic 1 = no interrupt pending (normal default condition) Symbol ISR[7:6] 5:4 ISR[5:4] 3:1 ISR[3:1] 0 ISR[0] SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 30 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 17. Bit 7 Line Control Register bits description Description Divisor latch enable. The internal baud rate counter latch and Enhanced Feature mode enable. logic 0 = divisor latch disabled (normal default condition) logic 1 = divisor latch enabled 6 LCR[6] Set break. When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR[6] to a logic 0. logic 0 = no TX break condition (normal default condition) logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the remote receiver to a line break condition 5:3 2 LCR[5:3] LCR[2] Programs the parity conditions (see Table 18). Stop bits. The length of stop bit is specified by this bit in conjunction with the programmed word length (see Table 19). logic 0 or cleared = default condition 1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received (see Table 20). logic 0 or cleared = default condition Table 18. LCR[5] X X 0 0 1 Table 19. LCR[2] 0 1 1 Table 20. LCR[1] 0 0 1 1 LCR[5:3] parity selection LCR[4] X 0 1 0 1 LCR[3] 0 1 1 1 1 Parity selection no parity odd parity even parity forced parity ‘1’ forced parity ‘0’ Symbol LCR[7] LCR[2] stop bit length Word length (bits) 5, 6, 7, 8 5 6, 7, 8 LCR[1:0] word length LCR[0] 0 1 0 1 Word length (bits) 5 6 7 8 Stop bit length (bit times) 1 11⁄2 2 SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 31 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 21. Bit 7 Modem Control Register bits description Description Clock select logic 0 = divide-by-1 clock input logic 1 = divide-by-4 clock input 6 MCR[6] IR enable (see Figure 31). logic 0 = enable the standard modem receive and transmit input/output interface (normal default condition) logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/inputs are routed to the infrared encoder/decoder. The data input and output levels will conform to the IrDA infrared interface requirement. As such, while in this mode, the infrared TX output will be a logic 0 during idle data conditions. 5 4 MCR[5] MCR[4] Reserved; set to ‘0’. Loopback. Enable the local loopback mode (diagnostics). In this mode the transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI are disconnected from the SC16C852L I/O pins. Internally the modem data and control pins are connected into a loopback data configuration (see Figure 10). In this mode, the receiver and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts’ sources are switched to the lower four bits of the Modem Control. Interrupts continue to be controlled by the IER register. logic 0 = disable Loopback mode (normal default condition) logic 1 = enable local Loopback mode (diagnostics) 3 MCR[3] OP2A/OP2B, INT enable logic 0 = forces INT (A, B) outputs to the 3-state mode and sets OP2A/OP2B to a logic 1 (normal default condition) logic 1 = forces the INT (A, B) outputs to the active mode and sets OP2A/OP2B to a logic 0 Remark: OP2A/OP2B pins do not exist on the HVQFN32 package. 2 MCR[2] OP1A/OP1B are not available as an external signal in the SC16C852L. This bit is instead used in the Loopback mode only. In the Loopback mode, this bit is used to write the state of the modem RI interface signal. RTS logic 0 = force RTS output to a logic 1 (normal default condition) logic 1 = force RTS output to a logic 0 0 MCR[0] DTR logic 0 = force DTR output to a logic 1 (normal default condition) logic 1 = force DTR output to a logic 0 Symbol MCR[7] 1 MCR[1] SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 32 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C852L and the CPU. Table 22. Bit 7 Line Status Register bits description Description FIFO data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current FIFO data. This bit is cleared when there are no remaining error flags associated with the remaining data in the FIFO. 6 LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. It is reset to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode, this bit is set to ‘1’ whenever the transmit FIFO and transmit shift register are both empty. THR empty. This bit is the Transmit Holding Register Empty indicator. This bit indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to CPU when the THR interrupt enable is set. The THR bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. The bit is reset to a logic 0 concurrently with the loading of the transmitter holding register by the CPU. In the FIFO mode, this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO. Break interrupt. logic 0 = no break condition (normal default condition) logic 1 = the receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. 3 LSR[3] Framing error. logic 0 = no framing error (normal default condition) logic 1 = framing error. The receive character did not have a valid stop bit(s). In the FIFO mode, this error is associated with the character at the top of the FIFO. 2 LSR[2] Parity error. logic 0 = no parity error (normal default condition) logic 1 = parity error. The receive character does not have correct parity information and is suspect. In the FIFO mode, this error is associated with the character at the top of the FIFO. 1 LSR[1] Overrun error. logic 0 = no overrun error (normal default condition) logic 1 = overrun error. A data overrun error occurred in the Receive Shift Register. This happens when additional data arrives while the FIFO is full. In this case, the previous data in the shift register is overwritten. Note that under this condition, the data byte in the Receive Shift Register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error. 0 LSR[0] Receive data ready. logic 0 = no data in Receive Holding Register or FIFO (normal default condition) logic 1 = data has been received and is saved in the Receive Holding Register or FIFO Symbol LSR[7] 5 LSR[5] 4 LSR[4] SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 33 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 7.8 Modem Status Register (MSR) This register shares the same address as EFCR register. This is a read-only register and it provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C852L is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register. When write, the data will be written to EFCR register. Table 23. Bit 7 6 5 4 3 Modem Status Register bits description Description CD. During normal operation, this bit is the complement of the CD input. Reading this bit in the loopback mode produces the state of MCR[3] (OP2). RI. During normal operation, this bit is the complement of the RI input. Reading this bit in the loopback mode produces the state of MCR[2] (OP1). DSR. During normal operation, this bit is the complement of the DSR input. During the loopback mode, this bit is equivalent to MCR[0] (DTR). CTS. During normal operation, this bit is the complement of the CTS input. During the loopback mode, this bit is equivalent to MCR[1] (RTS). ∆CD [1] logic 0 = no CD change (normal default condition) logic 1 = the CD input to the SC16C852L has changed state since the last time it was read. A modem Status Interrupt will be generated. 2 MSR[2] ∆RI [1] logic 0 = no RI change (normal default condition) logic 1 = the RI input to the SC16C852L has changed from a logic 0 to a logic 1. A modem Status Interrupt will be generated. 1 MSR[1] ∆DSR [1] logic 0 = no DSR change (normal default condition) logic 1 = the DSR input to the SC16C852L has changed state since the last time it was read. A modem Status Interrupt will be generated. 0 MSR[0] ∆CTS [1] logic 0 = no CTS change (normal default condition) logic 1 = the CTS input to the SC16C852L has changed state since the last time it was read. A modem Status Interrupt will be generated. [1] Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated. Symbol MSR[7] MSR[6] MSR[5] MSR[4] MSR[3] SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 34 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 7.9 Extra Feature Control Register (EFCR) This is a write-only register, and it allows the software access to these registers: first extra feature register set, second extra feature register set, Transmit FIFO Level Counter (TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT). Table 24. Bit 7:3 2:1 Extra Feature Control Register bits description Symbol EFCR[7:3] EFCR[2:1] Description reserved Enable Extra Feature Control bits 00 = General register set is accessible 01 = First extra feature register set is accessible 10 = Second extra feature register set is accessible 11 = reserved 0 EFCR[0] Enable TXLVLCNT and RXLVLCNT access 0 = TXLVLCNT and RXLVLCNT are disabled 1 = TXLVLCNT and RXLVLCNT are enabled and can be read. Remark: EFCR[2:1] has higher priority than EFCR[0]. TXLVLCNT and RXLVLCNT can only be accessed if EFCR[2:1] are zeroes. 7.10 Scratchpad Register (SPR) The SC16C852L provides a temporary data register to store 8 bits of user information. 7.11 Division Latch (DLL and DLM) These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLM, stores the most significant part of the divisor. DLL stores the least significant part of the division. 7.12 Transmit FIFO Level Count (TXLVLCNT) This register is a read-only register. It reports the number of spaces available in the transmit FIFO. 7.13 Receive FIFO Level Count (RXLVLCNT) This register is a read-only register. It reports the fill level of the receive FIFO (the number of characters in the RX FIFO). SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 35 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 7.14 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential numbers. Table 25. Bit 7 Enhanced Feature Register bits description Description Automatic CTS flow control. logic 0 = automatic CTS flow control is disabled (normal default condition) logic 1 = enable automatic CTS flow control. Transmission will stop when CTS goes to a logical 1. Transmission will resume when the CTSA/CTSB pin returns to a logical 0. 6 EFR[6] Automatic RTS flow control. Automatic RTS may be used for hardware flow control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS will go to a logic 1 at the next trigger level. RTS will return to a logic 0 when data is unloaded below the next lower trigger level (programmed trigger level 1). The state of this register bit changes with the status of the hardware flow control. RTS functions normally when hardware flow control is disabled. logic 0 = automatic RTS flow control is disabled (normal default condition) logic 1 = enable automatic RTS flow control 5 EFR[5] Special Character Detect. logic 0 = special character detect disabled (normal default condition) logic 1 = special character detect enabled. The SC16C852L compares each incoming receive character with Xoff2 data. If a match exists, the received data will be transferred to FIFO and ISR[4] will be set to indicate detection of special character. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. When this feature is enabled, the normal software flow control must be disabled (EFR[3:0] must be set to a logic 0). 4 EFR[4] Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and MCR[7:5] can be modified and latched. After modifying any bits in the enhanced registers, EFR[4] can be set to a logic 0 to latch the new values. This feature prevents existing software from altering or overwriting the SC16C852L enhanced functions. logic 0 = disable/latch enhanced features[1]. (Normal default condition.) logic 1 = enables the enhanced functions[1]. 3:0 EFR[3:0] Cont-3:0 TX, RX control. Logic 0 or cleared is the default condition. Combinations of software flow control can be selected by programming these bits. See Table 26. Enhanced function control bits IER[7:4], ISR[5:4], FCR[5:4] and MCR[7:5]. Symbol EFR[7] [1] SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 36 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder Software flow control functions[1] Cont-2 0 0 1 1 X X X 0 1 1 Cont-1 X X X X 0 1 0 1 1 1 Cont-0 X X X X 0 0 1 1 1 1 TX, RX software flow controls No transmit flow control Transmit Xon1/Xoff1 Transmit Xon2/Xoff2 Transmit Xon1 and Xon2/Xoff1 and Xoff2 No receive flow control Receiver compares Xon1/Xoff1 Receiver compares Xon2/Xoff2 Transmit Xon1/Xoff1 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 Transmit Xon2/Xoff2 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 Transmit Xon1 and Xon2, Xoff1 and Xoff2 Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 Table 26. Cont-3 0 1 0 1 X X X 1 0 1 [1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer. 7.15 Transmit Interrupt Level register (TXINTLVL) This 8-bit register is used to store the transmit FIFO trigger levels used for DMA and interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1. Table 27 shows TXINTLVL register bit settings. Table 27. Bit 7:0 TXINTLVL register bits description Description This register stores the programmable transmit interrupt trigger levels for 128-byte FIFO mode[1]. 0x00 = trigger level is set to 1 0x01 = trigger level is set to 1 ... 0x80 = trigger level is set to 128 [1] For 32-byte FIFO mode, refer to Section 7.3. Symbol TXINTLVL[7:0] 7.16 Receive Interrupt Level register (RXINTLVL) This 8-bit register is used to store the receive FIFO trigger levels used for DMA and interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1. Table 28 shows RXINTLVL register bit settings. Table 28. Bit 7:0 RXINTLVL register bits description Symbol RXINTLVL[7:0] Description This register stores the programmable receive interrupt trigger levels for 128-byte FIFO mode[1]. 0x00 = trigger level is set to 1 0x01 = trigger level is set to 1 ... 0x80 = trigger level is set to 128 SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 37 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder [1] For 32-byte FIFO mode, refer to Section 7.3. 7.17 Flow Control Trigger Level High (FLWCNTH) This 8-bit register is used to store the receive FIFO high threshold levels to start/stop transmission during hardware/software flow control. Table 29 shows FLWCNTH register bit settings; see Section 6.5. Table 29. Bit 7:0 FLWCNTH register bits description Symbol FLWCNTH[7:0] Description This register stores the programmable HIGH threshold level for hardware and software flow control for 128-byte FIFO mode[1]. 0x00 = trigger level is set to 1 0x01 = trigger level is set to 1 ... 0x80 = trigger level is set to 128 [1] For 32-byte FIFO mode, refer to Section 7.3. 7.18 Flow Control Trigger Level Low (FLWCNTL) This 8-bit register is used to store the receive FIFO low threshold levels to start/stop transmission during hardware/software flow control. Table 30 shows FLWCNTL register bit settings; see Section 6.5. Table 30. Bit 7:0 FLWCNTL register bits description Symbol FLWCNTL[7:0] Description This register stores the programmable LOW threshold level for hardware and software flow control for 128-byte FIFO mode[1]. 0x00 = trigger level is set to 1 0x01 = trigger level is set to 1 ... 0x80 = trigger level is set to 128 [1] For 32-byte FIFO mode, refer to Section 7.3. 7.19 Clock Prescaler (CLKPRES) This register hold values for the clock prescaler. Table 31. Bit 7:4 3:0 Clock Prescaler register bits description Symbol CLKPRES[7:4] CLKPRES[3:0] Description reserved Clock Prescaler value. Reset to 0. SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 38 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 7.20 RS-485 turn-around time delay (RS485TIME) The value in this register controls the turn-around time of the external line transceiver in bit time. In automatic 9-bit mode RTSA/RTSB or DTRA/DTRB pin is used to control the direction of the line driver, after the last bit of data has been shifted out of the transmit shift register the UART will count down the value in this register. When the count value reaches zero, the UART will assert RTSA/RTSB or DTRA/DTRB pin (logic 0) to turn the external RS-485 transceiver around for receiving. Table 32. Bit 7:0 RS-485 programmable turn-around time register bits description Symbol RS485TIME[7:0] Description External RS-485 transceiver turn-around time delay. The value represents the bit time at the programmed baud rate. 7.21 Advanced Feature Control Register 2 (AFCR2) Table 33. Bit 7:6 5 Advanced Feature Control Register 2 register bits description Symbol AFCR2[7:6] AFCR2[5] Description reserved RTSInvert. Invert RTS or DTR signal in automatic 9-bit mode. logic logic 0 = RTS or DTR is set to 0 by the UART during transmission, and to 1 during reception logic 1 = RTS or DTR is set to 1 by the UART during transmission, and to 0 during reception 4 AFCR2[4] RTSCon. Enable the transmitter to control RTSx or DTRx pin in automatic 9-bit mode. logic logic 0 = transmitter does not control RTSx or DTRx pin logic 1 = transmitter controls RTSx or DTRx pin 3 AFCR2[3] RS485 RTS/DTR. Select RTSx or DTRx pin to control the external transceiver. logic logic 0 = RTSx pin is used to control the external transceiver logic 1 = DTRx pin is used to control the external transceiver 2 AFCR2[2] TXDisable. Disable transmitter logic 0 = transmitter is enabled logic 1 = transmitter is disable 1 AFCR2[1] RXDisable. Disable receiver logic 0 = receiver is enabled logic 1 = receiver is disable 0 AFCR2[0] 9-bitMode. Enable 9-bit mode or Multidrop (RS-485) mode logic logic 0 = normal RS-232 mode logic 1 = enable 9-bit mode SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 39 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 7.22 Advanced Feature Control Register 1 (AFCR1) Table 34. Bit 7 Advanced Feature Control Register 1 register bits description Symbol AFCR1[7] Description Concurrent write. When this bit is set the host can write concurrently to the same register of all channel. logic logic 0 = Normal operation logic 1 = Concurrent Write operation 6:5 4 AFCR1[6:5] AFCR1[4] reserved Sleep RXLow. Program RX input to be edge-sensitive or level-sensitive. logic 0 = RX input is level-sensitive. If RXA/RXB pin is LOW, the UART will not go to sleep. Once the UART is in Sleep mode, it will wake up if RXA/RXB pin goes LOW. logic 1 = RX input is edge-sensitive. UART will go to sleep even if RXA/RXB pin is LOW, and will wake up when RXA/RXB pin toggles. 3 2 AFCR1[3] AFCR1[2] reserved RTS/CTS mapped to DTR/DSR. Switch the function of RTS/CTS to DTR/DSR. logic 0 = RTS and CTS signals are used for hardware flow control. logic 1 = DTR and DSR signals are used for hardware flow control. RTS and CTS retain their functionality. 1 AFCR1[1] SReset. Software Reset A write to this bit will reset the UART. Once the UART is reset this bit is automatically set to 0.[1] 0 AFCR1[0] TSR Interrupt. Select TSR interrupt mode logic 0 = transmit empty interrupt occurs when transmit FIFO falls below the trigger level or becomes empty. logic 1 = transmit empty interrupt occurs when transmit FIFO falls below the trigger level, or becomes empty and the last stop bit has been shifted out of the Transmit Shift Register. [1] It takes 4 XTAL1 clocks to reset the device. SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 40 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 7.23 SC16C852L external reset condition and software reset These two reset methods are identical and will reset the internal registers as indicated in Table 35. Table 35. Register IER FCR ISR LCR MCR LSR MSR EFCR SPR DLL DLM TXLVLCNT RXLVLCNT EFR Xon1 Xon2 Xoff1 Xoff2 TXINTLVL RXINTLVL FLWCNTH FLWCNTL CLKPRES RS485TIME AFCR2 AFCR1 Table 36. Output TXA, TXB OP2A, OP2B RTSA, RTSB DTRA, DTRB INTA, INTB Reset state for registers Reset state IER[7:0] = 0 FCR[7:0] = 0 ISR[7:1] = 0; ISR[0] = 1 LCR[7:0] = 0 MCR[7:0] = 0 LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0 MSR[7:4] = input signals; MSR[3:0] = 0 EFCR[7:0] = 0 SPR[7:0] = 1 undefined undefined TXLVLCNT[7:0] = 0 RXLVLCNT[7:0] = 0 EFR[7:0] = 0 undefined undefined undefined undefined TXINTLVL[7:0] = 0 RXINTLVL[7:0] = 0 FLWCNTH[7:0] = 0 FLWCNTL[7:0] = 0 CLKPRES[7:0] = 0 RS485TIME[7:0] = 0 AFCR2[7:0] = 0 AFCR1[7:0] = 0 Reset state for outputs Reset state logic 1 logic 1 logic 1 logic 1 3-state condition SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 41 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 8. Limiting values Table 37. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD Vn Tamb Tstg Ptot/pack [1] Parameter supply voltage voltage on any other pin ambient temperature storage temperature total power dissipation per package Conditions [1] Min VSS − 0.3 −40 −65 - Max 2.5 VDD + 0.3 +85 +150 500 Unit V V °C °C mW operating in free air Vn should not exceed 2.5 V. 9. Static characteristics Table 38. Static characteristics Tamb = −40 °C to +85 °C; VDD = 1.65 V to 1.95 V; unless otherwise specified. Symbol VIL(clk) VIH(clk) VIL VIH VOL VOH ILIL ILIH IL(clk) IDD IDD(sleep) IDD(lp) Ci [1] [2] [3] Parameter LOW-level clock input voltage HIGH-level clock input voltage LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage LOW-level input leakage current HIGH-level input leakage current clock leakage current supply current sleep mode supply current low-power mode supply current input capacitance Conditions Min 1.35 Typ - Max 0.25 0.45 0.35 1 1 30 30 2 5 5 5 Unit V V V V V V µA µA µA µA mA µA µA pF except XTAL1 clock except XTAL1 clock IOL = 2 mA IOH = −800 µA [1] [1] 1.35 1.45 - LOW-level HIGH-level f = 5 MHz [2] [3] - Except XTAL2. Sleep current might be higher if there is any activity on the UART data bus during Sleep mode. Activate by LOWPWR pin. SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 42 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 10. Dynamic characteristics Table 39. Dynamic characteristics - Intel or 16 mode Tamb = −40 °C to +85 °C; VDD = 1.65 V to 1.95 V; unless otherwise specified. Symbol tWH tWL tw(clk) fXTAL1 tsu(A) th(A) td(CS-IOR) Parameter pulse width HIGH pulse width LOW clock pulse width frequency on pin XTAL1 address setup time address hold time delay time from CS to IOR [1][2] Conditions Min 6 6 12.5 0 10 5 [4] [4] Typ - Max 80 50 50 1TRCLK 8TRCLK 40 20 50 50 50 1TRCLK 1TRCLK 24TRCLK 50 (216 − 1) Unit ns ns ns MHz ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s ns ns td(IOW-TXRDYH) delay time from IOW to TXRDY HIGH td(IOR-RXRDYH) delay time from IOR to RXRDY HIGH td(stop-RXRDY) td(start-TXRDY) tw(IOR) th(IOR-CS) td(IOR) td(IOR-Q) tdis(IOR-QZ) td(CSL-IOWL) tw(IOW) th(IOW-CS) td(IOW) tsu(D-IOWH) th(IOWH-D) td(IOW-Q) td(modem-INT) td(IOR-INTL) td(stop-INT) td(start-INT) td(IOW-TX) td(IOW-INTL) tw(RESET) N [1] [2] [3] [4] delay time from stop to RXRDY delay time from start to TXRDY IOR pulse width time hold time from IOR to chip select IOR delay time delay time from IOR to data output disable time from IOR to high-impedance data output[3] delay time from CS LOW to IOW LOW IOW pulse width time hold time from IOW to CS IOW delay time setup time from data input to IOW HIGH data input hold time after IOW HIGH delay time from IOW to data output delay time from modem to INT delay time from IOR to INT LOW delay time from stop to INT delay time from start to INT delay time from IOW to TX delay time from IOW to INT LOW pulse width on pin RESET baud rate divisor 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 20 0 10 5 10 0 10 5 5 - [4] 8TRCLK 10 1 [4] Applies to external clock, crystal oscillator max 24 MHz. Maximum frequency = -------------10 % of the data bus output voltage level. RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches. 1 t w ( clk ) SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 43 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder Table 40. Dynamic characteristics - Motorola or 68 mode Tamb = −40 °C to +85 °C; VDD = 1.65 V to 1.95 V; unless otherwise specified. Symbol tWH tWL tw(clk) fXTAL1 tsu(A) th(A) tsu(RWL-CSL) tsu(RWH-CSL) td(stop-RXRDY) td(start-TXRDY) tw(CS) td(CS) td(CS-Q) tdis(CS-QZ) th(CS-RWH) td(RW) tsu(D-CSH) th(CSH-D) td(modem-IRQL) td(CS-IRQH)R td(stop-IRQL) td(CS-RXRDYH)R td(CS-TX)W td(start-IRQL) td(CS-IRQH)W td(CS-TXRDYH)W td(CS-Q)W tw(RESET_N) N [1] [2] [3] Parameter pulse width HIGH pulse width LOW clock pulse width frequency on pin XTAL1 address setup time address hold time set-up time from R/W LOW to CS LOW set-up time from R/W HIGH to CS LOW delay time from stop to RXRDY delay time from start to TXRDY CS pulse width CS delay time delay time from CS to data output disable time from CS to high-impedance data output hold time from CS to R/W HIGH R/W delay time set-up time from data input to CS HIGH data input hold time after CS HIGH delay time from modem to IRQ LOW read delay time from CS to IRQ HIGH delay time from stop to IRQ LOW read delay time from CS to RXRDY HIGH write delay time from CS to TX delay time from start to IRQ LOW write delay time from CS to IRQ HIGH write delay time from CS to TXRDY HIGH write delay time from CS to data output pulse width on pin RESET baud rate divisor Conditions Min 6 6 12.5 [1][2] Typ - Max 80 1TRCLK 8TRCLK 40 20 50 50 1TRCLK 50 1TRCLK 50 50 50 (216 − 1) Unit ns ns ns MHz ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns s ns s ns ns ns ns 5 10 10 10 [3] [3] 20 10 5 10 5 5 - 25 pF load 25 pF load 25 pF load 25 pF load [3] 8TRCLK 10 1 [3] [3] 24TRCLK s Applies to external clock, crystal oscillator max 24 MHz. Maximum frequency = -------------RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches. 1 t w ( clk ) SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 44 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 10.1 Timing diagrams th(A) A0 to A2 tsu(A) valid address th(IOW-CS) CSx active td(CSL-IOWL) IOW tw(IOW) active th(IOWH-D) td(IOW) tsu(D-IOWH) D0 to D7 data 002aac405 Fig 11. General write timing in 16 mode A0 to A4 tsu(A) th(A) tw(CS) CS tsu(RWL-CSL) th(CS-RWH) R/W th(CSH-D) td(RW) tsu(D-CSH) D0 to D7 002aac408 Fig 12. General write timing in 68 mode SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 45 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder th(A) A0 to A2 tsu(A) valid address th(IOR-CS) CSx active td(CS-IOR) IOR tw(IOR) active td(IOR-Q) td(IOR) tdis(IOR-QZ) data 002aac406 D0 to D7 Fig 13. General read timing in 16 mode th(A) A0 to A4 tsu(A) tw(CS) td(CS) CS tsu(RWH-CSL) tdis(CS-QZ) R/W td(CS-Q) D0 to D7 002aac407 Fig 14. General read timing in 68 mode tWL external clock tWH tw(clk) 002aac357 1 f XTAL1 = -------------t w ( clk ) Fig 15. External clock timing SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 46 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder IOW active td(IOW-Q) RTSA, RTSB DTRA, DTRB change of state change of state CDA, CDB CTSA, CTSB DSRA, DSRB td(modem-INT) INT change of state change of state td(modem-INT) active td(IOR-INTL) active active IOR active active active td(modem-INT) RIA, RIB change of state 002aac611 Fig 16. Modem input/output timing in 16 mode CS (write)(1) active td(CS-Q)W RTSA, RTSB DTRA, DTRB change of state change of state CDA, CDB CTSA, CTSB DSRA, DSRB change of state td(modem-IRQL) change of state td(modem-IRQL) IRQ active active td(CS-IRQH)R active CS (read)(2) active active td(modem-IRQL) active RIA, RIB change of state 002aac618 (1) CS timing during a write cycle. See Figure 12. (2) CS timing during a read cycle. See Figure 14. Fig 17. Modem input/output timing in 68 mode SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 47 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit next data start bit RXA, RXB 5 data bits 6 data bits 7 data bits INT(1)(2) td(stop-INT) active td(IOR-INTL) IOR active 16 baud rate clock 002aac612 (1) INT is active when RX FIFO fills up to trigger level or a time-out condition happens (see Section 6.8). (2) INT is cleared when RX FIFO drops below trigger level. Fig 18. Receive timing in 16 mode start bit data bits (0 to 7) D0 D1 D2 5 data bits 6 data bits 7 data bits D3 D4 D5 D6 D7 parity bit stop bit next data start bit RXA, RXB td(stop-IRQL) active td(CS-IRQH)R IRQ(1)(2) CS (read) active 16 baud rate clock 002aac619 (1) IRQ is active when RX FIFO fills up to trigger level or time-out condition happens (see Section 6.8). (2) IRQ is cleared when RX FIFO drops below trigger level. Fig 19. Receive timing in 68 mode SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 48 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit next data start bit RXA, RXB td(stop-RXRDY) RXRDYA, RXRDYB active data ready td(IOR-RXRDYH) IOR active 002aac613 Fig 20. Receive ready timing in non-FIFO mode (16 mode) start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit next data start bit RXA, RXB td(stop-RXRDY) active data ready td(CS-RXRDYH)R CS (read) active 002aac620 RXRDYA, RXRDYB Fig 21. Receive ready timing in non-FIFO mode (68 mode) SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 49 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit RXA, RXB first byte that reaches the trigger level td(stop-RXRDY) RXRDYA, RXRDYB active data ready td(IOR-RXRDYH) IOR active 002aac614 Fig 22. Receive ready timing in FIFO mode (16 mode) start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit RXA, RXB first byte that reaches the trigger level td(stop-RXRDY) active data ready td(CS-RXRDYH)R CS (read) active 002aac621 RXRDYA, RXRDYB Fig 23. Receive ready timing in FIFO mode (68 mode) SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 50 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit next data start bit TXA, TXB 5 data bits 6 data bits 7 data bits INT(1)(2) td(start-INT) td(IOW-TX) IOW active active transmitter ready td(IOW-INTL) active 16 baud rate clock 002aac616 (1) INT is active when TX FIFO is empty or TX FIFO drops below trigger level. (2) INT is cleared when ISR is read or TX FIFO fills up to trigger level. Fig 24. Transmit timing in 16 mode start bit data bits (0 to 7) D0 D1 D2 5 data bits 6 data bits 7 data bits D3 D4 D5 D6 D7 parity bit stop bit next data start bit TXA, TXB IRQ(1)(2) td(start-IRQL) td(CS-TX)W CS (write) active active TX ready td(CS-IRQH)W active 16 baud rate clock 002aac622 (1) IRQ is active when TX FIFO is empty or TX FIFO drops below trigger level. (2) IRQ is cleared when ISR is read or TX FIFO fills up to trigger level. Fig 25. Transmit timing in 68 mode SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 51 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit next data start bit TXA, TXB IOW active td(start-TXRDY) D0 to D7 byte #1 td(IOW-TXRDYH) TXRDYA, TXRDYB active transmitter ready 002aac617 transmitter not ready Fig 26. Transmit ready timing in non-FIFO mode (16 mode) start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit next data start bit TXA, TXB CS (write) active td(start-TXRDY) D0 to D7 byte #1 td(CS-TXRDYH)W TXRDYA, TXRDYB transmitter not ready active transmitter ready 002aac623 Fig 27. Transmit ready timing in non-FIFO mode (68 mode) SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 52 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit TXA, TXB 5 data bits 6 data bits 7 data bits IOW active td(start-TXRDY) D0 to D7 byte #32 or byte #128 td(IOW-TXRDYH) TXRDYA, TXRDYB FIFO full 002aac615 Fig 28. Transmit ready timing in FIFO mode (DMA mode ‘1’) in 16 mode start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit TXA, TXB 5 data bits 6 data bits 7 data bits CS (write) active td(start-TXRDY) D0 to D7 byte #32 or byte #128 td(CS-TXRDYH)W TXRDYA, TXRDYB trigger lead 002aac624 Fig 29. Transmit ready timing in FIFO mode (DMA mode ‘1’) in 68 mode SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 53 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder UART frame start data bits stop TX data 0 1 0 1 0 0 1 1 0 1 IrDA TX data 1/ bit time 2 3/ bit time 16 bit time 002aaa212 Fig 30. Infrared transmit timing IrDA RX data bit time RX data 0 1 0 1 0 0 to 1 16× clock delay 0 1 1 0 1 start data bits stop UART frame 002aaa213 Fig 31. Infrared receive timing SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 54 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 11. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 37 25 24 ZE A e E HE A A2 A1 (A 3) θ Lp L detail X wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 θ 7 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 32. Package outline SOT313-2 (LQFP48) SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 55 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm SOT617-1 D B A terminal 1 index area E A A1 c detail X e1 e 9 L 8 17 e 1/2 e C b 16 vMCAB wMC y1 C y Eh 1/2 e e2 1 terminal 1 index area 24 32 Dh 0 2.5 scale E (1) 5.1 4.9 Eh 3.25 2.95 e 0.5 e1 3.5 e2 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm 25 X DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 5.1 4.9 Dh 3.25 2.95 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT617-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18 Fig 33. Package outline SOT617-1 (HVQFN32) SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 56 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm SOT912-1 D ball A1 index area B A E A A2 A1 detail X e1 1/2 e e b v w M M CAB C C y1 C y F E D C B A e e2 1/2 e ball A1 index area 1 2 3 4 5 6 X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.15 A1 0.25 0.15 A2 0.90 0.75 b 0.35 0.25 D 3.6 3.4 E 3.6 3.4 e 0.5 e1 2.5 e2 2.5 v 0.15 w 0.05 y 0.08 y1 0.1 OUTLINE VERSION SOT912-1 REFERENCES IEC --JEDEC --JEITA --- EUROPEAN PROJECTION ISSUE DATE 05-08-09 05-09-01 Fig 34. Package outline SOT912-1 (TFBGA36) SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 57 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 12. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 12.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering 12.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 58 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 35) than a PbSn process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 41 and 42 Table 41. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 42. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 35. SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 59 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 35. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 13. Abbreviations Table 43. Acronym CPU DLL DLM DMA FIFO IrDA ISDN LSB MSB PCB RoHS UART Abbreviations Description Central Processing Unit Divisor Latch LSB Divisor Latch MSB Direct Memory Access First In, First Out Infrared Data Association Integrated Service Digital Network Least Significant Bit Most Significant Bit Printed-Circuit Board Restriction of Hazardous Substances directive Universal Asynchronous Receiver/Transmitter SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 60 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 14. Revision history Table 44. Revision history Release date 20080118 Data sheet status Product data sheet Change notice Supersedes SC16C852L_2 Document ID SC16C852L_3 Modifications: • • added TFBGA36 package option Table 10 “SC16C852L internal registers”, sub-section “Second special register set”: – TXLVLCNT changed from “R/W” to “R” – RXLVLCNT changed from “R/W” to “R” • • Section 7.12 “Transmit FIFO Level Count (TXLVLCNT)”, 2nd sentence: changed from “It reports the number of characters available ...” to “It reports the number of spaces available ...” Table 38 “Static characteristics”: – changed maximum IDD(sleep) from “80 µA” to “5 µA” – changed maximum IDD(lp) from “80 µA” to “5 µA” • Table 39 “Dynamic characteristics - Intel or 16 mode”: – minimum tsu(A) changed from 5 ns to 0 ns – maximum td(IOR-Q) changed from 20 ns to 40 ns • SC16C852L_2 SC16C852L_1 Table 40 “Dynamic characteristics - Motorola or 68 mode”: maximum td(CS-Q) changed from 20 ns to 40 ns Product data sheet Objective data sheet SC16C852L_1 - 20070125 20061109 SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 61 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 62 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Functional description . . . . . . . . . . . . . . . . . . 11 6.1 UART A-B functions . . . . . . . . . . . . . . . . . . . . 12 6.2 Extended mode (128-byte FIFO) . . . . . . . . . . 12 6.3 Internal registers. . . . . . . . . . . . . . . . . . . . . . . 13 6.4 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4.1 32-byte FIFO mode. . . . . . . . . . . . . . . . . . . . . 14 6.4.2 128-byte FIFO mode. . . . . . . . . . . . . . . . . . . . 14 6.5 Hardware flow control . . . . . . . . . . . . . . . . . . . 14 6.6 Software flow control . . . . . . . . . . . . . . . . . . . 15 6.7 Special character detect . . . . . . . . . . . . . . . . . 16 6.8 Interrupt priority and time-out interrupts . . . . . 16 6.9 Programmable baud rate generator . . . . . . . . 17 6.10 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 19 6.11 Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 19 6.12 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.12.1 Conditions to enter Sleep mode . . . . . . . . . . . 21 6.12.2 Conditions to resume normal operation . . . . . 21 6.13 Low power feature . . . . . . . . . . . . . . . . . . . . . 21 6.14 RS-485 features . . . . . . . . . . . . . . . . . . . . . . . 22 6.14.1 Auto RS-485 RTS control . . . . . . . . . . . . . . . . 22 6.14.2 RS-485 RTS inversion . . . . . . . . . . . . . . . . . . 22 6.14.3 Auto 9-bit mode (RS-485). . . . . . . . . . . . . . . . 22 6.14.3.1 Normal Multi-drop mode . . . . . . . . . . . . . . . . . 22 6.14.3.2 Auto address detection . . . . . . . . . . . . . . . . . . 23 7 Register descriptions . . . . . . . . . . . . . . . . . . . 23 7.1 Transmit (THR) and Receive (RHR) Holding Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2 Interrupt Enable Register (IER) . . . . . . . . . . . 26 7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation. . . . . . . . . . . . . . . . . . . . . . . . 27 7.2.2 IER versus Receive/Transmit FIFO polled mode operation. . . . . . . . . . . . . . . . . . . . . . . . 27 7.3 FIFO Control Register (FCR) . . . . . . . . . . . . . 28 7.3.1 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3.1.1 Mode 0 (FCR bit 3 = 0) . . . . . . . . . . . . . . . . . . 28 7.3.1.2 Mode 1 (FCR bit 3 = 1) . . . . . . . . . . . . . . . . . . 28 7.3.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4 Interrupt Status Register (ISR) . . . . . . . . . . . . 30 7.5 Line Control Register (LCR) . . . . . . . . . . . . . . 31 7.6 Modem Control Register (MCR) . . . . . . . . . . . 32 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 8 9 10 10.1 11 12 12.1 12.2 12.3 12.4 13 14 15 15.1 15.2 15.3 15.4 16 17 Line Status Register (LSR) . . . . . . . . . . . . . . Modem Status Register (MSR) . . . . . . . . . . . Extra Feature Control Register (EFCR) . . . . . Scratchpad Register (SPR) . . . . . . . . . . . . . . Division Latch (DLL and DLM) . . . . . . . . . . . . Transmit FIFO Level Count (TXLVLCNT) . . . . Receive FIFO Level Count (RXLVLCNT) . . . . Enhanced Feature Register (EFR). . . . . . . . . Transmit Interrupt Level register (TXINTLVL) . Receive Interrupt Level register (RXINTLVL) . Flow Control Trigger Level High (FLWCNTH). Flow Control Trigger Level Low (FLWCNTL) . Clock Prescaler (CLKPRES) . . . . . . . . . . . . . RS-485 turn-around time delay (RS485TIME) Advanced Feature Control Register 2 (AFCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Feature Control Register 1 (AFCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SC16C852L external reset condition and software reset. . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 34 35 35 35 35 35 36 37 37 38 38 38 39 39 40 41 42 42 43 45 55 58 58 58 58 59 60 61 62 62 62 62 62 62 63 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 January 2008 Document identifier: SC16C852L_3