SC68C652BIB48

SC68C652B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs, IrDA encoder/decoder, and 68 mode µP interface Rev. 02 — 2 November 2009 Product data sheet 1. General description The SC68C652B is a 2 channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s. The SC68C652B is pin compatible with the SC68C2550B. The SC68C652B provides enhanced UART functions with 32-byte FIFOs, modem control interface, DMA mode data transfer, and infrared (IrDA) encoder/decoder. The DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDYn and RXRDYn signals. On-board status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by software to meet specific user requirements. An internal loopback capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC68C652B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range, and is available in the plastic LQFP48 package. 2. Features I I I I I I I I I I I I I I I I 1. 2 channel UART with 68 mode (Motorola) µP interface 5 V, 3.3 V and 2.5 V operation 5 V tolerant on input only pins1 Industrial temperature range (−40 °C to +85 °C) Software compatible with industry standard 16C450, 16C550, and SC16C650 Up to 5 Mbit/s baud rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V 32-byte transmit FIFO to reduce the bandwidth requirement of the external CPU 32-byte receive FIFO with error flags to reduce the bandwidth requirement of the external CPU Independent transmit and receive UART control Four selectable receive and transmit FIFO interrupt trigger levels Automatic software (Xon/Xoff) and hardware (RTSn/CTSn) flow control Programmable Xon/Xoff characters Software selectable baud rate generator Standard modem interface or infrared IrDA encoder/decoder interface Supports IrDA version 1.0 (up to 115.2 kbit/s) Sleep mode For data bus pins D7 to D0, see Table 27 “Limiting values”. NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder I Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break) I Transmit, Receive, Line Status, and Data Set interrupts independently controlled I Fully programmable character formatting: N 5, 6, 7, or 8-bit characters N Even, odd, or no parity formats N 1, 11⁄2, or 2 stop bit generation N Baud generation (DC to 5 Mbit/s) I False start bit detection I Complete status reporting capabilities I 3-state output TTL drive capabilities for bidirectional data bus and control bus I Line break generation and detection I Internal diagnostic capabilities: N Loopback controls for communications link fault isolation I Prioritized interrupt system controls I Modem control functions (CTS, RTS, DSR, DTR, RI, and CD) 3. Ordering information Table 1. Ordering information Package Name SC68C652BIB48 LQFP48 Description plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm Version SOT313-2 Type number SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 2 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 4. Block diagram SC68C652B TRANSMIT FIFO REGISTER D0 to D7 R/W RESET DATA BUS AND CONTROL LOGIC FLOW CONTROL LOGIC IR ENCODER TRANSMIT SHIFT REGISTER TXA, TXB INTERCONNECT BUS LINES AND CONTROL SIGNALS RECEIVE FIFO REGISTER RECEIVE SHIFT REGISTER RXA, RXB A0 to A3 CS REGISTER SELECT LOGIC FLOW CONTROL LOGIC IR DECODER DTRA, DTRB RTSA, RTSB OP2A, OP2B MODEM CONTROL LOGIC IRQ TXRDYA, TXRDYB RXRDYA, RXRDYB INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR CTSA, CTSB RIA, RIB CDA, CDB DSRA, DSRB 002aab323 XTAL1 XTAL2 Fig 1. Block diagram of SC68C652B SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 3 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 5. Pinning information 5.1 Pinning 43 TXRDYA 39 DSRA 38 CTSA 40 CDA 42 VCC 41 RIA D5 D6 D7 RXB RXA TXRDYB TXA TXB OP2B 1 2 3 4 5 6 7 8 9 37 n.c. 36 RESET 35 DTRB 34 DTRA 33 RTSA 32 OP2A 31 RXRDYA 30 IRQ 29 n.c. 28 A0 27 A1 26 A2 25 n.c. GND 24 002aab324 48 D4 47 D3 46 D2 R/W 15 45 D1 CDB 16 SC68C652BIB48 CS 10 A3 11 n.c. 12 XTAL1 13 XTAL2 14 GND 17 RXRDYB 18 VCC 19 DSRB 20 RIB 21 RTSB 22 CTSB 23 Fig 2. Pin configuration for LQFP48 5.2 Pin description Table 2. Symbol A0 A1 A2 A3 Pin description Pin 28 27 26 11 Type I I I I Description Address 0 select bit. Internal registers address selection. Address 1 select bit. Internal registers address selection. Address 2 select bit. Internal registers address selection. Address 3 select bit. A3 is used to select Channel A or Channel B. A logic LOW selects Channel A, and a logic HIGH selects Channel B. (See Table 3.) Carrier Detect (active LOW). These inputs are associated with individual UART channels A and B. A logic 0 on these pins indicates that a carrier has been detected by the modem for that channel. Chip Select (active LOW). This pin enables data transfers between the user CPU and the SC68C652B for the channel(s) addressed. Individual UART sections (A, B) are addressed by A3. See Table 3. CDA CDB 40 16 I I CS 10 I SC68C652B_2 44 D0 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 4 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder Pin description …continued Pin 38 23 Type I I Description Clear to Send (active LOW). These inputs are associated with individual UART channels A and B. A logic 0 (LOW) on the CTSn pins indicates the modem or data set is ready to accept transmit data from the SC68C652B. Status can be tested by reading MSR[4]. These pins have no effect on the UART’s transmit or receive operation. Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Table 2. Symbol CTSA CTSB D0 D1 D2 D3 D4 D5 D6 D7 DSRA DSRB 44 45 46 47 48 1 2 3 39 20 I/O I/O I/O I/O I/O I/O I/O I/O I I Data Set Ready (active LOW). These inputs are associated with individual UART channels A and B. A logic 0 (LOW) on these pins indicates the modem or data set is powered-on and is ready for data exchange with the UART. These pins have no effect on the UART’s transmit or receive operation. Data Terminal Ready (active LOW). These outputs are associated with individual UART channels A and B. A logic 0 (LOW) on these pins indicates that the SC68C652B is powered-on and ready. These pins can be controlled via the modem control register. Writing a logic 1 to MCR[0] will set the DTRn output pin to logic 0 (LOW), enabling the modem. The output of these pins will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. These pins have no effect on the UART’s transmit or receive operation. Signal and power ground Interrupt Request. Interrupts from UART channels A-B are wire-ORed internally to function as a single IRQ interrupt. This pin transitions to a logic 0 (if enabled by the interrupt enable register) whenever a UART channel(s) requires service. Individual channel interrupt status can be determined by addressing each channel through its associated internal register, using CS and A3. An external pull-up resistor must be connected between this pin and VCC. A logic LOW on this pin will transfer the contents of the data bus (D[7:0]) from an external CPU to an internal register that is defined by address bits A[2:0]. A logic HIGH on this pin will load the contents of an internal register defined by address bits A[2:0] on the SC68C652B data bus (D[7:0]) for access by an external CPU. not connected Output 2 (user-defined). This function is associated with individual channels A and B. The state of these pins is defined by the user through the software settings of MCR[3]. OP2A/OP2B is a logic 0 when MCR[3] is set to a logic 1. OP2A/OP2B is a logic 1 when MCR[3] is set to a logic 0. The output of these two pins is HIGH after reset. DTRA DTRB 34 35 O O GND IRQ 17, 24 30 I O R/W 15 I n.c. OP2A OP2B 12, 25, 29, 37 32 9 O O SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 5 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder Pin description …continued Pin 36 Type I Description Reset (active LOW). This pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. See Section 7.11 “SC68C652B external reset condition” for initialization details. Ring Indicator (active LOW). These inputs are associated with individual UART channels A and B. A logic 0 on these pins indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on these input pins generates an interrupt. Request to Send (active LOW). These outputs are associated with individual UART channels, A and B. A logic 0 on the RTSn pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this pin to a logic 0, indicating data is available. After a reset these pins are set to a logic 1. These pins have no effect on the UART’s transmit or receive operation. Receive data input. These inputs are associated with individual serial channel data to the SC68C652B receive input circuits A and B. The RXn pin will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loopback mode, these RXn input pins are disabled and transmit data is connected to the UART receive input internally. Receive Ready (active LOW). RXRDYA or RXRDYB goes LOW when the trigger level has been reached or the FIFO has at least one character. It goes HIGH when the receive FIFO is empty. Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC68C652B. The TXn pin will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loopback mode, the TXn output pins are disabled and transmit data is internally connected to the UART receive input. Transmit Ready A, B (active LOW). These outputs provide the transmit FIFO/THR status for individual transmit channels A and B. TXRDYn is primarily intended for monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual channel’s TXRDYA, TXRDYB buffer ready status is indicated by logic 0, that is, at least one location is empty and available in the FIFO or THR. This pin goes to a logic 1 (DMA mode 1) when there are no more empty locations in the FIFO or THR. This signal can also be used for single mode transfers (DMA mode 0). Table 2. Symbol RESET RIA RIB 41 21 I I RTSA RTSB 33 22 O O RXA RXB 5 4 I I RXRDYA RXRDYB TXA TXB 31 18 7 8 O O O O TXRDYA TXRDYB 43 6 O O SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 6 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder Pin description …continued Pin 19, 42 13 Type I I Description Power supply input. Crystal or external clock input. Functions as a crystal input or as an external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit (see Figure 3). This configuration requires an external 1 MΩ resistor between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be connected to this pin to provide custom data rates. See Section 6.8 “Programmable baud rate generator”. Output of the crystal oscillator or buffered clock. (See also XTAL1.) XTAL2 is used as a crystal oscillator output or a buffered clock output. Should be left open if an external clock is connected to XTAL1. For extended frequency operation, this pin should be tied to VCC via a 2 kΩ resistor. Table 2. Symbol VCC XTAL1 XTAL2 14 O SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 7 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 6. Functional description The SC68C652B UART is pin-compatible with the SC68C2550B UART. It provides more enhanced features. All additional features are provided through a special enhanced feature register. The UART will perform serial-to-parallel conversion on data characters received from peripheral devices or modems, and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each channel of the SC68C652B UART can be read at any time during functional operation by the processor. The SC68C652B can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or programmable trigger levels. Primary outputs RXRDYn and TXRDYn allow signalling of DMA transfers. The SC68C652B has selectable hardware flow control and software flow control. Hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the RTSn output and CTSn input signals. Software flow control automatically controls data flow by using programmable Xon/Xoff characters. The UART includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (216 − 1). 6.1 UART A-B functions The UART provides the user with the capability to bidirectionally transfer information between an external CPU, the SC68C652B package, and an external serial device. A logic 0 on chip select pin CS and A3 (LOW or HIGH) allows the user to configure, send data, and/or receive data via UART channels A and B. Individual channel select functions are shown in Table 3. Table 3. CS 1 0 0 Channel selection using CS pin A3 0 1 UART channel none channel A channel B SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 8 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 6.2 Internal registers The SC68C652B provides two sets of internal registers (A and B) consisting of 17 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in Table 4. The UART registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user accessible scratchpad register (SPR), along with advanced feature registers EFR and Xon1, Xon2, Xoff1 and Xoff2. Table 4. A2 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 [1] [2] [3] Internal registers decoding A1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 Read mode Receive Holding Register Interrupt Enable Register Interrupt Status Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratchpad Register (DLL/DLM)[2] LSB of Divisor Latch MSB of Divisor Latch Enhanced Feature Register Xon1 word Xon2 word Xoff1 word Xoff2 word LSB of Divisor Latch MSB of Divisor Latch Enhanced Feature Register Xon1 word Xon2 word Xoff1 word Xoff2 word Write mode Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register n/a n/a Scratchpad Register General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1] Baud rate register set Enhanced register set (EFR, Xon1, Xon2, Xoff1, Xoff2)[3] These registers are accessible only when LCR[7] is a logic 0. These registers are accessible only when LCR[7] is a logic 1. Enhanced Feature Register, Xon1, Xon2, and Xoff1, Xoff2 are accessible only when the LCR is set to ‘BFh’. 6.3 FIFO operation The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]). With SC68C2550B devices, the user can set the receive trigger level, but not the transmit trigger level. The SC68C652B provides independent trigger levels for both receiver and transmitter. To remain compatible with SC68C2550B, the transmit interrupt trigger level is set to 16 following a reset. It should be noted that the user can set the transmit trigger levels by writing to the FCR register, but activation will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached. SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 9 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder Flow control mechanism IRQ pin activation RX 8 16 24 28 TX 16 8 24 30 Negate RTS or send Xoff 8 16 24 28 Assert RTS or send Xon 0 7 15 23 Table 5. Selected trigger level (characters) 8 16 24 28 6.4 Hardware flow control When automatic hardware flow control is enabled, the SC68C652B monitors the CTSn pin for a remote buffer overflow indication and controls the RTSn pin for local buffer overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to a logic 1. If CTSn transitions from a logic 0 to a logic 1 indicating a flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6:7]), and the SC68C652B will suspend TXn transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTSn input returns to a logic 0, indicating more data may be sent. With the auto-RTS function enabled, an interrupt is generated when the receive FIFO reaches the programmed trigger level. The RTSn pin will not be forced to a logic 1 (RTS off), until the receive FIFO reaches the next trigger level. However, the RTSn pin will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the programmed trigger level. However, under the above described conditions, the SC68C652B will continue to accept data until the receive FIFO is full. 6.5 Software flow control When software flow control is enabled, the SC68C652B compares one or two sequential receive data characters with the programmed Xon or Xoff character value(s). If received character(s) match the programmed Xoff values, the SC68C652B will halt transmission as soon as the current character(s) has completed transmission. When a match occurs, the receive ready (if enabled via Xoff IER[5]) flags will be set and the interrupt output pin (if receive interrupt is enabled) will be activated. Following a suspension due to a match of the Xoff characters’ values, the SC68C652B will monitor the receive data stream for a match to the Xon1/Xon2 character value(s). If a match is found, the SC68C652B will resume operation and clear the flags (ISR[4]). Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset, the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff characters and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected, the SC68C652B compares two consecutive receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TXn transmissions accordingly. Under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible receive data buffer or FIFO. When using a software flow control, the Xon/Xoff characters cannot be used for data transfer. In the event that the receive buffer is overfilling and flow control needs to be executed, the SC68C652B automatically sends an Xoff message (when enabled) via the serial TXn output to the remote modem. The SC68C652B sends the Xoff1/Xoff2 characters as soon SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 10 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder as received data passes the programmed trigger level. To clear this condition, the SC68C652B will transmit the programmed Xon1/Xon2 characters as soon as receive data drops below the programmed trigger level. 6.6 Special feature software flow control A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit character is detected, wit will be placed on the user-accessible data stack along with normal incoming receive data. This condition is selected in conjunction with EFR[3:0]. Note that software flow control should be turned off when using this special mode by setting EFR[3:0] to a logic 0. The SC68C652B compares each incoming receive character with Xoff2 data. If a match exists, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate detection of a special character. Although Table 9 “SC68C652B internal registers” shows each X-register with eight bits of character information, the actual number of bits is dependent on the programmed word length. Line Control Register bits LCR[1:0] define the number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length selected by LCR[1:0] also determine the number of bits that will be used for the special character comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive character. 6.7 Hardware/software and time-out interrupts The interrupts are enabled by IER[3:0]. Care must be taken when handling these interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC68C652B will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to continuing operations. The ISR register provides the current singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have lowest interrupt priority. A condition can exist where a higher priority interrupt may mask the lower priority CTS/RTS interrupt(s). Only after servicing the higher pending interrupt will the lower priority CTS/RTS interrupt(s) be reflected in the status register. Servicing the interrupt without investigating further interrupt conditions can result in data errors. When two interrupt conditions have the same priority, it is important to service these interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case, the SC68C652B FIFO may hold more characters than the programmed trigger level. Following the removal of a data byte, the user should re-check LSR[0] for additional characters. A Receive Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the center of each stop bit received or each time the receive holding register (RHR) is read. The actual time-out value is 4 character time, including data information length, start bit, parity bit, and the size of stop bit, that is, 1×, 1.5×, or 2× bit times. SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 11 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 6.8 Programmable baud rate generator The SC68C652B supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s. The SC68C652B can support a standard data rate of 921.6 kbit/s. A single baud rate generator is provided for the transmitter and receiver, allowing independent transmit/receive channel control. The programmable baud rate generator is capable of operating with a frequency of up to 80 MHz. To obtain maximum data rate, it is necessary to use full rail swing on the clock input. The SC68C652B can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates (see Table 6). The generator divides the input 16× clock by any divisor from 1 to (216 − 1). The SC68C652B divides the basic external clock by 16. The basic 16× clock provides table rates to support standard and custom applications using the same system design. The rate table is configured via the DLL and DLM internal register functions. Customized baud rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator. Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 6 shows the selectable baud rate table available when using a 1.8432 MHz external clock input. XTAL1 XTAL2 X1 1.8432 MHz C1 22 pF C2 33 pF 002aab325 Fig 3. Crystal oscillator connection SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 12 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder Baud rate generator programming table using a 1.8432 MHz clock Output 16× clock divisor (decimal) 2304 1536 1047 768 384 192 96 48 32 24 16 12 6 3 2 1 Output 16× clock divisor (HEX) 900 600 417 300 180 C0 60 30 20 18 10 0C 06 03 02 01 DLM program value (HEX) 09 06 04 03 01 00 00 00 00 00 00 00 00 00 00 00 DLL program value (HEX) 00 00 17 00 80 C0 60 30 20 18 10 0C 06 03 02 01 Table 6. Output baud rate 50 75 110 150 300 600 1200 2400 3600 4800 7200 9600 19.2 k 38.4 k 57.6 k 115.2 k 6.9 DMA operation The SC68C652B FIFO trigger level provides additional flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDYn and TXRDYn output pins. Table 7 and Table 8 show this. Table 7. Effect of DMA mode on state of RXRDYn pin DMA mode 0-to-1 transition when FIFO empties 1-to-0 transition when FIFO reaches trigger level, or time-out occurs Non-DMA mode 1 = FIFO empty 0 = at least 1 byte in FIFO Table 8. Effect of DMA mode on state of TXRDYn pin DMA mode 0-to-1 transition when FIFO becomes full 1-to-0 transition when FIFO goes below trigger level Non-DMA mode 1 = at least 1 byte in FIFO 0 = FIFO empty 6.10 Loopback mode The internal loopback capability allows on-board diagnostics. In the loopback mode, the normal modem interface pins are disconnected and reconfigured for loopback internally (see Figure 4). MCR[3:0] register bits are used for controlling loopback diagnostic testing. In the loopback mode, the transmitter output pin (TXn) and the receiver input pin (RXn) are disconnected from their associated interface pins, and instead are connected together internally. The CTSn, DSRn, CDn, and RIn pins are disconnected from their normal modem control inputs pins, and instead are connected internally to MCR[1] RTS, SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 13 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder MCR[0] DTR, MCR[3] (OP2) and MCR[2] (OP1). Loopback test data is entered into the transmit holding register via the user data bus interface, D0 to D7. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loopback connection. The receive UART converts the serial data back into parallel data that is then made available at the user data interface D0 to D7. The user optionally compares the received data to the initial transmitted data for verifying error-free operation of the UART transmit/receive circuits. In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. SC68C652B TRANSMIT FIFO REGISTERS D0 to D7 R/W RESET DATA BUS AND CONTROL LOGIC FLOW CONTROL LOGIC IR ENCODER TRANSMIT SHIFT REGISTER TXA, TXB INTERCONNECT BUS LINES AND CONTROL SIGNALS RECEIVE FIFO REGISTERS RECEIVE SHIFT REGISTER MCR[4] = 1 RXA, RXB A0 to A3 CS REGISTER SELECT LOGIC FLOW CONTROL LOGIC IR DECODER RTSA, RTSB CTSA, CTSB DTRA, DTRB MODEM CONTROL LOGIC IRQ TXRDYA, TXRDYB RXRDYA, RXRDYB INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR DSRA, DSRB (OP1A, OP1B) RIA, RIB (OP2A, OP2B) CDA, CDB 002aab326 XTAL1 XTAL2 Fig 4. Internal loopback mode diagram SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 14 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7. Register descriptions Table 9 details the assigned bit functions for the SC68C652B internal registers. The assigned bit functions are more fully defined in Section 7.1 through Section 7.11. Table 9. SC68C652B internal registers Bit 6 bit 6 bit 6 RTS interrupt [3] A2 A1 A0 Register Default[1] Bit 7 General register 0 0 0 0 0 0 0 0 1 set[2] XX XX 00 bit 7 bit 7 CTS interrupt [3] Bit 5 bit 5 bit 5 Xoff interrupt [3] Bit 4 bit 4 bit 4 Sleep mode[3] Bit 3 bit 3 bit 3 modem status interrupt RX DMA mode select INT priority bit 2 parity enable Bit 2 bit 2 bit 2 receive line status interrupt XMIT FIFO reset INT priority bit 1 Bit 1 bit 1 bit 1 transmit holding register interrupt RCVR FIFO reset INT priority bit 0 Bit 0 bit 0 bit 0 receive holding register FIFOs enable INT status word length bit 0 DTR receive data ready ∆CTS bit 0 bit 0 bit 8 Cont-0 TX, RX Control RHR THR IER 0 1 0 FCR 00 RCVR trigger (MSB) FIFOs enabled divisor latch enable clock select[3] FIFO data error CD bit 7 bit 7 bit 15 AutoCTS RCVR trigger (LSB) FIFOs enabled TX trigger (MSB)[3] INT priority bit 4 TX trigger (LSB)[3] INT priority bit 3 0 1 0 ISR 01 0 1 1 LCR 00 set break set parity even parity IRDA enable 0 stop bits word length bit 1 (OP1) parity error ∆RI bit 2 bit 2 bit 10 Cont-2 TX, RX Control RTS overrun error ∆DSR bit 1 bit 1 bit 9 Cont-1 TX, RX Control 1 1 0 0 0 1 MCR LSR 00 60 loopback OP2 control break interrupt CTS bit 4 bit 4 bit 12 framing error ∆CD bit 3 bit 3 bit 11 THR and THR TSR empty empty RI bit 6 bit 6 bit 14 AutoRTS DSR bit 5 bit 5 bit 13 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 MSR SPR DLL DLM EFR X0 FF XX XX set[5] 00 Special register set[4] Enhanced register Cont-3 Special Enable character IER[4:7], TX, RX detect ISR[4:5], Control FCR[4:5], MCR[5:7] bit 5 bit 13 bit 5 bit 13 bit 4 bit 12 bit 4 bit 12 bit 3 bit 11 bit 3 bit 11 1 1 1 1 [1] [2] [3] [4] [5] 0 0 1 1 0 1 0 1 Xon1 Xon2 Xoff1 Xoff2 00 00 00 00 bit 7 bit 15 bit 7 bit 15 bit 6 bit 14 bit 6 bit 14 bit 2 bit 10 bit 2 bit 10 bit 1 bit 9 bit 1 bit 9 bit 0 bit 8 bit 0 bit 8 The value shown in represents the register’s initialized hexadecimal value; X = not applicable. Accessible only when LCR[7] is logic 0. These bits are only accessible when EFR[4] is set. Baud rate registers accessible only when LCR[7] is logic 1. Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to ‘BFh’. © NXP B.V. 2009. All rights reserved. SC68C652B_2 Product data sheet Rev. 02 — 2 November 2009 15 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR) The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D[7:0]) to the TSR and UART via the THR, providing that the THR is empty. The THR empty flag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR. Note that a write operation can be performed when the THR empty flag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR empty). The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a Receive Serial Shift Register (RSR). Receive data is removed from the SC68C652B and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16× clock rate. After 71⁄2 clocks, the start bit time should be shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. Receiver status codes will be posted in the LSR. 7.2 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the IRQ output pin. Table 10. Bit 7 Interrupt Enable Register bits description Symbol IER[7] Description CTS interrupt logic 0 = disable the CTS interrupt (normal default condition) logic 1 = enable the CTS interrupt. The SC68C652B issues an interrupt when the CTSn pin transitions from a logic 0 to a logic 1. 6 IER[6] RTS interrupt logic 0 = disable the RTS interrupt (normal default condition) logic 1 = enable the RTS interrupt. The SC68C652B issues an interrupt when the RTSn pin transitions from a logic 0 to a logic 1. 5 IER[5] Xoff interrupt logic 0 = disable the software flow control, receive Xoff interrupt (normal default condition) logic 1 = enable the software flow control, receive Xoff interrupt 4 IER[4] Sleep mode logic 0 = disable Sleep mode (normal default condition) logic 1 = enable Sleep mode 3 IER[3] Modem Status Interrupt. This interrupt will be issued whenever there is a modem status change as reflected in MSR[3:0]. logic 0 = disable the modem status register interrupt (normal default condition) logic 1 = enable the modem status register interrupt SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 16 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder Interrupt Enable Register bits description …continued Symbol IER[2] Description Receive Line Status interrupt. This interrupt will be issued whenever a receive data error condition exists as reflected in LSR[4:1]. logic 0 = disable the receiver line status interrupt (normal default condition) logic 1 = enable the receiver line status interrupt Table 10. Bit 2 1 IER[1] Transmit Holding Register interrupt. In the 16C450 mode, this interrupt will be issued whenever the THR is empty, and is associated with LSR[5]. In the FIFO modes, this interrupt will be issued whenever the FIFO is empty. logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt (normal default condition) logic 1 = enable the TXRDY (ISR level 3) interrupt 0 IER[0] Receive Holding Register. In the 16C450 mode, this interrupt will be issued when the RHR has data, or is cleared when the RHR is empty. In the FIFO mode, this interrupt will be issued when the FIFO has reached the programmed trigger level or is cleared when the FIFO drops below the trigger level. logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal default condition) logic 1 = enable the RXRDY (ISR level 2) interrupt 7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU when the receive FIFO has reached the programmed trigger level. It will be cleared when the receive FIFO drops below the programmed trigger level. • Receive FIFO status will also be reflected in the user accessible ISR register when the receive FIFO trigger level is reached. Both the ISR register receive status bit and the interrupt will be cleared when the FIFO drops below the trigger level. • The receive data ready bit (LSR[0]) is set as soon as a character is transferred from the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty. • When the Transmit FIFO and interrupts are enabled, an interrupt is generated when the transmit FIFO is empty due to the unloading of the data by the TSR and UART for transmission via the transmission media. The interrupt is cleared either by reading the ISR register, or by loading the THR with new data characters. SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 17 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0:3] enables the SC68C652B in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for transmit and/or receive data status. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). • • • • • LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO. LSR[4:1] will provide the type of receive errors, or a receive break, if encountered. LSR[5] will indicate when the transmit FIFO is empty. LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty. LSR[7] will show if any FIFO data errors occurred. 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode. 7.3.1 DMA mode 7.3.1.1 Mode 0 (FCR bit 3 = 0) Set and enable the interrupt for each single transmit or receive operation, and is similar to the 16C450 mode. Transmit Ready pin (TXRDYn) will go to a logic 0 whenever the FIFO (THR, if FIFO is not enabled) is empty. Receive Ready pin (RXRDYn) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with a character. 7.3.1.2 Mode 1 (FCR bit 3 = 1) Set and enable the interrupt in a block mode operation. The transmit interrupt is set when the transmit FIFO is below the programmed trigger level. The receive interrupt is set when the receive FIFO fills to the programmed trigger level. However, the FIFO continues to fill regardless of the programmed level until the FIFO is full. RXRDYn remains a logic 0 as long as the FIFO fill level is above the programmed trigger level. SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 18 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.3.2 FIFO mode Table 11. Bit 7:6 FIFO Control Register bits description Symbol FCR[7:6] Description RCVR trigger. These bits are used to set the trigger level for the receive FIFO interrupt. An interrupt is generated when the number of characters in the FIFO equals the programmed trigger level. However, the FIFO will continue to be loaded until it is full. Refer to Table 12. 5:4 FCR[5:4] TX trigger. Logic 0 or cleared is the default condition; TX trigger level = 16. These bits are used to set the trigger level for the transmit FIFO interrupt. The SC68C652B will issue a transmit empty interrupt when the number of characters in FIFO drops below the selected trigger level. Refer to Table 13. 3 FCR[3] DMA mode select logic 0 = set DMA mode ‘0’ (normal default condition) logic 1 = set DMA mode ‘1’ Transmit operation in mode ‘0’: When the SC68C652B is in the 16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no characters in the transmit FIFO or transmit holding register, the TXRDYn pin will be a logic 0. Once active, the TXRDYn pin will go to a logic 1 after the first character is loaded into the transmit holding register. Receive operation in mode ‘0’: When the SC68C652B is in 16C450 mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is at least one character in the receive FIFO, the RXRDYn pin will be a logic 0. Once active, the RXRDYn pin will go to a logic 1 when there are no more characters in the receiver. Transmit operation in mode ‘1’: When the SC68C652B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYn pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 when the trigger level has been reached. Receive operation in mode ‘1’: When the SC68C652B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached, or a Receive Time-Out has occurred, the RXRDYn pin will go to a logic 0. Once activated, it will go to a logic 1 after there are no more characters in the FIFO. 2 FCR[2] XMIT FIFO reset logic 0 = no FIFO transmit reset (normal default condition) logic 1 = clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. 1 FCR[1] RCVR FIFO reset logic 0 = no FIFO receive reset (normal default condition). logic 1 = clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. 0 FCR[0] FIFO enable logic 0 = disable the transmit and receive FIFO (normal default condition) logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’ when other FCR bits are written to, or they will not be programmed. SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 19 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder RCVR trigger levels FCR[6] 0 1 0 1 Receive FIFO trigger level (bytes) 8 16 24 28 Table 12. FCR[7] 0 0 1 1 Table 13. FCR[5] 0 0 1 1 TX FIFO trigger levels FCR[4] 0 1 0 1 TX FIFO trigger level (bytes) 16 8 24 30 SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 20 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.4 Interrupt Status Register (ISR) The SC68C652B provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced. A lower level interrupt may be seen after servicing the higher level interrupt and re-reading the interrupt status bits. Table 14 “Interrupt source” shows the data values (bit 0 to bit 5) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels. Table 14. Interrupt source Priority ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt level 1 2 2 3 4 5 6 Table 15. Bit 7:6 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 LSR (Receiver Line Status Register) RXRDY (Received Data Ready) RXRDY (Receive Data time-out) TXRDY (Transmitter Holding Register Empty) MSR (Modem Status Register) RXRDY (received Xoff signal)/ special character CTS, RTS change-of-state Interrupt Status Register bits description Symbol ISR[7:6] Description FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being used in the 16C450 mode. They are set to a logic 1 when the FIFOs are enabled in the SC68C652B mode. logic 0 or cleared = default condition INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1. ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5] indicates that CTS, RTS have been generated. Note that once set to a logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received. logic 0 or cleared = default condition INT priority bits 2:0. These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see Table 14). logic 0 or cleared = default condition INT status logic 0 = an interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine logic 1 = no interrupt pending (normal default condition) 5:4 ISR[5:4] 3:1 ISR[3:1] 0 ISR[0] SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 21 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 16. Bit 7 Line Control Register bits description Symbol LCR[7] Description Divisor latch enable. The internal baud rate counter latch and Enhanced Feature mode enable. logic 0 = divisor latch disabled (normal default condition) logic 1 = divisor latch enabled 6 LCR[6] Set break. When enabled, the Break control bit causes a break condition to be transmitted (the TXn output pin is forced to a logic 0 state). This condition exists until disabled by setting LCR[6] to a logic 0. logic 0 = no break condition (normal default condition) logic 1 = forces the transmitter output pin (TXn) to a logic 0 for alerting the remote receiver to a line break condition 5:3 2 LCR[5:3] LCR[2] Set parity; even parity; parity enable. Programs the parity conditions (see Table 17). Stop bits. The length of stop bit is specified by this bit in conjunction with the programmed word length (see Table 18). logic 0 or cleared = default condition 1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received (see Table 19). logic 0 or cleared = default condition Table 17. LCR[5] X X 0 0 1 Table 18. LCR[2] 0 1 1 Table 19. LCR[1] 0 0 1 1 SC68C652B_2 LCR[5:3] parity selection LCR[4] X 0 1 0 1 LCR[3] 0 1 1 1 1 Parity selection no parity odd parity even parity forced parity ‘1’ forced parity ‘0’ LCR[2] stop bit length Word length 5, 6, 7, 8 5 6, 7, 8 Stop bit length (bit times) 1 11⁄2 2 LCR[1:0] word length LCR[0] 0 1 0 1 Word length 5 6 7 8 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 22 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 20. Bit 7 Modem Control Register bits description Symbol MCR[7] Description Clock select logic 0 = divide-by-1 clock input logic 1 = divide-by-4 clock input 6 MCR[6] IR enable (see Figure 16) logic 0 = enable the standard modem receive and transmit input/output interface (normal default condition) logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TXn/RXn output/inputs are routed to the infrared encoder/decoder. The data input and output levels will conform to the IrDA infrared interface requirement. As such, while in this mode, the infrared TXn output will be a logic 0 during idle data conditions. 5 4 MCR[5] MCR[4] reserved; set to ‘0’ Loopback. Enable the local loopback mode (diagnostics). In this mode the transmitter output (TXn) and the receiver input (RXn), CTSn, DSRn, CDn, and RIn pins are disconnected from the SC68C652B I/O pins. Internally the modem data and control pins are connected into a loopback data configuration (see Figure 4). In this mode, the receiver and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts’ sources are switched to the lower four bits of the Modem Control. Interrupts continue to be controlled by the IER register. logic 0 = disable loopback mode (normal default condition) logic 1 = enable local loopback mode (diagnostics) 3 MCR[3] OP2 control logic 0 = forces OP2n output pin to HIGH state logic 1 = forces OP2n output pin to LOW state. In loopback mode, controls MSR[7]. 2 MCR[2] (OP1). OP1A/OP1B are not available as an external signal in the SC68C652B. This bit is instead used in the loopback mode only. In the loopback mode, this bit is used to write the state of the modem RIn pin interface signal. RTS logic 0 = force RTSn output pin to a logic 1 (normal default condition) logic 1 = force RTSn output pin to a logic 0 0 MCR[0] DTR logic 0 = force DTRn output pin to a logic 1 (normal default condition) logic 1 = force DTRn output pin to a logic 0 1 MCR[1] SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 23 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC68C652B and the CPU. Table 21. Bit 7 Line Status Register bits description Description FIFO data error logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current FIFO data. This bit is cleared when there are no remaining error flags associated with the remaining data in the FIFO. 6 LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. It is reset to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode, this bit is set to ‘1’ whenever the transmit FIFO and transmit shift register are both empty. THR empty. This bit is the Transmit Holding Register Empty indicator. This bit indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to CPU when the THR interrupt enable is set. The THR bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. The bit is reset to a logic 0 concurrently with the loading of the transmitter holding register by the CPU. In the FIFO mode, this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO. Break interrupt logic 0 = no break condition (normal default condition) logic 1 = the receiver received a break signal (RXn pin was a logic 0 for one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. 3 LSR[3] Framing error logic 0 = no framing error (normal default condition) logic 1 = framing error. The receive character did not have a valid stop bit(s). In the FIFO mode, this error is associated with the character at the top of the FIFO. 2 LSR[2] Parity error logic 0 = no parity error (normal default condition logic 1 = parity error. The receive character does not have correct parity information and is suspect. In the FIFO mode, this error is associated with the character at the top of the FIFO. 1 LSR[1] Overrun error logic 0 = no overrun error (normal default condition) logic 1 = overrun error. A data overrun error occurred in the receive shift register. This happens when additional data arrives while the FIFO is full. In this case, the previous data in the shift register is overwritten. Note that under this condition, the data byte in the receive shift register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error. 0 LSR[0] Receive data ready logic 0 = no data in receive holding register or FIFO (normal default condition). logic 1 = data has been received and is saved in the receive holding register or FIFO. Symbol LSR[7] 5 LSR[5] 4 LSR[4] SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 24 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC68C652B is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register. Table 22. Bit 7 6 5 4 3 Modem Status Register bits description Description CD. During normal operation, this bit is the complement of the CDn input pin. Reading this bit in the loopback mode produces the state of MCR[3] (OP2). RI. During normal operation, this bit is the complement of the RIn input pin. Reading this bit in the loopback mode produces the state of MCR[2] (OP1). DSR. During normal operation, this bit is the complement of the DSRn input pin. During the loopback mode, this bit is equivalent to the state of MCR[0]. CTS. During normal operation, this bit is the complement of the CTSn input pin. During the loopback mode, this bit is equivalent to the state of MCR[1]. ∆CD [1] logic 0 = no change of state on CDn pin (normal default condition) logic 1 = the CDn input pin to the SC68C652B has changed state since the last time it was read. A modem Status Interrupt will be generated. 2 MSR[2] ∆RI [1] logic 0 = no change of state on RIn pin (normal default condition) logic 1 = the RIn input pin to the SC68C652B has changed from a logic 0 to a logic 1. A modem Status Interrupt will be generated. 1 MSR[1] ∆DSR [1] logic 0 = no change of state on DSRn pin (normal default condition) logic 1 = the DSRn input pin to the SC68C652B has changed state since the last time it was read. A modem Status Interrupt will be generated. 0 MSR[0] ∆CTS [1] logic 0 = no change of state on CTSn pin (normal default condition) logic 1 = the CTSn input pin to the SC68C652B has changed state since the last time it was read. A modem Status Interrupt will be generated. [1] Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated. Symbol MSR[7] MSR[6] MSR[5] MSR[4] MSR[3] 7.9 Scratchpad Register (SPR) The SC68C652B provides a temporary data register to store 8 bits of user information. SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 25 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.10 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential numbers. Table 23. Bit 7 Enhanced Feature Register bits description Description Automatic CTS flow control logic 0 = automatic CTS flow control is disabled (normal default condition) logic 1 = enable automatic CTS flow control. Transmission will stop when CTSn goes to a logic 1. Transmission will resume when the CTSn pin returns to a logic 0. 6 EFR[6] Automatic RTS flow control. Automatic RTS may be used for hardware flow control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTSn will go to a logic 1 at the next trigger level. RTSn will return to a logic 0 when data is unloaded below the next lower trigger level (programmed trigger level 1). The state of this register bit changes with the status of the hardware flow control. RTSn functions normally when hardware flow control is disabled. logic 0 = automatic RTS flow control is disabled (normal default condition) logic 1 = enable automatic RTS flow control. 5 EFR[5] Special character detect logic 0 = Special character detect disabled (normal default condition) logic 1 = Special character detect enabled. The SC68C652B compares each incoming receive character with Xoff2 data. If a match exists, the received data will be transferred to FIFO and ISR[4] will be set to indicate detection of special character. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. When this feature is enabled, the normal software flow control must be disabled (EFR[3:0] must be set to a logic 0). 4 EFR[4] Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and MCR[7:5] can be modified and latched. After modifying any bits in the enhanced registers, EFR[4] can be set to a logic 0 to latch the new values. This feature prevents existing software from altering or overwriting the SC68C652B enhanced functions. logic 0 = disable/latch enhanced features. IER[7:4], ISR[5:4], FCR[5:4], and MCR[7:5] are saved to retain the user settings, then IER[7:4] ISR[5:4], FCR[5:4], and MCR[7:5] are set to a logic 0 to be compatible with SC16C554 mode. (Normal default condition.) logic 1 = enables the enhanced functions. When this bit is set to a logic 1, all enhanced features of the SC68C652B are enabled and user settings stored during a reset will be restored. 3:0 EFR[3:0] Cont-3:0 TX, RX control. Logic 0 or cleared is the default condition. Combinations of software flow control can be selected by programming these bits. See Table 24. Symbol EFR[7] SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 26 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder Software flow control functions[1] Cont-2 0 0 1 1 X X X 0 1 1 Cont-1 X X X X 0 1 0 1 1 1 Cont-0 X X X X 0 0 1 1 1 1 TX, RX software flow controls no transmit flow control transmit Xon1/Xoff1 transmit Xon2/Xoff2 transmit Xon1 and Xon2/Xoff1 and Xoff2 no receive flow control receiver compares Xon1/Xoff1 receiver compares Xon2/Xoff2 transmit Xon1/Xoff1 receiver compares Xon1 and Xon2/Xoff1 and Xoff2 transmit Xon2/Xoff2 receiver compares Xon1 and Xon2/Xoff1 and Xoff2 transmit Xon1 and Xon2/Xoff1 and Xoff2 receiver compares Xon1 and Xon2/Xoff1 and Xoff2 Table 24. Cont-3 0 1 0 1 X X X 1 0 1 [1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer. 7.11 SC68C652B external reset condition Table 25. Register IER FCR ISR LCR MCR LSR MSR SPR DLL DLM Table 26. Output TXA, TXB OP2A, OP2B RTSA, RTSB DTRA, DTRB IRQ Reset state for registers Reset state IER[7:0] = 0 FCR[7:0] = 0 ISR[7:1] = 0; ISR[0] = 1 LCR[7:0] = 0 MCR[7:0] = 0 LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0 MSR[7:4] = input signals; MSR[3:0] = 0 SFR[7:0] = 1 DLL[7:0] = X DLM[7:0] = X Reset state for outputs Reset state logic 1 logic 1 logic 1 logic 1 3-state condition SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 27 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 8. Limiting values Table 27. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC Vn Tamb Tstg Ptot/pack Parameter supply voltage voltage on any other pin ambient temperature storage temperature total power dissipation per package at D7 to D0 pins at input only pins operating Conditions Min GND − 0.3 GND − 0.3 −40 −65 Max 7 VCC + 0.3 5.3 +85 +150 500 Unit V V V °C °C mW SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 28 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 9. Static characteristics Table 28. Static characteristics Tamb = −40 °C to +85 °C; tolerance of VCC ± 10 %, unless otherwise specified. Symbol VIL(clk) VIH(clk) VIL VIH VOL Parameter clock LOW-level input voltage clock HIGH-level input voltage LOW-level input voltage HIGH-level input voltage LOW-level output voltage except X1 clock except X1 clock on all outputs IOL = 5 mA (data bus) IOL = 4 mA (other outputs) IOL = 2 mA (data bus) IOL = 1.6 mA (other outputs) VOH HIGH-level output voltage IOH = −5 mA (data bus) IOH = −1 mA (other outputs) IOH = −800 µA (data bus) IOH = −400 µA (other outputs) ILIL IL(clk) ICC ICC(sleep) Ci [1] [1] Conditions VCC = 2.5 V Min −0.3 1.8 −0.3 1.6 1.85 1.85 Max 0.45 VCC 0.65 0.4 0.4 ±10 ±30 3.5 200 5 VCC = 3.3 V Min −0.3 2.4 −0.3 2.0 2.0 Max 0.6 VCC 0.8 0.4 ±10 ±30 4.5 200 5 VCC = 5.0 V Min −0.5 3.0 −0.5 2.2 2.4 Max 0.6 VCC 0.8 0.4 ±10 ±30 4.5 200 5 Unit V V V V V V V V V V V V µA µA mA µA pF LOW-level input leakage current clock leakage current supply current sleep mode supply current input capacitance Except XTAL2; VOL = 1 V typical. SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 29 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 10. Dynamic characteristics Table 29. Dynamic characteristics Tamb = −40 °C to +85 °C; tolerance of VCC ± 10 %, unless specified otherwise. Symbol td1 td2 td3 td4 td6 td7 td8 td9 td10 td11 td12 td13 td14 td15 td16 td17 td18 th2 th3 th4 tWH tWL fXTAL t(RESET) tsu1 tsu2 tw1 [1] [2] [3] [4] Parameter R/W to chip select read cycle delay delay from CS to data data disable time write cycle delay delay from write to output delay to set interrupt from modem input delay to reset interrupt from read delay from stop to set interrupt delay from read to reset interrupt delay from start to set interrupt delay from write to transmit start delay from write to reset interrupt delay from stop to set RXRDY delay from read to reset RXRDY delay from write to set TXRDY delay from start to reset TXRDY R/W hold time from CS data hold time address hold time pulse width HIGH pulse width LOW clock speed RESET pulse width address set-up time data set-up time CS strobe width Conditions VCC = 2.5 V Min 10 Max 77 15 100 100 100 1TRCLK[1] 100 100 [1] VCC = 3.3 V and 5 V Min 10 20 25 8TRCLK 10 15 15 6 6 200 10 16 30 [1] Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns Max 26 15 33 24 24 1TRCLK[1] 29 100 24TRCLK[1] 70 1TRCLK[1] 75 70 16TRCLK[1] 80 - 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 20 25 8TRCLK 10 15 15 10 10 [2][3] [4] 24TRCLK[1] 100 1TRCLK[1] 100 100 16TRCLK[1] 48 - 200 10 16 77 RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches. Applies to external clock; crystal oscillator max 24 MHz. 1 f XTAL = -------------t w ( clk ) Reset pulse must happen when CS is inactive. SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 30 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 10.1 Timing diagrams A0 to A3 tsu1 CS td1 valid address tw1 th4 valid address td2 td4 R/W td3 D0 to D7 valid data valid data 002aab087 Fig 5. General read timing A0 to A3 tsu1 valid address tw1 th4 valid address CS td1 th2 td6 R/W tsu2 th3 D0 to D7 valid data valid data 002aab088 Fig 6. General write timing SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 31 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder CS (write)(1) active td7 RTSA, RTSB DTRA, DTRB change of state change of state CDA, CDB CTSA, CTSB DSRA, DSRB td8 change of state td8 change of state IRQ active td9 active active CS (read)(2) active active td8 active RIA, RIB change of state 002aab089 (1) CS timing during a write cycle. See Figure 6. (2) CS timing during a read cycle. See Figure 5. Fig 7. Modem input/output timing tWL external clock tWH tw(clk) 002aac357 1 f XTAL = -------------t w ( clk ) Fig 8. External clock timing SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 32 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder Start bit data bits (0 to 7) D0 D1 D2 5 data bits 6 data bits 7 data bits D3 D4 D5 D6 D7 parity bit Stop bit next data Start bit RXA, RXB td10 active td11 IRQ CS (read) active 16 baud rate clock 002aab090 Fig 9. Receive timing Start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit Stop bit next data Start bit RXA, RXB td15 RXRDYA, RXRDYB active data ready td16 CS (read) active 002aab091 Fig 10. Receive ready timing in non-FIFO mode SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 33 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder Start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit Stop bit RXA, RXB first byte that reaches the trigger level td15 RXRDYA, RXRDYB active data ready td16 CS (read) active 002aab092 Fig 11. Receive ready timing in FIFO mode Start bit data bits (0 to 7) D0 D1 D2 5 data bits 6 data bits 7 data bits active transmitter ready D3 D4 D5 D6 D7 parity bit Stop bit next data Start bit TXA, TXB IRQ td12 td13 td14 active CS (write) active 16 baud rate clock 002aab093 Fig 12. Transmit timing SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 34 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder Start bit TXA, TXB data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit Stop bit next data Start bit CS (write) active D0 to D7 byte #1 td18 td17 TXRDYA, TXRDYB active transmitter ready transmitter not ready 002aab094 Fig 13. Transmit ready timing in non-FIFO mode Start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit Stop bit TXA, TXB 5 data bits 6 data bits 7 data bits CS (write) active td18 D0 to D7 byte #32 td17 TXRDYA, TXRDYB trigger lead 002aab095 Fig 14. Transmit ready timing in FIFO mode SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 35 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder UART frame start data bits stop TX data 0 1 0 1 0 0 1 1 0 1 IrDA TX data 1/ bit time 2 3/ bit time 16 bit time 002aaa212 Fig 15. Infrared transmit timing IrDA RX data bit time RX data 0 1 0 1 0 0 to 1 16× clock delay 0 1 1 0 1 start data bits stop UART frame 002aaa213 Fig 16. Infrared receive timing SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 36 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 11. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 37 25 24 ZE A e E HE A A2 A1 (A 3) θ Lp L detail X wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 θ 7 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 17. Package outline SOT313-2 (LQFP48) SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 37 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 12.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 12.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 38 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 18) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 30 and 31 Table 30. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 31. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 18. SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 39 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 18. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 13. Abbreviations Table 32. Acronym CPU DMA FIFO IrDA ISDN LSB MSB UART Abbreviations Description Central Processing Unit Direct Memory Access First In, First Out Infrared Data Association Integrated Service Digital Network Least Significant Bit Most Significant Bit Universal Asynchronous Receiver and Transmitter SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 40 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 14. Revision history Table 33. Revision history Release date 20091102 Data sheet status Product data sheet Change notice Supersedes SC68C652B_1 Document ID SC68C652B_2 Modifications: • • • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Data sheet title modified from “... and Motorola µP interface” to “... and 68 mode µP interface” Section 2 “Features”, 3rd bullet item re-written; added Footnote 1 Table 10 “Interrupt Enable Register bits description”, description of bit 0: changed from “In the 68C450 mode” to “In the 16C450 mode” Table 11 “FIFO Control Register bits description”, description of bit 3: changed from “in the 68C450 mode” to “in the 16C450 mode” (in 2 places) Table 27 “Limiting values”: – Symbol Vn split to show 2 separate conditions: “at D7 to D0 pins” and “at input only pins” – Symbol “Ptot(pack)” changed to “Ptot/pack” – Parameter for Tamb changed from “operating temperature” to “ambient temperature”; “operating” moved to Conditions column • Table 28 “Static characteristics”: – Descriptive line below table title changed from “VCC = 2.5 V, 3.3 V ± 10 % or 5 V ± 10 %” to “tolerance of VCC ± 10 %” – Symbol/parameter changed from “VIL(CK), LOW-level clock input voltage” to “VIL(clk), clock LOW-level input voltage” – Symbol/parameter changed from “VIH(CK), HIGH-level clock input voltage” to “VIH(clk), clock HIGH-level input voltage” – Symbol changed from “ICL” to “IL(clk)” – Parameter for ICC(sleep) changed from “sleep current” to “sleep mode supply current” • Table 29 “Dynamic characteristics”: – Descriptive line below table title changed from “VCC = 2.5 V, 3.3 V ± 10 % or 5 V ± 10 %” to “tolerance of VCC ± 10 %” – Symbol/parameter “t1w, t2w, clock cycle period” is split into “tWH, pulse width HIGH” and “tWL, pulse width LOW” – Table note [3]: denominator in equation changed from “t3w” to “tw(clk)” – added Table note [4] and its reference at t(RESET) • Figure 8 “External clock timing”: – “tw2” changed to “tWL” – “tw1” changed to “tWH” – “tw3” changed to “tw(clk)” • SC68C652B_1 (9397 750 14657) Updated soldering information Product data sheet - 20050425 SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 41 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 42 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 7 7.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 8 UART A-B functions . . . . . . . . . . . . . . . . . . . . . 8 Internal registers. . . . . . . . . . . . . . . . . . . . . . . . 9 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hardware flow control . . . . . . . . . . . . . . . . . . . 10 Software flow control . . . . . . . . . . . . . . . . . . . 10 Special feature software flow control . . . . . . . 11 Hardware/software and time-out interrupts. . . 11 Programmable baud rate generator . . . . . . . . 12 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 13 Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 13 Register descriptions . . . . . . . . . . . . . . . . . . . 15 Transmit Holding Register (THR) and Receive Holding Register (RHR) . . . . . . . . . . 16 7.2 Interrupt Enable Register (IER) . . . . . . . . . . . 16 7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation. . . . . . . . . . . . . . . . . . . . . . . . 17 7.2.2 IER versus Receive/Transmit FIFO polled mode operation. . . . . . . . . . . . . . . . . . . . . . . . 18 7.3 FIFO Control Register (FCR) . . . . . . . . . . . . . 18 7.3.1 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.3.1.1 Mode 0 (FCR bit 3 = 0) . . . . . . . . . . . . . . . . . . 18 7.3.1.2 Mode 1 (FCR bit 3 = 1) . . . . . . . . . . . . . . . . . . 18 7.3.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.4 Interrupt Status Register (ISR) . . . . . . . . . . . . 21 7.5 Line Control Register (LCR) . . . . . . . . . . . . . . 22 7.6 Modem Control Register (MCR) . . . . . . . . . . . 23 7.7 Line Status Register (LSR) . . . . . . . . . . . . . . . 24 7.8 Modem Status Register (MSR). . . . . . . . . . . . 25 7.9 Scratchpad Register (SPR) . . . . . . . . . . . . . . 25 7.10 Enhanced Feature Register (EFR) . . . . . . . . . 26 7.11 SC68C652B external reset condition . . . . . . . 27 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28 9 Static characteristics. . . . . . . . . . . . . . . . . . . . 29 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 30 10.1 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 31 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 37 12 Soldering of SMD packages . . . . . . . . . . . . . . 38 12.1 Introduction to soldering . . . . . . . . . . . . . . . . . 38 12.2 12.3 12.4 13 14 15 15.1 15.2 15.3 15.4 16 17 Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 38 39 40 41 42 42 42 42 42 42 43 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 November 2009 Document identifier: SC68C652B_2