SE97BTP

SE97B DDR memory module temp sensor with integrated SPD Rev. 01 — 27 January 2010 Product data sheet 1. General description Meets JEDEC Specification 42.4 TSE2002B1, 3 Jun 2009. The NXP Semiconductors SE97B measures temperature from −40 °C to +125 °C with JEDEC Grade B ±1 °C maximum accuracy between +75 °C and +95 °C critical zone and also provide 256 bytes of EEPROM memory communicating via the I2C-bus/SMBus. It is typically mounted on a DDR3 Dual In-Line Memory Module (DIMM) measuring the DRAM temperature in accordance with the new JEDEC (JC-42.4) Mobile Platform Memory Module Temperature Sensor Component specification and also replacing the Serial Presence Detect (SPD) which is used to store memory module and vendor information. The SE97B thermal sensor and EEPROM operates over the VDD range of 3.0 V to 3.6 V. The TS consists of a ΔΣ Analog to Digital Converter (ADC) that monitors and updates its own temperature readings 10 times per second, converts the reading to a digital data, and latches them into the data temperature register. User-programmable registers, the specification of upper/lower alarm and critical temperature trip points, EVENT output control, and temperature shutdown, provide flexibility for DIMM temperature-sensing applications. When the temperature changes beyond the specified boundary limits, the SE97B outputs an EVENT signal using an open-drain output that can be pulled up between 0.9 V and 3.6 V. The user has the option of setting the EVENT output signal polarity as either an active LOW or active HIGH comparator output for thermostat operation, or as a temperature event interrupt output for microprocessor-based systems. The EVENT output can also be configured as only a critical temperature output. The EEPROM is designed specifically for DRAM DIMMs SPD. The lower 128 bytes (address 00h to 7Fh) can be Permanent Write Protected (PWP) or Reversible Write Protected (RWP) by software. This allows DRAM vendor and product information to be stored and write protected. The upper 128 bytes (address 80h to FFh) are not write protected and can be used for general purpose data storage. The SE97B has a single die for both the temp sensor and EEPROM for higher reliability and supports the industry-standard 2-wire I2C-bus/SMBus serial interface. The SMBus TIMEOUT function is supported to prevent system lock-ups. Manufacturer and Device ID registers provide the ability to confirm the identity of the device. Three address pins allow up to eight devices to be controlled on a single bus. The SE98B is available as the SE97B thermal sensor only. NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD Table 1. Feature Comparison of SE97 versus SE97B features SE97 old JEDEC specification no SMBus Timeout SMBus Timeout 25 ms to 35 ms 400 kHz VIL(max) = 0.3 × VDD; VIH(min) = 0.7 × VDD set to 0 frozen set to 0 yes set to 0 50 ns 1010 0010 0000 0001 Grade B 0.6 V 3.0 V to 3.6 V 3.0 V to 3.6 V 1.7 V to 3.6 V assembly plant Hong Kong 3.0 V to 3.6 V assembly plant Bangkok (thicker die and leadframe) 0000 0011 Improved Grade B 1.8 V 0.05 × VDD set to 1 set to 1 de-assert set to 1 SE97B new JEDEC specification SMBus Timeout 25 ms to 35 ms JEDEC specification Bit 8 ‘1’ Thermal Sensor shutdown Bit 8 ‘0’ Thermal Sensor active I2C-bus maximum frequency I2C SCL and SDA VIL/VIH voltage levels Capabilities bit 6 SMBus Timeout EVENT pin operation Capabilities bit 7 EVENT pin A0 pin is 10 V tolerant Capabilities bit 5 VHV I2C spike suppression I2C input hysteresis SE97 Device ID register Revision ID register Temperature Sensor accuracy Power-On Reset (POR) Temperature Sensor voltage range EEPROM Write voltage range EEPROM Read voltage range 2 mm × 3 mm × 0.8 mm package 2. Features 2.1 General features JEDEC (JC-42.4) DIMM temperature sensor plus 256-byte serial EEPROM for Serial Presence Detect (SPD) SDA open-drain output design for best operation in distributed multi-point applications Shutdown current: 0.1 μA (typ.) and 5.0 μA (max.) Power-on reset: 1.8 V (typ.) 2-wire interface: I2C-bus/SMBus compatible, 0 Hz to 400 kHz SMBus Alert Response Address and TIMEOUT 25 ms to 35 ms (programmable) ESD protection exceeds 2500 V HBM per JESD22-A114, 250 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Available in HWSON8 package 2.2 Temperature sensor features 11-bit ADC Temperature-to-Digital converter with 0.125 °C resolution Voltage range: 3.0 V to 3.6 V Operating current: 250 μA (typ.) and 400 μA (max.) SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 2 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD Programmable hysteresis threshold: off, 0 °C, 1.5 °C, 3 °C, 6 °C Over/under/critical temperature EVENT output B-grade accuracy: ±0.5 °C/±1 °C (typ./max.) → +75 °C to +95 °C ±1.0 °C/±2 °C (typ./max.) → +40 °C to +125 °C ±2.0 °C/±3 °C (typ./max.) → −40 °C to +125 °C 2.3 Serial EEPROM features Read and write voltage range: 3.0 V to 3.6 V Operating current: Write → 0.6 mA (typ.) for 3.5 ms (typ.) Read → 100 μA (typ.) Organized as 1 block of 256 bytes (256 × 8) 100,000 write/erase cycles and 10 years of data retention Permanent and Reversible Software Write Protect Software Write Protection for the lower 128 bytes 3. Applications DDR2 and DDR3 memory modules Laptops, personal computers and servers Enterprise networking Hard disk drives and other PC peripherals 4. Ordering information Table 2. Ordering information Topside mark 97B Package Name HWSON8 Description plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 × 3 × 0.8 mm Version SOT1069-2 Type number SE97BTP[1] [1] Industry standard 2 mm × 3 mm × 0.8 mm package to JEDEC WCE-3, PSON8 in 8 mm × 4 mm pitch tape 4 k quantity reels. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 3 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 5. Block diagram SE97B TEMPERATURE REGISTER CRITICAL ALARM TRIP UPPER ALARM TRIP LOWER ALARM TRIP CAPABILITY MANUFACTURING ID DEVICE/REV ID SMBus TIMEOUT/ALERT CONFIGURATION • • • • • • • HYSTERESIS SHUTDOWN TEMP SENSOR LOCK PROTECTION EVENT OUTPUT ON/OFF EVENT OUTPUT POLARITY EVENT OUTPUT STATUS CLEAR EVENT OUTPUT STATUS FFh POR BAND GAP TEMPERATURE SENSOR 11-BIT ΔΣ ADC VDD VSS EVENT SMBus/I2C-BUS INTERFACE FILTER SCL SDA 2-kbit EEPROM NO WRITE PROTECT 80h 7Fh SOFTWARE WRITE PROTECT 00h 10 V OVERVOLTAGE R 30 kΩ to 800 kΩ A0 A1 R 30 kΩ to 800 kΩ A2 R 30 kΩ to 800 kΩ POINTER REGISTER 002aae309 Fig 1. Block diagram of SE97B SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 4 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 6. Pinning information 6.1 Pinning terminal 1 index area A0 A1 A2 VSS 1 2 8 7 VDD EVENT SCL SDA SE97BTP 3 4 6 5 002aae311 Transparent top view Fig 2. Pin configuration for HWSON8 6.2 Pin description Table 3. Symbol A0 A1 A2 VSS SDA SCL EVENT VDD Pin description Pin 1 2 3 4 5 6 7 8 Type I I I ground I/O I O power Description I2C-bus/SMBus slave address bit 0 with internal pull-down. This input is overvoltage tolerant to support software write protection. I2C-bus/SMBus slave address bit 1 with internal pull-down I2C-bus/SMBus slave address bit 2 with internal pull-down device ground SMBus/I2C-bus serial data input/output (open-drain). Must have external pull-up resistor. SMBus/I2C-bus serial clock input/output (open-drain). Must have external pull-up resistor. Thermal alarm output for high/low and critical temperature limit (open-drain). Must have external pull-up resistor. device power supply (3.0 V to 3.6 V) SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 5 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 7. Functional description 7.1 Serial bus interface The SE97B communicates with a host controller by means of the 2-wire serial bus (I2C-bus/SMBus) that consists of a serial clock (SCL) and serial data (SDA) signals. The device supports SMBus, I2C-bus Standard-mode and Fast-mode. The I2C-bus standard speed is defined to have bus speeds from 0 Hz to 100 kHz, I2C-bus fast speed from 0 Hz to 400 kHz, and the SMBus is from 10 kHz to 100 kHz. The host or bus master generates the SCL signal, and the SE97B uses the SCL signal to receive or send data on the SDA line. Data transfer is serial, bidirectional, and is one byte at a time with the Most Significant Bit (MSB) transferred first. Since SCL and SDA are open-drain, pull-up resistors must be installed on these pins. 7.2 Slave address The SE97B uses a 4-bit fixed and 3-bit programmable (A0, A1 and A2) 7-bit slave address that allows a total of eight devices to coexist on the same bus. The A0, A1 and A2 pins are pulled LOW internally. The A0 pin is also overvoltage tolerant supporting 10 V software write protect. When it is driven higher than 7.0 V, writing a special command would put the EEPROM in reversible write protect mode (see Section 7.10.2 “Memory Protection”). Each pin is sampled at the start of each I2C-bus/SMBus access. The temperature sensor’s fixed address is ‘0011b’. The EEPROM’s fixed address for the normal EEPROM read/write is ‘1010b’, and for EEPROM software protection command is ‘0110b’. Refer to Figure 3. slave address MSB 0 0 1 1 A2 A1 LSB A0 R/W MSB X 1 0 slave address LSB 1 0 A2 A1 A0 R/W MSB X 0 1 slave address LSB 1 0 A2 A1 A0 R/W X fixed hardware selectable 002aab304 fixed hardware selectable 002aab351 fixed hardware selectable 002aab352 a. Temperature sensor Fig 3. Slave address b. EEPROM (normal read/write) c. EEPROM (software protection command) SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 6 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 7.3 EVENT output condition The EVENT output indicates conditions such as the temperature crossing a predefined boundary. The EVENT modes are very configurable and selected using the configuration register (CONFIG). The interrupt mode or comparator mode is selected using CONFIG[0], using either TCRIT/UPPER/LOWER or TCRIT only temperature bands (CONFIG[2]) as modified by hysteresis (CONFIG[10:9]). The UPPER/LOWER (CONFIG[6]) and TCRIT (CONFIG[7]) bands can be locked. Figure 4 shows an example of the measured temperature versus time, with the corresponding behavior of the EVENT output in each of these modes. Upon device power-up, the default condition for the EVENT output is high-impedance to prevent spurious or unwanted alarms, but can be later enabled (CONFIG[3]). CONFIG[3] does not have to be cleared (e.g., set back to (0)) before changing CONFIG[2] or CONFIG[0]. EVENT output polarity can be set to active HIGH or active LOW (CONFIG[1]). EVENT status can be read (CONFIG[4]) and cleared (CONFIG[5]). If the EVENT output is enabled (CONFIG[3] = 1) and the part is switched between Interrupt mode and Comparator mode or vice versa, the EVENT output may glitch during the change. If the device enters Shutdown mode (CONFIG[8]) with asserted EVENT output, the output either de-asserts (default) or remains asserted (frozen) depending on SMBUS[4]. 7.3.1 EVENT pin output voltage levels and resistor sizing The EVENT open-drain output is typically pulled up to a voltage level from 0.9 V to 3.6 V with an external pull-up resistor, but there is no real lower limit on the pull-up voltage for the EVENT pin since it is simply an open-drain NMOS pull-down output. It could be pulled up to 0.1 V and would not affect the output. From the system perspective, there will be a practical limit. That limit will be the voltage necessary for the device monitoring the interrupt pin to detect a HIGH on its input. A possible practical limit for a CMOS input would be 0.4 V. Another thing to consider is the value of the pull-up resistor. When a low supply voltage is applied to the drain (through the pull-up resistor) it is important to use a higher value pull-up resistor, to allow a larger maximum signal swing on the EVENT pin. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 7 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD temperature (°C) critical Upper Boundary Alarm Tamb Ttrip(u) − Thys Tth(crit) − Thys Ttrip(u) − Thys Ttrip(l) − Thys Lower Boundary Alarm Ttrip(l) − Thys time EVENT in Comparator mode EVENT in Interrupt mode software interrupt clear EVENT in ‘Critical Temp only’ mode (1) (2) (1) (3) (4) (3) (5) (7) (6) (4) (2) 002aae763 Refer to Table 4 for figure note information. Fig 4. Table 4. Figure note EVENT output condition EVENT output condition EVENT output boundary conditions EVENT output Comparator mode Interrupt mode Critical Temp only mode Temperature Register Status bits Bit 15 Above Critical Trip 0 0 0 0 1 0 Bit 14 Above Alarm Window 0 0 1 0 1 1 Bit 13 Below Alarm Window 0 1 0 0 0 0 (1) (2) (3) (4) (5) (6) (7) [1] Tamb ≥ Ttrip(l) Tamb < Ttrip(l) − Thys Tamb > Ttrip(u) Tamb ≤ Ttrip(u) − Thys Tamb ≥ Tth(crit) Tamb < Tth(crit) − Thys Table note [1] H L L H L L L L L L L H H H H H L H Between Tamb ≥ Tth(crit) and Tamb < Tth(crit) − Thys the EVENT output is in Comparator mode and bit 0 of CONFIG (EVENT output mode) is ignored. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 8 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 7.3.2 EVENT thresholds 7.3.2.1 Alarm window The device provides a comparison window with an UPPER trip point and a LOWER trip point, programmed through the Upper Boundary Alarm Trip register (02h), and Lower Boundary Alarm Trip register (03h). The Upper Boundary Alarm Trip register holds the upper temperature trip point, while the Lower Boundary Alarm Trip register holds the lower temperature trip point as modified by hysteresis as programmed in the Configuration register. When enabled, the EVENT output triggers whenever entering or exiting (crossing above or below) the alarm window. • Advisory note: – NXP device: The EVENT output can be cleared through the clear EVENT bit or SMBus Alert Response Address (ARA). – Competitor device: The EVENT output can be cleared only through the clear EVENT bit. – Work-around: Only clear EVENT output using the EVENT bit if both NXP and competitor devices are used. The Upper Boundary Alarm Trip should always be set above the Lower Boundary Alarm Trip. The alarm window limit is immediately compared with the temperature register even if it has not been recently updated (e.g., device has been in standby) when the EVENT is turned on (CONFIG[3]). Consider waiting one conversion cycle (125 ms) after setting the alarm window limit before enabling the EVENT output/comparing the alarm window limit with the temperature register to ensure that there is correct data in the temperature register. If SMBUS[2] is set, then the alarm window limit will only be compared to the Temperature register after it has been updated when EVENT is turned on. 7.3.2.2 Critical trip The Tth(crit) temperature setting is programmed in the Critical Alarm Trip register (04h) as modified by hysteresis as programmed in the Configuration register. When the temperature reaches the critical temperature value in this register (and EVENT is enabled), the EVENT output asserts and cannot be de-asserted until the temperature drops below the critical temperature threshold. The Event cannot be cleared through the clear EVENT bit or SMBus Alert. The Critical Alarm Trip should always be set above the Upper Boundary Alarm Trip. The critical trip limit is immediately compared with the temperature register even if it has not been recently updated (e.g., device has been in standby) when the EVENT is turned on (CONFIG[3]). Consider waiting one conversion cycle (125 ms) after setting the critical trip limit before enabling the EVENT output/comparing the critical trip limit with the temperature register to ensure that there is correct data in the temperature register. If SMBUS[2] is set, then the alarm window limit will only be compared to the Temperature register after it has been updated when EVENT is turned on. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 9 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 7.3.3 EVENT operation modes 7.3.3.1 Comparator mode In comparator mode, the EVENT output behaves like a window-comparator output that asserts when the temperature is outside the window (e.g., above the value programmed in the Upper Boundary Alarm Trip register or below the value programmed in the Lower Boundary Alarm Trip register or above the Critical Alarm Trip register if Tth(crit) only is selected). Reads/writes on these registers do not affect the EVENT output in comparator mode. The EVENT signal remains asserted until the temperature goes inside the alarm window or the window thresholds are reprogrammed so that the current temperature is within the alarm window. The comparator mode is useful for thermostat-type applications, such as turning on a cooling fan or triggering a system shutdown when the temperature exceeds a safe operating range. 7.3.3.2 Interrupt mode In interrupt mode, EVENT asserts whenever the temperature crosses an alarm window threshold. After such an event occurs, writing a 1 to the clear event bit in the configuration register de-asserts the EVENT output until the next trigger condition occurs. In interrupt mode, EVENT asserts when the temperature crosses the alarm upper boundary. If the EVENT output is cleared and the temperature continues to increase until it crosses the critical temperature threshold, EVENT asserts again. Because the temperature is greater than the critical temperature threshold, a clear event command does not clear the EVENT output. Once the temperature drops below the critical temperature, EVENT de-asserts immediately. If the EVENT output is not cleared before or when the temperature is in the critical temperature threshold, EVENT will remain asserted after the temperature drops below the critical temperature until a clear event command. 7.3.3.3 Switching between Comparator mode and Interrupt mode When the part is in Comparator mode and the temperature windows are set such that the BAW bit is set and the EVENT pin asserted (EventOutputControl = 1) and the part is switched to Interrupt mode, the EVENT is de-asserted. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 10 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 7.4 Conversion rate The conversion time is the amount of time required for the ADC to complete a temperature measurement for the local temperature sensor. The conversion rate is the inverse of the conversion period which describes the number of cycles the temperature measurement completes in one second—the faster the conversion rate, the faster the temperature reading is updated. The SE97B’s conversion rate is at least 8 Hz or 125 ms. 7.4.1 What temperature is read when conversion is in progress The SE97B has been designed to ensure a valid temperature is always available. When a read to the temperature register is initiated through the SMBus, the device checks to see if the temperature conversion process (Analog-to-Digital conversion) is complete and a new temperature is available: • If the temperature conversion process is complete, then the new temperature value is sent out on the SMBus. • If the temperature conversion process in not complete, then the previous temperature value is sent out on the SMBus. It is possible that while SMBus Master is reading the temperature register, a new temperature conversion completes. However, this will not affect the data (MSB or LSB) that is being shifted out. On the next read of the temperature register, the new temperature value will be shifted out. 7.5 Power-up default condition After power-on, the SE97B is initialized to the following default condition: • • • • • Starts monitoring local sensor EVENT register is cleared; EVENT output is pulled HIGH by external pull-ups EVENT hysteresis is defaulted to 0 °C Command pointer is defaulted to ‘00h’ Critical Temp, Alarm Temperature Upper and Lower Boundary Trip register are defaulted to 0 °C EVENT de-asserted and SMBus TIMEOUT between 25 ms and 35 ms enabled. • Capability register is defaulted to ‘00F7h’ for the B-grade and VHV capability, • Operational mode: comparator • SMBus register is defaulted to ‘21h’ 7.6 Device initialization SE97B temperature sensors have programmable registers, which, upon power-up, default to zero. The open-drain EVENT output is default to being disabled, comparator mode and active LOW. The alarm trigger registers default to being unprotected. The configuration registers, upper and lower alarm boundary registers and critical temperature window are defaulted to zero and need to be programmed to the desired values. SMBus TIMEOUT feature defaults to being enabled and can be programmed to disable. These registers are required to be initialized before the device can properly function. Except for the SPD, which does not have any programmable registers, and does not need to be initialized. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 11 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD Table 5 shows the default values and the example value to be programmed to these registers. Table 5. Register 01h Registers to be initialized Default value 0000h Example value 0209h Description Configuration register • • • 02h 03h 04h 22h 0000h 0000h 0000h 21h 0550h 1F40h 05F0h 21h hysteresis = 1.5 °C EVENT output = Interrupt mode EVENT output is enabled Upper Boundary Alarm Trip register = 85 °C Lower Boundary Alarm Trip register = −20 °C Critical Alarm Trip register = 95 °C SMBus register = no change 7.7 SMBus TIMEOUT The SE97B supports SMBus TIMEOUT feature. If the host holds SCL LOW more than 35 ms, the SE97B would reset its internal state machine to the bus IDLE state to prevent a system bus hang-up. This feature is turned on by default and release SDA. The SMBus TIMEOUT can be disabled by writing a ‘1’ to SMBUS[7]. Remark: When SMBus TIMEOUT is enabled, the I2C-bus minimum bus speed is limited by the SMBus TIMEOUT specification limit of 10 kHz. The SE97B has no SCL driver, so it cannot hold the SCL line LOW. 7.8 SMBus Alert Response Address (ARA) The SE97B supports SMBus ALERT when it is programmed for the Interrupt mode and when the EVENT polarity bit is set to ‘0’. In Comparator mode or when the EVENT polarity bit is set to ‘1’, the SMBus ALERT address is not acknowledged. The EVENT pin can be ANDed with other EVENT or interrupt signals from other slave devices to signal their intention to communicate with the host controller. When the host detects EVENT or other interrupt signal LOW, it issues an ARA to which a slave device would respond with its address. When there are multiple slave devices generating an ALERT the SE97B performs bus arbitration with the other slaves. If it wins the bus, it responds to the ARA and then clears the EVENT pin. This feature is turned off by default and can be enabled by writing a ‘0’ to SMBUS[0]. Remark: Either in comparator mode or when the SE97B crosses the critical temperature, the host must also read the EVENT status bit and provide remedy to the situation by bringing the temperature to within the alarm window or below the critical temperature if that bit is set. Otherwise, the EVENT pin will not get de-asserted. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 12 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD START bit read Alert Response Address 0 0 1 1 0 0 1 acknowledge device address 0 0 0 1 1 A2 no acknowledge STOP bit S host detects SMBus ALERT 0 A1 A0 0 1 P master sends a START bit, ARA and a read command Slave acknowledges and sends its slave address. The last bit of slave address is hard coded '0'. host NACK and sends a STOP bit 002aac685 Fig 5. How SE97B responds to SMBus Alert Response Address 7.9 SMBus/I2C-bus interface The data registers in this device are selected by the Pointer Register. At power-up, the Pointer Register is set to ‘00h’, the location for the Capability Register. The Pointer Register latches the last location to which it was set. Each data register falls into one of three types of user accessibility: • Read only • Write only • Write/Read same address A ‘write’ to this device will always include the address byte and the pointer byte. A write to any register other than the Pointer register requires two data bytes. Reading this device can take place either of two ways: • If the location latched in the Pointer register is correct (most of the time it is expected that the Pointer register will point to one of the Temperature register (as it will be the data most frequently read), then the read can simply consist of an address byte, followed by retrieving the two data bytes. • If the Pointer register needs to be set, then an address byte, pointer byte, repeat START, and another address byte will accomplish a read. The data byte has the most significant bit first. At the end of a read, this device can accept either Acknowledge (ACK) or No Acknowledge (NACK) from the Master (No Acknowledge is typically used as a signal for the slave that the Master has read its last byte). It takes this device 125 ms to measure the temperature. Refer to timing diagrams Figure 6 to Figure 9 for how to program the device. 1 SCL SDA S START A6 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 A5 A4 A3 A2 A1 A0 W A ACK by device D7 D6 D5 D4 D3 D2 D1 D0 A P ACK STOP by device 002aab308 device address and write register address A = ACK = Acknowledge bit. W = Write bit = 0. R = Read bit = 1. Fig 6. SMBus/I2C-bus write to the Pointer register SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 13 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 1 SCL SDA S START by host 1 SCL SDA by host D15 A6 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 (cont.) A5 A4 A3 A2 A1 A0 W A D7 ACK by device 8 9 1 D6 D5 D4 D3 D2 D1 D0 A (cont.) device address and write 2 3 4 5 6 7 write register address 2 3 4 5 6 7 ACK by device 8 9 D14 D13 D12 D11 D10 D9 D8 A ACK by device D7 D6 D5 D4 D3 D2 D1 D0 A P ACK STOP by device by host 002aab412 most significant byte data least significant byte data A = ACK = Acknowledge bit. W = Write bit = 0. R = Read bit = 1. Fig 7. SMBus/I2C-bus write to the Pointer register followed by a write data word 1 SCL SDA S START by host 1 SCL SDA SR repeated START by host SCL SDA D15 A6 A6 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 (cont.) A5 A4 A3 A2 A1 A0 W A ACK by device D7 D6 D5 D4 D3 D2 D1 D0 A (cont.) ACK by device device address and write 2 3 4 5 6 7 8 read register address 9 (cont.) A5 A4 A3 A2 A1 A0 R A ACK by device (cont.) device address and read 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 D14 D13 D12 D11 D10 D9 D8 A ACK by host D7 D6 D5 D4 D3 D2 D1 D0 A P NACK STOP by host by host 002aac686 returned most significant byte data returned least significant byte data A = ACK = Acknowledge bit. A = NACK = No Acknowledge bit. W = Write bit = 0. R = Read bit = 1. Fig 8. SMBus/I2C-bus write to Pointer register followed by a repeated START and an immediate data word read SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 14 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 1 SCL SDA S START by host 1 SCL SDA D15 A6 2 3 4 5 6 7 8 9 (cont.) A5 A4 A3 A2 A1 A0 R A ACK by device (cont.) device address and read 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 D14 D13 D12 D11 D10 D9 D8 A ACK by host D7 D6 D5 D4 D3 D2 D1 D0 A P NACK STOP by host 002aac687 returned most significant byte data returned least significant byte data A = ACK = Acknowledge bit. A = NACK = No Acknowledge bit. W = Write bit = 0. R = Read bit = 1. Fig 9. SMBus/I2C-bus word read from register with a pre-set pointer 7.10 EEPROM operation The 2-kbit EEPROM is organized as either 256 bytes of 8 bits each (byte mode), or 16 pages of 16 bytes each (page mode). Accessing the EEPROM in byte mode or page mode is automatic; partial page write of 2 bytes, 4 bytes, or 8 bytes is also supported. Communication with the EEPROM is via the 2-wire serial I2C-bus or SMBus. Figure 10 provides an overview of the EEPROM partitioning. 00h 01h FFh … 07h no write protect 80h 7Fh 16 pages or 256 bytes write protect by software 0Fh 00h 1 page or 16 bytes 8 pages or 128 bytes 002aac812 Fig 10. EEPROM partitioning SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 15 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 7.10.1 Write operations 7.10.1.1 Byte Write In Byte Write mode the master creates a START condition and then broadcasts the slave address, byte address, and data to be written. The slave acknowledges all 3 bytes by pulling down the SDA line during the ninth clock cycle following each byte. The master creates a STOP condition after the last ACK from the slave, which then starts the internal write operation (see Figure 11). During internal write, the slave will ignore any read/write request from the master. slave address (memory) SDA S 1 0 1 0 A2 A1 A0 0 A word address A data DATA A P START condition R/W acknowledge from slave acknowledge from slave acknowledge from slave STOP condition; write to the memory is performed 002aab246 Fig 11. Byte Write timing 7.10.1.2 Page Write The SE97B contains 256 bytes of data, arranged in 16 pages of 16 bytes each. The page is selected by the four Most Significant Bits (MSB) of the address byte presented to the device after the slave address, while the four Least Significant Bits (LSB) point to the byte within the page. By loading more than one data byte into the device, up to an entire page can be written in one write cycle (see Figure 12). The internal byte address counter will increment automatically after each data byte. If the master transmits more than 16 data bytes, then earlier bytes will be overwritten by later bytes in a wrap-around fashion within the selected page. The internal write cycle is started following the STOP condition created by the master. slave address (memory) SDA S 1 0 1 0 A2 A1 A0 0 A word address A data to memory DATA n A START condition R/W acknowledge from slave acknowledge from slave acknowledge from slave data to memory DATA n + 15 A P acknowledge from slave STOP condition; write to the memory is performed 002aab247 Fig 12. Page Write timing SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 16 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 7.10.1.3 Acknowledge polling Acknowledge polling can be used to determine if the SE97B is busy writing or is ready to accept commands. Polling is implemented by sending a ‘Selective Read’ command (described in Section 7.10.3 “Read operations”) to the device. The SE97B will not acknowledge the slave address as long as internal write is in progress. 7.10.2 Memory Protection The lower half (the first 128 bytes) of the memory can be write protected by special EEPROM commands without an external control pin. The SE97B features three types of memory write protection instructions, and three respective read Protection instructions. The level of write-protection (set or clear) that has been defined using these instructions remained defined even after power cycle. The memory protection commands are: • • • • • • Permanent Write Protection (PWP) Reversible Write Protection (RWP) Clear Write Protection (CWP) Read Permanent Write Protection (RPWP) Read Reversible Write Protection (RRWP) Read Clear Write Protection (RCWP) Table 6 is the summary for normal and memory protection instructions. Table 6. Command EEPROM commands summary Fixed address Bit 7[1] Normal EEPROM read/write Reversible Write Protection (RWP) Clear Reversible Write Protection (CRWP) Permanent Write Protection Read RWP Read CRWP Read PWP [1] [2] [3] The most significant bit, bit 7, is sent first. VI(ov) ranges from 7.0 V to 10 V. A0, A1, and A2 are compared against the respective external pins on the SE97B. Do not apply VI(ov) to the A0 pin during Normal EEPROM read/write, Permanent Write Protection (PWP) and Read PWP. Hardware selectable address Bit 5 1 1 1 1 1 1 1 Bit 4 0 0 0 0 0 0 0 Bit 3 A2 VSS VSS A2 VSS VSS A2 Bit 2 A1 VSS VDD A1 VSS VDD A1 Bit 1 A0 VI(ov)[2] VI(ov) A0 VI(ov) A0 [2] [2] R/W Bit 0 R/W 0 0 0 1 1 1 Bit 6 0 1 1 1 1 1 1 1 0 0 0 0 0 0 (PWP)[3] VI(ov)[2] This special EEPROM command consists of a unique 4-bit fixed address (0110b) and the voltage level applied on the 3-bit hardware address. Normally, to address the memory array, the 4-bit fixed address is ‘1010b’. To access the memory protection settings, the 4-bit fixed address is ‘0110b’. Figure 13 and Figure 14 show the write and read protection sequence, respectively. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 17 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD Up to eight memory devices can be connected on a single I2C-bus. Each one is given a 3-bit on the hardware selectable address (A2, A1, A0) inputs. The device only responds when the 4-bit fixed and hardware selectable bits are matched. The 8th bit is the read/write bit. This bit is set to 1 or 0 for read and write protection, respectively. The corresponding device acknowledges during the ninth bit time when there is a match on the 7-bit address. The device does not acknowledge when there is no match on the 7-bit address or when the device is already in permanent write protection mode and is programmed with any write protection instructions (i.e., PWP, RWP, CWP). slave address (memory) SDA S 0 1 1 0 A2 A1 A0 0 A X dummy byte address X X X X X X X A X X dummy data X X X X X X A P START condition R/W acknowledge(1) from slave acknowledge(1) from slave acknowledge(1) from slave STOP condition 002aab356 X = Don’t Care (1) Refer to Table 7 regarding the exact state of the acknowledge bit. Fig 13. Software Write Protect (write) slave address (memory) SDA S 0 1 1 0 A2 A1 A0 1 A X dummy byte address X X X X X X X A X X dummy data X X X X X X A P START condition R/W acknowledge(1) from slave no acknowledge(1) from slave no acknowledge(1) from slave STOP condition 002aac644 X = Don’t Care (1) Refer to Table 8 regarding the exact state of the acknowledge bit. Fig 14. Software Write Protect (read) 7.10.2.1 Permanent Write Protection (PWP) If the software write-protection has been set with the PWP instruction, the first 128 bytes of the memory are permanently write-protected. This write-protection cannot be cleared by any instruction, or by power-cycling the device. Also, once the PWP instruction has been successfully executed, the device no longer acknowledges any instruction (with 4-bit fixed address of 0110b) to access the write-protection settings. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 18 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 7.10.2.2 Reversible Write Protection (RWP) and Clear Reversible Write Protection (CRWP) If the software write-protection has been set with the RWP instruction, it can be cleared again with a CRWP instruction. The two instructions, RWP and CRWP have the same format as a Byte Write instruction, but with a different setting for the hardware address pins (as shown in Table 6). Like the Byte Write instruction, it is followed by an address byte and a data byte, but in this case the contents are all ‘Don’t Care’ (Figure 13). Another difference is that the voltage, VI(ov), must be applied on the A0 pin, and specific logical levels must be applied on the other two (A1 and A2), as shown in Table 6. Table 7. Acknowledge when writing data or defining write protection Instructions with R/W bit = 0. Status Permanently protected Protected with RWP Instruction PWP, RWP or CRWP page or byte write in lower 128 bytes RWP CRWP PWP page or byte write in lower 128 bytes Not protected PWP or RWP CRWP page or byte write ACK NACK ACK NACK ACK ACK ACK ACK ACK ACK Address not significant address not significant not significant not significant address not significant not significant address ACK NACK ACK NACK ACK ACK ACK ACK ACK ACK Data byte not significant data not significant not significant not significant data not significant not significant data ACK NACK NACK NACK ACK ACK NACK ACK ACK ACK Write cycle (tW) no no no yes yes no yes no yes 7.10.2.3 Read Permanent Write Protection (RPWP), Read Reversible Write Protection (RRWP), and Read Clear Reversible Write Protection (RCRWP) Read PWP, RWP, and CRWP allow the SE97B to be read in write protection mode. The instruction format is the same as that of the write protection except that the 8th bit, R/W, is set to 1. Figure 14 shows the instruction format, while Table 8 shows the responses when the instructions are issued. Table 8. Acknowledge when reading the write protection Instructions with R/W bit = 1. Status Permanently protected Protected with RWP Instruction RPWP, RRWP or RCRWP RRWP RCRWP RPWP Not protected RPWP, RRWP or RCRWP ACK NACK NACK ACK ACK ACK Address not significant not significant not significant not significant not significant ACK NACK NACK NACK NACK NACK Data byte not significant not significant not significant not significant not significant ACK NACK NACK NACK NACK NACK SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 19 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 7.10.3 Read operations 7.10.3.1 Current address read In Standby mode, the SE97B internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If the ‘previous’ byte was the last byte in memory, then the address counter will point to the first memory byte, and so on. If the SE97B decodes a slave address with a ‘1’ in the R/W bit position (Figure 15), it will issue an Acknowledge in the ninth clock cycle and will then transmit the data byte being pointed at by the address counter. The master can then stop further transmission by issuing a No Acknowledge on the ninth bit then followed by a STOP condition. slave address (memory) SDA S 1 0 1 0 A2 A1 A0 1 A data from memory A P START condition R/W acknowledge from slave no acknowledge from master STOP condition 002aab251 Fig 15. Current address read timing 7.10.3.2 Selective read The read operation can also be started at an address different from the one stored in the address counter. The address counter can be ‘initialized’ by performing a ‘dummy’ write operation (Figure 16). The START condition is followed by the slave address (with the R/W bit set to ‘0’) and the desired byte address. Instead of following-up with data, the master then issues a second START, followed by the ‘Current Address Read’ sequence, as described in Section 7.10.3.1. slave address (memory) SDA S 1 0 1 0 A2 A1 A0 0 A word address A START condition R/W acknowledge from slave acknowledge from slave slave address (memory) S 1 0 1 0 A2 A1 A0 1 A data from memory A P START condition R/W acknowledge from slave no acknowledge from master STOP condition 002aac901 Fig 16. Selective read timing SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 20 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 7.10.3.3 Sequential read If the master acknowledges the first data byte transmitted by the SE97B, then the device will continue transmitting as long as each data byte is acknowledged by the master (Figure 17). If the end of memory is reached during sequential Read, the address counter will ‘wrap around’ to the beginning of memory, and so on. Sequential Read works with either ‘Immediate Address Read’ or ‘Selective Read’, the only difference being the starting byte address. slave address (memory) SDA S 1 0 1 0 A2 A1 A0 1 A data from memory DATA n A data from memory DATA n + 1 A START condition R/W acknowledge from slave acknowledge from master acknowledge from master data from memory DATA n + X A P no acknowledge from master STOP condition 002aab253 Fig 17. Sequential read timing SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 21 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 8. Register descriptions 8.1 Register overview This section describes all the registers used in the SE97B. The registers are used for latching the temperature reading, storing the low and high temperature limits, configuring, the hysteresis threshold of the ADC, as well as reporting status. The device uses the pointer register to access these registers. Read registers, as the name implies, are used for read only, and the write registers are for write only. Any attempt to read from a write-only register will result in reading ‘0’s. Writing to a read-only register will have no effect on the read even though the write command is acknowledged. The Pointer register is an 8-bit register. All other registers are 16-bit. Table 9. Address (hex) n/a 00h 01h 02h 03h 04h 05h 06h 07h 08h to 21h 22h 23h to FFh Register summary Default state (hex) n/a F7h 0000h 0000h 0000h 0000h n/a 1131h A203h 0000h 21h 0000h Register name Short name JEDEC name Pointer register Capability register Configuration register Upper Boundary Alarm Trip register Lower Boundary Alarm Trip register Critical Alarm Trip register Temperature register Manufacturer ID register Device ID/Revision register reserved registers SMBus register reserved SMBUS Vendor-defined CAP CONFIG UPPER LOWER CRITICAL TEMP MANID DEVICEID Capabilities Configuration High Limit Low Limit TCRIT Limit Ambient Temperature Manufacturer ID Device/Revision A write to reserved registers my cause unexpected results which may result in requiring a reset by removing and re-applying its power. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 22 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 8.2 CAP — Capability register (00h, 16-bit read-only) Table 10. Bit Symbol Default Access Bit Symbol Default Access 0 R 7 EVSD 1 R 0 R 6 TMOUT 1 R Table 11. Bit 15:8 7 0 R 5 VHV 1 R 0 R 4 TRES 1 R CAP - Capability register (address 00h) bit allocation 15 14 13 12 RFU 0 R 3 TRES 0 R 0 R 2 WRNG 1 R 0 R 1 HACC 1 R 0 R 0 BCAP 1 R 11 10 9 8 Capability register (address 00h) bit description Symbol RFU EVSD Description Reserved for future use; must be zero. EVENT with shutdown action. 0 — The EVENT output freezes in its current state when entering shutdown. Upon exiting shutdown, the EVENT output remains in the previous state until the next thermal sample is taken. 1 (default) — The EVENT output is de-asserted (not driven) when entering shutdown, and remains de-asserted upon exit from shutdown until the next thermal sample is taken. Remark: Bit 7 follows the state of SMBUS[4] which can change EVENT output to freeze. 6 TMOUT Bus time-out period for thermal sensor access during normal operation. Note that bus time-out support is operational in shutdown mode, or for access to the EEPROM portion of the device. 1 — Parameter tto(SMBus) is supported within the range of 25 ms to 35 ms (SMBus compatible). 5 4:3 2 1 0 VHV TRES WRNG HACC BCAP High voltage standoff for pin A0. 1 — Supports a voltage up to 10 V on the A0 pin. Temperature resolution. 10 — 0.125 °C LSB (11-bit) Wider range. 1 — can read temperatures below 0 °C and set sign bit accordingly Higher accuracy (set during manufacture). 1 — B grade accuracy Basic capability. 1 — has Alarm and Critical Trips interrupt capability SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 23 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 8.3 CONFIG — Configuration register (01h, 16-bit read/write) Table 12. Bit Symbol Default Access Bit Symbol Default Access 0 R 7 CTLB 0 R/W 0 R 6 AWLB 0 R/W Table 13. Bit 15:11 10:9 CONFIG - Configuration register (address 01h) bit allocation 15 14 13 RFU 0 R 5 CEVNT 0 W 0 R 4 ESTAT 0 R 0 R 3 EOCTL 0 R/W 0 R/W 2 CVO 0 R/W 12 11 10 HEN 0 R/W 1 EP 0 R/W 9 8 SHMD 0 R/W 0 EMD 0 R/W Configuration register (address 01h) bit description Symbol RFU HEN Description reserved for future use; must be ‘0’. Hysteresis Enable. 00 — disable hysteresis (default) 01 — enable hysteresis at 1.5 °C 10 — enable hysteresis at 3 °C 11 — enable hysteresis at 6 °C When enabled, hysteresis is applied to temperature movement around trigger points. For example, consider the behavior of the ‘Above Alarm Window’ bit (bit 14 of the Temperature register) when the hysteresis is set to 3 °C. As the temperature rises, bit 14 will be set to ‘1’ (temperature is above the alarm window) when the Temperature register contains a value that is greater than the value in the Alarm Temperature Upper Boundary Register. If the temperature decreases, bit 14 will remain set until the measured temperature is less than or equal to the value in the Alarm Temperature Upper Boundary register minus 3 °C. (Refer to Figure 4 and Table 14). Similarly, the ‘Below Alarm Window’ bit (bit 13 of the Temperature register) will be set to ‘0’ (temperature is equal to or above the Alarm Window Lower Boundary Trip register) when the value in the Temperature register is equal to or greater than the value in the Alarm Temperature Lower Boundary register. As the temperature decreases, bit 13 will be set to ‘1’ when the value in the Temperature register is equal to or less than the value in the Alarm Temperature Lower Boundary register minus 3 °C. Note that hysteresis is also applied to EVENT pin functionality. When either of the Critical Trip or Alarm Window lock bits is set, these bits cannot be altered until unlocked. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 24 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD Configuration register (address 01h) bit description …continued Symbol SHMD Description Shutdown Mode. 0 — Temperature Sensor is active and converting (default). 1 — disabled Temperature Sensor will not generate interrupts or update the temperature data. When shut down, the thermal sensor diode and ADC are disabled to save power, no events will be generated. When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be set until unlocked. However, it can be cleared at any time. When in shutdown mode, the SE97B will still respond to commands normally. When coming out of shutdown, the EVENT output remains de-asserted as a new temperature conversion is done. Hysteresis is subtracted from the alarm thresholds if the temperature is falling but not used if the temperature is rising. The temperature trend will not be determined until at least two temperature conversions are done. Since all the alarm threshold flags (TEMP bits 13, 14, 15) are cleared with coming out of shutdown, it was decided to only apply hysteresis to the lower alarm threshold calculations when determining after the initial temperature conversion if the EVENT should assert. After the second temperature conversion the direction of temperature is known and TEMP bits 13, 14 or 15 are changed as required and the EVENT is asserted as required. Table 13. Bit 8 7 CTLB Critical Trip Lock bit. 0 — Critical Alarm Trip register is not locked and can be altered (default) 1 — Critical Alarm Trip register settings cannot be altered This bit is initially cleared. When set, this bit will return a ‘1’, and remains locked until cleared by internal Power-on reset. This bit can be written with a single write and does not require double writes. 6 AWLB Alarm Window Lock bit. 0 — Upper and Lower Alarm Trip registers are not locked and can be altered (default) 1 — Upper and Lower Alarm Trip registers setting cannot be altered This bit is initially cleared. When set, this bit will return a ‘1’ and remains locked until cleared by internal power-on reset. This bit can be written with a single write and does not require double writes. 5 CEVNT Clear EVENT (write only). 0 — no effect (default) 1 — clears active EVENT in Interrupt mode. Writing to this register has no effect in Comparator mode. If SMBUS[0] is a logic 0, the SMBus Alert Response Address (ARA) command can be sent to also clear the EVENT output. When read, this register always returns zero. 4 ESTAT EVENT Status (read only). 0 — EVENT output condition is not being asserted by this device (default) 1 — EVENT output pin is being asserted by this device due to Alarm Window or Critical Trip condition The actual event causing the event can be determined from the Read Temperature register. Interrupt Events can be cleared by writing to the ‘Clear EVENT’ bit (CEVNT) or SMBus Alert Response. Writing to this bit will have no effect. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 25 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD Configuration register (address 01h) bit description …continued Symbol EOCTL Description EVENT Output Control. 0 — EVENT output disabled (default) 1 — EVENT output enabled When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked. Table 13. Bit 3 2 CVO Critical Event Only. 0 — EVENT output on Alarm or Critical temperature event (default) 1 — EVENT only if temperature is above the value in the critical temperature register When the alarm window lock bit is set, this bit cannot be altered until unlocked. 1 EP EVENT Polarity. 0 — active LOW (default) 1 — active HIGH. When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked. When the EP (EVENT Polarity) bit is changed, the EVENT output would immediately change state on the SE97B. A new Shutdown mode has been added on the SE97B with two states defined by the SMBus register EventSleepState = 0. Freeze state of EVENT output and EventSleepState = 1: de-asserted state of EVENT output. So now if the EP bit changes, the EVENT output state will change immediately even during shutdown. It will not wait for the part to do a new temperature conversion after coming out of shutdown. Changes to all other bits in the CONFIG register and the SMBus register take effect after a new temperature conversion happens when the part comes out of shutdown. The EP bit is not related to temperature conversion or readings or if the part is in shutdown or active. Remark: In Shutdown mode, when DisableTimeout = 1 or if DisableTimeout = 0 and Enable SDIO = 0, the EVENT Polarity bit will not take effect immediately, but will updated after it comes out of shutdown. 0 EMD EVENT Mode. 0 — comparator output mode (default) 1 — interrupt mode When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 26 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD Table 14. Action Hysteresis Enable Below Alarm Window bit (bit 13) Temperature slope Threshold temperature Ttrip(l) − Thys Ttrip(l) Above Alarm Window bit (bit 14) Temperature slope rising falling Threshold temperature Ttrip(u) Ttrip(u) − Thys Above Critical Trip bit (bit 15) Temperature slope rising falling Threshold temperature Tth(crit) Tth(crit) − Thys sets clears falling rising current temperature temperature critical alarm threshold hysteresis upper alarm threshold hysteresis lower alarm threshold hysteresis time Above Critical Trip (register 05h; bit 15 = ACT bit) Above Alarm Window (register 05h; bit 14 = AAW bit) Below Alarm Window (register 05h; bit 13 = BAW bit) clear set clear clear set clear set clear 002aac799 Fig 18. Hysteresis: how it works SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 27 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 8.4 Temperature format The temperature data from the temperature read back register is an 11-bit 2’s complement word with the least significant bit (LSB) equal to 0.125 °C (resolution). • A value of 019Ch will represent 25.75 °C • A value of 07C0h will represent 124 °C • A value of 1E64h will represent −25.75 °C. The unused LSB (bit 0) is set to ‘0’. Bit 11 will have a resolution of 128 °C. The upper 3 bits of the temperature register indicate Trip Status based on the current temperature, and are not affected by the status of the EVENT output. One of the ways to calculate the Temperature, Upper Boundary, Lower Boundary, and Critical Alarm Trip values in °C from the 12-bit Temp data is: • If the SIGN bit = 0, then the temperature is positive, (°C) = +(Temp data) × 0.125 °C (0.250 °C for alarm registers). (°C) = −(2’s complement of Temp data) × 0.125 °C (0.250 °C for alarm registers). • If the SIGN bit = 1, then the temperature is negative, Table 15 lists the examples of the content of the temperature data register for positive and negative temperature for two scenarios of status bits: status bits = 000b and status bits = 111b. Table 15. Degree Celsius and Temperature Data register Content of Temperature Data register Status bits = 000b Binary +125 °C +25 °C +1 °C +0.25 °C +0.125 °C 0 °C −0.125 °C −0.25 °C −1 °C −20 °C −25 °C −55 °C Hex 07D0h 0190h 0010h 0004h 0002h 0000h 1FFEh 1FFCh 1FF0h 1F40h 1E70h 1C90h Status bits = 111b Binary Hex E7D0h E190h E010h E004h E002h E000h FFFEh FFFCh FFF0h FF40h FE70h FC90h Temperature 000 0 01111101 000 0 000 0 00011001 000 0 000 0 00000001 000 0 000 0 00000000 010 0 000 0 00000000 001 0 000 0 00000000 000 0 000 1 11111111 111 0 000 1 11111111 110 0 000 1 11111111 000 0 000 1 11110100 000 0 000 1 11100111 000 0 000 1 11001001 000 0 111 0 01111101 000 0 111 0 00011001 000 0 111 0 00000001 000 0 111 0 00000000 010 0 111 0 00000000 001 0 111 0 00000000 000 0 111 1 11111111 111 0 111 1 11111111 110 0 111 1 11111111 000 0 111 1 11110100 000 0 111 1 11100111 000 0 111 1 11001001 000 0 SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 28 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 8.5 Temperature Trip Point registers While writing to the 16-bit Upper, Lower, or Critical Boundary Alarm Trip registers, please ensure that both bytes get written before doing a new START or STOP to ensure that a valid temperature value gets written into the registers. 8.5.1 UPPER — Upper Boundary Alarm Trip register (02h, 16-bit read/write) The value is the upper threshold temperature value for Alarm mode. The data format is 2’s complement with bit 2 = 0.25 °C. ‘RFU’ bits will always report zero. Interrupts will respond to the presently programmed boundary values. If boundary values are being altered in-system, it is advised to turn off interrupts until a known state can be obtained to avoid superfluous interrupt activity. Table 16. Bit Symbol Default Access Bit Symbol Default Access Table 17. Bit 15:13 12 11:2 1:0 UPPER - Upper Boundary Alarm Trip register bit allocation 15 RFU 0 R 7 8 °C 0 R/W 14 RFU 0 R 6 4 °C 0 R/W 13 RFU 0 R 5 2 °C 0 R/W 12 SIGN 0 R/W 4 1 °C 0 R/W 11 128 °C 0 R/W 3 0.5 °C 0 R/W 10 64 °C 0 R/W 2 0.25 °C 0 R/W 9 32 °C 0 R/W 1 RFU 0 R 8 16 °C 0 R/W 0 RFU 0 R Upper Boundary Alarm Trip register bit description Symbol RFU SIGN RFU Description reserved; always ‘0’ Sign (MSB) Upper Boundary Alarm Trip Temperature (LSB = 0.25 °C) reserved; always ‘0’ SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 29 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 8.5.2 LOWER — Lower Boundary Alarm Trip register (03h, 16-bit read/write) The value is the lower threshold temperature value for Alarm mode. The data format is 2’s complement with bit 2 = 0.25 °C. RFU bits will always report zero. Interrupts will respond to the presently programmed boundary values. If boundary values are being altered in-system, it is advised to turn off interrupts until a known state can be obtained to avoid superfluous interrupt activity. Table 18. Bit Symbol Default Access Bit Symbol Default Access Table 19. Bit 15:13 12 11:2 1:0 LOWER - Lower Boundary Alarm Trip register bit allocation 15 RFU 0 R 7 8 °C 0 R/W 14 RFU 0 R 6 4 °C 0 R/W 13 RFU 0 R 5 2 °C 0 R/W 12 SIGN 0 R/W 4 1 °C 0 R/W 11 128 °C 0 R/W 3 0.5 °C 0 R/W 10 64 °C 0 R/W 2 0.25 °C 0 R/W 9 32 °C 0 R/W 1 RFU 0 R 8 16 °C 0 R/W 0 RFU 0 R Lower Boundary Alarm Trip register bit description Symbol RFU SIGN RFU Description reserved; always ‘0’ Sign (MSB) Lower Boundary Alarm Trip Temperature (LSB = 0.25 °C) reserved; always ‘0’ 8.5.3 CRITICAL — Critical Alarm Trip register (04h, 16-bit read/write) The value is the critical temperature. The data format is 2’s complement with bit 2 = 0.25 °C. RFU bits will always report zero. Table 20. Bit Symbol Default Access Bit Symbol Default Access Table 21. Bit 15:13 12 11:2 1:0 CRITICAL - Critical Alarm Trip register bit allocation 15 RFU 0 R 7 8 °C 0 R/W 14 RFU 0 R 6 4 °C 0 R/W 13 RFU 0 R 5 2 °C 0 R/W 12 SIGN 0 R/W 4 1 °C 0 R/W 11 128 °C 0 R/W 3 0.5 °C 0 R/W 10 64 °C 0 R/W 2 0.25 °C 0 R/W 9 32 °C 0 R/W 1 RFU 0 R 8 16 °C 0 R/W 0 RFU 0 R Critical Alarm Trip register bit description Symbol RFU SIGN RFU Description reserved; always ‘0’ Sign (MSB) Critical Alarm Trip Temperature (LSB = 0.25 °C) reserved; always ‘0’ SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 30 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 8.6 TEMP — Temperature register (05h, 16-bit read-only) Table 22. Bit Symbol Default Access Bit Symbol Default Access Table 23. Bit 15 TEMP - Temperature register bit allocation 15 ACT 0 R 7 8 °C 0 R 14 AAW 0 R 6 4 °C 0 R 13 BAW 0 R 5 2 °C 0 R 12 SIGN 0 R 4 1 °C 0 R 11 128 °C 0 R 3 0.5 °C 0 R 10 64 °C 0 R 2 0.25 °C 0 R 9 32 °C 0 R 1 0.125 °C 0 R 8 16 °C 0 R 0 RFU 0 R Temperature register bit description Symbol ACT Description Above Critical Trip. Increasing Tamb: 0 — Tamb < Tth(crit) 1 — Tamb ≥ Tth(crit) Decreasing Tamb: 0 — Tamb < Tth(crit) − Thys 1 — Tamb ≥ Tth(crit) − Thys 14 AAW Above Alarm Window. Increasing Tamb: 0 — Tamb ≤ Ttrip(u) 1 — Tamb > Ttrip(u) Decreasing Tamb: 0 — Tamb ≤ Ttrip(u) − Thys 1 — Tamb > Ttrip(u) − Thys 13 BAW Below Alarm Window. Increasing Tamb: 0 — Tamb ≥ Ttrip(l) 1 — Tamb < Ttrip(l) Decreasing Tamb: 0 — Tamb ≥ Ttrip(l) − Thys 1 — Tamb < Ttrip(l) − Thys 12 SIGN Sign bit. 0 — positive temperature value 1 — negative temperature value 11:1 0 RFU Temperature Value (2’s complement). (LSB = 0.125 °C) reserved; always ‘0’ SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 31 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 8.7 MANID — Manufacturer’s ID register (06h, 16-bit read-only) The SE97B Manufacturer’s ID register is intended to match NXP Semiconductors PCI SIG (1131h). Table 24. Bit Symbol Default Access Bit Symbol Default Access 0 R 0 R 1 R 1 R 0 R 7 0 R 6 0 R 5 MANID - Manufacturer’s ID register bit allocation 15 14 13 12 1 R 4 (cont.) 0 R 0 R 0 R 1 R 11 0 R 3 10 0 R 2 9 0 R 1 8 1 R 0 Manufacturer ID 8.8 DEVICEID — Device ID register (07h, 16-bit read-only) The SE97B device ID is A2h. The device revision is 03h. Table 25. Bit Symbol Default Access Bit Symbol Default Access 0 R 0 R 0 R 1 R 7 0 R 6 1 R 5 DEVICEID - Device ID register bit allocation for SE97B 15 14 13 12 0 R 4 0 R 11 0 R 3 0 R 10 0 R 2 0 R 9 1 R 1 1 R 8 0 R 0 1 R Device ID Device revision SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 32 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 8.9 SMBUS — SMBus register (22h, 8-bit read/write) Table 26. Bit Symbol Default Access Bit Symbol 0 R 7 Disable Timeout 0 R/W 0 R 6 RFU 0 R 5 Enable SDTO 1 R/W 0 R 4 Event Sleep State 1 R/W SMBUS - SMBus Time-out register bit allocation 15 14 13 12 RFU 0 R 3 IntrClear Mode 0 R/W 0 R 2 Flag Update Mode 0 R/W 0 R 1 RFU 0 R 0 Disable ARA 1 R/W 11 10 9 8 Default Access Table 27. Bit 15:8 7 0 R 0 R SMBus Time-out register bit description Description reserved; always ‘0’ 0 — SMBus time-out is enabled (default) 1 — SMBus time-out is disabled When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked. Symbol RFU DisableTimeout Disable SMBus time-out. 6 5 RFU EnableSDTO reserved; always ‘0’ SMBus time-out during Shutdown (CONFIG[8]). 0 — disable SMBus time-out 1 — enable SMBus time-out (default) Remark: DisableTimeout bit must be a logic 0 to enable this feature. When either Critical Trip or Alarm Window lock bits are set, this bit cannot be altered until unlocked. 4 EventSleep State[1] State of EVENT output when SHMD bit is set. 0 — EVENT pin state is frozen 1 — EVENT pin is de-asserted, state based on Polarity bit (default) When either Critical Trip or Alarm Window lock bits are set, this bit cannot be altered until unlocked. 3 IntrClear Mode[2] Interrupt Flop Clearing Mode. 0 — allow clearing interrupt flop while in comparator mode (default) 1 — disable clearing interrupt flow while in comparator mode When either Critical Trip or Alarm Window lock bits are set, this bit cannot be altered until unlocked. 2 FlagUpdate Mode Update AAW, BAW and ACT flags after each new temperature conversion. 0 — update AAW, BAW and ACT flags continuously (default) 1 — update flags with new temperature conversion When either Critical Trip or Alarm Window lock bits are set, this bit cannot be altered until unlocked. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 33 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD SMBus Time-out register bit description …continued Description reserved; always ‘0’ Disable SMBus Alert Response Address (ARA). 0 — SMBus ARA is enabled 1 — disable SMBus ARA (default) When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked. Table 27. Bit 1 0 Symbol RFU DisableARA [1] When the part comes out of shutdown, the state of the EVENT pin will not change until after the first temperature conversion. When the part enters shutdown, the ACT (TEMP[15]), AAW (TEMP[14]) and BAW (TEMP[13]) bits (flip-flops) will be cleared. The STTS424E02 allows clearing the interrupt when in comparator mode, but the other competitors do not. [2] Table 28. Disable Timeout[1] 0 SMBus register setting guide Enable SHMD SDTO[2] [3] X 0 Thermal sensor behavior TS is active and SMBus TO is on TS is active and SMBus TO is off TS is disabled and SMBus TO is on SPD behavior Power mode Use JEDEC - SMBus for TS and SPD (like SE97 if TS is on) I2C-bus - no SMBus TO JEDEC - SMBus for TS and SPD SPD read/write and Full power, SMBus TO is on oscillator is running SPD read/write and Full power, SMBus TO is off oscillator is running SPD read/write and Lower power, SMBus TO is on oscillator is off unless bus active or write to SPD SPD low power read/write and SMBus TO is off SPD low power read-only and SMBus TO is off Lower power, oscillator is off unless write to the SPD Lowest power, oscillator is off all the time 1 0 X 1 0 1 1 1 1 TS is disabled and SMBus TO is off TS is disabled and SMBus TO is off I2C-bus - no SMBus TO I2C-bus - no SMBus TO (like SE97 if TS is off) X 0 1 [1] SMBus Time-out. 0 — enabled (default) 1 — disabled [2] Shutdown time-out. 0 — SMBus Time-out disabled when SHMD = 1 1 — SMBus Time-out enabled when SHMD = 1 (default) [3] Thermal Sensor Shutdown mode. 0 — active (default) 1 — shutdown SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 34 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 9. Application design-in information In a typical application, the SE97B behaves as a slave device and interfaces to a bus master (or host) via the SCL and SDA lines. The EVENT output is monitored by the host, and asserts when the temperature reading exceeds the programmed values in the alarm registers. The A0, A1 and A2 pins are directly connected to VDD or VSS without any pull-up resistors. The SDA and SCL serial interface pins are open-drain I/Os that require pull-up resistors, and are able to sink a maximum of 3 mA with a voltage drop less than 0.4 V. Typical pull-up values for SCL and SDA are 10 kΩ, but the resistor values can be changed in order to meet the rise time requirement if the capacitance load is too large due to routing, connectors, or multiple components sharing the same bus. 3.3 V slave VDD 10 kΩ (3×) master SCL SE97B A0 A1 A2 SDA EVENT HOST CONTROLLER VSS 002aae313 Fig 19. Typical application showing SE97B interfacing with 3.3 V host mother board 3.3 V 0.1 μF 0.1 μF 0.1 μF 10 kΩ 10 kΩ 10 kΩ 10 kΩ 1.0 V ± 5 % VCC(B) VCC(A) B2 A2 VDD SCL SCL SDA EVENT HOST CONTROLLER SE97B A0 A1 A2 SDA EVENT PCA9509 B1 A1 VSS EN 002aae314 Fig 20. SE97B interfacing with 1.0 V host controller SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 35 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 9.1 SE97B in memory module application Figure 21 shows the SE97B being placed in the memory module application. The SE97B is centered in the memory module to monitor the temperature of the DRAM and also to provide a 2-kbit EEPROM as the Serial Presence Detect (SPD). In the event of overheating, the SE97B triggers the EVENT output and the memory controller throttles the memory bus to slow the DRAM. The memory controller can also read the SE97B and watch the DRAM thermal behavior, taking preventive measures when necessary. DIMM DRAM DRAM SE97B DRAM DRAM SMBus EVENT MEMORY CONTROLLER CPU 002aae315 Fig 21. System application 9.2 Layout consideration The SE97B does not require any additional components other than the host controller to read its temperature. It is recommended that a 0.1 μF bypass capacitor between the VDD and VSS pins is located as close as possible to the power and ground pins for noise protection. 9.3 Thermal considerations In general, self-heating is the result of power consumption and not a concern, especially with the SE97B, which consumes very low power. In the event the SDA and EVENT pins are heavily loaded with small pull-up resistor values, self-heating affects temperature accuracy by approximately 0.5 °C. Equation 1 is the formula to calculate the effect of self-heating: Δ T = R th ( j - a ) × [ ( V DD × I DD ( AV ) ) + ( V OL ( SDA ) × I OL ( sin k ) ( SDA ) ) + ( V OL ( EVENT ) × I OL ( sin k ) EVENT ) ] where: ΔT = Tj − Tamb Tj = junction temperature Tamb = ambient temperature Rth(j-a) = package thermal resistance VDD = supply voltage IDD(AV) = average supply current SE97B_1 © NXP B.V. 2010. All rights reserved. (1) Product data sheet Rev. 01 — 27 January 2010 36 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD VOL(SDA) = LOW-level output voltage on pin SDA VOL(EVENT) = LOW-level output voltage on pin EVENT IOL(sink)(SDA) = SDA output current LOW IOL(sink)EVENT = EVENT output current LOW Calculation example: Tamb (typical temperature inside the notebook) = 50 °C IDD(AV) = 400 μA VDD = 3.6 V Maximum VOL(SDA) = 0.4 V IOL(sink)(SDA) = 1 mA VOL(EVENT) = 0.4 V IOL(sink)EVENT = 3 mA Rth(j-a) = 56 °C/W Self heating due to power dissipation is: Δ T = 56 × [ ( 3.6 × 0.4 ) + ( 0.4 × 3 ) + ( 0.4 × 1 ) ] = 56 ° C ⁄ W × 3.04 m W = 0.17 ° C (2) 9.4 Hot plugging The SE97B can be used in hot plugging applications. Internal circuitry prevents damaging current backflow through the device when it is powered down, but with the I2C-bus, EVENT or address pins still connected. The open-drain SDA and EVENT pins (SCL and address pins are input only) effectively places the outputs in a high-impedance state during power-up and power-down, which prevents driver conflict and bus contention. The 50 ns noise filter will filter out any insertion glitches from the state machine, which is very robust and not prone to false operation. The device needs a proper power-up sequence to reset itself, not only for the device I2C-bus and I/O initial states, but also to load specific pre-defined data or calibration data into its operational registers. The power-up sequence should occur correctly with a fast ramp rate and the I2C-bus active. The SE97B might not respond immediately after power-up, but it should not damage the part if the power-up sequence is abnormal. If the SCL line is held LOW, the part will not exit the power-on reset mode since the part is held in reset until SCL is released. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 37 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 10. Limiting values Table 29. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD Vn VA0 Isink Tj(max) Tstg Parameter supply voltage voltage on any other pin voltage on pin A0 sink current maximum junction temperature storage temperature SDA, SCL, A1, A2, EVENT pins overvoltage input; A0 pin SDA, EVENT pins Conditions Min −0.5 −0.5 −0.5 −1 −65 Max +4.3 +4.3 +12.5 +10 150 +165 Unit V V V mA °C °C 11. Characteristics Table 30. Thermal sensor characteristics VDD = 3.0 V to 3.6 V; Tamb = −40 °C to +125 °C; unless otherwise specified. Symbol Tlim(acc) Parameter temperature limit accuracy Conditions B-grade; VDD = 3.0 V to 3.6 V Tamb = 75 °C to 95 °C Tamb = 40 °C to 125 °C Tamb = −40 °C to +125 °C Tres Tconv Ef(conv) temperature resolution conversion period conversion rate error percentage error in programmed data −1.0 −2.0 −3.0 −30 < ±0.5 < ±1.0 < ±2 0.125 100 +1.0 +2.0 +3.0 120 30 °C °C °C °C ms % Min Typ Max Unit SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 38 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD Table 31. DC characteristics VDD = 3.0 V to 3.6 V; Tamb = −40 °C to +125 °C; unless otherwise specified. These specifications are guaranteed by design. Symbol VDD IDD(AV) IDD Isd(VDD) VIH VIL VI(ov) VOL Parameter supply voltage average supply current supply current supply voltage shutdown mode current HIGH-level input voltage LOW-level input voltage overvoltage input voltage LOW-level output voltage SMBus inactive fSCL = 400 kHz SMBus inactive SCL, SDA SCL, SDA pin A0; VI(ov) − VDD > 4.8 V SDA, EVENT IOL = 0.7 mA IOL = 2.1 mA IOL = 3.0 mA VI(hys) Vth(POR)H Vth(rec)POR ILOH ILIH ILIL hysteresis of input voltage HIGH-level power-on reset threshold voltage power-on reset recovery threshold voltage HIGH-level output leakage current HIGH-level input leakage current LOW-level input leakage current VDD ≥ 2.2 V VDD ≤ 2.2 V device operation voltage increase device reset voltage decrease EVENT; VOH = VDD SDA, SCL; VI = VDD SDA, SCL; VI = VSS A0, A1, A2; VI = VSS 0.05 × VDD 0.10 × VDD 1.2 −1.0 −1.0 −1.0 −1.0 internal; A0, A1, A2 pins; VI = 0.3VDD to VDD pins A0, A1, A2; VI < 0.3VDD pins A0, A1, A2; VI ≥ 0.3VDD 30 800 1.8 5 5 0.2 0.4 0.5 2.9 +1.0 +1.0 +1.0 +1.0 8 10 4.0 V V V V V V V μA μA μA μA pF pF μA kΩ kΩ [2] [1] Conditions Min 3.0 0.7 × VDD −0.5 7.0 Typ 210 250 0.1 - Max 3.6 320 400 10 VDD + 1 +0.3 × VDD 10 Unit V μA μA μA V V V Ci(SCL/SDA) SCL and SDA input capacitance Ci(addr) Ipd ZIL ZIH [1] [2] address input capacitance pull-down current LOW-level input impedance HIGH-level input impedance If the temperature sensor is not needed it should be placed in standby, which will reduce IDD(AV) to 0.1 μA typical at room temperature or 3.0 μA typical at 125 °C. High-voltage input voltage applied to pin A0 during RWP and CRWP operations. The JEDEC specification is 7 V (min.) and 10 V (max.). When VDD is 3.6 V, then II(ov) > 4.8 V + VDD or > 4.8 V + 3.6 V then the minimum voltage is 8.4 V. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 39 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 320 IDD(AV) (μA) 220 002aaf180 350 IDD(AV) (μA) 250 VDD = 3.6 V 3.0 V 002aaf181 VDD = 3.6 V 3.0 V 120 150 20 −40 0 40 80 120 Tamb (°C) 50 −40 0 40 80 120 Tamb (°C) I2C-bus inactive. fSCL = 400 kHz. Fig 22. Average supply current 5 Isd(VDD) (μA) 3 VDD = 3.6 V 3.0 V 002aaf182 Fig 23. Average supply current 0.20 VOL (V) 0.16 002aaf183 0.12 VDD = 3.6 V 3.0 V 0.08 1 0.04 −1 −40 0 40 80 120 Tamb (°C) 0 −40 0 40 80 120 Tamb (°C) Fig 24. Shutdown supply current 0.4 VOL (V) 0.3 002aaf184 Fig 25. SDA output VOL at IOL = 0.7 mA 0.4 VOL (V) 0.3 002aaf185 0.2 VDD = 3.6 V 3.0 V 0.1 0.2 VDD = 3.6 V 3.0 V 0.1 0 −40 0 40 80 120 Tamb (°C) 0 −40 0 40 80 120 Tamb (°C) Fig 26. SDA output VOL at IOL = 2.1 mA Fig 27. SDA output VOL at IOL = 3.0 mA SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 40 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 0.20 VOL (V) 0.16 002aaf186 0.20 VOL (V) 0.16 002aaf187 0.12 VDD = 3.6 V 3.0 V 0.12 VDD = 3.6 V 3.0 V 0.08 0.08 0.04 0.04 0 −40 0 40 80 120 Tamb (°C) 0 −40 0 40 80 120 Tamb (°C) Fig 28. EVENT output VOL at IOL = 0.7 mA 0.20 VOL (V) 0.16 002aaf188 Fig 29. EVENT output VOL at IOL = 2.1 mA 15 conversion rate (conv/s) 13 002aad886 0.12 VDD = 3.6 V 3.0 V 11 0.08 9 0.04 7 0 −40 0 40 80 120 Tamb (°C) 5 −40 0 40 80 120 Tamb (°C) Fig 30. EVENT output VOL at IOL = 3.0 mA 140 Tconv (ms) 120 002aad887 Fig 31. Conversion rate 5 Tcy(W) (ms) 4 002aad888 100 3 80 60 −40 0 40 80 120 Tamb (°C) 2 −40 0 40 80 120 Tamb (°C) Fig 32. Conversion period Fig 33. EEPROM write cycle time SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 41 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 3.0 Vth (V) 2.5 002aad889 2.0 Vth (V) 1.5 002aad890 2.0 1.0 1.5 0.5 1.0 −40 0 40 80 120 Tamb (°C) 0 −40 0 40 80 120 Tamb (°C) For temp sensor conversion. For EEPROM read operation. Fig 34. Average power-on threshold voltage 3.0 Vth (V) 2.5 002aae107 Fig 35. Average power-on threshold voltage 002aad892 5 temp error (˚C) 3 2.0 1 1.5 1.0 −40 0 40 80 120 Tamb (°C) −1 102 103 104 105 106 107 108 noise frequency (Hz) For EEPROM write operation. VDD = 3.3 V + 150 mV (p-p); 0.1 μF AC coupling capacitor; no decoupling capacitor; Tamb = 25 °C. Fig 36. Average power-on threshold voltage Fig 37. Temperature error versus power supply noise frequency SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 42 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 3.0 Tlim(acc) (°C) 1.5 002aaf189 120 thermal response (%) 80 002aaf178 0 40 −1.5 −3.0 −40 0 40 80 120 Tamb (°C) 0 0 1 2 3 4 time (s) 5 From 25 °C (air) to 120 °C (oil bath) at 3.3 V. Fig 38. SE97B temperature accuracy Fig 39. Package thermal response SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 43 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD Table 32. SMBus AC characteristics VDD = 3.0 V to 3.6 V; Tamb = −40 °C to +125 °C; unless otherwise specified. These specifications are guaranteed by design. The AC specifications fully meet or exceed SMBus 2.0 specifications, but allow the bus to interface with the I2C-bus from DC to 400 kHz. Symbol fSCL tHIGH tLOW tto(SMBus) tr tf tSU;DAT th(i)(D) tHD;DAT tSU;STA tHD;STA tSU;STO tBUF tSP Parameter SCL clock frequency HIGH period of the SCL clock 70 % to 70 % LOW period of the SCL clock 30 % to 30 % SMBus time-out time rise time of both SDA and SCL signals fall time of both SDA and SCL signals data set-up time data input hold time data hold time set-up time for a repeated START condition hold time (repeated) START condition set-up time for STOP condition bus free time between a STOP and START condition pulse width of spikes that must be suppressed by the input filter data valid time output fall time power-on reset pulse time read power-up time write power-up time write cycle time power supply falling [8] [8] [2] [2][3] [4] [5] Conditions Standard mode Min 10[1] 4000 4700 25 250 0 200 4700 4000 4000 4700 Max 100 35 1000 300 3450 50 Fast mode Min 10[1] 600 1300 25 20 100 0 200 600 600 600 1300 Max 400 35 300 300 900 50 Unit kHz ns ns ms ns ns ns ns ns ns ns ns ns ns LOW period to reset SMBus 30 % of SDA to 70 % of SCL [6] tVD;DAT tf(o) tPOR tpu(R) tpu(W) Tcy(W) [1] [2] [3] [4] [5] [6] [7] [8] from clock 200 0.5 - 1 1 10 200 0.5 - 250 1 1 10 ns ns μs ms ms ms EEPROM power-up timing[7] Write cycle limits [9] Minimum clock frequency is 0 kHz if SMBus Timeout is disabled. Delay from SDA STOP to SDA START. A device must internally provide a hold time of at least 200 ns for SDA signal (referenced to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Delay from SCL HIGH-to-LOW transition to SDA edges. Delay from SCL LOW-to-HIGH transition to restart SDA. Delay from SDA START to first SCL HIGH-to-LOW transition. These parameters tested initially and after a design or process change that affects the parameter. tpu(R) and tpu(W) are the delays required from the time VDD is stable until the specified operation can be initiated. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 44 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD [9] The write cycle time is the time elapsed between the STOP command (following the write instruction) and the completion of the internal write cycle. During the internal write cycle, SDA is released by the slave and the device does not acknowledge external commands. tLOW tr SCL tBUF tHD;STA tHD;DAT tHIGH tSU;DAT tSU;STA tHD;DAT VIH VIL P S S P tSU;STO tf VIH VIL SDA SCL tSU;STO tSU;STA VIH VIL SDA tW STOP condition write cycle START condition VIH VIL 002aae750 S = START condition P = STOP condition Fig 40. AC waveforms SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 45 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 12. Package outline HWSON8: plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.8 mm SOT1069-2 X D B A A2 E A A1 A3 terminal 1 index area e1 terminal 1 index area 1 L K e b 4 v w CAB C y1 C detail X C y E2 8 D2 5 0 Dimensions Unit mm A(1) A1 A2 A3 0.2 b 0.30 0.25 0.18 D(1) 2.1 2.0 1.9 D2 1.6 1.5 1.4 E(1) 3.1 3.0 2.9 E2 1.6 1.5 1.4 1 scale e 0.5 e1 1.5 2 mm K L v 0.1 w y y1 max 0.80 0.05 0.65 nom 0.75 0.02 0.55 min 0.70 0.00 0.45 0.40 0.45 0.35 0.40 0.30 0.35 0.05 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT1069-2 References IEC --JEDEC MO-229 JEITA --European projection sot1069-2_po Issue date 09-10-22 09-11-18 Fig 41. Package outline SOT1069-2 (HWSON8) SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 46 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 47 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 42) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 33 and 34 Table 33. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 34. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 42. SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 48 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 42. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 35. Acronym ADC ARA CDM CPU DDR DIMM DRAM EEPROM ESD HBM I2C-bus LSB MM MSB PC PCB POR Abbreviations Description A-to-D Converter Alert Response Address Charged Device Model Central Processing Unit Double Data Rate Dual In-line Memory Module Dynamic Random Access Memory Electrically Erasable Programmable Read-Only Memory ElectroStatic Discharge Human Body Model Inter-Integrated Circuit bus Least Significant Bit Machine Model Most Significant Bit Personal Computer Printed-Circuit Board Power-On Reset SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 49 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD Abbreviations …continued Description System Management Bus Small Outline Dual In-line Memory Module Serial Presence Detect Table 35. Acronym SMBus SO-DIMM SPD 15. Revision history Table 36. SE97B_1 Revision history Release date 20100127 Data sheet status Product data sheet Change notice Supersedes Document ID SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 50 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 51 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 18. Contents General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General features . . . . . . . . . . . . . . . . . . . . . . . . 2 Temperature sensor features . . . . . . . . . . . . . . 2 Serial EEPROM features . . . . . . . . . . . . . . . . . 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Serial bus interface . . . . . . . . . . . . . . . . . . . . . . 6 Slave address . . . . . . . . . . . . . . . . . . . . . . . . . . 6 EVENT output condition . . . . . . . . . . . . . . . . . . 7 EVENT pin output voltage levels and resistor sizing. . . . . . . . . . . . . . . . . . . . . . . 7 7.3.2 EVENT thresholds . . . . . . . . . . . . . . . . . . . . . . 9 7.3.2.1 Alarm window . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.3.2.2 Critical trip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.3.3 EVENT operation modes . . . . . . . . . . . . . . . . 10 7.3.3.1 Comparator mode. . . . . . . . . . . . . . . . . . . . . . 10 7.3.3.2 Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . 10 7.3.3.3 Switching between Comparator mode and Interrupt mode . . . . . . . . . . . . . . . . . . . . . 10 7.4 Conversion rate . . . . . . . . . . . . . . . . . . . . . . . 11 7.4.1 What temperature is read when conversion is in progress . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.5 Power-up default condition . . . . . . . . . . . . . . . 11 7.6 Device initialization . . . . . . . . . . . . . . . . . . . . . 11 7.7 SMBus TIMEOUT . . . . . . . . . . . . . . . . . . . . . . 12 7.8 SMBus Alert Response Address (ARA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.9 SMBus/I2C-bus interface . . . . . . . . . . . . . . . . 13 7.10 EEPROM operation . . . . . . . . . . . . . . . . . . . . 15 7.10.1 Write operations . . . . . . . . . . . . . . . . . . . . . . . 16 7.10.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.10.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.10.1.3 Acknowledge polling . . . . . . . . . . . . . . . . . . . . 17 7.10.2 Memory Protection . . . . . . . . . . . . . . . . . . . . . 17 7.10.2.1 Permanent Write Protection (PWP) . . . . . . . . 18 7.10.2.2 Reversible Write Protection (RWP) and Clear Reversible Write Protection (CRWP) . . 19 7.10.2.3 Read Permanent Write Protection (RPWP), Read Reversible Write Protection (RRWP), and Read Clear Reversible Write Protection (RCRWP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.10.3 Read operations. . . . . . . . . . . . . . . . . . . . . . . 7.10.3.1 Current address read . . . . . . . . . . . . . . . . . . . 7.10.3.2 Selective read . . . . . . . . . . . . . . . . . . . . . . . . 7.10.3.3 Sequential read . . . . . . . . . . . . . . . . . . . . . . . 8 Register descriptions . . . . . . . . . . . . . . . . . . . 8.1 Register overview . . . . . . . . . . . . . . . . . . . . . 8.2 CAP — Capability register (00h, 16-bit read-only) . . . . . . . . . . . . . . . . . . 8.3 CONFIG — Configuration register (01h, 16-bit read/write). . . . . . . . . . . . . . . . . . 8.4 Temperature format . . . . . . . . . . . . . . . . . . . . 8.5 Temperature Trip Point registers . . . . . . . . . . 8.5.1 UPPER — Upper Boundary Alarm Trip register (02h, 16-bit read/write) . . . . . . . . . . . 8.5.2 LOWER — Lower Boundary Alarm Trip register (03h, 16-bit read/write) . . . . . . . . . . . 8.5.3 CRITICAL — Critical Alarm Trip register (04h, 16-bit read/write). . . . . . . . . . . . . . . . . . 8.6 TEMP — Temperature register (05h, 16-bit read-only) . . . . . . . . . . . . . . . . . . 8.7 MANID — Manufacturer’s ID register (06h, 16-bit read-only) . . . . . . . . . . . . . . . . . . 8.8 DEVICEID — Device ID register (07h, 16-bit read-only) . . . . . . . . . . . . . . . . . . 8.9 SMBUS — SMBus register (22h, 8-bit read/write). . . . . . . . . . . . . . . . . . . 9 Application design-in information. . . . . . . . . 9.1 SE97B in memory module application . . . . . . 9.2 Layout consideration . . . . . . . . . . . . . . . . . . . 9.3 Thermal considerations . . . . . . . . . . . . . . . . . 9.4 Hot plugging. . . . . . . . . . . . . . . . . . . . . . . . . . 10 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 11 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 13 Soldering of SMD packages . . . . . . . . . . . . . . 13.1 Introduction to soldering. . . . . . . . . . . . . . . . . 13.2 Wave and reflow soldering. . . . . . . . . . . . . . . 13.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 13.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information . . . . . . . . . . . . . . . . . . . . . . 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 20 21 22 22 23 24 28 29 29 30 30 31 32 32 33 35 36 36 36 37 38 38 46 47 47 47 47 48 49 50 51 51 51 51 51 continued >> SE97B_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 27 January 2010 52 of 53 NXP Semiconductors SE97B DDR memory module temp sensor with integrated SPD 17 18 Contact information. . . . . . . . . . . . . . . . . . . . . 51 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 January 2010 Document identifier: SE97B_1