SE98

SE98 DDR memory module temp sensor, 3.3 V Rev. 04 — 2 February 2009 Product data sheet 1. General description The NXP Semiconductors SE98 measures temperature from −40 °C to +125 °C communicating via the I2C-bus/SMBus. It is typically mounted on a Dual In-line Memory Module (DIMM) measuring the DRAM temperature in accordance with the new JEDEC (JC-42.4) Mobile Platform Memory Module Thermal Sensor Component specification. Placing the Temp Sensor (TS) on DIMM allows accurate monitoring of the DIMM module temperature to better estimate the DRAM case temperature (Tcase) to prevent it from exceeding the maximum operating temperature of 85 °C. The chip set throttles the memory traffic based on the actual temperatures instead of the calculated worst-case temperature or the ambient temperature using a temp sensor mounted on the motherboard. There is up to a 30 % improvement in thin and light notebooks that are using one or two 1G SO-DIMM modules, although other memory modules such as in server applications will also see an increase in system performance. Future uses of the TS will include more dynamic control over thermal throttling, the ability to use the Alarm Window to create multiple temperature zones for dynamic throttling and to save processor time by scaling the memory refresh rate. The TS consists of an Analog-to-Digital Converter (ADC) that monitors and updates its own temperature readings 8 times per second, converts the reading to a digital data, and latches them into the data temperature registers. User-programmable registers, such as Shutdown or Low-power modes and the specification of temperature event and critical output boundaries, provide flexibility for DIMM temperature-sensing applications. When the temperature changes beyond the specified boundary limits, the SE98 outputs an EVENT signal. The user has the option of setting the EVENT output signal polarity as either an active LOW or active HIGH comparator output for thermostat operation, or as a temperature event interrupt output for microprocessor-based systems. The EVENT output can even be configured as a critical temperature output. The SE98 supports the industry-standard 2-wire I2C-bus/SMBus serial interface. The SMBus TIMEOUT function is supported to prevent system lock-ups. Manufacturer and Device ID registers provide the ability to confirm the identify of the device. Three address pins allow up to eight devices to be controlled on a single bus. To maintain interchangeability with the I2C-bus/SMBus interface the electrical specifications are specified with the operating voltage of 3.0 V to 3.6 V. NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 2. Features 2.1 General features I I I I I I JEDEC (JC-42.4) SO-DIMM temperature sensor Optimized for voltage range: 3.0 V to 3.6 V Shutdown/Standby current: 8 µA (typ.) and 15 µA (max.) 2-wire interface: I2C-bus/SMBus compatible, 0 Hz to 400 kHz SMBus ALERT and TIMEOUT (programmable) Available packages: TSSOP8 and HVSON8 2.2 Temperature sensor features I I I I I Temperature-to-Digital converter Operating current: 200 µA (typ.) and 250 µA (max.) Programmable hysteresis threshold: 0 °C, 1.5 °C, 3 °C, 6 °C Over/under/critical temperature EVENT output C grade accuracy: N ±1 °C/±2 °C (typ./max.) → +75 °C to +95 °C N ±2 °C/±3 °C (typ./max.) → +40 °C to +125 °C N ±3 °C/±4 °C (typ./max.) → −40 °C to +125 °C 3. Applications I I I I DDR2 and DDR3 memory modules Laptops, personal computers and servers Enterprise networking Hard disk drives and other PC peripherals 4. Ordering information Table 1. Ordering information Topside mark SE98 SE98 Package Name TSSOP8 HVSON8 Description plastic thin shrink small outline package; 8 leads; body width 4.4 mm plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 × 3 × 0.85 mm Version SOT530-1 SOT908-1 Type number SE98PW SE98TK SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 2 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 5. Block diagram SE98 REGISTERS A0 CRITICAL TEMPERATURE LIMIT LOCK PROTECT UPPER TEMPERATURE LIMIT LOWER TEMPERATURE LIMIT HYSTERESIS THRESHOLD TEMPERATURE REGISTER 11-BIT ∆Σ ADC BAND GAP TEMPERATURE SENSOR VDD A1 A2 MANUFACTURER ID DEVICE ID DEVICE CAPABILITY REGISTER CONTROL LOGIC EVENT CONFIGURATION REGISTER VSS EVENT OUTPUT COMPARATOR/INT MODE EVENT OUTPUT POLARITY ENABLE/DISABLE EVENT OUTPUT EVENT OUTPUT STATUS SENSOR ENABLE/SHUTDOWN I2C-bus/SMBus INTERFACE SCL SDA POR CIRCUIT 002aab280 Fig 1. Block diagram of SE98 SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 3 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 6. Pinning information 6.1 Pinning terminal 1 index area A0 A1 A2 A0 A1 A2 VSS 1 2 3 4 002aab806 1 2 8 7 VDD EVENT SCL SDA SE98TK 3 4 6 5 8 VDD EVENT SCL SDA 002aab804 SE98PW 7 6 5 VSS Transparent top view Fig 2. Pin configuration for TSSOP8 Fig 3. Pin configuration for HVSON8 6.2 Pin description Table 2. Symbol A0[1] A1 A2 VSS SDA SCL EVENT VDD [1] Pin description Pin 1 2 3 4 5 6 7 8 Type I I I ground I/O I O power Description I2C-bus/SMBus slave address bit 0 I2C-bus/SMBus slave address bit 1 I2C-bus/SMBus slave address bit 2 device ground SMBus/I2C-bus serial data input/output (open-drain). Must have external pull-up resistor. SMBus/I2C-bus serial clock input/output (open-drain). Must have external pull-up resistor. Thermal alarm output for high/low and critical temperature limit (open-drain). Must have external pull-up resistor. device power supply (3.0 V to 3.6 V) In general, application of 10 V on the A0 pin would not damage the pin, but NXP Semiconductors does not guarantee the overvoltage for this pin. SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 4 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 7. Functional description 7.1 Serial bus interface The SE98 uses the 2-wire serial bus (I2C-bus/SMBus) to communicate with a host controller. The serial bus consists of a clock (SCL) and data (SDA) signals. The device can operate on either the I2C-bus Standard/Fast mode or SMBus. The I2C-bus Standard-mode is defined to have bus speeds from 0 Hz to 100 kHz, I2C-bus Fast-mode from 0 Hz to 400 kHz, and the SMBus is from 10 kHz to 100 kHz. The host or bus master generates the SCL signal, and the SE98 uses the SCL signal to receive or send data on the SDA line. Data transfer is serial, bidirectional, and is one bit at a time with the Most Significant Bit (MSB) transferred first, and a complete I2C-bus data is 1 byte. Since SCL and SDA are open-drain, pull-up resistors must be installed on these pins. 7.2 Slave address The SE98 uses a 4-bit fixed and 3-bit programmable (A0, A1 and A2) 7-bit slave address that allows a total of eight devices to co-exist on the same bus. The input of each pin is sampled at the start of each I2C-bus/SMBus access. The temperature sensor’s fixed address is 0011. slave address MSB 0 0 1 1 A2 A1 LSB A0 R/W X fixed hardware selectable 002aab304 Fig 4. Slave address SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 5 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 7.3 EVENT output condition The EVENT output indicates conditions such as the temperature crossing a predefined boundary. The EVENT modes are very configurable and selected using the configuration register (CONFIG). The interrupt mode or comparator mode is selected using CONFIG[0], using either TCRIT/UPPER/LOWER or TCRIT only temperature bands (CONFIG[2]) as modified by hysteresis (CONFIG[10:9]). The UPPER/LOWER (CONFIG[6]) and TCRIT (CONFIG[7]) bands can be locked. Figure 5 shows an example of the measured temperature versus time, with the corresponding behavior of the EVENT output in each of these modes. Upon device power-up, the default condition for the EVENT output is high-impedance to prevent spurious or unwanted alarms, but can be later enabled (CONFIG[3]). EVENT output polarity can be set to active HIGH or active LOW (CONFIG[1]). EVENT status can be read (CONFIG[4]) and cleared (CONFIG[5]). • Advisory note: – NXP device: After power-up, bit 3 (1) and bit 2 or bit 0 (leave as 0 or 1) can be set at the same time (e.g., in same byte) but once bit 3 is set (1) then changing bit 2 or bit 0 has no effect on the device operation. – Competitor device: Does not require that bit 3 be cleared (e.g., set back to (0)) before changing bit 2 or bit 0. – Work-around: In order to change bit 2 or bit 0 once bit 3 (1) is set, bit 3 (0) must be cleared in one byte and then change bit 2 or bit 0 and reset bit 3 (1) in the next byte. – SE98B will allow bit 2 or bit 0 to be changed even if bit 3 is set. If the device enters Shutdown mode (CONFIG[8]) with asserted EVENT output, the output remains asserted during shutdown. 7.3.1 EVENT pin output voltage levels and resistor sizing The EVENT open-drain output is typically pulled up to a voltage level from 0.9 V to 3.6 V with an external pull-up resistor, but there is no real lower limit on the pull-up voltage for the EVENT pin since it is simply an open-drain output. It could be pulled up to 0.1 V and would not affect the output. From the system perspective, there will be a practical limit. That limit will be the voltage necessary for the device monitoring the interrupt pin to detect a HIGH on its input. A possible practical limit for a CMOS input would be 0.4 V. Another thing to consider is the value of the pull-up resistor. When a low supply voltage is applied to the drain (through the pull-up resistor) it is important to use a higher value pull-up resistor, to allow a larger maximum signal swing on the EVENT pin. SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 6 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V temperature (°C) critical Upper Boundary Alarm Tamb Ttrip(u) − Thys Tth(crit) − Thys Ttrip(u) − Thys Ttrip(l) − Thys Lower Boundary Alarm Ttrip(l) − Thys time EVENT in Comparator mode EVENT in Interrupt mode software interrupt clear EVENT in ‘Critical Temp only’ mode (1) (2) (1) (3) (4) (3) (5) * (6) (4) (2) 002aae324 Refer to Table 3 for figure note information. Fig 5. Table 3. Figure note EVENT output condition EVENT output condition EVENT output boundary conditions EVENT output Comparator mode Interrupt mode Critical Temp only mode Temperature Register Status bits Bit 15 Above Critical Trip 0 0 0 0 1 0 Bit 14 Above Alarm Window 0 0 1 0 1 1 Bit 13 Below Alarm Window 0 1 0 0 0 0 (1) (2) (3) (4) (5) (6) Tamb ≥ Ttrip(l) Tamb < Ttrip(l) − Thys Tamb > Ttrip(u) Tamb ≤ Ttrip(u) − Thys Tamb ≥ Tth(crit) Tamb < Tth(crit) − Thys H L L H L L L L L L L H H H H H L H When Tamb ≥ Tth(crit) and Tamb < Tth(crit) − Thys the EVENT output is in Comparator mode and bit 0 of CONFIG (EVENT output mode) is ignored. SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 7 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 7.3.2 EVENT thresholds 7.3.2.1 Alarm window The device provides a comparison window with an UPPER trip point and a LOWER trip point, programmed through the Upper Boundary Alarm Trip register (02h), and Lower Boundary Alarm Trip register (03h). The Upper Boundary Alarm Trip register holds the upper temperature trip point, while the Lower Boundary Alarm Trip register holds the lower temperature trip point as modified by hysteresis as programmed in the Configuration register. When enabled, the EVENT output triggers whenever entering or exiting (crossing above or below) the alarm window. • Advisory note: – NXP Device: The EVENT output can be cleared through the Clear EVENT bit or SMBus Alert. – Competitor Device: The EVENT output can be cleared only through the Clear EVENT bit. – Work-around: Only clear EVENT output using the EVENT bit. – There will be no change to the NXP device. The Upper Boundary Alarm Trip should always be set above the Lower Boundary Alarm Trip. • Advisory note: – NXP device: Requires one conversion cycle (125 ms) after setting the alarm window before comparing the alarm limit with temperature register to ensure that there is correct data in the temperature register before comparing with the Alarm Window and operating EVENT output. – Competitor devices: Compares the alarm limit with temperature register at any time, so they get the EVENT output immediately when new UPPER or LOWER and Event B3 are set at the same time. – Work-around: Wait at least 125 ms before enabling EVENT output. – SE98B will compare alarm window and temperature register immediately after setting. 7.3.2.2 Critical trip The Tth(crit) temperature setting is programmed in the Critical Alarm Trip register (04h) as modified by hysteresis as programmed in the Configuration register. When the temperature reaches the critical temperature value in this register (and EVENT is enabled), the EVENT output asserts and cannot be de-asserted until the temperature drops below the critical temperature threshold. The Event cannot be cleared through the Clear EVENT bit or SMBus Alert. The Critical Alarm Trip should always be set above the Upper Boundary Alarm Trip. • Advisory note: – NXP device: Requires one conversion cycle (125 ms) after setting the alarm window before comparing the alarm limit with temperature register to ensure that there is correct data in the temperature register before comparing with the Alarm Window and operating EVENT output. SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 8 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V – Competitor devices: Compares the alarm limit with temperature register at any time, so they get the EVENT output immediately when new Tth(crit) and Event B3 are set at the same time. – Work-around: Wait at least 125 ms before enabling EVENT output. Intel will change Nehalem BIOS so that Tth(crit) is set for more than 125 ms before Event B3 is enabled and Event value is checked. 1. Set Tth(crit). 2. Doing something else (make sure that exceeds 125 ms). 3. Enable the EVENT output (B3 = 1). 4. Wait 20 µs. 5. Read Event value. – SE98B will compare alarm window and temperature register immediately after setting. 7.3.3 Event operation modes 7.3.3.1 Comparator mode In comparator mode, the EVENT output behaves like a window-comparator output that asserts when the temperature is outside the window (e.g., above the value programmed in the Upper Boundary Alarm Trip register or below the value programmed in the Lower Boundary Alarm Trip register or above the Critical Alarm Trip resister if Tth(crit) only is selected). Reads/writes on the registers do not affect the EVENT output in comparator mode. The EVENT signal remains asserted until the temperature goes inside the alarm window or the window thresholds are reprogrammed so that the current temperature is within the alarm window. The comparator mode is useful for thermostat-type applications, such as turning on a cooling fan or triggering a system shutdown when the temperature exceeds a safe operating range. 7.3.3.2 Interrupt mode In interrupt mode, EVENT asserts whenever the temperature crosses an alarm window threshold. After such an event occurs, writing a 1 to the Clear EVENT bit in the configuration register de-asserts the EVENT output until the next trigger condition occurs. In interrupt mode, EVENT asserts when the temperature crosses the alarm upper boundary. If the EVENT output is cleared and the temperature continues to increase until it crosses the critical temperature threshold, EVENT asserts again. Because the temperature is greater than the critical temperature threshold, a Clear EVENT command does not clear the EVENT output. Once the temperature drops below the critical temperature, EVENT de-asserts immediately. • Advisory note: – NXP device: If the EVENT output is not cleared before the temperature goes above the critical temperature threshold EVENT de-asserts immediately when temperature drops below the critical temperature. SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 9 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V – Competitor devices: If the EVENT output is not cleared before or when the temperature is in the critical temperature threshold, EVENT will remain asserted after the temperature drops below the critical temperature until a Clear EVENT command. – Work-around: Always clear the EVENT output before temperature exceeds the critical temperature. – SE98B will keep EVENT asserted after the temperature drops below the critical temperature until a Clear EVENT command de-asserts EVENT. 7.4 Conversion rate The conversion time is the amount of time required for the ADC to complete a temperature measurement for the local temperature sensor. The conversion rate is the inverse of the conversion period which describes the number of cycles the temperature measurement completes in one second—the faster the conversion rate, the faster the temperature reading is updated. The SE98’s conversion rate is at least 8 Hz or 125 ms. 7.5 Power-up default condition After power-on, the SE98 is initialized to the following default condition: • • • • • Starts monitoring local sensor EVENT register is cleared—EVENT output is pulled HIGH by external pull-ups EVENT hysteresis is defaulted to 0 °C Command pointer is defaulted to ‘00h’ Critical Temp, Alarm Temperature Upper and Lower Boundary Trip register are defaulted to 0 °C • Capability register is defaulted to ‘0015h’ • Operational mode: comparator • SMBus register is defaulted to ‘00h’ 7.6 Device initialization SE98 temperature sensors have programmable registers, which, upon power-up, default to zero. The open-drain EVENT output is default to being disabled, comparator mode and active LOW. The alarm trigger registers default to being unprotected. The configuration registers, upper and lower alarm boundary registers and critical temperature window are defaulted to zero and need to be programmed to the desired values. SMBus TIMEOUT feature defaults to being enabled and can be programmed to disable. These registers are required to be initialized before the device can properly function. Except for the SPD, which does not have any programmable registers, and does not need to be initialized. Table 4 shows the default values and the example value to be programmed to these registers. SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 10 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V Registers to be initialized Default value 0000h Example value 0209h Description Configuration register Table 4. Register 01h • • • 02h 03h 04h 22h 0000h 0000h 0000h 0000h 0550h 1F40h 05F0h 0000h hysteresis = 1.5 °C EVENT output = Interrupt mode EVENT output is enabled Upper Boundary Alarm Trip register = 85 °C Lower Boundary Alarm Trip register = −20 °C Critical Alarm Trip register = 95 °C SMBus register = no change 7.7 SMBus time-out The SE98 supports the SMBus time-out feature. If the host holds SCL LOW between 25 ms and 35 ms, the SE98 would reset its internal state machine to the bus idle state to prevent the system bus hang-up. This feature is turned on by default. The SMBus time-out is disabled by writing a logic 1 to bit 7 of register 22h. Remark: When SMBus time-out is enabled, the I2C-bus minimum bus speed is limited by the SMBus time-out timer, and goes down to only 10 kHz. 7.8 SMBus Alert The SE98 supports SMBus Alert when it is programmed for the Interrupt mode and when the EVENT polarity bit is set to logic 0. The EVENT pin can be ANDed with other EVENT or ALERT signals from other slave devices to signal their intention to communicate with the host controller. When the host detects EVENT or ALERT signal LOW, it issues an Alert Response Address (ARA) to which a slave device would respond with its address. When there are multiple slave devices generating an Alert the SE98 performs bus arbitration. If it wins the bus, it responds to the ARA and then clears the EVENT pin. Remark: Either in comparator mode or when the SE98 crosses the critical temperature, the host must also read the EVENT status bit and provide remedy to the situation by bringing the temperature to within the alarm window or below the critical temperature if that bit is set. Otherwise, the EVENT pin will not get de-asserted. START bit read Alert Response Address 0 0 1 1 0 0 1 acknowledge device address 0 0 0 1 1 A2 not acknowledge STOP bit S host detects SMBus ALERT 0 A1 A0 0 1 P master sends a START bit, ARA and a read command Slave acknowledges and sends its slave address. The last bit of slave address is hard coded '0'. host NACK and sends a STOP bit 002aab330 Fig 6. How SE98 responds to SMBus Alert SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 11 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 7.9 SMBus/I2C-bus interface The data registers in this device are selected by the Pointer register. At power-up, the Pointer register is set to ‘00’, the location for the Capability register. The Pointer register latches the last location it was set to. Each data register falls into one of three types of user accessibility: • Read only • Write only • Write/Read same address. A ‘write’ to this device will always include the address byte and the pointer byte. A write to any register other than the Pointer register requires two data bytes. Reading this device can take place either of two ways: • If the location latched in the Pointer register is correct (most of the time it is expected that the Pointer register will point to one of the Temperature register (as it will be the data most frequently read), then the read can simply consist of an address byte, followed by retrieving the two data bytes. • If the Pointer register needs to be set, then an address byte, pointer byte, repeat START, and another address byte will accomplish a read. The data byte has the most significant bit first. At the end of a read, this device can accept either Acknowledge (ACK) or No Acknowledge (NACK) from the Master (No Acknowledge is typically used as a signal for the slave that the Master has read its last byte). It takes this device 125 ms to measure the temperature. Refer to the timing diagrams in Figure 7, Figure 8, Figure 9 and Figure 10 on how to program the device. 1 SCL SDA S START A6 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 A5 A4 A3 A2 A1 A0 W A ACK by device D7 D6 D5 D4 D3 D2 D1 D0 A P ACK STOP by device 002aab308 device address and write register address A = ACK = Acknowledge bit. W = Write bit = 0. R = Read bit = 1. Fig 7. SMBus/I2C-bus write to the Pointer register SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 12 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 1 SCL SDA S START by host 1 SCL SDA by host D15 A6 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 (cont.) A5 A4 A3 A2 A1 A0 W A D7 ACK by device 8 9 1 D6 D5 D4 D3 D2 D1 D0 A (cont.) device address and write 2 3 4 5 6 7 write register address 2 3 4 5 6 7 ACK by device 8 9 D14 D13 D12 D11 D10 D9 D8 A ACK by device D7 D6 D5 D4 D3 D2 D1 D0 A P ACK STOP by device by host 002aab412 most significant byte data least significant byte data A = ACK = Acknowledge bit. W = Write bit = 0. R = Read bit = 1. Fig 8. SMBus/I2C-bus write to the Pointer register followed by a write data word 1 SCL SDA S START by host 1 SCL SDA SR repeated START by host SCL SDA D15 A6 A6 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 (cont.) A5 A4 A3 A2 A1 A0 W A ACK by device D7 D6 D5 D4 D3 D2 D1 D0 A (cont.) ACK by device device address and write 2 3 4 5 6 7 8 read register address 9 (cont.) A5 A4 A3 A2 A1 A0 R A ACK by device (cont.) device address and read 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 D14 D13 D12 D11 D10 D9 D8 A ACK by host D7 D6 D5 D4 D3 D2 D1 D0 NA P NACK STOP by host by host 002aab413 returned most significant byte data returned least significant byte data A = ACK = Acknowledge bit. NA = Not Acknowledge bit. W = Write bit = 0. R = Read bit = 1. Fig 9. SMBus/I2C-bus write to Pointer register followed by a repeat START and an immediate data word read SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 13 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 1 SCL SDA S START by host 1 SCL SDA D15 A6 2 3 4 5 6 7 8 9 (cont.) A5 A4 A3 A2 A1 A0 R A ACK by device (cont.) device address and read 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 D14 D13 D12 D11 D10 D9 D8 A ACK by host D7 D6 D5 D4 D3 D2 D1 D0 NA P NACK STOP by host 002aab414 returned most significant byte data returned least significant byte data A = ACK = Acknowledge bit. NA = Not Acknowledge bit. W = Write bit = 0. R = Read bit = 1. Fig 10. SMBus/I2C-bus word read from register with a pre-set pointer 7.10 Hot plugging The SE98 can be used in hot plugging applications. Internal circuitry prevents damaging current backflow through the device when it is powered down, but with the I2C-bus, EVENT or address pins still connected. The open-drain SDA and EVENT pins (SCL and address pins are input only) effectively places the outputs in a high-impedance state during power-up and power-down, which prevents driver conflict and bus contention. The 50 ns noise filter will filter out any insertion glitches from the state machine, which is very robust and not prone to false operation. The device needs a proper power-up sequence to reset itself, not only for the device I2C-bus and I/O initial states, but also to load specific pre-defined data or calibration data into its operational registers. The power-up sequence should occur correctly with a fast ramp rate and the I2C-bus active. The SE98 might not respond immediately after power-up, but it should not damage the part if the power-up sequence is abnormal. If the SCL line is held LOW, the part will not exit the power-on reset mode since the part is held in reset until SCL is released. SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 14 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 8. Register descriptions 8.1 Register overview This section describes all the registers used in the SE98. The registers are used for latching the temperature reading, storing the low and high temperature limits, configuring, the hysteresis threshold and the ADC, as well as reporting status. The device uses the Pointer register to access these registers. Read registers, as the name implies, are used for read only, and the write registers are for write only. Any attempt to read from a write-only register will result in reading zeroes. Writing to a read-only register will have no effect on the read even though the write command is acknowledged. The Pointer register is an 8-bit register. All other registers are 16-bit. Table 5. Address n/a 00h 01h 02h 03h 04h 05h 06h 07h 08h to 21h 22h 23h to FFh Register summary POR state n/a 0015h 0000h 0000h 0000h 0000h n/a 1131h A101h 0000h 0000h 0000h Register name Pointer register Capability register C grade = 0015h Configuration register Upper Boundary Alarm Trip register Lower Boundary Alarm Trip register Critical Alarm Trip register Temperature register Manufacturer ID register Device ID/Revision register reserved registers SMBus register reserved registers A write to reserved registers my cause unexpected results which may result in requiring a reset by removing and re-applying its power. SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 15 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 8.2 Capability register (00h, 16-bit read-only) Table 6. Bit Symbol Reset Access Bit Symbol Reset Access 0 R Table 7. Bit 15:5 4:3 2 1 0 0 R 7 0 R 6 RFU[2:0] 0 R 0 R 1 R 0 R 5 0 R 4 TRES[1:0] 0 R Capability register (address 00h) bit allocation 15 14 13 12 RFU[10:3] 0 R 3 0 R 2 WRNG 1 R 0 R 1 HACC 0 R 0 R 0 BCAP 1 R 11 10 9 8 Capability register (address 00h) bit description Symbol RFU TRES WRNG HACC BCAP Description Reserved for future use. Must be zero. Temperature resolution. 10 — 0.125 °C LSB (11-bit) Wider range. 1 — can read temperatures below 0 °C and set sign bit accordingly Higher accuracy (set during manufacture). 0 — C grade accuracy Basic capability. 1 — has Alarm and Critical Trips interrupt capability. SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 16 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 8.3 Configuration register (01h, 16-bit read/write) Table 8. Bit Symbol Default Access Bit Symbol Default Access 0 R 7 CTLB 0 R/W 0 R 6 AWLB 0 R/W Table 9. Bit 15:11 10:9 Configuration register (address 01h) bit allocation 15 14 13 RFU 0 R 5 CEVNT 0 R/W 0 R 4 ESTAT 0 R/W 0 R 3 EOCTL 0 R/W 0 R/W 2 CVO 0 R/W 12 11 10 HEN[1:0] 0 R/W 1 EP 0 R/W 9 8 SHMD 0 R/W 0 EMD 0 R/W Configuration register (address 01h) bit description Symbol RFU HEN Description reserved for future use; must be ‘0’. Hysteresis Enable 00 — Disable hysteresis (default) 01 — Enable hysteresis at 1.5 °C 10 — Enable hysteresis at 3 °C 11 — Enable hysteresis at 6 °C When enabled, hysteresis is applied to temperature movement around trigger points. For example, consider the behavior of the ‘Above Alarm Window’ bit (bit 14 of the Temperature register) when the hysteresis is set to 3 °C. As the temperature rises, bit 14 will be set to 1 (temperature is above the alarm window) when the Temperature register contains a value that is greater than the value in the Alarm Temperature Upper Boundary register. If the temperature decreases, bit 14 will remain set until the measured temperature is less than or equal to the value in the Alarm Temperature Upper Boundary register minus 3 °C. (Refer to Figure 5 and Table 10). Similarly, the ‘Below Alarm Window’ bit (bit 13 of the Temperature register) will be set to 0 (temperature is equal to or above the Alarm Window Lower Boundary Trip register) when the value in the Temperature register is equal to or greater than the value in the Alarm Temperature Lower Boundary register. As the temperature decreases, bit 13 will be set to 1 when the value in the Temperature register is equal to or less than the value in the Alarm Temperature Lower Boundary register minus 3 °C. Note that hysteresis is also applied to EVENT pin functionality. When either of the lock bits is set, these bits cannot be altered. 8 SHMD Shutdown Mode. 0 — Enabled Temperature Sensor (default) 1 — Disabled Temperature Sensor When shut down, the thermal sensor diode and Analog-to-Digital Converter (ADC) are disabled to save power, no events will be generated. When either of the lock bits is set, this bit cannot be set until unlocked. However, it can be cleared at any time. SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 17 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V Configuration register (address 01h) bit description …continued Symbol CTLB Description Critical Trip Lock bit. 0 — Critical Alarm Trip register is not locked and can be altered (default). 1 — Critical Alarm Trip register settings cannot be altered. This bit is initially cleared. When set, this bit will return a 1, and remains locked until cleared by internal Power-on reset. This bit can be written with a single write and do not require double writes. Table 9. Bit 7 6 AWLB Alarm Window Lock bit. 0 — Upper and Lower Alarm Trip registers are not locked and can be altered (default). 1 — Upper and Lower Alarm Trip registers setting cannot be altered. This bit is initially cleared. When set, this bit will return a 1 and remains locked until cleared by internal power-on reset. This bit can be written with a single write and does not require double writes. 5 CEVNT Clear EVENT (write only). 0 — No effect (default). 1 — Clears active EVENT in Interrupt mode. Writing to this register has no effect in Comparator mode. When read, this register always returns zero. 4 ESTAT EVENT Status (read only). 0 — EVENT output condition is not being asserted by this device (default). 1 — EVENT output pin is being asserted by this device due to Alarm Window or Critical Trip condition. The actual event causing the event can be determined from the Read Temperature register. Interrupt Events can be cleared by writing to the ‘Clear EVENT’ bit. Writing to this bit will have no effect. 3 EOCTL EVENT Output Control. 0 — EVENT output disabled (default). 1 — EVENT output enabled. When either of the lock bits is set, this bit cannot be altered until unlocked. 2 CVO Critical Event Only. 0 — EVENT output on Alarm or Critical temperature event (default) 1 — EVENT only if temperature is above the value in the critical temperature register When the Critical Trip or Alarm Window lock bit is set, this bit cannot be altered until unlocked. • Advisory note: – JEDEC specification requires only the Alarm Window lock bit to be set. – Workaround: Clear both Critical Trip and Alarm Window lock bits. – Future 1.7 V to 3.6 V SE98B will require only the Alarm Window lock bit to be set. SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 18 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V Configuration register (address 01h) bit description …continued Symbol EP Description EVENT Polarity. 0 — active LOW (default). 1 — active HIGH. When either of the alarm or critical lock bits is set, this bit cannot be altered until unlocked. Table 9. Bit 1 0 EMD EVENT Mode. 0 — comparator output mode (default) 1 — interrupt mode When either of the alarm or critical lock bits is set, this bit cannot be altered until unlocked. Table 10. Action Hysteresis enable Below Alarm Window Bit (bit 13) Temperature slope Threshold temperature Ttrip(l) − Thys Ttrip(l) Above Alarm Window Bit (bit 14) Temperature slope rising falling Temperature Ttrip(u) Ttrip(u) − Thys Above Critical Trip bit (bit 15) Temperature slope rising falling Threshold temperature Tth(crit) Tth(crit) − Thys sets clears falling rising current temperature temperature critical alarm threshold hysteresis upper alarm threshold hysteresis lower alarm threshold hysteresis time Above Critical Trip (register 05h; bit 15 = ACT bit) Above Alarm Window (register 05h; bit 14 = AAW bit) Below Alarm Window (register 05h; bit 13 = BAW bit) clear set clear clear set clear set clear 002aac799 Fig 11. Hysteresis: how it works SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 19 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 8.4 Temperature format The 16-bit value used in the following Trip Point Set and Temperature Read-Back registers is 2’s complement with the Least Significant Bit (LSB) equal to 0.0625 °C. For example: • A value of 019Ch will represent 25.75 °C • A value of 07C0h will represent 124 °C • A value of 1E64h will represent −25.75 °C. The resolution is 0.125 °C. The unused LSB (bit 0) is set to ‘0’. Bit 11 will have a resolution of 128 °C. The upper 3 bits of the temperature register indicate Trip Status based on the current temperature, and are not affected by the status of the EVENT output. Table 11 lists the examples of the content of the temperature data register for positive and negative temperature for two scenarios of status bits: status bits = 000b and status bits = 111b. Table 11. Degree Celsius and Temperature Data register Content of Temperature Data register Status bits = 000b Binary +125 °C +25 °C +1 °C +0.25 °C +0.125 °C 0 °C −0.125 °C −0.25 °C −1 °C −20 °C −25 °C −55 °C Hex 07D0h 0190h 0010h 0004h 0002h 0000h 1FFEh 1FFCh 1FF0h 1F40h 1E70h 1C90h Status bits = 111b Binary Hex E7D0h E190h E010h E004h E002h E000h FFFEh FFFCh FFF0h FF40h FE70h FC90h Temperature 000 0 01111101 000 0 000 0 00011001 000 0 000 0 00000001 000 0 000 0 00000000 010 0 000 0 00000000 001 0 000 0 00000000 000 0 000 1 11111111 111 0 000 1 11111111 110 0 000 1 11111111 000 0 000 1 11110100 000 0 000 1 11100111 000 0 000 1 11001001 000 0 111 0 01111101 000 0 111 0 00011001 000 0 111 0 00000001 000 0 111 0 00000000 010 0 111 0 00000000 001 0 111 0 00000000 000 0 111 1 11111111 111 0 111 1 11111111 110 0 111 1 11111111 000 0 111 1 11110100 000 0 111 1 11100111 000 0 111 1 11001001 000 0 SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 20 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 8.5 Temperature Trip Point registers 8.5.1 Upper Boundary Alarm Trip register (16-bit read/write) The value is the upper threshold temperature value for Alarm mode. The data format is 2’s complement with bit 2 = 0.25 °C. ‘RFU’ bits will always report zero. Interrupts will respond to the presently programmed boundary values. If boundary values are being altered in-system, it is advised to turn off interrupts until a known state can be obtained to avoid superfluous interrupt activity. Table 12. Bit Symbol Reset Access Bit Symbol Reset Access Table 13. Bit 15:13 12 11:2 1:0 0 R/W 0 R/W 0 R/W 0 R 7 Upper Boundary Alarm Trip register bit allocation 15 14 RFU 0 R 6 0 R 5 UBT[5:0] 0 R/W 0 R/W 0 R/W 0 R 13 12 SIGN 0 R/W 4 0 R/W 3 0 R/W 2 11 10 UBT[9:6] 0 R/W 1 RFU 0 R 0 R/W 0 9 8 Upper Boundary Alarm Trip register bit description Symbol RFU SIGN UBT RFU Description reserved; always 0 Sign (MSB) Upper Boundary Alarm Trip Temperature (LSB = 0.25 °C) reserved; always 0 SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 21 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 8.5.2 Lower Boundary Alarm Trip register (16-bit read/write) The value is the lower threshold temperature value for Alarm mode. The data format is 2’s complement with bit 2 = 0.25 °C. RFU bits will always report zero. Interrupts will respond to the presently programmed boundary values. If boundary values are being altered in-system, it is advised to turn off interrupts until a known state can be obtained to avoid superfluous interrupt activity. Table 14. Bit Symbol Reset Access Bit Symbol Reset Access Table 15. Bit 15:13 12 11:2 1:0 0 R/W 0 R/W 0 R/W 0 R 7 Lower Boundary Alarm Trip register bit allocation 15 14 RFU 0 R 6 0 R 5 LBT[5:0] 0 R/W 0 R/W 0 R/W 0 R 13 12 SIGN 0 R/W 4 0 R/W 3 0 R/W 2 11 10 LBT[9:6] 0 R/W 1 RFU 0 R 0 R/W 0 9 8 Lower Boundary Alarm Trip register bit description Symbol RFU SIGN LBT RFU Description reserved; always 0 Sign (MSB) Lower Boundary Alarm Trip Temperature (LSB = 0.25 °C) reserved; always 0 8.5.3 Critical Alarm Trip register (16-bit read/write) The value is the critical temperature. The data format is 2’s complement with bit 2 = 0.25 °C. RFU bits will always report zero. Table 16. Bit Symbol Reset Access Bit Symbol Reset Access Table 17. Bit 15:13 12 11:2 1:0 0 R/W 0 R/W 0 R/W 0 R 7 Lower Boundary Alarm Trip register bit allocation 15 14 RFU 0 R 6 0 R 5 CT[5:0] 0 R/W 0 R/W 0 R/W 0 R 13 12 SIGN 0 R/W 4 0 R/W 3 0 R/W 2 11 10 CT[9:6] 0 R/W 1 RFU 0 R 0 R/W 0 9 8 Critical Alarm Trip register bit description Symbol RFU SIGN CT RFU Description reserved; always 0 Sign (MSB) Critical Alarm Trip Temperature (LSB = 0.25 °C) reserved; always 0 SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 22 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 8.6 Temperature register (16-bit read-only) Table 18. Bit Symbol Reset Access Bit Symbol Reset Access Table 19. Bit 15 0 R 0 R 0 R Temperature register bit allocation 15 ACT 0 R 7 14 AAW 0 R 6 13 BAW 0 R 5 12 SIGN 0 R 4 TEMP[6:0] 0 R 0 R 0 R 0 R 0 R 3 11 10 0 R 2 9 0 R 1 8 0 R 0 RFU 0 R TEMP[10:7] Temperature register bit description Symbol ACT Description Above Critical Trip. 0 — temperature is below the Critical Alarm Trip register setting 1 — temperature is equal to or above the Critical Alarm Trip register setting 14 AAW Above Alarm Window. 0 — temperature is equal to or below the Upper Boundary Alarm Trip register 1 — temperature is above the Alarm window 13 BAW Below Alarm Window. 0 — temperature is equal to or above the Lower Boundary Alarm Trip register 1 — temperature is below the Alarm window 12 SIGN Sign bit. 0 — positive temperature value 1 — negative temperature value 11:1 0 TEMP RFU Temperature Value (2’s complement). (LSB = 0.125 °C) reserved; always 0 8.7 Manufacturer’s ID register (16-bit read-only) The manufacture’s ID matches that assigned to NXP Semiconductors PCI-SIG (1131h), and is intended for use to identify the manufacturer of the device. Table 20. Bit Symbol Reset Access Bit Symbol Reset Access 0 R 0 R 1 R 0 R 7 0 R 6 0 R 5 Manufacturer’s ID register bit allocation 15 14 13 12 1 R 4 1 R 11 0 R 3 0 R 10 0 R 2 0 R 9 0 R 1 0 R 8 1 R 0 1 R Manufacturer ID (continued) SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 23 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 8.8 Device ID register The device ID and device revision are A1h and 00h, respectively. Table 21. Bit Symbol Reset Access Bit Symbol Reset Access 0 R 0 R 0 R 1 R 7 0 R 6 1 R 5 0 R 4 0 R Device ID register bit allocation 15 14 13 12 11 0 R 3 0 R 10 0 R 2 0 R 9 0 R 1 0 R 8 1 R 0 1 R Device ID Device revision 8.9 SMBus register Table 22. Bit Symbol Reset Access Bit Symbol Reset Access Table 23. Bit 15:8 7 0 R 7 STMOUT 0 R/W 0 R 0 R 0 R 0 R 6 0 R 5 0 R 4 RFU 0 R 0 R 0 R SMBus Time-out register bit allocation 15 14 13 12 RFU 0 R 3 0 R 2 0 R 1 0 R 0 SALRT 0 R/W 11 10 9 8 SMBus Time-out register bit description Symbol RFU STMOUT Description reserved; always 0 SMBus time-out. 0 — SMBus time-out is enabled (default) 1 — disable SMBus time-out When either of the lock bits is set, this bit cannot be altered until unlocked. 6:1 0 RFU SALRT reserved; always 0 SMBus Alert. 0 — SMBus Alert is enabled (default) 1 — disable SMBus Alert When either of the lock bits is set, this bit cannot be altered until unlocked. SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 24 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 9. Application design-in information In a typical application, the SE98 behaves as a slave device and interfaces to the master (or host) via the SCL and SDA lines. The host monitors the EVENT output pin, which is asserted when the temperature reading exceeds the programmed values in the alarm registers. The A0, A1 and A2 pins are directly connected to the shared SPD’s A0, A1 and A2 pins, otherwise they must be pulled HIGH or LOW. The SDA and SCL serial interface pins are open-drain and require pull-up resistors, and are able to sink a maximum current of 3 mA with a voltage drop less than 0.4 V. Typical pull-up values for SCL and SDA are 10 kΩ, but the resistor values can be changed in order to meet the rise time requirement if the capacitance load is too large due to routing, connectors, or multiple components sharing the same bus. slave VDD 10 kΩ (3×) master SCL SE98 A0 A1 A2 SDA EVENT HOST CONTROLLER VSS 002aab282 Fig 12. Typical application 9.1 SE98 in memory module application Figure 13 shows the SE98 being placed in the memory module application. The SE98 is centered in the memory module to provide the function to monitor the temperature of the DRAM. In the event of overheat, the SE98 triggers the EVENT output and the memory controller can throttle the memory bus to slow the DRAM, or the CPU can increase the refresh rate for the DRAM. The memory controller can also read the SE98 and watch the DRAM thermal behavior. DIMM DRAM DRAM SE98 DRAM DRAM SMBus EVENT MEMORY CONTROLLER CPU 002aac804 Fig 13. System application SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 25 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 9.2 Layout consideration The SE98 does not require any additional components other than the host controller to measure temperature. A 0.1 µF bypass capacitor between the VDD and VSS pins is located as close as possible to the power and ground pins for noise protection. 9.3 Thermal considerations In general, self-heating is the result of power consumption and not a concern, especially with the SE98, which consumes very low power. In the event the SDA and EVENT pins are heavily loaded with small pull-up resistor values, self-heating affects temperature accuracy by approximately 0.5 °C. Equation 1 is the formula to calculate the effect of self-heating: T ∆ = R th ( j - a ) × [ ( V DD × I DD ) + ( V OL1 × I OL1 ) + ( V OL2 × I OL2 ) ] where: T∆ = Tj − Tamb Tj = junction temperature Tamb = ambient temperature Rth(j-a) = package thermal resistance VOL1 = SDA output low voltage VOL2 = EVENT output low voltage IOL1 = SDA output current LOW IOL2 = EVENT output current LOW. (1) 10. Limiting values Table 24. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD Vn VA0 Isink Vesd Parameter supply voltage voltage on any other pin voltage on pin A0 sink current electrostatic discharge voltage SDA, SCL, EVENT pins overvoltage input; A0 pin at SDA, SCL, EVENT pins HBM MM CDM Tj(max) Tstg [1] [1] Conditions Min −0.3 −0.3 −0.3 −1 −65 Max +4.2 +4.2 +10 +50.0 2500 250 1000 150 +165 Unit V V V mA V V V °C °C maximum junction temperature storage temperature In general, application of 10 V on the A0 pin would not damage the pin, but NXP Semiconductors does not guarantee the overvoltage for this pin. SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 26 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 11. Characteristics Table 25. Characteristics VDD = 3.0 V to 3.6 V; Tamb = −40 °C to +125 °C; unless otherwise specified. Symbol Tlim(acc) Parameter temperature limit accuracy Conditions C grade temperature accuracy; VDD = 3.3 V ± 10 % Tamb = 75 °C to 95 °C Tamb = 40 °C to 125 °C Tamb = −40 °C to +125 °C Tres IDD(AV) IDD(stb) Tconv Ef(conv) IL VDD temperature resolution average supply current standby supply current conversion period conversion rate error leakage current supply voltage percentage error in programmed data on A0, A1, A2 pins SMBus inactive −2.0 −3.0 −4.0 −30 3.0 < ±1 < ±2 < ±3 0.25 8 100 1 3.3 +2.0 +3.0 +4.0 250 15 +30 3.6 °C °C °C °C µA µA ms % µA V Min Typ Max Unit Table 26. SMBus DC characteristics VDD = 3.0 V to 3.6 V; Tamb = −40 °C to +120 °C; unless otherwise specified. These specifications are guaranteed by design. Symbol VIH VIL IOL(sink)EVENT IOL(sink)(SDA) ILOH ILIH ILIL Ci Parameter HIGH-level input voltage LOW-level input voltage LOW-level output sink current on pin EVENT HIGH-level output leakage current HIGH-level input leakage current LOW-level input leakage current input capacitance Conditions SCL, SDA; VDD = 3.0 V to 3.6 V SCL, SDA; VDD = 3.0 V to 3.6 V VOL = 0.4 V Min 2.2 1 6 −1.0 −1.0 Typ 5 Max 0.8 1.0 +1.0 +1.0 10 Unit V V mA mA µA µA µA pF LOW-level output sink current on pin SDA VOL = 0.6 V VOH = VDD VI = VDD or VSS VI = VDD or VSS SCL, SDA pins SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 27 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 300 IDD(AV) (µA) 200 002aac157 VDD = 3.0 V 3.3 V 3.6 V 16 IDD(stb) (µA) 12 002aac158 VDD = 3.0 V 3.3 V 3.6 V 8 100 4 0 −50 −25 0 25 50 75 125 100 Tamb (°C) 0 −50 −25 0 25 50 75 125 100 Tamb (°C) Fig 14. Supply current versus temperature 15.0 IOL(sink)EVENT (mA) 10.0 VDD = 3.0 V 3.3 V 3.6 V 002aac159 Fig 15. Standby supply current versus temperature 20.0 002aac160 VDD = 3.0 V 3.3 V 3.6 V 15.0 IOL(sink)(SDA) (mA) 10.0 5.0 5.0 0 −50 −25 0 25 50 75 125 100 Tamb (°C) 0 −50 −25 0 25 50 75 125 100 Tamb (°C) Fig 16. EVENT sink current at 0.4 V versus temperature 4 Temp Error (°C) 2 Fig 17. EVENT sink current at 0.6 V versus temperature 002aac161 0 −2 −4 −50 −25 0 25 50 75 125 100 Tamb (°C) Sample of 25 devices at VDD = 3.3 V Fig 18. Temperature Error versus temperature SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 28 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V Table 27. SMBus AC characteristics VDD = 3.0 V to 3.6 V; Tamb = −40 °C to +120 °C; unless otherwise specified. These specifications are guaranteed by design. The AC specifications fully meet or exceed SMBus 2.0 specifications, but allow the bus to interface with the I2C-bus from DC to 400 kHz. Symbol fSCL tLOW tHIGH tBUF tHD;STA tHD;DAT tSU;DAT tSU;STA tSU;STO tr tf tf(o) tto(SMBus) [1] [2] [3] [4] Parameter SCL clock frequency LOW period of the SCL clock HIGH period of the SCL clock bus free time between a STOP and START condition hold time (repeated) START condition data hold time data set-up time set-up time for a repeated START condition set-up time for STOP condition rise time of both SDA and SCL signals fall time of both SDA and SCL signals output fall time SMBus time-out time Conditions 10 % to 10 % 90 % to 90 % Min 0 1.3 0.6 4.7 Typ - Max 400 300 300 250 35 Unit kHz µs µs µs µs ns ns ns µs ns ns ns ms 10 % of SDA to 90 % of SCL [1] 4.7 300 250 250 0.6 - [2] [3] [4] 25 Delay from SDA START to first SCL HIGH-to-LOW transition. Delay from SCL HIGH-to-LOW transition to SDA edges. Delay from SCL LOW-to-HIGH transition to restart SDA. LOW period to reset SMBus. tLOW SCL tHD;STA tHD;DAT SDA tBUF P S tr tf tHD;STA tHIGH tSU;DAT tSU;STA tSU;STO S P 002aab235 Fig 19. AC timing diagram SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 29 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 12. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 4.4 mm SOT530-1 E D A X c y HE Z vMA 8 5 A2 A1 pin 1 index Lp L detail X (A3) A θ 1 e bp 4 wM 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.30 0.19 c 0.20 0.13 D(1) 3.1 2.9 E(2) 4.5 4.3 e 0.65 HE 6.5 6.3 L 0.94 Lp 0.7 0.5 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT530-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-24 03-02-18 Fig 20. Package outline SOT530-1 (TSSOP8) SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 30 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V HVSON8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 x 3 x 0.85 mm SOT908-1 0 1 scale 2 mm X D B A E A A1 c detail X terminal 1 index area terminal 1 index area 1 e1 e b 4 v w M M CAB C C y1 C y exposed tie bar (4×) L Eh exposed tie bar (4×) 8 5 Dh DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.3 0.2 c 0.2 D(1) 3.1 2.9 Dh 2.25 1.95 E(1) 3.1 2.9 Eh 1.65 1.35 e 0.5 e1 1.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT908-1 REFERENCES IEC JEDEC MO-229 JEITA EUROPEAN PROJECTION ISSUE DATE 05-09-26 05-10-05 Fig 21. Package outline SOT908-1 (HVSON8) SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 31 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 32 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 22) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 28 and 29 Table 28. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 29. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 22. SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 33 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 22. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 30. Acronym ADC ARA CDM CMOS DIMM DRAM HBM I2C-bus LSB MM MSB SO-DIMM POR SMBus SPD Abbreviations Description Analog-to-Digital Converter Alert Response Address Charged Device Model Complementary Metal-Oxide Semiconductor Dual In-line Memory Module Dynamic Random Access Memory Human Body Model Inter Integrated Circuit bus Least Significant Bit Machine Model Most Significant Bit Small Outline Dual In-line Memory Module Power-On Reset System Management Bus Serial Presence Detect SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 34 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 15. Revision history Table 31. SE98_4 Modifications: Revision history Release date 20090202 Data sheet status Product data sheet Change notice SMBus/I2C-bus Supersedes SE98_3 temperature sensor” to Document ID • • • • • • Changed data sheet descriptive title from “SO-DIMM “DDR memory module temp sensor, 3.3 V” Section 1 “General description”, first sentence: changed from “−20 °C to +125 °C” to “−40 °C to +125 °C” Section 2.2 “Temperature sensor features”, last bullet item changed from “−20 °C to +125 °C” to “−40 °C to +125 °C” Section 7.3 “EVENT output condition” re-written Added Section 7.10 “Hot plugging” Table 7 “Capability register (address 00h) bit description”: – description of symbol TRES: appended “(11-bit)” – description of symbol BCAP: changed from “has Alarm and Critical Trips capability” to “has Alarm and Critical Trips interrupt capability” • • Table 9 “Configuration register (address 01h) bit description”: description of bit 2, CVO, re-written Table 10 “Hysteresis enable”: – added 2 right-most columns “Critical Alarm Window Bit (bit 15)” – “Tth(low)” replaced with “Ttrip(l)” – “Tth(high)” replaced with “Ttrip(u)” – “hysteresis” replaced with “Thys” • • Section 8.4 “Temperature format”: added 4th paragraph and Table 11 Table 25 “Characteristics”: – changed descriptive line below table title from “Tamb = −20 °C to +125 °C” to “Tamb = −40 °C to +125 °C” – symbol Tlim(acc), condition “Tamb = −20 °C to +125 °C” changed to “Tamb = −40 °C to +125 °C” • • SE98_3 SE98_2 SE98_1 (9397 750 14649) Table 26 “SMBus DC characteristics”: changed descriptive line below table title from “Tamb = −20 °C to +120 °C” to “Tamb = −40 °C to +120 °C” Table 27 “SMBus AC characteristics”: changed descriptive line below table title from “Tamb = −20 °C to +120 °C” to “Tamb = −40 °C to +120 °C” Product data sheet Product data sheet Product data sheet SE98_2 SE98_1 - 20080404 20080107 20060510 SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 35 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 36 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V 18. Contents 1 2 2.1 2.2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.3.2 7.3.2.1 7.3.2.2 7.3.3 7.3.3.1 7.3.3.2 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 8.1 8.2 8.3 8.4 8.5 8.5.1 8.5.2 8.5.3 8.6 8.7 8.8 8.9 9 9.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General features . . . . . . . . . . . . . . . . . . . . . . . . 2 Temperature sensor features . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Serial bus interface . . . . . . . . . . . . . . . . . . . . . . 5 Slave address . . . . . . . . . . . . . . . . . . . . . . . . . . 5 EVENT output condition . . . . . . . . . . . . . . . . . . 6 EVENT pin output voltage levels and resistor sizing . . . . . . . . . . . . . . . . . . . . . . . . . . 6 EVENT thresholds . . . . . . . . . . . . . . . . . . . . . . 8 Alarm window . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Critical trip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Event operation modes . . . . . . . . . . . . . . . . . . . 9 Comparator mode. . . . . . . . . . . . . . . . . . . . . . . 9 Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . 9 Conversion rate. . . . . . . . . . . . . . . . . . . . . . . . 10 Power-up default condition . . . . . . . . . . . . . . . 10 Device initialization . . . . . . . . . . . . . . . . . . . . . 10 SMBus time-out . . . . . . . . . . . . . . . . . . . . . . . 11 SMBus Alert . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SMBus/I2C-bus interface . . . . . . . . . . . . . . . . 12 Hot plugging . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Register descriptions . . . . . . . . . . . . . . . . . . . 15 Register overview . . . . . . . . . . . . . . . . . . . . . . 15 Capability register (00h, 16-bit read-only). . . . 16 Configuration register (01h, 16-bit read/write) 17 Temperature format . . . . . . . . . . . . . . . . . . . . 20 Temperature Trip Point registers . . . . . . . . . . . 21 Upper Boundary Alarm Trip register (16-bit read/write) . . . . . . . . . . . . . . . . . . . . . . 21 Lower Boundary Alarm Trip register (16-bit read/write) . . . . . . . . . . . . . . . . . . . . . . 22 Critical Alarm Trip register (16-bit read/write) . 22 Temperature register (16-bit read-only) . . . . . 23 Manufacturer’s ID register (16-bit read-only) . 23 Device ID register . . . . . . . . . . . . . . . . . . . . . . 24 SMBus register . . . . . . . . . . . . . . . . . . . . . . . . 24 Application design-in information . . . . . . . . . 25 SE98 in memory module application . . . . . . . 25 9.2 9.3 10 11 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 Layout consideration . . . . . . . . . . . . . . . . . . . Thermal considerations . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 26 27 30 32 32 32 32 33 34 35 36 36 36 36 36 36 37 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 February 2009 Document identifier: SE98_4 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 38 of 39 NXP Semiconductors SE98 DDR memory module temp sensor, 3.3 V SE98_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 February 2009 39 of 39