SGTL5000XNLA3

Freescale Semiconductor Technical Data Document Number: SGTL5000 Rev. 6.0, 11/2013 Low Power Stereo Codec with Headphone Amp SGTL5000 The SGTL5000 is a Low Power Stereo Codec with Headphone Amp from Freescale, and is designed to provide a complete audio solution for products needing LINEIN, MIC_IN, LINEOUT, headphone-out, and digital I/O. Deriving it’s architecture from best in class, Freescale integrated products that are currently on the market. The SGTL5000 is able to achieve ultra low power with very high performance and functionality, all in one of the smallest footprints available. Target markets include media players, navigation devices, smart phones, tablets, medical equipment, exercise equipment, consumer audio equipment, etc. Features such as capless headphone design and an internal PLL help lower overall system cost. AUDIO CODEC Features • • • • PB-FREE 98ARE10742D 20-PIN QFN Analog Inputs • Stereo LINEIN - Support for external analog input • Stereo LINEIN - Codec bypass for low power • MIC bias provided • Programmable MIC gain • ADC - 85 dB SNR (-60 dB input) and -73 dB THD+N (VDDA = 1.8 V) Analog Outputs • HP Output - Capless design • HP Output - 62.5 mW max, 1.02 kHz sine into 16  load at 3.3 V • HP Output - 100 dB SNR (-60 dB input) and -80 dB THD+N (VDDA = 1.8 V, 16  load, DAC to headphone) • LINEOUT - 100 dB SNR (-60 dB input) and -85 dB THD+N (VDDIO = 3.3 V) Digital I/O I2S port to allow routing to Application Processor Integrated Digital Processing Freescale surround, Freescale bass, tone control/ parametric equalizer/graphic equalizer clocking/control PLL allows input of an 8.0 MHz to 27 MHz system clock - standard audio clocks are derived from PLL Power Supplies Designed to operate from 1.62 to 3.6 volts MP3/FM Input MIC IN/Speech Recognition LINEIN_R LINEIN_L MIC_IN MIC_BIAS Analog In (Stereo Line In, MIC) ADC ORDERING INFORMATION I2S_LRCLK I2S_SCLK I2S Interface SGTL5000XNLA3/R2 SGTL5000XNAA3/R2 DAC SYS_MCLK Headphone / Line Out w/ volume Audio Switch I2S_DOUT Temperature Range (TA) Device I2S_DIN Application Processor PB-FREE 98ARE10739D 32-PIN QFN -40 to 85 °C HP_R HP_L LINEOUT_R LINEOUT_L Audio Processing PLL I2C/SPI Control Note: SPI is not supported in the 3.0 mm x 3.0 mm 20-pin QFN package Figure 1. SGTL5000 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2008-2013. All rights reserved. Package 20 QFN 32 QFN Headphone Speaker Amp/Docking Station/FMTX INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM Analog Gain LINE_IN MIC_IN Analog Gain (0 to 22.5dB) MIC GAIN (0dB, 20dB, 30dB, 40dB ) Digital Gain DAC Volume Control -90dB to 0dB ADC DAC Headphone Volume Control -52dB to +12dB (CHIP_ANA_HP_CTRL) HP_OUT Audio Switch I2S_DIN Line Out Volume Control (CHIP_LINE_OUT_VOL) I2S_DOUT Mix +6dB AVC +12dB Surround Bass Enhancement +6dB LINEOUT Tone Control /GEQ/PEQ +12dB Only Gain is shown for the Digital Audio Processing blocks. For complete description please see Digital Audio Processing section. Figure 2. SGTL5000 Simplified Internal Block Diagram SGTL5000 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS 2 14 I2S_LRCLK VDDA 3 13 SYS_MCLK HP_L 4 12 VDDIO VAG 5 11 MIC_BIAS 6 7 8 9 10 LINEOUT_R LINEOUT_L LINEIN_R LINEIN_L MIC GND CTRL_CLK NC CTRL_DATA I2S_DIN I2S_DOUT 28 27 26 25 GND 1 24 I2S_SCLK HP_R 2 23 I2S_LRCLK GND 3 22 NC HP_VGND 4 VDDA 5 20 VDDIO HP_L 6 19 NC AGND 7 18 CPFILT NC 8 17 NC 21 SYS_MCLK GND 9 10 20 QFN Transparent Top View 11 12 13 14 15 16 MIC_BIAS HP_VGND 29 MIC I2S_SCLK 30 LINEIN_L 15 31 LINEIN_R 1 32 LINEOUT_L HP_R VDDD 16 LINEOUT_R I2S_DOUT 17 CTRL_ADR0_CS I2S_DIN 18 VAG CTRL_DATA 19 CTRL_MODE CTRL_CLK 20 NC VDDD PIN CONNECTIONS 32 QFN Transparent Top View Figure 3. SGTL5000 Pin Connections A functional description can be found in Functional Description, beginning on page 12. Table 1. SGTL5000 Pin Definitions 20 Pin QFN 32 Pin QFN Pin Name Pin Function Formal Name Right headphone output 1 2 HP_R Analog 2 4 HP_VGND Analog 3 5 VDDA Power Analog voltage 4 6 HP_L Analog Left headphone output - 7 AGND Analog Ground Ground - 8, 9, 17, 19, 22, 28 NC No Connect 5 10 VAG Analog DAC VAG filter 6 11 LINEOUT_R Analog Right LINEOUT 7 12 LINEOUT_L Analog Left LINEOUT 8 13 LINEIN_R Analog Right LINEIN 9 14 LINEIN_L Analog Left LINEIN Definition Headphone virtual ground Do not connect HP_VGND to system ground, even when unused. This is a virtual ground (DC voltage) that should never connect to an actual “0 Volt ground”. Use the widest, shortest trace possible for the HP_VGND. SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. SGTL5000 Pin Definitions (continued) 20 Pin QFN 32 Pin QFN Pin Name Pin Function Formal Name 10 15 MIC Analog Microphone input 11 16 MIC_BIAS Analog Mic bias — 18 CPFILT Analog Charge Pump Filter 12 20 VDDIO Power Digital I/O voltage 13 21 SYS_MCLK Digital System master clock 14 23 I2S_LRCLK Digital I2S frame clock 15 24 I2S_SCLK Digital I2S bit clock 16 25 I2S_DOUT Digital I2S data output 17 26 I2S_DIN Digital I2S data input 18 27 CTRL_DATA Digital I2C Mode: Serial Data (SDA); SPI Mode: Serial Data Input (MOSI) 19 29 CTRL_CLK Digital I2C Mode: Serial Clock (SCL); SPI Mode: Serial Clock (SCK) 20 30 VDDD Digital - 31 CTRL_ADR0_CS Digital I2C Mode: I2C Address Select 0; SPI Mode: SPI Chip Select - 32 CTRL_MODE Digital Mode select for I2C or SPI; When pulled low the Digital voltage Definition The CPFILT cap value is 0.1 F. If both VDDIO and VDDA are  3.0 V, the CPFILT pin must be connected to a 0.1 F cap to GND. If either is > 3.0 V, the CPFILT cap MUST NOT be placed. For new designs, connect VDDD to an external voltage source and to a 0.1 F capacitor to GND. control mode is I2C, when pulled high the control mode is SPI PAD 1, 3, 4, PAD GND Ground Ground The PAD must be soldered to ground. Star the ground pins of the chip, VAG ground, and all analog inputs/outputs to a single point, then to the ground plane. SGTL5000 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings Exceeding the absolute maximum ratings shown in the following table could cause permanent damage to the part and is not recommended. Normal operation is not guaranteed at the absolute maximum ratings, and extended exposure could affect long term reliability. Ratings Symbol Value Unit Maximum Digital Voltage VDDD 1.98 V Maximum Digital I/O Voltage VDDIO 3.6 V Maximum Analog Supply Voltage VDDA 3.6 V Maximum voltage on any digital input GND-0.3 to VDDIO+0.3 V Maximum voltage on any analog input GND-0.3 to VDDA+0.3 V - 55 to 125 C ELECTRICAL RATINGS THERMAL RATINGS Storage Temperature TSTG C Operating Temperature Ambient TA - 40 to 85 Symbol Value Unit Digital Voltage (If supplied externally). External VDDD connection required for new designs. VDDD 1.1 to 2.0 V Digital I/O Voltage VDDIO 1.62 to 3.6 V Analog Supply Voltage VDDA 1.62 to 3.6 V Table 3. Recommended Operating Conditions Ratings SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 4. Input/Output Electrical Characteristics Test Conditions unless otherwise noted: VDDIO = 3.3 V, VDDA = 3.3 V, TA = 25 °C, Slave mode, fS = 48 kHz, MCLK = 256 fS,  24 bit input, 1.02 kHz sine. Characteristic Symbol Min Typ Max Unit LINEIN Input Level (3.3 V VDDA) - - 2.83 VPP LINEIN Input Level (1.8 V VDDA) - - 1.60 VPP MIC Input Level (3.3 V VDDA) - - 2.83 VPP MIC Input Level (1.8 V VDDA) - - 1.60 VPP 1.46 1.52 1.68 2.53 2.61 3.11 LINEIN Input Impedance - 29 - k MIC Input Impedance - 2.9 - k LINEOUT Output Impedance LINEOUT Output level 0 dBFS at 1.031 kHz 12S input, 1.8 V LINEOUT supply (normally VDDIO), 10 k load VPP LINEOUT Output level 0 dBFS at 1.031 kHz 12S input, 3.3 V LINEOUT supply (normally VDDIO), 10 k load VPP - 320 -  LINEOUT Load 10 - - k HP (headphone) Load 16 - -  SYS_MCLK Input Voltage swing -0.3 VDDIO VDDIO+0.3 V SYS_MCLK Rise/Fall Time 0.5 - 10 ns SGTL5000 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Audio Performance 1 Test Conditions unless otherwise noted: VDDIO = 1.8 V, VDDA = 1.8 V, TA = 25 °C, Slave mode, fS = 48 kHz, MCLK = 256 fS,  24 bit input Characteristic Symbol Min Typ Max Unit LINEIN Input Level - 0.57 - VRMS LINEIN Input Impedance (at 1.02 kHz) - 29 - k SNR (-60 dB input) - 85 - dB THD+N - -70 - dB Frequency Response - 0.11 - dB Channel Separation - 79 - dB SNR (-60 dB input) - 98 - dB THD+N (10 k load) - -87 - dB THD+N (16  load) - -87 - dB Frequency Response - 0.05 - dB AUDIO PERFORMANCE 2 LINEIN -> ADC -> I S OUT LINEIN -> HEADPHONE_LINEOUT (CODEC BYPASS MODE) Channel Separation (at 1.0 kHz) 82 dB I2S IN -> DAC -> LINEOUT Output Level - 0.6 - VRMS SNR (-60 dB input) - 95 - dB THD+N - -85 - dB Frequency Response - 0.12 - dB Output Power - 17 - mW SNR (-60 dB input) - 100 - dB THD+N - -80 - dB Frequency Response - 0.12 - dB Output Power - 10 - mW SNR (-60 dB input) - 95 - dB THD+N - -86 - dB Frequency Response - 0.11 - dB SNR (-60 dB input) - 96 - dB THD+N - -84 - dB Frequency Response - 0.11 - dB PSRR (200 mVp-p at 1.0 kHz on VDDA) - 85 - dB 2 I S IN -> DAC -> HEADPHONE OUT - 16  LOAD 2 I S IN -> DAC -> HEADPHONE OUT - 32  LOAD 2 I S IN -> DAC -> HEADPHONE OUT - 10 K LOAD SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 6. Audio Performance 2 Test Conditions unless otherwise noted: VDDIO = 3.3 V, VDDA = 3.3 V, TA = 25°C, Slave mode, fS = 48 kHz, MCLK = 256 fS, 24 bit input. ADC tests were conducted with BIAS_CTRL = -37.5%, all other tests conducted with BIAS_CTRL = -50%. Characteristic Symbol Min Typ Max Unit LINEIN Input Level - 1.0 - VRMS LINEIN Input Impedance (at 1.02 kHz) - 29 - k SNR (-60 dB input) - 90 - dB THD+N - -72 - dB Frequency Response - 0.11 - dB Channel Separation - 80 - dB SNR (-60 dB input) - 102 - dB THD+N (10 k load) - -89 - dB THD+N (16  load) - -87 - dB Frequency Response - 0.05 - dB AUDIO PERFORMANCE 2 LINEIN -> ADC -> I S OUT LINEIN -> HEADPHONE_LINEOUT (CODEC BYPASS MODE) Channel Separation (at 1.0 kHz) 81 dB I2S IN -> DAC -> LINEOUT Output Level - 1.0 - VRMS SNR (-60 dB input) - 100 - dB THD+N - -85 - dB Frequency Response - 0.12 - dB Output Power - 58 - mW SNR (-60 dB input) - 98 - dB THD+N - -86 - dB Frequency Response - 0.12 - dB Output Power - 30 - mW SNR (-60 dB input) - 100 - dB THD+N - -88 - dB Frequency Response - 0.11 - dB SNR (-60 dB input) - 97 - dB THD+N - -85 - dB Frequency Response - 0.11 - dB PSRR (200 mVp-p at 1.0 kHz on VDDA) - 89 - dB 2 I S IN -> DAC -> HEADPHONE OUT - 16  LOAD 2 I S IN -> DAC -> HEADPHONE OUT - 32  LOAD 2 I S IN -> DAC -> HEADPHONE OUT - 10 K LOAD SGTL5000 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 7. Dynamic Electrical Characteristics Characteristic Symbol Min Typ Max Unit tPC 1.0(2) – - s I2C Serial Clock Frequency fI2C_CLK - - 400 kHz I2C Start condition hold time tI2CSH 150 - - ns I2C Stop condition setup time tI2CSTSU 150 - - ns I2C Data input setup time to rising edge of CTRL_CLK tI2CDSU 125 - - ns I2C Data input hold time from falling edge of CTRL_CLK (receiving data) tI2CDH 5.0 - - ns 2 tI2CDH 360 - - ns I2 C CTRL_CLK low time tI2CCLKL 300 - - ns CTRL_CLK high time tI2CCLKH 100 - - ns SPI Serial Clock Frequency fSPI_CLK - - TBD MHz SPI data input setup time tSPIDSU 10 - - ns SPI data input hold time tSPIDH 10 - - ns SPI CTRL_CLK low time tSPICLKL TBD - - ns SPI CTRL_CLK high time tSPICLKH TBD - - ns SPI clock to chip select tCCS 60 - - ns SPI chip select to clock tCSC 20 - - ns SPI chip select low tCSL 20 - - ns tCSH 20 fLRCLK 8.0 - 96 kHz fSCLK - 32*fLRCLK - kHz POWER UP TIMING Time from all supplies powered up and SYS_MCLK present to initial communication. See Figure 4. I2C BUS TIMING(3) See Figure 5. I C Data input hold time from falling edge of CTRL_CLK (driving data) I2 C SPI BUS TIMING (4) See Figure 6. SPI chip select high SPECIFICATIONS AND TIMING FOR THE 2 Frequency of I S_LRCLK Frequency of I2S_SCLK I2S PORT(5) ns See Figure 7. 64*fLRCLK I2S delay tI2S_D - - 10 ns I2S setup time tI2S_S 10 - - ns I2S hold time tI2S_H 10 - - ns Notes 1. The SGTL5000 has an internal reset that is deasserted 8 SYS_MCLK cycles after all power rails have been brought up. After this time, communication can start. 2. 1.0s represents 8 SYS_MCLK cycles at the minimum 8.0 MHz SYS_MCLK. 3. 4. This section provides timing for the SGTL5000 while in I2C mode (CTRL_MODE = 0). This section provides timing for the SGTL5000 while in SPI mode (CTRL_MODE = 1) 5. The following are the specifications and timing for I2S port. The timing applies to all formats. SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS Tpc VDDA VDDIO VDDD (if used) SYS_MCLK CTRL_DATA CTRL_CLK CTRL_ADR0_CS Initial Communication Figure 4. Power Up Timing 1/Fi2c_clk Ti2cdsu Ti2cclkh Ti2cclkl CTRL_CLK Ti2cstsu Ti2cdh Ti2csh CTRL_DATA Figure 5. I2C Timing (CTRL_MODE == 0) Tcsl Tcsh CTRL_ADR0_CS CTRL_AD0_CS 1/Fspi_clk Tspiclkh Tspiclkl Tccs Tcsc CTRL_CLK Tspidsu Tspidh CTRL_DATA Figure 6. SPI Timing SGTL5000 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS . Ti2s_s 1/Fsclk I2S_SCLK I2S_LRCLK In slave mode Ti2s_d I2S_LRCLK In master mode Ti2s_s Ti2s_h I2S_SCLK I2S_DIN Ti2s_d I2S_DOUT 1/Flrclk I2S_LRCLK Figure 7. I2S Interface Timing SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 11 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The SGTL5000 is a low power stereo codec with integrated headphone amplifier. It is designed to provide a complete audio solution for portable products needing LINEIN, mic-in, LINEOUT, headphone-out, and digital I/O. Deriving it’s architecture from best in class Freescale integrated products that are currently on the market, the SGTL5000 is able to achieve ultra low power with very high performance and functionality, all in one of the smallest footprints available. Target markets include portable media players, GPS units and smart phones. Features such as capless headphone design and USB clocking mode (12 MHz SYS_MCLK input) help lower overall system cost. In summary, the SGTL5000 accepts the following inputs: • Line input • Microphone input, with mic bias • Digital I2S input In addition, the SGTL5000 supports the following outputs: • Line output • Headphone output • Digital I2S output The following digital audio processing is included to allow for product differentiation: • Digital mixer • Freescale Surround • Freescale Bass Enhancement • Tone Control, parametric equalizer, or graphic equalizer The SGTL5000 can accept an external standard master clock at a multiple of the sampling frequency (i.e. 256*Fs, 385*Fs, 512*Fs). In addition it can take non-standard frequencies and use the internal PLL to derive the audio clocks. The device supports 8.0 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1kHz, 48 kHz, 96 kHz sampling frequencies. FUNCTIONAL INTERNAL BLOCK DESCRIPTION SYSTEM BLOCK DIAGRAM W/ SIGNAL FLOW AND GAIN MAP Figure 8 shows a block diagram that highlights the signal flow and gain map for the SGTL5000. Analog Gain LINE_IN MIC_IN Analog Gain (0 to 22.5dB) MIC GAIN (0dB, 20dB, 30dB, 40dB ) To guarantee against clipping, it is important that the gain in a signal path in addition to the signal level does not exceed 0 dB at any point. Digital Gain DAC Volume Control -90dB to 0dB ADC DAC Headphone Volume Control -52dB to +12dB (CHIP_ANA_HP_CTRL) HP_OUT Audio Switch I2S_DIN Line Out Volume Control (CHIP_LINE_OUT_VOL) I2S_DOUT Mix +6dB AVC +12dB Surround Bass Enhancement +6dB LINEOUT Tone Control /GEQ/PEQ +12dB Only Gain is shown for the Digital Audio Processing blocks. For complete description please see Digital Audio Processing section. Figure 8. System Block Diagram, Signal Flow and Gain SGTL5000 12 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION POWER The SGTL5000 has a flexible power architecture to allow the system designer to minimize power consumption and maximize performance at the lowest cost. External Power Supplies The SGTL5000 requires 2 external power supplies: VDDA and VDDIO. An optional third external power supply VDDD may be provided externally to achieve lower power. This external VDDD power supply is required for new designs. A description for the different power supplies is as follows: • VDDA: This external power supply is used for the internal analog circuitry including ADC, DAC, LINE inputs, MIC inputs, headphone outputs and reference voltages. VDDA supply ranges are shown in Maximum Ratings. A decoupling cap should be used on VDDA, as shown in the typical application diagrams in Typical Applications. • VDDIO: This external power supply controls the digital I/O levels as well as the output level of LINE outputs. VDDIO supply ranges are shown in Maximum Ratings. A decoupling cap should be used on VDDIO as shown in the typical application diagrams in Typical Applications. Note that if VDDA and VDDIO are derived from the same voltage, a single decoupling capacitor can be used to minimize cost. This capacitor should be placed closest to VDDA. • VDDD: This is a digital power supply that is used for internal digital circuitry. An external VDDD power supply is required for new designs. For lowest power, this supply can be driven at the lowest specified voltage given in Maximum Ratings. If an external supply is used for VDDD, a decoupling capacitor is recommended, as shown in the typical applications diagram. VDDD supply ranges are shown in Maximum Ratings for when externally driven. If the system drives VDDD externally, an efficient switching supply should be used or no system power savings is realized. Internal Power Supplies The SGTL5000 has two exposed internal power supplies, VAG and charge pump. • VAG is the internal voltage reference for the ADC and DAC. After startup the voltage of VAG should be set to VDDA/2 by writing CHIP_REF_CTRL->VAG_VAL. Refer to programming Chip Powerup and Supply Configurations. The VAG pin should have an external filter capacitor as shown in the typical application diagram. • Chargepump: This power supply is used for internal analog switches. If VDDA or VDDIO is greater than 2.7 V, this supply is automatically driven from the highest of VDDIO and VDDA. If both VDDIO and VDDA are less than 3.1 V, then the user should turn on the charge pump function to create the charge pump rail from VDDIO by writing CHIP_ANA_POWER-> VDDC_CHRGPMP_POWERUP register. Refer to programming Chip Powerup and Supply Configurations. • LINE_OUT_VAG is the line output voltage reference. It should be set to VDDIO/2 by writing CHIP_LINE_OUT_CTRL->LO_VAGCNTRL. Power Schemes The SGTL5000 supports a flexible architecture and allows the system designer to minimize power or maximize BOM savings. • For maximum cost savings, all supplies can be run at the same voltage. • Alternatively for minimum power, the analog and digital supplies can be run at minimum voltage while driving the digital I/O voltage at the voltage needed by the system. • To save power, independent supplies are provided for line outputs and headphone outputs. This allows for 1VRMS line outputs while using minimal headphone power. • For best power, VDDA should be run at the lowest possible voltage required for the maximum headphone output level. For highest performance, VDDA should be run at 3.3 V. For most applications a lower voltage can be used for the best performance/power combination. RESET The SGTL5000 has an internal reset that is deasserted 8 SYS_MCLKs after all power rails have been brought up. After this time communication can start. See Dynamic Electrical Characteristics. CLOCKING Clocking for the SGTL5000 is provided by a system master clock input (SYS_MCLK). SYS_MCLK should be synchronous to the sampling rate (Fs) of the I2S port. Alternatively any clock between 8.0 and 27 MHz can be provided on SYS_MCLK and the SGTL5000 can use an internal PLL to derive all internal and I2S clocks. This allows the system to use an available clock such as 12 MHz (common USB clock) for SYS_MCLK to reduce overall system costs. Synchronous SYS_MCLK input The SGTL5000 supports various combinations of SYS_MCLK frequency and sampling frequency as shown in Table 8. Using a synchronous SYS_MCLK allows for lower power as the internal PLL is not used. SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Table 8. Synchronous MCLK Rates and Sampling Frequencies CLOCK SUPPORTED RATES System Master Clock (SYS_MCLK) UNITS 256, 384, 512 Sampling Frequency (Fs) Fs 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48, 96 (6) kHz Notes 6. For a sampling frequency of 96 kHz, only 256 Fs SYS_MCLK is supported Using the PLL - Asynchronous SYS_MCLK input An integrated PLL is provided in the SGTL5000 that allows any clock from 8.0 to 27 MHz to be connected to SYS_MCLK. This can help save system costs, as a clock available elsewhere in the system can be used to derive all audio clocks using the internal PLL. In this case, the clock input to SYS_MCLK can be asynchronous with the sampling frequency needed in the system. For example, a 12 MHz Yes clock from the system processor could be used as the clock input to the SGTL5000. Three register fields need to be configured to properly use the PLL. They are CHIP_PLL_CTRL->INT_DIVISOR, CHIP_PLL_CTRL->FRAC_DIVISOR and CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2. Figure 9 shows a flowchart that shows how to determine the values to program in the register fields. SYS_MCLK>17MHz? No CHIP_CLK_TOP _CTRL->INPUT_FREQ_DIV2 = 1 CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0 PLL_INPUT_FREQ = SYS_MCLK/2 PLL_INPUT_FREQ = SYS_MCLK Yes Sampling Frequency = 44.1kHz? PLL_OUTPUT_FREQ=180 .6336 MHz No PLL_OUTPUT_FREQ=196 .608 MHz CHIP_PLL_CTRL->INT_DIVISOR = FLOOR (PLL_OUTPUT_FREQ/INPUT_FREQ CHIP_PLL_CTRL->FRAC_DIVISOR = ((PLL_OUTPUT_FREQ/INPUT_FREQ) - INT_DIVISOR) * 2048 Figure 9. PLL Programming Flowchart For example, when a 12 MHz digital signal is placed on MCLK, for a 48 kHz frame clock CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0 // SYS_MCLK < 17 MHz CHIP_PLL_CTRL->INT_DIVISOR = FLOOR (196.608 MHz/12 MHz) = 16 (decimal) CHIP_PLL_CTRL->FRAC_DIVISOR = ((196.608 MHz/ 12 MHz) - 16) * 2048 = 786 (decimal) Refer to PLL programming PLL Configuration. AUDIO SWITCH (SOURCE SELECT SWITCH) The audio switch is the central routing block that controls the signal flow from input to output. Any single input can be routed to any single or multiple outputs. Any signal can be routed to the Digital Audio Processor (DAP). The output of the DAP (an input to the audio switch) can in turn be routed to any physical output. The output of the DAP can not be routed into itself. Refer to Digital Audio Processing, for DAP information and configuration. It should be noted that the analog bypass from Line input to headphone output does not go through the audio switch. SGTL5000 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION To configure a route, the CHIP_SSS_CTRL register is used. Each output from the source select switch has its own register field that is used to select what input is routed to that output. For example, to route the I2S digital input through the DAP and then out to the DAC (headphone) outputs write SSS_CTRL->DAP_SELECT to 0x1 (selects I2S_IN) and SSS_CTRL->DAC_SELECT to 0x3 (selects DAP output). ANALOG INPUT BLOCK The analog input block contains a stereo line input and a microphone input with mic bias. Either input can be routed to the ADC. The line input can also be configured to bypass the CODEC and be routed directly to the headphone output. Line Inputs +16.5 dB of gain. The ADC gain is controlled in the CHIP_ANA_ADC_CTRL register. The ADC has an available zero cross detect (ZCD) that prevents any volume change until a zero-volt crossing of the audio signal is detected. This helps in eliminating pop or other audio anomalies. If the ADC is to be used, the chip reference bias current should not be set to -50% when in 3.0 V mode. ANALOG OUTPUTS The SGTL5000 contains a single stereo DAC that can be used to drive a headphone output and a line output. The DAC receives its input from the audio switch. The headphone output and the line output can be driven at the same time from the DAC. The headphone output can also be driven directly by the line input bypassing the ADC and DAC for a very low power mode of operation. The headphone output is powered by VDDA while the line output is powered by VDDIO. This allows the headphone output to be run at the lowest possible voltage while the line output can still meet line output level requirements. One stereo line input is provided for connection to line sources such as an FM radio or MP3 input. The source should be connected to the left and right line inputs through series coupling capacitors. The suggested value is shown in the typical application diagram in Typical Applications. As detailed in ADC, the line input can be routed to the ADC. The line input can also be routed to the headphone output by writing CHIP_ANA_CTRL->SELECT_HP. This selection bypasses the ADC and audio switch and routes the line input directly to the headphone output to enable a very low power pass through. The DAC output is routed to the headphone and the dedicated line output. The DAC output has a digital volume control from -90 dB to 0 dB in ~0.5 dB step sizes. This volume is shared among headphone output and line output. The register CHIP_DAC_VOL controls the DAC volume. Microphone Input Headphone One mono microphone input is provided for uses such as voice recording. Mic bias is provided. The mic bias is programmed with the CHIP_MIC_CTRL->BIAS_VOLT register field. Values from 1.25 V to 3.00 V are supported in 0.25 V steps. Mic bias should be set less than 200 mV from VDDA, e.g. with VDDA at 1.70 V, Mic bias should be set no greater than 1.50 V. The microphone should be connected through a series coupling capacitor. The suggested value is shown in the typical connection diagram. The microphone has programmable gain through the CHIP_MIC_CTRL->GAIN register field. Values of 0 dB, +20 dB, +30 dB and +40 dB are available. Stereo headphone outputs are provided which can be used to drive a headphone load or a line level output. The headphone output has its own independent analog volume control with a volume range of -52 dB to +12 dB in 0.5 dB step sizes. This volume control can be used in addition to the DAC volume control. For best performance the DAC volume control should be left at 0 dB until the headphone is brought to its lowest setting of -52 dB. The register CHIP_ANA_HP_CTRL is used to control the headphone volume. The headphone output has an independent mute that is controlled by the register field CHIP_ANA_CTRL>MUTE_HP. The line input is routed to the headphone output by writing CHIP_ANA_CTRL->SELECT_HP. This selection bypasses the ADC and audio switch and routes the line input directly to the headphone output to enable a very low power pass through. When the line input is routed to the headphone output, only the headphone analog volume and mute affects the headphone output. The headphone has an available zero cross detect (ZCD) which, as previously described, prevents any volume change until a zero-volt crossing of the audio signal is detected. This helps in eliminating pop or other audio anomalies. ADC The SGTL5000 contains an ADC, which takes its input from either the line input or a microphone. The register field CHIP_ANA_CTRL->SELECT_ADC controls this selection. The output of the ADC feeds the audio switch. The ADC has its own analog gain stage that provides 0 to +22.5 dB of gain in 1.5 dB steps. A bit is available that shifts this range down by 6.0 dB to effectively provide -6.0 dB to DAC SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Line Outputs The SGTL5000 contains a stereo line output. The line output has a dedicated gain stage that can be used to adjust the output level. The CHIP_LINE_OUT_VOL controls the line level output gain. The line outputs also have a dedicated mute that is controlled by the register field CHIP_ANA_CTRL>MUTE_LO. The line out volume is intended as maximum output level adjustment. It is intended to be used to set the maximum output swing. It does not have the range of a typical volume control and does not have a zero cross detect (ZCD). However the DAC digital volume could be used if volume control is desired. SGTL5000 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL DEVICE OPERATION POWER CONSUMPTION Table 9. Power Consumption: VDDA=1.8 V, VDDIO=1.8 V CURRENT CONSUMPTION (MA) MODE POWER (MW) VDDD VDDA VDDIO Playback (I2S->DAC->Headphone) - 2.54 0.9 6.19 Playback with DAP ((I2S->DAP->DAC->Headphone) - 3.59 0.9 8.08 Playback/Record (I2S->DAC->Headphone, ADC->I2S) - 3.71 1.10 8.67 Record (ADC->I2S) - 2.29 1.06 6.02 Analog playback, CODEC bypassed (LINEIN->HP) - 1.48 0.89 4.27 Standby, all analog power off - 0.019 0.002 0.038 Playback with PLL (I2S->DAC->HP) - 3.01 2.17 9.31 input, slave mode unless otherwise noted, paths tested as indicated, unused paths turned off. VDDD derived internally at 1.2 V, slave mode except for PLL case, 32  load on HP, Conditions: -100 dBFs signal Table 10. Power Consumption: VDDA=3.3 V, VDDIO=3.3 V CURRENT CONSUMPTION (MA) MODE POWER(MW) VDDD VDDA VDDIO Playback (I2S->DAC->Headphone) - 3.45 0.067 11.60 Playback with DAP ((I2S->DAP->DAC->Headphone) - 4.49 0.067 15.03 Playback/Record (I2S->DAC->Headphone, ADC->I2S) - 4.67 0.343 16.53 Record (ADC->I2S) - 2.90 0.296 10.56 Analog playback, CODEC bypassed (LINEIN->HP) - 1.91 0.039 6.43 Standby, all analog power off - 0.04 0.002 0.139 Playback with PLL (I2S->DAC->HP) - 3.92 2.76 22.05 DIGITAL INPUT & OUTPUT One I2S (Digital Audio) Port is provided which supports the following formats: I2S, Left Justified, Right Justified, and PCM mode. I2S, Left Justified, and Right Justified Modes I2S, Left Justified and Right Justified modes are stereo interface formats. The I2S_SCLK frequency, I2S_SCLK polarity, I2S_DIN/DOUT data length, and I2S_LRCLK polarity can all be changed through the CHIP_I2S_CTRL register. For I2S, Left Justified and Right Justified formats, SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION the left subframe should always be presented first regardless of the CHIP_I2S_CTRL->LRPOL setting. The I2S_LRCLK and I2S_SCLK can be programmed as master (driven to an external target) or slave (driven from an external source). When the clocks are in slave mode, they must be synchronous to SYS_MCLK. For this reason the SGTL5000 can only operate in synchronous mode (see Clocking) while in I2S slave mode. In master mode, the clocks are synchronous to SYS_MCLK or the output of the PLL when the part is running in asynchronous mode. Figure 10 shows functional examples of different common digital interface formats and their associated register settings. I2S Format (n = bit length) CHIP_I2S0_CTRL field values: (SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 0; LRALIGN = 0; LRPOL = 0) I2S_LRCLK I2S_SCLK I2S_DIN, DOUT Ln L (n-1) L01 L00 Rn R(n-1) R01 R00 Ln Left Justified Format (n = bit length) CHIP_I2S0_CTRL field values: (SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 0; LRALIGN = 1; LRPOL = 0) I2S_LRCLK I2S_SCLK I2S_DIN, DOUT Ln L(n-1) L1 L0 Rn R(n-1) R1 R0 Ln L(n-1) Right Justified Format (n = bit length) CHIP_I2S0_CTRL field values: SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 1; LRALIGN = 1; LRPOL = 0) I2S_LRCLK I2S_SCLK I2S_DIN, DOUT Ln L (n-1) L0 Rn R(n-1) R0 Figure 10. I2S Port Supported Formats SGTL5000 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION PCM Mode frame clock may be configured to clock in on the rising or falling edge of Bit Clock. PCM Format A is a format in which the data word begins one SCLK bit following the I2S_LRCLK transition, as in I2S Mode. PCM Format B is a format in which the data word begins after the I2S_LRCLK transition, as in Left Justified. In slave mode, the pulse width of the I2S_LRCLK does not matter. The pulse can range from one cycle high to all but one cycle high. In master mode, it is driven one cycle high. Figures 11 shows a functional drawing of the different formats in master mode. 2 The I S port can also be configured in PCM mode (also known as DSP mode). This mode is provided to allow connectivity to external devices such as Bluetooth modules. PCM mode differs from other interface formats presented in I2S, Left Justified, and Right Justified Modes, in that the frame clock (I2S_LRCLK) does not represent a different channel when high or low. Instead, it is a bit-wide pulse that marks the start of a frame. Data is aligned such that the left channel data is immediately followed by right channel data. Zero padding is filled in for the remaining bits. The data and PCM Format A CHIP_I2S0_CTRL = 0x01F4 (SCLKFREQ = 1; MS = 1; SCLK_INV = 1; DLEN = 3; I2S_MODE = 2; LRALIGN = 0) I2S_LRCLK I2S_SCLK Ln I2S_DIN, DOUT L (n-1) L0 Rn R( n-1) R1 R0 Ln L (n-1) L0 Rn R(n-1) R1 R0 PCM Format B CHIP_I2S0_CTRL = 0x01F6 (SCLKFREQ = 1; MS = 1; SCLK_INV = 1; DLEN = 3; I2S_MODE = 2; LRALIGN = 1) I2S_LRCLK I2S_SCLK I2S_DIN, DOUT Ln L(n-1) L0 Rn R(n-1) R0 Ln L( n-1) L0 Rn R(n-1) R0 Figure 11. PCM Formats DIGITAL AUDIO PROCESSING The SGTL5000 contains a digital audio processing block (DAP) connected to the source select switch. The digitized signal from the source select switch can be routed into the DAP block for audio processing. The DAP has the following 5 sub blocks: • Dual Input Mixer • Freescale Surround • Freescale Bass Enhancement • 7-Band Parameter EQ / 5-Band Graphic EQ / Tone Control (only one can be used at a time) • Automatic Volume Control (AVC) The block diagram in Figure 12 shows the sequence in which the signal passes through these blocks. SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Set DAP_CONTROL->DAP_EN to enable DAP block 7-Band Parametric EQ From Source Select Swtich Main Input Mix Input Automatic Automatic Volume Volume Control Control (AVC) (AVC) Dual Dual Input Input Mixer Mixer Freescale SigmaTel Bass Bass Enhance Enhance SigmaTel Freescale Surround Surround 5-Band Graphic EQ To Source Select Swtich Tone Control Each DAP sub-block can be configured in a pass-through mode Only one of PEQ/GEQ/TC can be used at a time Figure 12. Digital Audio Processing Block Diagram When the DAP block is added in the route, it must be enabled separately to get audio through. It is recommended to mute the outputs before enabling/disabling the DAP block to avoid any pops or clicks due to discontinuities in the output. Refer to Digital Audio Processor Configuration for programming examples on how to enable/disable the DAP block. Each sub-block of the DAP can be individually disabled if its processing is not required. The following sections describe the DAP sub-blocks and how to configure them. Dual Input Mixer The dual input digital mixer allows for two incoming streams from the source select switch as shown in DAP Dual Input Mixer. Main Channel Volume DAP_MAIN_CHAN->VOL Main Channel From Source Select Switch Sum Mixer Output To Freescale To SGTL Surround Surround Block Block Mix Channel From Source Select Switch Mix Channel Volume DAP_MIX_CHAN->VOL Figure 13. DAP - Dual Input Mixer The Dual Input Mixer can be enabled or configured in a pass-through mode (Main channel is passed through without any mixing). When enabled, the volume of the main and mix channels can be independently controlled before they are mixed together. The volume range allowed on each channel is 0% to 200% of the incoming signal level. The default is 100% (same as input signal level) volume on the main input and 0% (muted) on the mix input. Refer to Dual Input Mixer for programming examples on how to enable/disable the mixer and also to set the main and mix channel volume. Freescale Surround Freescale Surround is a royalty free virtual surround algorithm for stereo or mono inputs. It widens and deepens the sound stage of the music input. SGTL5000 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Input Output SigmaTel Freescale Surround Surround From Dual Mixer To Freescale BassEnhance Enhance To SGTL Bass DAP_SGTL_SURROUND -> WIDTH_CONTROL ->SELECT The Freescale Surround can be enabled or configured in pass-through mode (input is passed through without any processing). When enabling the Surround, mono or stereo input type must be selected based on the input signal. Surround width may be adjusted for the size of the sound stage. Refer to Freescale Surround and Freescale Surround On/ Off for a programming example on how to configure Surround width and how to enable/disable Surround. Freescale Bass Enhance Freescale Bass Enhance is a royalty-free algorithm that enhances natural bass response of the audio. Bass Enhance extracts bass content from right and left channels, adds bass and mixes this back up with the original signal. An optional complementary high pass filter is provided after the mixer. DAP_BASS_ENHANCE_CTRL ->LR_LEVEL Input Input (from Freescale Surround) (From SGTL Surround) DAP_BASS_ENHANCE_CTRL ->CUTOFF_HPF ->BYPASS_HPF High Pass Filter Low Pass Filter DAP_BASS_ENHANCE ->CUT_OFF Output (To PEQ/GEQ/TC) Bass Enhance DAP_BASS_ENHANCE_CTRL ->BASS_LEVEL Figure 14. DAP- Freescale Bass Enhance The Freescale Bass Enhance can be enabled or configured in pass-through mode (input is passed through without any processing). The cutoff frequency of the low-pass filter (LPF) can be selected based on the speakers frequency response. The cutoff frequency of the low-pass and high-pass filters are selectable between 80 to 225 Hz. Also, the input signal and bass enhanced signal can be individually adjusted for level before the two signals are mixed. Refer to Freescale Bass Enhance and Bass Enhance On/ Off for a programming example on how to configure Bass Enhance and how to enable/disable this feature. 7-Band Parametric EQ / 5-Band Graphic EQ / Tone Control One 7-band parametric equalizer (PEQ), one 5-band graphic equalizer (GEQ), and Tone Control (Bass and Treble control) blocks are implemented as mutually exclusive blocks. Only one block can be used at a given time. Refer to 7-Band Parametric EQ / 5-Band Graphic EQ / Tone Control for a programming example that shows how to select the desired EQ mode. 7-Band Parametric EQ The 7-band PEQ allows the designer to compensate for speaker response and to provide the ability to filter out resonant frequencies caused by the physical system design. The system designer can create custom EQ presets such as Rock, Speech, Classical, etc, which allows users the flexibility to customize their audio. The 7-band PEQ is implemented using 7 cascaded second order IIR filters. All filters are implemented using programmable bi-quad filters. Figure 15 shows the transfer function and Direct Form 1 of the five coefficient biquadratic filter. SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION H ( z)  b0  b1 z 1  b2 z 2 1  a1 z 1  a2 z 2 Direct Form 1  X(z) H(z)X(z) b0 z 1 z 1 b1 -a1 z 1 z 1 b2 -a2 Figure 15. 5-Coefficient Biquad Filter and Transfer Function If a band is enabled but is not being used (flat response), then a value of 0.5 should be put in b0 and all other coefficients should be set to 0.0. Note that the coefficients must be converted to hex values before writing to the registers. By default, all the filters are loaded with coefficients to give a flat response. In order to create EQ presets such as Rock, Speech, Classical, etc, the coefficients must be calculated, converted to 20-bit hex values and written to the registers. Note that coefficients are sample-rate dependent and separate coefficients must be generated for different sample rates. Please contact Freescale for assistance with generating the coefficients. Refer to 7-Band PEQ Preset Selection for a programming example that shows how load the filter coefficients when the end-user changes the preset. PEQ can be disabled (pass-through mode) by writing 0 to DAP_AUDIO_EQ->EN bits. 5-Band Graphic EQ The 5-band graphic equalizer is implemented using 5 parallel second order IIR filters. All filters are implemented using biquad filters whose coefficients are programmed to set the bands at a specific frequency. The GEQ bands are fixed at 115 Hz, 330 Hz, 990 Hz, 3000 Hz, and 9900 Hz. The volume on each band is independently adjustable in the range of +12 dB to -11.75 dB in 0.25 dB steps. Refer to 5-Band GEQ Volume Change for a programming example that shows how to change the GEQ volume. Tone Control Tone control comprises treble and bass controls. The tone control is implemented as one 2nd order low pass filter (bass) and one 2nd order high pass filter (treble). Refer to Tone Control - Bass and Treble Change for a programming example that shows how to change Bass and Treble values. Automatic Volume Control (AVC) An Automatic Volume Control (AVC) block is provided to reduce loud signals and amplify low level signals for easier listening. The AVC is designed to compress audio when the measured level is above the programmed threshold or to expand the audio to the programmed threshold when the measured audio is below the threshold. The threshold level is programmable with an allowed range of 0 to -96 dB. Figure 16 shows the AVC block diagram and controls. SGTL5000 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION DAP_AVC_THRESHOLD Input from Dual Input Mixer If < Threshold Decay (0.05dB/s to ~200dB/s) DAP_AVC_DECAY DAP_AVC_THRESHOLD -> MAX_GAIN Threshold Level Compare Volume Control Output To to Output Freescale Surround SGTL Surround If > Threshold Attack (0.8dB/s to ~3200dB/s) DAP_AVC_ATTACK Figure 16. DAP AVC Block Diagram When the measured audio level is below threshold, the AVC can apply a maximum gain of up to 12 dB. The maximum gain can be selected, either 0, 6, or 12 dB. When the maximum gain is set to 0 dB the AVC acts as a limiter. In this case the AVC only takes effect when the signal level is above the threshold. The rate at which the incoming signal is attenuated down to the threshold is called the attack rate. Too high of an attack causes an unnatural sound as the input signal may be distorted. Too low of an attack may cause saturation of the output as the incoming signal is not compressed quickly enough. The attack rate is programmable with allowed range of 0.05 dB/s to 200 dB/s. When the signal is below the threshold, AVC adjusts the volume up until either the threshold or the maximum gain is reached. The rate at which this volume is changed is called the decay rate. The decay rate is programmable with allowed range of 0.8 dB/s to 3200 dB/s. It is desirable to use very slow decay rate to avoid any distortion in the signal and prevent the AVC from entering a continuous attack-decay loop. Refer to Automatic Volume Control (AVC) and Automatic Volume Control (AVC) On/Off for a programming example that shows how to configure AVC and how to enable/disable AVC respectively. CONTROL The SGTL5000 supports both I2C and SPI control modes (note that SPI is not supported in the 20 QFN part). The CTRL_MODE pin chooses which mode is used. When CTRL_MODE is tied to ground, the control mode is I2C. When CTRL_MODE is tied to VDDIO, the control mode is SPI. Regardless of the mode, the control interface is used for all communication with the SGTL5000 including startup configuration, routing, volume, etc. I2C The I2C port is implemented according to the I2C specification v2.0. The I2C interface is used to read and write all registers. For the 32 QFN version of the SGTL5000, the I2C device address is 0n01010(R/W) where n is determined by CTRL_ADR0_CS and R/W is the read/write bit from the I2C protocol. For the 20 QFN version of the SGTL5000 the I2C address is always 0001010(R/W). The SGTL5000 is always the slave on all transactions, which means that an external master always drives CTRL_CLK. In general, an I2C transaction looks like the following. All locations are accessed with a 16 bit address. Each location is 16 bits wide. Example I2C write • Start condition • Device address with the R/W bit cleared to indicate write • Send two bytes for the 16 bit register address (most significant byte first) • Send two bytes for the 16 bits of data to be written to the register (most significant byte first) • Stop condition Example I2C read • Start condition • Device address with the R/W bit cleared to indicate write • Send two bytes for the 16 bit register address (most significant byte first) • Stop Condition followed by start condition (or a single restart condition) • Device address with the R/W bit set to indicate read • Read two bytes from the addressed register (most significant byte first) • Stop condition Figure 17 shows the functional I2C timing diagram. SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION I2C Address R/W ACK A15 A8 ACK A7 A0 ACK D15 D8 ACK Start Condition D7 D0 ACK Stop Condition Figure 17. Functional I2C Diagram The protocol has an auto increment feature. Instead of sending the stop condition after two bytes of data, the master may continue to send data byte pairs for writing, or it may send extra clocks for reading data byte pairs. In either case, the access address is incremented after every two bytes of data. A start or stop condition from the I2C master interrupts the current command. For reads, unless a new address is written, a new start condition with R/W=0 reads from the current address and continues to auto increment. The following diagrams describe the different access formats. The gray fields are from the I2C master, and the white fields are the SGTL5000 responses. Data [n] corresponds to the data read from the address sent, data[n+1] is the data from the next register, and so on. S = Start Condition Sr = Restart Condition A = Ack N = Nack P = Stop Condition Table 11. Write Single Location S Device Address W (0) A ADDR byte 1 A ADDR byte 0 A DATA byte 1 A DATA byte 0 A P Table 12. Write Auto increment S Device Address W (0) A A start ADDR byte 1 A start ADDR byte 0 A DATA [n] byte 1 DATA [n] byte 0 A DATA [n+1] byte 1 A DATA [n+1] byte 0 A P A DATA byte 1 A DATA byte 0 N P Table 13. Read Single Location S Device Address W (0) A ADDR byte 1 A ADDR byte 0 A Sr Device Address Sr Device Address R (1) Table 14. Read Auto increment S Device Address W (0) A start ADDR byte 1 A start ADDR byte 0 A R (1) A DATA [n] byte 1 A DATA [n] byte 0 A DATA [n+3] byte 1 A DATA [n+1] byte 1 A DATA [n+1] byte 0 DATA [n+3] byte 0 N N P Table 15. Read Continuing Auto increment S Device Address R A DATA [n+2] byte 1 A SPI Serial Peripheral Interface (SPI) is a communications protocol supported by the SGTL5000 (not supported in the 20 QFN package). The SGTL5000 is always a slave. The CTRL_ADR0_CS is used as the slave select (SS) when the master wants to select the SGTL5000 for communication. CTRL_CLK is connected to master’s SCLK and CTRL_DATA DATA [n+2] byte 0 A P is connected to master’s MOSI line. The part only supports SPI write operations and does not support read operations. Figure 18 shows the functional timing diagram of the SPI communication protocol as supported by the SGTL5000 chip. Note that on the rising edge of the SS, the chip latches to the previous 32 bits of data. It interprets the latest 16-bits as register value and the 16-bits preceding it as register address. SGTL5000 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION On rising edge of SS, latch the last 32 bits of data 16-bits Register Value 16-bits Register Address SS 23 31 7 15 0 SCK MOSI Addr 15 Addr 14 Addr 8 Addr 7 Addr 6 Addr 0 Val 15 Val 14 Val 8 Val 7 Val 6 Val 0 Figure 18. Functional Timing Diagram of SPI Protocol SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES PROGRAMMING EXAMPLES This section provides programming examples showing how to configure the chip. The registers can be written/read by using I2C communication protocol. The chip also supports SPI communication protocol (not supported in the 20 QFN package), but only register write operation is supported. PROTOTYPE FOR READING AND WRITING A REGISTER The generic register read write prototype is used throughout this section, as shown by the following. The I2C or SPI implementation is specific to the I2C/SPI hardware used in the system. used and desired configuration. The initialization sequence below assumes VDDIO = 3.3 V and VDDA = 1.8 V. //--------------- Power Supply Configuration---------------// NOTE: This next 2 Write calls is needed ONLY if VDDD is // This prototype writes a value to the entire register. All // internally driven by the chip // bit-fields of the register will be written. // Configure VDDD level to 1.2V (bits 3:0) Write REGISTER REGISTERVALUE Write CHIP_LINREG_CTRL // This prototype writes a value only to the bit-field specified. // Power up internal linear regulator (Set bit 9) // In the actual implementation, the other bit-fields should be Write CHIP_ANA_POWER // masked to prevent them from being written. Also, the // NOTE: This next Write call is needed ONLY if VDDD is // actual implementation should left-shift the BITFIELDVALUE // externally driven // by appropriate number to match the starting bit location of // Turn off startup power supplies to save power (Clear bit 12 and 13) // the BITFIELD. 0x0008 0x7260 Modify REGISTER -> BITFIELD, BITFIELDVALUE //Bitfield Location Write CHIP_ANA_POWER // Example implementation // VDDIO power supplies are less than 3.1V. // Modify DAP_EN (bit 0) bit to value 1 to enable DAP block // Enable the internal oscillator for the charge pump (Set bit 11) Modify(DAP_CONTROL_REG, 0xFFFE, 1 FRAC_DIVISOR Frac_Divisor // bits 10:0 Input/Output Routing To avoid any pops/clicks, the outputs should be muted during these chip configuration steps. Refer to Volume Control for volume and mute control. A few example routes are shown below: //----------------Set LINEOUT Volume Level------------------- // Example 1: I2S_IN -> DAP -> DAC -> LINEOUT, HP_OUT // Set the LINEOUT volume level based on voltage reference (VAG) // Route I2S_IN to DAP // values using this formula // Route DAP to DAC // Value = (int)(40*log(VAG_VAL/LO_VAGCNTRL) + 15) Modify CHIP_SSS_CTRL->DAC_SELECT 0x0003 // bits 5:4 // Assuming VAG_VAL and LO_VAGCNTRL is set to 0.9 V and 1.65 V respectively, the // left LO vol (bits 12:8) and right LO volume (bits 4:0) value should be set // to 5 // Select DAC as the input to HP_OUT Write CHIP_LINE_OUT_VOL 0x0505 System MCLK and Sample Clock // Configure SYS_FS clock to 48 kHz // Configure MCLK_FREQ to 256*Fs Modify CHIP_CLK_CTRL->SYS_FS 0x0002 // bits 3:2 Modify CHIP_CLK_CTRL->MCLK_FREQ 0x0000 // bits 1:0 // Configure the I2S clocks in master mode // NOTE: I2S LRCLK is same as the system sample clock Modify CHIP_I2S_CTRL->MS 0x0001 // bit 7 PLL Configuration These programming steps are needed only when the PLL is used. Refer to Using the PLL - Asynchronous SYS_MCLK input for details on when to use the PLL. To avoid any pops/clicks, the outputs should be muted during these chip configuration steps. Refer to Volume Control for volume and mute control. // Power up the PLL Modify CHIP_ANA_POWER->PLL_POWERUP 0x0001 // bit 10 Modify CHIP_ANA_POWER->VCOAMP_POWERUP 0x0001 // bit 8 // NOTE: This step is required only when the external SYS_MCLK // is above 17 MHz. In this case the external SYS_MCLK clock Modify CHIP_SSS_CTRL->DAP_SELECT 0x0001 // bits 7:6 Modify CHIP_ANA_CTRL->SELECT_HP 0x0000 // bit 6 // Example 2: MIC_IN -> ADC -> I2S_OUT // Set ADC input to MIC_IN Modify CHIP_ANA_CTRL->SELECT_ADC 0x0000 // bit 2 // Route ADC to I2S_OUT Modify CHIP_SSS_CTRL->I2S_SELECT 0x0000 // bits 1:0 // Example 3: LINEIN -> HP_OUT // Select LINEIN as the input to HP_OUT Modify CHIP_ANA_CTRL->SELECT_HP 0x0001 // bit 6 DIGITAL AUDIO PROCESSOR CONFIGURATION To avoid any pops/clicks, the outputs should be muted during these chip configuration steps. Refer to Volume Control for volume and mute control. // Enable DAP block // NOTE: DAP will be in a pass-through mode if none of DAP // sub-blocks are enabled. Modify DAP_CONTROL->DAP_EN 0x0001 // bit 0 Dual Input Mixer These programming steps are needed only if dual input mixer feature is used. // Enable Dual Input Mixer Modify DAP_CONTROL->MIX_EN 0x0001 // bit 4 // NOTE: This example assumes mix level of main and mix // must be divided by 2 // channels as 100% and 50% respectively Modify CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 0x0001 // bit 3 // Configure main channel volume to 100% (No change from input // level) Sys_MCLK_Input_Freq = Sys_MCLK_Input_Freq/2; Write DAP_MAIN_CHAN 0x4000 // PLL output frequency is different based on the sample clock // Configure mix channel volume to 50% (attenuate the mix // rate used. // input level by half) if (Sys_Fs_Rate == 44.1 kHz) Write DAP_MIX_CHAN 0x4000 PLL_Output_Freq = 180.6336 MHz else PLL_Output_Freq = 196.608 MHz // Set the PLL dividers Int_Divisor = floor(PLL_Output_Freq/Sys_MCLK_Input_Freq) Frac_Divisor = ((PLL_Output_Freq/Sys_MCLK_Input_Freq) Int_Divisor)*2048 Modify CHIP_PLL_CTRL->INT_DIVISOR Int_Divisor // bits 15:11 Freescale Surround The Freescale Surround on/off function is typically controlled by the end-user. End-user driven programming steps are shown in End-user Driven Chip Configuration. The default WIDTH_CONTROL of 4 should be appropriate for most applications. This optional programming step shows how to configure a different width value. SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES // Configure the surround width // (0x0 = Least width, 0x7 = Most width). This example shows // a width setting of 5 Modify DAP_SGTL_SURROUND->WIDTH_CONTROL 0x0005 // bits 6:4 Freescale Bass Enhance The Freescale Bass Enhance on/off function is typically controlled by the end-user. End-user driven programming steps are shown in End-user Driven Chip Configuration. The default LR_LEVEL value of 0x0005 results in no change in the input signal level and BASS_LEVEL value of 0x001F adds some harmonic boost to the main signal. The default settings should work for most applications. This optional programming step shows how to configure a different value. // Gain up the input signal level Modify DAP_BASS_ENHANCE_CTRL->LR_LEVEL 0x0002 // bits 7:4 // Add harmonic boost Modify DAP_BASS_ENHANCE_CTRL->BASS_LEVEL 0x003F); // bits 6:0 7-Band Parametric EQ / 5-Band Graphic EQ / Tone Control Only one audio EQ block can be used at a given time. The pseudocode in this section shows how to select each block. Some parameters of the audio EQ are typically controlled by the end-user. End-user driven programming steps are shown in End-user Driven Chip Configuration. // 7-Band PEQ Mode // Select 7-Band PEQ mode and enable 7 PEQ filters Write DAP_AUDIO_EQ 0x0001 Write DAP_PEQ 0x0007 Write DAP_AVC_DECAY 0x0028 I2S CONFIGURATION By default the I2S port on the chip is configured for 24-bits of data in I2S format with SCLK set for 64*Fs. This can be modified by setting various bit-fields in the CHIP_I2S_CTRL register. VOLUME CONTROL The outputs should be unmuted after all the configuration is complete. //---------------- Input Volume Control--------------------// Configure ADC left and right analog volume to desired default. // Example shows volume of 0dB Write CHIP_ANA_ADC_CTRL 0x0000 // Configure MIC gain if needed. Example shows gain of 20dB Modify CHIP_MIC_CTRL->GAIN 0x0001 // bits 1:0 //---------------- Volume and Mute Control--------------------// Configure HP_OUT left and right volume to minimum, unmute // HP_OUT and ramp the volume up to desired volume. Write CHIP_ANA_HP_CTRL 0x7F7F Modify CHIP_ANA_CTRL->MUTE_HP 0x0000 // bit 4 // Code assumes that left and right volumes are set to same value // So it only uses the left volume for the calculations usCurrentVolLeft = 0x7F; usNewVolLeft = usNewVol & 0xFF; usNumSteps = usNewVolLeft - usCurrentVolLeft; if (usNumSteps == 0) return; // Ramp up for (int i = 0; i < usNumSteps; i++) { ++usCurrentVolLeft; // Tone Control mode usCurrentVol = (usCurrentVolLeft MUTE_LO 0x0000 // bit 8 // Configure DAC left and right digital volume. Example shows // volume of 0dB Write CHIP_DAC_VOL 0x3C3C Modify CHIP_ADCDAC_CTRL->DAC_MUTE_LEFT 0x0000 // bit 2 Modify CHIP_ADCDAC_CTRL->DAC_MUTE_RIGHT 0x0000 // bit 3 // Unmute ADC Modify CHIP_ANA_CTRL->MUTE_ADC 0x0000 // bit 0 SGTL5000 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES END-USER DRIVEN CHIP CONFIGURATION End-users control features like volume up/down, and audio EQ parameters such as Bass and Treble. This requires programming the chip without introducing any pops/clicks or any other disturbance to the output. This section shows examples on how to program these features. VOLUME AND MUTE CONTROL Refer to Volume Control for examples on how to program volume when end-user changes the volume or mutes/ unmutes the output. Note that the DAC volume ramp is automatically handled by the chip. 7-BAND PEQ PRESET SELECTION This programming example shows how to load the filter coefficients when the end-user changes PEQ presets such as Rock, Speech, Classical etc. // Load the 5 coefficients for each band and write them to // appropriate filter address. Repeat this for all enabled // filters (this example shows 7 filters) usNumSteps = abs(usNewVol - usCurrentVol); if (usNumSteps == 0) return; for (int i = 0; i++; usNumSteps) { if (usNewVol > usCurrentVol) ++usCurrentVol; else --usCurrentVol; Write DAP_AUDIO_EQ_BASS_BAND0 usCurrentVol; } TONE CONTROL - BASS AND TREBLE CHANGE This programming example shows how to program the Tone Control Bass and Treble when end-user changes it on the fly. Tone Control Bass and Treble volume should be ramped in 0.5 dB steps in order to avoid any pops. The example assumes that Treble is changed to a new value. Bass can be programmed similarly. for (i = 0; i < 7; i++) // Read current Treble value { usCurrentVal = Read DAP_AUDIO_EQ_TREBLE_BAND4 // Note that each 20-bit coefficient is broken into 16-bit MSB // Convert the new Treble value to hex value // (unsigned short usXXMSB) and 4-bit LSB (unsigned short usNewVol = 4*dNewValDb + 47; // usXXLSB) // Calculate the number of steps Write DAP_COEF_WR_B0_LSB usB0MSB[i] usNumSteps = abs(usNewVal - usCurrentVal); Write DAP_COEF_WR_B0_MSB usB0LSB[i] if (usNumSteps == 0) return; Write DAP_COEF_WR_B1_LSB usB1MSB[i] for (int i = 0; i++; usNumSteps) Write DAP_COEF_WR_B1_MSB usB1LSB[i] { Write DAP_COEF_WR_B2_LSB usB2MSB[i] if (usNewVal > usCurrentVal) Write DAP_COEF_WR_B2_MSB usB2LSB[i] ++usCurrentVal; Write DAP_COEF_WR_A1_LSB usA1MSB[i] else Write DAP_COEF_WR_A1_MSB usA1LSB[i] --usCurrentVal; Write DAP_COEF_WR_A2_LSB usA2MSB[i] Write DAP_AUDIO_EQ_TREBLE_BAND4 usCurrentVal; Write DAP_COEF_WR_A2_MSB usA2LSB[i] } // Set the index of the filter (bits 7:0) and load the // coefficients FREESCALE SURROUND ON/OFF Modify DAP_FILTER_COEF_ACCESS->INDEX (0x0101 + i) This programming example shows how to program the Surround when end-user turns it on/off on their device. The Surround width should be ramped up to highest value before enabling/disabling the Surround to avoid any pops. // bit 8 } 5-BAND GEQ VOLUME CHANGE This programming example shows how to program the GEQ volume when end-user changes the volume on any of the 5 bands. GEQ volume should be ramped in 0.5 dB steps in order to avoid any pops. The example assumes that volume is ramped on Band 0. Other bands can be programmed similarly. // Read current volume set on Band 0 usCurrentVol = Read DAP_AUDIO_EQ_BASS_BAND0 // Read current Surround width value // WIDTH_CONTROL bits 6:4 usOriginalVal = (Read DAP_SGTL_SURROUND >> 4) && 0x0003; usNextVal = usOriginalVal; // Ramp up the width to maximum value of 7 for (int i = 0; i++; (7 - usOriginalVal) { ++usNextVal; // Convert the new volume to hex value Modify DAP_SGTL_SURROUND->WIDTH_CONTROL usNextVal; usNewVol = 4*dNewVolDb + 47; } // Calculate the number of steps // Enable (To disable, write 0x0000) Surround SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES // SELECT bits 1:0 { Modify DAP_SGTL_SURROUND->SELECT 0x0003; ++usNextVal; // Ramp down the width to original value for (int i = 0; i++; (7 - usOriginalVal) Modify DAP_BASS_ENHANCE_CTRL->BASS_LEVEL usNextVal; { } --usNextVal; // Enable (To disable, write 0x0000) Bass Enhance Modify DAP_SGTL_SURROUND->WIDTH_CONTROL usNextVal; // EN bit 0 } // Ramp Bass level back to original value Modify DAP_BASS_ENHANCE->EN 0x0001; for (int i = 0; i++; usNumSteps) BASS ENHANCE ON/OFF { This programming example shows how to program the Bass Enhance on/off when end-user turns it on/off on their device. The Bass level should be ramped down to the lowest Bass before Bass Enhance feature is turned on/off. --usNextVal; Modify DAP_BASS_ENHANCE_CTRL->BASS_LEVEL usNextVal; } // Read current Bass level value AUTOMATIC VOLUME CONTROL (AVC) ON/OFF // BASS_LEVEL bits 6:0 This programming example shows how to program the AVC on/off when end-user turns it on/off on their device. usOriginalVal = Read DAP_BASS_ENHANCE_CTRL && 0x007F; // Enable AVC (To disable, write 0x0000) usNextVal = usOriginalVal; Modify DAP_AVC_CTRL->EN 0x0001 // Ramp Bass level to lowest bass (lowest bass = 0x007F) // bit 0 usNumSteps = abs(0x007F - usOriginalVal); Register description for (int i = 0; i++; usNumSteps) CHIP_ID 0x0000 Table 16. CHIP_ID 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 PARTID 3 2 1 0 REVID BITS FIELD RW RESET 15:8 PARTID RO 0xA0 DEFINITION SGTL5000 Part ID 0xA0 - 8 bit identifier for SGTL5000 7:0 REVID RO 0x00 SGTL5000 Revision ID 0xHH - revision number for SGTL5000. Table 17. CHIP_DIG_POWER 0x0002 11 10 9 8 6 ADC_POWERUP RSVD 7 5 4 BITS FIELD RW RESET 15:7 RSVD RO 0x0 Reserved 6 ADC_POWERUP RW 0x0 Enable/disable the ADC block, both digital and analog 3 2 RSVD 1 0 I2S_IN_POWERUP 12 I2S_OUT_POWERUP 13 DAP_POWERUP 14 DAC_POWERUP 15 DEFINITION 0x0 = Disable 0x1 = Enable SGTL5000 30 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW RESET 5 DAC_POWERUP RW 0x0 DEFINITION Enable/disable the DAC block, both analog and digital 0x0 = Disable 0x1 = Enable 4 DAP_POWERUP RW 0x0 Enable/disable the DAP block 0x0 = Disable 0x1 = Enable 3:2 RSVD RW 0x0 Reserved 1 I2S_OUT_POWERUP RW 0x0 Enable/disable the I2S data output 0x0 = Disable 0x1 = Enable 0 I2S_IN_POWERUP RW 0x0 Enable/disable the I2S data input 0x0 = Disable 0x1 = Enable Table 18. CHIP_CLK_CTRL 0x0004 15 14 13 12 11 10 9 8 7 6 RSVD 5 4 RATE_MODE 3 2 SYS_FS 1 0 MCLK_FREQ BITS FIELD RW RESET DEFINITION 15:6 RSVD RO 0x0 Reserved 5:4 RATE_MODE RW 0x0 Sets the sample rate mode. MCLK_FREQ is still specified relative to the rate in SYS_FS 0x0 = SYS_FS specifies the rate 0x1 = Rate is 1/2 of the SYS_FS rate 0x2 = Rate is 1/4 of the SYS_FS rate 0x3 = Rate is 1/6 of the SYS_FS rate 3:2 SYS_FS RW 0x2 Sets the internal system sample rate 0x0 = 32 kHz 0x1 = 44.1 kHz 0x2 = 48 kHz 0x3 = 96 kHz 1:0 MCLK_FREQ RW 0x0 Identifies incoming SYS_MCLK frequency and if the PLL should be used 0x0 = 256*Fs 0x1 = 384*Fs 0x2 = 512*Fs 0x3 = Use PLL The 0x3 (Use PLL) setting must be used if the SYS_MCLK is not a standard multiple of Fs (256, 384, or 512). This setting can also be used if SYS_MCLK is a standard multiple of Fs. Before this field is set to 0x3 (Use PLL), the PLL must be powered up by setting CHIP_ANA_POWER->PLL_POWERUP and CHIP_ANA_POWER>VCOAMP_POWERUP. Also, the PLL dividers must be calculated based on the external MCLK rate and CHIP_PLL_CTRL register must be set (see CHIP_PLL_CTRL register description details on how to calculate the divisors). SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 31 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 19. CHIP_I2S_CTRL 0x0006 12 11 10 9 8 RSVD 7 MS 6 5 4 DLEN 3 2 I2S_MODE 1 LRALIGN 13 SCLK_INV 14 SCLKFREQ 15 0 LRPOL BITS FIELD RW RESET DEFINITION 15:9 RSVD RO 0x0 Reserved 8 SCLKFREQ RW 0x0 Sets frequency of I2S_SCLK when in master mode (MS=1). When in slave mode (MS=0), this field must be set appropriately to match SCLK input rate. 0x0 = 64Fs 0x1 = 32Fs - Not supported for RJ mode (I2S_MODE = 1) 7 MS RW 0x0 Configures master or slave of I2S_LRCLK and I2S_SCLK. 0x0 = Slave: I2S_LRCLK and I2S_SCLK are inputs 0x1 = Master: I2S_LRCLK and I2S_SCLK are outputs NOTE: If the PLL is used (CHIP_CLK_CTRL->MCLK_FREQ==0x3), the SGTL5000 must be a master of the I2S port (MS==1) 6 SCLK_INV RW 0x0 Sets the edge that data (input and output) is clocked in on for I2S_SCLK 0x0 = data is valid on rising edge of I2S_SCLK 0x1 = data is valid on falling edge of I2S_SCLK 5:4 DLEN RW 0x1 I2S data length 0x0 = 32 bits (only valid when SCLKFREQ=0), not valid for Right Justified Mode 0x1 = 24 bits (only valid when SCLKFREQ=0) 0x2 = 20 bits 0x3 = 16 bits 3:2 I2S_MODE RW 0x0 Sets the mode for the I2S port 0x0 = I2S mode or Left Justified (Use LRALIGN to select) 0x1 = Right Justified Mode 0x2 = PCM Format A/B 0x3 = RESERVED 1 LRALIGN RW 0x0 I2S_LRCLK Alignment to data word. Not used for Right Justified mode 0x0 = Data word starts 1 I2S_SCLK delay after I2S_LRCLK transition (I2S format, PCM format A) 0x1 = Data word starts after I2S_LRCLK transition (left justified format, PCM format B) 0 LRPOL RW 0x0 I2S_LRCLK Polarity when data is presented. 0x0 = I2S_LRCLK = 0 - Left, 1 - Right 1x0 = I2S_LRCLK = 0 - Right, 1 - Left The left subframe should be presented first regardless of the setting of LRPOL. SGTL5000 32 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 20. CHIP_SSS_CTRL 0x000A 10 RSVD 9 8 DAP_MIX_SELECT 11 I2S_LRSWAP 12 DAC_LRSWAP 13 DAP_LRSWAP RSVD 14 DAP_MIX_LRSWAP 15 7 6 DAP_SELECT BITS FIELD RW RESET 15 RSVD RW 0x0 Reserved 14 DAP_MIX_LRSWAP RW 0x0 DAP Mixer Input Swap 5 4 3 DAC_SELECT 2 RSVD 1 0 I2S_SELECT DEFINITION 0x0 = Normal Operation 0x1 = Left and Right channels for the DAP MIXER Input are swapped. 13 DAP_LRSWAP RW 0x0 DAP Input Swap 0x0 = Normal Operation 0x1 = Left and Right channels for the DAP Input are swapped 12 DAC_LRSWAP RW 0x0 DAC Input Swap 0x0 = Normal Operation 0x1 = Left and Right channels for the DAC are swapped 11 RSVD RW 0x0 Reserved 10 I2S_LRSWAP RW 0x0 I2S_DOUT Swap 0x0 = Normal Operation 0x1 = Left and Right channels for the I2S_DOUT are swapped 9:8 DAP_MIX_SELECT RW 0x0 Select data source for DAP mixer 0x0 = ADC 0x1 = I2S_IN 0x2 = Reserved 0x3 = Reserved 7:6 DAP_SELECT RW 0x0 Select data source for DAP 0x0 = ADC 0x1 = I2S_IN 0x2 = Reserved 0x3 = Reserved 5:4 DAC_SELECT RW 0x1 Select data source for DAC 0x0 = ADC 0x1 = I2S_IN 0x2 = Reserved 0x3 = DAP 3:2 RSVD RW 0x0 Reserved 1:0 I2S_SELECT WO 0x0 Select data source for I2S_DOUT 0x0 = ADC 0x1 = I2S_IN 0x2 = Reserved 0x3 = DAP SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 33 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 21. CHIP_ADCDAC_CTRL 0x000E 7 6 RSVD 5 4 RSVD BITS FIELD RW RESET 15:14 RSVD RO 0x0 Reserved 13 VOL_BUSY_DAC_RIG HT RO 0x0 Volume Busy DAC Right 3 2 1 0 ADC_HPF_BYPASS 8 ADC_HPF_FREEZE 9 DAC_MUTE_LEFT 10 DAC_MUTE_RIGHT 11 VOL_EXPO_RAMP 12 VOL_RAMP_EN RSVD 13 VOL_BUSY_DAC_LEFT 14 VOL_BUSY_DAC_RIGHT 15 DEFINITION 0x0 = Ready 0x1 = Busy - This indicates the channel has not reached its programmed volume/mute level 12 VOL_BUSY_DAC_LEF T RO 0x0 Volume Busy DAC Left 0x0 = Ready 0x1 = Busy - This indicates the channel has not reached its programmed volume/mute level 11:10 RSVD RO 0x0 Reserved 9 VOL_RAMP_EN RW 0x1 Volume Ramp Enable 0x0 = Disables volume ramp. New volume settings take immediate effect without a ramp 0x1 = Enables volume ramp This field affects DAC_VOL. The volume ramp effects both volume settings and mute. When set to 1 a soft mute is enabled. 8 VOL_EXPO_RAMP RW 0x0 Exponential Volume Ramp Enable 0x0 = Linear ramp over top 4 volume octaves 0x1 = Exponential ramp over full volume range This bit only takes effect if VOL_RAMP_EN is 1. 7:4 RSVD RW 0x0 Reserved 3 DAC_MUTE_RIGHT RW 0x1 DAC Right Mute 0x0 = Unmute 0x1 = Muted If VOL_RAMP_EN = 1, this is a soft mute. 2 DAC_MUTE_LEFT RW 0x1 DAC Left Mute 0x0 = Unmute 0x1 = Muted If VOL_RAMP_EN = 1, this is a soft mute. 1 ADC_HPF_FREEZE RW 0x0 ADC High Pass Filter Freeze 0x0 = Normal operation 0x1 = Freeze the ADC high-pass filter offset register. The offset continues to be subtracted from the ADC data stream. 0 ADC_HPF_BYPASS RW 0x0 ADC High Pass Filter Bypass 0x0 = Normal operation 0x1 = Bypassed and offset not updated SGTL5000 34 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 22. CHIP_DAC_VOL 0x0010 15 14 13 12 11 10 9 8 7 6 5 DAC_VOL_RIGHT 4 3 2 1 0 DAC_VOL_LEFT BITS FIELD RW RESET 15:8 DAC_VOL_RIGHT RW 0x3C DEFINITION DAC Right Channel Volume Set the Right channel DAC volume with 0.5017 dB steps from 0 to -90 dB 0x3B and less = Reserved 0x3C = 0 dB 0x3D = -0.5 dB 0xF0 = -90 dB 0xFC and greater = Muted If VOL_RAMP_EN = 1, there is an automatic ramp to the new volume setting. 7:0 DAC_VOL_LEFT RW 0x3C DAC Left Channel Volume Set the Left channel DAC volume with 0.5017 dB steps from 0 to -90 dB 0x3B and less = Reserved 0x3C = 0 dB 0x3D = -0.5 dB 0xF0 = -90 dB 0xFC and greater = Muted If VOL_RAMP_EN = 1, there is an automatic ramp to the new volume setting. Table 23. CHIP_PAD_STRENGTH 0x0014 15 14 13 12 11 10 RSVD 9 8 I2S_LRCLK 7 6 5 I2S_SCLK 4 I2S_DOUT BITS FIELD RW RESET 15:14 RSVD RW 0x0 Reserved 9:8 I2S_LRCLK RW 0x1 I2S LRCLK Pad Drive Strength 3 2 CTRL_DATA 1 0 CTRL_CLK DEFINITION Sets drive strength for output pads per the table below. VDDIO 1.8 V 2.5 V 3.3 V 0x0 = Disable 7:6 I2S_SCLK RW 0x1 0x1 = 1.66 mA 2.87 mA 4.02 mA 0x2 = 3.33 mA 5.74 mA 8.03 mA 0x3 = 4.99 mA 8.61 mA 12.05 mA I2S SCLK Pad Drive Strength Sets drive strength for output pads per the table below. VDDIO 1.8 V 2.5 V 3.3 V 0x0 = Disable 0x1 = 1.66 mA 2.87 mA 4.02 mA 0x2 = 3.33 mA 5.74 mA 8.03 mA 0x3 = 4.99 mA 8.61 mA 12.05 mA SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 35 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD 5:4 RW I2S_DOUT RW RESET 0x1 DEFINITION 2 I S DOUT Pad Drive Strength Sets drive strength for output pads per the table below. VDDIO 1.8 V 2.5 V 3.3 V 0x0 = Disable 3:2 CTRL_DATA RW 0x3 0x1 = 1.66 mA 2.87 mA 4.02 mA 0x2 = 3.33 mA 5.74 mA 8.03 mA 0x3 = 4.99 mA 8.61 mA 12.05 mA I2C DATA Pad Drive Strength Sets drive strength for output pads per the table below. VDDIO 1.8 V 2.5 V 3.3 V 0x0 = Disable 1:0 CTRL_CLK RW 0x3 0x1 = 1.66 mA 2.87 mA 4.02 mA 0x2 = 3.33 mA 5.74 mA 8.03 mA 0x3 = 4.99 mA 8.61 mA 12.05 mA I2 C CLK Pad Drive Strength Sets drive strength for output pads per the table below. VDDIO 1.8 V 2.5 V 3.3 V 0x0 = Disable 0x1 = 1.66 mA 2.87 mA 4.02 mA 0x2 = 3.33 mA 5.74 mA 8.03 mA 0x3 = 4.99 mA 8.61 mA 12.05 mA Table 24. CHIP_ANA_ADC_CTRL 0x0020 14 13 12 11 10 9 8 ADC_VOL_M6DB 15 RSVD 7 6 5 4 ADC_VOL_RIGHT BITS FIELD RW RESET 15:9 RSVD RO 0x0 Reserved 8 ADC_VOL_M6DB RW 0x0 ADC Volume Range Reduction 3 2 1 0 ADC_VOL_LEFT DEFINITION This bit shifts both right and left analog ADC volume range down by 6.0 dB. 0x0 = No change in ADC range 0x1 = ADC range reduced by 6.0 dB SGTL5000 36 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW RESET 7:4 ADC_VOL_RIGHT RW 0x0 DEFINITION ADC Right Channel Volume Right channel analog ADC volume control in 1.5.0 dB steps. 0x0 = 0 dB 0x1 = +1.5 dB ... 0xF = +22.5 dB This range is -6.0 dB to +16.5 dB if ADC_VOL_M6DB is set to 1. 3:0 ADC_VOL_LEFT RW 0x0 ADC Left Channel Volume Left channel analog ADC volume control in 1.5 dB steps. 0x0 = 0 dB 0x1 = +1.5 dB ... 0xF = +22.5 dB This range is -6.0 dB to +16.5 dB if ADC_VOL_M6DB is set to 1. Table 25. CHIP_ANA_HP_CTRL 0x0022 15 14 13 12 RSVD BITS 11 10 9 8 HP_VOL_RIGHT FIELD RW RESET 7 6 RSVD 5 4 3 2 1 0 HP_VOL_LEFT DEFINITION 15 RSVD RO 0x0 Reserved 14:8 HP_VOL_RIGHT RW 0x18 Headphone Right Channel Volume Right channel headphone volume control with 0.5 dB steps. 0x00 = +12 dB 0x01 = +11.5 dB 0x18 = 0 dB ... 0x7F = -51.5 dB 7 RSVD RO 0x0 Reserved 6:0 HP_VOL_LEFT RW 0x18 Headphone Left Channel Volume Left channel headphone volume control with 0.5 dB steps. 0x00 = +12 dB 0x01 = +11.5 dB 0x18 = 0 dB ... 0x7F = -51.5 dB Table 26 is an analog control register that includes mutes, input selects, and zero-cross-detectors for the ADC, headphone, and LINEOUT. SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 37 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 26. 7.0.0.11. CHIP_ANA_CTRL 0x0024 8 MUTE_LO RSVD 9 BITS FIELD RW RESET 15:9 RSVD RO 0x0 Reserved 8 MUTE_LO RW 0x1 LINEOUT Mute 7 RSVD 6 5 4 3 RSVD 2 1 0 MUTE_ADC 10 EN_ZCD_ADC 11 SELECT_ADC 12 MUTE_HP 13 EN_ZCD_HP 14 SELECT_HP 15 DEFINITION 0x0 = Unmute 0x1 = Mute 7 RSVD RO 0x0 Reserved 6 SELECT_HP RW 0x0 Select the headphone input. 0x0 = DAC 0x1 = LINEIN 5 EN_ZCD_HP RW 0x0 Enable the headphone zero cross detector (ZCD) 0x0 = HP ZCD disabled 0x1 = HP ZCD enabled 4 MUTE_HP RW 0x1 Mute the headphone outputs 0x0 = Unmute 0x1 = Mute 3 RSVD RO 0x0 Reserved 2 SELECT_ADC RW 0x0 Select the ADC input. 0x0 = Microphone 0x1 = LINEIN 1 EN_ZCD_ADC RW 0x0 Enable the ADC analog zero cross detector (ZCD) 0x0 = ADC ZCD disabled 0x1 = ADC ZCD enabled 0 MUTE_ADC RW 0x1 Mute the ADC analog volume 0x0 = Unmute 0x1 = Mute The Table 27, CHIP_LINREG_CTRL 0x0026 register controls the VDDD linear regulator and the charge pump. SGTL5000 38 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 27. CHIP_LINREG_CTRL 0x0026 14 13 12 11 10 9 8 7 VDDC_MAN_ASSN RSVD 6 5 VDDC_ASSN_OVRD 15 4 3 RSVD 2 1 0 D_PROGRAMMING BITS FIELD RW RESET DEFINITION 15:7 RSVD RO 0x0 Reserved 6 VDDC_MAN_ASSN RW 0x0 Determines chargepump source when VDDC_ASSN_OVRD is set. 0x0 = VDDA 0x1 = VDDIO 5 VDDC_ASSN_OVRD RW 0x0 Charge pump Source Assignment Override 0x0 = Charge pump source is automatically assigned based on higher of VDDA and VDDIO 0x1 = the source of charge pump is manually assigned by VDDC_MAN_ASSN If VDDIO and VDDA are both the same and greater than 3.1 V, VDDC_ASSN_OVRD and VDDC_MAN_ASSN should be used to manually assign VDDIO as the source for charge pump. 4 RSVD RW 0x0 Reserved 3:0 D_PROGRAMMING RW 0x0 Sets the VDDD linear regulator output voltage in 50 mV steps. Must clear the LINREG_SIMPLE_POWERUP and STARTUP_POWERUP bits in the 0x0030 register after power-up, for this setting to produce the proper VDDD voltage. 0x0 = 1.60 0xF = 0.85 The Table 28, CHIP_REF_CTRL 0x0028 register controls the bandgap reference bias voltage and currents. Table 28. CHIP_REF_CTRL 0x0028 14 13 12 11 10 9 8 RSVD 7 6 5 4 VAG_VAL BITS FIELD RW RESET 15:9 RSVD RO 0x0 Reserved 8:4 VAG_VAL RW 0x0 Analog Ground Voltage Control 3 2 BIAS_CTRL 1 0 SMALL_POP 15 DEFINITION These bits control the analog ground voltage in 25 mV steps. This should usually be set to VDDA/2 or lower for best performance (maximum output swing at minimum THD). This VAG reference is also used for the DAC and ADC voltage reference. So changing this voltage scales the output swing of the DAC and the output signal of the ADC. 0x00 = 0.800 V 0x1F = 1.575 V SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 39 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW RESET 3:1 BIAS_CTRL RW 0x0 DEFINITION Bias control These bits adjust the bias currents for all of the analog blocks. By lowering the bias current a lower quiescent power is achieved. It should be noted that this mode can affect performance by 3-4 dB. 0x0 = Nominal 0x1-0x3=+12.5% 0x4=-12.5% 0x5=-25% 0x6=-37.5% 0x7=-50% 0 SMALL_POP RW 0x0 VAG Ramp Control Setting this bit slows down the VAG ramp from ~200 to ~400 ms to reduce the startup pop, but increases the turn on/off time. 0x0 = Normal VAG ramp 0x1 = Slow down VAG ramp The Table 29, CHIP_MIC_CTRL 0x002A register controls the microphone gain and the internal microphone biasing circuitry. Table 29. CHIP_MIC_CTRL 0x002A 15 14 13 12 11 10 RSVD 9 8 7 6 BIAS_RESISTOR RSVD 5 4 BIAS_VOLT BITS FIELD RW RESET 15:10 RSVD RO 0x0 Reserved 9:8 BIAS_RESISTOR RW 0x0 MIC Bias Output Impedance Adjustment 3 2 RSVD 1 0 GAIN DEFINITION Controls an adjustable output impedance for the microphone bias. If this is set to zero the micbias block is powered off and the output is highZ. 0x0 = Powered off 0x1 = 2.0 k 0x2 = 4.0 k 0x3 = 8.0 k 7 RSVD RO 0x0 Reserved 6:4 BIAS_VOLT RW 0x0 MIC Bias Voltage Adjustment Controls an adjustable bias voltage for the microphone bias amp in 250 mV steps. This bias voltage setting should be no more than VDDA-200 mV for adequate power supply rejection. 0x0 = 1.25 V ... 0x7 = 3.00 V 3:2 RSVD RO 0x0 Reserved 1:0 GAIN RW 0x0 MIC Amplifier Gain Sets the microphone amplifier gain. At 0 dB setting the THD can be slightly higher than other paths- typically around ~65 dB. At other gain settings the THD are better. 0x0 = 0 dB 0x1 = +20 dB 0x2 = +30 dB 0x3 = +40 dB SGTL5000 40 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 30. CHIP_LINE_OUT_CTRL 0x002C 15 14 13 12 11 RSVD 10 9 8 7 OUT_CURRENT 6 5 4 RSVD 3 2 1 0 LO_VAGCNTRL BITS FIELD RW RESET DEFINITION 15:12 RSVD RO 0x0 Reserved 11:8 OUT_CURRENT RW 0x0 Controls the output bias current for the LINEOUT amplifiers. The nominal recommended setting for a 10 k load with 1.0 nF load cap is 0x3. There are only 5 valid settings. 0x0=0.18 mA, 0x1=0.27 mA, 0x3=0.36 mA, 0x7=0.45 mA, 0xF=0.54 mA 7:6 RSVD RO 0x0 Reserved 5:0 LO_VAGCNTRL RW 0x0 LINEOUT Amplifier Analog Ground Voltage Controls the analog ground voltage for the LINEOUT amplifiers in 25 mV steps. This should usually be set to VDDIO/2. 0x00 = 0.800 V ... 0x1F = 1.575 V ... 0x23 = 1.675 V 0x24-0x3F are invalid Table 31. CHIP_LINE_OUT_VOL 0x002E 15 14 13 12 RSVD 11 10 9 8 7 LO_VOL_RIGHT 6 5 4 RSVD BITS FIELD RW RESET 15:13 RSVD RO 0x0 Reserved 12:8 LO_VOL_RIGHT RW 0x4 LINEOUT Right Channel Volume 3 2 1 0 LO_VOL_LEFT DEFINITION Controls the right channel LINEOUT volume in 0.5 dB steps. Higher codes have more attenuation. See programming information for Left channel. 7:5 RSVD RO 0x0 Reserved 4:0 LO_VOL_LEFT RW 0x4 LINEOUT Left Channel Output Level The LO_VOL_LEFT is used to normalize the output level of the left line output to full scale based on the values used to set LINE_OUT_CTRL -> LO_VAGCNTRL and CHIP_REF_CTRL -> VAG_VAL. In general this field should be set to: 40*log((VAG_VAL)/(LO_VAGCNTRL)) + 15 Table 32 shows suggested values based on typical VDDIO and VDDA voltages. After setting to the nominal voltage, this field can be used to adjust the output level in +/-0.5 dB increments by using values higher or lower than the nominal setting. Table 32. LINEOUT Output Level Values VDDA VAG_VAL VDDIO LO_VAGCNTRL LO_VOL_* 1.8 V 0.9 3.3 V 1.55 0x06 1.8 V 0.9 1.8 V 0.9 0x0F 3.3 V 1.55 1.8 V 0.9 0x19 3.3 V 1.55 3.3 V 1.55 0x0F SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 41 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES The Table 33, CHIP_ANA_POWER 0x0030 register contains all of the power down controls for the analog blocks. The only other power-down controls are BIAS_RESISTOR in the MIC_CTRL register and the EN_ZCD control bits in ANA_CTRL. Table 33. CHIP_ANA_POWER 0x0030 0 LINEOUT_POWERUP 1 ADC_POWERUP 2 CAPLESS_HEADPHONE_POWERUP 3 DAC_POWERUP 4 HEADPHONE_POWERUP 5 REFTOP_POWERUP 6 ADC_MONO 7 VAG_POWERUP 8 VCOAMP_POWERUP 9 LINREG_D_POWERUP 10 PLL_POWERUP 11 VDDC_CHRGPMP_POWERUP 12 STARTUP_POWERUP RSVD 13 LINREG_SIMPLE_POWERUP 14 DAC_MONO 15 BITS FIELD RW RESET DEFINITION 15 RSVD RW 0x0 Reserved 14 DAC_MONO RW 0x1 While DAC_POWERUP is set, this allows the DAC to be put into left only mono operation for power savings. 0x0 = Mono (left only) 0x1 = Stereo 13 LINREG_SIMPLE_PO WERUP RW 0x1 Power up the simple (low power) digital supply regulator. After reset, this bit can be cleared IF VDDD is driven externally OR the primary digital linreg is enabled with LINREG_D_POWERUP 0x0 = Power down 0x1 = Power up 12 STARTUP_POWERUP RW 0x1 Power up the circuitry needed during the power up ramp and reset. After reset this bit can be cleared if VDDD is coming from an external source. 0x0 = Power down 0x1 = Power up 11 VDDC_CHRGPMP_PO WERUP RW 0x0 Power up the VDDC charge pump block. If neither VDDA or VDDIO is 3.0 V or larger this bit should be cleared before analog blocks are powered up. 0x0 = Power down 0x1 = Power up Note that for charge pump to function, either the PLL must be powered on and programmed correctly (refer to CHIP_CLK_CTRL->MCLK_FREQ description) or the internal oscillator (set CLK_TOP_CTRL->ENABLE_INT_OSC) must be enabled 10 PLL_POWERUP RW 0x0 PLL Power Up 0x0 = Power down 0x1 = Power up When cleared, the PLL is turned off. This must be set before CHIP_CLK_CTRL -> MCLK_FREQ is programmed to 0x3. The CHIP_PLL_CTRL register must be configured correctly before setting this bit. 9 LINREG_D_POWERUP RW 0x0 Power up the primary VDDD linear regulator. 0x0 = Power down 0x1 = Power up SGTL5000 42 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW RESET 8 VCOAMP_POWERUP RW 0x0 DEFINITION Power up the PLL VCO amplifier. 0x0 = Power down 0x1 = Power up 7 VAG_POWERUP RW 0x0 Power up the VAG reference buffer. Setting this bit starts the power up ramp for the headphone and LINEOUT. The headphone (and/or LINEOUT) powerup should be set BEFORE clearing this bit. When this bit is cleared the power-down ramp is started. The headphone (and/or LINEOUT) powerup should stay set until the VAG is fully ramped down (200 to 400 ms after clearing this bit). 0x0 = Power down 0x1 = Power up 6 ADC_MONO RW 0x1 While ADC_POWERUP is set, this allows the ADC to be put into left only mono operation for power savings. This mode is useful when only using the microphone input. 0x0 = Mono (left only) 0x1 = Stereo 5 REFTOP_POWERUP RW 0x1 Power up the reference bias currents 0x0 = Power down 0x1 = Power up This bit can be cleared when the part is a sleep state to minimize analog power. 4 HEADPHONE_POWER UP RW 0x0 Power up the headphone amplifiers 0x0 = Power down 0x1 = Power up 3 DAC_POWERUP RW 0x0 Power up the DACs 0x0 = Power down 0x1 = Power up 2 CAPLESS_HEADPHO NE_POWERUP RW 0x0 Power up the capless headphone mode 0x0 = Power down 0x1 = Power up 1 ADC_POWERUP RW 0x0 Power up the ADCs 0x0 = Power down 0x1 = Power up 0 LINEOUT_POWERUP RW 0x0 Power up the LINEOUT amplifiers 0x0 = Power down 0x1 = Power up SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 43 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES The Table 34, CHIP_PLL_CTRL 0x0032 register may only be changed after reset, and before PLL_POWERUP is set. Table 34. CHIP_PLL_CTRL 0x0032 15 14 13 12 11 10 9 8 7 INT_DIVISOR 6 5 4 3 2 1 0 FRAC_DIVISOR BITS FIELD RW RESET DEFINITION 15:11 INT_DIVISOR RW 0xA This is the integer portion of the PLL divisor. To determine the value of this field, use the following calculation: INT_DIVISOR = FLOOR(PLL_OUTPUT_FREQ/INPUT_FREQ) PLL_OUTPUT_FREQ = 180.6336 MHz if System sample rate = 44.1 kHz else PLL_OUTPUT_FREQ = 196.608 MHz if System sample rate!= 44.1 kHz INPUT_FREQ = Frequency of the external MCLK provided if CHIP_CLK_TOP_CTRL>INPUT_FREQ_DIV2 = 0x0 else INPUT_FREQ = (Frequency of the external MCLK provided/2) If CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x1 10:0 FRAC_DIVISOR RW 0x0 This is the fractional portion of the PLL divisor. To determine the value of this field, use the following calculation: FRAC_DIVISOR = ((PLL_OUTPUT_FREQ/INPUT_FREQ) - INT_DIVISOR)*2048 PLL_OUTPUT_FREQ = 180.6336 MHz if System sample rate = 44.1 kHz else PLL_OUTPUT_FREQ = 196.608 MHz if System sample rate!= 44.1 kHz INPUT_FREQ = Frequency of the external MCLK provided if CHIP_CLK_TOP_CTRL>INPUT_FREQ_DIV2 = 0x0 else INPUT_FREQ = (Frequency of the external MCLK provided/2) If CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x1 Table 35, CHIP_CLK_TOP_CTRL 0x0034 has the miscellaneous controls for the clock block. Table 35. CHIP_CLK_TOP_CTRL 0x0034 13 12 RSVD 11 10 9 8 7 6 5 4 3 INPUT_FREQ_DIV2 14 RSVD ENABLE_INT_OSC 15 2 1 0 RSVD BITS FIELD RW RESET DEFINITION 15:12 RESERVED RO 0x0 Reserved 11 ENABLE_INT_OSC RW 0x0 Setting this bit enables an internal oscillator to be used for the zero cross detectors, the short detect recovery, and the charge pump. This allows the I2S clock to be shut off while still operating an analog signal path. This bit can be kept on when the I2S clock is enabled, but the I2S clock is more accurate so it is preferred to clear this bit when I2S is present. 10:4 RSVD RW 0x0 Reserved SGTL5000 44 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW RESET 3 INPUT_FREQ_DIV2 RW 0x0 DEFINITION SYS_MCLK divider before PLL input 0x0 = pass through 0x1 = SYS_MCLK is divided by 2 before entering PLL This must be set when the input clock is above 17 MHz. This has no effect when the PLL is powered down. 2:0 RSVD RW Reserved 0x0 Status bits for analog blocks are found in Table 36, CHIP_ANA_STATUS 0x0036 Table 36. CHIP_ANA_STATUS 0x0036 13 12 11 10 LRSHORT_STS RSVD 9 8 7 6 5 4 3 2 PLL_IS_LOCKED 14 RSVD CSHORT_STS 15 1 0 RSVD BITS FIELD RW RESET DEFINITION 15:10 RSVD RO 0x0 Reserved 9 LRSHORT_STS RO 0x0 This bit is high whenever a short is detected on the left or right channel headphone drivers. 0x0 = Normal 0x1 = Short detected 8 CSHORT_STS RO 0x0 This bit is high whenever a short is detected on the capless headphone common/ center channel driver. 0x0 = Normal 0x1 = Short detected 7:5 RSVD RO 0x0 Reserved 4 PLL_IS_LOCKED RO 0x0 This bit goes high after the PLL is locked. 0x0 = PLL is not locked 0x1 = PLL is locked 3:0 RSVD RO 0x0 Reserved Table 37, CHIP_ANA_TEST1 0x0038 and Table 38, CHIP_ANA_TEST2 0x003A register controls are intended only for debug. Table 37. CHIP_ANA_TEST1 0x0038 6 5 4 3 2 1 0 TESTMODE HP_ANTIPOP 7 TM_SELECT_MIC 8 TM_HPCOMMON 9 TM_ADCIN_TOHP 10 VAG_CLASSA HP_I1_ADJ 11 VAG_DOUB_CURRENT 12 HP_CLASSAB HP_IALL_ADJ 13 HP_HOLD_GND 14 HP_HOLD_GND_CENTER 15 SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 45 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW 15:14 HP_IALL_ADJ RW RESET DEFINITION 0x0 These bits control the overall bias current of the headphone amplifier (all stages including first and output stage). 0x0=nominal, 0x1=-50%, 0x2=+50%, 0x3=-40% 13:12 HP_I1_ADJ RW 0x0 These bits control the bias current for the first stage of the headphone amplifier. 0x0=nominal, 0x1=-50%, 0x2=+100%, 0x3=+50% 11:9 HP_ANTIPOP RW 0x0 These bits control the headphone output current in classA mode and also the pull-down strength while powering off. These bits normally are not needed. 8 HP_CLASSAB RW 0x1 This defaults high. When this bit is high the headphone is in classAB mode. ClassA mode would normally not be used. 7 HP_HOLD_GND_CE NTER RW 0x1 This defaults high. When this bit is high and the capless headphone center channel is powered off, the output is tied to ground. This is the preferred mode of operation for best antipop performance. 6 HP_HOLD_GND RW 0x1 This defaults high. When this bit is high and the headphone is powered off, the output is tied to ground. This is the preferred mode of operation for best antipop performance. 5 VAG_DOUB_CURRE NT RW 0x0 Double the VAG output current when in classA mode. 4 VAG_CLASSA RW 0x0 Turn off the classAB output current for the VAG buffer. The classA current is limited so this may cause clipping in some modes. 3 TM_ADCIN_TOHP RW 0x0 Put ADCmux output onto the headphone output pin. Must remove headphone load and any external headphone compensation for this mode. 2 TM_HPCOMMON RW 0x0 Enable headphone common to be used in ADCmux for testing 1 TM_SELECT_MIC RW 0x0 Enable the mic-adc-dac-HP path 0 TESTMODE RW 0x0 Enable the analog test mode paths Table 38. CHIP_ANA_TEST2 0x003A 9 8 7 6 5 4 3 2 INVERT_ADC_DATA_TIMING 10 INVERT_ADC_SAMPLE_CLOCK 11 INVERT_DAC_DATA_TIMING 12 INVERT_DAC_SAMPLE_CLOCK 13 1 0 Reserved 14 LINEOUT_TO_VDDA RW 0x0 Changes the LINEOUT amplifier power supply from VDDIO to VDDA. Typically LINEOUT should be on the higher power supply. This bit is useful when VDDA is ~3.3 V and VDDIO is ~1.8 V. 13 SPARE RW 0x0 Spare registers to analog. 12 MONOMODE_DAC RW 0x0 Copy the left channel DAC data to the right channel. This allows both left and right to play from MONO dac data. 11 VCO_TUNE_AGAIN RW 0x0 When toggled high then low forces the PLL VCO to retune the number of inverters in the ring oscillator loop. RSVD ADC_DITHEROFF 0x0 ADC_LESSI RO DAC_CLASSA RSVD DAC_DIS_RTZ 15 DAC_DOUBLE_I RESET DAC_EXTEND_RTZ RW MONOMODE_DAC FIELD SPARE BITS LINEOUT_TO_VDDA LO_PASS_MASTERVAG 14 VCO_TUNE_AGAIN 15 DEFINITION SGTL5000 46 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW RESET DEFINITION 10 LO_PASS_MASTERV AG RW 0x0 Tie the main analog VAG to the LINEOUT VAG. This can improve SNR for the LINEOUT when both are the same voltage. 9 INVERT_DAC_SAMPL E_CLOCK RW 0x0 Change the clock edge used for the DAC output sampling. 8 INVERT_DAC_DATA_ TIMING RW 0x0 Change the clock edge used for the digital to analog DAC data crossing. 7 DAC_EXTEND_RTZ RW 0x0 Extend the return-to-zero time for the DAC. 6 DAC_DOUBLE_I RW 0x0 Double the output current of the DAC amplifier when it is in classA mode. 5 DAC_DIS_RTZ RW 0x0 Turn off the return-to-zero in the DAC. In mode cases, this hurts the SNDR of the DAC. 4 DAC_CLASSA RW 0x0 Turn off the classAB mode in the DAC amplifier. This mode should normally not be used. The output current is not high enough to support a full scale signal in this mode. 3 INVERT_ADC_SAMPL E_CLOCK RW 0x0 Change the clock edge used for the ADC sampling. 2 INVERT_ADC_DATA_ TIMING RW 0x0 Change the clock edge used for the analog to digital ADC data crossing 1 ADC_LESSI RW 0x0 Drops ADC bias currents by 20% 0 ADC_DITHEROFF RW 0x0 Turns off the ADC dithering. The Table 39, CHIP_SHORT_CTRL 0x003C register contains controls for the headphone short detectors. Table 39. CHIP_SHORT_CTRL 0x003C 15 14 13 12 11 10 RSVD 9 8 LVLADJL 7 RSVD 6 5 4 LVLADJC 3 2 MODE_LR 1 0 RSVD LVLADJR MODE_CM BITS FIELD RW RESET 15 RSVD RO 0x0 Reserved 14:12 LVLADJR RW 0x0 These bits adjust the sensitivity of the right channel headphone short detector in 25 mA steps.This trip point can vary by ~30% over process so leave plenty of guard band to avoid false trips. This short detect trip point is also effected by the bias current adjustments made by CHIP_REF_CTRL -> BIAS_CTRL and by CHIP_ANA_TEST1 > HP_IALL_ADJ. DEFINITION 0x3=25 mA 0x2=50 mA 0x1=75 mA 0x0=100 mA 0x4=125 mA 0x5=150 mA 0x6=175 mA 0x7=200 mA 11 RSVD RO 0x0 Reserved SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 47 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW RESET DEFINITION 10:8 LVLADJL RW 0x0 These bits adjust the sensitivity of the left channel headphone short detector in 25 mA steps.This trip point can vary by ~30% over process so leave plenty of guard band to avoid false trips. This short detect trip point is also effected by the bias current adjustments made by CHIP_REF_CTRL -> BIAS_CTRL and by CHIP_ANA_TEST1 > HP_IALL_ADJ. 0x3=25 mA 0x2=50 mA 0x1=75 mA 0x0=100 mA 0x4=125 mA 0x5=150 mA 0x6=175 mA 0x7=200 mA 7 RSVD RO 0x0 Reserved 6:4 LVLADJC RW 0x0 These bits adjust the sensitivity of the capless headphone center channel short detector in 50 mA steps. This trip point can vary by ~30% over process so leave plenty of guard band to avoid false trips. This short detect trip point is also effected by the bias current adjustments CHIP_REF_CTRL -> BIAS_CTRL and by CHIP_ANA_TEST1 -> HP_IALL_ADJ. 0x3=50 mA 0x2=100 mA 0x1=150 mA 0x0=200 mA 0x4=250 mA 0x5=300 mA 0x6=350 mA 0x7=400 mA 3:2 MODE_LR RW 0x0 These bits control the behavior of the short detector for the capless headphone central channel driver. This mode should be set prior to powering up the headphone amplifier. When a short is detected the amplifier output switches to classA mode internally to avoid excessive currents. 0x0 = Disable short detector, reset short detect latch, software view non-latched short signal 0x1 = Enable short detector and reset the latch at timeout (every ~50 ms) 0x2 = This mode is not used/invalid 0x3 = Enable short detector with only manual reset (have to return to 0x0 to reset the latch) 1:0 MODE_CM RW 0x0 These bits control the behavior of the short detector for the capless headphone central channel driver. This mode should be set prior to powering up the headphone amplifier. When a short is detected the amplifier output switches to classA mode interally to avoid excessive currents. 0x0 = Disable short detector, reset short detect latch, software view non-latched short signal 0x1 = Enable short detector and reset the latch at timeout (every ~50 ms) 0x2 = Enable short detector and auto reset when output voltage rises (preferred mode) 0x3 = Enable short detector with only manual reset (have to return to 0x0 to reset the latch) SGTL5000 48 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 40. DAP_CONTROL 0x0100 15 14 13 12 11 10 9 8 7 6 5 4 RSVD 3 2 MIX_EN BITS FIELD RW RESET 15:5 RSVD RO 0x0 Reserved 4 MIX_EN RW 0x0 Enable/Disable the DAP mixer path 1 0 RSVD DAP_EN DEFINITION 0x0 = Disable 0x1 = Enable When enabled, DAP_EN must also be enabled to use the mixer. 3:1 RSVD RO 0x0 Reserved 0 DAP_EN RW 0x0 Enable/Disable digital audio processing (DAP) 0x0 = Disable. When disabled, no audio passes through. 0x1 = Enable. When enabled, audio can pass through DAP even if none of the DAP functions are enabled. Table 41. DAP_PEQ 0x0102 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RSVD 1 0 EN BITS FIELD RW RESET DEFINITION 15:3 RSVD RO 0x0 Reserved 2:0 EN RW 0x0 Set to Enable the PEQ filters 0x0 = Disabled 0x1 = 1 Filter Enabled 0x2 = 2 Filters Enabled ..... 0x7 = Cascaded 7 Filters DAP_AUDIO_EQ->EN bit must be set to 1 in order to enable the PEQ Table 42. DAP_BASS_ENHANCE 0x0104 14 13 12 11 10 9 8 BYPASS_HPF 15 RSVD 7 6 RSVD BITS FIELD RW RESET 15:9 RSVD RO 0x0 Reserved 8 BYPASS_HPF RW 0x0 Bypass high pass filter 5 4 CUTOFF 3 2 RSVD 1 0 EN DEFINITION 0x0 = Enable high pass filter 0x1 = Bypass high pass filter 7 RSVD RO 0x0 Reserved SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 49 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW RESET 6:4 CUTOFF RW 0x4 DEFINITION Set cut-off frequency 0x0 = 80 Hz 0x1 = 100 Hz 0x2 = 125 Hz 0x3 = 150 Hz 0x4 = 175 Hz 0x5 = 200 Hz 0x6 = 225 Hz 3:1 RSVD RO 0x0 Reserved 0 EN RW 0x0 Enable/Disable Bass Enhance 0x0 = Disable 0x1 = Enable Table 43. DAP_BASS_ENHANCE_CTRL 0x0106 15 14 RSVD 13 12 11 10 9 8 LR_LEVEL 7 RSVD 6 5 4 3 2 1 0 3 2 1 0 BASS_LEVEL BITS FIELD RW RESET DEFINITION 15:14 RSVD RO 0x0 Reserved 13:8 LR_LEVEL RW 0x5 Left/Right Mix Level Control 0x00= +6.0 dB for Main Channel ...... 0x3F= Least L/R Channel Level 7 RSVD RO 0x0 6:0 BASS_LEVEL RW 0x1f Bass Harmonic Level Control 0x00= Most Harmonic Boost ...... 0x7F=Least Harmonic Boost Table 44. DAP_AUDIO_EQ 0x0108 15 14 13 12 11 10 9 8 7 6 5 4 RSVD EN BITS FIELD RW RESET DEFINITION 15:2 RSVD RO 0x0 Reserved 1:0 EN RW 0x0 Selects between PEQ/GEQ/Tone Control and Enables it. 0x0 = Disabled. 0x1 = Enable PEQ. NOTE: DAP_PEQ->EN bit must also be set to the desired number of filters (bands) in order for the PEQ to be enabled. 0x2 = Enable Tone Control 0x3 = Enable 5 Band GEQ SGTL5000 50 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 45. DAP_SGTL_SURROUND 0x010A 15 14 13 12 11 10 9 8 7 RSVD 6 5 4 3 WIDTH_CONTROL 2 RSVD 1 0 SELECT BITS FIELD RW RESET DEFINITION 15:7 RSVD RO 0x0 Reserved 6:4 WIDTH_CONTROL RW 0x4 Freescale Surround Width Control - The width control changes the perceived width of the sound field. 0x0 = Least Width ...... 0x7 = Most Width 3:2 RSVD RO 0x0 Reserved 1:0 SELECT RW 0x0 Freescale Surround Selection 0x0 = Disabled 0x1 = Disabled 0x2 = Mono input Enable 0x3 = Stereo input Enable Table 46. DAP_FILTER_COEF_ACCESS 0x010C 15 14 13 12 11 10 9 RSVD 8 7 6 5 WR 4 3 2 1 0 INDEX BITS FIELD RW RESET DEFINITION 15:9 RSVD RO 0x0 Reserved 8 WR WO 0x0 When set, the coefficients written in the ten coefficient data registers are loaded into the filter specified by INDEX 7:0 INDEX RW 0x0 Specifies the index for each of the seven bands of the filter coefficient that needs to be written to. Each filter has 5 coefficients that need to be loaded into the 10 coefficient registers (MSB, LSB) before setting the index and WR bit. Steps to write coefficients: 1. Write the five 20-bit coefficient values to DAP_COEF_WR_XX_MSB and DAP_COEF_WR_XX_LSB registers (XX= B0,B1,B2,A1,A2) 2. Set INDEX of the coefficient from the table below. 3. Set the WR bit to load the coefficient. NOTE: Steps 2 and 3 can be performed with a single write to DAP_FILTER_COEF_ACCESS register. Coefficient address: Band 0 = 0x00 Band 1 = 0x01 Band 2 = 0x02 Band 3 = 0x03 Band 4 = 0x04 ... Band 7 = 0x06 SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 51 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 47. DAP_COEF_WR_B0_MSB 0x010E 15 14 13 12 11 10 9 8 7 6 5 BIT_19 BIT_18 BIT_17 BIT_16 BIT_15 BIT_14 BIT_13 BIT_12 BIT_11 BIT_10 BIT_9 BITS FIELD RW RESET 15 BIT_19 WO 0x0 14 BIT_18 WO 0x0 13 BIT_17 WO 0x0 12 BIT_16 WO 0x0 11 BIT_15 WO 0x0 10 BIT_14 WO 0x0 9 BIT_13 WO 0x0 8 BIT_12 WO 0x0 7 BIT_11 WO 0x0 6 BIT_10 WO 0x0 5 BIT_9 WO 0x0 4 BIT_8 WO 0x0 3 BIT_7 WO 0x0 2 BIT_6 WO 0x0 1 BIT_5 WO 0x0 0 BIT_4 WO 0x0 4 3 2 1 0 BIT_8 BIT_7 BIT_6 BIT_5 BIT_4 DEFINITION Most significant 16-bits of the 20-bit filter coefficient that needs to be written Table 48. DAP_COEF_WR_B0_LSB 0x0110 15 14 13 12 11 10 9 8 7 6 5 4 RSVD BITS FIELD RW RESET 15:4 RSVD RO 0x0 3 BIT_3 WO 0x0 2 BIT_2 WO 0x0 1 BIT_1 WO 0x0 0 BIT_0 WO 0x0 3 2 1 0 BIT_3 BIT_2 BIT_1 BIT_0 DEFINITION Least significant 4 bits of the 20-bit filter coefficient that needs to be written. SGTL5000 52 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 49. DAP_AUDIO_EQ_BASS_BAND0 0x0116 115 Hz 15 14 13 12 11 10 9 8 7 6 5 4 RSVD 3 2 1 0 2 1 0 2 1 0 VOLUME BITS FIELD RW RESET 15:7 RSVD RO 0x0 6:0 VOLUME RW 0x2F DEFINITION Reserved Sets Tone Control Bass/GEQ Band0 0x5F = sets to 12 dB 0x2F = sets to 0 dB 0x00 = sets to -11.75 dB Each LSB is 0.25 dB Table 50. DAP_AUDIO_EQ_BAND1 0x0118 330 Hz 15 14 13 12 11 10 9 8 7 6 5 4 RSVD 3 VOLUME BITS FIELD RW RESET 15:7 RSVD RO 0x0 6:0 VOLUME RW 0x2F DEFINITION Reserved Sets GEQ Band1 0x5F = sets to 12 dB 0x2F = sets to 0 dB 0x00 = sets to -11.75 dB Each LSB is 0.25 dB Table 51. DAP_AUDIO_EQ_BAND2 0x011A 990 Hz 15 14 13 12 11 10 9 8 7 6 5 4 RSVD 3 VOLUME BITS FIELD RW RESET 15:7 RSVD RO 0x0 6:0 VOLUME RW 0x2F DEFINITION Reserved Sets GEQ Band2 0x5F = sets to 12 dB 0x2F = sets to 0 dB 0x00 = sets to -11.75 dB Each LSB is 0.25 dB SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 53 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 52. DAP_AUDIO_EQ_BAND3 0x011C 3000 Hz 15 14 13 12 11 10 9 8 7 6 5 4 3 RSVD 2 1 0 VOLUME BITS FIELD RW RESET 15:7 RSVD RO 0x0 6:0 VOLUME RW 0x2F DEFINITION Reserved Sets GEQ Band3 0x5F = sets to 12 dB 0x2F = sets to 0 dB 0x00 = sets to -11.75 dB Each LSB is 0.25 dB Table 53. DAP_AUDIO_EQ_TREBLE_BAND4 0x011E 9900 Hz 15 14 13 12 11 10 9 8 7 6 5 4 RSVD BITS FIELD RW 3 2 1 0 2 1 0 VOLUME RESET 15:7 RSVD RO 0x0 6:0 VOLUME RW 0x2F DEFINITION Reserved Sets Tone Control Treble/GEQ Band4 0x5F = sets to 12 dB 0x2F = sets to 0 dB 0x00 = sets to -11.75 dB Each LSB is 0.25 dB Table 54, DAP_MAIN_CHAN 0x0120 sets the main channel volume level . Table 54. DAP_MAIN_CHAN 0x0120 15 14 13 12 11 10 9 8 7 6 5 4 3 VOL BITS FIELD RW RESET 15:0 VOL RW 0x8000 DEFINITION DAP Main Channel Volume 0xFFFF = 200% 0x8000 (default) = 100% 0x0000 = 0% Table 55, DAP_MIX_CHAN 0x0122 sets the mix channel volume level . Table 55. DAP_MIX_CHAN 0x0122 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VOL BITS FIELD RW RESET 15:0 VOL RW 0x0000 DEFINITION DAP Mix Channel Volume 0xFFFF = 200% 0x8000 = 100% 0x0000 (default) = 0% SGTL5000 54 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 56. DAP_AVC_CTRL 0x0124 14 RSVD RSVD 13 12 11 MAX_GAIN 10 RSVD 9 8 7 LBI_RESPONSE 6 RSVD 5 4 3 HARD_LIMIT_EN 15 2 1 0 RSVD EN BITS FIELD RW RESET DEFINITION 15 RSVD RO 0x0 Reserved 14 RSVD RW 0x1 Reserved. 13:12 MAX_GAIN RW 0x1 Maximum gain that can be applied by the AVC in expander mode. 0x0 = 0 dB gain 0x1 = 6.0 dB of gain 0x2 = 12 dB of gain 11:10 RSVD RO 0x0 Reserved 9:8 LBI_RESPONSE RW 0x1 Integrator Response 0x0 = 0 mS LBI 0x1 = 25 mS LBI 0x2 = 50 mS LBI 0x3 = 100 mS LBI 7:6 RSVD RO 0x0 Reserved 5 HARD_LIMIT_EN RW 0x0 Enable Hard Limiter Mode 0x0 = Hard limit disabled. AVC Compressor/Expander is enabled. 0x1 = Hard limit enabled. The signal is limited to the programmed threshold. (Signal saturates at the threshold) 4:1 RSVD RO 0x0 Reserved 0 EN RW 0x0 Enable/disable AVC 0x0 = Disable 0x1 = Enable Table 57. DAP_AVC_THRESHOLD 0x0126 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 THRESH BITS FIELD RW RESET 15:0 THRESH RW 0x1473 DEFINITION AVC Threshold Value Threshold is programmable. Use the following formula to calculate hex value: Hex Value = ((10^(THRESHOLD_dB/20))*0.636)*2^15 Threshold can be set in the range of 0 dB to -96 dB Example Values: 0x1473 = Set Threshold to -12 dB 0x0A40 = Set Threshold to -18 dB SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 55 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 58. DAP_AVC_ATTACK 0x0128 15 14 13 12 11 10 9 8 7 6 RSVD 5 4 3 2 1 0 RATE BITS FIELD RW RESET DEFINITION 15:12 RSVD RO 0x0 Reserved 11:0 RATE RW 0x28 AVC Attack Rate This is the rate at which the AVC applies attenuation to the signal to bring it to the threshold level. AVC Attack Rate is programmable. To use a custom rate, use the formula below to convert from dB/S to hex value: Hex Value = (1 - (10^(-(Rate_dBs/(20*SYS_FS)))) * 2^19 where, SYS_FS is the system sample rate configured in CHIP_CLK_CTRL register. Example values: 0x28 = 32 dB/s 0x10 = 8.0 dB/s 0x05 = 4.0 dB/s 0x03 = 2.0 dB/s Table 59. DAP_AVC_DECAY 0x012A 15 14 13 12 11 10 9 8 7 6 RSVD 5 4 3 2 1 0 RATE BITS FIELD RW RESET DEFINITION 15:12 RSVD RO 0x0 Reserved 11:0 RATE RW 0x50 AVC Decay Rate This is the rate at which the AVC releases the attenuation previously applied to the signal during attack. AVC Decay Rate is programmable. To use a custom rate, use the formula below to convert from dB/S to hex value: Hex Value = (1 - (10^(-(Rate_dBs/(20*SYS_FS)))) * 2^23 where, SYS_FS is the system sample rate configured in CHIP_CLK_CTRL register. Example values: 0x284 = 32 dB/s 0xA0 = 8.0 dB/s 0x50 = 4.0 dB/s 0x28 = 2.0 dB/s Table 60. DAP_COEF_WR_B1_MSB 0x012C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSB BITS FIELD RW RESET 15:0 MSB RW 0x0 DEFINITION Most significant 16-bits of the 20-bit filter coefficient that needs to be written SGTL5000 56 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 61. DAP_COEF_WR_B1_LSB 0x012E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RSVD 1 0 LSB BITS FIELD RW RESET DEFINITION 15:4 RSVD RO 0x0 Reserved 3:0 LSB RW 0x0 Least significant 4 bits of the 20-bit filter coefficient that needs to be written. Table 62. DAP_COEF_WR_B2_MSB 0x0130 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSB BITS FIELD RW RESET 15:0 MSB RW 0x0 DEFINITION Most significant 16-bits of the 20-bit filter coefficient that needs to be written Table 63. DAP_COEF_WR_B2_LSB 0x0132 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RSVD 1 0 LSB BITS FIELD RW RESET DEFINITION 15:4 RSVD RO 0x0 Reserved 3:0 LSB RW 0x0 Least significant 4 bits of the 20-bit filter coefficient that needs to be written. Table 64. DAP_COEF_WR_A1_MSB 0x0134 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSB BITS FIELD RW RESET 15:0 MSB RW 0x0 DEFINITION Most significant 16-bits of the 20-bit filter coefficient that needs to be written Table 65. DAP_COEF_WR_A1_LSB 0x0136 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RSVD 1 0 LSB BITS FIELD RW RESET DEFINITION 15:4 RSVD RO 0x0 Reserved 3:0 LSB RW 0x0 Least significant 4 bits of the 20-bit filter coefficient that needs to be written. Table 66. DAP_COEF_WR_A2_MSB 0x0138 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSB BITS FIELD RW RESET 15:0 MSB RW 0x0 DEFINITION Most significant 16-bits of the 20-bit filter coefficient that needs to be written SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 57 FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 67. DAP_COEF_WR_A2_LSB 0x013A 15 14 13 12 11 10 9 8 7 6 5 4 RSVD 3 2 1 0 LSB BITS FIELD RW RESET DEFINITION 15:4 RSVD RO 0x0 Reserved 3:0 LSB RW 0x0 Least significant 4 bits of the 20-bit filter coefficient that needs to be written. SGTL5000 58 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS INTRODUCTION TYPICAL APPLICATIONS INTRODUCTION connected to a 0.1 F cap to GND. If either is > 3.0 V, the CPFILT cap MUST NOT be placed. HP_VGND Note: Do not connect HP_VGND to system ground, even when unused. This is a virtual ground (DC voltage) that should never connect to an actual “0 Volt ground”. Use the widest, shortest trace possible for the HP_VGND. Typical connections are shown in the following application diagrams. For new designs, and for either the 20 QFN or 32 QFN part, an external VDDD power supply connection is required along with a 0.1 F cap connection from VDDD to ground. CPFILT Note: The CPFILT cap value is 0.1 F. If both VDDIO and VDDA are  3.0 V, the CPFILT pin must be VDDD (1.1V - 2.0V, 11mA Min) 32QFN Typical Application Schematic Note: External VDDD required for new designs. C1 0.1uF CTRL_MODE CTRL_ADR0_CS VDDD CTRL_CLK NC CTRL_DATA I2S_DIN I2S_DOUT Note: Capless headphone design shown here. For cap-coupled design, see 20QFN Typical Application Schematic. 1 2 3 4 5 6 7 8 2 3 4 5 1 J1 Audio Jack GND HP_R GND HP_VGND VDDA HP_L AGND NC C3 9 10 11 12 13 14 15 16 0.1uF SGTL5000_32QFN Notes: C5 1. This 32QFN schematic shows VDDD (pin 30) being derived externally. An external VDDD is required for new designs. For lowest power operation, VDDD can be driven from an external 1.2V switching supply with a 0.1uF capacitor to ground. 2. If both VDDIO and VDDA are equal to or below 3V, the CPFILT pin (pin 17) must be connected to a 0.1uF capacitor to ground. If either is above 3V, this capacitor must not be placed. 3. The above shows I2C implementation as CTRL_MODE (pin 32) is tied to ground. In addition, address 0 of the I2C address is 0 as CTRL_ADR0_CS (pin 31) is tied to ground. I2S_SCLK I2S_LRCLK NC SYS_MCLK VDDIO NC CPFILT NC NC VAG LINEOUT_R LINEOUT_L LINEIN_R LINEIN_L MIC MIC_BIAS VDDA I2S_DIN I2S_DOUT I2S_SCLK I2S_LRCLK 32 31 30 29 28 27 26 25 U1 CTRL_CLK CTRL_DATA GND SYS_MCLK 24 23 22 21 20 19 18 17 VDDIO C2 0.1uF PAD Solder Pad to GND C4 0.1uF X1 1 2 0.1uF MIC C6 1uF LINE_OUT_R C7 R1 1uF Note: R1 only needed if internal BIAS_RESISTOR settings are not suitable. LINE_OUT_L C8 2.2k 1uF C9 1uF LINE_IN_L LINE_IN_R C10 1uF 4. AGND (pin 7) should be "star" connected to the jack grounds for LINEIN and LINEOUT, and to the VAG capacitor ground. This node should via to the ground plane (or connected to ground) at a single point. Figure 19. 32 QFN Typical Application Schematic SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 59 TYPICAL APPLICATIONS INTRODUCTION VDDD (1.1V - 2.0V, 11mA Min) Note: External VDDD required for new designs. I2C_CLK I2C_DATA C1 I2S_DIN I2SDOUT I2S_SCLK I2S_LRCLK 0.1uF 20 19 18 17 16 U1 J1 2 3 4 5 1 C2 220uF C3 220uF VDDD CTRL_CLK CTRL_DATA I2S_DIN I2S_DOUT Note: Cap-coupled headphone design shown here. For capless design, see 32QFN Typical Application Schematic. 1 2 3 4 5 VDDA HP_R HP_VGND VDDA HP_L VAG I2S_SCLK I2S_LRCLK SYS_MCLK VDDIO MIC_BIAS LINEOUT_R LINEOUT_L LINEIN_R LINEIN_L MIC Audio Jack C5 0.1uF SGTL5000_20QFN 15 14 13 12 11 VDDIO C4 0.1uF GND PAD R1 Solder Pad to GND 6 7 8 9 10 C6 0.1uF SYS_MCLK C7 2.2k C8 1uF Note: R1 only needed if internal BIAS_RESISTOR settings are not suitable. 0.1uF X1 C9 1uF C10 LINE_OUT_RIGHT 1 2 1uF LINE_IN_LEFT LINE_OUT_LEFT MIC LINE_IN_RIGHT C11 1uF C12 1uF Note: Bottom PAD/FLAG/Paddle MUST be connected to ground. Figure 20. 20 QFN Typical Application Schematic SGTL5000 60 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the 98Axxxxxxxxx listed on the following pages. EP SUFFIX 20-PIN 98ARE10742D REVISION 0 SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 61 PACKAGING PACKAGE DIMENSIONS EP SUFFIX 20-PIN 98ARE10742D REVISION 0 SGTL5000 62 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS EP SUFFIX 20-PIN 98ARE10742D REVISION 0 SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 63 PACKAGING PACKAGE DIMENSIONS FC SUFFIX 32-PIN 98ARE10739D REVISION 0 SGTL5000 64 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS FC SUFFIX 32-PIN 98ARE10739D REVISION 0 SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 65 PACKAGING PACKAGE DIMENSIONS FC SUFFIX 32-PIN 98ARE10739D REVISION 0 SGTL5000 66 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION 3.0 6/2010 • 4.0 9/2010 • Corrected Pin 4 explanation (32-pin package) and added Pin 3 (32-Pin package) to Table 1. 5/2013 • • • • • • Corrected LINEOUT - 100 dB SNR (-60 dB input) and -85 dB THD+N (VDDIO = 3.3 V) in features Added note for HP_VGND and CPFILT in pin definition table Moved Recommended Operating Conditions to separate table Added Input/Output Electrical Characteristics Corrected LINEIN Input Level from 0.75 to 0.57 Corrected Table 7 Test Conditions unless otherwise noted: VDDIO = 1.8 V, VDDA = 1.8 V, TA = 25 °C, Slave mode, fS = 48 kHz, MCLK = 256 fS, 24 bit input Added note for HP_VGND and CPFILT to Typical Applications introduction Corrected pin nomenclature as required for consistency Clarified Bits 3:0 in Figure 27 Corrected pin name in Figure 3 and Table 1 Corrected address name in Figure 6, I2C, SPI Changed limits on LINEOUT Output level Changed 0x00 = sets to 12 dB to 11.75 dB, and deleted “To convert dB to hex value, use Hex Value = 4* dB value + 47” on tables 49, 50, 51, 52 and 53. Revised back page. Updated document properties. Added SMARTMOS sentence to first paragraph. Added comment for “new designs” where applicable Corrected pin designations in the Pin Connections section Changed limits and conditions for LINEOUT Output level and LINEOUT Output level Added two new application diagrams in Typical Applications section 5.0 • • • • • • • • • • • • 6.0 11/2013 • • • • • • Conversion from the old Freescale form and style to the current version. No existing content has been added, altered, or removed. Modified front page intro text to include more target markets and to remove type of IC technology Increased HP max output power from 45 mW to 62.5 mW at 1.02 kHz based on bench measurements Changed TYP LINEIN input impedance from 100kohm to 29 kohm at 1.02 kHz based on bench measurements Added MIC input impedance based on bench measurements Removed 10 kohm MIN LINEIN input impedance, and added 29 kohm as TYP in Table 5 and Table 6 Added 12 kHz sample rate to Functional Description Introduction, and added 12 kHz and 24 kHz sample rates to Table 8 SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 67 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. Home Page: freescale.com There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based Web Support: freescale.com/support Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no on the information in this document. warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale and the Freescale logo, are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. Document Number: SGTL5000 Rev. 6.0 11/2013