SI9410DY,518

Si9410DY N-channel TrenchMOS ™ logic level FET Rev. 03 — 23 January 2004 M3D315 Product data 1. Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS™ technology. 2. Features ■ Low on-state resistance ■ Fast switching 3. Applications ■ ■ ■ ■ ■ DC-to-DC converters DC motor control Lithium-ion battery applications Notebook PC Portable equipment applications. 4. Pinning information Table 1: Pinning - SOT96-1 (SO8), simplified outline and symbol Pin Description 1 n/c 2,3 source (s) 4 gate (g) 5,6,7,8 drain (d) Simplified outline 8 5 1 4 Symbol d g Top view MBK187 SOT96-1 (SO8) MBB076 s Si9410DY Philips Semiconductors N-channel TrenchMOS ™ logic level FET 5. Quick reference data Table 2: Quick reference data Symbol Parameter Conditions Typ Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj ≤ 150 °C - 30 V ID drain current (DC) Tamb = 25 °C; pulsed; tp ≤ 10 s - 7 A Ptot total power dissipation Tamb = 25 °C; pulsed; tp ≤ 10 s - 2.5 W Tj junction temperature - 150 °C RDSon drain-source on-state resistance VGS = 10 V; ID = 7 A 19 30 mΩ VGS = 5 V; ID = 4 A 23 40 mΩ VGS = 4.5 V; ID = 3.5 A 25 50 mΩ 6. Ordering information Table 3: Ordering information Type number Si9410DY Package Name Description Version SO8 Plastic small outline package; 8 leads SOT96-1 7. Limiting values Table 4: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS drain-source voltage (DC) VGS gate-source voltage (DC) ID drain current (DC) IDM peak drain current Ptot total power dissipation Conditions Min Max Unit 25 °C ≤ Tj ≤ 150 °C - 30 V - ±20 V Tamb = 25 °C; pulsed; tp ≤ 10 s; Figure 2 and 3 - 7 A Tamb = 70 °C; pulsed; tp ≤ 10 s; Figure 2 - 5.8 A Tamb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 - 20.8 A Tamb = 25 °C; pulsed; tp ≤ 10 s; Figure 1 - 2.5 W Tamb = 70 °C; pulsed; tp ≤ 10 s; Figure 1 - 1.6 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C - 2.3 A Source-drain diode IS source (diode forward) current (DC) Tamb = 25 °C; pulsed: tp ≤ 10 s © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12542 Product data Rev. 03 — 23 January 2004 2 of 12 Si9410DY Philips Semiconductors N-channel TrenchMOS ™ logic level FET 03aa11 120 03aa19 120 Ider (%) Pder (%) 80 80 40 40 0 0 0 50 100 150 200 Tamb (°C) 0 50 100 150 200 Tamb (°C) VGS ≥ 10 V P tot P der = ---------------------- × 100% P ° ID I D = ------------------- × 100% I ° tot ( 25 C ) D ( 25 C ) Fig 1. Normalized total power dissipation as a function of ambient temperature. Fig 2. Normalized continuous drain current as a function of ambient temperature. 03ae46 102 ID (A) Limit RDSon = VDS /ID tp = 10 µ s 10 1 ms 1 100 ms DC 1s 10-1 10-2 10-1 10 s 1 10 VDS (V) 102 Tamb = 25 °C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12542 Product data Rev. 03 — 23 January 2004 3 of 12 Si9410DY Philips Semiconductors N-channel TrenchMOS ™ logic level FET 8. Thermal characteristics Table 5: Thermal characteristics Symbol Parameter thermal resistance from junction to ambient Rth(j-a) Conditions Min Typ Max Unit mounted on a printed-circuit board; minimum footprint, tp ≤ 10 s; Figure 4 - - 50 K/W 8.1 Transient thermal impedance 03ae45 102 Zth(j-a) δ = 0.5 (K/W) 0.2 10 0.1 0.05 0.02 1 δ= P single pulse tp T t tp T 10-1 10-5 10-4 10-3 10-2 10-1 1 10 tp (s) Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12542 Product data Rev. 03 — 23 January 2004 4 of 12 Si9410DY Philips Semiconductors N-channel TrenchMOS ™ logic level FET 9. Characteristics Table 6: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 1 - - V Tj = 25 °C - - 2 µA Tj = 55 °C - - 25 µA - - 100 nA Static characteristics VGS(th) gate-source threshold voltage ID = 250 µA; VDS = VGS; Figure 9 IDSS drain-source leakage current VDS = 24 V; VGS = 0 V IGSS gate-source leakage current RDSon drain-source on-state resistance VGS = ±20 V; VDS = 0 V VGS = 10 V; ID = 7 A; Figure 7 and 8 - 19 30 mΩ VGS = 5 V; ID = 4 A; Figure 8 - 23 40 mΩ VGS = 4.5 V; ID = 3.5 A; Figure 7 and 8 - 25 50 mΩ Dynamic characteristics gfs forward transconductance VDS = 15 V; ID = 7 A - 15 - S Qg(tot) total gate charge ID = 7 A; VDS = 15 V; VGS = 10 V; Figure 13 - 14.6 50 nC Qgs gate-source charge - 2 - nC Qgd gate-drain (Miller) charge - 3 - nC td(on) turn-on delay time - 5 30 ns tr rise time - 6 60 ns td(off) turn-off delay time - 21 150 ns tf fall time - 11 140 ns - 0.85 1.1 V - 30 - ns VDD = 25 V; RD = 25 Ω; VGS = 10 V; RG = 6 Ω Source-drain (reverse) diode VSD source-drain (diode forward) voltage IS = 2 A; VGS = 0 V; Figure 12 trr reverse recovery time IS = 2 A; dIS/dt = −100 A/µs; VGS = 0 V © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12542 Product data Rev. 03 — 23 January 2004 5 of 12 Si9410DY Philips Semiconductors N-channel TrenchMOS ™ logic level FET 03ae47 30 10 V 6 V 4.5 V Tj = 25 °C ID (A) 3.6 V 3.4 V 20 03ae49 30 4V VDS > ID x RDSon ID (A) 20 3.2 V 3V 10 10 2.8 V 150 °C Tj = 25 °C 2.6 V VGS = 2.4 V 0 0 0 0.2 0.4 0.6 0.8 1 VDS (V) Tj = 25 °C 0 1 2 3 4 VGS (V) Tj = 25 °C and 150 °C; VDS > ID x RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristic: drain current as a function of gate-source voltage; typical values. 03ae48 60 Tj = 25 °C 03ad57 2 VGS = 3.2 V a RDSon 3.4 V (mΩ) 1.5 3.6 V 40 4V 1 4.5 V 6V 10 V 20 0.5 0 0 0 10 20 ID (A) 30 Tj = 25 °C -60 0 60 120 Tj (°C) 180 R DSon a = --------------------------R ° DSon ( 25 C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12542 Product data Rev. 03 — 23 January 2004 6 of 12 Si9410DY Philips Semiconductors N-channel TrenchMOS ™ logic level FET 03aa33 2.5 VGS(th) max ID (A) 10-2 typ 10-3 (V) 2 1.5 03ai52 10-1 min min 1 typ max 10-4 10-5 0.5 10-6 0 -60 0 60 120 Tj (°C) 180 0 ID = 250 µA; VDS = VGS 1 2 3 VGS (V) Tj = 25 °C; VDS = 5 V Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. 03ae52 103 Ciss C (pF) 102 Coss Crss 10 10-1 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12542 Product data Rev. 03 — 23 January 2004 7 of 12 Si9410DY Philips Semiconductors N-channel TrenchMOS ™ logic level FET 03ae51 30 ID = 7 A VGS (V) 8 VGS = 0 V IS (A) 03ae53 10 Tj = 25 °C VDD = 15 V 20 6 4 10 150 °C Tj = 25 °C 2 0 0 0 0.3 0.6 0.9 1.2 VSD (V) Tj = 25 °C and 150 °C; VGS = 0 V 0 10 15 QG (nC) ID = 7 A; VDD = 15 V Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 13. Gate-source voltage as a function of gate charge; typical values. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12542 Product data 5 Rev. 03 — 23 January 2004 8 of 12 Si9410DY Philips Semiconductors N-channel TrenchMOS ™ logic level FET 10. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 inches 0.010 0.057 0.069 0.004 0.049 0.05 0.244 0.039 0.028 0.041 0.228 0.016 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 14. SOT96-1 (SO8). © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12542 Product data Rev. 03 — 23 January 2004 9 of 12 Si9410DY Philips Semiconductors N-channel TrenchMOS ™ logic level FET 11. Revision history Table 7: Revision history Rev Date 03 20040123 CPCN Description HZG469 Product data (9397 750 12542) Modifications: • • • • • • • • • • 02 20010705 - Updated to latest standards. Section 7 “Limiting values” Figure 3 modified. Section 8 “Thermal characteristics” Figure 4 modified. Section 9 “Characteristics” Rdson modified. Section 9 “Characteristics” ID(on) removed. Section 9 “Characteristics” Qg(tot), Qgs and Qgd modified. Section 9 “Characteristics” tdon, tr, tdoff and tf modified. Section 9 “Characteristics” forward transfer characteristic graph removed. Section 9 “Characteristics” trr removed. Section 9 “Characteristics” Figure 5, 6, 7, 10, 11, 12 and 13 modified. Product data (9397 750 08238) Modification: • 01 20010515 - Correction to IDM condition. Product data; initial version © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12542 Product data Rev. 03 — 23 January 2004 10 of 12 Si9410DY Philips Semiconductors N-channel TrenchMOS ™ logic level FET 12. Data sheet status Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 13. Definitions 14. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 15. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. Product data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12542 Rev. 03 — 23 January 2004 11 of 12 Philips Semiconductors Si9410DY N-channel TrenchMOS ™ logic level FET Contents 1 2 3 4 5 6 7 8 8.1 9 10 11 12 13 14 15 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 © Koninklijke Philips Electronics N.V. 2004. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 23 January 2004 Document order number: 9397 750 12542