SJA1105
5-port automotive Ethernet switch
Rev. 1 — 7 November 2016
Product data sheet
1. General description
The SJA1105 is an IEEE 802.3-compliant 5-port automotive Ethernet switch. Each of the
five ports can be individually configured to operate in MII, RMII and RGMII modes. This
arrangement provides the flexibility to connect a mix of switches, microprocessors and
PHY devices such as the TJA1100 BroadR-Reach PHY from NXP Semiconductors
(Ref. 1 and Ref. 2) and other commercially available Fast Ethernet and Gigabit Ethernet
PHYs. The high-speed interface makes it easy to cascade multiple SJA1105s for
scalability. It can be used in various automotive scenarios such as gateway applications,
body domain controllers or for interconnecting multiple ECUs in a daisy chain. Audio
Video Bridging (AVB) support (Ref. 3) fully leverages infotainment and advanced driver
assistance systems.
The SJA1105 comes in two pin-compatible variants. The SJA1105EL supports Ethernet
and AVB. The SJA1105TEL includes additional functionality to support Time-Triggered
Ethernet (TTEthernet) and Time-Sensitive Networking (TSN).
2. Features and benefits
2.1 General features
5-port store and forward architecture
Each port individually configurable for MII and RMII operation at 10 Mbit/s or
100 Mbit/s and RGMII operation at 10 Mbit/s, 100 Mbit/s or 1000 Mbit/s
Interface-dependent selectable I/O supply voltages; 1.2 V core voltage
Small footprint: LFBGA159 (12 mm 12 mm) package
Automotive Grade 2 ambient operating temperature: 40 C to +105 C
Automotive product qualification in accordance with AEC-Q100
2.2 Ethernet switching and AVB features
IEEE 802.3 compliant
128 kB frame buffer
1024 entry MAC address learning table
Address learning space can be configured for static and learned addresses
2 kB frame length handling
IEEE 802.1Q defined tag support
4096 VLANs
Egress tagging/untagging on a per-VLAN basis per port
QoS handling based on IEEE 802.1Q
Per-port priority remapping and 8 configurable egress queues per port
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
Ingress rate-limiting on a per-port and per-priority basis for Unicast/Multicast and
Broadcast traffic
Frame replication and retagging of traffic
Frame mirroring for enhanced diagnostics
Hardware support for IEEE 802.1AS and IEEE 802.1Qav for AVB traffic support
Ingress and egress timestamping per port
Ten IEEE 802.1Qav credit-based shapers available; shapers can be freely allocated to
any priority queue on a per port basis
Support for AVB SR Class A, Class B and Class C traffic
IEEE 1588v2 one-step sync forwarding in hardware
IEEE 802.1X support for setting port reachability and disabling address learning
Broadcast storm protection
Statistics for dropped frames and buffer load
2.3 TT and TSN features (SJA1105TEL only)
IEEE 802.1Qbv time-aware traffic
IEEE 802.1Qci per-stream policing (pre-standard)
Support for ring-based redundancy (for time-triggered traffic only)
1024 deterministic Ethernet flows with per-flow based:
Time-triggered traffic transmission
Ingress policing and reception window check
Active and redundant routes
Statistics
2.4 Interface features
MII/RMII interfaces supporting all standard Ethernet PHY technologies such as (but
not limited to) Fast Ethernet (IEEE 100BASE-TX), IEEE 100BASE-T1 and optical
PHYs
RGMII for interfacing with Gigabit Ethernet (1000BASE-T) PHYs (Gigabit Ethernet;
Ref. 4)
MAC and PHY modes for interfacing (MII/RMII/RGMII) directly with another switch or
host processor
Programmable drive strength for all interfaces
SPI at up to 25 MHz for host processor access
2.5 Other features
SJA1105
Product data sheet
25 MHz system clock input from crystal oscillator or AC-coupled single-ended clock
25 MHz reference clock output
Device reset input from host processor
IEEE 1149.1 compliant JTAG interface for TAP controller access and boundary scan
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Rev. 1 — 7 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
3. Ordering information
Table 1.
Ordering information
Type number
SJA1105EL
Package
Name
Description
Version
LFBGA159
plastic low profile fine-pitch ball grid array package; 159 balls
SOT1427-1
SJA1105TEL
4. Block diagram
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RMII interface connections
6.2.3 RGMII signaling and encoding
The PHY-MAC and MAC-MAC connections in an RGMII-configured interface are shown in
Figure 8. The RGMII protocol is intended to be an alternative to the IEEE 802.3z GMII
standard (not supported on the SJA1105). The objective is to reduce the number of pins
needed to connect the MAC and PHY in a cost-effective and technology-independent
way. RGMII has the added advantage over RMII in that it supports Gigabit operation.
In order to achieve a reduced pin count, the number of data signals and associated
control signals is reduced. Control signals are multiplexed together and transmitted data is
synchronized with both clock edges (double data rate).
RGMII is a symmetrical interface. For 1000 Mbit/s, 100 Mbit/s and 10 Mbit/s operation, the
clocks operate at 125 MHz, 25 MHz and 2.5 MHz (50 ppm) respectively. The TXC signal
is always generated by the MAC. The PHY generates the RXC. Note that RGMII requires
an external delay of between 1.5 ns and 2 ns on TXC and RXC.
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b. MAC-MAC interface
RGMII interface connections
SJA1105
Product data sheet
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Rev. 1 — 7 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
6.3 SPI interface
The SJA1105 provides an SPI bus slave as the host control interface. The host can
control/configure the SJA1105 by accessing the configuration address space and the
programming address space.
This interface acts as a slave in a synchronous serial data link that conforms with the SPI
standard as defined in the SPI Block Guide from Motorola (Ref. 7). The interface operates
in SPI Transfer mode 1 (CPOL = 0, CPHA = 1).
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SPI transfer timing (example)
An example SPI timing diagram is shown in Figure 9. Data is captured on the falling edge
of the clock and transmitted on the rising edge. Both master and slave must operate in the
same mode.
When CGU registers are read, a 64 ns delay must be inserted between the control and
data phases to allow the device to retrieve the data. Alternatively, the access can be
performed at a frequency below 17.8 MHz. In addition, a read-after-write time of >130 ns
between an SPI write and read transaction to the same register must be guaranteed. See
the SJA1105 software user manuals (Ref. 8) for further details on the data format.
The number of SPI clock cycles must be between 64 and 2080 and be a multiple of 32. In
order to ensure support for a wide a range of microcontrollers, the SPI interface can
operate at a supply voltage of 3.3 V, 2.5 V or 1.8 V (determined by the voltage connected
to VDDIO_HOST; see Section 11).
SJA1105
Product data sheet
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Rev. 1 — 7 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
7. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDDA(osc)
oscillator analog supply
voltage
on pin VDDA_OSC
0.5
+1.6
V
VDDA(PLL)
PLL analog supply voltage
on pin VDDA_PLL
0.5
+1.6
V
VDDC
core supply voltage
on pins VDD_CORE
0.5
+1.6
V
VDD(host)
host supply voltage
on pin VDDIO_HOST
0.5
+5
V
VDD(clk)
clock supply voltage
on pin VDDIO_CLO
0.5
+5
V
VDD(MII)
MII supply voltage
on pins VDDIO_MIIx
0.5
+5
V
2000
+2000
V
corner balls
750
+750
V
other balls
500
+500
V
VESD
electrostatic discharge voltage Human Body Model (HBM); 100 pF, 1.5 k
Charged Device Model (CDM)
[1]
[2]
Tj
junction temperature
40
+125
C
Tstg
storage temperature
55
+150
C
[1]
According to AEC-Q100-002.
[2]
According to AEC-Q100-011.
8. Thermal characteristics
Table 7.
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction to ambient
4-layer board (JESD51-9)
29
K/W
Rth(j-lead)
thermal resistance from junction to lead
4-layer board (JESD51-9)
15
K/W
j-top
thermal characterization parameter from junction to top 4-layer board (JESD51-9)
of package
0.33
K/W
SJA1105
Product data sheet
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SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
9. Static characteristics
Table 8.
Static characteristics
Tj = 40 C to +125 C; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into
the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
3.3 V signaling
3.00
3.30
3.60
V
2.5 V signaling
2.30
2.50
2.70
V
1.8 V signaling
1.65
1.80
1.95
V
3.3 V signaling
3.00
3.30
3.60
V
2.5 V signaling
2.30
2.50
2.70
V
1.8 V signaling
1.65
1.80
1.95
V
MII/RMII
3.00
3.30
3.60
V
RGMII
2.30
2.50
2.70
V
Supply voltages; see Figure 15
Clock and host interface supply (pins VDDIO_CLO and VDDIO_HOST)
VDD(clk)
VDD(host)
clock supply voltage
host supply voltage
MII interface supply (pins VDDIO_MII0 to VDDIO_MII4)
VDD(MII)
MII supply voltage
Core, oscillator and PLL supply (pins VDD_CORE, VDDA_OSC and VDDA_PLL)
VDDC
core supply voltage
1.14
1.20
1.30
V
VDDA(osc)
oscillator analog supply voltage
see Figure 15
1.10
1.20
1.30
V
VDDA(PLL)
PLL analog supply voltage
1.10
1.20
1.30
V
Supply currents
Clock and host interface supply (pins VDDIO_CLO and VDDIO_HOST)
IDD(host)
host supply current
VDD(HOST) = 3.30 V
-
-
2.8
mA
IDD(clk)
clock supply current
VVDD(CLK) = 3.30 V
-
-
3.5
mA
CL = 18 pF
-
-
65.5
mA
25 % load PRBS
-
14.3
-
mA
100 % load PRBS
-
31.8
-
mA
CL = 25 pF
-
-
15.5
mA
25 % load PRBS
-
6.8
-
mA
100 % load PRBS
-
8.5
-
mA
CL = 25 pF
-
-
11.5
mA
25 % load PRBS
-
0.7
-
mA
100 % load PRBS
-
2.4
-
mA
MII interface supply (pins VDDIO_MII0 to VDDIO_MII4)
IDD(MII)
MII supply current
port set to RGMII, 1 Gbit/s
port set to RMII, 100 Mbit/s
port set to MII, 100 Mbit/s
SJA1105
Product data sheet
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SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
Table 8.
Static characteristics …continued
Tj = 40 C to +125 C; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into
the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
-
110
mA
25 % PRBS
-
37.7
-
mA
100 % PRBS
-
54.3
-
mA
25 % PRBS
-
31.0
-
mA
100 % PRBS
-
33.2
-
mA
PLL0 enabled; see Ref. 8
-
-
1.2
mA
PLL0 and PLL1 enabled; see
Ref. 8
-
-
2.4
mA
-
350
-
A
0.2
1.0
2.5
mA
HIGH level
0.65
0.76
1.01
V
LOW level
0.60
0.72
0.91
V
0.1
VVDD(HOST)
-
V
3.3 V signaling
2.0
-
VVDD(HOST)
+ 0.5
V
2.5 V signaling
1.7
-
VVDD(HOST)
+ 0.5
V
1.8 V signaling
0.65
VVDD(HOST)
VVDD(HOST)
+ 0.5
V
3.3 V signaling
0.5
-
+0.8
V
2.5 V signaling
0.5
-
+0.7
V
1.8 V signaling
0.5
-
+0.35
VVDD(HOST)
V
Core, oscillator and PLL supply (pins VDD_CORE, VDDA_OSC and VDDA_PLL)
IDDC
core supply current
worst case
all ports set to RGMII,
1 Gbit/s
all ports set to MII/RMII, 100 Mbit/s
IDDA(PLL)
IDDA(osc)
PLL analog supply current
oscillator analog supply current
Istartup(osc) oscillator start-up current
Power-On Reset (POR)
Vtrip(POR)
pin
power-on reset trip voltage
RST_N[1]
Vhys(i)
input hysteresis voltage
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
Rpu(weak)
weak pull-up resistance
40
50
57
k
Ci
input capacitance
-
-
8.0
pF
-
-
3.5
pF
Oscillator (pins OSC_IN and OSC_OUT)
Crystal oscillator mode
Ci
input capacitance
Cshunt
shunt capacitance
CL(ext)
external load capacitance
on pin OSC_IN
-
-
7.0
pF
on pin OSC_IN
[2]
-
8
-
pF
on pin OSC_OUT
[2]
-
8
-
pF
-
100
-
pF
0.20
-
VDDA(OSC)
V
Clock mode
Cdec
decoupling capacitance
Vi(OSC_IN) input voltage on pin OSC_IN
SJA1105
Product data sheet
RMS value
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SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
Table 8.
Static characteristics …continued
Tj = 40 C to +125 C; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into
the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
3.3 V signaling (supported for
MII/RMII operation)
2.0
-
VDDx + 0.5[3] V
2.5 V signaling (supported for
RGMII operation)
1.7
-
VDDx[3] + 0.5 V
1.8 V signaling (not supported
for MII, RMII or RGMII)
0.65
VDDx[3]
-
VDDx[3] + 0.5 V
3.3 V signaling
0.5
-
+0.8
V
2.5 V signaling
0.5
-
+0.7
V
1.8 V signaling
0.5
-
+0.35
VDDx[3]
V
0.1
VDDx[3]
-
-
V
I/O pins (VDDIO_MII0 to VDDIO_MII4, SPI, JTAG, CLK_OUT, PTP_CLK)
HIGH-level input voltage
VIH
LOW-level input voltage
VIL
Vhys(i)
input hysteresis voltage
Rpu(weak)
weak pull-up resistance
VIO = 0 V
40.0
50.0
57.0
k
Rpd(weak)
weak pull-down resistance
VIO = VDDx
40.0
50.0
57.0
k
IOSH
HIGH-level short-circuit output
current
-
-
111.7
mA
IOSL
LOW-level short-circuit output
current
-
-
110.2
mA
Ci
input capacitance
-
-
5.0
pF
Zo
output impedance
40.0
-
67.5
[1]
Pins RST_N and TRST_N must be held LOW simultaneously to reset the device.
[2]
Value is crystal dependent.
[3]
Supply voltage on I/O pin x.
SJA1105
Product data sheet
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Rev. 1 — 7 November 2016
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SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
10. Dynamic characteristics
Table 9.
Dynamic characteristics
Tj = 40 C to +125 C; capacitive load of 4 pF; all voltages are defined with respect to ground unless otherwise specified;
positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
high-speed mode
0.3
-
0.8
ns
fast-speed mode
0.5
-
1.3
ns
medium-speed mode
0.8
-
2.0
ns
low-speed mode
1.4
-
2.7
ns
high-speed mode
0.4
-
1.1
ns
fast-speed mode
0.6
-
1.7
ns
medium-speed mode
1.1
-
2.4
ns
low-speed mode
1.8
-
3.1
ns
I/O pins (VDDIO_MII0 to VDDIO_MII4, SPI, JTAG, CLK_OUT, PTP_CLK)
tr(o)
output rise time
3.3 V signaling
2.5 V signaling
1.8 V signaling
tf(o)
output fall time
high-speed mode
0.5
-
1.9
ns
fast-speed mode
0.9
-
2.5
ns
medium-speed mode
1.5
-
3.2
ns
low-speed mode
2.3
-
4.1
ns
high-speed mode
0.6
-
0.8
ns
fast-speed mode
0.6
-
1.0
ns
medium-speed mode
0.6
-
1.8
ns
low-speed mode
1.2
-
2.7
ns
high-speed mode
0.5
-
0.9
ns
fast-speed mode
0.5
-
1.4
ns
medium-speed mode
1.0
-
2.3
ns
low-speed mode
1.6
-
3.0
ns
high-speed mode
0.5
-
1.6
ns
fast-speed mode
0.7
-
2.3
ns
medium-speed mode
1.4
-
3.0
ns
low-speed mode
2.0
-
3.9
ns
-
25
-
MHz
-
275
800
s
45
50
55
%
3.3 V signaling
2.5 V signaling
1.8 V signaling
Oscillator (pins OSC_IN and OSC_OUT)
Crystal oscillator mode[1]
fxtal
crystal frequency
tstartup
start-up time
duty cycle
SJA1105
Product data sheet
25 MHz crystal;
COSC_IN = COSC_OUT = 8 pF
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SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
Table 9.
Dynamic characteristics …continued
Tj = 40 C to +125 C; capacitive load of 4 pF; all voltages are defined with respect to ground unless otherwise specified;
positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Ncy(clk)startup
number of start-up clock cycles
until clock is stable;
25 MHz crystal;
COSC_IN = COSC_OUT = 8 pF
-
1000
-
-
-
25
-
MHz
-
10
-
-
pulse width
5.0
-
-
s
fclk
clock frequency
-
25
-
MHz
duty cycle
40
50
60
%
fclk
clock frequency
-
100
-
kHz
duty cycle
-
50
-
%
0.1
-
25
MHz
45
50
55
%
Clock mode
fclk(i)
input clock frequency
Ncy(clk)startup
number of start-up clock cycles
until clock is stable
pin RST_N
tw
pin CLK_OUT
pin PTP_CLK
SPI: pins SS_N, SCK, SDI and SDO
[2]
fclk
clock frequency
duty cycle
tsu(D)
data input set-up time
w.r.t. SCK sampling edge
12.4
-
-
ns
th(D)
data input hold time
w.r.t. SCK sampling edge
18
-
-
ns
td(clk-data)
clock to data delay time
w.r.t. SCK launching edge;
high-speed mode; 25 pF load
0
-
14
ns
td(W-R)
write to read delay time
130
-
-
ns
td(addr-data)
address to data delay time
64
-
-
ns
0.1
-
16
MHz
40
50
JTAG: pins TRST_N, TDI, TCK, TMS and TDO
fclk
clock frequency
duty cycle
60
%
tw
pulse width
on pin TRST_N
100.0 -
-
ns
tsu(D)
data input set-up time
w.r.t. TCK sampling edge
4.0
-
-
ns
th(D)
data input hold time
w.r.t. TCK sampling edge
25
-
-
ns
td(clk-data)
clock to data delay time
w.r.t. TCK launching edge;
high-speed mode; 25 pF load
-
-
20.0
ns
xMII ports
port configured by host for MII MAC mode; pad speed selection: medium noise, fast speed
fclk
clock frequency
transmit (TX_CLK) and receive
(RX_CLK) clocks; 100 Mbit/s
operating speed
-
25
-
MHz
duty cycle
of transmit and receive clocks
35
50
65
%
tsu(D)
data input set-up time
on pins RXDx, RX_DV and RX_ER
w.r.t. rising edge on RX_CLK
10
-
-
ns
th(D)
data input hold time
on pins RXDx, RX_DV and RX_ER
w.r.t. rising edge on RX_CLK
10
-
-
ns
SJA1105
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
Table 9.
Dynamic characteristics …continued
Tj = 40 C to +125 C; capacitive load of 4 pF; all voltages are defined with respect to ground unless otherwise specified;
positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
td(clk-data)
clock to data delay time
on pins TXDx, TX_EN and TX_ER
w.r.t. rising edge on TX_CLK
0
-
25
ns
port configured by host for MII PHY mode; pad speed selection: medium noise, fast speed
tsu(D)
data input set-up time
on pins RXDx, RX_DV and RX_ER
w.r.t. rising edge on RX_CLK
10
-
-
ns
th(D)
data input hold time
on pins RXDx, RX_DV and RX_ER
w.r.t. rising edge on RX_CLK
0
-
-
ns
td(clk-data)
clock to data delay time
on pins TXDx, TX_EN and TX_ER
w.r.t. rising edge on TX_CLK
12
-
25
ns
port configured by host for RMII mode; pad speed selection: medium noise, fast speed
fclk
clock frequency
reference clock (REF_CLK);
100 Mbit/s operating speed
-
50
-
MHz
duty cycle
of reference clock
35
50
65
%
tsu(D)
data input set-up time
on pins RXDx, CRS_DV and
RX_ER w.r.t. rising edge on
REF_CLK
4
-
-
ns
th(D)
data input hold time
on pins RXDx, CRS_DV and
RX_ER w.r.t. rising edge on
REF_CLK
0
-
-
ns
td(clk-data)
clock to data delay time
on pins RXDx, CRS_DV and
RX_ER w.r.t. rising edge on
REF_CLK; fast speed I/O setting
2
-
10
ns
1 Gbit/s operating speed
-
125
-
MHz
100 Mbit/s operating speed
-
25
-
MHz
10 Mbit/s operating speed
-
2.5
-
MHz
port configured by host for RGMII mode; pad speed selection: high noise, high speed
fclk
clock frequency
duty cycle
tsk(o)
output skew time
input skew time
tsk(I)
transmit (TXC) and receive (RXC)
clocks
of transmit and receive clocks
1 Gbit/s operating speed
45
50
55
%
100/10 Mbit/s operating speed
40
50
60
%
0.5
-
+0.5
ns
1.0
-
2.6
ns
at the transmitter w.r.t. edge on TXC
at the receiver w.r.t. edge on RXC
[3]
[1]
A 100 ppm crystal is needed for MII and a 50 ppm crystal for RMII/RGMII.
[2]
CGU configuration register read-access timing is stricter at 25 MHz (max); see Section 6.3.
[3]
Implies that PCB board design requires the clock to be routed such that an additional trace delay of more than 1.5 ns and less than
2.0 ns is added to the associated clock signal or an external delay line is used.
SJA1105
Product data sheet
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SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
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Fig 11. RMII timing diagram
SJA1105
Product data sheet
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SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
7;& DWWUDQVPLWWHU
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Fig 12. RGMII timing diagram
SJA1105
Product data sheet
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5-port automotive Ethernet switch
11. Application information
The SJA1105 features a programmable traffic interface. Each of the five ports can be
individually configured for 10 Mbit/s or 100 Mbit/s MII/RMII/RGMII, or for 1 Gbit/s RGMII
operation. A typical use case is illustrated in Figure 13.
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Fig 13. Typical SJA1105 application circuit
In this configuration, four TJA1100 BroadR-Reach PHYs are connected to the SJA1105
for MII/RMII operation while a host processor has RGMII connectivity with the SJA1105.
The I/O supply voltage needed at a port depends on the selected configuration: 3.3 V for
MII/RMII operation and 2.5 V for RGMII operation.
SJA1105
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SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
Port 1 to Port 4 are configured for MII/RMII operation, so a 3.3 V supply is connected to
pins VDDIO_MII1 to VDDIO_MII4. A 2.5 V supply is connected to VDDIO_MII1 since it is
configured for RGMII operation.
The SPI, JTAG and PTP_CLK interfaces are supplied via VDDIO_HOST. The 25 MHz
clock output, CLK_OUT, is supplied from VDDIO_CLO. Both VDDIO_HOST and
VDDIO_CLO accept a 1.8 V, 2.5 V or 3.3 V supply.
SJA1105 devices can be cascaded, as illustrated in Figure 14. Note that Ethernet
connectivity to the host processor is only needed if the system has to support AVB
operation or other bridge management protocols such as STP/RSTP. If such operations
are not needed, all the ports can be used for data traffic.
In Crystal oscillator mode, the SJA1105 oscillator is used as a crystal oscillator with an
external 25 MHz crystal and, typically, a 2 8 pF load. In Clock mode, the SJA1105
oscillator is used as a clock input with an external clock connected to input terminal
OSC_IN with OSC_OUT left open.
SJA1105
Product data sheet
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Rev. 1 — 7 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
25 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
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(1) RGMII requires an external delay of between 1.5 ns and 2 ns on TXC and RXC.
Fig 14. Cascading SJA1105 devices
SJA1105
Product data sheet
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Rev. 1 — 7 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
26 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
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PCB layout guidelines showing capacitor placement can be found in AH1604 ‘SJA1105 Hardware Design Application Hints’
Fig 15. Power supply filtering
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Fig 16. Device clocking
11.1 Application hints
Further information on the application of the SJA1105 can be found in NXP application
hints AH1402 ‘Application Hints - 5-port Ethernet Switch’, AH1601 ‘Device Configuration
Application Hints‘, and AH1604 ‘SJA1105 Hardware Design Application Hints’.
SJA1105
Product data sheet
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Rev. 1 — 7 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
27 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
12. Test information
12.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-H - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.
SJA1105
Product data sheet
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Rev. 1 — 7 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
28 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
13. Package outline
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Fig 17. Package outline SOT1427-1 (LFBGA159)
SJA1105
Product data sheet
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5-port automotive Ethernet switch
14. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
15. Abbreviations
Table 10.
SJA1105
Product data sheet
Abbreviations
Abbreviation
Description
AVB
Audio Video Bridging
CMC
Common Mode Choke
CRC
Cyclic Redundancy Check
ECU
Electronic Control Unit
Gbit
Gigabit
IFG
InterFrame Gap
JTAG
Joint Test Action Group
LAN
Local Area Network
MAC
Medium Access Controller
Mbit
Megabit
MII
Media Independent Interface
NMOS
N-channel Metal-Oxide Silicon
OTP
One-Time Programmable
PHY
Physical Layer (of the interface)
PLL
Phase-Locked Loop
PMOS
P-channel Metal-Oxide Silicon
PRBS
Pseudo Random Binary Sequence
PTP
Precision Time Protocol
QoS
Quality of Service
RGMII
Reduced Gigabit Media Independent Interface
RMII
Reduced Media Independent Interface
RSTP
Rapid Spanning Tree Protocol
SMI
Serial Management Interface
SOF
Start Of Frame
SPI
Serial Peripheral Interface
SR
Stream Reservation (class)
STP
Spanning Tree Protocol
TAP
Test Access Port
TSN
Time-Sensitive Networking
TTEthernet
Time-Triggered Ethernet
UTP
Unshielded Twisted Pair
VL
Virtual Link
VLAN
Virtual LAN
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Rev. 1 — 7 November 2016
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NXP Semiconductors
5-port automotive Ethernet switch
16. References
[1]
OPEN Alliance BroadR-Reach Physical Layer Transceiver Specification for
Automotive Applications, V3.2, 24 June 2014
[2]
TJA1100 OPEN Alliance BroadR-Reach PHY for Automotive Ethernet data sheet
available from NXP Semiconductors
[3]
IEEE 802.1BA - Audio Video Bridging (AVB) Systems
[4]
Reduced Gigabit Media Independent Interface (RGMII), V1.3, 12 October
2000, V1.3, Broadcom Corporation, Hewlett Packard, Marvell
[5]
IEEE Std. 802.3
[6]
Reduced Media Independent Interface (RMII), March 20, 1998, RMII Consortium
Copyright AMD Inc., Broadcom Corp., National Semiconductor Corp., and Texas
Instruments Inc., 1997
[7]
SPI Block Guide, V03.06, 04 February 2003, Motorola Inc.
[8]
UM10851 SJA1105EL and UM10944 SJA1105TEL software user manuals available
from NXP Semiconductors
17. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
SJA1105 v.1.1
20161107
Product data sheet
-
-
SJA1105
Product data sheet
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5-port automotive Ethernet switch
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
SJA1105
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Product data sheet
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33 of 34
SJA1105
NXP Semiconductors
5-port automotive Ethernet switch
20. Contents
1
2
2.1
2.2
2.3
2.4
2.5
3
4
5
5.1
5.2
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
6.1.12
6.1.13
6.1.14
6.1.15
6.1.16
6.1.17
6.1.18
6.1.19
6.1.20
6.1.21
6.2
6.2.1
6.2.2
6.2.3
6.3
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
General features . . . . . . . . . . . . . . . . . . . . . . . . 1
Ethernet switching and AVB features . . . . . . . . 1
TT and TSN features (SJA1105TEL only) . . . . 2
Interface features . . . . . . . . . . . . . . . . . . . . . . . 2
Other features. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 8
Functional overview . . . . . . . . . . . . . . . . . . . . . 8
Auxiliary Configuration Unit (ACU) . . . . . . . . . . 8
Clock Generation Unit (CGU) . . . . . . . . . . . . . . 8
Reset Generation Unit (RGU). . . . . . . . . . . . . . 8
Serial Peripheral Interface (SPI) . . . . . . . . . . . . 9
Status and Control Unit (SCU) . . . . . . . . . . . . . 9
Configuration Stream Decoder/Configuration
Controller (CSD/CC) . . . . . . . . . . . . . . . . . . . . . 9
xMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Dynamic Memory Management (DMM)/Frame
Memory Controller (FMC)/ Frame Buffer
Management (FBM) . . . . . . . . . . . . . . . . . . . . . 9
Receive MAC (RXM) . . . . . . . . . . . . . . . . . . . . 9
Input Queue (IQ). . . . . . . . . . . . . . . . . . . . . . . . 9
VLAN Lookup (VLAN_LU) . . . . . . . . . . . . . . . . 9
Address Lookup (L2ADDR_LU) . . . . . . . . . . . . 9
Policing (L2_POLICE) . . . . . . . . . . . . . . . . . . 10
Forwarding (L2_FORW) . . . . . . . . . . . . . . . . . 10
Transmit MAC (TXM) . . . . . . . . . . . . . . . . . . . 10
Audio Video Bridging (AVB) . . . . . . . . . . . . . . 10
Loopback Port (LBP) . . . . . . . . . . . . . . . . . . . 10
Virtual Link Lookup (VL_LU);
SJA1105TEL only . . . . . . . . . . . . . . . . . . . . . . 10
Virtual Link Policing (VL_POLICE);
SJA1105TEL only . . . . . . . . . . . . . . . . . . . . . . 10
Virtual Link Forwarding (VL_FORW);
SJA1105TEL only . . . . . . . . . . . . . . . . . . . . . . 11
Clock Synchronization Subsystem (CSS) and
Schedule Engine (SCH); SJA1105TEL only . . 11
Media Independent Interfaces (xMII) . . . . . . . 11
MII signaling and encoding . . . . . . . . . . . . . . . 12
RMII signaling and encoding . . . . . . . . . . . . . 12
RGMII signaling and encoding . . . . . . . . . . . . 13
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
8
9
10
11
11.1
12
12.1
13
14
15
16
17
18
18.1
18.2
18.3
18.4
19
20
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Thermal characteristics . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Application hints . . . . . . . . . . . . . . . . . . . . . . .
Test information . . . . . . . . . . . . . . . . . . . . . . .
Quality information . . . . . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
16
19
24
27
28
28
29
30
30
31
31
32
32
32
32
33
33
34
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 November 2016
Document identifier: SJA1105
工商网监
湘ICP备2023018690号
