SL3S1204
UCODE 7
Rev. 4.0 — 5 March 2019
241340
1
Product data sheet
COMPANY PUBLIC
General description
NXP’s UCODE 7 IC is the leading-edge EPC Gen2 RFID chip that offers best-in-class
performance and features for use in the most demanding RFID tagging applications.
Particularly well suited for inventory management application, like e.g Retail and Fashion,
with its leading edge RF performance for any given form factor, UCODE 7 enables
long read distance and fast inventory of dense RFID tag population. With its broadband
design, it offers the possibility to manufacture true global RFID label with best-in-class
performance over worldwide regulations.
The device also provides a pre-serialized 96-bit EPC and a Parallel encoding feature. For
applications where the same 58-bit Stock Keeping Unit (SKU) needs to be encoded on
multiple tags, at the same time, a combination of both features improves and simplifies
the tag initialization process.
On top UCODE 7 offers a Tag Power Indicator for RFID tag initialization optimization and
a Product Status Flag for Electronic Article Surveillance (EAS) application.
SL3S1204
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UCODE 7
2
Features and benefits
2.1 Key features
•
•
•
•
•
•
•
•
•
Read sensitivity -21 dBm
Write sensitivity -16 dBm
Parallel encoding mode: 100 items in 60ms
Encoding speed: 16 bits per millisecond
Innovative functionalities
– Tag Power Indicator
– Pre-serialization for 96-bit EPC
– Integrated Product Status Flag (PSF)
Compatible with single-slit antenna
Up to 128-bit EPC
96-bit Unique Tag Identifier (TID) factory locked,
including 48-bit unique serial number
EPC Gen2 v2.0 ready
2.1.1 Memory
•
•
•
•
•
•
•
•
•
Up to 128-bit of EPC memory
Supports pre-serialization for 96-bit EPC
96-bit Tag IDentifier (TID) factory locked
48-bit unique serial number factory-encoded into TID
No User Memory
32-bit kill password to permanently disable the tag
32-bit access password
Wide operating temperature range: -40 °C up to +85 °C
Minimum 100.000 write cycle endurance
2.2 Key benefits
2.2.1 End user benefit
• Long READ and WRITE ranges due to leading edge chip sensitivity
• Very fast bulk encoding
• Product identification through unalterable extended TID range, including a 48-bit serial
number
• Reliable operation in dense reader and noisy environments through high interference
rejection
2.2.2 Antenna design benefits
• High sensitivity enables smaller and cost efficient antenna designs for the same retail
category
• Tag Power Indicator features enables very high density of inlay on rolls without crosstalk issues during writing/encoding
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UCODE 7
• The different input capacitance for the single slit antenna solution provides an
additional possibility in tuning of the impedance for the antenna design
2.2.3 Label manufacturer benefit
•
•
•
•
•
Large RF pad-to-pad distance to ease antenna design
Symmetric RF inputs are less sensitive to process variation
Single slit antenna for a more mechanically stable antenna connection
Pre-serialization of the 96-bit EPC
Extremely fast encoding of the EPC content
2.3 Supported features
• All mandatory commands of EPC global specification V.1.2.0 are implemented
including:
– (Perma)LOCK
– Kill Command
• The following optional commands are implemented in conformance with the EPC
specification:
– Access
– BlockWrite (2 words, 32-bit)
• Product Status Flag bit: enables the UHF RFID tag to be used as EAS
(Electronic Article Surveillance) tag without the need for a back-end data base.
• Tag Power Indicator: enables the reader to select only ICs/tags that have enough
power to be written to.
• Parallel encoding: allows for the ability to bring (multiple) tag(s) quickly to the OPEN
state and hence allowing single tags to be identified simply, without timing restrictions,
or multiple tags to be e.g. written to at the same time, considerably reducing the
encoding process
All supported features of UCODE 7 can be activated using standard EPCglobal READ /
WRITE / ACCESS / SELECT commands. No custom commands are needed to take
advantage of all the features in case of unlocked EPC memory. The parallel encoding
feature may however require a firmware upgrade of the reader to use its full potential.
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UCODE 7
3
Applications
3.1 Markets
• Retail/Fashion (apparel, footwear, jewelry, cosmetics)
• Fast Moving Consumer Goods
3.2 Applications
•
•
•
•
Retail Inventory management
Supply chain management
Loss prevention
Asset management
Outside the applications mentioned above, please contact NXP Semiconductors for
support.
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UCODE 7
4
Ordering information
Table 1. Ordering information
Type number
Package
Name
IC type
Description
SL3S1204FUD/BG1
Wafer
UCODE 7
bumped die on sawn 8" 120 μm wafer 7 μm Polyimide not applicable
spacer
SL3S1204FUD/HA1
Wafer
UCODE 7
die with large pads 3 μm Au, 10 μm Polyimide spacer
on sawn 8" 120 μm wafer
not applicable
SL3S1204FUD2/BG1
Wafer
UCODE 7
bumped die on sawn 12" 120 μm wafer 7 μm
Polyimide spacer
not applicable
SL3S1204FTB0/1
XSON6
UCODE 7
plastic extremely thin small outline package; no leads; SOT886F1
6 terminals; body 1 × 1.45 × 0.5 mm
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UCODE 7
5
Marking
Table 2. Marking codes
SL3S1204
Product data sheet
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Type number
Marking code
Comment
Version
SL3S1204FTB0/1
YM
UCODE 7
SOT886
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UCODE 7
6
Block diagram
The SL3S1204 IC consists of three major blocks:
• Analog Interface
• Digital Control
• EEPROM
The analog part provides stable supply voltage and demodulates data received from the
reader which is then processed by the digital part. Further, the modulation transistor of
the analog part transmits data back to the reader.
The digital section includes the state machines, processes the protocol and handles
communication with the EEPROM, which contains the EPC and the user data.
ANALOG
RF INTERFACE
RF1
RECT
DIGITAL CONTROL
VREG
VDD
DEMOD
data
in
antenna
EEPROM
ANTICOLLISION
READWRITE
CONTROL
MEMORY
ACCESS CONTROL
RF2
MOD
data
out
EEPROM INTERFACE
CONTROL
RF INTERFACE
CONTROL
R/W
SEQUENCER
CHARGE PUMP
aaa-005856
Figure 1. Block diagram of UCODE 7 IC
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UCODE 7
7
Pinning information
TP1
SL3S1204 trademark
RF2
SL3S12x4FTB0
TP2
RF1
RF2
1
6
RF1
n.c.
2
5
n.c.
n.c.
3
4
n.c.
aaa-018831
Transparent top view
aaa-005611
Figure 2. Pinning bare die
Figure 3. Pin configuration for SOT886
7.1 Pin description
Table 3. Pin description bare die
Symbol
Description
TP1
test pad 1
RF1
antenna connector 1
TP2
test pad 2
RF2
antenna connector 2
Table 4. Pin description SOT886
SL3S1204
Product data sheet
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Pin
Symbol
Description
1
RF2
antenna connector
2
n.c.
not connected
3
n.c.
not connected
4
n.c.
not connected
5
n.c.
not connected
6
RF1
antenna connector
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UCODE 7
8
Wafer layout
8.1 Wafer layout 8 inch
(1)
TP1
RF2
(5)
Y
(6)
(4)
X
(7)
TP2
RF1
(8)
(2)
(3)
not to scale!
1.
2.
3.
4.
5.
6.
7.
8.
aaa-005606
Die to Die distance (metal sealring - metal sealring) 21,4 μm, (X-scribe line width: 15 μm)
Die to Die distance (metal sealring - metal sealring) 21,4 μm, (Y-scribe line width: 15 μm)
Chip step, x-length: 460 μm
Chip step, y-length: 505 μm
Bump to bump distance X (TP1 - RF2): 358 μm
Bump to bump distance Y (RF1 - RF2): 403 μm
Distance bump to metal sealring X: 40,3 μm (outer edge - top metal)
Distance bump to metal sealring Y: 40,3 μm
Bump size X x Y: 60 μm x 60 μm
Remark: TP1 and TP2 are electrically disconnected after dicing
Figure 4. UCODE 7 8 inch wafer layout
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UCODE 7
8.2 Wafer layout 8 inch with large pads
(2)
(1)
TP1
RF2
(4)
(5)
(13)
(12)
(11)
TP2
RF1
(10)
Y
(6)
X
(8)
(7)
(9)
(3)
not to scale!
aaa-026778
1. Die to Die distance (metal sealring - metal sealring) 21,4 μm, (Y-scribe line width: 15 μm)
2. Die to Die distance (metal sealring - metal sealring) 21,4 μm, (X-scribe line width: 15 μm)
3. Chip step, x-length: 460 μm
4. Chip step, y-length: 505 μm
5. Bump to bump distance Y (RF1 - RF2): 115 μm
6. Distance bump to metal sealring X: 23,5 μm
7. Bump size (TP1, TP2) X: 130 μm
8. Bump to bump distance X (RF1 - TP2): 50 μm
9. Bump size (RF1, RF2) X: 218 μm
10. Distance bump to metal sealring Y: 23,5 μm
11. Bump size (TP1, TP2) Y: 153,1 μm
12. Bump size (RF1, RF2) Y: 164 μm
13. Distance bump to metal sealring Y: 466,5 μm
Remark: TP1 and TP2 are electrically disconnected after dicing
Figure 5. UCODE 7 8 inch wafer layout with large pads
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UCODE 7
8.3 Wafer layout 12 inch
(1)
TP1
RF2
(5)
Y
(6)
(4)
X
(7)
TP2
RF1
(8)
(2)
(3)
not to scale!
1.
2.
3.
4.
5.
6.
7.
8.
aaa-005606
Die to Die distance (metal sealring - metal sealring) 39 μm, (X-scribe line width: 35 μm)
Die to Die distance (metal sealring - metal sealring) 39 μm, (Y-scribe line width: 35 μm)
Chip step, x-length: 480 μm
Chip step, y-length: 525μm
Bump to bump distance X (TP1 - RF2): 358 μm
Bump to bump distance Y (RF1 - RF2): 403 μm
Distance bump to metal sealring X: 40,3 μm (outer edge - top metal)
Distance bump to metal sealring Y: 40,3 μm
Bump size X x Y: 60 μm x 60 μm
Remark: TP1 and TP2 are electrically disconnected after dicing
Figure 6. UCODE 7 12 inch wafer layout
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UCODE 7
9
Mechanical specification
The UCODE 7 wafers are available in 120 μm thickness. The 120 μm thick wafer is
enhanced with 7μm /10μm Polyimide spacer resulting in less coupling between the
antenna and the active circuit, leaving more room for process control (like pressure).
9.1 Wafer specification
9.1.1 8 inch Wafer, Standard bumps
See [2].
Table 5. Specifications
Wafer
Designation
each wafer is scribed with batch number and
wafer number
Diameter
200 mm (8") unsawn - 205 mm typical sawn
on foil
Thickness
SL3S1204FUD/BG
120 μm ± 15 μm
Number of pads
4
Pad location
non diagonal / placed in chip corners
Distance pad to pad RF1-RF2
403.0 μm
Distance pad to pad TP1-RF2
358.0 μm
Process
CMOS 0.14 μm
Batch size
25 wafers
Potential good dies per wafer
126.524
Wafer backside
Material
Si
Treatment
ground and stress release
Roughness
Ra max. 0.5 μm, Rt max. 5 μm
Chip dimensions
2
Die size excluding scribe
0.490 mm × 0.445 mm = 0.218 mm
Scribe line width:
x-dimension = 15 μm
y-dimension = 15 μm
Passivation on front
Type
Sandwich structure
Material
PE-Nitride (on top)
Thickness
1.75 μm total thickness of passivation
Polyimide spacer
7 μm ± 1 μm
Au bump
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UCODE 7
Bump material
> 99.9 % pure Au
Bump hardness
35 – 80 HV 0.005
Bump shear strength
> 70 MPa
Bump height
[1]
SL3S1204FUD/BG
25 μm
Bump height uniformity
within a die
± 2 μm
– within a wafer
± 3 μm
– wafer to wafer
± 4 μm
Bump flatness
± 1.5 μm
Bump size
– RF1, RF2
60 × 60 μm
– TP1, TP2
60 × 60 μm
Bump size variation
± 5 μm
[1]
Because of the 7 μm spacer, the bump will measure 18 μm relative height protruding the spacer.
9.1.2 8 inch Wafer, Large pads
See [2].
Table 6. Specifications
Wafer
Designation
each wafer is scribed with batch number and
wafer number
Diameter
200 mm (8") unsawn - 205 mm typical sawn
on foil
Thickness
SL3S1204FUD/HA
120 μm ± 15 μm
Number of pads
4
Pad location
non diagonal / placed in chip corners
Process
CMOS 0.14 μm
Batch size
25 wafers
Potential good dies per wafer
126.524
Wafer backside
Material
Si
Treatment
ground and stress release
Roughness
Ra max. 0.5 μm, Rt max. 5 μm
Chip dimensions
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2
Die size excluding scribe
0.490 mm × 0.445 mm = 0.218 mm
Scribe line width:
x-dimension = 15 μm
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UCODE 7
y-dimension = 15 μm
Passivation on front
Type
Sandwich structure
Material
PE-Nitride (on top)
Thickness
1.75 μm total thickness of passivation
Polyimide spacer
10 μm ± 2 μm
Au Pad
Pad material
> 99.9 % pure Au
Pad hardness
35 – 80 HV 0.005
Pad shear strength
> 70 MPa
Pad height
SL3S1204FUD/HA
3 μm
Pad height uniformity
within a die
max. 2 μm
– within a wafer
max. 4 μm
Pad flatness
max. 3 μm
Pad size
– RF1, RF2 (max. details see wafer layout)
218 × 164 μm
– TP1, TP2 (max. details see wafer layout)
130 × 153.1 μm
Pad size variation
± 5 μm
9.1.3 12 inch Wafer
See [4]
Table 7. Specifications
Wafer
Designation
each wafer is scribed with batch number and
wafer number
Diameter
300 mm (12") unsawn and sawn on foil
Thickness
SL3S1204FUD2
120 μm ± 15 μm
Number of pads
4
Pad location
non diagonal / placed in chip corners
Distance pad to pad RF1-RF2
403.0 μm
Distance pad to pad TP1-RF2
358.0 μm
Process
CMOS 0.14 μm
Batch size
25 wafers
Potential good dies per wafer
264.696
Wafer backside
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UCODE 7
Material
Si
Treatment
ground and stress release
Roughness
Ra max. 0.5 μm, Rt max. 5 μm
Chip dimensions
2
Die size excluding scribe
0.490 mm × 0.445 mm = 0.218 mm
Scribe line width:
x-dimension = 35 μm
y-dimension = 35 μm
Passivation on front
Type
Sandwich structure
Material
PE-Nitride (on top)
Thickness
1.75 μm total thickness of passivation
Polyimide spacer
7 μm ± 1 μm
Au bump
Bump material
> 99.9 % pure Au
Bump hardness
35 – 80 HV 0.005
Bump shear strength
> 70 MPa
Bump height
[1]
SL3S1204FUD2
25 μm
Bump height uniformity
within a die
± 2 μm
– within a wafer
± 3 μm
– wafer to wafer
± 4 μm
Bump flatness
± 1.5 μm
Bump size
– RF1, RF2
60 × 60 μm
– TP1, TP2
60 × 60 μm
Bump size variation
± 5 μm
[1]
Because of the 7 μm spacer, the bump will measure 18 μm relative height protruding the spacer.
9.1.4 Fail die identification
No inkdots are applied to the wafer.
Electronic wafer mapping (SECS II format) covers the electrical test results and
additionally the results of mechanical/visual inspection.
See [2]
See [4]
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UCODE 7
9.1.5 Map file distribution
See [2]
See [4]
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UCODE 7
10 Functional description
10.1 Air interface standards
The UCODE 7 fully supports all parts of the "Specification for RFID Air Interface
EPCglobal, EPC Radio-Frequency Identity Protocols, Class-1 Generation-2 UHF RFID,
Protocol for Communications at 860 MHz to 960 MHz, Version 1.2.0".
10.2 Power transfer
The interrogator provides an RF field that powers the tag, equipped with a UCODE 7.
The antenna transforms the impedance of free space to the chip input impedance in
order to get the maximum possible power for the UCODE 7 on the tag.
The RF field, which is oscillating on the operating frequency provided by the interrogator,
is rectified to provide a smoothed DC voltage to the analog and digital modules of the IC.
The antenna that is attached to the chip may use a DC connection between the two
antenna pads. Therefore the UCODE 7 also enables loop antenna design.
10.3 Data transfer
10.3.1 Interrogator to tag Link
An interrogator transmits information to the UCODE 7 by modulating an UHF RF signal.
The UCODE 7 receives both information and operating energy from this RF signal. Tags
are passive, meaning that they receive all of their operating energy from the interrogator's
RF waveform.
An interrogator is using a fixed modulation and data rate for the duration of at least one
inventory round. It communicates to the UCODE 7 by modulating an RF carrier.
For further details refer to [1]. Interrogator-to-tag (R=>T) communications.
10.3.2 Tag to interrogator Link
Upon transmitting a valid command an interrogator receives information from a UCODE
7 tag by transmitting an unmodulated RF carrier and listening for a backscattered reply.
The UCODE 7 backscatters by switching the reflection coefficient of its antenna between
two states in accordance with the data being sent. For further details refer to [1], chapter
6.3.1.3.
The UCODE 7 communicates information by backscatter-modulating the amplitude
and/or phase of the RF carrier. Interrogators shall be capable of demodulating either
demodulation type.
The encoding format, selected in response to interrogator commands, is either FM0
baseband or Miller-modulated subcarrier.
10.4 Supported commands
The UCODE 7 supports all mandatory EPCglobal V1.2.0 commands including
• Kill command
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UCODE 7
• (perma) LOCK command
In addition the UCODE7 supports the following optional commands:
• ACCESS
• Block Write (32 bit)
10.5 UCODE 7 memory
The UCODE 7 memory is implemented according EPCglobal
Class1Gen2 and organized in three banks:
Table 8. UCODE 7 memory sections
Name
Size
Bank
Reserved memory (32 bit ACCESS and 32 bit KILL password)
64 bit
00b
EPC (excluding 16 bit CRC-16 and 16 bit PC)
128 bit
01b
UCODE 7 Configuration Word
16 bit
01b
TID (including permalocked unique 48 bit serial number)
96 bit
10b
The logical address of all memory banks begin at zero (00h).
In addition to the three memory banks one configuration word to handle the UCODE 7
specific features is available at EPC bank 01 address bit-200h. The configuration word is
described in detail in 9.6.
The TID complies to the extended tag Identification scheme according GS1 EPC Tag
Data Standard 1.6.
10.5.1 UCODE 7 overall memory map
Table 9. UCODE 7 overall memory map
Bank
address
Memory
address
Type
Content
Initial
Remark
Bank 00
00h to 1Fh
reserved
kill password
all 00h
unlocked memory
20h to 3Fh
reserved
access password
all 00h
unlocked memory
00h to 0Fh
EPC
CRC-16: refer to [1]
10h to 14h
EPC
EPC length
00110b
unlocked memory
15h
EPC
UMI
0b
unlocked memory
16h
EPC
XPC indicator
0b
hardwired to 0
17h to 1Fh
EPC
numbering system indicator
00h
unlocked memory
unlocked memory
Bank 01
EPC
Bank 01
Config Word
memory mapped
calculated CRC
20h to 9Fh
EPC
EPC
[1]
200h
EPC
RFU
0b
locked memory
201h
EPC
RFU
0b
locked memory
202h
EPC
Parallel encoding
0b
Action bit
203h
EPC
RFU
0b
locked memory
204h
EPC
Tag Power Indicator
0b
Action bit
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UCODE 7
Bank
address
Bank 10
TID
[1]
[2]
[3]
[4]
[5]
Memory
address
Type
Content
Initial
Remark
205h
EPC
RFU
0b
locked memory
206h
EPC
RFU
0b
locked memory
207h
EPC
RFU
0b
locked memory
208h
EPC
RFU
0b
locked memory
209h
EPC
max. backscatter strength
1b
permanent bit
20Ah
EPC
RFU
0b
locked memory
20Bh
EPC
RFU
0b
locked memory
20Ch
EPC
RFU
0b
locked memory
20Dh
EPC
RFU
0b
locked memory
20Eh
EPC
RFU
0b
locked memory
20Fh
EPC
PSF alarm flag
0b
Permanent bit
00h to 07h
TID
allocation class identifier
1110 0010b
locked memory
08h to 13h
TID
tag mask designer identifier
1000 0000 0110b
locked memory
14h
TID
config word indicator
1b
[3]
[3]
[4]
locked memory
[5]
14h to 1Fh
TID
tag model number
TMNR
locked memory
20h to 2Fh
TID
XTID header
2000h
locked memory
30h to 5Fh
TID
serial number
SNR
locked memory
HEX E280 6890 0000 nnnn nnnn nnnn
where n are the nibbles of the SNR from the TID
Action bits: meant to trigger a feature upon a SELECT command on the related bit ref feature control mechanism, seeSection 10.6.1
Permanent bit: permanently stored bits in the memory; Read/Writeable according EPC bank lock status, see Section 10.6.1
Indicates the existence of a Configuration Word at the end of the EPC number
See Figure 7
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UCODE 7
10.5.2 UCODE 7 TID memory details
First 48 bit of TID
memory
Class ID
Mask
Designer
ID
E28068902000
E2h
806h
UCODE 7
Addresses
Model Number
Config
Word
Indicator
1b
00h
Sub
Version
Version Nr. (Silicon) Nr.
0001b
0010000b
XTID
Header
2000h
5Fh
TID
MS Byte
MSBit
Bit
Address
LS Byte
LSBit
00h
07h 08h
Class Identifier
Bits
7
MSBit
E2h
13h 14h
Mask-Designer Identifier
0
11
(EAN.UCC)
0
806h
Bits
20h
2Fh 30h
Model Number
11
(NXP; with XTID)
Address
1Fh
890h
XTID
0
15
(UCODE 7)
14h
2000h
1b
Sub Version Number
3
47
0
000000000000h to FFFFFFFFFFFFh
1Fh
Model Number
0 6
0001b
5Fh
Serial Number
0
(indication of 48bit
unique SNR)
18h 19h
C.
W.
I.
0
LSBit
0
0010000b
(UCODE 7)
aaa-005659
Figure 7. UCODE 7 TID memory structure
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UCODE 7
10.6 Supported features
The UCODE 7 is equipped with a number of additional features, which are implemented
in such a way that standard EPCglobal READ / WRITE / ACCESS / SELECT commands
can be used to operate these features.
The Configuration Word, as mentioned in the memory map, describes the additional
features located at address 200h of the EPC memory.
Bit 14h of the TID indicates the existence of a Configuration Word. This flag will enable
the selection of configuration word enhanced transponders in mixed tag populations.
Please refer to [3] for additional reference.
10.6.1 UCODE 7 features control mechanism
The different features of the UCODE 7 can be activated / de-activated by addressing
or changing the content of the corresponding bit in the configuration word located at
address 200h in the EPC memory bank (see Table 10). The de-activation of the action bit
features will only happen after chip reset.
Table 10. Configuration word UCODE 7
Locked memory
Action bit
Locked memory Action bit
Locked memory
RFU
RFU
Parallel
encoding
RFU
Tag Power
Indicator
RFU
RFU
RFU
0
1
2
3
4
5
6
7
Table 11. Configuration word UCODE 7 ... continued
Locked Permanent
memory bit
Locked memory
Permanent
bit
RFU
max.
backscatter
strength
RFU
RFU
RFU
RFU
RFU
PSF Alarm bit
8
9
10
11
12
13
14
15
The configuration word contains 2 different type of bits:
• Action bits: meant to trigger a feature upon a SELECT command on the related bit:
Parallel encoding
Tag Power indicator
• Permanent bits: permanently stored bits in the memory
Max. Backscatter Strength
PSF Alarm bit
The activation or the de-activation of the feature behind the permanent bits happens only
when attempting to write a "1" value to the related bit (value toggling) - writing "0" value
will have no effect.
If the feature is activated, the related bit will be read with a "1" value and, if de-activated,
with a "0" value.
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UCODE 7
The permanent bits can only be toggled by using standard EPC WRITE (not a
BlockWrite) if the EPC bank is unlocked or within the SECURED state if the EPC is
locked. If the EPC is perma locked, they cannot be changed.
Action bits will trigger a certain action only if the pointer of the SELECT command exactly
matches the action-bit address (i.e. 202h or 204h), if the length=1 and if mask=1b
(no multiple trigger of actions possible within one single SELECT command).
After issuing a SELECT to any action bits an interrogator shall transmit CW for RTCal [1]
+ 80 μs before sending the next command.
If the truncate bit in the SELECT command is set to "1" the SELECT will be ignored.
A SELECT on action bits will not change the digital state of the chip.
The action bits can be triggered regardless if the EPC memory is unlocked, locked or
permalocked.
10.6.2 Backscatter strength reduction
The UCODE 7 features two levels of backscatter strengths. Per default maximum
backscatter is enabled in order to enable maximum read rates. When clearing the flag
the strength can be reduced if needed.
10.6.3 Pre-serialization of the 96-bit EPC
Description
The 96-bit EPC, which is the initial EPC length settings of UCODE7, will be delivered preserialized with the 48-bit serial number from the TID.
Use cases and benefits
With a pre-serialized EPC, the encoding process of the tags with UCODE 7 gets simpler
and faster as it only needs to encode the SKU (58-bit header of the EPC).
10.6.4 Parallel encoding
Description
This feature of the UCODE 7 can be activated by the "Parallel encoding bit" in the
Configuration-Word located at (202h).
Upon issuing a EPC SELECT command on the "Parallel encoding bit", in a population of
UCODE 7 tags, a subsequent QUERY brings all tags go the OPEN state with a specific
handle ("AAAAh").
Once in the OPEN state, for example a WRITE command will apply to all tags in the
OPEN state (see Figure 9). This parallel encoding is considerably lowering the encoding
time compared to a standard implementation (see Figure 8).
The amount of tags that can be encoded at the same time will depend on the strength of
the reader signal. Since all tags will backscatter their ACKNOWLEDGE (ACK) response
at the same time, the reader will observe collision in the signal from the tags.
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UCODE 7
QUERY/Adjust/Rep
QUERY/Adjust/Rep
READER
WRITE
Req_RN
Req_RN
ACK
WRITE
Req_RN
(16-bit)
handle
RN16
TAG 1
handle
PC + EPC
RN16
ACK
Req_RN
(16-bit)
handle
RN16
TAG 2
handle
PC + EPC
handle
Tags
Only TAG 1 is being addressed
Only TAG 2 is being addressed
aaa-006843
Figure 8. Example of 16-bit Write command with standard EPC Gen 2 commands
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UCODE 7
QUERY (Q=0)
(16-bit)
READER
WRITE
AAAAh
AAAAh
TAG 1
AAAAh
AAAAh
AAAAh
AAAAh
Tags
AAAAh
AAAAh
AAAAh
Req_RN
SELECT on
Parallel
encoding bit
TAG 2
TAG n
All UCODE 7 tags receive the Command
aaa-006844
Figure 9. Illustration of Parallel encoding for 16-bit Write command
Use cases and benefits
Parallel encoding feature of UCODE 7 can enable ultra fast bulk encoding.
Taking in addition advantage of the pre-serialization scheme of UCODE 7, the same SKU
can be encoded in multiple tags as the EPC will be delivered pre-serialized already.
In the case of only one tag answering (like in printer encoding), this feature could be used
to save some overhead in commands to do direct EPC encoding after the handle reply.
Since this is a UCODE 7 specific feature the use of this features requires support on the
reader side.
10.6.5 Tag Power Indicator
Description
Upon a SELECT command on the "Tag Power Indicator", located in the config word
204h, an internal power check on the chip is performed to see if the power level is
sufficient to perform a WRITE command. The decision level is defined as nominal WRITE
sensitivity minus 1dB. In the case there is enough power, the SELECT command is
matching and non-matching if not enough power. The tag can then be singulated by the
standard inventory procedure.
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UCODE 7
Use cases and benefits
This feature gives the possibility to select only the tag(s) that receive enough power to
be written during e.g. printer encoding in a dense environment of tags even though the
reader may read more than one tag (see Figure 10 for illustration). The power level still
needs to be adjusted to transmit enough writing power to one tag only to do one tag
singulation.
Power level for READ/WRITE
too low/too low
OK/too low
OK/too low
OK/OK
Only this tag will select itself
OK/too low
OK/too low
too low/too low
aaa-005662
Figure 10. Selection of tags with Tag Power Indicator feature
10.6.6 Product Status Flag (PSF)
Description
The PSF is a general purpose bit located in the Configuration word at address 20Fh with
a value that can be freely changed.
Use cases and benefits
The PSF bit can be used as an EAS (Electronic Article Surveillance) flag, quality checked
flag or similar.
In order to detect the tag with the PSF activated, a EPC SELECT command selecting
the PSF flag of the Configuration word can be used. In the following inventory round only
PSF enabled chips will reply their EPC number.
10.6.7 Single-slit antenna solution
Description
In UCODE 7 the test pads TP1 and TP2 are electrically disconnected meaning they are
not electrically active and can be safely short-circuited to the RF pads RF1 and RF2 (see
Figure 11).
Standard assembly
Single-slit assembly
Supporting pads
aaa-005857
Figure 11. Standard antenna design versus single-slit antenna
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UCODE 7
Uses cases and benefits
Using single-slit antenna enables easier assembly and antenna design. Inlay
manufacturer will only have to take care about one slit of the antenna instead of two in
case all pads need to be disconnected from each other.
Additionally single-slit antenna assembly and the related increased input capacitance
(see Table 13) can be used advantageously over the standard antenna design as
additional room for optimization to different antenna design.
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UCODE 7
11 Limiting values
[1][2]
Table 12. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to RFN
Symbol
Parameter
Conditions
Min
Max
Unit
-55
+125
°C
-40
+85
°C
-
±2
kV
-
100
mW
Bare die limitations
Tstg
storage temperature
Tamb
ambient temperature
VESD
electrostatic discharge
voltage
Human body model
[3][4]
Pad limitations
Pi
[1]
[2]
[3]
[4]
input power
maximum power
dissipation, RFP pad
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any conditions other than those described in the
Operating Conditions and Electrical Characteristics section of this specification is not implied.
This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of
excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater
than the rated maxima.
ANSI/ESDA/JEDEC JS-001
For ESD measurement, the die chip has been mounted into a CDIP20 package.
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe
precautions for handling electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5,
JESD625-A or equivalent standards.
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UCODE 7
12 Characteristics
12.1 UCODE 7 bare die characteristics
Table 13. UCODE 7 RF interface characteristics (RF1, RF2)
Symbol
Parameter
fi
input frequency
Conditions
Min
Typ
Max
Unit
840
-
960
MHz
Pi(min)
minimum input power
READ sensitivity
[1][2][3]
-
-21
-
dBm
-
-16
-
dBm
Pi(min)
minimum input power
WRITE sensitivity
[4]
t 16bit
Encoding speed
16-bit
[5]
-
1
-
ms
32-bit (block write)
[5]
-
1.8
-
ms
parallel
[2][6]
-
0.63
-
pF
866 MHz
[2][6]
-
14.5-j293 -
Ω
915 MHz
[2][6]
-
12.5-j277 -
Ω
953 MHz
[2][6]
-
12.5-j267 -
Ω
915MHz
[8]
-
18-j245
Ω
915MHz
[8][9]
-
13.5-j195 -
Ω
[2][6]
-
0.68
pF
866 MHz
[2][6]
-
12.6-j267 -
Ω
915 MHz
[2][6]
-
11.8-j254 -
Ω
953 MHz
[2][6]
-
11.5-j244 -
Ω
[4]
-
-15
dBm
Ci
Chip input capacitance
Z
Chip impedance
Z
Typical assembled impedance
[7]
Z
Typical assembled impedance
[7]
in case of single-slit antenna
assembly
Ci
Chip input capacitance, Large Pads parallel
Z
Chip impedance, Large Pads
-
Tag Power Indicator mode
Pi(min)
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
minimum input power level to be
able to select the tag
-
Power to process a QUERY command
Measured with a 50 Ω source impedance directly on the chip
Results in approximately -21,5dBm tag sensitivity with a 2dBi gain antenna
Tag sensitivity on a 2dBi gain antenna
When the memory content is "0000...".
At minimum operating power
Assuming a 80fF additional input capacitance, 250fF in case of single slit antenna
The antenna shall be matched to this impedance
Depending on the specific assembly process, sensitivity losses of few tenths of dB might occur
Table 14. UCODE 7 memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb ≤ 55 °C
20
-
-
year
100k
-
-
cycle
EEPROM characteristics
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tret
retention time
Nendu(W)
write endurance
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UCODE 7
12.2 UCODE 7 SOT886 characteristics
Table 15. UCODE 7 RF interface characteristics (RF1, RF1)
Symbol
Product data sheet
COMPANY PUBLIC
Conditions
Pi(min)
minimum input power
READ
sensitivity
[1][2]
Z
impedance
915 MHz
[3]
[1]
[2]
[3]
SL3S1204
Parameter
Min
Typ
Max
Unit
-
-21
-
dBm
-
12.8 -j248
-
Ω
Power to process a Query command.
Measured with a 50 Ω source impedance.
At minimum operating power.
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UCODE 7
13 Package outline
XSON6: plastic, extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.45 x 0.5 mm
SOT886-1
X
A
A1
D
B
A
detail X
E
terminal 1
index area
terminal 1
index area
e1
C
v
w
b
L2
1
3
C A B
C
y1 C
y
L1
e
L
6
4
0
2 mm
scale
Dimensions (mm are the original dimensions)
Unit
mm
A
A1
b
D
E
max 0.50 0.05 0.25 1.50 1.05
nom
0.20 1.45 1.00
0.00 0.17 1.40 0.95
min
e
0.6
e1
1.0
L
L1
L2
v
w
y
y1
0.35 0.40 0.10
0.30 0.35 0.05 0.10 0.05 0.05 0.05
0.27 0.32 0.02
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outline
version
References
IEC
JEDEC
JEITA
sot886-1_po
European
projection
Issue date
13-07-03
13-07-10
SOT886-1
Figure 12. Package outline SOT886
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UCODE 7
14 Packing information
14.1 Wafer
See [2]
See [4]
14.2 SOT886
See: www.nxp.com/packages/SOT886.html
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15 Abbreviations
Table 16. Abbreviations
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Acronym
Description
CRC
Cyclic Redundancy Check
CW
Continuous Wave
DSB-ASK
Double Side Band-Amplitude Shift Keying
DC
Direct Current
EAS
Electronic Article Surveillance
EEPROM
Electrically Erasable Programmable Read Only Memory
EPC
Electronic Product Code (containing Header, Domain Manager, Object Class
and Serial Number)
FM0
Bi phase space modulation
G2
Generation 2
IC
Integrated Circuit
PIE
Pulse Interval Encoding
PSF
Product Status Flag
RF
Radio Frequency
UHF
Ultra High Frequency
SECS
Semi Equipment Communication Standard
TID
Tag IDentifier
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UCODE 7
16 References
[1]
[2]
[3]
[4]
EPCglobal: EPC Radio-Frequency Identity Protocols Class-1 Generation-2
UHF RFID Protocol for Communications at 860 MHz – 960 MHz, Version 1.1.0
(December 17, 2005)
Data sheet - Delivery type description – General specification for 8" wafer on UV1
tape with electronic fail die marking, BU-S&C document number: 1093**
Application note - AN11274 – FAQ on UCODE 7
Data sheet - Delivery type description – General specification for 12" wafer on UVtape with electronic fail die marking, BU-S&C document number: 1862**
1 ** ... document version number
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17 Revision history
Table 17. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
SL3S1204 v. 4.0
20190305
Product data sheet
-
SL3S1204 v. 3.9
Modifications:
• Section 16 updated
SL3S1204 v. 3.9
20170321
Product data sheet
-
SL3S1204 v. 3.8
Modifications:
•
•
•
•
•
SL3S1204 v. 3.8
20161011
Product data sheet
-
SL3S1204 v. 3.7
Modifications:
• Figure 7: updated
• Figure 12: updated
• Editorial changes
SL3S1204 v. 3.7
20160718
Product data sheet
-
SL3S1204 v. 3.6
Modifications:
• Update Automatic Pre-serialization functionality
• Figure 7 - change of TID
SL3S1204 v. 3.6
20160524
-
SL3S1204 v. 3.5
Modifications:
•
•
•
•
•
SL3S1204 v. 3.5
20150706
Product data sheet
-
SL3S1204 v. 3.4
Modifications:
• SOT886 package added
SL3S1204 v. 3.4
20141017
Product data sheet
-
SL3S1204 v. 3.3
Modifications:
• Table 9: corrected
• Editorial changes
SL3S1204 v. 3.3
20131217
Product data sheet
-
SL3S1204 v. 3.2
Modifications:
• Figure 7: Automatic self pre-serialization scheme for 96-bit EPC: corrected
SL3S1204 v. 3.2
20131120
Modifications:
• Security level changed from "COMPANY PROPRIETARY" to "COMPANY PUBLIC"
SL3S1204 v. 3.1
20130603
Modifications:
• Security level changed from "COMPANY CONFIDENTIAL" to "COMPANY PROPRIETARY"
241330
20130522
Modifications
•
•
•
•
•
241312
20130422
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Introduction of Large Pads
Table 1 :updated
Section 8.2: added
Section 9.1.2: added
Table 13: updated
Product data sheet
Introduction of 12 inch wafer delivery
Section 8.3: added
Section 9.1.3: added
Section 14.2: added
Table 15: impedance value added
Product data sheet
Product data sheet
Product data sheet
-
SL3S1204 v. 3.1
241330
241312
Editorial changes
Figure 4: updated
Table 9: updated
Table 10: updated
Table 13: updated
Objective data sheet
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Document ID
Release date
Modifications
•
•
•
•
•
241311
20130325
Modifications
General Update
241310
20130226
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Data sheet status
Change notice
Supersedes
Editorial changes
Figure 7: updated
Figure 7: Automatic self pre-serialization scheme for 96-bit EPC: updated
Figure 10: updated
Figure 11: updated
Objective data sheet
Objective data sheet
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18 Legal information
18.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
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Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 4.0 — 5 March 2019
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NXP Semiconductors
UCODE 7
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
SL3S1204
Product data sheet
COMPANY PUBLIC
18.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
UCODE — is a trademark of NXP B.V.
All information provided in this document is subject to legal disclaimers.
Rev. 4.0 — 5 March 2019
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37 / 40
SL3S1204
NXP Semiconductors
UCODE 7
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.
Ordering information ..........................................5
Marking codes ...................................................6
Pin description bare die .................................... 8
Pin description SOT886 .................................... 8
Specifications .................................................. 12
Specifications .................................................. 13
Specifications .................................................. 14
UCODE 7 memory sections ............................ 18
UCODE 7 overall memory map .......................18
Configuration word UCODE 7 ......................... 21
SL3S1204
Product data sheet
COMPANY PUBLIC
Tab. 11.
Tab. 12.
Tab. 13.
Tab. 14.
Tab. 15.
Tab. 16.
Tab. 17.
Configuration word UCODE 7 ... continued ..... 21
Limiting values ................................................ 27
UCODE 7 RF interface characteristics (RF1,
RF2) ................................................................ 28
UCODE 7 memory characteristics .................. 28
UCODE 7 RF interface characteristics (RF1,
RF1) ................................................................ 29
Abbreviations ...................................................32
Revision history ...............................................34
All information provided in this document is subject to legal disclaimers.
Rev. 4.0 — 5 March 2019
241340
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38 / 40
SL3S1204
NXP Semiconductors
UCODE 7
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Block diagram of UCODE 7 IC ......................... 7
Pinning bare die ................................................ 8
Pin configuration for SOT886 ............................8
UCODE 7 8 inch wafer layout ...........................9
UCODE 7 8 inch wafer layout with large
pads .................................................................10
UCODE 7 12 inch wafer layout ....................... 11
UCODE 7 TID memory structure .................... 20
SL3S1204
Product data sheet
COMPANY PUBLIC
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Example of 16-bit Write command with
standard EPC Gen 2 commands .................... 23
Illustration of Parallel encoding for 16-bit
Write command ............................................... 24
Selection of tags with Tag Power Indicator
feature ............................................................. 25
Standard antenna design versus single-slit
antenna ............................................................25
Package outline SOT886 ................................ 30
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Rev. 4.0 — 5 March 2019
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39 / 40
SL3S1204
NXP Semiconductors
UCODE 7
Contents
1
2
2.1
2.1.1
2.2
2.2.1
2.2.2
2.2.3
2.3
3
3.1
3.2
4
5
6
7
7.1
8
8.1
8.2
8.3
9
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
10
10.1
10.2
10.3
10.3.1
10.3.2
10.4
10.5
10.5.1
10.5.2
10.6
10.6.1
10.6.2
10.6.3
10.6.4
10.6.5
10.6.6
10.6.7
11
12
12.1
12.2
13
14
14.1
General description ............................................ 1
Features and benefits .........................................2
Key features ...................................................... 2
Memory .............................................................. 2
Key benefits .......................................................2
End user benefit ................................................ 2
Antenna design benefits .................................... 2
Label manufacturer benefit ................................3
Supported features ............................................ 3
Applications .........................................................4
Markets .............................................................. 4
Applications ........................................................4
Ordering information .......................................... 5
Marking .................................................................6
Block diagram ..................................................... 7
Pinning information ............................................ 8
Pin description ................................................... 8
Wafer layout ........................................................ 9
Wafer layout 8 inch ........................................... 9
Wafer layout 8 inch with large pads .................10
Wafer layout 12 inch ....................................... 11
Mechanical specification .................................. 12
Wafer specification .......................................... 12
8 inch Wafer, Standard bumps ........................ 12
8 inch Wafer, Large pads ................................ 13
12 inch Wafer .................................................. 14
Fail die identification ........................................ 15
Map file distribution ......................................... 16
Functional description ......................................17
Air interface standards .....................................17
Power transfer ................................................. 17
Data transfer ....................................................17
Interrogator to tag Link .................................... 17
Tag to interrogator Link ................................... 17
Supported commands ......................................17
UCODE 7 memory .......................................... 18
UCODE 7 overall memory map ....................... 18
UCODE 7 TID memory details ........................ 20
Supported features .......................................... 21
UCODE 7 features control mechanism ............21
Backscatter strength reduction ........................ 22
Pre-serialization of the 96-bit EPC ...................22
Parallel encoding ............................................. 22
Tag Power Indicator ........................................ 24
Product Status Flag (PSF) ...............................25
Single-slit antenna solution ..............................25
Limiting values .................................................. 27
Characteristics .................................................. 28
UCODE 7 bare die characteristics ...................28
UCODE 7 SOT886 characteristics .................. 29
Package outline .................................................30
Packing information ..........................................31
Wafer ............................................................... 31
14.2
15
16
17
18
SOT886 ............................................................31
Abbreviations .................................................... 32
References ......................................................... 33
Revision history ................................................ 34
Legal information .............................................. 36
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2019.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 5 March 2019
Document identifier: SL3S1204
Document number: 241340
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