SLRC40001T/OFE,112

SLRC400 ICODE reader IC Rev. 3.3 — 23 March 2010 054333 Product data sheet PUBLIC 1. Introduction This data sheet describes the functionality of the SLRC400 Integrated Circuit (IC). It includes the functional and electrical specifications and from a system and hardware viewpoint gives detailed information on how to design-in the device. 2. General description The SLRC400 is a member of a new family of highly integrated reader ICs for contactless communication at 13.56 MHz. This family of reader ICs provide: • outstanding modulation and demodulation for passive contactless communication • a wide range of methods and protocols The transmitter module Section 8.9 on page 24 can directly drive an antenna designed for proximity operating distance up to 100 mm without additional active circuitry. The receiver module provides a robust and efficient demodulation/decoding circuitry implementation for compatible transponder signals (see Section 8.10 on page 28). All layers of the ICODE1 and ISO/IEC 15693 protocols are supported. The receiver module provides a robust and efficient demodulation/decoding circuitry implementation for ICODE1 and ISO/IEC 15693 compatible transponder signals. The digital module manages ICODE1 and ISO/IEC 15693 framing and error detection (CRC). A parallel interface can be directly connected to any 8-bit microprocessor to ensure reader/terminal design flexibility. 3. Features and benefits 3.1 General Highly integrated analog circuitry for demodulating and decoding label response Buffered output drivers enable antenna connection using the minimum of external components Proximity operating distance up to 100 mm Supports both ICODE1 and ISO/IEC 15693 protocols Parallel microprocessor interface with internal address latch and IRQ line Flexible interrupt handling Automatic detection of parallel microprocessor interface type 64-byte send and receive FIFO buffer Hard reset with low power function SLRC400 NXP Semiconductors ICODE reader IC Software controlled Power-down mode Programmable timer Unique serial number User programmable start-up configuration Bit-oriented and byte oriented framing Independent power supply pins for analog, digital and transmitter modules Internal oscillator buffer optimized for low phase jitter enables 13.56 MHz quartz connection Clock frequency filtering 3.3 V operation for transmitter (antenna driver) in short range and proximity applications 4. Applications Electronic payment systems Identification systems Access control systems Subscriber services Banking systems Digital content systems 5. Ordering information Table 1. Ordering information Type number SLRC40001T/0FE SLRC400_33 Product data sheet PUBLIC Package Name Description Version SO32 plastic small outline package; 32 leads; body width 7.5 mm SOT287-1 All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 2 of 101 SLRC400 NXP Semiconductors ICODE reader IC 6. Block diagram 2;6 26(  2'7  %0)  % % %  %(XS%((XS(            4%6%00)0-28)6*%')'328630 -2'09(-2+%9831%8-'-28)6*%')()8)'8-32%2(7=2',632-7%8-32 *-*3'328630 78%8)1%',-2) &=8)*-*3 '311%2(6)+-78)6 463+6%11%&0)8-1)6 '3286306)+-78)6 &%2/ :308%+) 132-836 %2( 43;)632 ()8)'8   (:77 6)7)8 '328630 43;)6(3;2 '328630   -28)66948'328630 »&=8) ))4631 (:(( 6784( -65 '6''6' +)2)6%8-32%2(',)'/ ))4631 %'')77 '328630 4%6%00)07)6-%0'32:)68)6 &-8'3928)6 1%78)6/)=&9**)6 4%6-8=+)2)6%8-32%2(',)'/ *6%1)+)2)6%8-32%2(',)'/ '6=48392-8 &-8()'3(-2+ &-847)9(3 6%2(31+)2)6%836 &-8)2'3(-2+   7)6-%0(%8%7;-8', RG 7-+398 0):)07,-*8)67 %140-89() 6%8-2+ '366)0%8-32 %2( &-8()'3(-2+ 6)*)6)2') :308%+) %2%03+ 8)78 1908-40) 0, the TimeSlotPeriod starts. If the FIFO buffer contains data when the end of TimeSlotPeriod is reached, the data is sent. If the FIFO buffer is empty nothing happens. As long as the TimeSlotPeriod is > 0, the TimeSlotPeriod counter automatically starts on reaching the end. This forms the exact time relationship between the start and finish of the command frame used to generate and send ICODE1 Quit frames. When the TimeSlotPeriod > 0, the next Frame starts with exactly the same interval TimeSlotPeriod/CoderRate delayed after each previous send frame. CoderRate defines the clock frequency of the encoder. If TimeSlotPeriod[7:0] = 0, the send function is not automatically triggered. The content of the TimeSlotPeriod register can be changed while it is running but the change is only effective after the next TimeSlotPeriod restart. Example: • CoderRate = 0 0.5 (~52.97 kHz) • The interval should be 8.458 ms for ICODE1 standard mode TimeSlotPeriod = CoderRate Interval = 52.97 kHz 8.458 ms 1 = 447 = 1BFh Remark: The TimeSlotPeriod MSB bit is contained in the SIGOUTSelect register. '311%2( 59-8 59-8 6)74327) 874 Fig 7. SLRC400_33 Product data sheet PUBLIC 6)74327) 874 EEO TimeSlotPeriod All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 19 of 101 SLRC400 NXP Semiconductors ICODE reader IC Table 17. TimeSlotPeriod ICODE1 mode TimeSlotPeriod for TSP1 TimeSlotPeriod for TSP2 standard mode BFh 1BFh fast mode 5Fh 67h Remark: Set bit TxCRCEn to logic 0 before the Quit frame is sent. If TxCRCEn is not set to logic 0, the Quit frame is sent with a calculated CRC value. Use the CRC8 algorithm to calculate the Quit value. 8.5.2 Using the timer unit functions 8.5.2.1 Time-out and WatchDog counters After starting the timer using TReloadValue[7:0], the timer unit decrements the TimerValue register beginning with a given start event. If a given stop event occurs, such as a bit being received from the label, the timer unit stops without generating an interrupt. If a stop event does not occur, such as the label not answering within the expected time, the timer unit decrements down to zero and generates a timer interrupt request. This signals to the microprocessor the expected event has not occurred within the given time (tTimer). 8.5.2.2 Stopwatch The time (tTimer) between a start and stop event is measured by the microprocessor using the timer unit. Setting the TimerReload register triggers the timer which in turn, starts to decrement. If the defined stop event occurs, the timer stops. The time between start and stop is calculated by the microprocessor using Equation 5, when the timer does not decrement down to zero. t = TReLoad value – TimerValue 8.5.2.3 (5) t Timer Programmable one shot timer and periodic trigger Programmable one shot timer: The microprocessor starts the timer unit and waits for the timer interrupt. The interrupt occurs after the time specified by t Timer (TAutoRestart bit = logic 0). Periodic trigger: If the microprocessor sets the TAutoRestart bit, and TReloadValue is not equal to zero, it generates an interrupt request after every tTimer cycle. 8.5.3 Timer unit registers Table 18 shows the related flags of the timer unit in alphabetical order. Table 18. Associated timer unit registers and flags Flags SLRC400_33 Product data sheet PUBLIC Register name Bit Register address TAutoRestart TimerClock 5 2Ah TimerValue[7:0] TimerValue 7 to 0 0Ch TReloadValue[7:0] TimerReload 7 to 0 2Ch TPreScaler[4:0] TimerClock 4 to 0 2Ah TRunning SecondaryStatus 7 05h TStartNow Control 1 09h All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 20 of 101 SLRC400 NXP Semiconductors ICODE reader IC Table 18. Associated timer unit registers and flagsiGSRXMRYIH Flags Register name Bit Register address TStartTxBegin TimerControl 0 2Bh TStartTxEnd TimerControl 1 2Bh TStopNow Control 2 09h TStopRxBegin TimerControl 2 2Bh TStopRxEnd TimerControl 3 2Bh 8.6 Power reduction modes 8.6.1 Hard power-down Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pads and defined internally (except pin RSTPD itself). The output pins are frozen at a given value. The status of all pins during a hard power-down is shown in Table 19. Table 19. Signal on pins during Hard power-down Symbol Pin Type Description OSCIN IRQ 1 I not separated from input, pulled to AVSS 2 O high-impedance n.c. 3 I separated from input SIGOUT 4 O LOW TX1 5 O HIGH TX2 7 O LOW NCS 9 I separated from input NWR 10 I separated from input NRD 11 I separated from input D0 to D7 13 to 20 I/O separated from input ALE 21 I separated from input A0 22 I/O separated from input A1 23 I separated from input A2 24 I separated from input AUX 27 O high-impedance RX 29 I not changed VMID 30 A pulled to VDDA RSTPD 31 I not changed OSCOUT 32 O HIGH 8.6.2 Soft power-down mode Soft power-down mode is entered immediately using the Control register bit PowerDown. All internal current sinks, including the oscillator buffer, are switched off. The digital input buffers are not separated from the input pads and keep their functionality. In addition, the digital output pins do not change their state. SLRC400_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 21 of 101 SLRC400 NXP Semiconductors ICODE reader IC After resetting the Control register bit PowerDown, the bit indicating Soft power-down mode is only cleared after 512 clock cycles. Resetting it does not immediately clear it. The PowerDown bit is automatically cleared when the Soft power-down mode is exited. Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to become stable. This is because the internal oscillator is supplied by V DDA and any clock cycles will not be detected by the internal logic until V DDA is stable. 8.6.3 Standby mode The Standby mode is immediately entered when the Control register StandBy bit is set. All internal current sinks, including the internal digital clock buffer are switched off. However, the oscillator buffer is not switched off. The digital input buffers are not separated by the input pads, keeping their functionality and the digital output pins do not change their state. In addition, the oscillator does not need time to wake-up. After resetting the Control register StandBy bit, it takes four clock cycles on pin OSCIN for Standby mode to exit. Resetting bit StandBy does not immediately clear it. It is automatically cleared when the Standby mode is exited. 8.6.4 Automatic receiver power-down It is a power saving feature to switch off the receiver circuit when it is not needed. Setting bit RxAutoPD = logic 1, automatically powers down the receiver when it is not in use. Setting bit RxAutoPD = logic 0, keeps the receiver continuously powered up. 8.7 StartUp phase The events executed during the StartUp phase are shown in Figure 8. 7XEVX9TTLEWI WXEXIW X6784( XVIWIX XMRMX ,EVHTS[IV HS[RTLEWI 6IWIXTLEWI -RMXMEPMWMRK TLEWI VIEH] EEO Fig 8. The StartUp procedure 8.7.1 Hard power-down phase The hard power-down phase is active during the following cases: • a Power-On Reset (POR) caused by power-up on pins DVDD activated when V DDD is below the digital reset threshold. • a Power-On Reset (POR) caused by power-up on pins AVDD activated when VDDA is below the analog reset threshold. • a HIGH-level on pin RSTPD which is active while pin RSTPD is HIGH. The HIGH level period on pin RSTPD must be at least 100 s (tPD 100 s). Shorter phases will not necessarily result in the reset phase (t reset). The rising or falling edge slew rate on pin RSTPD is not critical because pin RSTPD is a Schmitt trigger input. SLRC400_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 22 of 101 SLRC400 NXP Semiconductors ICODE reader IC 8.7.2 Reset phase The reset phase automatically follows the Hard power-down. Once the oscillator is running stably, the reset phase takes 512 clock cycles. During the reset phase, some register bits are preset by hardware. The respective reset values are given in the description of each register (see Section 9.5 on page 40). Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to become stable. This is because the internal oscillator is supplied by V DDA and any clock cycles will not be detected by the internal logic until V DDA is stable. 8.7.3 Initialization phase The initialization phase automatically follows the reset phase and takes 128 clock cycles. During the initializing phase the content of the EEPROM blocks 1 and 2 is copied into the register subaddresses 10h to 2Fh (see Section 8.2.2 on page 10). Remark: During the production test, the SLRC400 is initialized with default configuration values. This reduces the microprocessor’s configuration time to a minimum. 8.7.4 Initializing the parallel interface type A different initialization sequence is used for each microprocessor. This enables detection of the correct microprocessor interface type and synchronization of the microprocessor’s and the SLRC400’s start-up. See Section 8.1.3 on page 7 for detailed information on the different connections for each microprocessor interface type. During StartUp phase, the command value is set to 3Fh once the oscillator attains clock frequency stability at an amplitude of > 90 % of the nominal 13.56 MHz clock frequency. At the end of the initialization phase, the SLRC400 automatically switches to idle and the command value changes to 00h. To ensure correct detection of the microprocessor interface, the following sequence is executed: • the Command register is read until the 6-bit register value is 00h. On reading the 00h value, the internal initialization phase is complete and the SLRC400 is ready to be controlled • write 80h to the Page register to initialize the microprocessor interface • read the Command register. If it returns a value of 00h, the microprocessor interface was successfully initialized • write 00h to the Page registers to activate linear addressing mode. SLRC400_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 23 of 101 SLRC400 NXP Semiconductors ICODE reader IC 8.8 Oscillator circuit ():-') 37'398 37'-2 1,^ T* T* EEO Fig 9. Quartz clock connection The clock applied to the SLRC400 acts as a time basis for the synchronous system encoder and decoder. The stability of the clock frequency is an important factor for correct operation. To obtain highest performance, clock jitter must be as small as possible. This is best achieved by using the internal oscillator buffer with the recommended circuitry. If an external clock source is used, the clock signal must be applied to pin OSCIN. In this case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock quality has been verified. It must meet the specifications described in Section 12.4.4 on page 84. Remark: We do not recommend using an external clock source. 8.9 Transmitter pins TX1 and TX2 The signal on pins TX1 and TX2 is the 13.56 MHz carrier modulated by an envelope signal. It can be used to drive an antenna directly, using minimal passive components for matching and filtering (see Section 14.1 on page 85). To enable this, the output circuitry is designed with a very low-impedance source resistance. The TxControl register is used to control the TX1 and TX2 signals. 8.9.1 Configuring pins TX1 and TX2 TX1 pin configurations are described in Table 20. Table 20. Pin TX1 configurations TxControl register configuration Envelope TX1 signal TX1RFEn 0 X LOW (GND) 1 0 13.56 MHz modulated carrier 1 1 13.56 MHz unmodulated carrier TX2 pin configurations are described in Table 21. SLRC400_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 24 of 101 SLRC400 NXP Semiconductors ICODE reader IC Table 21. Pin TX2 configurations TxControl register configuration Envelope TX2 signal TX2RFEn TX2Cw TX2Inv 0 X X X LOW (GND) 1 0 0 0 13.56 MHz modulated carrier 1 0 0 1 13.56 MHz unmodulated carrier 1 0 1 0 13.56 MHz modulated carrier frequency, 180 phase-shift relative to TX1 1 0 1 1 13.56 MHz unmodulated carrier, 180 phase-shift relative to TX1 1 1 0 X 13.56 MHz unmodulated carrier 1 1 1 X 13.56 MHz unmodulated carrier, 180 phase-shift relative to TX1 8.9.2 Antenna operating distance versus power consumption Using different antenna matching circuits (by varying the supply voltage on the antenna driver supply pin TVDD), it is possible to find the trade-off between maximum effective operating distance and power consumption. Different antenna matching circuits are described in the Application note Ref. 1. 8.9.3 Antenna driver output source resistance The output source conductance of pins TX1 and TX2 for driving a HIGH level can be adjusted between 1 and 100 using the CwConductance register GsCfgCW[5:0] bits. The values are relative to the reference source resistance (R S(ref)) which is measured during the production test and stored in the SLRC400 EEPROM. It can be read from the product information field (see Section 8.2.1 on page 9). The electrical specification can be found in Section 12.3.3 on page 79. SLRC400_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 25 of 101 SLRC400 NXP Semiconductors ICODE reader IC 8.9.3.1 Source resistance table Table 22. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW 1%28!1ERXMWWE))6 '-6'9-86= '366)0%8-32 '-6'9-86= 1,^ ()13(90%836 :'SVV(5 :'SVV2- :'SVV25 XS 8IWX%RE3YX7IP WCHEXE WCGSPP WCGPSGO :)ZEP6 :)ZEP0 EEO Fig 10. Receiver circuit block diagram The signal can be observed on its way through the receiver as shown in Figure 10. One signal at a time can be routed to pin AUX using the TestAnaSelect register as described in Section 14.2.2 on page 88. 8.10.2 Receiver operation In general, the default settings programmed in the StartUp initialization file are suitable for use with the SLRC400 to ICODE label data communication. However, in some environments specific user settings will achieve better performance. 8.10.2.1 Automatic Q-clock calibration The quadrature demodulation concept of the receiver generates a phase signal (I-clock) and a 90 phase-shifted quadrature signal (Q-clock). To achieve the optimum demodulator performance, the Q-clock and the I-clock must be phase-shifted by 90 . After the reset phase, a calibration procedure is automatically performed. Automatic calibration can be set-up to execute at the end of each Transceive command if bit ClkQCalib = logic 0. Setting bit ClkQCalib = logic 1 disables all automatic calibrations except after the reset sequence. Automatic calibration can also be triggered by the software when bit ClkQCalib has a logic 0 to logic 1 transition. SLRC400_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 29 of 101 SLRC400 NXP Semiconductors ICODE reader IC GEPMFVEXMSRMQTYPWI JVSQVIWIXWIUYIRGI EVMWMRKIHKIMRMXMEXIW 5GPSGOGEPMFVEXMSR GEPMFVEXMSRMQTYPWI JVSQIRHSJ 8VERWGIMZIGSQQERH 'PO5'EPMFFMX EEO Fig 11. Automatic Q-clock calibration Remark: The duration of the automatic Q-clock calibration is 65 oscillator periods or approximately 4.8 s. The ClockQControl register’s ClkQDelay[4:0] value is proportional to the phase-shift between the Q-clock and the I-clock. The ClkQ180Deg status flag bit is set when the phase-shift between the Q-clock and the I-clock is greater than 180 . Remark: • The StartUp initialization file enables automatic Q-clock calibration after a reset • If bit ClkQCalib = logic 1, automatic calibration is not performed. Leaving this bit set to logic 1 can be used to permanently disable automatic calibration. • It is possible to write data to the ClkQDelay[4:0] bits using the microprocessor. The aim could be to disable automatic calibration and set the delay using the software. Configuring the delay value using the software requires bit ClkQCalib to have been previously set to logic 1 and a time interval of at least 4.8 s has elapsed. Each delay value must be written with bit ClkQCalib set to logic 1. If bit ClkQCalib is logic 0, the configured delay value is overwritten by the next automatic calibration interval. 8.10.2.2 Amplifier The demodulated signal must be amplified by the variable amplifier to achieve the best performance. The gain of the amplifiers can be adjusted using the RxControl1 register Gain[1:0] bits; see Table 24. Table 24. Gain factors for the internal amplifier 7II 8EFPIw6\'SRXVSPVIKMWXIVFMXHIWGVMTXMSRWxSRTEKIJSVEHHMXMSREPMRJSVQEXMSR Register setting Gain factor (simulation results) Gain factor [dB] (simulation results) 00 22 20 01 35 24 10 82 31 11 130 35 8.10.2.3 Correlation circuitry The correlation circuitry calculates the degree of matching between the received and an expected signal. The output is a measure of the amplitude of the expected signal in the received signal. This is done for both, the Q and I-channels. The correlator provides two outputs for each of the two input channels, resulting in a total of four output signals. SLRC400_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 30 of 101 SLRC400 NXP Semiconductors ICODE reader IC The correlation circuitry needs the phase information for the incoming label signal for optimum performance. This information is defined for the microprocessor using the BitPhase register. This value defines the phase relationship between the transmitter and receiver clock in multiples of the BitPhase time (t BitPhase) = 1 / 13.56 MHz. 8.10.2.4 Evaluation and digitizer circuitry The correlation results are evaluated for each bit-half of the Manchester coded signal. The evaluation and digitizer circuit decides from the signal strengths of both bit-halves, if the current bit is valid • If the bit is valid, its value is identified • If the bit is not valid, it is checked to identify if it contains a bit-collision Select the following levels for optimal using RxThreshold register bits: • MinLevel[3:0]: defines the minimum signal strength of the stronger bit-halve’s signal which is considered valid. • CollLevel[3:0]: defines the minimum signal strength relative to the amplitude of the stronger half-bit that has to be exceeded by the weaker half-bit of the Manchester coded signal to generate a bit-collision. If the signal’s strength is below this value, logic 1 and logic 0 can be determined unequivocally. After data transmission, the label is not allowed to send its response before a preset time period which is called the frame guard time in the ISO/IEC 15693 standard (similar to ICODE1). The length of this time period is set using the RxWait register’s RxWait[7:0] bits. The RxWait register defines when the receiver is switched on after data transmission to the label in multiples of one bit duration. If bit RcvClkSelI is set to logic 1, the I-clock is used to clock the correlator and evaluation circuits. If bit RcvClkSelI is set to logic 0, the Q-clock is used. Remark: It is recommended to use the Q-clock. 8.11 Serial signal switch The SLRC400 comprises two main blocks: • digital circuitry: comprising the state machines, encoder and decoder logic etc. • analog circuitry: comprising the modulator, antenna drivers, receiver and amplification circuitry The interface between these two blocks can be configured so that the interface signals are routed to pin SIGOUT. 8.11.1 Serial signal switch block diagram Figure 12 shows the serial signal switches. Three different switches are implemented in the serial signal switch enabling the SLRC400 to be used in different configurations. The serial signal switch can also be used to check the transmitted and received data during the design-in phase or for test purposes. Section 14.2.1 on page 87 describes the analog test signals and measurements at the serial signal switch. SLRC400_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 31 of 101 SLRC400 NXP Semiconductors ICODE reader IC WIVMEPHEXESYX 1-00)6'3()6 3983* 6>36 3983*     IRZIPSTI  VIWIVZIH  8 (XS( 1YPXMTPI\IHEHHVIWWFYW X%:(70 %XS% X6,%< %XS% 7ITEVEXIHEHHVIWWFYW EEP Fig 17. Common read/write strobe timing diagram When separate address and data lines are used, the multiplexed addresses on the data bus do not use the ALE signal. When multiplexed address and data lines are used, the address lines (A0 to A2) must be connected as described in Section 8.1.3 on page 7. 12.4.3 EPP bus timing Table 149. Common read/write strobe timing specification for EPP SLRC400_33 Product data sheet PUBLIC Symbol Parameter Conditions Min Typ Max Unit tASLASH address strobe LOW time nAStrb 20 - - ns tAVASH address valid to address strobe HIGH time multiplexed address bus set-up time 15 - - ns tASHAV address valid after address strobe HIGH time multiplexed address bus hold time 8 - - ns All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 82 of 101 SLRC400 NXP Semiconductors ICODE reader IC Table 149. Common read/write strobe timing specification for EPPiGSRXMRYIH Symbol Parameter Conditions Min Typ Max Unit tSLDSL chip select LOW to data strobe LOW time NCS LOW to nDStrb LOW 0 - - ns tDSHSH data strobe HIGH to chip select HIGH time nDStrb HIGH to NCS HIGH 0 - - ns tDSLDV data strobe LOW to data input valid read cycle time - - 65 ns tDSHDZ data strobe HIGH to data input high read cycle impedance time - - 20 ns tDSLQV data strobe LOW to data output valid time nDStrb LOW - - 35 ns tDSHQX data output hold after data strobe HIGH time nDStrb HIGH 8 - - ns tDSHWX write hold after data strobe HIGH time nWrite 8 - - ns tDSLDSH data strobe LOW time nDStrb 65 - - ns tWLDSL write LOW to data strobe LOW time nWrite valid to nDStrb LOW 8 - - ns tDSL-WAITH data strobe LOW to WAIT HIGH time nDStrb LOW to nWait HIGH - - 75 ns tDSH-WAITL data strobe HIGH to WAIT LOW time nDStrb HIGH to nWait LOW - - 75 ns X(7,7, X70(70 2'7 X;0(70 X(7,;< R;VMXI X(70(7, R(7XVF R%7XVF X(70(: X(705: X(7,5< X(7,(> (XS( %XS% (XS( X(70;%-8, X(7,;%-80 R;EMX EEN Fig 18. Timing diagram for common read/write strobe; EPP Remark: Figure 18 does not distinguish between the address write cycle and a data write cycle. The timings for the address write and data write cycle are different. In EPP mode, the address lines (A0 to A2) must be connected as described in Section 8.1.3 on page 7. SLRC400_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 83 of 101 SLRC400 NXP Semiconductors ICODE reader IC 12.4.4 Clock frequency The clock input is pin OSCIN. Table 150. Clock frequency Symbol Parameter Conditions Min Typ Max Unit fclk clock frequency checked by the clock filter - 13.56 - MHz clk clock duty cycle 40 50 60 % - - 10 ps tjit jitter time of clock edges The clock applied to the SLRC400 acts as a time constant for the synchronous system’s encoder and decoder. The stability of the clock frequency is an important factor for ensuring proper performance. To obtain highest performance, clock jitter must be as small as possible. This is best achieved using the internal oscillator buffer and the recommended circuitry; see Section 8.8 on page 24. 13. EEPROM characteristics The EEPROM size is 8 16 8 = 1024 bit. Table 151. EEPROM characteristics SLRC400_33 Product data sheet PUBLIC Symbol Parameter Conditions Min Typ Max Unit Nendu(W_ER) write or erase endurance erase/write cycles 100000 - - Hz tret retention time Tamb 10 - - year ter erase time - - 2.9 ms ta(W) write access time - - 2.9 ms 55 C All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 84 of 101 SLRC400 NXP Semiconductors ICODE reader IC 14. Application information 14.1 Typical application 14.1.1 Circuit diagram Figure 19 shows a typical application where the antenna is directly matched to the SLRC400: (:(( 6IWIX %:(( 8:(( (:(( 6784( %:(( 8:(( GSRXVSPPMRIW ' 0 HEXEFYW 8> SLRC400_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 97 of 101 SLRC400 NXP Semiconductors ICODE reader IC Table 151. EEPROM characteristics . . . . . . . . . . . . . . . .84 Table 152. Signal routed to pin SIGOUT . . . . . . . . . . . . .87 Table 153. Analog test signal selection . . . . . . . . . . . . . .88 Table 154. Digital test signal selection . . . . . . . . . . . . . . . 88 Table 155. Abbreviations and acronyms . . . . . . . . . . . . . 92 Table 156. Revision history . . . . . . . . . . . . . . . . . . . . . . . 93 22. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. SLRC400 block diagram . . . . . . . . . . . . . . . . . . . .3 SLRC400 pin configuration . . . . . . . . . . . . . . . . . .4 Connection to microprocessor: separate read and write strobes . . . . . . . . . . . . . . . . . . . . . .7 Connection to microprocessor: common read and write strobes . . . . . . . . . . . . . . . . . . . . . .8 Connection to microprocessor: EPP common read/write strobes and handshake. . . . . . . . . . . . .8 Timer module block diagram . . . . . . . . . . . . . . . .17 TimeSlotPeriod . . . . . . . . . . . . . . . . . . . . . . . . . .19 The StartUp procedure. . . . . . . . . . . . . . . . . . . . .22 Quartz clock connection . . . . . . . . . . . . . . . . . . .24 Receiver circuit block diagram. . . . . . . . . . . . . . .29 Automatic Q-clock calibration . . . . . . . . . . . . . . .30 Serial signal switch block diagram. . . . . . . . . . . .32 Timing for transmitting byte oriented frames . . . .68 Label communication state diagram . . . . . . . . . .72 EEPROM programming timing diagram. . . . . . . .74 Separate read/write strobe timing diagram . . . . .81 Common read/write strobe timing diagram . . . . .82 Timing diagram for common read/write strobe; EPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Application example circuit diagram: directly matched antenna . . . . . . . . . . . . . . . . . . . . . . . . .85 Q-clock receiving path . . . . . . . . . . . . . . . . . . . . .90 Package outline SOT287-1 . . . . . . . . . . . . . . . . .91 continued >> SLRC400_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 98 of 101 SLRC400 NXP Semiconductors ICODE reader IC 23. Contents 1 2 3 3.1 4 5 6 7 7.1 8 8.1 8.1.1 8.1.2 8.1.3 8.1.3.1 8.1.3.2 8.1.3.3 8.2 8.2.1 8.2.2 8.2.2.1 8.2.2.2 8.2.2.3 8.3 8.3.1 8.3.1.1 8.3.2 8.3.3 8.3.4 8.4 8.4.1 8.4.2 8.4.2.1 8.4.2.2 8.4.3 8.4.4 8.5 8.5.1 8.5.1.1 8.5.1.2 8.5.1.3 8.5.1.4 8.5.1.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 6 Digital interface . . . . . . . . . . . . . . . . . . . . . . . . . 6 Overview of supported microprocessor interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Automatic microprocessor interface detection . 6 Connection to different microprocessor types . 7 Separate read and write strobe . . . . . . . . . . . . 7 Common read and write strobe . . . . . . . . . . . . 8 Common read and write strobe: EPP with handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Memory organization of the EEPROM . . . . . . . 9 Product information field (read only). . . . . . . . . 9 Register initialization file (read/write) . . . . . . . 10 StartUp register initialization file (read/write) . 10 Factory default StartUp register initialization file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Register initialization file (read/write) . . . . . . . 12 FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Accessing the FIFO buffer . . . . . . . . . . . . . . . 12 Access rules . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Controlling the FIFO buffer . . . . . . . . . . . . . . . 13 FIFO buffer status information . . . . . . . . . . . . 13 FIFO buffer registers and flags . . . . . . . . . . . . 13 Interrupt request system. . . . . . . . . . . . . . . . . 14 Interrupt sources overview . . . . . . . . . . . . . . . 14 Interrupt request handling. . . . . . . . . . . . . . . . 15 Controlling interrupts and getting their status . 15 Accessing the interrupt registers . . . . . . . . . . 15 Configuration of pin IRQ . . . . . . . . . . . . . . . . . 15 Register overview interrupt request system . . 16 Timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Timer unit implementation . . . . . . . . . . . . . . . 17 Timer unit block diagram . . . . . . . . . . . . . . . . 17 Controlling the timer unit. . . . . . . . . . . . . . . . . 17 Timer unit clock and period. . . . . . . . . . . . . . . 18 Timer unit status . . . . . . . . . . . . . . . . . . . . . . . 19 Time-slot period . . . . . . . . . . . . . . . . . . . . . . . 19 8.5.2 8.5.2.1 8.5.2.2 8.5.2.3 Using the timer unit functions. . . . . . . . . . . . . Time-out and WatchDog counters . . . . . . . . . Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable one shot timer and periodic trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.3 Timer unit registers . . . . . . . . . . . . . . . . . . . . 8.6 Power reduction modes . . . . . . . . . . . . . . . . . 8.6.1 Hard power-down. . . . . . . . . . . . . . . . . . . . . . 8.6.2 Soft power-down mode . . . . . . . . . . . . . . . . . 8.6.3 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . 8.6.4 Automatic receiver power-down. . . . . . . . . . . 8.7 StartUp phase . . . . . . . . . . . . . . . . . . . . . . . . 8.7.1 Hard power-down phase . . . . . . . . . . . . . . . . 8.7.2 Reset phase. . . . . . . . . . . . . . . . . . . . . . . . . . 8.7.3 Initialization phase . . . . . . . . . . . . . . . . . . . . . 8.7.4 Initializing the parallel interface type . . . . . . . 8.8 Oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . 8.9 Transmitter pins TX1 and TX2 . . . . . . . . . . . . 8.9.1 Configuring pins TX1 and TX2. . . . . . . . . . . . 8.9.2 Antenna operating distance versus power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . 8.9.3 Antenna driver output source resistance . . . . 8.9.3.1 Source resistance table . . . . . . . . . . . . . . . . . 8.9.3.2 Changing the modulation index . . . . . . . . . . . 8.9.3.3 Calculating the relative source resistance . . . 8.9.3.4 Calculating the effective source resistance . . 8.9.4 Pulse width. . . . . . . . . . . . . . . . . . . . . . . . . . . 8.10 Receiver circuitry . . . . . . . . . . . . . . . . . . . . . . 8.10.1 Receiver circuit block diagram . . . . . . . . . . . . 8.10.2 Receiver operation. . . . . . . . . . . . . . . . . . . . . 8.10.2.1 Automatic Q-clock calibration . . . . . . . . . . . . 8.10.2.2 Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.10.2.3 Correlation circuitry . . . . . . . . . . . . . . . . . . . . 8.10.2.4 Evaluation and digitizer circuitry . . . . . . . . . . 8.11 Serial signal switch . . . . . . . . . . . . . . . . . . . . 8.11.1 Serial signal switch block diagram . . . . . . . . . 8.11.2 Serial signal switch registers . . . . . . . . . . . . . 9 SLRC400 registers . . . . . . . . . . . . . . . . . . . . . 9.1 Register addressing modes . . . . . . . . . . . . . . 9.1.1 Page registers . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2 Dedicated address bus . . . . . . . . . . . . . . . . . 9.1.3 Multiplexed address bus . . . . . . . . . . . . . . . . 9.2 Register bit behavior . . . . . . . . . . . . . . . . . . . 9.3 Register overview . . . . . . . . . . . . . . . . . . . . . 9.4 SLRC400 register flags overview. . . . . . . . . . 9.5 Register descriptions . . . . . . . . . . . . . . . . . . . 9.5.1 Page 0: Command and status . . . . . . . . . . . . 9.5.1.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 20 20 20 21 21 21 22 22 22 22 23 23 23 24 24 24 25 25 26 26 28 28 28 28 28 29 29 30 30 31 31 31 32 34 34 34 34 34 34 36 38 40 40 40 continued >> SLRC400_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 99 of 101 SLRC400 NXP Semiconductors ICODE reader IC 9.5.1.2 9.5.1.3 9.5.1.4 9.5.1.5 9.5.1.6 9.5.1.7 9.5.1.8 9.5.2 9.5.2.1 9.5.2.2 9.5.2.3 9.5.2.4 9.5.2.5 9.5.2.6 9.5.2.7 9.5.2.8 9.5.3 9.5.3.1 9.5.3.2 9.5.3.3 9.5.3.4 9.5.3.5 9.5.3.6 9.5.3.7 9.5.3.8 9.5.4 9.5.4.1 9.5.4.2 9.5.4.3 9.5.4.4 9.5.4.5 9.5.4.6 9.5.4.7 9.5.4.8 9.5.5 9.5.5.1 9.5.5.2 9.5.5.3 9.5.5.4 9.5.5.5 9.5.5.6 9.5.5.7 9.5.5.8 9.5.6 9.5.6.1 9.5.6.2 9.5.6.3 9.5.6.4 9.5.6.5 9.5.6.6 9.5.6.7 Command register . . . . . . . . . . . . . . . . . . . . . 40 FIFOData register . . . . . . . . . . . . . . . . . . . . . . 41 PrimaryStatus register . . . . . . . . . . . . . . . . . . 41 FIFOLength register . . . . . . . . . . . . . . . . . . . . 42 SecondaryStatus register . . . . . . . . . . . . . . . . 43 InterruptEn register. . . . . . . . . . . . . . . . . . . . . 43 InterruptRq register. . . . . . . . . . . . . . . . . . . . . 44 Page 1: Control and status . . . . . . . . . . . . . . . 45 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 45 Control register . . . . . . . . . . . . . . . . . . . . . . . . 45 ErrorFlag register . . . . . . . . . . . . . . . . . . . . . . 45 CollPos register . . . . . . . . . . . . . . . . . . . . . . . 46 TimerValue register. . . . . . . . . . . . . . . . . . . . . 46 CRCResultLSB register . . . . . . . . . . . . . . . . . 46 CRCResultMSB register . . . . . . . . . . . . . . . . . 47 BitFraming register . . . . . . . . . . . . . . . . . . . . . 47 Page 2: Transmitter and control . . . . . . . . . . . 48 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 48 TxControl register . . . . . . . . . . . . . . . . . . . . . . 48 CwConductance register . . . . . . . . . . . . . . . . 49 ModConductance register. . . . . . . . . . . . . . . . 49 CoderControl register . . . . . . . . . . . . . . . . . . . 50 ModWidth register. . . . . . . . . . . . . . . . . . . . . . 51 ModWidthSOF register . . . . . . . . . . . . . . . . . . 51 PreSet17 register . . . . . . . . . . . . . . . . . . . . . . 51 Page 3: Receiver and decoder control . . . . . . 51 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 51 RxControl1 register. . . . . . . . . . . . . . . . . . . . . 51 DecoderControl register . . . . . . . . . . . . . . . . . 52 BitPhase register . . . . . . . . . . . . . . . . . . . . . . 53 RxThreshold register . . . . . . . . . . . . . . . . . . . 53 PreSet1D register . . . . . . . . . . . . . . . . . . . . . . 53 RxControl2 register. . . . . . . . . . . . . . . . . . . . . 54 ClockQControl register . . . . . . . . . . . . . . . . . . 54 Page 4: RF Timing and channel redundancy . 55 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 55 RxWait register . . . . . . . . . . . . . . . . . . . . . . . . 55 ChannelRedundancy register . . . . . . . . . . . . . 55 CRCPresetLSB register . . . . . . . . . . . . . . . . . 56 CRCPresetMSB register. . . . . . . . . . . . . . . . . 56 TimeSlotPeriod register . . . . . . . . . . . . . . . . . 57 SIGOUTSelect register . . . . . . . . . . . . . . . . . . 57 PreSet27 register . . . . . . . . . . . . . . . . . . . . . . 58 Page 5: FIFO, timer and IRQ pin configuration 58 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 58 FIFOLevel register . . . . . . . . . . . . . . . . . . . . . 58 TimerClock register. . . . . . . . . . . . . . . . . . . . . 58 TimerControl register . . . . . . . . . . . . . . . . . . . 59 TimerReload register . . . . . . . . . . . . . . . . . . . 59 IRQPinConfig register. . . . . . . . . . . . . . . . . . . 60 PreSet2E register . . . . . . . . . . . . . . . . . . . . . . 60 9.5.6.8 9.5.7 9.5.7.1 9.5.7.2 PreSet2F register. . . . . . . . . . . . . . . . . . . . . . Page 6: reserved . . . . . . . . . . . . . . . . . . . . . . Page register . . . . . . . . . . . . . . . . . . . . . . . . . Reserved registers 31h, 32h, 33h, 34h, 35h, 36h and 37h . . . . . . . . . . . . . . . . . . . . . . 9.5.8 Page 7: Test control . . . . . . . . . . . . . . . . . . . . 9.5.8.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.8.2 Reserved register 39h . . . . . . . . . . . . . . . . . . 9.5.8.3 TestAnaSelect register . . . . . . . . . . . . . . . . . . 9.5.8.4 PreSet3B register. . . . . . . . . . . . . . . . . . . . . . 9.5.8.5 PreSet3C register . . . . . . . . . . . . . . . . . . . . . 9.5.8.6 TestDigiSelect register . . . . . . . . . . . . . . . . . . 9.5.8.7 Reserved registers 3Eh, 3Fh . . . . . . . . . . . . . 10 SLRC400 command set . . . . . . . . . . . . . . . . . 10.1 SLRC400 command overview . . . . . . . . . . . . 10.1.1 Basic states . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 StartUp command 3Fh . . . . . . . . . . . . . . . . . . 10.1.3 Idle command 00h . . . . . . . . . . . . . . . . . . . . . 10.2 Commands for label communication . . . . . . . 10.2.1 Transmit command 1Ah . . . . . . . . . . . . . . . . . 10.2.1.1 Using the Transmit command . . . . . . . . . . . . 10.2.1.2 RF channel redundancy and framing. . . . . . . 10.2.1.3 Transmission of frames with more than 64 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 Receive command 16h . . . . . . . . . . . . . . . . . 10.2.2.1 Using the Receive command . . . . . . . . . . . . . 10.2.2.2 RF channel redundancy and framing. . . . . . . 10.2.2.3 Collision detection . . . . . . . . . . . . . . . . . . . . . 10.2.2.4 Communication errors . . . . . . . . . . . . . . . . . . 10.2.3 Transceive command 1Eh . . . . . . . . . . . . . . . 10.2.4 States of the label communication . . . . . . . . . 10.2.5 Label communication state diagram . . . . . . . 10.3 EEPROM commands. . . . . . . . . . . . . . . . . . . 10.3.1 WriteE2 command 01h . . . . . . . . . . . . . . . . . 10.3.1.1 Programming process . . . . . . . . . . . . . . . . . . 10.3.1.2 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . 10.3.1.3 WriteE2 command error flags . . . . . . . . . . . . 10.3.2 ReadE2 command 03h . . . . . . . . . . . . . . . . . 10.4 Diverse commands . . . . . . . . . . . . . . . . . . . . 10.4.1 LoadConfig command 07h. . . . . . . . . . . . . . . 10.4.1.1 Register assignment . . . . . . . . . . . . . . . . . . . 10.4.1.2 Relevant LoadConfig command error flags . . 10.4.2 CalcCRC command 12h . . . . . . . . . . . . . . . . 10.4.2.1 CRC coprocessor settings . . . . . . . . . . . . . . . 10.4.2.2 CRC coprocessor status flags . . . . . . . . . . . . 10.5 Error handling during command execution . . 11 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 12 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 12.1 Operating conditions . . . . . . . . . . . . . . . . . . . 12.2 Current consumption . . . . . . . . . . . . . . . . . . . 60 60 60 61 61 61 61 61 62 62 62 63 64 64 65 65 66 66 66 66 67 67 68 68 69 69 70 70 71 72 73 73 73 74 74 75 75 75 75 76 76 76 76 77 77 77 77 78 continued >> SLRC400_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved. 100 of 101 SLRC400 NXP Semiconductors ICODE reader IC 12.3 Pin characteristics . . . . . . . . . . . . . . . . . . . . . 12.3.1 Input pin characteristics . . . . . . . . . . . . . . . . . 12.3.2 Digital output pin characteristics . . . . . . . . . . . 12.3.3 Antenna driver output pin characteristics . . . . 12.4 AC electrical characteristics . . . . . . . . . . . . . . 12.4.1 Separate read/write strobe bus timing . . . . . . 12.4.2 Common read/write strobe bus timing . . . . . . 12.4.3 EPP bus timing . . . . . . . . . . . . . . . . . . . . . . . . 12.4.4 Clock frequency . . . . . . . . . . . . . . . . . . . . . . . 13 EEPROM characteristics . . . . . . . . . . . . . . . . . 14 Application information. . . . . . . . . . . . . . . . . . 14.1 Typical application . . . . . . . . . . . . . . . . . . . . . 14.1.1 Circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . 14.1.2 Circuit description . . . . . . . . . . . . . . . . . . . . . . 14.1.2.1 EMC low-pass filter. . . . . . . . . . . . . . . . . . . . . 14.1.2.2 Antenna matching. . . . . . . . . . . . . . . . . . . . . . 14.1.2.3 Receiver circuit . . . . . . . . . . . . . . . . . . . . . . . . 14.1.2.4 Antenna coil . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Test signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.1 Measurements using the serial signal switch . 14.2.2 Analog test signals . . . . . . . . . . . . . . . . . . . . . 14.2.3 Digital test signals. . . . . . . . . . . . . . . . . . . . . . 14.2.4 Examples of analog and digital test signals . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 78 79 79 80 80 81 82 84 84 85 85 85 85 85 86 86 86 87 87 88 88 89 91 92 92 93 94 94 94 94 95 95 96 98 99 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 23 March 2010 054333