Document Number: MPC5566
Rev. 3, September 2012
Freescale
Data Sheet: Technical Data
MPC5566
Microcontroller Data Sheet
This document provides electrical specifications, pin
assignments, and package diagrams for the MPC5566
microcontroller device. For functional characteristics,
refer to the MPC5566 Microcontroller Reference
Manual.
1
Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . 5
3.3 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 EMI (Electromagnetic Interference) Characteristics 8
3.5 ESD (Electromagnetic Static Discharge) Characteristics9
3.6 Voltage Regulator Controller (VRC) and
Power-On Reset (POR) Electrical Specifications9
3.7 Power-Up/Down Sequencing . . . . . . . . . . . . . . . . 10
3.8 DC Electrical Specifications. . . . . . . . . . . . . . . . . . 14
3.9 Oscillator and FMPLL Electrical Characteristics . . 20
3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 22
3.11 H7Fa Flash Memory Electrical Characteristics . . . 23
3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.14 Fast Ethernet AC Timing Specifications . . . . . . . . 46
4
Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.1 MPC5566 416 PBGA Pinout . . . . . . . . . . . . . . . . . 50
4.2 MPC5566 416-Pin Package Dimensions . . . . . . . 53
5
Revision History for the MPC5566 Data Sheet . . . . . . . 55
5.1 Information Changed Between Revisions 2.0 and 3.0
55
5.2 Information Changed Between Revisions 1.0 and 2.0
55
5.3 Information Changed Between Revisions 0.0 and 1.0
57
Overview
The MPC5566 microcontroller (MCU) is a member of
the MPC5500 family of microcontrollers built on the
Power Architectureembedded technology. This family
of parts has many new features coupled with high
performance CMOS technology to provide substantial
reduction of cost per feature and significant performance
improvement over the MPC500 family.
The host processor core of this device complies with the
Power Architecture embedded category that is 100%
user-mode compatible (including floating point library)
with the original PowerPC instruction set.The embedded
architecture enhancements improve the performance in
embedded applications. The core also has additional
instructions, including digital signal processing (DSP)
instructions, beyond the original PowerPC instruction
set.
© Freescale Inc., 2008,2012. All rights reserved.
Overview
The MPC5500 family of parts contains many new features coupled with high performance CMOS
technology to provide significant performance improvement over the MPC565x.
The host processor core of the MPC5566 also includes an instruction set enhancement allowing variable
length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this
enhancement, it is possible to significantly reduce the code size footprint.
The MPC5566 has two levels of memory hierarchy. The fastest accesses are to the 32-kilobytes (KB)
unified cache. The next level in the hierarchy contains the 128-KB on-chip internal SRAM and threemegabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and data.
The external bus interface is designed to support most of the standard memories used with the MPC5xx
family.
The complex input/output timer functions of the MPC5566 are performed by two enhanced time processor
unit (eTPU) engines. Each eTPU engine controls 32 hardware channels, providing a total of 64 hardware
channels. The eTPU has been enhanced over the TPU by providing: 24-bit timers, double-action hardware
channels, variable number of parameters per channel, angle clock hardware, and additional control and
arithmetic instructions. The eTPU is programmed using a high-level programming language.
The less complex timer functions of the MPC5566 are performed by the enhanced modular input/output
system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action, double-action,
pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include
edge-aligned and center-aligned PWM.
Off-chip communication is performed by a suite of serial protocols including controller area networks
(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications
interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of
timer channels and general-purpose input/output (GPIOs) signals.
The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC).s 40-channels.
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset
control are also determined by the SIU. The internal multiplexer submodule provides multiplexing of
eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing.
The Fast Ethernet (FEC) module is a RISC-based controller that supports both 10 and 100 Mbps
Ethernet/IEEE® 802.3 networks and is compatible with three different standard MAC (media access
controller) PHY (physical) interfaces to connect to an external Ethernet bus. The FEC supports the 10 or
100 Mbps MII (media independent interface), and the 10 Mbps-only with a seven-wire interface, which
uses a subset of the MII signals. The upper 16-bits of the 32-bit external bus interface (EBI) are used to
connect to an external Ethernet device. The FEC contains built-in transmit and receive message FIFOs and
DMA support.
MPC5566 Microcontroller Data Sheet, Rev. 3
2
Freescale Semiconductor
Ordering Information
2
Ordering Information
M PC 5566 M ZP 80 R
Qualification status
Core code
Device number
Temperature range
Package identifier
Operating frequency (MHz)
Tape and reel status
Temperature Range
M = –40° C to 125° C
Package Identifier
ZP = 416PBGA SnPb
VR = 416PBGA Pb-free
Operating Frequency
80 = 80 MHz
112 = 112 MHz
132 = 132 MHz
144 = 144 MHz
Note: Not all options are available on all devices. Refer to Table 1.
Tape and Reel Status
R = Tape and reel
(blank) = Trays
Qualification Status
P = Pre qualification
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
Figure 1. MPC5500 Family Part Number Example
Unless noted in this data sheet, all specifications apply from TL to TH.
Table 1. Orderable Part Numbers
Freescale Part
Number1
Speed (MHz)
Package Description
Nominal
Max. 3 (fMAX)
144
147
132
135
112
114
MPC5566MVR80
80
82
MPC5566MZP144
144
147
132
135
112
114
80
82
MPC5566MVR144
MPC5566MVR132
MPC5566MVR112
MPC5566MZP132
MPC5566MZP112
MPC5566MZP80
MPC5566 416 package
Lead-free (PbFree)
MPC5566 416 package
Leaded (SnPb)
Operating Temperature 2
Min. (TL)
Max. (TH)
–40° C
125° C
–40° C
125° C
1
All devices are PPC5566, rather than MPC5566 or SPC5566, until product qualifications are complete. Not all configurations are
available in the PPC parts.
2 The lowest ambient operating temperature is referenced by T ; the highest ambient operating temperature is referenced by T .
L
H
3 Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM).
82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM;
135 MHz parts allow for 132 MHz system clock + 2% FM; and 147 MHz parts allow for 144 MHz system clock + 2% FM.
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
3
Electrical Characteristics
3
Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and
AC timing specifications for the MCU.
3.1
Maximum Ratings
Table 2. Absolute Maximum Ratings 1
Spec
Characteristic
Symbol
Min.
Max.
Unit
1
1.5 V core supply voltage 2
VDD
–0.3
1.7
V
2
Flash program/erase voltage
VPP
–0.3
6.5
V
4
Flash read voltage
VFLASH
–0.3
4.6
V
5
SRAM standby voltage
VSTBY
–0.3
1.7
V
6
Clock synthesizer voltage
VDDSYN
–0.3
4.6
V
7
3.3 V I/O buffer voltage
VDD33
–0.3
4.6
V
8
Voltage regulator control input voltage
VRC33
–0.3
4.6
V
9
Analog supply voltage (reference to VSSA)
VDDA
–0.3
5.5
V
VDDE
–0.3
4.6
V
VDDEH
–0.3
6.5
V
–1.0 5
–1.0 5
6.5 6
4.6 7
V
10
11
12
I/O supply voltage (fast I/O pads)
3
I/O supply voltage (slow and medium I/O pads)
3
4
DC input voltage
VDDEH powered I/O pads
VDDE powered I/O pads
VIN
13
Analog reference high voltage (reference to VRL)
VRH
–0.3
5.5
V
14
VSS to VSSA differential voltage
VSS – VSSA
–0.1
0.1
V
15
VDD to VDDA differential voltage
VDD – VDDA
–VDDA
VDD
V
16
VREF differential voltage
VRH – VRL
–0.3
5.5
V
17
VRH to VDDA differential voltage
VRH – VDDA
–5.5
5.5
V
18
VRL to VSSA differential voltage
VRL – VSSA
–0.3
0.3
V
19
VDDEH to VDDA differential voltage
VDDEH – VDDA
–VDDA
VDDEH
V
20
VDDF to VDD differential voltage
VDDF – VDD
–0.3
0.3
V
21
VRC33 to VDDSYN differential voltage spec has been moved to Table 9 DC Electrical Specifications, Spec 43a.
22
VSSSYN to VSS differential voltage
VSSSYN – VSS
–0.1
0.1
V
23
VRCVSS to VSS differential voltage
VRCVSS – VSS
–0.1
0.1
V
24
Maximum DC digital input current 8
(per pin, applies to all digital pins) 4
IMAXD
–2
2
mA
25
Maximum DC analog input current 9
(per pin, applies to all analog pins)
IMAXA
–3
3
mA
26
Maximum operating temperature range 10
Die junction temperature
TJ
TL
150.0
oC
27
Storage temperature range
TSTG
–55.0
150.0
oC
MPC5566 Microcontroller Data Sheet, Rev. 3
4
Freescale Semiconductor
Electrical Characteristics
Table 2. Absolute Maximum Ratings 1 (continued)
Spec
28
29
Characteristic
Symbol
Min.
Max.
Maximum solder temperature 11
Lead free (Pb-free)
Leaded (SnPb)
TSDR
—
—
260.0
245.0
Moisture sensitivity level 12
MSL
—
3
Unit
o
C
1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,
and functional operation at the maxima is not guaranteed. Stress beyond any of the listed maxima can affect device reliability
or cause permanent damage to the device.
2
1.5 V ± 10% for proper operation. This parameter is specified at a maximum junction temperature of 150 oC.
3
All functional non-supply I/O pins are clamped to VSS and VDDE, or VDDEH.
4
AC signal overshoot and undershoot of up to ± 2.0 V of the input voltages is permitted for an accumulative duration of
60 hours over the complete lifetime of the device (injection current not limited for this duration).
5
Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met. Keep the negative DC
voltage greater than –0.6 V on eTPUB[15] and SINB during the internal power-on reset (POR) state.
6 Internal structures hold the input voltage less than the maximum voltage on all pads powered by V
DDEH supplies, if the
maximum injection current specification is met (2 mA for all pins) and VDDEH is within the operating voltage specifications.
7 Internal structures hold the input voltage less than the maximum voltage on all pads powered by V
DDE supplies, if the maximum
injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications.
8 Total injection current for all pins (including both digital and analog) must not exceed 25 mA.
9 Total injection current for all analog input pins must not exceed 15 mA.
10 Lifetime operation at these specification limits is not guaranteed.
11 Moisture sensitivity profile per IPC/JEDEC J-STD-020D.
12 Moisture sensitivity per JEDEC test method A112.
3.2
Thermal Characteristics
The shaded rows in the following table indicate information specific to a four-layer board.
Table 3. MPC5566 Thermal Characteristics
Spec
1
4
5
6
Unit
RJA
24
°C/W
RJA
16
°C/W
1, 3
3
Junction to ambient (@200 ft./min., one-layer board)
RJMA
18
°C/W
4
Junction to ambient (@200 ft./min., four-layer board 2s2p)
RJMA
13
°C/W
RJB
8
°C/W
RJC
6
°C/W
JT
2
°C/W
7
2
416 PBGA
Junction to ambient, natural convection (four-layer board 2s2p)
6
3
Junction to ambient, natural convection (one-layer board)
Symbol
1, 2
2
5
1
MPC5566 Thermal Characteristic
Junction to board (four-layer board 2s2p)
Junction to case
4
5
Junction to package top, natural convection
6
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other board components, and board thermal resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
5
Electrical Characteristics
3.2.1
General Notes for Specifications at Maximum Junction Temperature
An estimation of the device junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RJA PD)
where:
TA = ambient temperature for the package (oC)
RJA = junction to ambient thermal resistance (oC/W)
PD = power dissipation in the package (W)
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide
consistent values for estimations and comparisons. The difference between the values determined for the
single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground
plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance
depends on the:
• Construction of the application board (number of planes)
• Effective size of the board which cools the component
• Quality of the thermal and electrical connections to the planes
• Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to
connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal
performance. When the clearance between the vias leave the planes virtually disconnected, the thermal
performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly
packed printed circuit board. The value obtained on a board with the internal planes is usually within the
normal range if the application board has:
• One oz. (35 micron nominal thickness) internal planes
• Components are well separated
• Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the surrounding
components. In addition, the ambient temperature varies widely within the application. For many natural
convection and especially closed box applications, the board temperature at the perimeter (edge) of the
package is approximately the same as the local air temperature near the device. Specifying the local
ambient conditions explicitly as the board temperature provides a more precise description of the local
ambient conditions that determine the temperature of the device.
MPC5566 Microcontroller Data Sheet, Rev. 3
6
Freescale Semiconductor
Electrical Characteristics
At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TB + (RJB PD)
where:
TJ = junction temperature (oC)
TB = board temperature at the package perimeter (oC/W)
RJB = junction-to-board thermal resistance (oC/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air does not factor into the calculation, an acceptable value
for the junction temperature is predictable. Ensure the application board is similar to the thermal test
condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a
case-to-ambient thermal resistance:
RJA = RJC + RCA
where:
RJA = junction-to-ambient thermal resistance (oC/W)
RJC = junction-to-case thermal resistance (oC/W)
RCA = case-to-ambient thermal resistance (oC/W)
RJC is device related and is not affected by other factors. The thermal environment can be controlled to
change the case-to-ambient thermal resistance, RCA. For example, change the air flow around the device,
add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal
dissipation on the printed circuit board surrounding the device. This description is most useful for
packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient.
For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal
resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes
when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The
junction-to-board thermal resistance describes the thermal performance when most of the heat is
conducted to the printed circuit board. This model can be used to generate simple estimations and for
computational fluid dynamics (CFD) thermal models.
To determine the junction temperature of the device in the application on a prototype board, use the
thermal characterization parameter (JT) to determine the junction temperature by measuring the
temperature at the top center of the package case using the following equation:
TJ = TT + (JT PD)
where:
TT = thermocouple temperature on top of the package (oC)
JT = thermal characterization parameter (oC/W)
PD = power dissipation in the package (W)
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
7
Electrical Characteristics
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using
a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple
so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple
junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat
against the package case to avoid measurement errors caused by the cooling effects of the thermocouple
wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Rd.
San Jose, CA., 95134
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at
800-854-7179 or 303-397-7956.
JEDEC specifications are available on the web at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive
Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and
Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
3.3
Package
The MPC5566 is available in packaged form. Read the package options in Section 2, “Ordering
Information.” Refer to Section 4, “Mechanicals,” for pinouts and package drawings.
3.4
EMI (Electromagnetic Interference) Characteristics
Table 4. EMI Testing Specifications 1
Spec
Characteristic
Minimum
Typical
Maximum
Unit
0.15
—
1000
MHz
1
Scan range
2
Operating frequency
—
—
fMAX
MHz
3
VDD operating voltages
—
1.5
—
V
4
VDDSYN, VRC33, VDD33, VFLASH, VDDE operating voltages
—
3.3
—
V
5
VPP, VDDEH, VDDA operating voltages
—
5.0
—
V
2
6
Maximum amplitude
—
—
14
32 3
dBuV
7
Operating temperature
—
—
25
oC
1
EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing was performed on the MPC5554
and applied to the MPC5500 family as generic EMI performance data.
2 Measured with the single-chip EMI program.
3 Measured with the expanded EMI program.
MPC5566 Microcontroller Data Sheet, Rev. 3
8
Freescale Semiconductor
Electrical Characteristics
3.5
ESD (Electromagnetic Static Discharge) Characteristics
Table 5. ESD Ratings 1, 2
Characteristic
Symbol
Value
Unit
2000
V
R1
1500
C
100
pF
ESD for human body model (HBM)
HBM circuit description
500 (all pins)
ESD for field induced charge model (FDCM)
V
750 (corner pins)
Number of pulses per pin:
Positive pulses (HBM)
Negative pulses (HBM)
—
—
1
1
—
—
Interval of pulses
—
1
second
1
2
All ESD testing conforms to CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
Device failure is defined as: ‘If after exposure to ESD pulses, the device does not meet the device specification requirements,
which includes the complete DC parametric and functional testing at room temperature and hot temperature.
Voltage Regulator Controller (VRC) and
Power-On Reset (POR) Electrical Specifications
3.6
The following table lists the VRC and POR electrical specifications:
Table 6. VRC and POR Electrical Specifications
Spec
1
Characteristic
3.3 V (VDDSYN) POR
3
RESET pin supply
(VDDEH6) POR 1, 2
1
VRC33 voltage
6
Current can be sourced
7
Max.
Units
VPOR15
1.1
1.1
1.35
1.35
V
Asserted (ramp up)
Negated (ramp up)
Asserted (ramp down)
Negated (ramp down)
VPOR33
0.0
2.0
2.0
0.0
0.30
2.85
2.85
0.30
V
Negated (ramp up)
Asserted (ramp down)
VPOR5
2.0
2.0
2.85
2.85
V
VTRANS_START
1.0
2.0
V
When VRC allows the pass
transistor to completely turn on 3, 4
VTRANS_ON
2.0
2.85
V
When the voltage is greater than
the voltage at which the VRC keeps
the 1.5 V supply in regulation 5, 6
VVRC33REG
3.0
—
V
11.0
—
mA
9.0
—
mA
7.5
—
mA
—
1.0
V
Before VRC allows the pass
transistor to start turning on
4
5
Min.
Negated (ramp up)
Asserted (ramp down)
1.5 V (VDD) POR 1
2
Symbol
by VRCCTL at Tj:
–40o C
o
25 C
150o
8
IVRCCTL
7
C
Voltage differential during power up such that:
VDD33 can lag VDDSYN or VDDEH6 before VDDSYN and VDDEH6 reach the
VPOR33 and VPOR5 minimums respectively.
VDD33_LAG
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
9
Electrical Characteristics
Table 6. VRC and POR Electrical Specifications (continued)
Spec
9
Characteristic
Absolute value of slew rate on power supply pins
Symbol
Min.
Max.
Units
—
—
50
V/ms
60
—
—
65
—
—
85
500
—
o
10
Required gain at Tj:
– 40 C
IDD IVRCCTL (@ fsys = fMAX) 6, 7, 8, 9
25o C
150o C
BETA
10
1
The internal POR signals are VPOR15, VPOR33, and VPOR5. On power up, assert RESET before the internal POR negates.
RESET must remain asserted until the power supplies are within the operating conditions as specified in Table 9 DC Electrical
Specifications. On power down, assert RESET before any power supplies fall outside the operating conditions and until the
internal POR asserts.
2
VIL_S (Table 9, Spec15) is guaranteed to scale with VDDEH6 down to VPOR5.
3
Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.
4
It is possible to reach the current limit during ramp up—do not treat this event as short circuit current.
5 At peak current for device.
6 Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal
traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass
transistor to the VDD package signals must have a maximum of 100 nH inductance and minimal resistance
(less than 1 ). VRCCTL must have a nominal 1 F phase compensation capacitor to ground. VDD must have a 20 F (nominal)
bulk capacitor (greater than 4 F over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of
eight 0.01 F, two 0.1 F, and one 1 F capacitors around the package on the VDD supply signals.
7 I
VRCCTL is measured at the following conditions: VDD = 1.35 V, VRC33 = 3.1 V, VVRCCTL = 2.2 V.
8 Refer to Table 1 for the maximum operating frequency.
9 Values are based on I
DD from high-use applications as explained in the IDD Electrical Specification.
10 BETA represents the worst-case external transistor. It is measured on a per-part basis and calculated as (I
DD IVRCCTL).
3.7
Power-Up/Down Sequencing
Power sequencing between the 1.5 V power supply and VDDSYN or the RESET power supplies is required
if using an external 1.5 V power supply with VRC33 tied to ground (GND). To avoid power-sequencing,
VRC33 must be powered up within the specified operating range, even if the on-chip voltage regulator
controller is not used. Refer to Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),” and
Section 3.7.3, “Power-Down Sequence (VRC33 Grounded).”
Power sequencing requires that VDD33 must reach a certain voltage where the values are read as ones
before the POR signal negates. Refer to Section 3.7.1, “Input Value of Pins During POR Dependent on
VDD33.”
Although power sequencing is not required between VRC33 and VDDSYN during power up, VRC33 must
not lead VDDSYN by more than 600 mV or lag by more than 100 mV for the VRC stage turn-on to operate
within specification. Higher spikes in the emitter current of the pass transistor occur if VRC33 leads or lags
VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power
supply circuitry and the amount of board level capacitance.
Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase
of the current consumed by VRC33. If VRC33 lags VDDSYN by more than 100 mV, the increase in current
consumed can drop VDD low enough to assert the 1.5 V POR again. Oscillations are possible when the
MPC5566 Microcontroller Data Sheet, Rev. 3
10
Freescale Semiconductor
Electrical Characteristics
1.5 V POR asserts and stops the system clock, causing the voltage on VDD to rise until the 1.5 V POR
negates again. All oscillations stop when VRC33 is powered sufficiently.
When powering down, VRC33 and VDDSYN have no delta requirement to each other, because the bypass
capacitors internal and external to the device are already charged. When not powering up or down, no delta
between VRC33 and VDDSYN is required for the VRC to operate within specification.
There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current
spikes, and so on. Therefore, the state of the I/O pins during power up and power down varies depending
on which supplies are powered.
Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type).
Table 7. Pin Status for Fast Pads During the Power Sequence
VDDE
VDD33
VDD
POR
Pin Status for Fast Pad Output Driver
pad_fc (fast)
Low
—
—
Asserted
Low
VDDE
Low
Low
Asserted
High
VDDE
Low
VDD
Asserted
High
VDDE
VDD33
Low
Asserted
High impedance (Hi-Z)
VDDE
VDD33
VDD
Asserted
Hi-Z
VDDE
VDD33
VDD
Negated
Functional
Table 8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and
pad_sh (slow type).
Table 8. Pin Status for Medium and Slow Pads During the Power Sequence
VDDEH
VDD
POR
Pin Status for Medium and Slow Pad Output Driver
pad_mh (medium) pad_sh (slow)
Low
—
Asserted
Low
VDDEH
Low
Asserted
High impedance (Hi-Z)
VDDEH
VDD
Asserted
Hi-Z
VDDEH
VDD
Negated
Functional
The values in Table 7 and Table 8 do not include the effect of the weak-pull devices on the output pins
during power up.
Before exiting the internal POR state, the voltage on the pins go to a high-impedance state until POR
negates. When the internal POR negates, the functional state of the signal during reset applies and the
weak-pull devices
(up or down) are enabled as defined in the device reference manual. If VDD is too low to correctly
propagate the logic signals, the weak-pull devices can pull the signals to VDDE and VDDEH.
To avoid this condition, minimize the ramp time of the VDD supply to a time period less than the time
required to enable the external circuitry connected to the device outputs.
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
11
Electrical Characteristics
During initial power ramp-up, when Vstby is 0.6v or above. a typical current of 1-3mA and maximum of
4mA may be seen until VDD is applied. This current will not reoccur until Vstby is lowered below Vstby
min. specification.
Figure 2 shows an approximate interpolation of the ISTBY worst-case specification to estimate values at
different voltages and temperatures. The vertical lines shown at 25 C, 60 C, and 150 C in Figure 2 are
the actual IDD_STBY specifications (27d) listed in Table 9.
Figure 2. fISTBY Worst-case Specifications
MPC5566 Microcontroller Data Sheet, Rev. 3
12
Freescale Semiconductor
Electrical Characteristics
3.7.1
Input Value of Pins During POR Dependent on VDD33
When powering up the device, VDD33 must not lag the latest VDDSYN or RESET power pin (VDDEH6) by
more than the VDD33 lag specification listed in Table 6, spec 8. This avoids accidentally selecting the
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power
pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification
applies during power up only. VDD33 has no lead or lag requirements when powering down.
3.7.2
Power-Up Sequence (VRC33 Grounded)
The 1.5 V VDD power supply must rise to 1.35 V before the 3.3 V VDDSYN power supply and the RESET
power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does
not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V
POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since
they can negate as low as 2.0 V, VDD must be within specification before the 3.3 V POR and the RESET
POR negate.
VDDSYN and RESET Power
VDD
2.0 V
1.35 V
VDD must reach 1.35 V before VDDSYN and the RESET power reach 2.0 V
Figure 3. Power-Up Sequence (VRC33 Grounded)
3.7.3
Power-Down Sequence (VRC33 Grounded)
The only requirement for the power-down sequence with VRC33 grounded is if VDD decreases to less than
its operating range, VDDSYN or the RESET power must decrease to less than 2.0 V before the VDD power
increases to its operating range. This ensures that the digital 1.5 V logic, which is reset only by an ORed
POR and can cause the 1.5 V supply to decrease less than its specification value, resets correctly. See
Table 6, footnote 1.
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
13
Electrical Characteristics
3.8
DC Electrical Specifications
Table 9. DC Electrical Specifications (TA = TL to TH)
Spec
1
Characteristic
Core supply voltage (average DC RMS voltage)
1
Symbol
Min
Max.
Unit
VDD
1.35
1.65
V
VDDE
1.62
3.6
V
2
Input/output supply voltage (fast input/output)
3
Input/output supply voltage (slow and medium input/output)
VDDEH
3.0
5.25
V
4
3.3 V input/output buffer voltage
VDD33
3.0
3.6
V
5
Voltage regulator control input voltage
VRC33
3.0
3.6
V
VDDA
4.5
5.25
V
VPP
4.5
5.25
V
2
6
Analog supply voltage
8
Flash programming voltage 3
9
Flash read voltage
VFLASH
3.0
3.6
V
10
SRAM standby voltage 4
VSTBY
0.8
1.2
V
11
Clock synthesizer operating voltage
VDDSYN
3.0
3.6
V
12
Fast I/O input high voltage
VIH_F
0.65 VDDE
VDDE + 0.3
V
13
Fast I/O input low voltage
VIL_F
VSS – 0.3
0.35 VDDE
V
14
Medium and slow I/O input high voltage
VIH_S
0.65 VDDEH
VDDEH + 0.3
V
15
Medium and slow I/O input low voltage
VIL_S
VSS – 0.3
0.35 VDDEH
V
16
Fast input hysteresis
VHYS_F
0.1 VDDE
V
17
Medium and slow I/O input hysteresis
VHYS_S
0.1 VDDEH
V
18
Analog input voltage
VINDC
VSSA – 0.3
VDDA + 0.3
V
19
Fast output high voltage (IOH_F = –2.0 mA)
VOH_F
0.8 VDDE
—
V
20
Slow and medium output high voltage
IOH_S = –2.0 mA
IOH_S = –1.0 mA
VOH_S
0.80 VDDEH
0.85 VDDEH
—
V
21
Fast output low voltage (IOL_F = 2.0 mA)
VOL_F
—
0.2 VDDE
V
22
Slow and medium output low voltage
IOL_S = 2.0 mA
IOL_S = 1.0 mA
VOL_S
—
Load capacitance (fast I/O) 5
DSC (SIU_PCR[8:9]) = 0b00
= 0b01
= 0b10
= 0b11
CL
24
Input capacitance (digital pins)
25
26
23
V
0.20 VDDEH
0.15 VDDEH
—
—
—
—
10
20
30
50
pF
pF
pF
pF
CIN
—
7
pF
Input capacitance (analog pins)
CIN_A
—
10
pF
Input capacitance:
(Shared digital and analog pins AN[12]_MA[0]_SDS,
AN[13]_MA[1]_SDO, AN[14]_MA[2]_SDI, and AN[15]_FCK)
CIN_M
—
12
pF
MPC5566 Microcontroller Data Sheet, Rev. 3
14
Freescale Semiconductor
Electrical Characteristics
Table 9. DC Electrical Specifications (TA = TL to TH) (continued)
Spec
Characteristic
Symbol
Min
Max.
Unit
IDD
IDD
IDD
IDD
—
—
—
—
650
530
820
650
mA
mA
mA
mA
IDD
IDD
—
—
750
585
mA
mA
IDD
IDD
IDD
IDD
—
—
—
—
630
500
785
630
mA
mA
mA
mA
IDD
IDD
—
—
710
550
mA
mA
IDD
IDD
IDD
IDD
—
—
—
—
600
450
680
500
mA
mA
mA
mA
IDD
IDD
—
—
650
490
mA
mA
IDD
IDD
IDD
IDD
—
—
—
—
490
360
545
400
mA
mA
mA
mA
IDD
IDD
—
—
530
395
mA
mA
27d RAM standby current.12
IDD_STBY @ 25o C
VSTBY @ 0.8 V
VSTBY @ 1.0 V
VSTBY @ 1.2 V
IDD_STBY
IDD_STBY
IDD_STBY
—
—
—
20
30
50
A
A
A
IDD_STBY @ 60o C
VSTBY @ 0.8 V
VSTBY @ 1.0 V
VSTBY @ 1.2 V
IDD_STBY
IDD_STBY
IDD_STBY
—
—
—
70
100
200
A
A
A
IDD_STBY @ 150o C (Tj)
VSTBY @ 0.8 V
VSTBY @ 1.0 V
VSTBY @ 1.2 V
IDD_STBY
IDD_STBY
IDD_STBY
—
—
—
1200
1500
2000
A
A
A
27e Operating current 1.5 V supplies @ 147 MHz: 6
8-way cache 7
VDD (including VDDF max current) @1.65 V typical use 8, 9
VDD (including VDDF max current) @1.35 V typical use 8, 9
VDD (including VDDF max current) @1.65 V high use 9, 10
VDD (including VDDF max current) @1.35 V high use 9, 10
4-way cache 11
VDD (including VDDF max current) @1.65 V high use 9, 10
VDD (including VDDF max current) @1.35 V high use 9, 10
27a Operating current 1.5 V supplies @ 135 MHz: 6
8-way cache 7
VDD (including VDDF max current) @1.65 V typical use 8, 9
VDD (including VDDF max current) @1.35 V typical use 8, 9
VDD (including VDDF max current) @1.65 V high use 9, 10
VDD (including VDDF max current) @1.35 V high use 9, 10
4-way cache 11
VDD (including VDDF max current) @1.65 V high use 9, 10
VDD (including VDDF max current) @1.35 V high use 9, 10
27b Operating current 1.5 V supplies @ 114 MHz: 6
8-way cache 7
VDD (including VDDF max current) @1.65 V typical use 8, 9
VDD (including VDDF max current) @1.35 V typical use 8, 9
VDD (including VDDF max current) @1.65 V high use 9, 10
VDD (including VDDF max current) @1.35 V high use 9, 10
4-way cache 11
VDD (including VDDF max current) @1.65 V high use 9, 10
VDD (including VDDF max current) @1.35 V high use 9, 10
27c Operating current 1.5 V supplies @ 82 MHz: 6
8-way cache 7
VDD (including VDDF max current) @1.65 V typical use 8, 9
VDD (including VDDF max current) @1.35 V typical use 8, 9
VDD (including VDDF max current) @1.65 V high use 9, 10
VDD (including VDDF max current) @1.35 V high use 9, 10
4-way cache 11
VDD (including VDDF max current) @1.65 V high use 9, 10
VDD (including VDDF max current) @1.35 V high use 9, 10
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
15
Electrical Characteristics
Table 9. DC Electrical Specifications (TA = TL to TH) (continued)
Spec
28
29
30
31
Characteristic
Symbol
Min
Max.
Unit
VDD33 13
IDD_33
—
2 + (values
derived from
procedure of
footnote 13)
mA
VFLASH
IVFLASH
—
10
mA
VDDSYN
IDDSYN
—
15
mA
Operating current 5.0 V supplies (12 MHz ADCLK):
VDDA (VDDA0 + VDDA1)
Analog reference supply current (VRH, VRL)
VPP
IDD_A
IREF
IPP
—
—
—
20.0
1.0
25.0
mA
mA
mA
Operating current VDDE supplies: 14
VDDEH1
VDDE2
VDDE3
VDDEH4
VDDE5
VDDEH6
VDDE7
VDDEH8
VDDEH9
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
IDD9
—
—
—
—
—
—
—
—
—
Refer to
footnote 14
mA
mA
mA
mA
mA
mA
mA
mA
mA
10
20
20
110
130
170
A
A
A
10
20
20
100
130
170
A
A
A
IACT_S
10
20
150
170
A
A
IINACT_D
–2.5
2.5
A
IIC
–2.0
2.0
mA
IINACT_A
–150
150
nA
IINACT_AD
–2.5
2.5
A
VSS – VSSA
–100
100
mV
VRL
VSSA – 0.1
VSSA + 0.1
V
VRL – VSSA
–100
100
mV
VRH
VDDA – 0.1
VDDA + 0.1
V
VRH – VRL
4.5
5.25
V
Operating current 3.3 V supplies @ fMAX MHz
Fast I/O weak pullup current 15
1.62–1.98 V
2.25–2.75 V
3.00–3.60 V
IACT_F
Fast I/O weak pulldown current 15
1.62–1.98 V
2.25–2.75 V
3.00–3.60 V
32
Slow and medium I/O weak pullup/down current 15
3.0–3.6 V
4.5–5.5 V
33
I/O input leakage current 16
34
DC injection current (per pin)
35
Analog input current, channel off
17
35a Analog input current, shared analog / digital pins
(AN[12], AN[13], AN[14], AN[15])
36
VSS to VSSA differential voltage 18
37
Analog reference low voltage
38
VRL differential voltage
39
Analog reference high voltage
40
VREF differential voltage
MPC5566 Microcontroller Data Sheet, Rev. 3
16
Freescale Semiconductor
Electrical Characteristics
Table 9. DC Electrical Specifications (TA = TL to TH) (continued)
Spec
Characteristic
Symbol
Min
Max.
Unit
41
VSSSYN to VSS differential voltage
VSSSYN – VSS
–50
50
mV
42
VRCVSS to VSS differential voltage
VRCVSS – VSS
–50
50
mV
43
VDDF to VDD differential voltage
VDDF – VDD
–100
100
mV
43a VRC33 to VDDSYN differential voltage
VRC33 – VDDSYN
–0.1
0.1 19
V
VIDIFF
–2.5
2.5
V
TA = (TL to TH)
TL
TH
C
—
—
50
V/ms
44
Analog input differential signal range (with common mode 2.5 V)
45
Operating temperature range, ambient (packaged)
46
Slew rate on power-supply pins
1
VDDE2 and VDDE3 are limited to 2.25–3.6 V only if SIU_ECCR[EBTS] = 0; VDDE2 and VDDE3 have a range of 1.6–3.6 V if
SIU_ECCR[EBTS] = 1.
2
| VDDA0 – VDDA1 | must be < 0.1 V.
3 V
PP can drop to 3.0 V during read operations.
4 If standby operation is not required, connect V
STBY to ground.
5 Applies to CLKOUT, external bus pins, and Nexus pins.
6 Maximum average RMS DC current.
7 Eight-way cache enabled (L1CSR0[CORG] = 0b0).
8 Average current measured on automotive benchmark.
9 Peak currents can be higher on specialized code.
10 High use current measured while running optimized SPE assembly code with all code and data 100% locked in cache
(0% miss rate) with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously from
SRAM to SRAM. Higher currents are possible if an ‘idle’ loop that crosses cache lines is run from cache. Write code to avoid this
condition.
11 Four-way cache enabled (L1CSR0[CORG] = 0b1) or (L1CSR0[CORG] = 0b0 with L1CSR0[WAM] = 0b1, L1CSR0[WID] = 0b1111,
L1CSR0[WDD] = 0b1111, L1CSR0[AWID] = 0b1, and L1CSR0[AWDD] = 0b1).
12 The current specification relates to average standby operation after SRAM has been loaded with data. For power up current see
Section 3.7, “Power-Up/Down Sequencing”, Figure 2.
13 Power requirements for the V
DD33 supply depend on the frequency of operation, load of all I/O pins, and the voltages on the I/O
segments. Refer to Table 11 for values to calculate the power dissipation for a specific operation.
14 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O
segment, and the voltage of the I/O segment. Refer to Table 10 for values to calculate power dissipation for specific operation. The
total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment.
15 Absolute value of current, measured at V and V .
IL
IH
16 Weak pullup/down inactive. Measured at V
=
DDE 3.6 V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh.
17
Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 oC
to 12 oC, in the ambient temperature range of 50 oC to 125 oC. Applies to pad types: pad_a and pad_ae.
18
VSSA refers to both VSSA0 and VSSA1. | VSSA0 – VSSA1 | must be < 0.1 V.
19
Up to 0.6 V during power up and power down.
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
17
Electrical Characteristics
3.8.1
I/O Pad Current Specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The
power consumption is the sum of all output pin currents for a segment. The output pin current can be
calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to
calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in
Table 10.
Table 10. I/O Pad Average DC Current (TA = TL to TH)1
Frequency
(MHz)
Load2 (pF)
Voltage (V)
Drive Select /
Slew Rate
Control Setting
Current (mA)
25
50
5.25
11
8.0
10
50
5.25
01
3.2
2
50
5.25
00
0.7
4
2
200
5.25
00
2.4
5
50
50
5.25
11
17.3
Spec
Pad Type
Symbol
1
2
3
6
Slow
IDRV_SH
20
50
5.25
01
6.5
3.33
50
5.25
00
1.1
8
3.33
200
5.25
00
3.9
9
66
10
3.6
00
2.8
7
Medium
IDRV_MH
10
66
20
3.6
01
5.2
11
66
30
3.6
10
8.5
12
66
50
3.6
11
11.0
13
66
10
1.98
00
1.6
14
66
20
1.98
01
2.9
15
66
30
1.98
10
4.2
16
66
50
1.98
11
6.7
17
56
10
3.6
00
2.4
18
56
20
3.6
01
4.4
19
56
30
3.6
10
7.2
20
56
50
3.6
11
9.3
56
10
1.98
00
1.3
22
56
20
1.98
01
2.5
23
56
30
1.98
10
3.5
24
56
50
1.98
11
5.7
25
40
10
3.6
00
1.7
26
40
20
3.6
01
3.1
27
40
30
3.6
10
5.1
21
Fast
IDRV_FC
28
40
50
3.6
11
6.6
29
40
10
1.98
00
1.0
30
40
20
1.98
01
1.8
31
40
30
1.98
10
2.5
32
40
50
1.98
11
4.0
1
These values are estimates from simulation and are not tested. Currents apply to output pins only.
2
All loads are lumped.
MPC5566 Microcontroller Data Sheet, Rev. 3
18
Freescale Semiconductor
Electrical Characteristics
3.8.2
I/O Pad VDD33 Current Specifications
The power consumption of the VDD33 supply dependents on the usage of the pins on all I/O segments. The
power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The output
pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all fast
(pad_fc) pins. The input pin VDD33 current can be calculated from Table 11 based on the voltage,
frequency, and load on all pad_sh and pad_mh pins. Use linear scaling to calculate pin currents for voltage,
frequency, and load parameters that fall outside the values given in Table 11.
Table 11. VDD33 Pad Average DC Current (TA = TL to TH) 1
Spec
Pad Type
Symbol
Frequency
(MHz)
Load 2
(pF)
VDD33
(V)
VDDE
(V)
Drive
Select
Current
(mA)
Inputs
1
Slow
I33_SH
66
0.5
3.6
5.5
NA
0.003
2
Medium
I33_MH
66
0.5
3.6
5.5
NA
0.003
3
66
10
3.6
3.6
00
0.35
4
66
20
3.6
3.6
01
0.53
5
66
30
3.6
3.6
10
0.62
6
66
50
3.6
3.6
11
0.79
7
66
10
3.6
1.98
00
0.35
8
66
20
3.6
1.98
01
0.44
9
66
30
3.6
1.98
10
0.53
10
66
50
3.6
1.98
11
0.70
11
56
10
3.6
3.6
00
0.30
12
56
20
3.6
3.6
01
0.45
13
56
30
3.6
3.6
10
0.52
Outputs
14
56
50
3.6
3.6
11
0.67
56
10
3.6
1.98
00
0.30
16
56
20
3.6
1.98
01
0.37
17
56
30
3.6
1.98
10
0.45
18
56
50
3.6
1.98
11
0.60
19
40
10
3.6
3.6
00
0.21
20
40
20
3.6
3.6
01
0.31
21
40
30
3.6
3.6
10
0.37
15
Fast
I33_FC
22
40
50
3.6
3.6
11
0.48
23
40
10
3.6
1.98
00
0.21
24
40
20
3.6
1.98
01
0.27
25
40
30
3.6
1.98
10
0.32
26
40
50
3.6
1.98
11
0.42
1
These values are estimated from simulation and not tested. Currents apply to output pins for the fast pads only and to input
pins for the slow and medium pads only.
2
All loads are lumped.
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
19
Electrical Characteristics
3.9
Oscillator and FMPLL Electrical Characteristics
Table 12. FMPLL Electrical Specifications
(VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH)
Spec
Characteristic
Symbol
Minimum
Maximum
1
PLL reference frequency range: 1
Crystal reference
External reference
Dual controller (1:1 mode)
fref_crystal
fref_ext
fref_1:1
8
8
24
20
20
fsys 2
2
System frequency 2
fsys
fICO(MIN) 2RFD
fMAX 3
MHz
3
System clock period
tCYC
—
1 fsys
ns
4
Loss of reference frequency 4
fLOR
100
1000
kHz
5
Self-clocked mode (SCM) frequency 5
fSCM
7.4
17.5
MHz
EXTAL input high voltage crystal mode 6
VIHEXT
VXTAL + 0.4 V
—
V
All other modes
[dual controller (1:1), bypass, external reference]
VIHEXT
(VDDE5 2) + 0.4 V
—
V
EXTAL input low voltage crystal mode 7
VILEXT
—
VXTAL – 0.4 V
V
All other modes
[dual controller (1:1), bypass, external reference]
VILEXT
—
(VDDE5 2) – 0.4 V
V
IXTAL
2
6
mA
6
7
Unit
MHz
8
XTAL current 8
9
Total on-chip stray capacitance on XTAL
CS_XTAL
—
1.5
pF
10
Total on-chip stray capacitance on EXTAL
CS_EXTAL
—
1.5
pF
11
Crystal manufacturer’s recommended capacitive
load
CL
Refer to crystal
specification
Refer to crystal
specification
pF
Discrete load capacitance to connect to EXTAL
CL_EXTAL
—
(2 CL) – CS_EXTAL
– CPCB_EXTAL 9
pF
Discrete load capacitance to connect to XTAL
CL_XTAL
—
(2 CL) – CS_XTAL
– CPCB_XTAL 9
pF
tlpll
—
750
s
tskew
–2
2
ns
12
13
14
PLL lock time 10
15
Dual controller (1:1) clock skew
(between CLKOUT and EXTAL) 11, 12
16
Duty cycle of reference
tDC
40
60
%
17
Frequency unLOCK range
fUL
–4.0
4.0
% fSYS
18
Frequency LOCK range
fLCK
–2.0
2.0
% fSYS
MPC5566 Microcontroller Data Sheet, Rev. 3
20
Freescale Semiconductor
Electrical Characteristics
Table 12. FMPLL Electrical Specifications (continued)
(VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH)
Spec
Characteristic
Symbol
Minimum
Maximum
19
CLKOUT period jitter, measured at fSYS max: 13, 14
Peak-to-peak jitter (clock edge to clock edge)
Long term jitter (averaged over a 2 ms interval)
CJITTER
20
Frequency modulation range limit 15
(do not exceed fsys maximum)
21
ICO frequency
fico = [fref_crystal (MFD + 4)] (PREDIV + 1) 16
fico = [fref_ext (MFD + 4)] (PREDIV + 1)
22
Predivider output frequency (to PLL)
Unit
—
—
5.0
0.01
CMOD
0.8
2.4
%fSYS
fico
48
fMAX
MHz
fPREDIV
4
20 17
MHz
%
fCLKOUT
1
Nominal crystal and external reference values are worst-case not more than 1%. The device operates correctly if the frequency
remains within ± 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.
2 All internal registers retain data at 0 Hz.
3 Up to the maximum frequency rating of the device (refer to Table 1).
4 Loss of reference frequency is defined as the reference frequency detected internally, which transitions the PLL into self-clocked
mode.
5 The PLL operates at self-clocked mode (SCM) frequency when the reference frequency falls below f
LOR. SCM frequency is
measured on the CLKOUT ball with the divider set to divide-by-two of the system clock.
NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed.
6 Use the EXTAL input high voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (Vextal – Vxtal) must be 400 mV for the oscillator’s comparator to produce the output clock.
7 Use the EXTAL input low voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (Vxtal – Vextal) must be 400 mV for the oscillator’s comparator to produce the output clock.
8 I
xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
9 C
PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
10 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time also includes the crystal
startup time.
11 PLL is operating in 1:1 PLL mode.
12 V
DDE = 3.0–3.6 V.
13 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f .
sys
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage
for a given interval. CLKOUT divider is set to divide-by-two.
14 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod).
15 Modulation depth selected must not result in f
sys value greater than the fsys maximum specified value.
16 f
RFD).
sys = fico (2
17
Maximum value for dual controller (1:1) mode is (fMAX 2) with the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
21
Electrical Characteristics
3.10
eQADC Electrical Characteristics
Table 13. eQADC Conversion Specifications (TA = TL to TH)
Spec
Characteristic
Symbol
Minimum
Maximum
Unit
FADCLK
1
12
MHz
13 + 2 (15)
14 + 2 (16)
13 + 128 (141)
14 + 128 (142)
1
ADC clock (ADCLK) frequency 1
Conversion cycles
Differential
Single ended
CC
2
3
Stop mode recovery time 2
TSR
10
—
s
—
1.25
—
mV
3
ADCLK
cycles
4
Resolution
5
INL: 6 MHz ADC clock
INL6
–4
4
Counts 3
6
INL: 12 MHz ADC clock
INL12
–8
7
8
9
10
DNL: 6 MHz ADC clock
DNL: 12 MHz ADC clock
Offset error with calibration
Full-scale gain error with calibration
7, 8, 9, 10
8
Counts
DNL6
–3
4
34
Counts
DNL12
–6 4
6
4
Counts
OFFWC
–4 5
4
5
Counts
GAINWC
–8 6
8
6
Counts
IINJ
–1
1
mA
11
Disruptive input injection current
12
Incremental error due to injection current. All channels are
10 k < Rs