NXP Semiconductors
Data Sheet: Technical Data
Document Number: MPC5604BC
Rev. 15, 10/2021
MPC5604B/C
MPC5604B/C
Microcontroller Data Sheet
208 MAPBGA (17 x 17 x 1.7 mm)
100 LQFP (14 x 14 x 1.4 mm)
Features
• Single issue, 32-bit CPU core complex (e200z0)
– Compliant with the Power Architecture® embedded
category
– Includes an instruction set enhancement allowing
variable length encoding (VLE) for code size footprint
reduction. With the optional encoding of mixed 16-bit
and 32-bit instructions, it is possible to achieve
significant code size footprint reduction.
• Up to 512 KB on-chip code flash supported with the flash
controller and ECC
• 64 (4 × 16) KB on-chip data flash memory with ECC
• Up to 48 KB on-chip SRAM with ECC
• Memory protection unit (MPU) with 8 region descriptors
and 32-byte region granularity
• Interrupt controller (INTC) with 148 interrupt vectors,
including 16 external interrupt sources and 18 external
interrupt/wakeup sources
• Frequency modulated phase-locked loop (FMPLL)
• Crossbar switch architecture for concurrent access to
peripherals, flash memory, or RAM from multiple bus
masters
• Boot assist module (BAM) supports internal flash
programming via a serial link (CAN or SCI)
• Timer supports input/output channels providing a range of
16-bit input capture, output compare, and pulse width
modulation functions (eMIOS-lite)
• 10-bit analog-to-digital converter (ADC)
• 3 serial peripheral interface (DSPI) modules
• Up to 4 serial communication interface (LINFlex)
modules
144 LQFP (20 x 20 x 1.4 mm)
64 LQFP (10 x 10 x 1.4 mm)
• Up to 6 enhanced full CAN (FlexCAN) modules with
configurable buffers
• 1 inter IC communication interface (I2C) module
• Up to 123 configurable general purpose pins supporting
input and output operations (package dependent)
• Real Time Counter (RTC) with clock source from128 kHz
or 16 MHz internal RC oscillator supporting autonomous
wakeup with 1 ms resolution with max timeout of 2
seconds
• Up to 6 periodic interrupt timers (PIT) with 32-bit counter
resolution
• 1 System Module Timer (STM)
• Nexus development interface (NDI) per IEEE-ISTO
5001-2003 Class Two Plus standard
• Device/board boundary Scan testing supported with per
Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)
• On-chip voltage regulator (VREG) for regulation of
input supply for all internal levels
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .7
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2 Pad configuration during reset phases . . . . . . . . . . . . .11
2.3 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.4 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.5 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.6 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.7 Nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . .31
2.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.10 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .31
2.11 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.11.1 NVUSRO[PAD3V5V] field description . . . . . . . .32
2.11.2 NVUSRO[OSCILLATOR_MARGIN] field description
32
2.11.3 NVUSRO[WATCHDOG_EN] field description . .32
2.12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .33
2.13 Recommended operating conditions . . . . . . . . . . . . . .34
2.14 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .36
2.14.1 Package thermal characteristics . . . . . . . . . . . .36
2.14.2 Power considerations. . . . . . . . . . . . . . . . . . . . .37
2.15 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . .37
2.15.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.15.2 I/O input DC characteristics . . . . . . . . . . . . . . . .38
2.15.3 I/O output DC characteristics. . . . . . . . . . . . . . .39
2.15.4 Output pin transition times . . . . . . . . . . . . . . . . .42
2.15.5 I/O pad current specification . . . . . . . . . . . . . . .42
2.16 RESET electrical characteristics. . . . . . . . . . . . . . . . . .48
2.17 Power management electrical characteristics. . . . . . . .51
2.17.1 Voltage regulator electrical characteristics . . . .51
2.17.2 Low voltage detector electrical characteristics .56
2.18 Power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.19 Flash memory electrical characteristics . . . . . . . . . . . .59
2.20
2.21
2.22
2.23
2.24
2.25
3
4
5
2.19.1 Program/Erase characteristics . . . . . . . . . . . . . 59
2.19.2 Flash power supply DC characteristics . . . . . . 60
2.19.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 61
Electromagnetic compatibility (EMC) characteristics. . 61
2.20.1 Designing hardened software to avoid noise
problems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.20.2 Electromagnetic interference (EMI) . . . . . . . . . 62
2.20.3 Absolute maximum ratings (electrical sensitivity)62
Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Slow external crystal oscillator (32 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 68
Fast internal RC oscillator (16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Slow internal RC oscillator (128 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.26 ADC electrical characteristics . . . . . . . . . . . . . . . . . . .
2.26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.26.2 Input impedance and ADC accuracy . . . . . . . .
2.26.3 ADC electrical characteristics . . . . . . . . . . . . .
2.27 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.27.1 Current consumption . . . . . . . . . . . . . . . . . . . .
2.27.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . .
2.27.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . .
2.27.4 JTAG characteristics. . . . . . . . . . . . . . . . . . . . .
Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . .
3.1.1 64 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 100 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3 144 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4 208 MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
72
72
77
79
79
80
86
87
88
88
89
92
95
97
99
99
MPC5604B/C Microcontroller Data Sheet, Rev. 15
2
NXP Semiconductors
3
Introduction
1.1
Document overview
This document describes the features of the family and options available within the family members, and highlights important electrical and physical
characteristics of the device. To ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet.
1.2
Description
The MPC5604B/C is a family of next generation microcontrollers built on the Power Architecture® embedded category.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
The MPC5604B/C family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family
of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. The advanced and cost-efficient host
processor core of this automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length
encoding) APU, providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power
consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating
systems and configuration code to assist with users implementations.
Table 1. MPC5604B/C device comparison1
Device
Feature
MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC5604
02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL BxMG
CPU
e200z0h
Execution
speed2
Static – up to 64 MHz
Code Flash
256 KB
384 KB
Data Flash
64 KB (4 × 16 KB)
RAM
24 KB
32 KB
28 KB
MPU
NXP Semiconductor s
ADC (10-bit)
40 KB
• PWM + MC
+ IC/OC4
32 KB
48 KB
8-entry
12 ch
28 ch
36 ch
8 ch
28 ch
12 ch
28 ch
36 ch
CTU
Total timer
I/O3 eMIOS
512 KB
8 ch
28 ch
12 ch
28 ch
36 ch
8 ch
28 ch
36 ch
Yes
12 ch,
16-bit
28 ch,
16-bit
56 ch,
16-bit
12 ch,
16-bit
28 ch,
16-bit
12 ch,
16-bit
28 ch,
16-bit
56 ch,
16-bit
12 ch,
16-bit
28 ch,
16-bit
12 ch,
16-bit
28 ch,
16-bit
56 ch,
16-bit
12 ch,
16-bit
28 ch,
16-bit
56 ch,
16-bit
2 ch
5 ch
10 ch
2 ch
5 ch
2 ch
5 ch
10 ch
2 ch
5 ch
2 ch
5 ch
10 ch
2 ch
5 ch
10 ch
Introduction
1
4
Table 1. MPC5604B/C device comparison1 (continued)
Feature
MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC5604
02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL BxMG
• PWM +
IC/OC4
10 ch
20 ch
40 ch
10 ch
20 ch
10 ch
20 ch
40 ch
10 ch
20 ch
10 ch
20 ch
40 ch
10 ch
20 ch
40 ch
• IC/OC4
—
3 ch
6 ch
—
3 ch
—
3 ch
6 ch
—
3 ch
—
3 ch
6 ch
—
3 ch
6 ch
35
SCI (LINFlex)
SPI (DSPI)
2
4
3
MPC5604B/C Microcontroller Data Sheet, Rev. 15
26
CAN
(FlexCAN)
2
3
5
6
2
3
37
I2C
1
2
3
4
5
6
7
8
9
5
6
45
79
2
3
37
2
3
5
6
Yes
45
79
123
45
79
45
79
Debug
Package
3
1
32 kHz
oscillator
GPIO8
2
123
45
79
123
45
JTAG
64
LQFP
100
LQFP
144
LQFP
64
LQFP
100
LQFP
64
LQFP
100
LQFP
144
LQFP
79
123
Nexus2+
64
LQFP
100
LQFP
64
LQFP
100
LQFP
Feature set dependent on selected peripheral multiplexing—table shows example implementation.
Based on 125 °C ambient operating temperature.
See the eMIOS section of the device reference manual for information on the channel configuration and functions.
IC – Input Capture; OC – Output Compare; PWM – Pulse Width Modulation; MC – Modulus counter.
SCI0, SCI1 and SCI2 are available. SCI3 is not available.
CAN0, CAN1 are available. CAN2, CAN3, CAN4 and CAN5 are not available.
CAN0, CAN3 and either CAN1 or CAN4 are available. CAN2, CAN5 and CAN6 are not available
I/O count based on multiplexing with peripherals.
208 MAPBGA available only as development package for Nexus2+.
144
LQFP
64
LQFP
100
208
LQFP MAPBGA9
Introduction
Device
NXP Semiconductor s
Introduction
1.3
Block diagram
Figure 1 shows a top-level block diagram of the MPC5604B/C device series.
SRAM
48 KB
Code Flash Data Flash
512 KB
64 KB
SRAM
controller
Flash
controller
JTAG
Instructions
Nexus port
e200z0h
Nexus
(Master)
Data
NMI
Nexus 2+
(Master)
SIUL
Voltage
regulator
Interrupt requests
from peripheral
blocks
NMI
INTC
Clocks
MPU
64-bit 2 x 3 Crossbar Switch
JTAG port
(Slave)
(Slave)
(Slave)
MPU
registers
CMU
FMPLL
RTC
STM
SWT
ECSM
MC_RGM MC_CGM MC_ME MC_PCU
PIT
SSCM
BAM
Peripheral bridge
Interrupt
request
SIUL
Reset control
36 Ch.
ADC
CTU
2x
eMIOS
4x
LINFlex
3x
DSPI
6x
FlexCAN
I2C
External
interrupt
request
IMUX
WKPU
GPIO and
pad control
I/O
...
...
...
...
...
Interrupt
request with
wakeup
functionality
Legend:
ADC
BAM
FlexCAN
CMU
CTU
DSPI
eMIOS
FMPLL
I2C
IMUX
INTC
JTAG
LINFlex
ECSM
MC_CGM
Analog-to-Digital Converter
Boot Assist Module
Controller Area Network
Clock Monitor Unit
Cross Triggering Unit
Deserial Serial Peripheral Interface
Enhanced Modular Input Output System
Frequency-Modulated Phase-Locked Loop
Inter-integrated Circuit Bus
Internal Multiplexer
Interrupt Controller
JTAG controller
Serial Communication Interface (LIN support)
Error Correction Status Module
Clock Generation Module
MC_ME
MC_PCU
MC_RGM
MPU
Nexus
NMI
PIT
RTC
SIUL
SRAM
SSCM
STM
SWT
WKPU
Mode Entry Module
Power Control Unit
Reset Generation Module
Memory Protection Unit
Nexus Development Interface (NDI) Level
Non-Maskable Interrupt
Periodic Interrupt Timer
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Wakeup Unit
Figure 1. Block diagram
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
5
Introduction
Table 2 summarizes the functions of all blocks present in the MPC5604B/C series of microcontrollers.
Please note that the presence and number of blocks vary by device and package.
Table 2. MPC5604B/C series block summary
Block
Function
Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Clock monitor unit (CMU)
Monitors clock source (internal and external) integrity
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices
(DSPI)
Error Correction Status Module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset status
register, wakeup control for exiting sleep modes, and optional features such as
information on memory errors reported by error-correcting codes
Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host processor
(eDMA)
via “n” programmable channels.
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network) Supports the standard CAN communications protocol
Frequency-modulated
phase-locked loop (FMPLL)
Generates high-speed system clocks and supports programmable frequency
modulation
Internal multiplexer (IMUX) SIU
subblock
Allows flexible mapping of peripheral interface on the different pins of the device
Inter-integrated circuit (I2C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of
data exchange between devices
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINFlex controller
Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with a minimum of CPU load
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control unit,
reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Power control unit (MC_PCU)
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the device
MPC5604B/C Microcontroller Data Sheet, Rev. 15
6
NXP Semiconductors
Package pinouts and signal descriptions
Table 2. MPC5604B/C series block summary (continued)
Block
Function
Memory protection unit (MPU)
Provides hardware access control for all memory references generated in a
device
Nexus development interface
(NDI)
Provides real-time development support capabilities in compliance with the
IEEE-ISTO 5001-2003 standard
Periodic interrupt timer (PIT)
Produces periodic interrupts and triggers
Real-time counter (RTC)
A free running counter used for time keeping applications, the RTC can be
configured to generate an interrupt at a predefined interval independent of the
mode of operation (run mode or low-power mode)
System integration unit (SIU)
Provides control over all the electrical pad controls and up 32 ports with 16 bits
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
System status configuration
module (SSCM)
Provides system configuration and status data (such as memory size and status,
device mode and security status), device identification data, debug status port
enable and selection, and bus and peripheral abort enable/disable
System timer module (STM)
Provides a set of output compare events to support AUTOSAR (Automotive Open
System Architecture) and operating system tasks
Software watchdog timer (SWT)
Provides protection from runaway code
Wakeup unit (WKPU)
The wakeup unit supports up to 18 external sources that can generate interrupts
or wakeup events, of which 1 can cause non-maskable interrupt requests or
wakeup events.
Crossbar (XBAR) switch
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width.
2
Package pinouts and signal descriptions
2.1
Package pinouts
The available LQFP pinouts and the 208 MAPBGA ballmap are provided in the following figures. For pin signal descriptions,
please refer to the device reference manual.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
7
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PB[2]
PC[8]
PC[4]
PC[5]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
Package pinouts and signal descriptions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 LQFP
Top view
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PA[3]
PB[15]
PB[14]
PB[13]
PB[12]
PB[11]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC
VSS_HV_ADC
PC[7]
PA[15]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PB[9]
PB[8]
PB[10]
PB[4]
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PB[3]
PC[9]
PA[2]
PA[1]
PA[0]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[10]
PB[0]
PB[1]
PC[6]
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PB[2]
PC[8]
PC[4]
PC[5]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
Figure 2. MPC560xB LQFP 64-pin configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 LQFP
Top view
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PF[14]
PF[15]
PG[0]
PG[1]
PA[3]
PB[15]
PB[14]
PB[11]
PB[7]
VDD_HV_ADC
VSS_HV_ADC
PC[7]
PA[15]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PB[9]
PB[8]
PB[10]
PB[4]
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PB[3]
PC[9]
PA[2]
PA[1]
PA[0]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[10]
PB[0]
PB[1]
PC[6]
Figure 3. MPC560xC LQFP 64-pin configuration
MPC5604B/C Microcontroller Data Sheet, Rev. 15
8
NXP Semiconductors
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PB[2]
PC[8]
PC[13]
PC[12]
PE[7]
PE[6]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PE[12]
Package pinouts and signal descriptions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100 LQFP
Top view
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
VDD_HV
VSS_HV
PA[3]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
PD[12]
PB[11]
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC
VSS_HV_ADC
PC[7]
PA[15]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PB[9]
PB[8]
PB[10]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PB[4]
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PB[3]
PC[9]
PC[14]
PC[15]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[11]
PC[10]
PB[0]
PB[1]
PC[6]
Note:
Availability of port pin alternate functions depends on product selection.
Figure 4. LQFP 100-pin configuration
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144 LQFP
Top view
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PE[13]
PF[14]
PF[15]
VDD_HV
VSS_HV
PG[0]
PG[1]
PH[3]
PH[2]
PH[1]
PH[0]
PG[12]
PG[13]
PA[3]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
PD[12]
PB[11]
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC
VSS_HV_ADC
PC[7]
PF[10]
PF[11]
PA[15]
PF[13]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PB[9]
PB[8]
PB[10]
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PB[4]
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PB[3]
PC[9]
PC[14]
PC[15]
PG[5]
PG[4]
PG[3]
PG[2]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PG[9]
PG[8]
PC[11]
PC[10]
PG[7]
PG[6]
PB[0]
PB[1]
PF[9]
PF[8]
PF[12]
PC[6]
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PB[2]
PC[8]
PC[13]
PC[12]
PE[7]
PE[6]
PH[8]
PH[7]
PH[6]
PH[5]
PH[4]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PG[11]
PG[10]
PE[15]
PE[14]
PG[15]
PG[14]
PE[12]
Package pinouts and signal descriptions
Note:
Availability of port pin alternate functions depends on product selection.
Figure 5. LQFP 144-pin configuration
MPC5604B/C Microcontroller Data Sheet, Rev. 15
10
NXP Semiconductors
Package pinouts and signal descriptions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
PC[8]
PC[13]
NC
NC
PH[8]
PH[4]
PC[5]
PC[0]
NC
NC
PC[2]
NC
PE[15]
NC
NC
NC
A
B
PC[9]
PB[2]
NC
PC[12]
PE[6]
PH[5]
PC[4]
PH[9]
PH[10]
NC
PC[3]
PG[11]
PG[15]
PG[14]
PA[11]
PA[10]
B
C
PC[14]
VDD_HV
PB[3]
PE[7]
PH[7]
PE[5]
PE[3]
VSS_LV
PC[1]
NC
PA[5]
NC
PE[14]
PE[12]
PA[9]
PA[8]
C
D
NC
NC
PC[15]
NC
PH[6]
PE[4]
PE[2]
VDD_LV
VDD_HV
NC
PA[6]
NC
PG[10]
PF[14]
PE[13]
PA[7]
D
E
PG[4]
PG[5]
PG[3]
PG[2]
PG[1]
PG[0]
PF[15]
VDD_HV
E
F
PE[0]
PA[2]
PA[1]
PE[1]
PH[0]
PH[1]
PH[3]
PH[2]
F
G
PE[9]
PE[8]
PE[10]
PA[0]
VSS_HV VSS_HV VSS_HV VSS_HV
VDD_HV
NC
NC
MSEO
G
H
VSS_HV
PE[11]
VDD_HV
NC
VSS_HV VSS_HV VSS_HV VSS_HV
MDO3
MDO2
MDO0
MDO1
H
J
RESET
VSS_LV
NC
NC
VSS_HV VSS_HV VSS_HV VSS_HV
NC
NC
NC
NC
J
K
EVTI
NC
VDD_BV
VDD_LV
VSS_HV VSS_HV VSS_HV VSS_HV
NC
PG[12]
PA[3]
PG[13]
K
L
PG[9]
PG[8]
NC
EVTO
PB[15]
PD[15]
PD[14]
PB[14]
L
M
PG[7]
PG[6]
PC[10]
PC[11]
PB[13]
PD[13]
PD[12]
PB[12]
M
N
PB[1]
PF[9]
PB[0]
NC
NC
PA[4]
VSS_LV
EXTAL
VDD_HV
PF[0]
PF[4]
NC
PB[11]
PD[10]
PD[9]
PD[11]
N
P
PF[8]
NC
PC[7]
NC
NC
PA[14]
VDD_LV
XTAL
PB[10]
PF[1]
PF[5]
PD[0]
PD[3]
VDD_HV
_ADC
PB[6]
PB[7]
P
R
PF[12]
PC[6]
PF[10]
PF[11]
VDD_HV
PA[15]
PA[13]
NC
OSC32K
_XTAL
PF[3]
PF[7]
PD[2]
PD[4]
PD[7]
VSS_HV
_ADC
PB[5]
R
T
NC
NC
NC
MCKO
NC
PF[13]
PA[12]
NC
OSC32K
_EXTAL
PF[2]
PF[6]
PD[1]
PD[5]
PD[6]
PD[8]
PB[4]
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Note: 208 MAPBGA available only as development package for Nexus 2+.
NC
= Not connected
Figure 6. 208 MAPBGA configuration
2.2
Pad configuration during reset phases
All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are forced to tristate with the following exceptions:
• PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash.
• PA[8] (ABS[0]) is pull-up.
• RESET pad is driven low. This is pull-up only after PHASE2 reset completion.
• JTAG pads (TCK, TMS and TDI) are pull-up whilst TDO remains tristate.
• Precise ADC pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available).
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
11
Package pinouts and signal descriptions
•
•
Main oscillator pads (EXTAL, XTAL) are tristate.
Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output.
2.3
Voltage supply pins
Voltage supply pins are used to provide power to the device. Three dedicated VDD_LV/VSS_LV supply
pairs are used for 1.2 V regulator stabilization.
Table 3. Voltage supply pin descriptions
Pin number
Port pin
Function
64 LQFP1
7, 28, 56
100 LQFP
208
MAPBGA2
144 LQFP
VDD_HV
Digital supply voltage
15, 37, 70, 84 19, 51, 100, C2, D9, E16,
123
G13, H3, N9,
R5
VSS_HV
Digital ground
6, 8, 26, 55
14, 16, 35,
69, 83
18, 20, 49,
99, 122
G7, G8, G9,
G10, H1, H7,
H8, H9, H10,
J7, J8, J9,
J10, K7, K8,
K9, K10
VDD_LV
1.2V decoupling pins. Decoupling
capacitor must be connected between
these pins and the nearest VSS_LV pin.3
11, 23, 57
19, 32, 85
23, 46, 124
D8, K4, P7
VSS_LV
1.2V decoupling pins. Decoupling
capacitor must be connected between
these pins and the nearest VDD_LV pin.3
10, 24, 58
18, 33, 86
22, 47, 125
C8, J2, N7
VDD_BV
Internal regulator supply voltage
12
20
24
K3
VSS_HV_ADC Reference ground and analog ground for
the ADC
33
51
73
R15
VDD_HV_ADC Reference voltage and analog supply for
the ADC
34
52
74
P14
1
Pin numbers apply to both the MPC560xB and MPC560xC packages.
208 MAPBGA available only as development package for Nexus2+
3 A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable
voltage (see the recommended operating conditions in the device datasheet for details).
2
2.4
Pad types
In the device the following types of pads are available for system pins and functional port pins:
S = Slow1
M = Medium1 2
F = Fast1 2
1. See the I/O pad electrical characteristics in the device datasheet for details.
2. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (see PCR.SRC
in section Pad Configuration Registers (PCR0–PCR122) in the device reference manual).
MPC5604B/C Microcontroller Data Sheet, Rev. 15
12
NXP Semiconductors
Package pinouts and signal descriptions
I = Input only with analog feature1
J = Input/Output (‘S’ pad) with analog feature
X = Oscillator
2.5
System pins
The system pins are listed in Table 4.
RESET configuration
Table 4. System pin descriptions
Pad type
64 LQFP1
100 LQFP
144 LQFP
208 MAPBGA2
RESET Bidirectional reset with Schmitt-Trigger characteristics
and noise filter.
I/O
M
Input, weak
pull-up only
after PHASE2
9
17
21
J1
EXTAL Analog output of the oscillator amplifier circuit, when the
oscillator is not in bypass mode.
Analog input for the clock generator when the oscillator is
in bypass mode.3
I/O
X
Tristate
27
36
50
N8
I
X
Tristate
25
34
48
P8
System pin
I/O direction
Pin number
Function
XTAL
Analog input of the oscillator amplifier circuit. Needs to be
grounded if oscillator is used in bypass mode.3
1
Pin numbers apply to both the MPC560xB and MPC560xC packages.
208 MAPBGA available only as development package for Nexus2+
3 See the relevant section of the datasheet
2
2.6
Functional ports
The functional port pins are listed in Table 5.
208 MAPBGA3
Tristate
144 LQFP
M
100 LQFP
I/O
I/O
O
—
I
MPC560xC 64 LQFP
SIUL
eMIOS_0
CGL
—
WKPU
Pin number
MPC560xB 64 LQFP
GPIO[0]
E0UC[0]
CLKOUT
—
WKPU[19]4
RESET configuration
I/O direction2
AF0
AF1
AF2
AF3
—
Pad type
Peripheral
PCR[0]
Function
PCR
PA[0]
Alternate function1
Port pin
Table 5. Functional port pin descriptions
5
5
12
16
G4
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
13
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Port pin
PCR
Alternate function1
Function
Peripheral
I/O direction2
Pad type
RESET configuration
MPC560xB 64 LQFP
MPC560xC 64 LQFP
100 LQFP
144 LQFP
208 MAPBGA3
Pin number
PA[1]
PCR[1]
AF0
AF1
AF2
AF3
—
—
GPIO[1]
E0UC[1]
—
—
NMI5
WKPU[2]4
SIUL
eMIOS_0
—
—
WKPU
WKPU
I/O
I/O
—
—
I
I
S
Tristate
4
4
7
11
F3
PA[2]
PCR[2]
AF0
AF1
AF2
AF3
—
GPIO[2]
E0UC[2]
—
—
WKPU[3]4
SIUL
eMIOS_0
—
—
WKPU
I/O
I/O
—
—
I
S
Tristate
3
3
5
9
F2
PA[3]
PCR[3]
AF0
AF1
AF2
AF3
—
GPIO[3]
E0UC[3]
—
—
EIRQ[0]
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
S
Tristate
43
39
68
90
K15
PA[4]
PCR[4]
AF0
AF1
AF2
AF3
—
GPIO[4]
E0UC[4]
—
—
WKPU[9]4
SIUL
eMIOS_0
—
—
WKPU
I/O
I/O
—
—
I
S
Tristate
20
20
29
43
N6
PA[5]
PCR[5]
AF0
AF1
AF2
AF3
GPIO[5]
E0UC[5]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
M
Tristate
51
51
79
118 C11
PA[6]
PCR[6]
AF0
AF1
AF2
AF3
—
GPIO[6]
E0UC[6]
—
—
EIRQ[1]
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
S
Tristate
52
52
80
119 D11
PA[7]
PCR[7]
AF0
AF1
AF2
AF3
—
GPIO[7]
E0UC[7]
LIN3TX
—
EIRQ[2]
SIUL
eMIOS_0
LINFlex_3
—
SIUL
I/O
I/O
O
—
I
S
Tristate
44
44
71
104 D16
MPC5604B/C Microcontroller Data Sheet, Rev. 15
14
NXP Semiconductors
Package pinouts and signal descriptions
Function
Peripheral
I/O direction2
MPC560xB 64 LQFP
MPC560xC 64 LQFP
100 LQFP
144 LQFP
PCR[8]
AF0
AF1
AF2
AF3
—
N/A6
—
GPIO[8]
E0UC[8]
—
—
EIRQ[3]
ABS[0]
LIN3RX
SIUL
eMIOS_0
—
—
SIUL
BAM
LINFlex_3
I/O
I/O
—
—
I
I
I
S
Input, weak
pull-up
45
45
72
105 C16
PA[9]
PCR[9]
AF0
AF1
AF2
AF3
N/A6
GPIO[9]
E0UC[9]
—
—
FAB
SIUL
eMIOS_0
—
—
BAM
I/O
I/O
—
—
I
S
Pull-down
46
46
73
106 C15
PA[10]
PCR[10]
AF0
AF1
AF2
AF3
GPIO[10]
E0UC[10]
SDA
—
SIUL
eMIOS_0
I2C_0
—
I/O
I/O
I/O
—
S
Tristate
47
47
74
107 B16
PA[11]
PCR[11]
AF0
AF1
AF2
AF3
GPIO[11]
E0UC[11]
SCL
—
SIUL
eMIOS_0
I2C_0
—
I/O
I/O
I/O
—
S
Tristate
48
48
75
108 B15
PA[12]
PCR[12]
AF0
AF1
AF2
AF3
—
GPIO[12]
—
—
—
SIN_0
SIUL
—
—
—
DSPI0
I/O
—
—
—
I
S
Tristate
22
22
31
45
T7
PA[13]
PCR[13]
AF0
AF1
AF2
AF3
GPIO[13]
SOUT_0
—
—
SIUL
DSPI_0
—
—
I/O
O
—
—
M
Tristate
21
21
30
44
R7
PA[14]
PCR[14]
AF0
AF1
AF2
AF3
—
GPIO[14]
SCK_0
CS0_0
—
EIRQ[4]
SIUL
DSPI_0
DSPI_0
—
SIUL
I/O
I/O
I/O
—
I
M
Tristate
19
19
28
42
P6
PA[15]
PCR[15]
AF0
AF1
AF2
AF3
—
GPIO[15]
CS0_0
SCK_0
—
WKPU[10]4
SIUL
DSPI_0
DSPI_0
—
WKPU
I/O
I/O
I/O
—
I
M
Tristate
18
18
27
40
R6
208 MAPBGA3
Alternate function1
PA[8]
Pad type
PCR
Pin number
Port pin
RESET configuration
Table 5. Functional port pin descriptions (continued)
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
15
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Port pin
PCR
Alternate function1
Function
Peripheral
I/O direction2
Pad type
RESET configuration
MPC560xB 64 LQFP
MPC560xC 64 LQFP
100 LQFP
144 LQFP
208 MAPBGA3
Pin number
PB[0]
PCR[16]
AF0
AF1
AF2
AF3
GPIO[16]
CAN0TX
—
—
SIUL
FlexCAN_0
—
—
I/O
O
—
—
M
Tristate
14
14
23
31
N3
PB[1]
PCR[17]
AF0
AF1
AF2
AF3
—
—
GPIO[17]
—
—
—
WKPU[4]4
CAN0RX
SIUL
—
—
—
WKPU
FlexCAN_0
I/O
—
—
—
I
I
S
Tristate
15
15
24
32
N1
PB[2]
PCR[18]
AF0
AF1
AF2
AF3
GPIO[18]
LIN0TX
SDA
—
SIUL
LINFlex_0
I2C_0
—
I/O
O
I/O
—
M
Tristate
64
64
100 144
B2
PB[3]
PCR[19]
AF0
AF1
AF2
AF3
—
—
GPIO[19]
—
SCL
—
WKPU[11]4
LIN0RX
SIUL
—
I2C_0
—
WKPU
LINFlex_0
I/O
—
I/O
—
I
I
S
Tristate
1
1
1
1
C3
PB[4]
PCR[20]
AF0
AF1
AF2
AF3
—
GPIO[20]
—
—
—
GPI[0]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
32
32
50
72
T16
PB[5]
PCR[21]
AF0
AF1
AF2
AF3
—
GPIO[21]
—
—
—
GPI[1]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
35
—
53
75
R16
PB[6]
PCR[22]
AF0
AF1
AF2
AF3
—
GPIO[22]
—
—
—
GPI[2]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
36
—
54
76
P15
PB[7]
PCR[23]
AF0
AF1
AF2
AF3
—
GPIO[23]
—
—
—
GPI[3]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
37
35
55
77
P16
MPC5604B/C Microcontroller Data Sheet, Rev. 15
16
NXP Semiconductors
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Port pin
PCR
Alternate function1
Function
Peripheral
I/O direction2
Pad type
RESET configuration
MPC560xB 64 LQFP
MPC560xC 64 LQFP
100 LQFP
144 LQFP
208 MAPBGA3
Pin number
PB[8]
PCR[24]
AF0
AF1
AF2
AF3
—
—
GPIO[24]
—
—
—
ANS[0]
OSC32K_XTAL7
SIUL
—
—
—
ADC
SXOSC
I
—
—
—
I
I/O
I
Tristate
30
30
39
53
R9
PB[9]
PCR[25]
AF0
AF1
AF2
AF3
—
—
GPIO[25]
—
—
—
ANS[1]
OSC32K_EXTAL7
SIUL
—
—
—
ADC
SXOSC
I
—
—
—
I
I/O
I
Tristate
29
29
38
52
T9
PB[10]
PCR[26]
AF0
AF1
AF2
AF3
—
—
GPIO[26]
—
—
—
ANS[2]
WKPU[8]4
SIUL
—
—
—
ADC
WKPU
I/O
—
—
—
I
I
J
Tristate
31
31
40
54
P9
PB[11]8
PCR[27]
AF0
AF1
AF2
AF3
—
GPIO[27]
E0UC[3]
—
CS0_0
ANS[3]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
I/O
I
J
Tristate
38
36
59
81
N13
PB[12]
PCR[28]
AF0
AF1
AF2
AF3
—
GPIO[28]
E0UC[4]
—
CS1_0
ANX[0]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
J
Tristate
39
—
61
83
M16
PB[13]
PCR[29]
AF0
AF1
AF2
AF3
—
GPIO[29]
E0UC[5]
—
CS2_0
ANX[1]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
J
Tristate
40
—
63
85
M13
PB[14]
PCR[30]
AF0
AF1
AF2
AF3
—
GPIO[30]
E0UC[6]
—
CS3_0
ANX[2]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
J
Tristate
41
37
65
87
L16
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
17
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Port pin
PCR
Alternate function1
Function
Peripheral
I/O direction2
Pad type
RESET configuration
MPC560xB 64 LQFP
MPC560xC 64 LQFP
100 LQFP
144 LQFP
208 MAPBGA3
Pin number
PB[15]
PCR[31]
AF0
AF1
AF2
AF3
—
GPIO[31]
E0UC[7]
—
CS4_0
ANX[3]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
J
Tristate
42
38
67
89
L13
PC[0]9
PCR[32]
AF0
AF1
AF2
AF3
GPIO[32]
—
TDI
—
SIUL
—
JTAGC
—
I/O
—
I
—
M
Input, weak
pull-up
59
59
87
126
A8
PC[1]9
PCR[33]
AF0
AF1
AF2
AF3
GPIO[33]
—
TDO10
—
SIUL
—
JTAGC
—
I/O
—
O
—
M
Tristate
54
54
82
121
C9
PC[2]
PCR[34]
AF0
AF1
AF2
AF3
—
GPIO[34]
SCK_1
CAN4TX11
—
EIRQ[5]
SIUL
DSPI_1
FlexCAN_4
—
SIUL
I/O
I/O
O
—
I
M
Tristate
50
50
78
117 A11
PC[3]
PCR[35]
AF0
AF1
AF2
AF3
—
—
—
GPIO[35]
CS0_1
MA[0]
—
CAN1RX
CAN4RX11
EIRQ[6]
SIUL
DSPI_1
ADC
—
FlexCAN_1
FlexCAN_4
SIUL
I/O
I/O
O
—
I
I
I
S
Tristate
49
49
77
116 B11
PC[4]
PCR[36]
AF0
AF1
AF2
AF3
—
—
GPIO[36]
—
—
—
SIN_1
CAN3RX11
SIUL
—
—
—
DSPI_1
FlexCAN_3
I/O
—
—
—
I
I
M
Tristate
62
62
92
131
B7
PC[5]
PCR[37]
AF0
AF1
AF2
AF3
—
GPIO[37]
SOUT_1
CAN3TX11
—
EIRQ[7]
SIUL
DSPI1
FlexCAN_3
—
SIUL
I/O
O
O
—
I
M
Tristate
61
61
91
130
A7
PC[6]
PCR[38]
AF0
AF1
AF2
AF3
GPIO[38]
LIN1TX
—
—
SIUL
LINFlex_1
—
—
I/O
O
—
—
S
Tristate
16
16
25
36
R2
MPC5604B/C Microcontroller Data Sheet, Rev. 15
18
NXP Semiconductors
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Port pin
PCR
Alternate function1
Function
Peripheral
I/O direction2
Pad type
RESET configuration
MPC560xB 64 LQFP
MPC560xC 64 LQFP
100 LQFP
144 LQFP
208 MAPBGA3
Pin number
PC[7]
PCR[39]
AF0
AF1
AF2
AF3
—
—
GPIO[39]
—
—
—
LIN1RX
WKPU[12]4
SIUL
—
—
—
LINFlex_1
WKPU
I/O
—
—
—
I
I
S
Tristate
17
17
26
37
P3
PC[8]
PCR[40]
AF0
AF1
AF2
AF3
GPIO[40]
LIN2TX
—
—
SIUL
LINFlex_2
—
—
I/O
O
—
—
S
Tristate
63
63
99
143
A1
PC[9]
PCR[41]
AF0
AF1
AF2
AF3
—
—
GPIO[41]
—
—
—
LIN2RX
WKPU[13]4
SIUL
—
—
—
LINFlex_2
WKPU
I/O
—
—
—
I
I
S
Tristate
2
2
2
2
B1
PC[10]
PCR[42]
AF0
AF1
AF2
AF3
GPIO[42]
CAN1TX
CAN4TX11
MA[1]
SIUL
FlexCAN_1
FlexCAN_4
ADC
I/O
O
O
O
M
Tristate
13
13
22
28
M3
PC[11]
PCR[43]
AF0
AF1
AF2
AF3
—
—
—
GPIO[43]
—
—
—
CAN1RX
CAN4RX11
WKPU[5]4
SIUL
—
—
—
FlexCAN_1
FlexCAN_4
WKPU
I/O
—
—
—
I
I
I
S
Tristate
—
—
21
27
M4
PC[12]
PCR[44]
AF0
AF1
AF2
AF3
—
GPIO[44]
E0UC[12]
—
—
SIN_2
SIUL
eMIOS_0
—
—
DSPI_2
I/O
I/O
—
—
I
M
Tristate
—
—
97
141
B4
PC[13]
PCR[45]
AF0
AF1
AF2
AF3
GPIO[45]
E0UC[13]
SOUT_2
—
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
O
—
S
Tristate
—
—
98
142
A2
PC[14]
PCR[46]
AF0
AF1
AF2
AF3
—
GPIO[46]
E0UC[14]
SCK_2
—
EIRQ[8]
SIUL
eMIOS_0
DSPI_2
—
SIUL
I/O
I/O
I/O
—
I
S
Tristate
—
—
3
3
C1
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
19
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Port pin
PCR
Alternate function1
Function
Peripheral
I/O direction2
Pad type
RESET configuration
MPC560xB 64 LQFP
MPC560xC 64 LQFP
100 LQFP
144 LQFP
208 MAPBGA3
Pin number
PC[15]
PCR[47]
AF0
AF1
AF2
AF3
GPIO[47]
E0UC[15]
CS0_2
—
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
I/O
—
M
Tristate
—
—
4
4
D3
PD[0]
PCR[48]
AF0
AF1
AF2
AF3
—
GPIO[48]
—
—
—
GPI[4]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
—
41
63
P12
PD[1]
PCR[49]
AF0
AF1
AF2
AF3
—
GPIO[49]
—
—
—
GPI[5]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
—
42
64
T12
PD[2]
PCR[50]
AF0
AF1
AF2
AF3
—
GPIO[50]
—
—
—
GPI[6]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
—
43
65
R12
PD[3]
PCR[51]
AF0
AF1
AF2
AF3
—
GPIO[51]
—
—
—
GPI[7]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
—
44
66
P13
PD[4]
PCR[52]
AF0
AF1
AF2
AF3
—
GPIO[52]
—
—
—
GPI[8]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
—
45
67
R13
PD[5]
PCR[53]
AF0
AF1
AF2
AF3
—
GPIO[53]
—
—
—
GPI[9]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
—
46
68
T13
PD[6]
PCR[54]
AF0
AF1
AF2
AF3
—
GPIO[54]
—
—
—
GPI[10]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
—
47
69
T14
MPC5604B/C Microcontroller Data Sheet, Rev. 15
20
NXP Semiconductors
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Port pin
PCR
Alternate function1
Function
Peripheral
I/O direction2
Pad type
RESET configuration
MPC560xB 64 LQFP
MPC560xC 64 LQFP
100 LQFP
144 LQFP
208 MAPBGA3
Pin number
PD[7]
PCR[55]
AF0
AF1
AF2
AF3
—
GPIO[55]
—
—
—
GPI[11]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
—
48
70
R14
PD[8]
PCR[56]
AF0
AF1
AF2
AF3
—
GPIO[56]
—
—
—
GPI[12]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
—
49
71
T15
PD[9]
PCR[57]
AF0
AF1
AF2
AF3
—
GPIO[57]
—
—
—
GPI[13]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
—
56
78
N15
PD[10]
PCR[58]
AF0
AF1
AF2
AF3
—
GPIO[58]
—
—
—
GPI[14]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
—
57
79
N14
PD[11]
PCR[59]
AF0
AF1
AF2
AF3
—
GPIO[59]
—
—
—
GPI[15]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
—
58
80
N16
PD[12]8
PCR[60]
AF0
AF1
AF2
AF3
—
GPIO[60]
CS5_0
E0UC[24]
—
ANS[4]
SIUL
DSPI_0
eMIOS_0
—
ADC
I/O
O
I/O
—
I
J
Tristate
—
—
60
82
M15
PD[13]
PCR[61]
AF0
AF1
AF2
AF3
—
GPIO[61]
CS0_1
E0UC[25]
—
ANS[5]
SIUL
DSPI_1
eMIOS_0
—
ADC
I/O
I/O
I/O
—
I
J
Tristate
—
—
62
84
M14
PD[14]
PCR[62]
AF0
AF1
AF2
AF3
—
GPIO[62]
CS1_1
E0UC[26]
—
ANS[6]
SIUL
DSPI_1
eMIOS_0
—
ADC
I/O
O
I/O
—
I
J
Tristate
—
—
64
86
L15
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
21
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Port pin
PCR
Alternate function1
Function
Peripheral
I/O direction2
Pad type
RESET configuration
MPC560xB 64 LQFP
MPC560xC 64 LQFP
100 LQFP
144 LQFP
208 MAPBGA3
Pin number
PD[15]
PCR[63]
AF0
AF1
AF2
AF3
—
GPIO[63]
CS2_1
E0UC[27]
—
ANS[7]
SIUL
DSPI_1
eMIOS_0
—
ADC
I/O
O
I/O
—
I
J
Tristate
—
—
66
88
L14
PE[0]
PCR[64]
AF0
AF1
AF2
AF3
—
—
GPIO[64]
E0UC[16]
—
—
CAN5RX11
WKPU[6]4
SIUL
eMIOS_0
—
—
FlexCAN_5
WKPU
I/O
I/O
—
—
I
I
S
Tristate
—
—
6
10
F1
PE[1]
PCR[65]
AF0
AF1
AF2
AF3
GPIO[65]
E0UC[17]
CAN5TX11
—
SIUL
eMIOS_0
FlexCAN_5
—
I/O
I/O
O
—
M
Tristate
—
—
8
12
F4
PE[2]
PCR[66]
AF0
AF1
AF2
AF3
—
GPIO[66]
E0UC[18]
—
—
SIN_1
SIUL
eMIOS_0
—
—
DSPI_1
I/O
I/O
—
—
I
M
Tristate
—
—
89
128
D7
PE[3]
PCR[67]
AF0
AF1
AF2
AF3
GPIO[67]
E0UC[19]
SOUT_1
—
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
O
—
M
Tristate
—
—
90
129
C7
PE[4]
PCR[68]
AF0
AF1
AF2
AF3
—
GPIO[68]
E0UC[20]
SCK_1
—
EIRQ[9]
SIUL
eMIOS_0
DSPI_1
—
SIUL
I/O
I/O
I/O
—
I
M
Tristate
—
—
93
132
D6
PE[5]
PCR[69]
AF0
AF1
AF2
AF3
GPIO[69]
E0UC[21]
CS0_1
MA[2]
SIUL
eMIOS_0
DSPI_1
ADC
I/O
I/O
I/O
O
M
Tristate
—
—
94
133
C6
PE[6]
PCR[70]
AF0
AF1
AF2
AF3
GPIO[70]
E0UC[22]
CS3_0
MA[1]
SIUL
eMIOS_0
DSPI_0
ADC
I/O
I/O
O
O
M
Tristate
—
—
95
139
B5
PE[7]
PCR[71]
AF0
AF1
AF2
AF3
GPIO[71]
E0UC[23]
CS2_0
MA[0]
SIUL
eMIOS_0
DSPI_0
ADC
I/O
I/O
O
O
M
Tristate
—
—
96
140
C4
MPC5604B/C Microcontroller Data Sheet, Rev. 15
22
NXP Semiconductors
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Port pin
PCR
Alternate function1
Function
Peripheral
I/O direction2
Pad type
RESET configuration
MPC560xB 64 LQFP
MPC560xC 64 LQFP
100 LQFP
144 LQFP
208 MAPBGA3
Pin number
PE[8]
PCR[72]
AF0
AF1
AF2
AF3
GPIO[72]
CAN2TX12
E0UC[22]
CAN3TX11
SIUL
FlexCAN_2
eMIOS_0
FlexCAN_3
I/O
O
I/O
O
M
Tristate
—
—
9
13
G2
PE[9]
PCR[73]
AF0
AF1
AF2
AF3
—
—
—
GPIO[73]
—
E0UC[23]
—
WKPU[7]4
CAN2RX12
CAN3RX11
SIUL
—
eMIOS_0
—
WKPU
FlexCAN_2
FlexCAN_3
I/O
—
I/O
—
I
I
I
S
Tristate
—
—
10
14
G1
PE[10]
PCR[74]
AF0
AF1
AF2
AF3
—
GPIO[74]
LIN3TX
CS3_1
—
EIRQ[10]
SIUL
LINFlex_3
DSPI_1
—
SIUL
I/O
O
O
—
I
S
Tristate
—
—
11
15
G3
PE[11]
PCR[75]
AF0
AF1
AF2
AF3
—
—
GPIO[75]
—
CS4_1
—
LIN3RX
WKPU[14]4
SIUL
—
DSPI_1
—
LINFlex_3
WKPU
I/O
—
O
—
I
I
S
Tristate
—
—
13
17
H2
PE[12]
PCR[76]
AF0
AF1
AF2
AF3
—
—
GPIO[76]
—
E1UC[19]13
—
SIN_2
EIRQ[11]
SIUL
—
eMIOS_1
—
DSPI_2
SIUL
I/O
—
I/O
—
I
I
S
Tristate
—
—
76
109 C14
PE[13]
PCR[77]
AF0
AF1
AF2
AF3
GPIO[77]
SOUT2
E1UC[20]
—
SIUL
DSPI_2
eMIOS_1
—
I/O
O
I/O
—
S
Tristate
—
—
—
103 D15
PE[14]
PCR[78]
AF0
AF1
AF2
AF3
—
GPIO[78]
SCK_2
E1UC[21]
—
EIRQ[12]
SIUL
DSPI_2
eMIOS_1
—
SIUL
I/O
I/O
I/O
—
I
S
Tristate
—
—
—
112 C13
PE[15]
PCR[79]
AF0
AF1
AF2
AF3
GPIO[79]
CS0_2
E1UC[22]
—
SIUL
DSPI_2
eMIOS_1
—
I/O
I/O
I/O
—
M
Tristate
—
—
—
113 A13
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
23
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Port pin
PCR
Alternate function1
Function
Peripheral
I/O direction2
Pad type
RESET configuration
MPC560xB 64 LQFP
MPC560xC 64 LQFP
100 LQFP
144 LQFP
208 MAPBGA3
Pin number
PF[0]
PCR[80]
AF0
AF1
AF2
AF3
—
GPIO[80]
E0UC[10]
CS3_1
—
ANS[8]
SIUL
eMIOS_0
DSPI_1
—
ADC
I/O
I/O
O
—
I
J
Tristate
—
—
—
55
N10
PF[1]
PCR[81]
AF0
AF1
AF2
AF3
—
GPIO[81]
E0UC[11]
CS4_1
—
ANS[9]
SIUL
eMIOS_0
DSPI_1
—
I
I/O
I/O
O
—
I
J
Tristate
—
—
—
56
P10
PF[2]
PCR[82]
AF0
AF1
AF2
AF3
—
GPIO[82]
E0UC[12]
CS0_2
—
ANS[10]
SIUL
eMIOS_0
DSPI_2
—
ADC
I/O
I/O
I/O
—
I
J
Tristate
—
—
—
57
T10
PF[3]
PCR[83]
AF0
AF1
AF2
AF3
—
GPIO[83]
E0UC[13]
CS1_2
—
ANS[11]
SIUL
eMIOS_0
DSPI_2
—
ADC
I/O
I/O
O
—
I
J
Tristate
—
—
—
58
R10
PF[4]
PCR[84]
AF0
AF1
AF2
AF3
—
GPIO[84]
E0UC[14]
CS2_2
—
ANS[12]
SIUL
eMIOS_0
DSPI_2
—
ADC
I/O
I/O
O
—
I
J
Tristate
—
—
—
59
N11
PF[5]
PCR[85]
AF0
AF1
AF2
AF3
—
GPIO[85]
E0UC[22]
CS3_2
—
ANS[13]
SIUL
eMIOS_0
DSPI_2
—
ADC
I/O
I/O
O
—
I
J
Tristate
—
—
—
60
P11
PF[6]
PCR[86]
AF0
AF1
AF2
AF3
—
GPIO[86]
E0UC[23]
—
—
ANS[14]
SIUL
eMIOS_0
—
—
ADC
I/O
I/O
—
—
I
J
Tristate
—
—
—
61
T11
PF[7]
PCR[87]
AF0
AF1
AF2
AF3
—
GPIO[87]
—
—
—
ANS[15]
SIUL
—
—
—
ADC
I/O
—
—
—
I
J
Tristate
—
—
—
62
R11
MPC5604B/C Microcontroller Data Sheet, Rev. 15
24
NXP Semiconductors
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Port pin
PCR
Alternate function1
Function
Peripheral
I/O direction2
Pad type
RESET configuration
MPC560xB 64 LQFP
MPC560xC 64 LQFP
100 LQFP
144 LQFP
208 MAPBGA3
Pin number
PF[8]
PCR[88]
AF0
AF1
AF2
AF3
GPIO[88]
CAN3TX14
CS4_0
CAN2TX15
SIUL
FlexCAN_3
DSPI_0
FlexCAN_2
I/O
O
O
O
M
Tristate
—
—
—
34
P1
PF[9]
PCR[89]
AF0
AF1
AF2
AF3
—
—
GPIO[89]
—
CS5_0
—
CAN2RX15
CAN3RX14
SIUL
—
DSPI_0
—
FlexCAN_2
FlexCAN_3
I/O
—
O
—
I
I
S
Tristate
—
—
—
33
N2
PF[10]
PCR[90]
AF0
AF1
AF2
AF3
GPIO[90]
—
—
—
SIUL
—
—
—
I/O
—
—
—
M
Tristate
—
—
—
38
R3
PF[11]
PCR[91]
AF0
AF1
AF2
AF3
—
GPIO[91]
—
—
—
WKPU[15]4
SIUL
—
—
—
WKPU
I/O
—
—
—
I
S
Tristate
—
—
—
39
R4
PF[12]
PCR[92]
AF0
AF1
AF2
AF3
GPIO[92]
E1UC[25]
—
—
SIUL
eMIOS_1
—
—
I/O
I/O
—
—
M
Tristate
—
—
—
35
R1
PF[13]
PCR[93]
AF0
AF1
AF2
AF3
—
GPIO[93]
E1UC[26]
—
—
WKPU[16]4
SIUL
eMIOS_1
—
—
WKPU
I/O
I/O
—
—
I
S
Tristate
—
—
—
41
T6
PF[14]
PCR[94]
AF0
AF1
AF2
AF3
GPIO[94]
CAN4TX11
E1UC[27]
CAN1TX
SIUL
FlexCAN_4
eMIOS_1
FlexCAN_4
I/O
O
I/O
O
M
Tristate
—
43
—
102 D14
PF[15]
PCR[95]
AF0
AF1
AF2
AF3
—
—
—
GPIO[95]
—
—
—
CAN1RX
CAN4RX11
EIRQ[13]
SIUL
—
—
—
FlexCAN_1
FlexCAN_4
SIUL
I/O
—
—
—
I
I
I
S
Tristate
—
42
—
101 E15
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
25
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Port pin
PCR
Alternate function1
Function
Peripheral
I/O direction2
Pad type
RESET configuration
MPC560xB 64 LQFP
MPC560xC 64 LQFP
100 LQFP
144 LQFP
208 MAPBGA3
Pin number
PG[0]
PCR[96]
AF0
AF1
AF2
AF3
GPIO[96]
CAN5TX11
E1UC[23]
—
SIUL
FlexCAN_5
eMIOS_1
—
I/O
O
I/O
—
M
Tristate
—
41
—
98
E14
PG[1]
PCR[97]
AF0
AF1
AF2
AF3
—
—
GPIO[97]
—
E1UC[24]
—
CAN5RX11
EIRQ[14]
SIUL
—
eMIOS_1
—
FlexCAN_5
SIUL
I/O
—
I/O
—
I
I
S
Tristate
—
40
—
97
E13
PG[2]
PCR[98]
AF0
AF1
AF2
AF3
GPIO[98]
E1UC[11]
—
—
SIUL
eMIOS_1
—
—
I/O
I/O
—
—
M
Tristate
—
—
—
8
E4
PG[3]
PCR[99]
AF0
AF1
AF2
AF3
—
GPIO[99]
E1UC[12]
—
—
WKPU[17]4
SIUL
eMIOS_1
—
—
WKPU
I/O
I/O
—
—
I
S
Tristate
—
—
—
7
E3
PG[4]
PCR[100] AF0
AF1
AF2
AF3
GPIO[100]
E1UC[13]
—
—
SIUL
eMIOS_1
—
—
I/O
I/O
—
—
M
Tristate
—
—
—
6
E1
PG[5]
PCR[101] AF0
AF1
AF2
AF3
—
GPIO[101]
E1UC[14]
—
—
WKPU[18]4
SIUL
eMIOS_1
—
—
WKPU
I/O
I/O
—
—
I
S
Tristate
—
—
—
5
E2
PG[6]
PCR[102] AF0
AF1
AF2
AF3
GPIO[102]
E1UC[15]
—
—
SIUL
eMIOS_1
—
—
I/O
I/O
—
—
M
Tristate
—
—
—
30
M2
PG[7]
PCR[103] AF0
AF1
AF2
AF3
GPIO[103]
E1UC[16]
—
—
SIUL
eMIOS_1
—
—
I/O
I/O
—
—
M
Tristate
—
—
—
29
M1
PG[8]
PCR[104] AF0
AF1
AF2
AF3
—
GPIO[104]
E1UC[17]
—
CS0_2
EIRQ[15]
SIUL
eMIOS_1
—
DSPI_2
SIUL
I/O
I/O
—
I/O
I
S
Tristate
—
—
—
26
L2
MPC5604B/C Microcontroller Data Sheet, Rev. 15
26
NXP Semiconductors
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Peripheral
I/O direction2
Pad type
RESET configuration
MPC560xB 64 LQFP
MPC560xC 64 LQFP
100 LQFP
144 LQFP
208 MAPBGA3
GPIO[105]
E1UC[18]
—
SCK_2
SIUL
eMIOS_1
—
DSPI_2
I/O
I/O
—
I/O
S
Tristate
—
—
—
25
L1
PG[10]
PCR[106] AF0
AF1
AF2
AF3
GPIO[106]
E0UC[24]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
S
Tristate
—
—
—
114 D13
PG[11]
PCR[107] AF0
AF1
AF2
AF3
GPIO[107]
E0UC[25]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
M
Tristate
—
—
—
115 B12
PG[12]
PCR[108] AF0
AF1
AF2
AF3
GPIO[108]
E0UC[26]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
M
Tristate
—
—
—
92
K14
PG[13]
PCR[109] AF0
AF1
AF2
AF3
GPIO[109]
E0UC[27]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
M
Tristate
—
—
—
91
K16
PG[14]
PCR[110] AF0
AF1
AF2
AF3
GPIO[110]
E1UC[0]
—
—
SIUL
eMIOS_1
—
—
I/O
I/O
—
—
S
Tristate
—
—
—
110 B14
PG[15]
PCR[111] AF0
AF1
AF2
AF3
GPIO[111]
E1UC[1]
—
—
SIUL
eMIOS_1
—
—
I/O
I/O
—
—
M
Tristate
—
—
—
111 B13
PH[0]
PCR[112] AF0
AF1
AF2
AF3
—
GPIO[112]
E1UC[2]
—
—
SIN1
SIUL
eMIOS_1
—
—
DSPI_1
I/O
I/O
—
—
I
M
Tristate
—
—
—
93
F13
PH[1]
PCR[113] AF0
AF1
AF2
AF3
GPIO[113]
E1UC[3]
SOUT1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
O
—
M
Tristate
—
—
—
94
F14
Alternate function1
PCR[105] AF0
AF1
AF2
AF3
PCR
PG[9]
Port pin
Function
Pin number
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
27
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Peripheral
I/O direction2
Pad type
RESET configuration
MPC560xB 64 LQFP
MPC560xC 64 LQFP
100 LQFP
144 LQFP
208 MAPBGA3
GPIO[114]
E1UC[4]
SCK_1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
I/O
—
M
Tristate
—
—
—
95
F16
PH[3]
PCR[115] AF0
AF1
AF2
AF3
GPIO[115]
E1UC[5]
CS0_1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
I/O
—
M
Tristate
—
—
—
96
F15
PH[4]
PCR[116] AF0
AF1
AF2
AF3
GPIO[116]
E1UC[6]
—
—
SIUL
eMIOS_1
—
—
I/O
I/O
—
—
M
Tristate
—
—
—
134
A6
PH[5]
PCR[117] AF0
AF1
AF2
AF3
GPIO[117]
E1UC[7]
—
—
SIUL
eMIOS_1
—
—
I/O
I/O
—
—
S
Tristate
—
—
—
135
B6
PH[6]
PCR[118] AF0
AF1
AF2
AF3
GPIO[118]
E1UC[8]
—
MA[2]
SIUL
eMIOS_1
—
ADC
I/O
I/O
—
O
M
Tristate
—
—
—
136
D5
PH[7]
PCR[119] AF0
AF1
AF2
AF3
GPIO[119]
E1UC[9]
CS3_2
MA[1]
SIUL
eMIOS_1
DSPI_2
ADC
I/O
I/O
O
O
M
Tristate
—
—
—
137
C5
PH[8]
PCR[120] AF0
AF1
AF2
AF3
GPIO[120]
E1UC[10]
CS2_2
MA[0]
SIUL
eMIOS_1
DSPI_2
ADC
I/O
I/O
O
O
M
Tristate
—
—
—
138
A5
PH[9]9
PCR[121] AF0
AF1
AF2
AF3
GPIO[121]
—
TCK
—
SIUL
—
JTAGC
—
I/O
—
I
—
S
Input, weak
pull-up
60
60
88
127
B8
PH[10]9 PCR[122] AF0
AF1
AF2
AF3
GPIO[122]
—
TMS
—
SIUL
—
JTAGC
—
I/O
—
I
—
S
Input, weak
pull-up
53
53
81
120
B9
Alternate function1
PCR[114] AF0
AF1
AF2
AF3
PCR
PH[2]
Port pin
Function
Pin number
MPC5604B/C Microcontroller Data Sheet, Rev. 15
28
NXP Semiconductors
Package pinouts and signal descriptions
1
Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module.
PCR.PA = 00 → AF0; PCR.PA = 01 → AF1; PCR.PA = 10 → AF2; PCR.PA = 11 → AF3. This is intended to select
the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the
values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is
reported as “—”.
2
Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by
setting the values of the PSMIO.PADSELx bitfields inside the SIUL module.
3
208 MAPBGA available only as development package for Nexus2+
4
All WKPU pins also support external interrupt capability. See wakeup unit chapter for further details.
5
NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.
6
“Not applicable” because these functions are available only while the device is booting. Refer to BAM chapter of the
reference manual for details.
7
Value of PCR.IBE bit must be 0
8
Be aware that this pad is used on the MPC5607B 100-pin and 144-pin to provide VDD_HV_ADC and
VSS_HV_ADC1. Therefore, you should be careful in ensuring compatibility between MPC5604B/C and
MPC5607B.
9 Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
If the user configures these JTAG pins in GPIO mode the device is no longer compliant with IEEE 1149.1-2001.
10 The TDO pad has been moved into the STANDBY domain in order to allow low-power debug handshaking in
STANDBY mode. However, no pull-resistor is active on the TDO pad while in STANDBY mode. At this time the pad
is configured as an input. When no debugger is connected the TDO pad is floating causing additional current
consumption. To avoid the extra consumption TDO must be connected. An external pull-up resistor in the range of
47–100 kΩ should be added between the TDO pin and VDD_HV. Only in case the TDO pin is used as application
pin and a pull-up cannot be used then a pull-down resistor with the same value should be used between TDO pin
and GND instead.
11 Available only on MPC560xC versions, MPC5603B 64 LQFP, MPC5604B 64 LQFP and MPC5604B 208 MAPBGA
devices
12 Not available on MPC5602B devices
13 Not available in 100 LQFP package
14 Available only on MPC5604B 208 MAPBGA devices
15 Not available on MPC5603B 144-pin devices
2.7
Nexus 2+ pins
In the 208 MAPBGA package, eight additional debug pins are available (see Table 6).
Table 6. Nexus 2+ pin descriptions
Pin number
Debug pin
Function
I/O
direction
MCKO
Message clock out
O
F
MDO0
Message data out 0
O
MDO1
Message data out 1
MDO2
MDO3
Pad type
Function
after reset
100
LQFP
144
LQFP
208 MAP
BGA
—
—
—
T4
M
—
—
—
H15
O
M
—
—
—
H16
Message data out 2
O
M
—
—
—
H14
Message data out 3
O
M
—
—
—
H13
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
29
Package pinouts and signal descriptions
Table 6. Nexus 2+ pin descriptions (continued)
Pin number
Debug pin
Function
I/O
direction
EVTI
Event in
I
M
EVTO
Event out
O
MSEO
Message start/end out
O
Pad type
Function
after reset
100
LQFP
144
LQFP
208 MAP
BGA
Pull-up
—
—
K1
M
—
—
—
L4
M
—
—
—
G16
MPC5604B/C Microcontroller Data Sheet, Rev. 15
30
NXP Semiconductors
Package pinouts and signal descriptions
2.8
Electrical characteristics
2.9
Introduction
This section contains electrical characteristics of the device as well as temperature and power
considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However,
it is advisable to take precautions to avoid applying any voltage higher than the specified maximum rated
voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This
could be done by the internal pull-up and pull-down, which is provided by the product for most general
purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on
the system.
In the tables where the device logic provides signals with their respective timing characteristics, the
symbol “CC” for Controller Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to
the device, the symbol “SR” for System Requirement is included in the Symbol column.
2.10
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the classifications listed in Table 7 are used and the parameters are tagged
accordingly in the tables where appropriate.
Table 7. Parameter classifications
Classification tag
Tag description
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
31
Package pinouts and signal descriptions
2.11
NVUSRO register
Bit values in the Non-Volatile User Options (NVUSRO) Register control portions of the device
configuration, namely electrical parameters such as high voltage supply and oscillator margin, as well as
digital functionality (watchdog enable/disable after reset).
For a detailed description of the NVUSRO register, please refer to the device reference manual.
2.11.1
NVUSRO[PAD3V5V] field description
The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 8 shows how
NVUSRO[PAD3V5V] controls the device configuration.
Table 8. PAD3V5V field description
Value1
1
2.11.2
Description
0
High voltage supply is 5.0 V
1
High voltage supply is 3.3 V
Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
NVUSRO[OSCILLATOR_MARGIN] field description
The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value.
Table 9 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
Table 9. OSCILLATOR_MARGIN field description
Value1
1
2.11.3
Description
0
Low consumption configuration (4 MHz/8 MHz)
1
High margin configuration (4 MHz/16 MHz)
Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
NVUSRO[WATCHDOG_EN] field description
The watchdog enable/disable configuration after reset is dependent on the WATCHDOG_EN bit value.
Table 10 shows how NVUSRO[WATCHDOG_EN] controls the device configuration.
Table 10. WATCHDOG_EN field description
Value1
1
Description
0
Disable after reset
1
Enable after reset
Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
32
NXP Semiconductors
Package pinouts and signal descriptions
2.12
Absolute maximum ratings
Table 11. Absolute maximum ratings
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
0
0
V
VDD
SR Voltage on VDD_HV pins with respect to
ground (VSS)
—
−0.3
6.0
V
VSS_LV
SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground
(VSS)
—
VDD_BV
SR Voltage on VDD_BV pin (regulator
supply) with respect to ground (VSS)
—
Relative to VDD
VSS_ADC SR Voltage on VSS_HV_ADC (ADC
reference) pin with respect to ground
(VSS)
—
VDD_ADC SR Voltage on VDD_HV_ADC pin (ADC
reference) with respect to ground (VSS)
—
VIN
SR Voltage on any GPIO pin with respect to
ground (VSS)
VSS−0.1 VSS+0.1
−0.3
6.0
−0.3
VDD+0.3
VSS−0.1 VSS+0.1
−0.3
6.0
V
V
V
V
VDD −0.3 VDD+0.3
Relative to VDD
—
Relative to VDD
−0.3
6.0
—
VDD+0.3
V
IINJPAD
SR Injected input current on any pin during
overload condition
—
−10
10
IINJSUM
SR Absolute sum of all injected input
currents during overload condition
—
−50
50
—
70
—
64
—
—
150
mA
—
−55
150
°C
IAVGSEG SR Sum of all the static I/O current within a VDD = 5.0 V ± 10%, PAD3V5V = 0
supply segment
VDD = 3.3 V ± 10%, PAD3V5V = 1
ICORELV SR Low voltage static current sink through
VDD_BV
TSTORAGE SR Storage temperature
mA
mA
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of this specification are not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability. During overload conditions (VIN > VDD or
VIN < VSS), the voltage on pins with respect to ground (VSS) must not
exceed the recommended values.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
33
Package pinouts and signal descriptions
2.13
Recommended operating conditions
Table 12. Recommended operating conditions (3.3 V)
Value
Symbol
VSS
Parameter
0
0
V
SR Voltage on VDD_HV pins with respect to ground
(VSS)
—
3.0
3.6
V
VSS_LV2
SR Voltage on VSS_LV (low voltage digital supply)
pins with respect to ground (VSS)
—
VSS−0.1
VSS+0.1
V
VDD_BV3
SR Voltage on VDD_BV pin (regulator supply) with
respect to ground (VSS)
—
3.0
3.6
V
4
5
6
7
Relative to VDD VDD−0.1
VDD+0.1
VSS_ADC
SR Voltage on VSS_HV_ADC (ADC reference) pin
with respect to ground (VSS)
—
VSS−0.1
VSS+0.1
V
VDD_ADC4
SR Voltage on VDD_HV_ADC pin (ADC reference)
with respect to ground (VSS)
—
3.05
3.6
V
SR Voltage on any GPIO pin with respect to ground
(VSS)
Relative to VDD VDD−0.1
VDD+0.1
—
VSS−0.1
—
Relative to VDD
—
VDD+0.1
IINJPAD
SR Injected input current on any pin during overload
condition
—
−5
5
IINJSUM
SR Absolute sum of all injected input currents during
overload condition
—
−50
50
TVDD
SR VDD slope to ensure correct power up6
—
3.07
fCPU ≤ 64 MHz
−40
85
TJ C-Grade Part SR Junction temperature under bias
−40
110
TA V-Grade Part SR Ambient temperature under bias
−40
105
TJ V-Grade Part SR Junction temperature under bias
−40
130
TA M-Grade Part SR Ambient temperature under bias
−40
125
TJ M-Grade Part SR Junction temperature under bias
−40
150
TA C-Grade Part SR Ambient temperature under bias
3
Max
—
1
VIN
2
Unit
Min
SR Digital ground on VSS_HV pins
VDD
1
Conditions
V
mA
0.25[V/µs] V/s
)
°C
100 nF capacitance needs to be provided between each VDD/VSS pair
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
400 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL,
device is reset.
Guaranteed by device validation.
Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH).
MPC5604B/C Microcontroller Data Sheet, Rev. 15
34
NXP Semiconductors
Package pinouts and signal descriptions
Table 13. Recommended operating conditions (5.0 V)
Value
Symbol
3
4
5
6
7
Unit
Min
Max
SR Digital ground on VSS_HV pins
—
0
0
V
VDD1
SR Voltage on VDD_HV pins with respect to
ground (VSS)
—
4.5
5.5
V
Voltage drop2
3.0
5.5
VSS−0.1
VSS+0.1
V
4.5
5.5
V
3.0
5.5
Relative to VDD
VDD−0.1
VDD+0.1
VSS−0.1
VSS+0.1
V
4.5
5.5
V
3.0
5.5
Relative to VDD
VDD−0.1
VDD+0.1
—
VSS−0.1
—
Relative to VDD
—
VDD+0.1
VSS_LV3
SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground (VSS)
—
VDD_BV4
SR Voltage on VDD_BV pin (regulator supply)
with respect to ground (VSS)
—
Voltage drop
VSS_ADC
SR Voltage on VSS_HV_ADC (ADC reference)
pin with respect to ground (VSS
—
VDD_ADC5
SR Voltage on VDD_HV_ADC pin (ADC
reference) with respect to ground (VSS)
—
SR Voltage on any GPIO pin with respect to
ground (VSS)
Voltage drop
2
2
V
IINJPAD
SR Injected input current on any pin during
overload condition
—
−5
5
IINJSUM
SR Absolute sum of all injected input currents
during overload condition
—
−50
50
SR VDD slope to ensure correct power up6
—
3.07
0.25 V/µs
V/s
fCPU ≤ 64 MHz
−40
85
°C
TVDD
2
Conditions
VSS
VIN
1
Parameter
TA C-Grade Part
SR Ambient temperature under bias
TJ C-Grade Part
SR Junction temperature under bias
−40
110
TA V-Grade Part
SR Ambient temperature under bias
−40
105
TJ V-Grade Part
SR Junction temperature under bias
−40
130
TA M-Grade Part
SR Ambient temperature under bias
−40
125
TJ M-Grade Part
SR Junction temperature under bias
−40
150
mA
100 nF capacitance needs to be provided between each VDD/VSS pair.
Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain
analog electrical characteristics will not be guaranteed to stay within the stated limits.
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
100 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
1 µF (electrolithic/tantalum) + 47 nF (ceramic) capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
Another ceramic cap of 10 nF with low inductance package can be added.
Guaranteed by device validation.
Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH).
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
35
Package pinouts and signal descriptions
NOTE
RAM data retention is guaranteed with VDD_LV not below 1.08 V.
2.14
Thermal characteristics
2.14.1
Package thermal characteristics
Table 14. LQFP thermal characteristics1
Symbol
RθJA
CC
C
D
Parameter
Thermal resistance,
junction-to-ambient natural
convection3
Conditions2
Single-layer board - 1s
Four-layer board - 2s2p
RθJB
CC
D
Thermal resistance,
junction-to-board4
Single-layer board - 1s
Four-layer board - 2s2p
RθJC
CC
D
Thermal resistance,
junction-to-case5
Single-layer board - 1s
Four-layer board - 2s2p
ΨJB
CC
D
Junction-to-board thermal
characterization parameter,
natural convection
Single-layer board - 1s
Four-layer board - 2s2p
Pin count
Value
Unit
64
60
°C/W
100
64
144
64
64
42
100
51
144
49
64
24
100
36
144
37
64
24
100
34
144
35
64
11
100
22
144
22
64
11
100
22
144
22
64
TBD
100
33
144
34
64
TBD
100
34
144
35
°C/W
°C/W
°C/W
MPC5604B/C Microcontroller Data Sheet, Rev. 15
36
NXP Semiconductors
Package pinouts and signal descriptions
Table 14. LQFP thermal characteristics1 (continued)
Symbol
ΨJC
CC
C
D
Parameter
Junction-to-case thermal
characterization parameter,
natural convection
Conditions2
Single-layer board - 1s
Four-layer board - 2s2p
Pin count
Value
Unit
64
TBD
°C/W
100
9
144
10
64
TBD
100
9
144
10
1
Thermal characteristics are based on simulation.
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C
3
Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test
board meets JEDEC specification for this package.
4 Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
5 Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface
layer.
2
2.14.2
Power considerations
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1:
TJ = TA + (PD x RθJA)
Eqn. 1
Where:
TA is the ambient temperature in °C.
RθJA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PI/O (PD = PINT + PI/O).
PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power.
PI/O represents the power dissipation on input and output pins; user determined.
Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be
significant, if the device is configured to continuously drive external modules and/or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
PD = K / (TJ + 273 °C)
Eqn. 2
K = PD x (TA + 273 °C) + RθJA x PD2
Eqn. 3
Therefore, solving equations 1 and 2:
Where:
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
37
Package pinouts and signal descriptions
K is a constant for the particular part, which may be determined from Equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be
obtained by solving equations 1 and 2 iteratively for any value of TA.
2.15
2.15.1
I/O pad electrical characteristics
I/O pad types
The device provides four main I/O pad types depending on the associated alternate functions:
• Slow pads—These pads are the most common pads, providing a good compromise between
transition time and low electromagnetic emission.
• Medium pads—These pads provide transition fast enough for the serial communication channels
with controlled current to reduce electromagnetic emission.
• Fast pads—These pads provide maximum speed. There are used for improved Nexus debugging
capability.
• Input only pads—These pads are associated to ADC channels and the external 32 kHz crystal
oscillator (SXOSC) providing low input leakage.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of
reducing AC performance.
2.15.2
I/O input DC characteristics
Table 15 provides input DC electrical characteristics as described in Figure 7.
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1’
(GPDI register of SIUL)
PDIx = ‘0’
Figure 7. I/O input DC electrical characteristics definition
MPC5604B/C Microcontroller Data Sheet, Rev. 15
38
NXP Semiconductors
Package pinouts and signal descriptions
Table 15. I/O input DC electrical characteristics
Symbol
C
Typ
Max
SR P Input high level CMOS (Schmitt
Trigger)
—
0.65VDD
—
VDD+0.4
VIL
SR P Input low level CMOS (Schmitt
Trigger)
—
−0.4
—
0.35VDD
—
0.1VDD
—
—
TA = −40 °C
—
2
200
TA = 25 °C
—
2
200
D
TA = 85 °C
—
5
300
D
TA = 105 °C
—
12
500
P
TA = 125 °C
—
70
1000
ILKG CC D Digital input leakage
No injection
on adjacent
pin
D
WFI
2
WNFI
2
Unit
Min
VIH
VHYS CC C Input hysteresis CMOS (Schmitt
Trigger)
1
Value
Conditions1
Parameter
2
V
nA
SR P Wakeup input filtered pulse
—
—
—
40
ns
SR P Wakeup input not filtered pulse
—
1000
—
—
ns
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and
voltage.
2.15.3
I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
• Table 16 provides weak pull figures. Both pull-up and pull-down resistances are supported.
• Table 17 provides output driver characteristics for I/O pads when in SLOW configuration.
• Table 18 provides output driver characteristics for I/O pads when in MEDIUM configuration.
• Table 19 provides output driver characteristics for I/O pads when in FAST configuration.
Table 16. I/O pull-up/pull-down DC electrical characteristics
Symbol
C
Parameter
|IWPU| CC P Weak pull-up current
absolute value
C
P
P
1
2
Unit
Min
Typ
Max
PAD3V5V = 0
10
—
150
PAD3V5V = 12
10
—
250
PAD3V5V = 1
10
—
150
VIN = VIH, VDD = 5.0 V ± 10% PAD3V5V = 0
10
—
150
PAD3V5V = 1
10
—
250
VIN = VIH, VDD = 3.3 V ± 10% PAD3V5V = 1
10
—
150
VIN = VIL, VDD = 5.0 V ± 10%
VIN = VIL, VDD = 3.3 V ± 10%
|IWPD| CC P Weak pull-down current
absolute value
C
Value
Conditions1
µA
µA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
39
Package pinouts and signal descriptions
Table 17. SLOW configuration output buffer electrical characteristics
Symbol C
Parameter
Value
Conditions1
Push Pull IOH = −2 mA,
VOH CC P Output high level
SLOW configuration
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
Unit
Min
Typ
Max
0.8VDD
—
—
C
IOH = −2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
0.8VDD
—
—
C
IOH = −1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
VDD−0.8
—
—
—
—
0.1VDD
VOL CC P Output low level
Push Pull IOL = 2 mA,
SLOW configuration
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
1
2
C
IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
—
—
0.1VDD
C
IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
V
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 18. MEDIUM configuration output buffer electrical characteristics
Symbol C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
Push Pull IOH = −3.8 mA,
VOH CC C Output high level
MEDIUM configuration
VDD = 5.0 V ± 10%, PAD3V5V = 0
0.8VDD
—
—
P
IOH = −2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
0.8VDD
—
—
C
IOH = −1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
0.8VDD
—
—
C
IOH = −1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
VDD−0.8
—
—
C
IOH = −100 µA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
0.8VDD
—
—
V
MPC5604B/C Microcontroller Data Sheet, Rev. 15
40
NXP Semiconductors
Package pinouts and signal descriptions
Table 18. MEDIUM configuration output buffer electrical characteristics (continued)
Symbol C
VOL CC C Output low level
Push Pull IOL = 3.8 mA,
MEDIUM configuration
VDD = 5.0 V ± 10%, PAD3V5V = 0
1
2
Value
Conditions1
Parameter
Unit
Min
Typ
Max
—
—
0.2VDD
P
IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
C
IOL = 1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
—
—
0.1VDD
C
IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
C
IOL = 100 µA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
0.1VDD
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 19. FAST configuration output buffer electrical characteristics
Symbol C
VOH CC P Output high level
FAST configuration
1
Push Pull IOH = −14mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
Unit
Min
Typ
Max
0.8VDD
—
—
C
IOH = −7mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
0.8VDD
—
—
C
IOH = −11mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
VDD−0.8
—
—
—
—
0.1VDD
VOL CC P Output low level
FAST configuration
2
Value
Conditions1
Parameter
Push Pull IOL = 14mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
C
IOL = 7mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
—
—
0.1VDD
C
IOL = 11mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
V
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
41
Package pinouts and signal descriptions
2.15.4
Output pin transition times
Table 20. Output pin transition times
Symbol C
Value
Conditions1
Parameter
Unit
Min Typ Max
ttr
CC D Output transition time output
pin2
T
SLOW configuration
D
—
—
50
CL = 50 pF
—
—
100
CL = 100 pF
—
—
125
—
—
50
CL = 25 pF
T
CL = 50 pF
—
—
100
D
CL = 100 pF
—
—
125
—
—
10
—
—
20
—
—
40
—
—
12
—
—
25
—
—
40
—
—
4
CL = 50 pF
—
—
6
CL = 100 pF
—
—
12
—
—
4
CL = 50 pF
—
—
7
CL = 100 pF
—
—
12
CL = 25 pF
CL = 50 pF
CL = 25 pF
T
CL = 50 pF
D
CL = 100 pF
CL = 25 pF
CL = 25 pF
1
2
VDD = 3.3 V ± 10%, PAD3V5V = 1
VDD = 5.0 V ± 10%, PAD3V5V = 0
SIUL.PCRx.SRC = 1
CL = 100 pF
D
CC D Output transition time output
pin2
FAST configuration
ttr
VDD = 5.0 V ± 10%, PAD3V5V = 0
D
CC D Output transition time output
pin2
T
MEDIUM configuration
D
ttr
CL = 25 pF
VDD = 3.3 V ± 10%, PAD3V5V = 1
SIUL.PCRx.SRC = 1
VDD = 5.0 V ± 10%, PAD3V5V = 0
VDD = 3.3 V ± 10%, PAD3V5V = 1
ns
ns
ns
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
CL includes device and package capacitances (CPKG < 5 pF).
2.15.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a
VDD/VSS supply pair as described in Table 21.
Table 21. I/O supply segment
Supply segment
Package
1
208
MAPBGA1
2
3
4
Equivalent to 144 LQFP segment pad distribution
pin100–pin122 pin 123–pin19
5
6
MCKO
MDOn/MSEO
—
—
144 LQFP
pin20–pin49
pin51–pin99
100 LQFP
pin16–pin35
pin37–pin69
pin70–pin83
pin 84–pin15
—
—
64 LQFP
pin8–pin26
pin28–pin55
pin56–pin7
—
—
—
MPC5604B/C Microcontroller Data Sheet, Rev. 15
42
NXP Semiconductors
Package pinouts and signal descriptions
1
208 MAPBGA available only as development package for Nexus2+
Table 22 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment should remain below
the IAVGSEG maximum value.
Table 22. I/O consumption
Symbol
C
ISWTSLW,2 CC D Dynamic I/O current for CL = 25 pF
SLOW configuration
ISWTMED2 CC D Dynamic I/O current for CL = 25 pF
MEDIUM configuration
ISWTFST2 CC D Dynamic I/O current for CL = 25 pF
FAST configuration
IRMSSLW CC D Root mean square I/O
current for SLOW
configuration
CL = 25 pF, 2 MHz
CL = 25 pF, 4 MHz
CL = 25 pF, 2 MHz
CL = 25 pF, 4 MHz
Typ
Max
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
20
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
16
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
29
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
17
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
110
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
50
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
2.3
—
—
3.2
—
—
6.6
—
—
1.6
—
—
2.3
—
—
4.7
—
—
6.6
—
—
13.4
—
—
18.3
—
—
5
—
—
8.5
—
—
11
—
—
22
—
—
33
—
—
56
—
—
14
—
—
20
—
—
35
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF, 2 MHz
CL = 25 pF, 13 MHz
CL = 25 pF, 40 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
CL = 100 pF, 13 MHz
CL = 25 pF, 13 MHz
CL = 25 pF, 40 MHz
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF, 13 MHz
IRMSFST CC D Root mean square I/O
current for FAST
configuration
CL = 25 pF, 40 MHz
CL = 25 pF, 64 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
CL = 100 pF, 40 MHz
CL = 25 pF, 40 MHz
CL = 25 pF, 64 MHz
Unit
Min
CL = 100 pF, 2 MHz
IRMSMED CC D Root mean square I/O
current for MEDIUM
configuration
Value
Conditions1
Parameter
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF, 40 MHz
mA
mA
mA
mA
mA
mA
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
43
Package pinouts and signal descriptions
Table 22. I/O consumption (continued)
Symbol
IAVGSEG
1
2
C
Value
Conditions1
Parameter
Unit
Min
Typ
Max
—
—
70
—
—
65
SR D Sum of all the static I/O VDD = 5.0 V ± 10%, PAD3V5V = 0
current within a supply
VDD = 3.3 V ± 10%, PAD3V5V = 1
segment
mA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to125 °C, unless otherwise specified
Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
Table 23 provides the weight of concurrent switching I/Os.
Due to the dynamic current limitations, the sum of the weight of concurrent switching I/Os on a single
segment must not exceed 100% to ensure device functionality.
Table 23. I/O weight1
144/100 LQFP
64 LQFP
Supply segment
Pad
144
100
64
LQFP LQFP LQFP2
4
4
4
3
Weight 5 V
Weight 3.3 V
Weight 5 V
Weight 3.3 V
SRC3 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
PB[3]
10%
—
12%
—
10%
—
12%
—
PC[9]
10%
—
12%
—
10%
—
12%
—
—
PC[14]
9%
—
11%
—
—
—
—
—
—
PC[15]
9%
13%
11%
12%
—
—
—
—
—
—
PG[5]
9%
—
11%
—
—
—
—
—
—
—
PG[4]
9%
12%
10%
11%
—
—
—
—
—
—
PG[3]
9%
—
10%
—
—
—
—
—
—
—
PG[2]
8%
12%
10%
10%
—
—
—
—
4
3
PA[2]
8%
—
9%
—
8%
—
9%
—
—
PE[0]
8%
—
9%
—
—
—
—
—
3
PA[1]
7%
—
9%
—
7%
—
9%
—
—
PE[1]
7%
10%
8%
9%
—
—
—
—
—
PE[8]
7%
9%
8%
8%
—
—
—
—
—
PE[9]
6%
—
7%
—
—
—
—
—
—
PE[10]
6%
—
7%
—
—
—
—
—
3
PA[0]
5%
8%
6%
7%
5%
8%
6%
7%
—
PE[11]
5%
—
6%
—
—
—
—
—
MPC5604B/C Microcontroller Data Sheet, Rev. 15
44
NXP Semiconductors
Package pinouts and signal descriptions
Table 23. I/O weight1 (continued)
144/100 LQFP
64 LQFP
Supply segment
Pad
144
100
64
LQFP LQFP LQFP2
1
Weight 5 V
Weight 3.3 V
Weight 5 V
Weight 3.3 V
SRC3 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
—
—
PG[9]
9%
—
10%
—
—
—
—
—
—
—
PG[8]
9%
—
11%
—
—
—
—
—
1
—
PC[11]
9%
—
11%
—
—
—
—
—
1
PC[10]
9%
13%
11%
12%
9%
13%
11%
12%
—
—
PG[7]
10%
14%
11%
12%
—
—
—
—
—
—
PG[6]
10%
14%
12%
12%
—
—
—
—
1
1
PB[0]
10%
14%
12%
12%
10%
14%
12%
12%
PB[1]
10%
—
12%
—
10%
—
12%
—
—
—
PF[9]
10%
—
12%
—
—
—
—
—
—
—
PF[8]
10%
15%
12%
13%
—
—
—
—
—
—
PF[12]
10%
15%
12%
13%
—
—
—
—
1
1
PC[6]
10%
—
12%
—
10%
—
12%
—
PC[7]
10%
—
12%
—
10%
—
12%
—
—
—
PF[10]
10%
14%
12%
12%
—
—
—
—
—
—
PF[11]
10%
—
11%
—
—
—
—
—
1
1
PA[15]
9%
12%
10%
11%
9%
12%
10%
11%
—
—
PF[13]
8%
—
10%
—
—
—
—
—
1
1
PA[14]
8%
11%
9%
10%
8%
11%
9%
10%
PA[4]
8%
—
9%
—
8%
—
9%
—
PA[13]
7%
10%
9%
9%
7%
10%
9%
9%
PA[12]
7%
—
8%
—
7%
—
8%
—
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
45
Package pinouts and signal descriptions
Table 23. I/O weight1 (continued)
144/100 LQFP
64 LQFP
Supply segment
Pad
144
100
64
LQFP LQFP LQFP2
2
2
2
Weight 5 V
Weight 3.3 V
Weight 5 V
Weight 3.3 V
SRC3 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
PB[9]
1%
—
1%
—
1%
—
1%
—
PB[8]
1%
—
1%
—
1%
—
1%
—
PB[10]
6%
—
7%
—
6%
—
7%
—
—
—
PF[0]
6%
—
7%
—
—
—
—
—
—
—
PF[1]
7%
—
8%
—
—
—
—
—
—
—
PF[2]
7%
—
8%
—
—
—
—
—
—
—
PF[3]
7%
—
9%
—
—
—
—
—
—
—
PF[4]
8%
—
9%
—
—
—
—
—
—
—
PF[5]
8%
—
10%
—
—
—
—
—
—
—
PF[6]
8%
—
10%
—
—
—
—
—
—
—
PF[7]
9%
—
10%
—
—
—
—
—
2
—
PD[0]
1%
—
1%
—
—
—
—
—
—
PD[1]
1%
—
1%
—
—
—
—
—
—
PD[2]
1%
—
1%
—
—
—
—
—
—
PD[3]
1%
—
1%
—
—
—
—
—
—
PD[4]
1%
—
1%
—
—
—
—
—
—
PD[5]
1%
—
1%
—
—
—
—
—
—
PD[6]
1%
—
1%
—
—
—
—
—
—
PD[7]
1%
—
1%
—
—
—
—
—
—
PD[8]
1%
—
1%
—
—
—
—
—
2
PB[4]
1%
—
1%
—
1%
—
1%
—
PB[5]
1%
—
1%
—
1%
—
2%
—
PB[6]
1%
—
1%
—
1%
—
2%
—
PB[7]
1%
—
1%
—
1%
—
2%
—
—
PD[9]
1%
—
1%
—
—
—
—
—
—
PD[10]
1%
—
1%
—
—
—
—
—
—
PD[11]
1%
—
1%
—
—
—
—
—
2
PB[11]
11%
—
13%
—
17%
—
21%
—
—
PD[12]
11%
—
13%
—
—
—
—
—
2
PB[12]
11%
—
13%
—
18%
—
21%
—
—
PD[13]
10%
—
12%
—
—
—
—
—
MPC5604B/C Microcontroller Data Sheet, Rev. 15
46
NXP Semiconductors
Package pinouts and signal descriptions
Table 23. I/O weight1 (continued)
144/100 LQFP
64 LQFP
Supply segment
Pad
144
100
64
LQFP LQFP LQFP2
2
3
2
Weight 5 V
Weight 3.3 V
Weight 5 V
Weight 3.3 V
SRC3 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
2
PB[13]
10%
—
12%
—
18%
—
21%
—
—
PD[14]
10%
—
12%
—
—
—
—
—
2
PB[14]
10%
—
12%
—
18%
—
21%
—
—
PD[15]
10%
—
11%
—
—
—
—
—
2
PB[15]
9%
—
11%
—
18%
—
21%
—
PA[3]
9%
—
11%
—
18%
—
21%
—
—
—
PG[13]
9%
13%
10%
11%
—
—
—
—
—
—
PG[12]
9%
12%
10%
11%
—
—
—
—
—
—
PH[0]
5%
8%
6%
7%
—
—
—
—
—
—
PH[1]
5%
7%
6%
6%
—
—
—
—
—
—
PH[2]
5%
6%
5%
6%
—
—
—
—
—
—
PH[3]
4%
6%
5%
5%
—
—
—
—
—
—
PG[1]
4%
—
4%
—
—
—
—
—
—
—
PG[0]
3%
4%
4%
4%
—
—
—
—
—
—
PF[15]
3%
—
4%
—
—
—
—
—
—
—
PF[14]
4%
5%
5%
5%
—
—
—
—
—
—
PE[13]
4%
—
5%
—
—
—
—
—
3
2
PA[7]
5%
—
6%
—
16%
—
19%
—
PA[8]
5%
—
6%
—
16%
—
19%
—
PA[9]
5%
—
6%
—
15%
—
18%
—
PA[10]
6%
—
7%
—
15%
—
18%
—
PA[11]
6%
—
8%
—
14%
—
17%
—
—
PE[12]
7%
—
8%
—
—
—
—
—
—
—
PG[14]
7%
—
8%
—
—
—
—
—
—
—
PG[15]
7%
10%
8%
9%
—
—
—
—
—
—
PE[14]
7%
—
8%
—
—
—
—
—
—
—
PE[15]
7%
9%
8%
8%
—
—
—
—
—
—
PG[10]
6%
—
8%
—
—
—
—
—
—
—
PG[11]
6%
9%
7%
8%
—
—
—
—
3
2
PC[3]
6%
—
7%
—
7%
—
9%
—
PC[2]
6%
8%
7%
7%
6%
9%
8%
8%
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
47
Package pinouts and signal descriptions
Table 23. I/O weight1 (continued)
144/100 LQFP
64 LQFP
Supply segment
Pad
144
100
64
LQFP LQFP LQFP2
3
4
3
Weight 3.3 V
Weight 5 V
Weight 3.3 V
SRC3 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
PA[5]
5%
7%
6%
6%
6%
8%
7%
7%
PA[6]
5%
—
6%
—
5%
—
6%
—
PH[10]
4%
6%
5%
5%
5%
7%
6%
6%
PC[1]
5%
—
5%
—
5%
—
5%
—
PC[0]
6%
9%
7%
8%
6%
9%
7%
8%
PH[9]
7
7
8
8
7
7
8
8
—
PE[2]
7%
10%
9%
9%
—
—
—
—
—
PE[3]
8%
11%
9%
9%
—
—
—
—
3
PC[5]
8%
11%
9%
10%
8%
11%
9%
10%
PC[4]
8%
12%
10%
10%
8%
12%
10%
10%
—
PE[4]
8%
12%
10%
11%
—
—
—
—
—
PE[5]
9%
12%
10%
11%
—
—
—
—
—
—
PH[4]
9%
13%
11%
11%
—
—
—
—
—
—
PH[5]
9%
—
11%
—
—
—
—
—
—
—
PH[6]
9%
13%
11%
12%
—
—
—
—
—
—
PH[7]
9%
13%
11%
12%
—
—
—
—
—
—
PH[8]
10%
14%
11%
12%
—
—
—
—
4
—
PE[6]
10%
14%
12%
12%
—
—
—
—
—
PE[7]
10%
14%
12%
12%
—
—
—
—
—
PC[12]
10%
14%
12%
13%
—
—
—
—
—
PC[13]
10%
—
12%
—
—
—
—
—
3
PC[8]
10%
—
12%
—
10%
—
12%
—
PB[2]
10%
15%
12%
13%
10%
15%
12%
13%
4
2
Weight 5 V
3
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to125 °C, unless otherwise specified
Segments shown apply to MPC560xB devices only
3 SRC: “Slew Rate Control” bit in SIU_PCR
2
2.16
RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
48
NXP Semiconductors
Package pinouts and signal descriptions
VDD
VDDMIN
RESET
VIH
VIL
device reset forced by RESET
device start-up phase
Figure 8. Start-up reset requirements
VRESET
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
WFRST
filtered by
lowpass filter
unknown reset
state
device under hardware reset
WFRST
WNFRST
Figure 9. Noise filtering on reset signal
Table 24. Reset electrical characteristics
Symbol
VIH
C
Parameter
SR P Input High Level CMOS
(Schmitt Trigger)
Value
Conditions1
—
Unit
Min
Typ
Max
0.65VDD
—
VDD+0.4
V
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
49
Package pinouts and signal descriptions
Table 24. Reset electrical characteristics (continued)
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
VIL
SR P Input low Level CMOS
(Schmitt Trigger)
—
−0.4
—
0.35VDD
V
VHYS
CC C Input hysteresis CMOS
(Schmitt Trigger)
—
0.1VDD
—
—
V
VOL
CC P Output low level
Push Pull, IOL = 2mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
V
C
Push Pull, IOL = 1mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
—
—
0.1VDD
C
Push Pull, IOL = 1mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
CL = 25pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
10
CL = 50pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
20
CL = 100pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
40
CL = 25pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
12
CL = 50pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
25
CL = 100pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
40
WFRST SR P RESET input filtered
pulse
—
—
—
40
ns
WNFRST SR P RESET input not filtered
pulse
—
1000
—
—
ns
VDD = 3.3 V ± 10%, PAD3V5V = 1
10
—
150
µA
VDD = 5.0 V ± 10%, PAD3V5V = 0
10
—
150
10
—
250
ttr
CC D Output transition time
output pin3
|IWPU| CC P Weak pull-up current
absolute value
D
P
VDD = 5.0 V ± 10%, PAD3V5V =
12
ns
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
This transient configuration does not occurs when device is used in the VDD = 3.3 V ± 10% range.
3 C includes device and package capacitance (C
L
PKG < 5 pF).
2
MPC5604B/C Microcontroller Data Sheet, Rev. 15
50
NXP Semiconductors
Package pinouts and signal descriptions
2.17
2.17.1
Power management electrical characteristics
Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from
the high voltage ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD.
The following supplies are involved:
• HV—High voltage external power supply for voltage regulator module. This must be provided
externally through VDD_HV power pin.
• BV—High voltage external power supply for internal ballast module. This must be provided
externally through VDD_BV power pin. Voltage values should be aligned with VDD.
• LV—Low voltage internal power supply for core, FMPLL and flash digital logic. This is generated
by the internal voltage regulator but provided outside to connect stability capacitor. It is further
split into four main domains to ensure noise isolation between critical LV modules within the
device:
— LV_COR—Low voltage supply for the core. It is also used to provide supply for FMPLL
through double bonding.
— LV_CFLA—Low voltage supply for code flash module. It is supplied with dedicated ballast
and shorted to LV_COR through double bonding.
— LV_DFLA—Low voltage supply for data flash module. It is supplied with dedicated ballast
and shorted to LV_COR through double bonding.
— LV_PLL—Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
51
Package pinouts and signal descriptions
CREG2 (LV_COR/LV_CFLA)
VDD_HV
VSS_LV
VDD_BV
Voltage Regulator
I
VSS_LVn
DEVICE
VDD_BV
CREG1 (LV_COR/LV_DFLA)
VDD_LVn
CDEC1 (Ballast decoupling)
VREF
VDD_LV
VDD_LV
DEVICE
VSS_LV
VSS_LV
VDD_LV
CREG3
(LV_COR/LV_PLL)
VSS_HV
VDD_HV
CDEC2
(supply/IO decoupling)
Figure 10. Voltage regulator capacitance connection
The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order
to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as
near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board
to less than 5 nH.
Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to
ensure stable voltage (see 2.13, Recommended operating conditions).
The internal voltage regulator requires a controlled slew rate of both VDD_HV and VDD_BV as described in
Figure 11.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
52
NXP Semiconductors
Package pinouts and signal descriptions
VDD_HV
VDD_HV(MAX)
d
VDD
dt
VDD_HV(MIN)
POWER UP
FUNCTIONAL RANGE
POWER DOWN
Figure 11. VDD_HV and VDD_BV maximum slope
When STANDBY mode is used, further constraints are applied to the both VDD_HV and VDD_BV in order
to guarantee correct regulator function during STANDBY exit. This is described on Figure 12.
STANDBY regulator constraints should normally be guaranteed by implementing equivalent of CSTDBY
capacitance on application board (capacitance and ESR typical values), but would actually depend on
exact characteristics of application external regulator.
VDD_HV
VDD_HV
VDD_HV(MAX)
ΔVDD(STDBY)
ΔVDD(STDBY)
VDD_HV(MIN)
d
VDD ( STDBY )
dt
VDD_LV
VDD_LV(NOMINAL)
0V
Figure 12. VDD_HV and VDD_BV supply constraints during STANDBY mode exit
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
53
Package pinouts and signal descriptions
Table 25. Voltage regulator electrical characteristics
Symbol
C
Parameter
Value
Conditions1
CREGn
SR — Internal voltage regulator external
capacitance
—
RREG
SR — Stability capacitor equivalent serial Range:
resistance
10 kHz to 20 MHz
CDEC1
SR — Decoupling capacitance2 ballast
Unit
Min
Typ
Max
200
—
500
nF
—
—
0.2
Ω
4704
—
nF
VDD_BV/VSS_LV pair:
1003
VDD_BV = 4.5 V to 5.5 V
VDD_BV/VSS_LV pair:
VDD_BV = 3 V to 3.6 V
400
—
CDEC2
SR — Decoupling capacitance regulator VDD/VSS pair
supply
10
100
d
VDD
dt
SR — Maximum slope on VDD
—
—
250 mV/µs
SR — Maximum instant variation on VDD
during standby exit
—
—
30
mV
SR — Maximum slope on VDD during
standby exit
—
—
15
mV/µs
—
1.32
—
V
1.16
1.28
—
—
—
150
mA
mA
|ΔVDD(STDBY)|
—
nF
d
VDD ( STDBY )
dt
VMREG
CC T Main regulator output voltage
P
IMREG
IMREGINT
Before exiting from
reset
After trimming
SR — Main regulator current provided to
VDD_LV domain
—
CC D Main regulator module current
consumption
IMREG = 200 mA
—
—
2
IMREG = 0 mA
—
—
1
VLPREG
CC P Low power regulator output
voltage
After trimming
1.16
1.28
—
V
ILPREG
SR — Low power regulator current
provided to VDD_LV domain
—
—
15
mA
ILPREGINT
CC D Low power regulator module
current consumption
ILPREG = 15 mA;
TA = 55 °C
—
—
600
µA
ILPREG = 0 mA;
TA = 55 °C
—
5
—
After trimming
1.16
1.28
—
—
VULPREG
CC P Ultra low power regulator output
voltage
—
V
MPC5604B/C Microcontroller Data Sheet, Rev. 15
54
NXP Semiconductors
Package pinouts and signal descriptions
Table 25. Voltage regulator electrical characteristics (continued)
Symbol
2
3
4
5
6
Parameter
IULPREG
SR — Ultra low power regulator current
provided to VDD_LV domain
IULPREGINT
CC D Ultra low power regulator module
current consumption
IDD_BV
1
C
CC D In-rush average current on VDD_BV
during power-up5
Value
Conditions1
Unit
Min
Typ
Max
—
—
5
mA
IULPREG = 5 mA;
TA = 55 °C
—
—
100
µA
IULPREG = 0 mA;
TA = 55 °C
—
2
—
—
—
3006
—
—
mA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage.
A typical value is in the range of 470 nF.
This value is acceptable to guarantee operation from 4.5 V to 5.5 V
External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV
in operating range.
In-rush average current is seen only for short time (maximum 20 µs) during power-up and on standby exit. It is
dependant on the sum of the CREGn capacitances.
The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must
be sized accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.
The |ΔVDD(STDBY)| and dVDD(STDBY)/dt system requirement can be used to define the component used
for the VDD supply generation. The following two examples describe how to calculate capacitance size:
Example 1. No regulator (worst case)
The |ΔVDD(STDBY)| parameter can be seen as the VDD voltage drop through the ESR resistance of the
regulator stability capacitor when the IDD_BV current required to load VDD_LV domain during the standby
exit. It is thus possible to define the maximum equivalent resistance ESRSTDBY(MAX) of the total
capacitance on the VDD supply:
ESRSTDBY(MAX) = |ΔVDD(STDBY)|/IDD_BV = (30 mV)/(300 mA) = 0.1Ω 1
The dVDD(STDBY)/dt parameter can be seen as the VDD voltage drop at the capacitance pin (excluding
ESR drop) while providing the IDD_BV supply required to load VDD_LV domain during the standby exit. It
is thus possible to define the minimum equivalent capacitance CSTDBY(MIN) of the total capacitance on
the VDD supply:
CSTDBY(MIN) = IDD_BV/dVDD(STDBY)/dt = (300 mA)/(15 mV/µs) = 20 µF
This configuration is a worst case, with the assumption no regulator is available.
1. Based on typical time for standby exit sequence of 20 µs, ESR(MIN) can actually be considered at ~50 kHz.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
55
Package pinouts and signal descriptions
Example 2. Simplified regulator
The regulator should be able to provide significant amount of the current during the standby exit process.
For example, in case of an ideal voltage regulator providing 200 mA current, it is possible to recalculate
the equivalent ESRSTDBY(MAX) and CSTDBY(MIN) as follows:
ESRSTDBY(MAX) = |ΔVDD(STDBY)|/(IDD_BV − 200 mA) = (30 mV)/(100 mA) = 0.3 Ω
CSTDBY(MIN) = (IDD_BV − 200 mA)/dVDD(STDBY)/dt = (300 mA − 200 mA)/(15 mV/µs) = 6.7 µF
In case optimization is required, CSTDBY(MIN) and ESRSTDBY(MAX) should be calculated based on the
regulator characteristics as well as the board VDD plane characteristics.
2.17.2
Low voltage detector electrical characteristics
The device implements a Power-on Reset (POR) module to ensure correct power-up initialization, as well
as four low voltage detectors (LVDs) to monitor the VDD and the VDD_LV voltage while device is supplied:
• POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state
(refer to RGM Destructive Event Status (RGM_DES) Register flag F_POR in device reference
manual)
• LVDHV3 monitors VDD to ensure device reset below minimum functional supply (refer to RGM
Destructive Event Status (RGM_DES) Register flag F_LVD27 in device reference manual)
• LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range (refer to RGM
Functional Event Status (RGM_FES) Register flag F_LVD45 in device reference manual)
• LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status (RGM_DES)
Register flag F_LVD12_PD1 in device reference manual
• LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status (RGM_DES)
Register flag F_LVD12_PD0 in device reference manual)
NOTE
When enabled, power domain No. 2 is monitored through LVDLVBKP.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
56
NXP Semiconductors
Package pinouts and signal descriptions
VDD
VLVDHVxH
VLVDHVxL
RESET
Figure 13. Low voltage detector vs reset
NOTE
Figure 13 does not apply to LVDHV5 low voltage detector because
LVDHV5 is automatically disabled during reset and it must be enabled by
software again. Once the device is forced to reset by LVDHV5, the
LVDHV5 is disabled and reset is released as soon as internal reset sequence
is completed regardless of LVDHV5H threshold.
Table 26. Low voltage detector electrical characteristics
Symbol
C
Parameter
VPORUP
SR P Supply for functional POR module
VPORH
CC P Power-on reset threshold
T
Value
Conditions1
Unit
Min
Typ
Max
1.0
—
5.5
1.5
—
2.6
—
1.5
—
2.6
—
—
—
2.95
—
TA = 25 °C,
after trimming
VLVDHV3H
CC T LVDHV3 low voltage detector high threshold
VLVDHV3L
CC P LVDHV3 low voltage detector low threshold
2.6
—
2.9
VLVDHV5H
CC T LVDHV5 low voltage detector high threshold
—
—
4.5
VLVDHV5L
CC P LVDHV5 low voltage detector low threshold
3.8
—
4.4
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold
1.08
—
1.16
VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold
1.08
—
1.16
1
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
57
Package pinouts and signal descriptions
2.18
Power consumption
Table 27 provides DC electrical characteristics for significant application modes. These values are
indicative values; actual consumption depends on the application.
Table 27. Power consumption on VDD_BV and VDD_HV
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
—
115
1403
mA
mA
IDDMAX2
CC D RUN mode maximum
average current
IDDRUN4
CC T RUN mode typical average fCPU = 8 MHz
current5
T
fCPU = 16 MHz
—
7
—
—
18
—
T
fCPU = 32 MHz
—
29
—
P
fCPU = 48 MHz
—
40
100
fCPU = 64 MHz
—
51
125
Slow internal RC oscillator TA = 25 °C
(128 kHz) running
TA = 125 °C
—
8
15
—
14
25
—
180
7008
D
Slow internal RC oscillator TA = 25 °C
(128 kHz) running
TA = 55 °C
—
500
—
D
TA = 85 °C
—
1
68
P
IDDHALT
CC C HALT mode
current6
P
IDDSTOP
IDDSTDBY2
IDDSTDBY1
CC P STOP mode current7
—
D
TA = 105 °C
—
2
98
P
TA = 125 °C
—
4.5
128
CC P STANDBY2 mode current9 Slow internal RC oscillator TA = 25 °C
(128 kHz) running
D
TA = 55 °C
—
30
100
—
75
—
D
TA = 85 °C
—
180
700
D
TA = 105 °C
—
315
1000
P
TA = 125 °C
—
560
1700
Slow internal RC oscillator TA = 25 °C
(128 kHz) running
TA = 55 °C
—
20
60
—
45
—
D
TA = 85 °C
—
100
350
D
TA = 105 °C
—
165
500
D
TA = 125 °C
—
280
900
CC T STANDBY1 mode
current10
D
mA
µA
mA
µA
µA
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
IDDMAX is drawn only from the VDD_BV pin. Running consumption does not include I/Os toggling which is highly
dependent on the application. The given value is thought to be a worst case value with all peripherals running, and
code fetched from code flash while modify operation ongoing on data flash. Notice that this value can be significantly
reduced by application: switch off not used peripherals (default), reduce peripheral frequency through internal
prescaler, fetch from RAM most used functions, use low power mode when possible.
3
Higher current may be sinked by device during power-up and standby exit. Please refer to in rush current on Table 25.
4 I
DDRUN is drawn only from the VDD_BV pin. RUN current measured with typical application with accesses on both flash
and RAM.
2
MPC5604B/C Microcontroller Data Sheet, Rev. 15
58
NXP Semiconductors
Package pinouts and signal descriptions
5
Only for the “P” classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and
LIN in loop back mode, DSPI as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and
running at max frequency, periodic SW/WDG timer reset enabled.
6
Data Flash Power Down. Code Flash in Low Power. SIRC (128 kHz) and FIRC (16 MHz) on. 10 MHz XTAL clock.
FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clock gated. LINFlex:
instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 clock gated. eMIOS: instance: 0 ON (16
channels on PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked
but no communication). RTC/API ON. PIT ON. STM ON. ADC ON but not conversion except 2 analog watchdog.
7
Only for the “P” classification: No clock, FIRC (16 MHz) off, SIRC (128 kHz) on, PLL off, HPvreg off,
ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode.
8
When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main
regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction
temperatures exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the
maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to
the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA.
9
Only for the “P” classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum
consumption, all possible modules switched off.
10 ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules
switched off.
2.19
Flash memory electrical characteristics
2.19.1
Program/Erase characteristics
Table 28 shows the program and erase characteristics.
Table 28. Program and erase specifications
Value
Symbol
C
Parameter
Tdwprogram CC C Double word (64 bits) program time4
Unit
Min
Typ1
Initial
max2
Max3
—
22
50
500
µs
T16Kpperase
16 KB block preprogram and erase time
—
300
500
5000
ms
T32Kpperase
32 KB block preprogram and erase time
—
400
600
5000
ms
T128Kpperase
128 KB block preprogram and erase time
—
800
1300
7500
ms
—
—
30
30
µs
Tesus
CC D Erase suspend latency
1
Typical program and erase times assume nominal supply values and operation at 25 °C.
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4 Actual hardware programming times. This does not include software overhead.
2
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
59
Package pinouts and signal descriptions
Table 29. Flash module life
Value
Symbol
C
Parameter
Conditions
Unit
CC C Number of program/erase cycles 16 KB blocks
per block over the operating
32 KB blocks
temperature range (TJ)
128 KB blocks
P/E
Min
Typ
Max
100,000
—
—
10,000 100,000
—
1,000
100,000
—
20
—
—
Blocks with
1,001–10,000 P/E cycles
10
—
—
Blocks with
10,001–100,000 P/E cycles
5
—
—
Retention CC C Minimum data retention at 85 °C Blocks with
average ambient temperature1
0–1,000 P/E cycles
1
cycles
years
Ambient temperature averaged over duration of application, not to exceed recommended product operating
temperature range.
ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability
results. Some units will experience single bit corrections throughout the life of the product with no impact
to product reliability.
Table 30. Flash read access timing
Symbol
fREAD
1
2.19.2
C
Conditions1
Parameter
Max
Unit
2 wait states
64
MHz
C
1 wait state
40
C
0 wait states
20
CC P Maximum frequency for Flash reading
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
Flash power supply DC characteristics
Table 31 shows the power supply DC characteristics on external supply.
Table 31. Flash memory power supply DC electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
Code flash memory module read
IFREAD2 CC D Sum of the current consumption on
VDD_HV and VDD_BV on read access fCPU = 64 MHz3
—
15
33
Data flash memory module read
fCPU = 64 MHz3
—
15
33
mA
MPC5604B/C Microcontroller Data Sheet, Rev. 15
60
NXP Semiconductors
Package pinouts and signal descriptions
Table 31. Flash memory power supply DC electrical characteristics
Symbol
C
IFMOD2 CC D Sum of the current consumption on
VDD_HV and VDD_BV on matrix
modification (program/erase)
IFLPW
IFPWD
CC D Sum of the current consumption on
VDD_HV and VDD_BV
CC D Sum of the current consumption on
VDD_HV and VDD_BV
Value
Conditions1
Parameter
Unit
Min
Typ
Max
Program/Erase ongoing while
reading code flash memory
registers fCPU = 64 MHz3
—
15
33
Program/Erase ongoing while
reading data flash memory
registers fCPU = 64 MHz3
—
15
33
During code flash memory
low-power mode
—
—
900
During data flash memory
low-power mode
—
—
900
During code flash memory
power-down mode
—
—
150
During data flash memory
power-down mode
—
—
150
mA
µA
µA
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
This value is only relative to the actual duration of the read cycle
3 f
CPU 64 MHz can be achieved only at up to 105 °C
2
2.19.3
Start-up/Switch-off timings
Table 32. Start-up time/Switch-off time
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
Code Flash
—
—
125
Data Flash
—
—
125
CC T Delay for Flash module to exit low-power
mode
T
Code Flash
—
—
0.5
Data Flash
—
—
0.5
CC T Delay for Flash module to exit power-down
mode
T
Code Flash
—
—
30
Data Flash
—
—
30
TFLALPENTRY CC T Delay for Flash module to enter low-power
mode
T
Code Flash
—
—
0.5
Data Flash
—
—
0.5
TFLAPDENTRY CC T Delay for Flash module to enter power-down
T mode
Code Flash
—
—
1.5
Data Flash
—
—
1.5
TFLARSTEXIT
CC T Delay for Flash module to exit reset mode
T
TFLALPEXIT
TFLAPDEXIT
1
2.20
µs
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
61
Package pinouts and signal descriptions
2.20.1
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application
environment and simplified MCU software. It should be noted that good EMC performance is highly
dependent on the user application and the software in particular.
Therefore it is recommended that the user apply EMC software optimization and prequalification tests in
relation with the EMC level requested for his application.
• Software recommendations: The software flowchart must include the management of runaway
conditions such as:
— Corrupted program counter
— Unexpected reset
— Critical data corruption (control registers...)
• Prequalification trials: Most of the common failures (unexpected reset and program counter
corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins
for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When unexpected
behavior is detected, the software can be hardened to prevent unrecoverable errors occurring.
2.20.2
Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission test conforms
to the IEC 61967-1 standard, which specifies the general conditions for EMI measurements.
Table 33. EMI radiated emission measurement1,2
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
—
0.150
—
fCPU SR — Operating frequency
—
—
64
—
MHz
VDD_LV SR — LV operating voltages
—
—
1.28
—
V
No PLL frequency
VDD = 5 V, TA = 25 °C,
modulation
LQFP144 package
Test conforming to IEC 61967-2,
±2% PLL frequency
fOSC = 8 MHz/fCPU = 64 MHz
modulation
—
—
18
dBµV
—
—
14
dBµV
—
SR — Scan range
SEMI CC T Peak level
1
2
Max
1000 MHz
EMI testing and I/O port waveforms per IEC 61967-1, -2, -4
For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your
local marketing representative.
2.20.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed
in order to determine its performance in terms of electrical sensitivity.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
62
NXP Semiconductors
Package pinouts and signal descriptions
2.20.3.1
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of
each sample according to each pin combination. The sample size depends on the number of supply pins in
the device (3 parts*(n+1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard.
Table 34. ESD absolute maximum ratings1 2
Symbol
C
Ratings
Conditions
Class
Max value
Unit
V
VESD(HBM) CC T Electrostatic discharge voltage
(Human Body Model)
TA = 25 °C
conforming to AEC-Q100-002
H1C
2000
VESD(MM) CC T Electrostatic discharge voltage
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
VESD(CDM) CC T Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
C3A
500
750 (corners)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
2.20.3.2
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 35. Latch-up results
Symbol
LU
2.21
CC
C
Parameter
T Static latch-up class
Conditions
TA = 125 °C
conforming to JESD 78
Class
II level A
Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics
The device provides an oscillator/resonator driver. Figure 14 describes a simple model of the internal
oscillator driver and provides an example of a connection for an oscillator or a resonator.
Table 36 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
63
Package pinouts and signal descriptions
EXTAL
C1
Crystal
EXTAL
XTAL
C2
DEVICE
VDD
I
R
EXTAL
XTAL
Resonator
DEVICE
XTAL
DEVICE
Notes:
1. XTAL/EXTAL must not be directly used to drive external circuits
2. A series resistor may be required, according to crystal oscillator supplier recommendations.
Figure 14. Crystal oscillator and resonator connection scheme
Table 36. Crystal description
Crystal
motional
capacitance
(Cm) fF
Crystal
motional
inductance
(Lm) mH
Load on
xtalin/xtalout
C1 = C2
(pF)1
Shunt
capacitance
between
xtalout
and xtalin
C02 (pF)
Nominal
frequency
(MHz)
NDK crystal
reference
Crystal
equivalent
series
resistance
ESR Ω
4
NX8045GB
300
2.68
591.0
21
2.93
8
NX5032GA
300
2.46
160.7
17
3.01
10
150
2.93
86.6
15
2.91
12
120
3.11
56.5
15
2.93
16
120
3.90
25.3
10
3.00
1
The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing
includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
2 The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads,
package, etc.).
MPC5604B/C Microcontroller Data Sheet, Rev. 15
64
NXP Semiconductors
Package pinouts and signal descriptions
S_MTRANS bit (ME_GS register)
‘1’
‘0’
VXTAL
1/fFXOSC
VFXOSC
90%
VFXOSCOP
10%
tFXOSCSU
valid internal clock
Figure 15. Fast external crystal oscillator (4 to 16 MHz) timing diagram
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
65
Package pinouts and signal descriptions
Table 37. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Symbol
fFXOSC
C
Parameter
SR — Fast external crystal
oscillator frequency
—
gmFXOSC CC C Fast external crystal
VDD = 3.3 V ± 10%,
oscillator transconductance PAD3V5V = 1
OSCILLATOR_MARGIN = 0
VFXOSC
1
2.22
Typ
Max
4.0
—
16.0
MHz
2.2
—
8.2
mA/V
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 0
2.0
—
7.4
CC C
VDD = 3.3 V ± 10%,
PAD3V5V = 1
OSCILLATOR_MARGIN = 1
2.7
—
9.7
CC C
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 1
2.5
—
9.2
CC T Oscillation amplitude at
EXTAL
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
1.3
—
—
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1
1.3
—
—
—
—
0.95
—
V
—
—
2
3
mA
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
—
—
6
ms
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1
—
—
1.8
CC T Fast external crystal
oscillator consumption
tFXOSCSU CC T Fast external crystal
oscillator start-up time
2
Unit
Min
CC P
VFXOSCOP CC C Oscillation operating point
IFXOSC,2
Value
Conditions1
V
VIH
SR P Input high level CMOS
(Schmitt Trigger)
Oscillator bypass mode
0.65VDD
—
VDD+0.4
V
VIL
SR P Input low level CMOS
(Schmitt Trigger)
Oscillator bypass mode
−0.4
—
0.35VDD
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
Stated values take into account only analog module consumption but not the digital contributor (clock tree and
enabled peripherals)
Slow external crystal oscillator (32 kHz) electrical characteristics
The device provides a low power oscillator/resonator driver.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
66
NXP Semiconductors
Package pinouts and signal descriptions
OSC32K_EXTAL
OSC32K_EXTAL
Crystal
Resonator
C1
OSC32K_XTAL
OSC32K_XTAL
C2
DEVICE
DEVICE
Note: OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.
Figure 16. Crystal oscillator and resonator connection scheme
C0
Crystal
C1
Cm
C2
Rm
Lm
C1
C2
Figure 17. Equivalent circuit of a quartz crystal
Table 38. Crystal motional characteristics1
Value
Symbol
Parameter
Conditions
Unit
Typ
Max
Lm
Motional inductance
—
—
11.796
—
KH
Cm
Motional capacitance
—
—
2
—
fF
—
18
—
28
pF
AC coupled @ C0 = 2.85 pF4
—
—
65
kΩ
AC coupled @ C0 = 4.9 pF4
—
—
50
pF4
—
—
35
4
—
—
30
C1/C2 Load capacitance at OSC32K_XTAL and
OSC32K_EXTAL with respect to ground2
Rm3
Motional resistance
AC coupled @ C0 = 7.0
AC coupled @ C0 = 9.0 pF
1
Min
Crystal used: Epson Toyocom MC306
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
67
Package pinouts and signal descriptions
2
This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to
ground. It includes all the parasitics due to board traces, crystal and package.
3
Maximum ESR (Rm) of the crystal is 50 kΩ
4
C0 includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins
OSCON bit (OSC_CTL register)
1
0
VOSC32K_XTAL
1/fSXOSC
VSXOSC
90%
10%
TSXOSCSU
valid internal clock
Figure 18. Slow external crystal oscillator (32 kHz) timing diagram
Table 39. Slow external crystal oscillator (32 kHz) electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
fSXOSC
SR — Slow external crystal oscillator frequency
—
32
32.768
40
kHz
VSXOSC
CC T Oscillation amplitude
—
—
2.1
—
V
—
—
2.5
—
µA
—
—
—
8
µA
—
22
s
ISXOSCBIAS CC T Oscillation bias current
ISXOSC
CC T Slow external crystal oscillator consumption
TSXOSCSU CC T Slow external crystal oscillator start-up time
—
—
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified. Values are specified for no
neighbor GPIO pin activity. If oscillator is enabled (OSC32K_XTAL and OSC32K_EXTAL pins), neighboring pins
should not toggle.
2 Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal.
2.23
FMPLL electrical characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system
clock from the main oscillator driver.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
68
NXP Semiconductors
Package pinouts and signal descriptions
Table 40. FMPLL electrical characteristics
Symbol
C
Value
Conditions1
Parameter
Unit
Min
Typ
Max
fPLLIN
SR — FMPLL reference clock2
—
4
—
64
MHz
ΔPLLIN
SR — FMPLL reference clock duty
cycle2
—
40
—
60
%
—
16
—
64
MHz
—
256
—
512
MHz
—
245
—
533
fPLLOUT CC D FMPLL output clock frequency
fVCO3
CC P VCO frequency without
frequency modulation
C VCO frequency with frequency
modulation
fCPU
SR — System clock frequency
—
—
—
64
MHz
fFREE
CC P Free-running frequency
—
20
—
150
MHz
tLOCK
CC P FMPLL lock time
Stable oscillator (fPLLIN = 16 MHz)
—
40
100
µs
fsys maximum
–4
—
4
%
fPLLIN = 16 MHz (resonator),
fPLLCLK @ 64 MHz, 4000 cycles
—
—
10
ns
TA = 25 °C
—
—
4
mA
ΔtSTJIT CC — FMPLL short term
jitter4
ΔtLTJIT CC — FMPLL long term jitter
IPLL
CC C FMPLL consumption
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in
functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN.
3 Frequency modulation is considered ±4%
4 Short term jitter is measured on the clock rising edge at cycle n and n+4.
2
2.24
Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at the power-up
of the device.
Table 41. Fast internal RC oscillator (16 MHz) electrical characteristics
Symbol
fFIRC
C
Parameter
CC P Fast internal RC oscillator high
frequency
SR —
Value
Conditions1
TA = 25 °C, trimmed
—
Unit
Min
Typ
Max
—
16
—
12
MHz
20
IFIRCRUN2, CC T Fast internal RC oscillator high
frequency current in running mode
TA = 25 °C, trimmed
—
—
200
µA
IFIRCPWD CC D Fast internal RC oscillator high
frequency current in power down
mode
TA = 125 °C
—
—
10
µA
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
69
Package pinouts and signal descriptions
Table 41. Fast internal RC oscillator (16 MHz) electrical characteristics (continued)
Symbol
C
Value
Conditions1
Parameter
Unit
Min
Typ
Max
sysclk = off
—
500
—
sysclk = 2 MHz
—
600
—
sysclk = 4 MHz
—
700
—
sysclk = 8 MHz
—
900
—
sysclk = 16 MHz
—
1250
—
—
1.1
2.0
µs
ΔFIRCPRE CC T Fast internal RC oscillator precision TA = 25 °C
after software trimming of fFIRC
−1
—
+1
%
ΔFIRCTRIM CC T Fast internal RC oscillator trimming TA = 25 °C
step
—
1.6
−5
—
IFIRCSTOP CC T Fast internal RC oscillator high
TA = 25 °C
frequency and system clock current
in stop mode
tFIRCSU
CC C Fast internal RC oscillator start-up
time
VDD = 5.0 V ± 10%
ΔFIRCVAR CC P Fast internal RC oscillator variation
in over temperature and supply with
respect to fFIRC at TA = 25 °C in
high-frequency configuration
1
—
µA
%
+5
%
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
2
2.25
Slow internal RC oscillator (128 kHz) electrical characteristics
The device provides a 128 kHz slow internal RC oscillator. This can be used as the reference clock for the
RTC module.
Table 42. Slow internal RC oscillator (128 kHz) electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
—
128
—
100
—
150
—
—
5
µA
CC P Slow internal RC oscillator low
frequency
SR —
TA = 25 °C, trimmed
ISIRC2,
CC C Slow internal RC oscillator low
frequency current
TA = 25 °C, trimmed
tSIRCSU
CC P Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V ± 10%
time
—
8
12
µs
ΔSIRCPRE
CC C Slow internal RC oscillator precision TA = 25 °C
after software trimming of fSIRC
−2
—
+2
%
ΔSIRCTRIM
CC C Slow internal RC oscillator trimming
step
—
2.7
—
fSIRC
—
—
kHz
MPC5604B/C Microcontroller Data Sheet, Rev. 15
70
NXP Semiconductors
Package pinouts and signal descriptions
Table 42. Slow internal RC oscillator (128 kHz) electrical characteristics (continued)
Symbol
ΔSIRCVAR
1
2
C
Parameter
Value
Conditions1
CC C Slow internal RC oscillator variation High frequency configuration
in temperature and supply with
respect to fSIRC at TA = 55 °C in high
frequency configuration
Unit
Min
Typ
Max
−10
—
+10
%
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
71
Package pinouts and signal descriptions
2.26
2.26.1
ADC electrical characteristics
Introduction
The device provides a 10-bit Successive Approximation Register (SAR) analog-to-digital converter.
Offset error (EO)
Gain error (EG)
1023
1022
1021
1020
1019
1 LSB ideal = VDD_ADC / 1024
1018
(2)
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(5)
(2) The ideal transfer curve
4
(3) Differential non-linearity error (DNL)
(4)
(4) Integral non-linearity error (INL)
3
(5) Center of a step of the actual transfer curve
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset error (EO)
Figure 19. ADC characteristic and error definitions
2.26.2
Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC
impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can
MPC5604B/C Microcontroller Data Sheet, Rev. 15
72
NXP Semiconductors
Package pinouts and signal descriptions
be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to
attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase,
when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple
RC filter). The RC filtering may be limited according to the value of source impedance of the transducer
or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking
into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input
impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling
capacitance: being CS and Cp2 substantially two switched capacitances, with a frequency equal to the
conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a
conversion rate of 1 MHz, with CS+Cp2 equal to 3 pF, a resistance of 330 kΩ is obtained (REQ = 1 /
(fc × (CS+Cp2)), where fc represents the conversion rate at the considered channel). To minimize the error
induced by the voltage partitioning between this resistance (sampled voltage on CS+Cp2) and the sum of
RS + RF, the external circuit must be designed to respect the Equation 4:
Eqn. 4
RS + RF
V A • --------------------- < 1
--- LSB
R EQ
2
Equation 4 generates a constraint for external network design, in particular on a resistive path.
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
VA
Filter
RF
Current Limiter
RL
CF
CP1
Channel
Selection
Sampling
RSW1
RAD
CP2
CS
RS: Source impedance
RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW1: Channel selection switch impedance
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1 and CP2)
CS: Sampling capacitance
Figure 20. Input equivalent circuit (precise channels)
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
73
Package pinouts and signal descriptions
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
Filter
RS
Current Limiter
RF
Extended
Switch
Sampling
RSW1
RSW2
RAD
RL
CF
VA
Channel
Selection
CP1
CP3
CP2
CS
RS: Source impedance
RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW1: Channel selection switch impedance (two contributions, RSW1 and RSW2)
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1, CP2 and CP3)
CS: Sampling capacitance
Figure 21. Input equivalent circuit (extended channels)
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances
CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit in Figure 20):
A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close).
Voltage transient on CS
VCS
VA
VA2
ΔV < 0.5 LSB
1
2
τ1 < (RSW + RAD) CS 2048 • C S
MPC5604B/C Microcontroller Data Sheet, Rev. 15
76
NXP Semiconductors
Package pinouts and signal descriptions
2.26.3
ADC electrical characteristics
Table 43. ADC input leakage current
Value
Symbol C
Parameter
Conditions
Unit
ILKG CC D Input leakage current TA = −40 °C No current injection on adjacent pin
Min
Typ
Max
—
1
70
D
TA = 25 °C
—
1
70
D
TA = 85 °C
—
3
100
D
TA = 105 °C
—
8
200
P
TA = 125 °C
—
45
400
nA
Table 44. ADC conversion characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
VSS_ADC SR — Voltage on
VSS_HV_ADC (ADC
reference) pin with
respect to ground
(VSS)2
—
−0.1
—
0.1
V
VDD_ADC SR — Voltage on
VDD_HV_ADC pin
(ADC reference) with
respect to ground
(VSS)
—
VDD−0.1
—
VDD+0.1
V
VAINx
SR — Analog input voltage3
—
VSS_ADC−0.1
—
VDD_ADC+0.1
V
fADC
SR — ADC analog frequency
—
6
—
32 + 4%
MHz
ΔADC_SYS SR — ADC digital clock duty ADCLKSEL =
cycle (ipg_clk)
14
45
—
55
%
IADCPWD SR — ADC0 consumption in
power down mode
—
—
—
50
µA
IADCRUN SR — ADC0 consumption in
running mode
—
—
—
4
mA
tADC_PU SR — ADC power up delay
—
—
—
1.5
µs
fADC = 32 MHz, INPSAMP = 17
0.5
—
fADC = 6 MHz, INPSAMP = 255
—
—
0.625
—
ts
CC T Sampling time5
time6
fADC = 32 MHz, INPCMP = 2
µs
42
tc
CC P Conversion
µs
CS
CC D ADC input sampling
capacitance
—
—
—
3
pF
CP1
CC D ADC input pin
capacitance 1
—
—
—
3
pF
CP2
CC D ADC input pin
capacitance 2
—
—
—
1
pF
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
77
Package pinouts and signal descriptions
Table 44. ADC conversion characteristics (continued)
Symbol
CP3
3
4
5
6
7
Value
Conditions1
Unit
Min
Typ
Max
—
—
—
1
pF
RSW1
CC D Internal resistance of
analog source
—
—
—
3
kΩ
RSW2
CC D Internal resistance of
analog source
—
—
—
2
kΩ
RAD
CC D Internal resistance of
analog source
—
—
—
2
kΩ
IINJ
SR — Input current Injection Current
injection on one
ADC input,
different from
the converted
one
VDD =
3.3 V ± 10%
−5
—
5
mA
VDD =
5.0 V ± 10%
−5
—
5
CC T Absolute value for
integral non-linearity
No overload
—
0.5
1.5
LSB
| DNL | CC T Absolute differential
non-linearity
No overload
—
0.5
1.0
LSB
| EO |
CC T Absolute offset error
—
—
0.5
—
LSB
| EG |
CC T Absolute gain error
—
—
0.6
—
LSB
TUEp
CC P Total unadjusted error7 Without current injection
for precise channels,
T
With current injection
input only pins
−2
0.6
2
LSB
CC T Total unadjusted error7 Without current injection
for extended channel
T
With current injection
−3
TUEx
2
Parameter
CC D ADC input pin
capacitance 3
| INL |
1
C
−3
−4
3
1
3
LSB
4
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
Analog and digital VSS must be common (to be tied together externally).
VAINx may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured
by internal divider by 2.
During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within ts. After the end of
the sampling time ts, changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock ts depend on programming.
This parameter does not include the sampling time ts, but only the time for determining the digital result and the time
to load the result’s register with the conversion result.
Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
78
NXP Semiconductors
Package pinouts and signal descriptions
2.27
On-chip peripherals
2.27.1
Current consumption
Table 45. On-chip peripherals current consumption1
Symbol
IDD_BV(CAN)
IDD_BV(eMIOS)
C
Parameter
CC T CAN (FlexCAN) supply
current on VDD_BV
CC T eMIOS supply current on
VDD_BV
Conditions
Bitrate:
Total (static + dynamic)
500 Kbyte/s consumption:
• FlexCAN in loop-back
Bitrate:
mode
125 Kbyte/s
• XTAL @ 8 MHz used as
CAN engine clock source
• Message sending period is
580 µs
Static consumption:
• eMIOS channel OFF
• Global prescaler enabled
IDD_BV(SCI)
CC T SCI (LINFlex) supply
current on VDD_BV
Total (static + dynamic) consumption:
• LIN mode
• Baudrate: 20 Kbyte/s
IDD_BV(SPI)
CC T SPI (DSPI) supply current
on VDD_BV
CC T ADC supply current on
VDD_BV
µA
8 * fperiph + 27
µA
3
5 * fperiph + 31
µA
Ballast static consumption (only clocked)
1
µA
Ballast dynamic consumption (continuous
communication):
• Baudrate: 2 Mbit/s
• Transmission every 8 µs
• Frame: 16 bits
16 * fperiph
VDD = 5.5 V Ballast static consumption
(no conversion)
41 * fperiph
Ballast dynamic consumption
(continuous conversion)3
IDD_HV_ADC(ADC) CC T ADC supply current on
VDD_HV_ADC
8 * fperiph + 85
29 * fperiph
Dynamic consumption:
• It does not change varying the frequency
(0.003 mA)
IDD_BV(ADC)
Typical value2 Unit
VDD = 5.5 V Analog static consumption
(no conversion)
µA
5 * fperiph
2 * fperiph
µA
Analog dynamic consumption 75 * fperiph + 32
(continuous conversion)
IDD_HV(FLASH)
IDD_HV(PLL)
CC T Code Flash + Data Flash
VDD = 5.5 V
supply current on VDD_HV
—
8.21
mA
CC T PLL supply current on
VDD_HV
—
30 * fperiph
µA
VDD = 5.5 V
1
Operating conditions: TA = 25 °C, fperiph = 8 MHz to 64 MHz
fperiph is an absolute value.
3 During the conversion, the total current consumption is given from the sum of the static and dynamic consumption, i.e.,
(41 + 5) * fperiph.
2
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
79
Package pinouts and signal descriptions
2.27.2
DSPI characteristics
Table 46. DSPI characteristics1
DSPI0/DSPI1
No.
1
—
Symbol
tSCK
fDSPI
C
Unit
Min
Typ
Max
Min
Typ
Max
Master mode
(MTFE = 0)
125
—
—
333
—
—
D
Slave mode
(MTFE = 0)
125
—
—
333
—
—
D
Master mode
(MTFE = 1)
83
—
—
125
—
—
D
Slave mode
(MTFE = 1)
83
—
—
125
—
—
—
—
fCPU
—
—
fCPU
MHz
—
—
153
ns
SR D SCK cycle time
SR D DSPI digital controller frequency
—
ΔtCSC
CC D Internal delay between pad Master mode
associated to SCK and pad
associated to CSn in
master mode for CSn1→0
—
—
—
ΔtASC
CC D Internal delay between pad Master mode
associated to SCK and pad
associated to CSn in
master mode for CSn1→1
—
—
1303
—
—
1303
ns
2
tCSCext4 SR D CS to SCK delay
Slave mode
32
—
—
32
—
—
ns
3
tASCext5 SR D After SCK delay
Slave mode
1/fDSPI + 5
—
—
1/fDSPI + 5
—
—
ns
—
tSCK/2
—
—
tSCK/2
—
ns
tSDC
CC D SCK duty cycle
Master mode
SR D
Slave mode
tSCK/2
—
—
tSCK/2
—
—
5
tA
SR D Slave access time
Slave mode
—
—
1/fDSPI + 70
—
—
1/fDSPI + 130
ns
6
tDI
SR D Slave SOUT disable time
Slave mode
7
—
—
7
—
—
ns
7
tPCSC
SR D PCSx to PCSS time
0
—
—
0
—
—
ns
8
tPASC
SR D PCSS to PCSx time
0
—
—
0
—
—
ns
9
tSUI
Master mode
43
—
—
145
—
—
ns
Slave mode
5
—
—
5
—
—
Master mode
0
—
—
0
—
—
Slave mode
26
—
—
26
—
—
—
—
32
—
—
50
—
—
52
—
—
160
0
—
—
0
—
—
8
—
—
13
—
—
10
tHI
11
tSUO7
12
tHO7
SR D Data setup time for inputs
SR D Data hold time for inputs
CC D Data valid after SCK edge Master mode
Slave mode
CC D Data hold time for outputs Master mode
Slave mode
1
ns
1302
4
2
DSPI2
Parameter
ns
ns
ns
Operating conditions: CL = 10 to 50 pF, SlewIN = 3.5 to 15 ns.
Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK
starts before CSn is asserted. DSPI2 has only SLOW SCK available.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
80
NXP Semiconductors
Package pinouts and signal descriptions
3
4
5
6
7
Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is
deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available.
The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay
between internal CS and internal SCK must be higher than ΔtCSC to ensure positive tCSCext.
The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between
internal CS and internal SCK must be higher than ΔtASC to ensure positive tASCext.
This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of the DSPI_MCR.
SCK and SOUT configured as MEDIUM pad
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
81
Package pinouts and signal descriptions
2
3
PCSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
SIN
10
First Data
Last Data
Data
12
SOUT
First Data
11
Data
Last Data
Note: Numbers shown reference Table 46.
Figure 24. DSPI classic SPI timing – master, CPHA = 0
PCSx
SCK Output
(CPOL = 0)
10
SCK Output
(CPOL = 1)
9
SIN
Data
First Data
12
SOUT
First Data
Last Data
11
Data
Last Data
Note: Numbers shown reference Table 46.
Figure 25. DSPI classic SPI timing – master, CPHA = 1
MPC5604B/C Microcontroller Data Sheet, Rev. 15
82
NXP Semiconductors
Package pinouts and signal descriptions
3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
First Data
SOUT
9
6
Data
Last Data
Data
Last Data
10
First Data
SIN
11
12
Note: Numbers shown reference Table 46.
Figure 26. DSPI classic SPI timing – slave, CPHA = 0
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
6
10
First Data
Note: Numbers shown reference Table 46.
Figure 27. DSPI classic SPI timing – slave, CPHA = 1
MPC5604B/C Microcontroller Data Sheet, Rev. 15
NXP Semiconductors
83
Package pinouts and signal descriptions
3
PCSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
SIN
10
First Data
Last Data
Data
12
SOUT
11
First Data
Last Data
Data
Note: Numbers shown reference Table 46.
Figure 28. DSPI modified transfer format timing – master, CPHA = 0
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
SIN
First Data
Data
12
SOUT
First Data
Data
Last Data
11
Last Data
Note: Numbers shown reference Table 46.
Figure 29. DSPI modified transfer format timing – master, CPHA = 1
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Package pinouts and signal descriptions
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
First Data
SOUT
Data
6
Last Data
10
9
Data
First Data
SIN
12
11
5
Last Data
Note: Numbers shown reference Table 46.
Figure 30. DSPI modified transfer format timing – slave, CPHA = 0
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
12
First Data
SOUT
9
SIN
Data
Last Data
Data
Last Data
6
10
First Data
Note: Numbers shown reference Table 46.
Figure 31. DSPI modified transfer format timing – slave, CPHA = 1
MPC5604B/C Microcontroller Data Sheet, Rev. 15
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Package pinouts and signal descriptions
8
7
PCSS
PCSx
Note: Numbers shown reference Table 46.
Figure 32. DSPI PCS strobe (PCSS) timing
2.27.3
Nexus characteristics
Table 47. Nexus characteristics
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
1
tTCYC
CC D TCK cycle time
64
—
—
ns
2
tMCYC
CC D MCKO cycle time
32
—
—
ns
3
tMDOV
CC D MCKO low to MDO data valid
—
—
8
ns
4
tMSEOV
CC D MCKO low to MSEO_b data valid
—
—
8
ns
5
tEVTOV
CC D MCKO low to EVTO data valid
—
—
8
ns
10
tNTDIS
CC D TDI data setup time
15
—
—
ns
tNTMSS
CC D TMS data setup time
15
—
—
ns
tNTDIH
CC D TDI data hold time
5
—
—
ns
tNTMSH
CC D TMS data hold time
5
—
—
ns
11
12
tTDOV
CC D TCK low to TDO data valid
35
—
—
ns
13
tTDOI
CC D TCK low to TDO data invalid
6
—
—
ns
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NXP Semiconductors
Package pinouts and signal descriptions
TCK
10
11
TMS, TDI
12
TDO
Note: Numbers shown reference Table 47.
Figure 33. Nexus TDI, TMS, TDO timing
2.27.4
JTAG characteristics
Table 48. JTAG characteristics
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
1
tJCYC
CC
D TCK cycle time
64
—
—
ns
2
tTDIS
CC
D TDI setup time
15
—
—
ns
3
tTDIH
CC
D TDI hold time
5
—
—
ns
4
tTMSS
CC
D TMS setup time
15
—
—
ns
5
tTMSH
CC
D TMS hold time
5
—
—
ns
6
tTDOV
CC
D TCK low to TDO valid
—
—
33
ns
7
tTDOI
CC
D TCK low to TDO invalid
6
—
—
ns
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Package characteristics
TCK
2/4
DATA INPUTS
3/5
INPUT DATA VALID
6
DATA OUTPUTS
OUTPUT DATA VALID
7
DATA OUTPUTS
Note: Numbers shown reference Table 48.
Figure 34. Timing diagram – JTAG boundary scan
3
Package characteristics
3.1
Package mechanical data
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Package characteristics
3.1.1
64 LQFP
Figure 35. 64 LQFP package mechanical drawing (1 of 3)
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Package characteristics
Figure 36. 64 LQFP package mechanical drawing (2 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 15
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Package characteristics
Figure 37. 64 LQFP package mechanical drawing (3 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 15
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Package characteristics
3.1.2
100 LQFP
Figure 38. 100 LQFP package mechanical drawing (1 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 15
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Package characteristics
Figure 39. 100 LQFP package mechanical drawing (2 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 15
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Package characteristics
Figure 40. 100 LQFP package mechanical drawing (3 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 15
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Package characteristics
3.1.3
144 LQFP
Figure 41. 144 LQFP package mechanical drawing (1 of 2)
MPC5604B/C Microcontroller Data Sheet, Rev. 15
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95
Package characteristics
Figure 42. 144 LQFP package mechanical drawing (2 of 2)
MPC5604B/C Microcontroller Data Sheet, Rev. 15
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Package characteristics
3.1.4
208 MAPBGA
Figure 43. 208 MAPBGA package mechanical drawing (1 of 2)
MPC5604B/C Microcontroller Data Sheet, Rev. 15
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Package characteristics
Figure 44. 208 MAPBGA package mechanical drawing (2 of 2)
MPC5604B/C Microcontroller Data Sheet, Rev. 15
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Ordering information
4
Ordering information
Figure 45. Commercial product code structure
Example code:
M
PC
56
0
4
B
F1
M
LL
4
R
Qualification Status
PowerPC Core
Automotive Platform
Core Version
Flash Size (core dependent)
Product
Fab and Mask Indicator
Temperature spec.
Package Code
Frequency
R = Tape & Reel (blank if Tray)
Qualification Status
M = MC status
S = Auto qualified
P = PC status
Flash Size (z0 core)
2 = 256 KB
3 = 384 KB
4 = 512 KB
Temperature spec.
C = −40 to 85 °C
V = −40 to 105 °C
M = −40 to 125 °C
Automotive Platform
56 = PPC in 90nm
Product
B = Body
C = Gateway
Package Code
LH = 64 LQFP
LL = 100 LQFP
LQ = 144 LQFP
MG = 208 MAPBGA1
Core Version
0 = e200z0
Note: Not all options are available on all devices.
1
Fab and Mask Indicator
F = ATMC Fab
K = TSMC Fab
A = ATMC Fab or TSMC Fab
Second digit usually differentiate mask rev
Frequency
4 = Up to 48 MHz
6 = Up to 64 MHz
208 MAPBGA available only as development package for Nexus2+
5
Document revision history
Table 49 summarizes revisions to this document.
Table 49. Revision history
Revision
1
Date
Description of Changes
04-Apr-2008 Initial release.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
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Document revision history
Table 49. Revision history (continued)
Revision
2
Date
Description of Changes
06-Mar-2009 Made minor editing and formatting changes to improve readability
Harmonized oscillator naming throughout document
Features:
—Replaced 32 KB with 48 KB as max SRAM size
—Updated description of INTC
—Changed max number of GPIO pins from 121 to 123
Updated Section 1.2, Description
Updated Table 3
Added Section 2, Block diagram
Section 3, Package pinouts and signal descriptions: Removed signal descriptions (these
are found in the device reference manual)
Updated Figure 5:
—Replaced VPP with VSS_HV on pin 18
—Added MA[1] as AF3 for PC[10] (pin 28)
—Added MA[0] as AF2 for PC[3] (pin 116)
—Changed description for pin 120 to PH[10] / GPIO[122] / TMS
—Changed description for pin 127 to PH[9] / GPIO[121] / TCK
—Replaced NMI[0] with NMI on pin 11
Updated Figure 4:
—Replaced VPP with VSS_HV on pin 14
—Added MA[1] as AF3 for PC[10] (pin 22)
—Added MA[0] as AF2 for PC[3] (pin 77)
—Changed description for pin 81 to PH[10] / GPIO[122] / TMS
—Changed description for pin 88 to PH[9] / GPIO[121] / TCK
—Removed E1UC[19] from pin 76
—Replaced [11] with WKUP[11] for PB[3] (pin 1)
—Replaced NMI[0] with NMI on pin 7
Updated Figure 6:
—Changed description for ball B8 from TCK to PH[9]
—Changed description for ball B9 from TMS to PH[10]
—Updated descriptions for balls R9 and T9
Added 2.10, Parameter classification and tagged parameters in tables where appropriate
Added 2.11, NVUSRO register
Updated Table 11
2.13, Recommended operating conditions: Added note on RAM data retention to end of
section
Updated Table 12 and Table 13
Added 2.14.1, Package thermal characteristics
Updated 2.14.2, Power considerations
Updated Figure 7
MPC5604B/C Microcontroller Data Sheet, Rev. 15
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Document revision history
Table 49. Revision history (continued)
Revision
2 (cont.)
4
Date
Description of Changes
06-Mar-2009 Updated Table 15, Table 16, Table 17, Table 18 and Table 19
Added 2.15.4, Output pin transition times
Updated Table 22
Updated Figure 8
Updated Table 24
2.17.1, Voltage regulator electrical characteristics: Amended description of LV_PLL
Figure 10: Exchanged position of symbols CDEC1 and CDEC2
Updated Table 25
Added Figure 13
Updated Table 26 and Table 27
Updated 2.19, Flash memory electrical characteristics
Added 2.20, Electromagnetic compatibility (EMC) characteristics
Updated 2.21, Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Updated 2.22, Slow external crystal oscillator (32 kHz) electrical characteristics
Updated Table 40, Table 41 and Table 42
Added 2.27, On-chip peripherals
Added Table 43
Updated Table 44
Updated Table 47
Added Appendix A, Abbreviations
06-Aug-2009 Updated Figure 6
Table 11
• VDD_ADC: changed min value for “relative to VDD” condition
• VIN: changed min value for “relative to VDD” condition
• ICORELV: added new row
Table 13
• TA C-Grade Part, TJ C-Grade Part, TA V-Grade Part, TJ V-Grade Part, TA M-Grade Part, TJ M-Grade Part:
added new rows
• Changed capacitance value in footnote
Table 20
• MEDIUM configuration: added condition for PAD3V5V = 0
Updated Figure 10
Table 25
• CDEC1: changed min value
• IMREG: changed max value
• IDD_BV: added max value footnote
Table 26
• VLVDHV3H: changed max value
• VLVDHV3L: added max value
• VLVDHV5H: changed max value
• VLVDHV5L: added max value
Updated Table 27
Table 29
• Retention: deleted min value footnote for “Blocks with 100,000 P/E cycles“
Table 37
• IFXOSC: added typ value
Table 39
• VSXOSC: changed typ value
• TSXOSCSU: added max value footnote
Table 40
• ΔtLTJIT: added max value
Updated Figure 38
MPC5604B/C Microcontroller Data Sheet, Rev. 15
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Document revision history
Table 49. Revision history (continued)
Revision
5
Date
Description of Changes
02-Nov-2009 In the “MPC5604B/C series block summary” table, added a new row.
In the “Absolute maximum ratings” table, changed max value of VDD_BV, VDD_ADC, and
VIN.
In the “Recommended operating conditions (3.3 V)” table, deleted min value of TVDD.
In the “Reset electrical characteristics” table, changed footnotes 3 and 5.
In the “Voltage regulator electrical characteristics” table:
• CREGn: changed max value.
• CDEC1: split into 2 rows.
• Updated voltage values in footnote 4
In the “Low voltage monitor electrical characteristics” table:
• Updated column Conditions.
• VLVDLVCORL, VLVDLVBKPL: changed min/max value.
In the “Program and erase specifications” table, added initial max value of Tdwprogram.
In the “Flash module life” table, changed min value for blocks with 100K P/E cycles
In the “Flash power supply DC electrical characteristics” table:
• IFREAD, IFMOD: added typ value.
• Added footnote 1.
Added “NVUSRO[WATCHDOG_EN] field description” section.
Section 4.18: “ADC electrical characteristics” has been moved up in hierarchy (it was
Section 4.18.5).
In the “ADC conversion characteristics” table, changed initial max value of RAD.
In the “On-chip peripherals current consumption” table:
• Removed min/max from the heading.
• Changed unit of measurement and consequently rounded the values.
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Document revision history
Table 49. Revision history (continued)
Revision
6
Date
Description of Changes
15-Mar-2010 In the “Introduction” section, relocated a note.
In the “MPC5604B/C device comparison” table, added footnote regarding SCI and CAN.
In the “Absolute maximum ratings” table, removed the min value of VIN relative to VDD.
In the “Recommended operating conditions (3.3 V)” table:
• TA C-Grade Part, TJ C-Grade Part, TA V-Grade Part, TJ V-Grade Part, TA M-Grade Part, TJ M-Grade Part:
added new rows.
• TVDD: made single row.
In the “LQFP thermal characteristics” table, added more rows.
Removed “208 MAPBGA thermal characteristics” table.
In the “I/O consumption” table:
• Removed IDYNSEG row.
• Added “I/O weight” table.
In the “Voltage regulator electrical characteristics” table:
• Updated the values.
• Removed IVREGREF and IVREDLVD12.
• Added a note about IDD_BC.
In the “Low voltage monitor electrical characteristics” table:
• Updated VPORH values.
• Updated VLVDLVCORL value.
Entirely updated the “Low voltage power domain electrical characteristics” table.
In the “Program and erase specifications” table, inserted Teslat row.
Entirely updated the “Flash power supply DC electrical characteristics” table.
Entirely updated the “Start-up time/Switch-off time” table.
In the “Crystal oscillator and resonator connection scheme” figure, relocated a note.
In the “Slow external crystal oscillator (32 kHz) electrical characteristics” table:
• Removed gmSXOSC row.
• Inserted values of ISXOSCBIAS.
Entirely updated the “Fast internal RC oscillator (16 MHz) electrical characteristics” table.
In the “ADC conversion characteristics” table: updated the description of the conditions of
tADC_PU and tADC_S.
Entirely updated the “DSPI characteristics” table.
In the “Orderable part number summary” table, modified some orderable part number.
Updated the “Commercial product code structure” figure.
Removed the note about the condition from “Flash read access timing” table
Removed the notes that assert the values need to be confirmed before validation
Exchanged the order of “LQFP 100-pin configuration” and “LQFP 144-pin configuration”
Exchanged the order of “LQFP 100-pin package mechanical drawing” and “LQFP 144-pin
package mechanical drawing”
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Document revision history
Table 49. Revision history (continued)
Revision
Date
Description of Changes
7
05-Jul-2010
Added 64 LQFP package information
Updated the “Features” section.
Figures “LQFP 100-pin configuration” and “LQFP 100-pin configuration”: removed
alternate function information
Added “Functional port pin descriptions” table
Added eDMA block in the “MPC5604B/C series block diagram” figure
Deleted the “NVUSRO[WATCHDOG_EN] field description” section
In the “Recommended operating conditions (3.3 V)” and “Recommended operating
conditions (5.0 V)” tables, deleted the conditions of TA C-Grade Part, TA V-Grade Part, TA M-Grade
Part
In the “LQFP thermal characteristics” table, rounded the values.
In the “RESET electrical characteristics” section, replaced “nRSTIN” with “RESET”.
In the “I/O input DC electrical characteristics” table:
• WFI: inserted a footnote
• WNFI: inserted a footnote
In the “Low voltage monitor electrical characteristics” table:
• changed min value VLVDHV3L, from 2.7 to 2.6
• Inserted max value of VLVDLVCORL
In the “FMPLL electrical characteristics” table, rounded the values of fVCO.
In the “DSPI characteristics” table:
• Added ΔtASC row
• Update values of tA
In the “ADC conversion characteristics” table, added “IADCPWD” and “IADCRUN” rows
Removed “Orderable part number summary” table.
8
25-Nov-2010 Editorial changes and improvements.
In the “MPC5604B/C device comparison” table, changed the temperature value from 105
to 125 °C, in the footnote regarding “Execution speed”.
In the “Recommended operating conditions (3.3 V)” and “Recommended operating
conditions (5.0 V)” tables, restored the conditions of TA C-Grade Part, TA V-Grade Part, TA
M-Grade Part
In the “LQFP thermal characteristics” table, added values concerning 64 LQFP package.
In the “MEDIUM configuration output buffer electrical characteristics” table: fixed a typo in
last row of conditions column, there was IOH that now is IOL.
In the “Reset electrical characteristics” table, changed the parameter classification tag for
VOL and |IWPU|.
In the “Low voltage monitor electrical characteristics” table, changed the max value of
VLVDLVCORL from 1.5V to 1.15V.
In the “Program and erase specifications” table, replaced “Teslat” with “Tesus”.
In the “FMPLL electrical characteristics” table, changed the parameter classification tag
for fVCO.
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Document revision history
Table 49. Revision history (continued)
Revision
9
Date
Description of Changes
16 June 2011 Formatting and minor editorial changes throughout
Harmonized oscillator nomenclature
Removed all instances of note “All 64 LQFP information is indicative and must be
confirmed during silicon validation.”
Device comparison table: changed temperature value in footnote 2 from 105 °C to 125 °C
MPC560xB LQFP 64-pin configuration and MPC560xC LQFP 64-pin configuration:
renamed pin 6 from VPP_TEST to VSS_HV
Removed “Pin Muxing” section; added sections “Pad configuration during reset phases”,
“Voltage supply pins”, “Pad types”, “System pins,” “Functional ports”, and “Nexus 2+
pins”
Section “NVUSRO register”: edited content to separate configuration into electrical
parameters and digital functionality; updated footnote describing default value of ‘1’ in
field descriptions NVUSRO[PAD3V5V] and NVUSRO[OSCILLATOR_MARGIN]
Added section “NVUSRO[WATCHDOG_EN] field description”
Recommended operating conditions (3.3 V) and Recommended operating conditions
(5.0 V): updated conditions for ambient and junction temperature characteristics
I/O input DC electrical characteristics: updated ILKG characteristics
Section “I/O pad current specification”: removed content referencing the IDYNSEG
maximum value
I/O consumption: replaced instances of “Root medium square” with “Root mean square”
I/O weight: replaced instances of bit “SRE” with “SRC”; added pads PH[9] and PH[10];
added supply segments; removed weight values in 64-pin LQFP for pads that do not
exist in that package
Reset electrical characteristics: updated parameter classification for |IWPU|
Updated Voltage regulator electrical characteristics
Section “Low voltage detector electrical characteristics”: changed title (was “Voltage
monitor electrical characteristics”); added event status flag names found in RGM
chapter of device reference manual to POR module and LVD descriptions; replaced
instances of “Low voltage monitor” with “Low voltage detector”; updated values for
VLVDLVBKPL and VLVDLVCORL; replaced “LVD_DIGBKP” with “LVDLVBKP” in note
Updated section “Power consumption”
Fast external crystal oscillator (4 to 16 MHz) electrical characteristics: updated parameter
classification for VFXOSCOP
Crystal oscillator and resonator connection scheme: added footnote about possibility of
adding a series resistor
Slow external crystal oscillator (32 kHz) electrical characteristics: updated footnote 1
FMPLL electrical characteristics: added short term jitter characteristics; inserted “—” in
empty min value cell of tlock row
Section “Input impedance and ADC accuracy”: changed “VA/VA2” to “VA2/VA” in
Equation 11
ADC input leakage current: updated ILKG characteristics
ADC conversion characteristics: updated symbols
On-chip peripherals current consumption: changed “supply current on “VDD_HV_ADC” to
“supply current on” VDD_HV” in IDD_HV(FLASH) row; updated IDD_HV(PLL) value—was
3 * fperiph, is 30 * fperiph; updated footnotes
DSPI characteristics: added rows tPCSC and tPASC
Added DSPI PCS strobe (PCSS) timing diagram
MPC5604B/C Microcontroller Data Sheet, Rev. 15
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Document revision history
Table 49. Revision history (continued)
Revision
Date
Description of Changes
10
15 Oct 2012
Table 2 (Bolero 512K device comparison), added footnote for MPC5603BxLH and
MPC5604BxLH about FlexCAN availability.
Table 2 (MPC5604B/C series block summary), replaced “System watchdog timer” with
“Software watchdog timer” and specified AUTOSAR (Automotive Open System
Architecture)
Table 5 (Functional port pin descriptions):
replaced footnote “Available only on MPC560xC versions and MPC5604B 208
MAPBGA devices” with “Available only on MPC560xC versions, MPC5603B 64 LQFP,
MPC5604B 64 LQFP and MPC5604B 208 MAPBGA devices”,
replaced VDD with VDD_HV
Figure 10 (Voltage regulator capacitance connection), updated pin name appearance
Renamed Figure 11 (VDD_HV and VDD_BV maximum slope) (was “VDD and VDD_BV
maximum slope”)
Renamed Figure 12 (VDD_HV and VDD_BV supply constraints during STANDBY mode exit)
(was “VDD and VDD_BV supply constraints during STANDBY mode exit”)
Table 12 (Recommended operating conditions (3.3 V)), added minimum value of TVDD
and footnote about it.
Table 13 (Recommended operating conditions (5.0 V)), added minimum value of TVDD
and footnote about it.
Section 2.17.1, “Voltage regulator electrical characteristics:
replaced “slew rate of VDD/VDD_BV” with “slew rate of both VDD_HV and VDD_BV”
replaced “When STANDBY mode is used, further constraints apply to the VDD/VDD_BV
in order to guarantee correct regulator functionality during STANDBY exit.” with “When
STANDBY mode is used, further constraints are applied to the both VDD_HV and
VDD_BV in order to guarantee correct regulator function during STANDBY exit.”
Table 27 (Power consumption on VDD_BV and VDD_HV), updated footnotes of IDDMAX
and IDDRUN stating that both currents are drawn only from the VDD_BV pin.
Table 31 (Flash memory power supply DC electrical characteristics), in the parameter
column replaced VDD_BV and VDD_HV respectively with VDD_BV and VDD_HV.
Table 45 (On-chip peripherals current consumption), in the parameter column replaced
VDD_BV, VDD_HV and VDD_HV_ADC respectively with VDD_BV, VDD_HV and
VDD_HV_ADC
Updated Section 2.26.2, “Input impedance and ADC accuracy
Table 46 (DSPI characteristics), modified symbol for tPCSC and tPASC
11
14 Nov 2012 In the cover feature list:
added “and ECC” at the end of “Up to 512 KB on-chip code flash supported with the
flash controller”
added “with ECC” at the end of “Up to 48 KB on-chip SRAM”
Table 12 (Recommended operating conditions (3.3 V)), removed minimum value of TVDD
and relative footnote.
Table 13 (Recommended operating conditions (5.0 V)), removed minimum value of TVDD
and relative footnote.
12
19 Mar 2014 Added “K=TSMC Fab” against the Fab and mask indicator in Figure 45 (Commercial
product code structure).
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Document revision history
Table 49. Revision history (continued)
Revision
Date
Description of Changes
13
19 Jan 2015 In Table 1 (MPC5604B/C device comparison):
• changed the MPC5604BxLH entry for CAN (FlexCAN) from 37 to 26.
• updated tablenote 7.
In Table 13 (Recommended operating conditions (5.0 V)), updated tablenote 5 to: “1 µF
(electrolithic/tantalum) + 47 nF (ceramic) capacitance needs to be provided between
VDD_ADC/VSS_ADC pair. Another ceramic cap of 10nF with low inductance package can be
added”.
In Section 2.17.2, “Low voltage detector electrical characteristics, added a note on
LVHVD5 detector.
In Section 4, “Ordering information, added a note: “Not all options are available on all
devices”.
14
30 oct 2017
15
In Table 1 (MPC5604B/C device comparison) for MPC56 04BxLH changed the CAN from
2 to 3.
In Table 12 (Recommended operating conditions (3.3 V)) added Min value for TVDD
In Table 13 (Recommended operating conditions (5.0 V)) added Min value for TVDD
8 August 2021 In 4, Ordering information, updated Fab and Masking information.
MPC5604B/C Microcontroller Data Sheet, Rev. 15
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Abbreviations
Appendix A Abbreviations
Table A-1 lists abbreviations used but not defined elsewhere in this document.
Table A-1. Abbreviations
Abbreviation
Meaning
CMOS
Complementary metal–oxide–semiconductor
CPHA
Clock phase
CPOL
Clock polarity
CS
Peripheral chip select
EVTO
Event out
MCKO
Message clock out
MDO
Message data out
MSEO
Message start/end out
MTFE
Modified timing format enable
SCK
Serial communications clock
SOUT
Serial data out
TBD
To be defined
TCK
Test clock input
TDI
Test data input
TDO
Test data output
TMS
Test mode select
MPC5604B/C Microcontroller Data Sheet, Rev. 15
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PEG, PowerQUICC, Processor Expert, QorIQ, QorIQ Qonverge, Ready Play,
SafeAssure, the SafeAssure logo, StarCore, Symphony, VortiQa, Vybrid, Airfast,
BeeKit, BeeStack, CoreNet, Flexis, MXC, Platform in a Package, QUICC Engine,
SMARTMOS, Tower, TurboLink, and UMEMS are trademarks of NXP B.V. All other
product or service names are the property of their respective owners. AMBA, Arm,
Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight,
Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP,
RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME,
ULINK-PLUS, ULINKpro, ÉþVision, Versatile are trademarks or registered trademarks
of Arm Limited (or its subsidiaries) in the US and/or elsewhere. The related technology
may be protected by any or all of patents, copyrights, designs and trade secrets. All
rights reserved. Oracle and Java are registered trademarks of Oracle and/or its
affiliates. The Power Architecture and Power.org word marks and the Power and
Power.org logos and related marks are trademarks and service marks licensed by
Power.org.
© 2021 NXP B.V.
Document Number: MPC5604BC
Rev. 15
10/2021
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