NXP Semiconductors
Data Sheet: Technical Data
Document Number: MPC5606B
Rev. 5, 11/2017
MPC5606BK
100 LQFP
14 mm x 14 mm
MPC5606BK Microcontroller
Data Sheet
1
Introduction
1.1
Document overview
This document describes the features of the family and
options available within the family members, and highlights
important electrical and physical characteristics of the device.
1.2
176 LQFP
24 mm x 24 mm
1
2
3
Description
This family of 32-bit system-on-chip (SoC) microcontrollers
is the latest achievement in integrated automotive application
controllers. It belongs to an expanding family of
automotive-focused products designed to address the next
wave of body electronics applications within the vehicle.
The advanced and cost-efficient e200z0 host processor core of
this automotive controller family complies with the Power
Architecture® technology and only implements the VLE
(variable-length encoding) APU (Auxiliary Processor Unit),
providing improved code density. It operates at speeds of up
to 64 MHz and offers high performance processing optimized
for low power consumption. It capitalizes on the available
development infrastructure of current Power Architecture
devices and is supported with software drivers, operating
systems and configuration code to assist with users
implementations.
144 LQFP
20 mm x 20 mm
4
5
6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . 4
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . 27
3.4 Recommended operating conditions . . . . . . . . . . . . . . . 28
3.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.6 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . 33
3.7 RESET electrical characteristics . . . . . . . . . . . . . . . . . . 45
3.8 Power management electrical characteristics . . . . . . . . 48
3.9 Power consumption in different application modes . . . . 53
3.10 Flash memory electrical characteristics . . . . . . . . . . . . . 54
3.11 Electromagnetic compatibility (EMC) characteristics . . . 56
3.12 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.13 Slow external crystal oscillator (32 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.14 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . . 63
3.15 Fast internal RC oscillator (16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.16 Slow internal RC oscillator (128 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.17 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . . 66
3.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.1 Package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . 85
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
1.3
Device comparison
Table 1 summarizes the functions of the blocks present on the MPC5606BK.
Table 1. MPC5606BK family comparison1
Feature
MPC5605BK
Package
100 LQFP
144 LQFP
MPC5606BK
176 LQFP
CPU
100 LQFP
144 LQFP
176 LQFP
e200z0h
Execution speed2
Up to 64 MHz
Code flash memory
768 KB
1 MB
Data flash memory
64 (4 x 16) KB
SRAM
64 KB
80 KB
MPU
8-entry
eDMA
16 ch
10-bit ADC
Yes
dedicated3
7 ch
15 ch
29 ch
shared with 12-bit ADC
7 ch
15 ch
29 ch
19 ch
12-bit ADC
Yes
dedicated4
5 ch
shared with 10-bit ADC
19 ch
Total timer I/O5
eMIOS
37 ch,
16-bit
64 ch,
16-bit
37 ch,
16-bit
Counter / OPWM / ICOC6
10 ch
7
7 ch
O(I)PWM / OPWFMB / OPWMCB / ICOC
O(I)PWM /
ICOC8
9
OPWM / ICOC
64 ch,
16-bit
7 ch
14 ch
13 ch
33 ch
SCI (LINFlex)
4
6
8
4
6
8
SPI (DSPI)
3
5
6
3
5
6
77
121
149
CAN (FlexCAN)
6
I2C
1
32 KHz oscillator
GPIO10
Debug
Yes
77
121
149
JTAG
1
Feature set dependent on selected peripheral multiplexing; table shows example.
Based on 125 °C ambient operating temperature.
3
Not shared with 12-bit ADC, but possibly shared with other alternate functions.
4 Not shared with 10-bit ADC, but possibly shared with other alternate functions.
5 Refer to eMIOS section of device reference manual for information on the channel configuration and functions.
6 Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output Compare.
7 Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output Compare.
8
Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and Pulse width
measurement.
9 Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare.
10 Maximum I/O count based on multiplexing with peripherals.
2
MPC5606BK Microcontroller Data Sheet, Rev. 5
2
NXP Semiconductors
1.4
Block diagram
Figure 1 shows a top-level block diagram of the MPC5606BK.
SRAM
80 KB
Code Flash Data Flash
1.0 MB
64 KB
SRAM
Controller
Flash memory
controller
eDMA
JTAG
(Master)
Data
NMI
(Master)
SIUL
Voltage
Regulator
Interrupt requests
from peripheral
blocks
NMI
INTC
Clocks
MPU
Instructions
e200z0h
64-bit 3 × 3 Crossbar Switch
(Master)
JTAG Port
(Slave)
(Slave)
Interrupt
request with
wakeup
functionality
(Slave)
MPU
Registers
WKPU
CMU
FMPLL
RTC
STM
SWT
ECSM
MC_RGM MC_CGM
PIT
MC_ME MC_PCU
BAM
SSCM
I2C
6x
FlexCAN
Peripheral Bridge
Interrupt
Request
SIUL
Reset Control
19 ch 10-bit/12-bit
ADC
External
Interrupt
Request
29 ch 10-bit
ADC
8x
LINFlex
64 ch
eMIOS
CTU
6x
DSPI
5 ch 12-bit
ADC
IMUX
GPIO &
Pad Control
I/O
...
...
...
...
...
Legend:
ADC
BAM
FlexCAN
CFlash
CMU
CTU
DFlash
DSPI
eDMA
eMIOS
FMPLL
I2C
IMUX
INTC
JTAG
Analog-to-Digital Converter
Boot Assist Module
Controller Area Network
Code flash memory
Clock Monitor Unit
Cross Triggering Unit
Data flash memory
Deserial Serial Peripheral Interface
Enhanced Direct Memory Access
Enhanced Modular Input Output System
Frequency-Modulated Phase-Locked Loop
Inter-integrated Circuit Bus
Internal Multiplexer
Interrupt Controller
JTAG controller
LINFlex
MC_CGM
MC_ME
MPU
NMI
MC_PCU
MC_RGM
PIT
RTC
SIUL
SRAM
SSCM
STM
SWT
WKPU
Serial Communication Interface (LIN support)
Clock Generation Module
Mode Entry Module
Memory Protection Unit
Non-Maskable Interrupt
Power Control Unit
Reset Generation Module
Periodic Interrupt Timer
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Wakeup Unit
Figure 1. MPC5606BK block diagram
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
3
2
Package pinouts and signal descriptions
2.1
Package pinouts
The available LQFP pinouts are provided in the following figures. For pin signal descriptions, please see Table 2.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176 LQFP
Top view
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PE[13]
PF[14]
PF[15]
VDD_HV
VSS_HV
PG[0]
PG[1]
PH[3]
PH[2]
PH[1]
PH[0]
PG[12]
PG[13]
PA[3]
PI[13]
PI[12]
PI[11]
PI[10]
PI[9]
PI[8]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
PD[12]
VDD_HV_ADC1
VSS_HV_ADC1
PB[11]
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC0
VSS_HV_ADC0
PC[7]
PF[10]
PF[11]
PA[15]
PF[13]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PB[9]
PB[8]
PB[10]
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PJ[3]
PJ[2]
PJ[1]
PJ[0]
PI[15]
PI[14]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
VDD_HV
VSS_HV
PD[8]
PB[4]
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PB[3]
PC[9]
PC[14]
PC[15]
PJ[4]
VDD_HV
VSS_HV
PH[15]
PH[13]
PH[14]
PI[6]
PI[7]
PG[5]
PG[4]
PG[3]
PG[2]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PG[9]
PG[8]
PC[11]
PC[10]
PG[7]
PG[6]
PB[0]
PB[1]
PF[9]
PF[8]
PF[12]
PC[6]
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PB[2]
PC[8]
PC[13]
PC[12]
PI[0]
PI[1]
PI[2]
PI[3]
PE[7]
PE[6]
PH[8]
PH[7]
PH[6]
PH[5]
PH[4]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PI[4]
PI[5]
PH[12]
PH[11]
PG[11]
PG[10]
PE[15]
PE[14]
PG[15]
PG[14]
PE[12]
Figure 2 shows the MPC5606BK in the 176 LQFP package.
Figure 2. 176 LQFP pinout
MPC5606BK Microcontroller Data Sheet, Rev. 5
4
NXP Semiconductors
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PB[2]
PC[8]
PC[13]
PC[12]
PE[7]
PE[6]
PH[8]
PH[7]
PH[6]
PH[5]
PH[4]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PG[11]
PG[10]
PE[15]
PE[14]
PG[15]
PG[14]
PE[12]
Figure 3 shows the MPC5606BK in the 144 LQFP package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144 LQFP
Top view
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PE[13]
PF[14]
PF[15]
VDD_HV
VSS_HV
PG[0]
PG[1]
PH[3]
PH[2]
PH[1]
PH[0]
PG[12]
PG[13]
PA[3]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
VDD_HV_ADC1
VSS_HV_ADC1
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC0
VSS_HV_ADC0
PC[7]
PF[10]
PF[11]
PA[15]
PF[13]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PB[9]
PB[8]
PB[10]
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PB[4]
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PB[3]
PC[9]
PC[14]
PC[15]
PG[5]
PG[4]
PG[3]
PG[2]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PG[9]
PG[8]
PC[11]
PC[10]
PG[7]
PG[6]
PB[0]
PB[1]
PF[9]
PF[8]
PF[12]
PC[6]
Figure 3. 144 LQFP pinout
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
5
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PB[2]
PC[8]
PC[13]
PC[12]
PE[7]
PE[6]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PE[12]
Figure 4 shows the MPC5606BK in the 100 LQFP package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100 LQFP
Top view
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
VDD_HV
VSS_HV
PA[3]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
VDD_HV_ADC1
VSS_HV_ADC1
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC0
VSS_HV_ADC0
PC[7]
PA[15]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PB[9]
PB[8]
PB[10]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PB[4]
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PB[3]
PC[9]
PC[14]
PC[15]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[11]
PC[10]
PB[0]
PB[1]
PC[6]
Figure 4. 100 LQFP pinout
MPC5606BK Microcontroller Data Sheet, Rev. 5
6
NXP Semiconductors
2.2
Pin muxing
Table 2 defines the pin list and muxing for this device.
Each entry of Table 2 shows all the possible configurations for each pin, via the alternate functions. The default function
assigned to each pin after reset is indicated by AF0.
Pad type2
RESET
config.3
Pin number
I/O
direction
Peripheral
Table 2. Functional port pins
100
LQFP
PA[0]
PCR[0]
AF0
AF1
AF2
AF3
—
GPIO[0]
E0UC[0]
CLKOUT
E0UC[13]
WKUP[19]4
SIUL
eMIOS_0
MC_CGM
eMIOS_0
WKUP
I/O
I/O
O
I/O
I
M
Tristate
12
16
24
PA[1]
PCR[1]
AF0
AF1
AF2
AF3
—
GPIO[1]
E0UC[1]
NMI5
—
WKUP[2]4
SIUL
eMIOS_0
WKUP
—
WKUP
I/O
I/O
I
—
I
S
Tristate
7
11
19
PA[2]
PCR[2]
AF0
AF1
AF2
AF3
—
GPIO[2]
E0UC[2]
—
MA[2]
WKUP[3]4
SIUL
eMIOS_0
—
ADC_0
WKUP
I/O
I/O
—
O
I
S
Tristate
5
9
17
PA[3]
PCR[3]
AF0
AF1
AF2
AF3
—
—
GPIO[3]
E0UC[3]
LIN5TX
CS4_1
EIRQ[0]
ADC1_S[0]
SIUL
eMIOS_0
LINFlex_5
DSPI_1
SIUL
ADC_1
I/O
I/O
O
O
I
I
J
Tristate
68
90
114
PA[4]
PCR[4]
AF0
AF1
AF2
AF3
—
—
GPIO[4]
E0UC[4]
—
CS0_1
LIN5RX
WKUP[9]4
SIUL
eMIOS_0
—
DSPI_1
LINFlex_5
WKUP
I/O
I/O
—
I/O
I
I
S
Tristate
29
43
51
PA[5]
PCR[5]
AF0
AF1
AF2
AF3
GPIO[5]
E0UC[5]
LIN4TX
—
SIUL
eMIOS_0
LINFlex_4
—
I/O
I/O
O
—
M
Tristate
79
118
146
PA[6]
PCR[6]
AF0
AF1
AF2
AF3
—
—
GPIO[6]
E0UC[6]
—
CS1_1
EIRQ[1]
LIN4RX
SIUL
eMIOS_0
—
DSPI_1
SIUL
LINFlex_4
I/O
I/O
—
O
I
I
S
Tristate
80
119
147
Port
pin
PCR
Alternate
register function1
Function
144
LQFP
176
LQFP
Port A
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
7
GPIO[7]
E0UC[7]
LIN3TX
—
EIRQ[2]
ADC1_S[1]
SIUL
eMIOS_0
LINFlex_3
—
SIUL
ADC_1
I/O
I/O
O
—
I
I
PCR[8]
AF0
AF1
AF2
AF3
—
N/A6
—
GPIO[8]
E0UC[8]
E0UC[14]
—
EIRQ[3]
ABS[0]
LIN3RX
SIUL
eMIOS_0
eMIOS_0
—
SIUL
BAM
LINFlex_3
I/O
I/O
I/O
—
I
I
I
PA[9]
PCR[9]
AF0
AF1
AF2
AF3
N/A6
GPIO[9]
E0UC[9]
—
CS2_1
FAB
SIUL
eMIOS_0
—
DSPI_1
BAM
PA[10]
PCR[10]
AF0
AF1
AF2
AF3
—
GPIO[10]
E0UC[10]
SDA
LIN2TX
ADC1_S[2]
PA[11]
PCR[11]
AF0
AF1
AF2
AF3
—
—
—
PA[12]
PCR[12]
PA[13]
PA[14]
RESET
config.3
I/O
direction
AF0
AF1
AF2
AF3
—
—
Pin number
Pad type2
Function
Peripheral
Table 2. Functional port pins (continued)
100
LQFP
144
LQFP
176
LQFP
J
Tristate
71
104
128
S
Input,
weak
pull-up
72
105
129
I/O
I/O
—
O
I
S
Pulldown
73
106
130
SIUL
eMIOS_0
I2C_0
LINFlex_2
ADC_1
I/O
I/O
I/O
O
I
J
Tristate
74
107
131
GPIO[11]
E0UC[11]
SCL
—
EIRQ[16]
LIN2RX
ADC1_S[3]
SIUL
eMIOS_0
I2C_0
—
SIUL
LINFlex_2
ADC_1
I/O
I/O
I/O
—
I
I
I
J
Tristate
75
108
132
AF0
AF1
AF2
AF3
—
—
GPIO[12]
—
E0UC[28]
CS3_1
EIRQ[17]
SIN_0
SIUL
—
eMIOS_0
DSPI_1
SIUL
DSPI_0
I/O
—
I/O
O
I
I
S
Tristate
31
45
53
PCR[13]
AF0
AF1
AF2
AF3
GPIO[13]
SOUT_0
E0UC[29]
—
SIUL
DSPI_0
eMIOS_0
—
I/O
O
I/O
—
M
Tristate
30
44
52
PCR[14]
AF0
AF1
AF2
AF3
—
GPIO[14]
SCK_0
CS0_0
E0UC[0]
EIRQ[4]
SIUL
DSPI_0
DSPI_0
eMIOS_0
SIUL
I/O
I/O
I/O
I/O
I
M
Tristate
28
42
50
Port
pin
PCR
Alternate
register function1
PA[7]
PCR[7]
PA[8]
MPC5606BK Microcontroller Data Sheet, Rev. 5
8
NXP Semiconductors
AF0
AF1
AF2
AF3
—
GPIO[15]
CS0_0
SCK_0
E0UC[1]
WKUP[10]4
RESET
config.3
PCR[15]
Function
Pad type2
PA[15]
PCR
Alternate
register function1
I/O
direction
Port
pin
Peripheral
Table 2. Functional port pins (continued)
100
LQFP
SIUL
DSPI_0
DSPI_0
eMIOS_0
WKUP
I/O
I/O
I/O
I/O
I
M
Tristate
27
40
48
Pin number
144
LQFP
176
LQFP
Port B
PB[0]
PCR[16]
AF0
AF1
AF2
AF3
GPIO[16]
CAN0TX
E0UC[30]
LIN0TX
SIUL
FlexCAN_0
eMIOS_0
LINFlex_0
I/O
O
I/O
O
M
Tristate
23
31
39
PB[1]
PCR[17]
AF0
AF1
AF2
AF3
—
—
—
GPIO[17]
—
E0UC[31]
—
WKUP[4]4
CAN0RX
LIN0RX
SIUL
—
eMIOS_0
—
WKUP
FlexCAN_0
LINFlex_0
I/O
—
I/O
—
I
I
I
S
Tristate
24
32
40
PB[2]
PCR[18]
AF0
AF1
AF2
AF3
GPIO[18]
LIN0TX
SDA
E0UC[30]
SIUL
LINFlex_0
I2C_0
eMIOS_0
I/O
O
I/O
I/O
M
Tristate
100
144
176
PB[3]
PCR[19]
AF0
AF1
AF2
AF3
—
—
GPIO[19]
E0UC[31]
SCL
—
WKUP[11]4
LIN0RX
SIUL
eMIOS_0
I2C_0
—
WKUP
LINFlex_0
I/O
I/O
I/O
—
I
I
S
Tristate
1
1
1
PB[4]
PCR[20]
AF0
AF1
AF2
AF3
—
—
—
—
—
—
—
ADC0_P[0]
ADC1_P[0]
GPIO[20]
—
—
—
—
ADC_0
ADC_1
SIUL
—
—
—
—
I
I
I
I
Tristate
50
72
88
PB[5]
PCR[21]
AF0
AF1
AF2
AF3
—
—
—
—
—
—
—
ADC0_P[1]
ADC1_P[1]
GPIO[21]
—
—
—
—
ADC_0
ADC_1
SIUL
—
—
—
—
I
I
I
I
Tristate
53
75
91
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
9
—
—
—
—
ADC0_P[2]
ADC1_P[2]
GPIO[22]
—
—
—
—
ADC_0
ADC_1
SIUL
—
—
—
—
I
I
I
PCR[23]
AF0
AF1
AF2
AF3
—
—
—
—
—
—
—
ADC0_P[3]
ADC1_P[3]
GPIO[23]
—
—
—
—
ADC_0
ADC_1
SIUL
—
—
—
—
I
I
I
PB[8]
PCR[24]
AF0
AF1
AF2
AF3
—
—
—
—
GPIO[24]
—
—
—
OSC32K_XTAL7
WKUP[25]
ADC0_S[0]
ADC1_S[4]
SIUL
—
—
—
OSC32K
WKUP
ADC_0
ADC_1
PB[9]
PCR[25]
AF0
AF1
AF2
AF3
—
—
—
—
GPIO[25]
—
—
—
OSC32K_EXTAL7
WKUP[26]
ADC0_S[1]
ADC1_S[5]
PB[10]
PCR[26]
AF0
AF1
AF2
AF3
—
—
—
PB[11]
PCR[27]
PB[12]
PCR[28]
RESET
config.3
I/O
direction
AF0
AF1
AF2
AF3
—
—
—
Pin number
Pad type2
Function
Peripheral
Table 2. Functional port pins (continued)
100
LQFP
144
LQFP
176
LQFP
I
Tristate
54
76
92
I
Tristate
55
77
93
I
—
—
—
—
I
I
I
I
—
39
53
61
SIUL
—
—
—
OSC32K
WKUP
ADC_0
ADC_1
I
—
—
—
—
I
I
I
I
—
38
52
60
GPIO[26]
—
—
—
WKUP[8]4
ADC0_S[2]
ADC1_S[6]
SIUL
—
—
—
WKUP
ADC_0
ADC_1
I/O
—
—
—
I
I
I
J
Tristate
40
54
62
AF0
AF1
AF2
AF3
—
GPIO[27]
E0UC[3]
—
CS0_0
ADC0_S[3]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
I/O
I
J
Tristate
—
—
97
AF0
AF1
AF2
AF3
—
GPIO[28]
E0UC[4]
—
CS1_0
ADC0_X[0]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
J
Tristate
61
83
101
Port
pin
PCR
Alternate
register function1
PB[6]
PCR[22]
PB[7]
MPC5606BK Microcontroller Data Sheet, Rev. 5
10
NXP Semiconductors
Peripheral
I/O
direction
Pad type2
RESET
config.3
Table 2. Functional port pins (continued)
100
LQFP
PB[13]
PCR[29]
AF0
AF1
AF2
AF3
—
GPIO[29]
E0UC[5]
—
CS2_0
ADC0_X[1]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
J
Tristate
63
85
103
PB[14]
PCR[30]
AF0
AF1
AF2
AF3
—
GPIO[30]
E0UC[6]
—
CS3_0
ADC0_X[2]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
J
Tristate
65
87
105
PB[15]
PCR[31]
AF0
AF1
AF2
AF3
—
GPIO[31]
E0UC[7]
—
CS4_0
ADC0_X[3]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
J
Tristate
67
89
107
Port
pin
PCR
Alternate
register function1
Function
Pin number
144
LQFP
176
LQFP
Port C
PC[0]8
PCR[32]
AF0
AF1
AF2
AF3
GPIO[32]
—
TDI
—
SIUL
—
JTAGC
—
I/O
—
I
—
M
Input,
weak
pull-up
87
126
154
PC[1]8
PCR[33]
AF0
AF1
AF2
AF3
GPIO[33]
—
TDO
—
SIUL
—
JTAGC
—
I/O
—
O
—
F9 Tristate
82
121
149
PC[2]
PCR[34]
AF0
AF1
AF2
AF3
—
GPIO[34]
SCK_1
CAN4TX
DEBUG[0]
EIRQ[5]
SIUL
DSPI_1
FlexCAN_4
SSCM
SIUL
I/O
I/O
O
O
I
M
Tristate
78
117
145
PC[3]
PCR[35]
AF0
AF1
AF2
AF3
—
—
—
GPIO[35]
CS0_1
MA[0]
DEBUG[1]
EIRQ[6]
CAN1RX
CAN4RX
SIUL
DSPI_1
ADC_0
SSCM
SIUL
FlexCAN_1
FlexCAN_4
I/O
I/O
O
O
I
I
I
S
Tristate
77
116
144
PC[4]
PCR[36]
AF0
AF1
AF2
AF3
—
—
—
GPIO[36]
E1UC[31]
—
DEBUG[2]
EIRQ[18]
SIN_1
CAN3RX
SIUL
eMIOS_1
—
SSCM
SIUL
DSPI_1
FlexCAN_3
I/O
I/O
—
O
I
I
I
M
Tristate
92
131
159
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
11
GPIO[37]
SOUT_1
CAN3TX
DEBUG[3]
EIRQ[7]
SIUL
DSPI_1
FlexCAN_3
SSCM
SIUL
I/O
O
O
O
I
PCR[38]
AF0
AF1
AF2
AF3
GPIO[38]
LIN1TX
E1UC[28]
DEBUG[4]
SIUL
LINFlex_1
eMIOS_1
SSCM
I/O
O
I/O
O
PC[7]
PCR[39]
AF0
AF1
AF2
AF3
—
—
GPIO[39]
—
E1UC[29]
DEBUG[5]
LIN1RX
WKUP[12]4
SIUL
—
eMIOS_1
SSCM
LINFlex_1
WKUP
PC[8]
PCR[40]
AF0
AF1
AF2
AF3
GPIO[40]
LIN2TX
E0UC[3]
DEBUG[6]
PC[9]
PCR[41]
AF0
AF1
AF2
AF3
—
—
PC[10] PCR[42]
RESET
config.3
I/O
direction
AF0
AF1
AF2
AF3
—
Pin number
Pad type2
Function
Peripheral
Table 2. Functional port pins (continued)
100
LQFP
144
LQFP
176
LQFP
M
Tristate
91
130
158
S
Tristate
25
36
44
I/O
—
I/O
O
I
I
S
Tristate
26
37
45
SIUL
LINFlex_2
eMIOS_0
SSCM
I/O
O
I/O
O
S
Tristate
99
143
175
GPIO[41]
—
E0UC[7]
DEBUG[7]
WKUP[13]4
LIN2RX
SIUL
—
eMIOS_0
SSCM
WKUP
LINFlex_2
I/O
—
I/O
O
I
I
S
Tristate
2
2
2
AF0
AF1
AF2
AF3
GPIO[42]
CAN1TX
CAN4TX
MA[1]
SIUL
FlexCAN_1
FlexCAN_4
ADC_0
I/O
O
O
O
M
Tristate
22
28
36
PC[11] PCR[43]
AF0
AF1
AF2
AF3
—
—
—
GPIO[43]
—
—
MA[2]
WKUP[5]4
CAN1RX
CAN4RX
SIUL
—
—
ADC_0
WKUP
FlexCAN_1
FlexCAN_4
I/O
—
—
O
I
I
I
S
Tristate
21
27
35
PC[12] PCR[44]
AF0
AF1
AF2
AF3
—
—
GPIO[44]
E0UC[12]
—
—
EIRQ[19]
SIN_2
SIUL
eMIOS_0
—
—
SIUL
DSPI_2
I/O
I/O
—
—
I
I
M
Tristate
97
141
173
PC[13] PCR[45]
AF0
AF1
AF2
AF3
GPIO[45]
E0UC[13]
SOUT_2
—
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
O
—
S
Tristate
98
142
174
Port
pin
PCR
Alternate
register function1
PC[5]
PCR[37]
PC[6]
MPC5606BK Microcontroller Data Sheet, Rev. 5
12
NXP Semiconductors
Peripheral
I/O
direction
Pad type2
RESET
config.3
Table 2. Functional port pins (continued)
100
LQFP
PC[14] PCR[46]
AF0
AF1
AF2
AF3
—
GPIO[46]
E0UC[14]
SCK_2
—
EIRQ[8]
SIUL
eMIOS_0
DSPI_2
—
SIUL
I/O
I/O
I/O
—
I
S
Tristate
3
3
3
PC[15] PCR[47]
AF0
AF1
AF2
AF3
—
GPIO[47]
E0UC[15]
CS0_2
—
EIRQ[20]
SIUL
eMIOS_0
DSPI_2
—
SIUL
I/O
I/O
I/O
—
I
M
Tristate
4
4
4
Port
pin
PCR
Alternate
register function1
Function
Pin number
144
LQFP
176
LQFP
Port D
PD[0]
PCR[48]
AF0
AF1
AF2
AF3
—
—
—
GPIO[48]
—
—
—
WKUP[27]
ADC0_P[4]
ADC1_P[4]
SIUL
—
—
—
WKUP
ADC_0
ADC_1
I
—
—
—
I
I
I
I
Tristate
41
63
77
PD[1]
PCR[49]
AF0
AF1
AF2
AF3
—
—
—
GPIO[49]
—
—
—
WKUP[28]
ADC0_P[5]
ADC1_P[5]
SIUL
—
—
—
WKUP
ADC_0
ADC_1
I
—
—
—
I
I
I
I
Tristate
42
64
78
PD[2]
PCR[50]
AF0
AF1
AF2
AF3
—
—
GPIO[50]
—
—
—
ADC0_P[6]
ADC1_P[6]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
43
65
79
PD[3]
PCR[51]
AF0
AF1
AF2
AF3
—
—
GPIO[51]
—
—
—
ADC0_P[7]
ADC1_P[7]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
44
66
80
PD[4]
PCR[52]
AF0
AF1
AF2
AF3
—
—
GPIO[52]
—
—
—
ADC0_P[8]
ADC1_P[8]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
45
67
81
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
13
GPIO[53]
—
—
—
ADC0_P[9]
ADC1_P[9]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
PCR[54]
AF0
AF1
AF2
AF3
—
—
GPIO[54]
—
—
—
ADC0_P[10]
ADC1_P[10]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
PD[7]
PCR[55]
AF0
AF1
AF2
AF3
—
—
GPIO[55]
—
—
—
ADC0_P[11]
ADC1_P[11]
SIUL
—
—
—
ADC_0
ADC_1
PD[8]
PCR[56]
AF0
AF1
AF2
AF3
—
—
GPIO[56]
—
—
—
ADC0_P[12]
ADC1_P[12]
PD[9]
PCR[57]
AF0
AF1
AF2
AF3
—
—
PD[10] PCR[58]
RESET
config.3
I/O
direction
AF0
AF1
AF2
AF3
—
—
Pin number
Pad type2
Function
Peripheral
Table 2. Functional port pins (continued)
100
LQFP
144
LQFP
176
LQFP
I
Tristate
46
68
82
I
Tristate
47
69
83
I
—
—
—
I
I
I
Tristate
48
70
84
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
49
71
87
GPIO[57]
—
—
—
ADC0_P[13]
ADC1_P[13]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
56
78
94
AF0
AF1
AF2
AF3
—
—
GPIO[58]
—
—
—
ADC0_P[14]
ADC1_P[14]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
57
79
95
PD[11] PCR[59]
AF0
AF1
AF2
AF3
—
—
GPIO[59]
—
—
—
ADC0_P[15]
ADC1_P[15]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
58
80
96
PD[12] PCR[60]
AF0
AF1
AF2
AF3
—
GPIO[60]
CS5_0
E0UC[24]
—
ADC0_S[4]
SIUL
DSPI_0
eMIOS_0
—
ADC_0
I/O
O
I/O
—
I
J
Tristate
—
—
100
Port
pin
PCR
Alternate
register function1
PD[5]
PCR[53]
PD[6]
MPC5606BK Microcontroller Data Sheet, Rev. 5
14
NXP Semiconductors
Peripheral
I/O
direction
Pad type2
RESET
config.3
Table 2. Functional port pins (continued)
100
LQFP
PD[13] PCR[61]
AF0
AF1
AF2
AF3
—
GPIO[61]
CS0_1
E0UC[25]
—
ADC0_S[5]
SIUL
DSPI_1
eMIOS_0
—
ADC_0
I/O
I/O
I/O
—
I
J
Tristate
62
84
102
PD[14] PCR[62]
AF0
AF1
AF2
AF3
—
GPIO[62]
CS1_1
E0UC[26]
—
ADC0_S[6]
SIUL
DSPI_1
eMIOS_0
—
ADC_0
I/O
O
I/O
—
I
J
Tristate
64
86
104
PD[15] PCR[63]
AF0
AF1
AF2
AF3
—
GPIO[63]
CS2_1
E0UC[27]
—
ADC0_S[7]
SIUL
DSPI_1
eMIOS_0
—
ADC_0
I/O
O
I/O
—
I
J
Tristate
66
88
106
Port
pin
PCR
Alternate
register function1
Function
Pin number
144
LQFP
176
LQFP
Port E
PE[0]
PCR[64]
AF0
AF1
AF2
AF3
—
—
GPIO[64]
E0UC[16]
—
—
WKUP[6]4
CAN5RX
SIUL
eMIOS_0
—
—
WKUP
FlexCAN_5
I/O
I/O
—
—
I
I
S
Tristate
6
10
18
PE[1]
PCR[65]
AF0
AF1
AF2
AF3
GPIO[65]
E0UC[17]
CAN5TX
—
SIUL
eMIOS_0
FlexCAN_5
—
I/O
I/O
O
—
M
Tristate
8
12
20
PE[2]
PCR[66]
AF0
AF1
AF2
AF3
—
—
GPIO[66]
E0UC[18]
—
—
EIRQ[21]
SIN_1
SIUL
eMIOS_0
—
—
SIUL
DSPI_1
I/O
I/O
—
—
I
I
M
Tristate
89
128
156
PE[3]
PCR[67]
AF0
AF1
AF2
AF3
GPIO[67]
E0UC[19]
SOUT_1
—
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
O
—
M
Tristate
90
129
157
PE[4]
PCR[68]
AF0
AF1
AF2
AF3
—
GPIO[68]
E0UC[20]
SCK_1
—
EIRQ[9]
SIUL
eMIOS_0
DSPI_1
—
SIUL
I/O
I/O
I/O
—
I
M
Tristate
93
132
160
PE[5]
PCR[69]
AF0
AF1
AF2
AF3
GPIO[69]
E0UC[21]
CS0_1
MA[2]
SIUL
eMIOS_0
DSPI_1
ADC_0
I/O
I/O
I/O
O
M
Tristate
94
133
161
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
15
GPIO[70]
E0UC[22]
CS3_0
MA[1]
EIRQ[22]
SIUL
eMIOS_0
DSPI_0
ADC_0
SIUL
I/O
I/O
O
O
I
PCR[71]
AF0
AF1
AF2
AF3
—
GPIO[71]
E0UC[23]
CS2_0
MA[0]
EIRQ[23]
SIUL
eMIOS_0
DSPI_0
ADC_0
SIUL
I/O
I/O
O
O
I
PE[8]
PCR[72]
AF0
AF1
AF2
AF3
GPIO[72]
CAN2TX
E0UC[22]
CAN3TX
SIUL
FlexCAN_2
eMIOS_0
FlexCAN_3
PE[9]
PCR[73]
AF0
AF1
AF2
AF3
—
—
—
GPIO[73]
—
E0UC[23]
—
WKUP[7]4
CAN2RX
CAN3RX
PE[10]
PCR[74]
AF0
AF1
AF2
AF3
—
PE[11]
PCR[75]
PE[12]
PE[13]
RESET
config.3
I/O
direction
AF0
AF1
AF2
AF3
—
Pin number
Pad type2
Function
Peripheral
Table 2. Functional port pins (continued)
100
LQFP
144
LQFP
176
LQFP
M
Tristate
95
139
167
M
Tristate
96
140
168
I/O
O
I/O
O
M
Tristate
9
13
21
SIUL
—
eMIOS_0
—
WKUP
FlexCAN_2
FlexCAN_3
I/O
—
I/O
—
I
I
I
S
Tristate
10
14
22
GPIO[74]
LIN3TX
CS3_1
E1UC[30]
EIRQ[10]
SIUL
LINFlex_3
DSPI_1
eMIOS_1
SIUL
I/O
O
O
I/O
I
S
Tristate
11
15
23
AF0
AF1
AF2
AF3
—
—
GPIO[75]
E0UC[24]
CS4_1
—
LIN3RX
WKUP[14]4
SIUL
eMIOS_0
DSPI_1
—
LINFlex_3
WKUP
I/O
I/O
O
—
I
I
S
Tristate
13
17
25
PCR[76]
AF0
AF1
AF2
AF3
—
—
—
GPIO[76]
—
E1UC[19]10
—
EIRQ[11]
SIN_2
ADC1_S[7]
SIUL
—
eMIOS_1
—
SIUL
DSPI_2
ADC_1
I/O
—
I/O
—
I
I
I
J
Tristate
76
109
133
PCR[77]
AF0
AF1
AF2
AF3
GPIO[77]
SOUT_2
E1UC[20]
—
SIUL
DSPI_2
eMIOS_1
—
I/O
O
I/O
—
S
Tristate
—
103
127
Port
pin
PCR
Alternate
register function1
PE[6]
PCR[70]
PE[7]
MPC5606BK Microcontroller Data Sheet, Rev. 5
16
NXP Semiconductors
Peripheral
I/O
direction
Pad type2
RESET
config.3
Table 2. Functional port pins (continued)
100
LQFP
PE[14]
PCR[78]
AF0
AF1
AF2
AF3
—
GPIO[78]
SCK_2
E1UC[21]
—
EIRQ[12]
SIUL
DSPI_2
eMIOS_1
—
SIUL
I/O
I/O
I/O
—
I
S
Tristate
—
112
136
PE[15]
PCR[79]
AF0
AF1
AF2
AF3
GPIO[79]
CS0_2
E1UC[22]
—
SIUL
DSPI_2
eMIOS_1
—
I/O
I/O
I/O
—
M
Tristate
—
113
137
Port
pin
PCR
Alternate
register function1
Function
Pin number
144
LQFP
176
LQFP
Port F
PF[0]
PCR[80]
AF0
AF1
AF2
AF3
—
GPIO[80]
E0UC[10]
CS3_1
—
ADC0_S[8]
SIUL
eMIOS_0
DSPI_1
—
ADC_0
I/O
I/O
O
—
I
J
Tristate
—
55
63
PF[1]
PCR[81]
AF0
AF1
AF2
AF3
—
GPIO[81]
E0UC[11]
CS4_1
—
ADC0_S[9]
SIUL
eMIOS_0
DSPI_1
—
ADC_0
I/O
I/O
O
—
I
J
Tristate
—
56
64
PF[2]
PCR[82]
AF0
AF1
AF2
AF3
—
GPIO[82]
E0UC[12]
CS0_2
—
ADC0_S[10]
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
O
—
I
J
Tristate
—
57
65
PF[3]
PCR[83]
AF0
AF1
AF2
AF3
—
GPIO[83]
E0UC[13]
CS1_2
—
ADC0_S[11]
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
O
—
I
J
Tristate
—
58
66
PF[4]
PCR[84]
AF0
AF1
AF2
AF3
—
GPIO[84]
E0UC[14]
CS2_2
—
ADC0_S[12]
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
O
—
I
J
Tristate
—
59
67
PF[5]
PCR[85]
AF0
AF1
AF2
AF3
—
GPIO[85]
E0UC[22]
CS3_2
—
ADC0_S[13]
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
O
—
I
J
Tristate
—
60
68
PF[6]
PCR[86]
AF0
AF1
AF2
AF3
—
GPIO[86]
E0UC[23]
CS1_1
—
ADC0_S[14]
SIUL
eMIOS_0
DSPI_1
—
ADC_0
I/O
I/O
O
—
I
J
Tristate
—
61
69
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
17
GPIO[87]
—
CS2_1
—
ADC0_S[15]
SIUL
—
DSPI_1
—
ADC_0
I/O
—
O
—
I
PCR[88]
AF0
AF1
AF2
AF3
GPIO[88]
CAN3TX
CS4_0
CAN2TX
SIUL
FlexCAN_3
DSPI_0
FlexCAN_2
I/O
O
O
O
PF[9]
PCR[89]
AF0
AF1
AF2
AF3
—
—
—
GPIO[89]
E1UC[1]
CS5_0
—
WKUP[22]4
CAN2RX
CAN3RX
SIUL
eMIOS_1
DSPI_0
—
WKUP
FlexCAN_2
FlexCAN_3
PF[10]
PCR[90]
AF0
AF1
AF2
AF3
GPIO[90]
CS1_0
LIN4TX
E1UC[2]
PF[11]
PCR[91]
AF0
AF1
AF2
AF3
—
—
PF[12]
PCR[92]
PF[13]
PF[14]
RESET
config.3
I/O
direction
AF0
AF1
AF2
AF3
—
Pin number
Pad type2
Function
Peripheral
Table 2. Functional port pins (continued)
100
LQFP
144
LQFP
176
LQFP
J
Tristate
—
62
70
M
Tristate
—
34
42
I/O
I/O
O
—
I
I
I
S
Tristate
—
33
41
SIUL
DSPI_0
LINFlex_4
eMIOS_1
I/O
O
O
I/O
M
Tristate
—
38
46
GPIO[91]
CS2_0
E1UC[3]
—
WKUP[15]4
LIN4RX
SIUL
DSPI_0
eMIOS_1
—
WKUP
LINFlex_4
I/O
O
I/O
—
I
I
S
Tristate
—
39
47
AF0
AF1
AF2
AF3
GPIO[92]
E1UC[25]
LIN5TX
—
SIUL
eMIOS_1
LINFlex_5
—
I/O
I/O
O
—
M
Tristate
—
35
43
PCR[93]
AF0
AF1
AF2
AF3
—
—
GPIO[93]
E1UC[26]
—
—
WKUP[16]4
LIN5RX
SIUL
eMIOS_1
—
—
WKUP
LINFlex_5
I/O
I/O
—
—
I
I
S
Tristate
—
41
49
PCR[94]
AF0
AF1
AF2
AF3
GPIO[94]
CAN4TX
E1UC[27]
CAN1TX
SIUL
FlexCAN_4
eMIOS_1
FlexCAN_1
I/O
O
I/O
O
M
Tristate
—
102
126
Port
pin
PCR
Alternate
register function1
PF[7]
PCR[87]
PF[8]
MPC5606BK Microcontroller Data Sheet, Rev. 5
18
NXP Semiconductors
AF0
AF1
AF2
AF3
—
—
—
GPIO[95]
E1UC[4]
—
—
EIRQ[13]
CAN1RX
CAN4RX
RESET
config.3
PCR[95]
Function
Pad type2
PF[15]
PCR
Alternate
register function1
I/O
direction
Port
pin
Peripheral
Table 2. Functional port pins (continued)
100
LQFP
SIUL
eMIOS_1
—
—
SIUL
FlexCAN_1
FlexCAN_4
I/O
I/O
—
—
I
I
I
S
Tristate
—
101
125
Pin number
144
LQFP
176
LQFP
Port G
PG[0]
PCR[96]
AF0
AF1
AF2
AF3
GPIO[96]
CAN5TX
E1UC[23]
—
SIUL
FlexCAN_5
eMIOS_1
—
I/O
O
I/O
—
M
Tristate
—
98
122
PG[1]
PCR[97]
AF0
AF1
AF2
AF3
—
—
GPIO[97]
—
E1UC[24]
—
EIRQ[14]
CAN5RX
SIUL
—
eMIOS_1
—
SIUL
FlexCAN_5
I/O
—
I/O
—
I
I
S
Tristate
—
97
121
PG[2]
PCR[98]
AF0
AF1
AF2
AF3
GPIO[98]
E1UC[11]
SOUT_3
—
SIUL
eMIOS_1
DSPI_3
—
I/O
I/O
O
—
M
Tristate
—
8
16
PG[3]
PCR[99]
AF0
AF1
AF2
AF3
—
GPIO[99]
E1UC[12]
CS0_3
—
WKUP[17]4
SIUL
eMIOS_1
DSPI_3
—
WKUP
I/O
I/O
O
—
I
S
Tristate
—
7
15
PG[4] PCR[100]
AF0
AF1
AF2
AF3
GPIO[100]
E1UC[13]
SCK_3
—
SIUL
eMIOS_1
DSPI_3
—
I/O
I/O
I/O
—
M
Tristate
—
6
14
PG[5] PCR[101]
AF0
AF1
AF2
AF3
—
—
GPIO[101]
E1UC[14]
—
—
WKUP[18]4
SIN_3
SIUL
eMIOS_1
—
—
WKUP
DSPI_3
I/O
I/O
—
—
I
I
S
Tristate
—
5
13
PG[6] PCR[102]
AF0
AF1
AF2
AF3
GPIO[102]
E1UC[15]
LIN6TX
—
SIUL
eMIOS_1
LINFlex_6
—
I/O
I/O
O
—
M
Tristate
—
30
38
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
19
Peripheral
I/O
direction
Pad type2
RESET
config.3
Table 2. Functional port pins (continued)
100
LQFP
PG[7] PCR[103]
AF0
AF1
AF2
AF3
—
—
GPIO[103]
E1UC[16]
E1UC[30]
—
WKUP[20]4
LIN6RX
SIUL
eMIOS_1
eMIOS_1
—
WKUP
LINFlex_6
I/O
I/O
I/O
—
I
I
S
Tristate
—
29
37
PG[8] PCR[104]
AF0
AF1
AF2
AF3
—
GPIO[104]
E1UC[17]
LIN7TX
CS0_2
EIRQ[15]
SIUL
eMIOS_1
LINFlex_7
DSPI_2
SIUL
I/O
I/O
O
I/O
I
S
Tristate
—
26
34
PG[9] PCR[105]
AF0
AF1
AF2
AF3
—
—
GPIO[105]
E1UC[18]
—
SCK_2
WKUP[21]4
LIN7RX
SIUL
eMIOS_1
—
DSPI_2
WKUP
LINFlex_7
I/O
I/O
—
I/O
I
I
S
Tristate
—
25
33
PG[10] PCR[106]
AF0
AF1
AF2
AF3
—
GPIO[106]
E0UC[24]
E1UC[31]
—
SIN_4
SIUL
eMIOS_0
eMIOS_1
—
DSPI_4
I/O
I/O
I/O
—
I
S
Tristate
—
114
138
PG[11] PCR[107]
AF0
AF1
AF2
AF3
GPIO[107]
E0UC[25]
CS0_4
—
SIUL
eMIOS_0
DSPI_4
—
I/O
I/O
O
—
M
Tristate
—
115
139
PG[12] PCR[108]
AF0
AF1
AF2
AF3
GPIO[108]
E0UC[26]
SOUT_4
—
SIUL
eMIOS_0
DSPI_4
—
I/O
I/O
O
—
M
Tristate
—
92
116
PG[13] PCR[109]
AF0
AF1
AF2
AF3
GPIO[109]
E0UC[27]
SCK_4
—
SIUL
eMIOS_0
DSPI_4
—
I/O
I/O
I/O
—
M
Tristate
—
91
115
PG[14] PCR[110]
AF0
AF1
AF2
AF3
GPIO[110]
E1UC[0]
—
—
SIUL
eMIOS_1
—
—
I/O
I/O
—
—
S
Tristate
—
110
134
PG[15] PCR[111]
AF0
AF1
AF2
AF3
—
GPIO[111]
E1UC[1]
—
—
—
SIUL
eMIOS_1
—
—
—
I/O
I/O
—
—
—
M
Tristate
—
111
135
Port
pin
PCR
Alternate
register function1
Function
Pin number
144
LQFP
176
LQFP
Port H
MPC5606BK Microcontroller Data Sheet, Rev. 5
20
NXP Semiconductors
Peripheral
I/O
direction
Pad type2
RESET
config.3
Table 2. Functional port pins (continued)
100
LQFP
PH[0] PCR[112]
AF0
AF1
AF2
AF3
—
GPIO[112]
E1UC[2]
—
—
SIN_1
SIUL
eMIOS_1
—
—
DSPI_1
I/O
I/O
—
—
I
M
Tristate
—
93
117
PH[1] PCR[113]
AF0
AF1
AF2
AF3
GPIO[113]
E1UC[3]
SOUT_1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
O
—
M
Tristate
—
94
118
PH[2] PCR[114]
AF0
AF1
AF2
AF3
GPIO[114]
E1UC[4]
SCK_1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
I/O
—
M
Tristate
—
95
119
PH[3] PCR[115]
AF0
AF1
AF2
AF3
GPIO[115]
E1UC[5]
CS0_1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
I/O
—
M
Tristate
—
96
120
PH[4] PCR[116]
AF0
AF1
AF2
AF3
GPIO[116]
E1UC[6]
—
—
SIUL
eMIOS_1
—
—
I/O
I/O
—
—
M
Tristate
—
134
162
PH[5] PCR[117]
AF0
AF1
AF2
AF3
GPIO[117]
E1UC[7]
—
—
SIUL
eMIOS_1
—
—
I/O
I/O
—
—
S
Tristate
—
135
163
PH[6] PCR[118]
AF0
AF1
AF2
AF3
GPIO[118]
E1UC[8]
—
MA[2]
SIUL
eMIOS_1
—
ADC_0
I/O
I/O
—
O
M
Tristate
—
136
164
PH[7] PCR[119]
AF0
AF1
AF2
AF3
GPIO[119]
E1UC[9]
CS3_2
MA[1]
SIUL
eMIOS_1
DSPI_2
ADC_0
I/O
I/O
O
O
M
Tristate
—
137
165
PH[8] PCR[120]
AF0
AF1
AF2
AF3
GPIO[120]
E1UC[10]
CS2_2
MA[0]
SIUL
eMIOS_1
DSPI_2
ADC_0
I/O
I/O
O
O
M
Tristate
—
138
166
PH[9]8 PCR[121]
AF0
AF1
AF2
AF3
GPIO[121]
—
TCK
—
SIUL
—
JTAGC
—
I/O
—
I
—
S
Input,
weak
pull-up
88
127
155
PH[10]8 PCR[122]
AF0
AF1
AF2
AF3
GPIO[122]
—
TMS
—
SIUL
—
JTAGC
—
I/O
—
I
—
M
Input,
weak
pull-up
81
120
148
Port
pin
PCR
Alternate
register function1
Function
Pin number
144
LQFP
176
LQFP
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
21
Peripheral
I/O
direction
Pad type2
RESET
config.3
Table 2. Functional port pins (continued)
100
LQFP
PH[11] PCR[123]
AF0
AF1
AF2
AF3
GPIO[123]
SOUT_3
CS0_4
E1UC[5]
SIUL
DSPI_3
DSPI_4
eMIOS_1
I/O
O
I/O
I/O
M
Tristate
—
—
140
PH[12] PCR[124]
AF0
AF1
AF2
AF3
GPIO[124]
SCK_3
CS1_4
E1UC[25]
SIUL
DSPI_3
DSPI_4
eMIOS_1
I/O
I/O
I/O
—
M
Tristate
—
—
141
PH[13] PCR[125]
AF0
AF1
AF2
AF3
GPIO[125]
SOUT_4
CS0_3
E1UC[26]
SIUL
DSPI_4
DSPI_3
eMIOS_1
I/O
O
I/O
—
M
Tristate
—
—
9
PH[14] PCR[126]
AF0
AF1
AF2
AF3
GPIO[126]
SCK_4
CS1_3
E1UC[27]
SIUL
DSPI_4
DSPI_3
eMIOS_1
I/O
I/O
I/O
—
M
Tristate
—
—
10
PH[15] PCR[127]
AF0
AF1
AF2
AF3
GPIO[127]
SOUT_5
—
E1UC[17]
SIUL
DSPI_5
—
eMIOS_1
I/O
O
—
—
M
Tristate
—
—
8
Port
pin
PCR
Alternate
register function1
Function
Pin number
144
LQFP
176
LQFP
Port I
PI[0]
PCR[128]
AF0
AF1
AF2
AF3
GPIO[128]
E0UC[28]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
S
Tristate
—
—
172
PI[1]
PCR[129]
AF0
AF1
AF2
AF3
—
—
GPIO[129]
E0UC[29]
—
—
WKUP[24]4
—
SIUL
eMIOS_0
—
—
WKUP
—
I/O
I/O
—
—
I
—
S
Tristate
—
—
171
PI[2]
PCR[130]
AF0
AF1
AF2
AF3
GPIO[130]
E0UC[30]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
S
Tristate
—
—
170
PI[3]
PCR[131]
AF0
AF1
AF2
AF3
—
—
GPIO[131]
E0UC[31]
—
—
WKUP[23]4
—
SIUL
eMIOS_0
—
—
WKUP
—
I/O
I/O
—
—
I
—
S
Tristate
—
—
169
PI[4]
PCR[132]
AF0
AF1
AF2
AF3
GPIO[132]
E1UC[28]
SOUT_4
—
SIUL
eMIOS_1
DSPI_4
—
I/O
I/O
O
—
S
Tristate
—
—
143
MPC5606BK Microcontroller Data Sheet, Rev. 5
22
NXP Semiconductors
Peripheral
I/O
direction
Pad type2
RESET
config.3
Table 2. Functional port pins (continued)
100
LQFP
PI[5]
PCR[133]
AF0
AF1
AF2
AF3
GPIO[133]
E1UC[29]
SCK_4
—
SIUL
eMIOS_1
DSPI_4
—
I/O
I/O
I/O
—
S
Tristate
—
—
142
PI[6]
PCR[134]
AF0
AF1
AF2
AF3
GPIO[134]
E1UC[30]
CS0_4
—
SIUL
eMIOS_1
DSPI_4
—
I/O
I/O
I/O
—
S
Tristate
—
—
11
PI[7]
PCR[135]
AF0
AF1
AF2
AF3
GPIO[135]
E1UC[31]
CS1_4
—
SIUL
eMIOS_1
DSPI_4
—
I/O
I/O
I/O
—
S
Tristate
—
—
12
PI[8]
PCR[136]
AF0
AF1
AF2
AF3
—
GPIO[136]
—
—
—
ADC0_S[16]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
J
Tristate
—
—
108
PI[9]
PCR[137]
AF0
AF1
AF2
AF3
—
GPIO[137]
—
—
—
ADC0_S[17]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
J
Tristate
—
—
109
PI[10] PCR[138]
AF0
AF1
AF2
AF3
—
GPIO[138]
—
—
—
ADC0_S[18]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
J
Tristate
—
—
110
PI[11] PCR[139]
AF0
AF1
AF2
AF3
—
—
GPIO[139]
—
—
—
ADC0_S[19]
SIN_3
SIUL
—
—
—
ADC_0
DSPI_3
I/O
—
—
—
I
I
J
Tristate
—
—
111
PI[12] PCR[140]
AF0
AF1
AF2
AF3
—
GPIO[140]
CS0_3
—
—
ADC0_S[20]
SIUL
DSPI_3
—
—
ADC_0
I/O
I/O
—
—
I
J
Tristate
—
—
112
PI[13] PCR[141]
AF0
AF1
AF2
AF3
—
GPIO[141]
CS1_3
—
—
ADC0_S[21]
SIUL
DSPI_3
—
—
ADC_0
I/O
I/O
—
—
I
J
Tristate
—
—
113
Port
pin
PCR
Alternate
register function1
Function
Pin number
144
LQFP
176
LQFP
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
23
Peripheral
I/O
direction
Pad type2
RESET
config.3
Table 2. Functional port pins (continued)
100
LQFP
PI[14] PCR[142]
AF0
AF1
AF2
AF3
—
—
GPIO[142]
—
—
—
ADC0_S[22]
SIN_4
SIUL
—
—
—
ADC_0
DSPI_4
I/O
—
—
—
I
I
J
Tristate
—
—
76
PI[15] PCR[143]
AF0
AF1
AF2
AF3
—
GPIO[143]
CS0_4
—
—
ADC0_S[23]
SIUL
DSPI_4
—
—
ADC_0
I/O
I/O
—
—
I
J
Tristate
—
—
75
Port
pin
PCR
Alternate
register function1
Function
Pin number
144
LQFP
176
LQFP
Port J
PJ[0]
PCR[144]
AF0
AF1
AF2
AF3
—
GPIO[144]
CS1_4
—
—
ADC0_S[24]
SIUL
DSPI_4
—
—
ADC_0
I/O
I/O
—
—
I
J
Tristate
—
—
74
PJ[1]
PCR[145]
AF0
AF1
AF2
AF3
—
—
GPIO[145]
—
—
—
ADC0_S[25]
SIN_5
SIUL
—
—
——
ADC_0
DSPI_5
I/O
—
—
—
I
I
J
Tristate
—
—
73
PJ[2]
PCR[146]
AF0
AF1
AF2
AF3
—
GPIO[146]
CS0_5
—
—
ADC0_S[26]
SIUL
DSPI_5
—
—
ADC_0
I/O
I/O
—
—
I
J
Tristate
—
—
72
PJ[3]
PCR[147]
AF0
AF1
AF2
AF3
—
GPIO[147]
CS1_5
—
—
ADC0_S[27]
SIUL
DSPI_5
—
—
ADC_0
I/O
I/O
—
—
I
J
Tristate
—
—
71
PJ[4]
PCR[148]
AF0
AF1
AF2
AF3
GPIO[148]
SCK_5
E1UC[18]
—
SIUL
DSPI_5
eMIOS_1
—
I/O
I/O
—
—
M
Tristate
—
—
5
1
Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module.
PCR.PA = 00 → AF0; PCR.PA = 01 → AF1; PCR.PA = 10 → AF2; PCR.PA = 11 → AF3. This is intended to
select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless
of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function
is reported as “—”.
2 See Table 3.
3 The RESET configuration applies during and after reset.
MPC5606BK Microcontroller Data Sheet, Rev. 5
24
NXP Semiconductors
4
All WKUP pins also support external interrupt capability. See the WKPU chapter of the MPC5606BK
Microcontroller Reference Manual for further details.
5
NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.
6
“Not applicable” because these functions are available only while the device is booting. See the BAM chapter
of the MPC5606BK Microcontroller Reference Manual for details.
7 Value of PCR.IBE bit must be 0.
8
Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
It is up to the user to configure these pins as GPIO when needed.
9
PC[1] is a fast/medium pad but is in medium configuration by default. This pad is in Alternate Function 2 mode
after reset which has TDO functionality. The reset value of PCR.OBE is 1, but this setting has no impact as long
as this pad stays in AF2 mode. After configuring this pad as GPIO (PCR.PA = 0), output buffer is enabled as
reset value of PCR.OBE = 1.
10
Not available in 100LQFP package.
Table 3. Pad types
Type
3
Description
F
Fast
I
Input only with analog feature
J
Input/output with analog feature
M
Medium
S
Slow
Electrical characteristics
This section contains electrical characteristics of the device as well as temperature and power considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take
precautions to avoid application of any voltage higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by
the internal pull-up and pull-down, which is provided by the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on the system.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
3.1
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding, the classifications listed in Table 4 are used and the parameters are tagged accordingly in the tables where
appropriate.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
25
Table 4. Parameter classifications
Classification tag
Tag description
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.2
NVUSRO register
Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are
controlled via bit values in the Non-Volatile User Options Register (NVUSRO) register.
For a detailed description of the NVUSRO register, please refer to the MPC5606BK Microcontroller Reference Manual.
3.2.1
NVUSRO[PAD3V5V] field description
Table 5 shows how NVUSRO[PAD3V5V] controls the device configuration.
Table 5. PAD3V5V field description1
Value2
1
2
Description
0
High voltage supply is 5.0 V
1
High voltage supply is 3.3 V
See the MPC5606BK Microcontroller Reference Manual for more information on the NVUSRO register.
The default manufacturing value is ‘1’. This value can be programmed by the customer in Shadow Flash.
The DC electrical characteristics are dependent on the PAD3V5V bit value.
3.2.2
NVUSRO[OSCILLATOR_MARGIN] field description
Table 6 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
Table 6. OSCILLATOR_MARGIN field description1
Value2
1
2
Description
0
Low consumption configuration (4 MHz/8 MHz)
1
High margin configuration (4 MHz/16 MHz)
See the MPC5606BK Microcontroller Reference Manual for more information on the NVUSRO register.
The default manufacturing value is ‘1’. This value can be programmed by the customer in Shadow Flash.
The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value.
MPC5606BK Microcontroller Data Sheet, Rev. 5
26
NXP Semiconductors
3.2.3
NVUSRO[WATCHDOG_EN] field description
The watchdog enable/disable configuration after reset is dependent on the WATCHDOG_EN bit value.
Table 7 shows how NVUSRO[WATCHDOG_EN] controls the device configuration.
Table 7. WATCHDOG_EN field description1
Value2
1
2
3.3
Description
0
Disable after reset
1
Enable after reset
See the MPC5606BK Microcontroller Reference Manual for more information on the NVUSRO register.
The default manufacturing value is ‘1’. This value can be programmed by the customer in Shadow Flash.
Absolute maximum ratings
Table 8. Absolute maximum ratings
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
0
0
V
VDD
SR Voltage on VDD_HV pins with respect to
ground (VSS)
—
–0.3
6.0
V
VSS_LV
SR Voltage on VSS_LV (low voltage digital supply)
pins with respect to ground (VSS)
—
VDD_BV
SR Voltage on VDD_BV pin (regulator supply) with
respect to ground (VSS)
—
Relative to VDD
VSS_ADC SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1
(ADC reference) pin with respect to ground
(VSS)
—
VDD_ADC SR Voltage on VDD_HV_ADC0, VDD_HV_ADC1
(ADC reference) with respect to ground (VSS)
—
VIN
SR Voltage on any GPIO pin with respect to
ground (VSS)
Relative to VDD
—
Relative to VDD
VSS – 0.1 VSS + 0.1
–0.3
6.0
–0.3
VDD + 0.3
VSS – 0.1 VSS + 0.1
–0.3
6.0
–0.3
6.0
—
VDD + 0.3
SR Injected input current on any pin during
overload condition
—
–10
10
IINJSUM
SR Absolute sum of all injected input currents
during overload condition
—
–50
50
IAVGSEG
SR Sum of all the static I/O current within a supply VDD = 5.0 V ± 10%,
segment
PAD3V5V = 0
—
70
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
64
–55
150
—
V
V
V
VDD − 0.3 VDD + 0.3
IINJPAD
TSTORAGE SR Storage temperature
V
V
mA
mA
°C
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
27
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. During overload conditions (VIN > VDD or
VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the
recommended values.
3.4
Recommended operating conditions
Table 9. Recommended operating conditions (3.3 V)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
0
0
V
VDD1
SR Voltage on VDD_HV pins with respect
to ground (VSS)
—
3.0
3.6
V
VSS_LV2
SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground
(VSS)
—
VDD_BV3
SR Voltage on VDD_BV pin (regulator
supply) with respect to ground (VSS)
—
Relative to VDD
—
VSS_ADC
SR Voltage on VSS_HV_ADC0,
VSS_HV_ADC1 (ADC reference) pin
with respect to ground (VSS)
VDD_ADC4
—
SR Voltage on VDD_HV_ADC0,
VDD_HV_ADC1 (ADC reference) with
Relative to VDD
respect to ground (VSS)
VIN
SR Voltage on any GPIO pin with respect
to ground (VSS)
—
Relative to VDD
VSS − 0.1 VSS + 0.1
3.0
3.6
V
VDD − 0.1 VDD + 0.1
VSS − 0.1 VSS + 0.1
3.05
3.6
V
V
VDD − 0.1 VDD + 0.1
VSS − 0.1
—
—
VDD + 0.1
IINJPAD
SR Injected input current on any pin during
overload condition
—
−5
5
IINJSUM
SR Absolute sum of all injected input
currents during overload condition
—
−50
50
SR VDD slope to ensure correct power up6
—
3.07
TVDD
V
V
mA
0.25 V/µs V/s
MPC5606BK Microcontroller Data Sheet, Rev. 5
28
NXP Semiconductors
Table 9. Recommended operating conditions (3.3 V) (continued)
Value
Symbol
TA C-Grade
Parameter
SR Ambient temperature under bias
Conditions
Unit
fCPU < 64 MHz8
Min
Max
−40
85
−40
110
−40
105
−40
130
−40
125
−40
150
°C
Part
TJ C-Grade
SR Junction temperature under bias
—
Part
TA V-Grade
SR Ambient temperature under bias
fCPU < 64 MHz8
Part
TJ V-Grade
SR Junction temperature under bias
—
Part
TA M-Grade
SR Ambient temperature under bias
fCPU < 64 MHz8
Part
TJ M-Grade
SR Junction temperature under bias
—
Part
1
2
3
4
5
6
7
8
100 nF capacitance needs to be provided between each VDD/VSS pair.
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics). Supply ramp slope on VDD_BV should always be faster or equal
to slope of VDD_HV. Otherwise, device may enter regulator bypass mode if slope on VDD_BV is slower.
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/O DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, the
device is reset.
Guaranteed by device validation
Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH).
This frequency includes the 4% frequency modulation guard band.
Table 10. Recommended operating conditions (5.0 V)
Value
Symbol
Parameter
Conditions
VSS
SR Digital ground on VSS_HV pins
—
VDD1
SR Voltage on VDD_HV pins with respect to ground
(VSS)
—
2
Voltage drop
Unit
Min
Max
0
0
V
4.5
5.5
V
3.0
5.5
VSS_LV3
SR Voltage on VSS_LV (low voltage digital supply) pins
with respect to ground (VSS)
—
VSS − 0.1
VSS + 0.1
V
VDD_BV4
SR Voltage on VDD_BV pin (regulator supply) with
respect to ground (VSS)
—
4.5
5.5
V
3.0
5.5
3.0
VDD + 0.1
Voltage
drop2
Relative to VDD
VSS_ADC
SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC
reference) pin with respect to ground (VSS)
—
VSS − 0.1 VSS + 0.1
V
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
29
Table 10. Recommended operating conditions (5.0 V) (continued)
Value
Symbol
Parameter
Conditions
VDD_ADC5 SR Voltage on VDD_HV_ADC0, VDD_HV_ADC1
(ADC reference) with respect to ground (VSS)
—
2
Voltage drop
Relative to VDD
VIN
SR Voltage on any GPIO pin with respect to ground
(VSS)
—
Relative to VDD
Unit
Min
Max
4.5
5.5
3.0
5.5
V
VDD − 0.1 VDD + 0.1
VSS − 0.1
—
—
VDD + 0.1
V
IINJPAD
SR Injected input current on any pin during overload
condition
—
−5
5
IINJSUM
SR Absolute sum of all injected input currents during
overload condition
—
−50
50
SR VDD slope to ensure correct power up6
—
3.07
0.25 V/µs
V/s
fCPU < 64 MHz8
−40
85
°C
—
−40
110
fCPU < 64 MHz8
−40
105
—
−40
130
fCPU < 64 MHz8
−40
125
—
−40
150
TVDD
TA C-Grade SR Ambient temperature under bias
mA
Part
TJ C-Grade SR Junction temperature under bias
Part
TA V-Grade SR Ambient temperature under bias
Part
TJ V-Grade SR Junction temperature under bias
Part
TA M-Grade SR Ambient temperature under bias
Part
TJ M-Grade SR Junction temperature under bias
Part
1
2
3
4
5
6
7
8
100 nF capacitance needs to be provided between each VDD/VSS pair.
Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain
analog electrical characteristics will not be guaranteed to stay within the stated limits.
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics). While the supply voltage ramps up, the slope on VDD_BV should
be less than 0.9VDD_HV in order to ensure the device does not enter regulator bypass mode.
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
Guaranteed by device validation. Please refer to Section 3.5.1, External ballast resistor recommendations for
minimum VDD slope to be guaranteed to ensure correct power up in case of external resistor usage.
Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH).
This frequency includes the 4% frequency modulation guard band.
NOTE
RAM data retention is guaranteed with VDD_LV not below 1.08 V.
MPC5606BK Microcontroller Data Sheet, Rev. 5
30
NXP Semiconductors
3.5
Thermal characteristics
3.5.1
External ballast resistor recommendations
External ballast resistor on VDD_BV pin helps in reducing the overall power dissipation inside the device. This resistor is
required only when maximum power consumption exceeds the limit imposed by package thermal characteristics.
As stated in Table 11 LQFP thermal characteristics, considering a thermal resistance of 144 LQFP as 48.3 °C/W, at ambient
temperature TA = 125 °C, the junction temperature Tj will cross 150 °C if the total power dissipation is greater than
(150 – 125)/48.3 = 517 mW. Therefore, the total device current IDDMAX at 125 °C/5.5 V must not exceed 94.1 mA (i.e.,
PD/VDD). Assuming an average IDD(VDD_HV) of 15–20 mA consumption typically during device RUN mode, the LV domain
consumption IDD(VDD_BV) is thus limited to IDDMAX – IDD(VDD_HV), i.e., 80 mA.
Therefore, respecting the maximum power allowed as explained in Section 3.5.2, Package thermal characteristics, it is
recommended to use this resistor only in the 125 °C/5.5 V operating corner as per the following guidelines:
•
•
•
If IDD(VDD_BV) < 80 mA, then no resistor is required.
If 80 mA < IDD(VDD_BV) < 90 mA, then 4 Ω resistor can be used.
If IDD(VDD_BV) > 90 mA, then 8 Ω resistor can be used.
Using resistance in the range of 4–8 Ω, the gain will be around 10–20% of total consumption on VDD_BV. For example, if 8 Ω
resistor is used, then power consumption when IDD(VDD_BV) is 110 mA is equivalent to power consumption when
IDD(VDD_BV) is 90 mA (approximately) when resistor not used.
In order to ensure correct power up, the minimum VDD_BV to be guaranteed is 30 ms/V. If the supply ramp is slower than this
value, then LVDHV3B monitoring ballast supply VDD_BV pin gets triggered leading to device reset. Until the supply reaches
certain threshold, this low voltage monitor generates destructive reset event in the system. This threshold depends on the
maximum IDD(VDD_BV) possible across the external resistor.
3.5.2
Package thermal characteristics
Table 11. LQFP thermal characteristics1
Symbol
C
Parameter
Conditions2
Value
Pin count
Unit
Min Typ Max
RθJA CC D Thermal resistance,
junction-to-ambient natural
convection3
Single-layer board — 1s
Four-layer board — 2s2p
RθJB CC
Thermal resistance,
junction-to-board4
Single-layer board — 1s
Four-layer board — 2s2p
100
—
—
64
144
—
—
64
176
—
—
64
100
—
—
49.7
144
—
—
48.3
176
—
—
47.3
100
—
—
36
144
—
—
38
176
—
—
38
100
—
—
33.6
144
—
—
33.4
176
—
—
33.4
°C/W
°C/W
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
31
Table 11. LQFP thermal characteristics1 (continued)
Symbol
C
Conditions2
Parameter
Value
Pin count
Unit
Min Typ Max
RθJC CC
Thermal resistance,
junction-to-case5
Single-layer board — 1s
Four-layer board — 2s2p
100
—
—
23
144
—
—
23
176
—
—
23
100
—
—
19.8
144
—
—
19.2
176
—
—
18.8
°C/W
1
Thermal characteristics are targets based on simulation.
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C.
3 Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA
and RthJMA.
4 Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package. When Greek letters are not available, the symbols are typed as RthJB.
5 Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface
layer. When Greek letters are not available, the symbols are typed as RthJC.
2
3.5.3
Power considerations
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1:
TJ = TA + (PD x RθJA)
Eqn. 1
Where:
TA is the ambient temperature in °C.
RθJA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PI/O (PD = PINT + PI/O).
PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power.
PI/O represents the power dissipation on input and output pins; user determined.
Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be significant, if the device
is configured to continuously drive external modules and/or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
PD = K / (TJ + 273 °C)
Eqn. 2
K = PD x (TA + 273 °C) + RθJA x PD2
Eqn. 3
Therefore, solving equations 1 and 2:
Where:
MPC5606BK Microcontroller Data Sheet, Rev. 5
32
NXP Semiconductors
K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations 1 and 2
iteratively for any value of TA.
3.6
3.6.1
I/O pad electrical characteristics
I/O pad types
The device provides four main I/O pad types depending on the associated alternate functions:
•
•
•
•
Slow pads — are the most common pads, providing a good compromise between transition time and low
electromagnetic emission.
Medium pads — provide transition fast enough for the serial communication channels with controlled current to
reduce electromagnetic emission.
Fast pads — provide maximum speed. These are used for improved debugging capability.
Input only pads — are associated with ADC channels and 32 kHz low power external crystal oscillator providing low
input leakage.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.
3.6.2
I/O input DC characteristics
Table 12 provides input DC electrical characteristics as described in Figure 5.
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1
(GPDI register of SIUL)
PDIx = ‘0’
Figure 5. I/O input DC electrical characteristics definition
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
33
Table 12. I/O input DC electrical characteristics
Symbol
C
Value
Conditions1
Parameter
Unit
Min
Typ
Max
VIH
SR P Input high level CMOS (Schmitt
Trigger)
—
0.65VDD
—
VDD + 0.4
VIL
SR P Input low level CMOS (Schmitt
Trigger)
—
−0.4
—
0.35VDD
—
0.1VDD
—
—
TA = −40 °C
—
2
—
TA = 25 °C
—
2
—
D
TA = 85 °C
—
5
300
D
TA = 105 °C
—
12
500
P
TA = 125 °C
—
70
1000
VHYS CC C Input hysteresis CMOS (Schmitt
Trigger)
ILKG CC P Digital input leakage
No injection
on adjacent
pin
P
WFI
2
WNFI
1
2
V
nA
SR P Wakeup input filtered pulse
—
—
—
40
ns
SR P Wakeup input not filtered pulse
—
1000
—
—
ns
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and
voltage.
2
3.6.3
I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
•
•
•
•
Table 13 provides weak pull figures. Both pull-up and pull-down resistances are supported.
Table 14 provides output driver characteristics for I/O pads when in SLOW configuration.
Table 15 provides output driver characteristics for I/O pads when in MEDIUM configuration.
Table 16 provides output driver characteristics for I/O pads when in FAST configuration.
Table 13. I/O pull-up/pull-down DC electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min
|IWPU| CC P Weak pull-up current
absolute value
C
P
|IWPD| CC P Weak pull-down current
absolute value
C
P
1
2
VIN = VIL, VDD = 5.0 V ± 10% PAD3V5V = 0
Typ Max
10
—
150
10
—
250
VIN = VIL, VDD = 3.3 V ± 10% PAD3V5V = 1
10
—
150
VIN = VIH, VDD = 5.0 V ± 10% PAD3V5V = 0
10
—
150
PAD3V5V = 1
10
—
250
VIN = VIH, VDD = 3.3 V ± 10% PAD3V5V = 1
10
—
150
PAD3V5V = 12
µA
µA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET are configured in input or in high impedance state.
MPC5606BK Microcontroller Data Sheet, Rev. 5
34
NXP Semiconductors
Table 14. SLOW configuration output buffer electrical characteristics
Symbol
VOH
VOL
1
2
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
Push Pull IOH = −2 mA,
VDD = 5.0 V ± 10%,
PAD3V5V = 0
(recommended)
0.8VDD
—
—
C
IOH = −2 mA,
VDD = 5.0 V ± 10%,
PAD3V5V = 12
0.8VDD
—
—
C
IOH = −1 mA,
VDD = 3.3 V ± 10%,
PAD3V5V = 1
(recommended)
VDD − 0.8
—
—
Push Pull IOL = 2 mA,
VDD = 5.0 V ± 10%,
PAD3V5V = 0
(recommended)
—
—
0.1VDD
C
IOL = 2 mA,
VDD = 5.0 V ± 10%,
PAD3V5V = 12
—
—
0.1VDD
C
IOL = 1 mA,
VDD = 3.3 V ± 10%,
PAD3V5V = 1
(recommended)
—
—
0.5
CC P Output high level
SLOW configuration
CC P Output low level
SLOW configuration
V
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET are configured in input or in high impedance state.
Table 15. MEDIUM configuration output buffer electrical characteristics
Symbol C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
Push Pull IOH = −3.8 mA,
VOH CC C Output high level
MEDIUM configuration
VDD = 5.0 V ± 10%, PAD3V5V = 0
0.8VDD
—
—
P
IOH = −2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
0.8VDD
—
—
C
IOH = −1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
0.8VDD
—
—
C
IOH = −1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
VDD − 0.8 —
—
C
IOH = −100 µA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
0.8VDD
—
V
—
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
35
Table 15. MEDIUM configuration output buffer electrical characteristics (continued)
Symbol C
Parameter
Value
Conditions1
Unit
Min
VOL CC C Output low level
Push Pull IOL = 3.8 mA,
MEDIUM configuration
VDD = 5.0 V ± 10%, PAD3V5V = 0
1
2
Typ
Max
—
— 0.2VDD
P
IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
— 0.1VDD
C
IOL = 1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
—
— 0.1VDD
C
IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
C
IOL = 100 µA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
— 0.1VDD
V
0.5
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET are configured in input or in high impedance state.
Table 16. FAST configuration output buffer electrical characteristics
Symbol
Parameter
Value
Conditions1
Unit
Min
Typ
Max
VOH CC P Output high level Push Pull IOH = −14 mA,
FAST configuration
VDD = 5.0 V ± 10%,
PAD3V5V = 0
(recommended)
0.8VDD
—
—
C
IOH = −7 mA,
VDD = 5.0 V ± 10%,
PAD3V5V = 12
0.8VDD
—
—
C
IOH = −11 mA,
VDD = 3.3 V ± 10%,
PAD3V5V = 1
(recommended)
VDD − 0.8
—
—
—
—
0.1VDD
VOL
1
C
CC P Output low level
Push Pull IOL = 14 mA,
FAST configuration
VDD = 5.0 V ± 10%,
PAD3V5V = 0
(recommended)
C
IOL = 7 mA,
VDD = 5.0 V ± 10%,
PAD3V5V = 12
—
—
0.1VDD
C
IOL = 11 mA,
VDD = 3.3 V ± 10%,
PAD3V5V = 1
(recommended)
—
—
0.5
V
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
MPC5606BK Microcontroller Data Sheet, Rev. 5
36
NXP Semiconductors
2
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET are configured in input or in high impedance state.
3.6.4
Output pin transition times
Table 17. Output pin transition times
Symbol
C
Value
Conditions1
Parameter
Unit
Min Typ Max
Ttr
CC D Output transition time output pin2 CL = 25 pF
SLOW configuration
T
CL = 50 pF
D
CL = 100 pF
D
CL = 25 pF
T
CL = 50 pF
Ttr
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF
D
Ttr
VDD = 5.0 V ± 10%,
PAD3V5V = 0
CC D Output transition time output
MEDIUM configuration
T
pin2
CL = 25 pF
CL = 50 pF
D
CL = 100 pF
D
CL = 25 pF
T
CL = 50 pF
D
CL = 100 pF
CC D Output transition time output pin2 CL = 25 pF
FAST configuration
CL = 50 pF
VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
VDD = 5.0 V ± 10%,
PAD3V5V = 0
CL = 100 pF
CL = 25 pF
CL = 50 pF
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF
1
2
3.6.5
—
—
50
—
—
100
—
—
125
—
—
50
—
—
100
—
—
125
—
—
10
—
—
20
—
—
40
—
—
12
—
—
25
—
—
40
—
—
4
—
—
6
—
—
12
—
—
4
—
—
7
—
—
12
ns
ns
ns
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
CL includes device and package capacitances (CPKG < 5 pF).
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as
described in Table 18.
Table 19 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG
maximum value.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
37
Table 18. I/O supply segments
Supply segment
Package
1
2
3
4
5
6
7
8
176 LQFP
pin7 –
pin27
pin28 –
pin57
pin59 –
pin85
pin86 –
pin123
pin124 –
pin150
pin151 –
pin6
—
—
144 LQFP
pin20 –
pin49
pin51 –
pin99
pin100 –
pin122
pin 123 –
pin19
—
—
—
—
100 LQFP
pin16 –
pin35
pin37 –
pin69
pin70 –
pin83
pin84 –
pin15
—
—
—
—
Table 19. I/O consumption
Symbol
C
Value
Conditions1
Parameter
Unit
Min Typ Max
ISWTSLW,2 CC D Dynamic I/O current for
SLOW configuration
ISWTMED2 CC D Dynamic I/O current for
MEDIUM configuration
ISWTFST2 CC D Dynamic I/O current for
FAST configuration
IRMSSLW CC D Root medium square I/O
current for SLOW
configuration
CL = 25 pF
CL = 25 pF
CL = 25 pF
CL = 25 pF, 2 MHz
CL = 25 pF, 4 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
20
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
16
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
29
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
17
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
110 mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
50
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
2.3
—
—
3.2
—
—
6.6
—
—
1.6
—
—
2.3
—
—
4.7
—
—
6.6
—
— 13.4
—
— 18.3
—
—
5
—
—
8.5
—
—
11
CL = 100 pF, 2 MHz
CL = 25 pF, 2 MHz
CL = 25 pF, 4 MHz
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF, 2 MHz
IRMSMED CC D Root medium square I/O
current for MEDIUM
configuration
CL = 25 pF, 13 MHz
CL = 25 pF, 40 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
CL = 100 pF, 13 MHz
CL = 25 pF, 13 MHz
CL = 25 pF, 40 MHz
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF, 13 MHz
mA
mA
mA
mA
MPC5606BK Microcontroller Data Sheet, Rev. 5
38
NXP Semiconductors
Table 19. I/O consumption (continued)
Symbol
C
Value
Conditions1
Parameter
Unit
Min Typ Max
IRMSFST
CC D Root medium square I/O
current for FAST
configuration
CL = 25 pF, 40 MHz
—
—
22
—
—
33
—
—
56
—
—
14
—
—
20
CL = 100 pF, 40 MHz
—
—
35
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
70
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
65
CL = 25 pF, 64 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
CL = 100 pF, 40 MHz
CL = 25 pF, 40 MHz
CL = 25 pF, 64 MHz
SR D Sum of all the static I/O
current within a supply
segment
IAVGSEG
1
2
VDD = 3.3 V ± 10%,
PAD3V5V = 1
mA
mA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to125 °C, unless otherwise specified
Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
Table 20 provides the weight of concurrent switching I/Os.
In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain
below the 100%.
Table 20. I/O weight1
176 LQFP
144/100 LQFP
Supply segment
Pad
4
—
4
—
Weight 3.3 V
Weight 5 V
Weight 3.3 V
SRC2 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
176 LQFP 144 LQFP 100 LQFP
6
Weight 5 V
PB[3]
5%
—
6%
—
13%
—
15%
—
PC[9]
4%
—
5%
—
13%
—
15%
—
PC[14]
4%
—
4%
—
13%
—
15%
—
PC[15]
3%
4%
4%
4%
12%
18%
15%
16%
PJ[4]
3%
4%
3%
3%
—
—
—
—
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
39
Table 20. I/O weight1 (continued)
176 LQFP
144/100 LQFP
Supply segment
Pad
Weight 3.3 V
Weight 5 V
Weight 3.3 V
SRC2 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
176 LQFP 144 LQFP 100 LQFP
1
Weight 5 V
—
—
PH[15]
2%
3%
3%
3%
—
—
—
—
—
—
PH[13]
3%
4%
3%
4%
—
—
—
—
—
—
PH[14]
3%
4%
4%
4%
—
—
—
—
—
—
PI[6]
4%
—
4%
—
—
—
—
—
—
—
PI[7]
4%
—
4%
—
—
—
—
—
4
—
PG[5]
4%
—
5%
—
10%
—
12%
—
—
PG[4]
4%
6%
5%
5%
9%
13%
11%
12%
—
PG[3]
4%
—
5%
—
9%
—
11%
—
—
PG[2]
4%
6%
5%
5%
9%
12%
10%
11%
4
PA[2]
4%
—
5%
—
8%
—
10%
—
PE[0]
4%
—
5%
—
8%
—
9%
—
PA[1]
4%
—
5%
—
8%
—
9%
—
PE[1]
4%
6%
5%
6%
7%
10%
9%
9%
PE[8]
4%
6%
5%
6%
7%
10%
8%
9%
PE[9]
4%
—
5%
—
6%
—
8%
—
PE[10]
4%
—
5%
—
6%
—
7%
—
PA[0]
4%
6%
5%
5%
6%
8%
7%
7%
PE[11]
4%
—
5%
—
5%
—
6%
—
MPC5606BK Microcontroller Data Sheet, Rev. 5
40
NXP Semiconductors
Table 20. I/O weight1 (continued)
176 LQFP
144/100 LQFP
Supply segment
Pad
1
Weight 3.3 V
Weight 5 V
Weight 3.3 V
SRC2 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
176 LQFP 144 LQFP 100 LQFP
2
Weight 5 V
—
PG[9]
9%
—
10%
—
9%
—
10%
—
—
PG[8]
9%
—
11%
—
9%
—
11%
—
1
PC[11]
9%
—
11%
—
9%
—
11%
—
PC[10]
9%
13%
11%
12%
9%
13%
11%
12%
—
PG[7]
9%
—
11%
—
9%
—
11%
—
—
PG[6]
10%
14%
11%
12%
10%
14%
11%
12%
1
PB[0]
10%
14%
12%
12%
10%
14%
12%
12%
PB[1]
10%
—
12%
—
10%
—
12%
—
—
PF[9]
10%
—
12%
—
10%
—
12%
—
—
PF[8]
10%
14%
12%
13%
10%
14%
12%
13%
—
PF[12]
10%
15%
12%
13%
10%
15%
12%
13%
1
PC[6]
10%
—
12%
—
10%
—
12%
—
PC[7]
10%
—
12%
—
10%
—
12%
—
—
PF[10]
10%
14%
11%
12%
10%
14%
11%
12%
—
PF[11]
9%
—
11%
—
9%
—
11%
—
1
PA[15]
8%
12%
10%
10%
8%
12%
10%
10%
—
PF[13]
8%
—
10%
—
8%
—
10%
—
1
PA[14]
8%
11%
9%
10%
8%
11%
9%
10%
PA[4]
7%
—
9%
—
7%
—
9%
—
PA[13]
7%
10%
8%
9%
7%
10%
8%
9%
PA[12]
7%
—
8%
—
7%
—
8%
—
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
41
Table 20. I/O weight1 (continued)
176 LQFP
144/100 LQFP
Supply segment
Pad
2
2
Weight 3.3 V
Weight 5 V
Weight 3.3 V
SRC2 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
176 LQFP 144 LQFP 100 LQFP
3
Weight 5 V
PB[9]
1%
—
1%
—
1%
—
1%
—
PB[8]
1%
—
1%
—
1%
—
1%
—
PB[10]
5%
—
6%
—
6%
—
7%
—
—
PF[0]
5%
—
6%
—
6%
—
8%
—
—
PF[1]
5%
—
6%
—
7%
—
8%
—
—
PF[2]
6%
—
7%
—
7%
—
9%
—
—
PF[3]
6%
—
7%
—
8%
—
9%
—
—
PF[4]
6%
—
7%
—
8%
—
10%
—
—
PF[5]
6%
—
7%
—
9%
—
10%
—
—
PF[6]
6%
—
7%
—
9%
—
11%
—
—
PF[7]
6%
—
7%
—
9%
—
11%
—
—
—
PJ[3]
6%
—
7%
—
—
—
—
—
—
—
PJ[2]
6%
—
7%
—
—
—
—
—
—
—
PJ[1]
6%
—
7%
—
—
—
—
—
—
—
PJ[0]
6%
—
7%
—
—
—
—
—
—
—
PI[15]
6%
—
7%
—
—
—
—
—
—
—
PI[14]
6%
—
7%
—
—
—
—
—
2
2
PD[0]
1%
—
1%
—
1%
—
1%
—
PD[1]
1%
—
1%
—
1%
—
1%
—
PD[2]
1%
—
1%
—
1%
—
1%
—
PD[3]
1%
—
1%
—
1%
—
1%
—
PD[4]
1%
—
1%
—
1%
—
1%
—
PD[5]
1%
—
1%
—
1%
—
1%
—
PD[6]
1%
—
1%
—
1%
—
2%
—
PD[7]
1%
—
1%
—
1%
—
2%
—
MPC5606BK Microcontroller Data Sheet, Rev. 5
42
NXP Semiconductors
Table 20. I/O weight1 (continued)
176 LQFP
144/100 LQFP
Supply segment
Pad
4
2
2
Weight 3.3 V
Weight 5 V
Weight 3.3 V
SRC2 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
176 LQFP 144 LQFP 100 LQFP
4
Weight 5 V
PD[8]
1%
—
1%
—
1%
—
2%
—
PB[4]
1%
—
1%
—
1%
—
2%
—
PB[5]
1%
—
1%
—
1%
—
2%
—
PB[6]
1%
—
1%
—
1%
—
2%
—
PB[7]
1%
—
1%
—
1%
—
2%
—
PD[9]
1%
—
1%
—
1%
—
2%
—
PD[10]
1%
—
1%
—
1%
—
2%
—
PD[11]
1%
—
1%
—
1%
—
2%
—
—
—
PB[11]
1%
—
1%
—
—
—
—
—
—
—
PD[12]
11%
—
13%
—
—
—
—
—
2
2
PB[12]
11%
—
13%
—
15%
—
17%
—
PD[13]
11%
—
13%
—
14%
—
17%
—
PB[13]
11%
—
13%
—
14%
—
17%
—
PD[14]
11%
—
13%
—
14%
—
17%
—
PB[14]
11%
—
13%
—
14%
—
16%
—
PD[15]
11%
—
13%
—
13%
—
16%
—
PB[15]
11%
—
13%
—
13%
—
15%
—
—
—
PI[8]
10%
—
12%
—
—
—
—
—
—
—
PI[9]
10%
—
12%
—
—
—
—
—
—
—
PI[10]
10%
—
12%
—
—
—
—
—
—
—
PI[11]
10%
—
12%
—
—
—
—
—
—
—
PI[12]
10%
—
12%
—
—
—
—
—
—
—
PI[13]
10%
—
11%
—
—
—
—
—
2
2
PA[3]
9%
—
11%
—
11%
—
13%
—
—
PG[13]
9%
13%
11%
11%
10%
14%
12%
13%
—
PG[12]
9%
13%
10%
11%
10%
14%
12%
12%
—
PH[0]
6%
8%
7%
7%
6%
9%
7%
8%
—
PH[1]
6%
8%
7%
7%
6%
8%
7%
7%
—
PH[2]
5%
7%
6%
6%
5%
7%
6%
7%
—
PH[3]
5%
7%
5%
6%
5%
7%
6%
6%
—
PG[1]
4%
—
5%
—
4%
—
5%
—
—
PG[0]
4%
5%
4%
5%
4%
5%
4%
5%
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
43
Table 20. I/O weight1 (continued)
176 LQFP
144/100 LQFP
Supply segment
Pad
3
Weight 3.3 V
Weight 5 V
Weight 3.3 V
SRC2 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
176 LQFP 144 LQFP 100 LQFP
5
Weight 5 V
—
PF[15]
4%
—
4%
—
4%
—
4%
—
—
PF[14]
4%
6%
5%
5%
4%
6%
5%
5%
—
PE[13]
4%
—
5%
—
4%
—
5%
—
3
PA[7]
5%
—
6%
—
5%
—
6%
—
PA[8]
5%
—
6%
—
5%
—
6%
—
PA[9]
6%
—
7%
—
6%
—
7%
—
PA[10]
6%
—
8%
—
6%
—
8%
—
PA[11]
8%
—
9%
—
8%
—
9%
—
PE[12]
8%
—
9%
—
8%
—
9%
—
—
PG[14]
8%
—
9%
—
8%
—
9%
—
—
PG[15]
8%
11%
9%
10%
8%
11%
9%
10%
—
PE[14]
8%
—
9%
—
8%
—
9%
—
—
PE[15]
8%
11%
9%
10%
8%
11%
9%
10%
—
PG[10]
8%
—
9%
—
8%
—
9%
—
—
PG[11]
7%
11%
9%
9%
7%
11%
9%
9%
—
—
PH[11]
7%
10%
9%
9%
—
—
—
—
—
—
PH[12]
7%
10%
8%
9%
—
—
—
—
—
—
PI[5]
7%
—
8%
—
—
—
—
—
—
—
PI[4]
7%
—
8%
—
—
—
—
—
3
3
PC[3]
6%
—
8%
—
6%
—
8%
—
PC[2]
6%
8%
7%
7%
6%
8%
7%
7%
PA[5]
6%
8%
7%
7%
6%
8%
7%
7%
PA[6]
5%
—
6%
—
5%
—
6%
—
PH[10]
5%
7%
6%
6%
5%
7%
6%
6%
PC[1]
5%
19%
5%
13%
5%
19%
5%
13%
MPC5606BK Microcontroller Data Sheet, Rev. 5
44
NXP Semiconductors
Table 20. I/O weight1 (continued)
176 LQFP
144/100 LQFP
Supply segment
Pad
1
2
4
4
Weight 3.3 V
Weight 5 V
Weight 3.3 V
SRC2 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
176 LQFP 144 LQFP 100 LQFP
6
Weight 5 V
PC[0]
6%
9%
7%
8%
7%
10%
8%
8%
PH[9]
7%
—
8%
—
7%
—
9%
—
PE[2]
7%
10%
8%
9%
8%
11%
9%
10%
PE[3]
7%
10%
9%
9%
8%
12%
10%
10%
PC[5]
7%
11%
9%
9%
8%
12%
10%
11%
PC[4]
8%
11%
9%
10%
9%
13%
10%
11%
PE[4]
8%
11%
9%
10%
9%
13%
11%
12%
PE[5]
8%
11%
10%
10%
9%
14%
11%
12%
—
PH[4]
8%
12%
10%
10%
10%
14%
12%
12%
—
PH[5]
8%
—
10%
—
10%
—
12%
—
—
PH[6]
8%
12%
10%
11%
10%
15%
12%
13%
—
PH[7]
9%
12%
10%
11%
11%
15%
13%
13%
—
PH[8]
9%
12%
10%
11%
11%
16%
13%
14%
4
PE[6]
9%
12%
10%
11%
11%
16%
13%
14%
PE[7]
9%
12%
10%
11%
11%
16%
14%
14%
—
—
PI[3]
9%
—
10%
—
—
—
—
—
—
—
PI[2]
9%
—
10%
—
—
—
—
—
—
—
PI[1]
9%
—
10%
—
—
—
—
—
—
—
PI[0]
9%
—
10%
—
—
—
—
—
4
4
PC[12]
8%
12%
10%
11%
12%
18%
15%
16%
PC[13]
8%
—
10%
—
13%
—
15%
—
PC[8]
8%
—
10%
—
13%
—
15%
—
PB[2]
8%
11%
9%
10%
13%
18%
15%
16%
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
SRC is the Slew Rate Control bit in SIU_PCRx
3.7
RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
45
VDD
VDDMIN
RESET
VIH
VIL
device reset forced by RESET
device start-up phase
Figure 6. Start-up reset requirements
VRESET
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
WFRST
filtered by
lowpass filter
unknown reset
state
device under hardware reset
WFRST
WNFRST
Figure 7. Noise filtering on reset signal
Table 21. Reset electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min
VIH
SR P Input High Level CMOS
(Schmitt Trigger)
—
Typ
Max
0.65VDD — VDD + 0.4
V
MPC5606BK Microcontroller Data Sheet, Rev. 5
46
NXP Semiconductors
Table 21. Reset electrical characteristics (continued)
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
VIL
SR P Input low Level CMOS
(Schmitt Trigger)
—
−0.4
—
0.35VDD
V
VHYS
CC C Input hysteresis CMOS
(Schmitt Trigger)
—
0.1VDD
—
—
V
Push Pull, IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
V
Push Pull, IOL = 1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
—
—
0.1VDD
Push Pull, IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
CL = 25 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
10
CL = 50 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
20
CL = 100 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
40
CL = 25 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
12
CL = 50 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
25
CL = 100 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
40
WFRST SR P RESET input filtered pulse
—
—
—
40
ns
WNFRST SR P RESET input not filtered pulse
—
1000
—
—
ns
10
—
150
µA
10
—
150
10
—
250
VOL
Ttr
|IWPU|
CC P Output low level
CC D Output transition time output
pin3 MEDIUM configuration
CC P Weak pull-up current absolute VDD = 3.3 V ± 10%, PAD3V5V = 1
value
VDD = 5.0 V ± 10%, PAD3V5V = 0
VDD = 5.0 V ± 10%, PAD3V5V = 14
ns
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to the MC_RGM chapter of
the MPC5606BK Microcontroller Reference Manual).
3 C includes device and package capacitance (C
L
PKG < 5 pF).
4 The configuration PAD3V5 = 1 when V
DD = 5 V is only transient configuration during power-up. All pads but RESET
are configured in input or in high impedance state.
2
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
47
3.8
Power management electrical characteristics
3.8.1
Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage
ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD. The following supplies are involved:
•
•
•
HV: High voltage external power supply for voltage regulator module. This must be provided externally through VDD
power pin.
BV: High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV
power pin. Voltage values should be aligned with VDD.
LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated by the internal
voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure
noise isolation between critical LV modules within the device:
— LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding.
— LV_CFLA: Low voltage supply for code Flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_DFLA: Low voltage supply for data Flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.
CREG2 (LV_COR/LV_CFLA)
GND
VDD
VSS_LV
VDD_BV
Voltage Regulator
I
VSS_LVn
VDD_BV
CREG1 (LV_COR/LV_DFLA)
VDD_LVn
CDEC1 (Ballast decoupling)
VREF
VDD_LV
VDD_LV
DEVICE
VSS_LV
GND
VSS_LV
DEVICE
GND
VDD_LV
VSS
VDD
GND
CREG3 (LV_COR/LV_PLL)
CDEC2 (supply/IO decoupling)
Figure 8. Voltage regulator capacitance connection
The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable
low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins.
Care should also be taken to limit the serial inductance of the board to less than 5 nH.
MPC5606BK Microcontroller Data Sheet, Rev. 5
48
NXP Semiconductors
Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see
Section 3.4, Recommended operating conditions).
The internal voltage regulator requires controlled slew rate of VDD/VDD_BV as described in Figure 9.
VDD_HV
VDD_HV(MAX)
VDD_HV(MIN)
POWER UP
FUNCTIONAL RANGE
POWER DOWN
Figure 9. VDD and VDD_BV maximum slope
When STANDBY mode is used, further constraints apply to the VDD/VDD_BV in order to guarantee correct regulator
functionality during STANDBY exit. This is described in Figure 10.
STANDBY regulator constraints should normally be guaranteed by implementing equivalent of CSTDBY capacitance on
application board (capacitance and ESR typical values), but would actually depend on the exact characteristics of the
application’s external regulator.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
49
VDD_HV
VDD_HV
VDD_HV(MAX)
d
VDD ( STDBY )
dt
ΔVDD(STDBY)
ΔVDD(STDBY)
VDD_HV(MIN)
d VDD ( STDBY )
dt
VDD_LV
VDD_LV(NOMINAL)
0V
Figure 10. VDD and VDD_BV supply constraints during STANDBY mode exit
Table 22. Voltage regulator electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
CREGn
SR — Internal voltage regulator external
capacitance
—
200
—
500
nF
RREG
SR — Stability capacitor equivalent serial
resistance
—
—
—
0.2
Ω
CDEC1
SR — Decoupling capacitance2 ballast
VDD_BV/VSS_LV pair:
VDD_BV = 4.5 V to
5.5 V
1003
4704
—
nF
VDD_BV/VSS_LV pair:
VDD_BV = 3 V to 3.6 V
400
—
CDEC2
SR — Decoupling capacitance regulator
supply
VDD/VSS pair
10
100
—
nF
VMREG
CC P Main regulator output voltage
Before exiting from
reset
—
1.32
—
V
1.15
1.28
1.32
—
—
150
After trimming
IMREG
SR — Main regulator current provided to
VDD_LV domain
—
mA
MPC5606BK Microcontroller Data Sheet, Rev. 5
50
NXP Semiconductors
Table 22. Voltage regulator electrical characteristics (continued)
Symbol
IMREGINT
C
Parameter
—
2
IMREG = 0 mA
—
—
1
VLPREG
CC P Low power regulator output voltage
After trimming
1.15
1.23
1.32
V
ILPREG
SR — Low power regulator current provided
to VDD_LV domain
—
—
15
mA
—
—
600
µA
ILPREG = 0 mA;
TA = 55 °C
—
5
—
After trimming
1.15
1.23
1.32
V
—
—
5
mA
IULPREG = 5 mA;
TA = 55 °C
—
—
100
µA
IULPREG = 0 mA;
TA = 55 °C
—
2
—
CC P Ultra low power regulator output
voltage
IULPREG
SR — Ultra low power regulator current
provided to VDD_LV domain
IULPREGINT
CC D Ultra low power regulator module
current consumption
Δ VDD ( STDBY ) )
d VDD ( STDBY )
dt
5
6
—
CC D Low power regulator module current ILPREG = 15 mA;
consumption
TA = 55 °C
VULPREG
d
VDD
dt
4
Max
—
IDD_BV
3
Typ
IMREG = 200 mA
—
2
Unit
Min
CC D Main regulator module current
consumption
ILPREGINT
1
Value
Conditions1
—
mA
CC D Inrush average current on VDD_BV
during power-up5
—
—
—
3006
mA
SR — Maximum slope on VDD
—
—
—
250
mV/µs
SR — Maximum instant variation on VDD
during STANDBY exit
—
—
—
30
mV
SR — Maximum slope on VDD during
STANDBY exit
—
—
—
15
mV/µs
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical
value is in the range of 470 nF.
This value is acceptable to guarantee operation from 4.5 V to 5.5 V
External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV in operating
range.
Inrush current is seen only for short time during power-up and on standby exit (max 20 µs, depending on external capacitances
to be load).
The duration of the inrush current depends on the capacitance placed on LV pins. BV decoupling capacitors must be sized
accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.
3.8.2
Voltage monitor electrical characteristics
The device implements a Power-on Reset module to ensure correct power-up initialization, as well as four low voltage detectors
to monitor the VDD and the VDD_LV voltage while device is supplied:
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
51
•
•
•
•
•
•
POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state
LVDHV3 monitors VDD to ensure device reset below minimum functional supply
LVDHV3B monitors VDD_BV to ensure device reset below minimum functional supply
LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range
LVDLVCOR monitors power domain No. 1
LVDLVBKP monitors power domain No. 0
NOTE
When enabled, power domain No. 2 is monitored through LVDLVBKP.
VDD
VLVDHVxH
VLVDHVxL
RESET
Figure 11. Low voltage monitor vs. reset
Table 23. Low voltage monitor electrical characteristics
Symbol
Parameter
VPORUP
SR D Supply for functional POR module
VPORH
CC P Power-on reset threshold
Value
Conditions1
TA = 25 °C,
after trimming
Unit
Min
Typ
Max
1.0
—
5.5
1.5
—
2.6
VLVDHV3H
CC T LVDHV3 low voltage detector high threshold
—
—
2.95
VLVDHV3L
CC P LVDHV3 low voltage detector low threshold
2.6
—
2.9
VLVDHV3BH
CC T LVDHV3B low voltage detector high threshold
—
—
2.95
VLVDHV3BL
CC P LVDHV3BL low voltage detector low threshold
2.6
—
2.9
VLVDHV5H
CC T LVDHV5 low voltage detector high threshold
—
—
4.5
VLVDHV5L
CC P LVDHV5 low voltage detector low threshold
3.8
—
4.4
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold
1.08
—
—
CC P LVDLVBKP low voltage detector low threshold
1.08
—
1.14
VLVDLVBKPL
1
C
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
MPC5606BK Microcontroller Data Sheet, Rev. 5
52
NXP Semiconductors
3.9
Power consumption in different application modes
Table 24 provides DC electrical characteristics for significant application modes. These values are indicative values; actual
consumption depends on the application.
Table 24. Electrical characteristics in different application modes1
Symbol
C
Parameter
Typ
Max
—
81
1304 mA
fCPU = 8 MHz
—
12
—
fCPU = 16 MHz
—
27
—
C
fCPU = 32 MHz
—
40
—
P
fCPU = 48 MHz
—
54
95
fCPU = 64 MHz
—
67
120
TA = 25 °C
—
10
15
TA = 125 °C
—
15
28
TA = 25 °C
—
130
500
TA = 55 °C
—
180
—
D
TA = 85 °C
—
1
5
D
TA = 105 °C
—
3
9
TA = 125 °C
—
5
14
TA = 25 °C
—
17
80
TA = 55 °C
—
30
—
C
TA = 85 °C
—
110
—
C
TA = 105 °C
—
280
950
TA = 125 °C
—
460
1700
TA = 25 °C
—
12
50
TA = 55 °C
—
24
—
C
TA = 85 °C
—
48
—
C
TA = 105 °C
—
150
500
C
TA = 125 °C
—
260
—
CC T RUN mode typical average
current6
T
P
IDDHALT
CC C HALT mode
current7
P
IDDSTOP
Unit
Min
IDDMAX3 CC C RUN mode maximum average
current
IDDRUN5
Value
Conditions2
CC P STOP mode current8
D
—
Slow internal RC
oscillator (128 kHz)
running
Slow internal RC
oscillator (128 kHz)
running
P
IDDSTDBY2 CC P STANDBY2 mode
current9
C
Slow internal RC
oscillator (128 kHz)
running
C
IDDSTDBY1 CC C STANDBY1 mode
C
current10
Slow internal RC
oscillator (128 kHz)
running
mA
mA
µA
mA
µA
µA
1
Except for IDDMAX, all consumptions in this table apply to VDD_BV only and do not include VDD_HV.
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
3
Running consumption is given on voltage regulator supply (VDDREG). IDDMAX is composed of three components:
IDDMAX = IDD(VDD_BV) + IDD(VDD_HV) + IDD(VDD_HV_ADC). It does not include a fourth component linked to I/Os
toggling which is highly dependent on the application. The given value is thought to be a worst case value
(64 MHz at 125 °C) with all peripherals running, and code fetched from code flash while modify operation on-going
on data flash. Note that this value can be significantly reduced by the application: switch off unused peripherals
(default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low
power mode when possible.
2
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
53
4
Higher current may be sunk by device during power-up and standby exit. Please refer to inrush current in Table 22.
RUN current measured with typical application with accesses on both Flash and RAM.
6
Only for the “P” classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and
LIN in loop back mode, DSPI as Master, PLL as system clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and
running at max frequency, periodic SW/WDG timer reset enabled.
7 Data Flash Power Down. Code Flash in Low Power. SIRC 128 kHz and FIRC 16 MHz on. 10 MHz XTAL clock.
FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clocks gated. LINFlex:
instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 to 9 clocks gated. eMIOS: instance:
0 ON (16 channels on PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI:
instance: 0 (clocked but no communication), instance: 1 to 5 clocks gated. RTC/API ON. PIT ON. STM ON. ADC1
OFF. ADC0 ON but no conversion except two analog watchdogs.
8
Only for the “P” classification: No clock, FIRC 16 MHz off, SIRC 128 kHz on, PLL off, HPvreg off,
ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode.
9
Only for the “P” classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum
consumption, all possible modules switched off.
10
ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules
switched off.
5
3.10
Flash memory electrical characteristics
3.10.1
Program/erase characteristics
Table 25 shows the program and erase characteristics.
Table 25. Program and erase specifications
Value
Symbol
Tdwprogram
C
Parameter
CC C Double word (64 bits) program time4
Conditions
Min Typ1
Code Flash
—
Data Flash
T16Kpperase
16 KB block preprogram and erase time
Code Flash
32 KB block preprogram and erase time
Code Flash
Max3
50
500
µs
500
5000
ms
600
5000
ms
22
—
Data Flash
T32Kpperase
18
Unit
Initial
max2
200
300
—
Data Flash
300
400
T32Kpperase
32 KB block preprogram and erase time for
sector B0F4
Code Flash
—
600
1200
10000
ms
T128Kpperase
128 KB block preprogram and erase time
Code Flash
—
600
1300
7500
ms
1200 2600
15000
ms
Data Flash
T128Kpperase
128 KB block preprogram and erase time for
sector B0F5
Teslat
D Erase Suspend Latency
TESRT
C Erase Suspend Request Rate
800
Code Flash
—
—
—
—
30
30
µs
Code Flash
20
—
—
—
ms
Data Flash
10
—
—
—
MPC5606BK Microcontroller Data Sheet, Rev. 5
54
NXP Semiconductors
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3
The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4 Actual hardware programming times. This does not include software overhead.
Table 26. Flash module life
Value
Symbol
C
Parameter
Conditions
Unit
Typ
Max
P/E
CC C Number of program/erase
cycles per block for 16 KB
blocks over the operating
temperature range (TJ)
—
100000
—
—
cycles
P/E
CC C Number of program/erase
cycles per block for 32 KB
blocks over the operating
temperature range (TJ)
—
10000
100000
—
cycles
P/E
CC C Number of program/erase
cycles per block for 128 KB
blocks over the operating
temperature range (TJ)
—
1000
100000
—
cycles
20
—
—
years
10
—
—
years
5
—
—
years
Retention
CC C Minimum data retention at 85 Blocks with
°C average ambient
0–1,000 P/E cycles
temperature1
Blocks with
1,001–10,000 P/E
cycles
Blocks with
10,001–100,000 P/E
cycles
1
Min
Ambient temperature averaged over duration of application, not to exceed recommended product operating
temperature range.
ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units
will experience single bit corrections throughout the life of the product with no impact to product reliability.
Table 27. Flash read access timing
Symbol
fREAD
1
C
Parameter
Conditions1
Max
Unit
2 wait states
64
MHz
C
1 wait state
40
C
0 wait states
20
CC P Maximum frequency for Flash reading
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
3.10.2
Flash power supply DC characteristics
Table 28 shows the power supply DC characteristics on external supply.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
55
Table 28. Flash power supply DC electrical characteristics
Symbol
Value
Conditions1
Parameter
Unit
Min Typ Max
ICFREAD CC Sum of the current consumption on
VDDHV and VDDBV on read access
IDFREAD
Flash module read
fCPU = 64 MHz2
ICFMOD CC Sum of the current consumption on
VDDHV and VDDBV on matrix
IDFMOD
modification (program/erase)
1
2
Code Flash
—
—
33
Data Flash
—
—
33
Program
Code Flash
/Erase on-going while
Data Flash
reading Flash registers
2
fCPU = 64 MHz
—
—
52
—
—
33
Code Flash
—
—
1.1
mA
Data Flash
—
—
900
µA
Code Flash
—
—
150
µA
Data Flash
—
—
150
ICFLPW CC Sum of the current consumption on
VDDHV and VDDBV during Flash low
IDFLPW
power mode
—
ICFPWD CC Sum of the current consumption on
VDDHV and VDDBV during Flash power
IDFPWD
down mode
—
mA
mA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified.
fCPU 64 MHz can be achieved at up to 125 °C.
3.10.3
Start-up/Switch-off timings
Table 29. Start-up time/Switch-off time
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ Max
TFLARSTEXIT
CC T Delay for Flash module to exit reset mode
—
—
—
125
TFLALPEXIT
CC T Delay for Flash module to exit low-power mode
—
—
—
0.5
TFLAPDEXIT
CC T Delay for Flash module to exit power-down
mode
—
—
—
30
TFLALPENTRY
CC T Delay for Flash module to enter low-power
mode
—
—
—
0.5
TFLAPDENTRY
CC T Delay for Flash module to enter power-down
mode
—
—
—
1.5
1
µs
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
3.11
Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
3.11.1
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified
MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in
particular.
MPC5606BK Microcontroller Data Sheet, Rev. 5
56
NXP Semiconductors
Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC
level requested for the application.
Software recommendations − The software flowchart must include the management of runaway conditions such as:
— Corrupted program counter
— Unexpected reset
— Critical data corruption (control registers...)
Prequalification trials − Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the
software can be hardened to prevent unrecoverable errors occurring.
•
•
3.11.2
Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC61967-1
standard, which specifies the general conditions for EMI measurements.
Table 30. EMI radiated emission measurement1,2
Value
Symbol
C
Parameter
Conditions
Unit
Min
—
fCPU
1
2
Max
SR — Scan range
—
0.150
SR — Operating frequency
—
—
64
—
MHz
—
—
1.28
—
V
No PLL frequency
modulation
—
—
18
dBµV
± 2% PLL frequency
modulation
—
—
14
dBµV
VDD_LV SR — LV operating voltages
SEMI
Typ
CC T Peak level
VDD = 5 V, TA = 25 °C,
LQFP144 package
Test conforming to IEC
61967-2,
fOSC = 8 MHz/fCPU =
64 MHz
1000 MHz
EMI testing and I/O port waveforms per IEC 61967-1, -2, -4
For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your
local marketing representative.
3.11.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine
its performance in terms of electrical sensitivity.
3.11.3.1
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according
to each pin combination. The sample size depends on the number of supply pins in the device (3 parts×(n + 1) supply pin). This
test conforms to the AEC-Q100-002/-003/-011 standard.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
57
Table 31. ESD absolute maximum ratings1,2
Conditions
Class
Max value3
Unit
VESD(HBM) Electrostatic discharge voltage
(Human Body Model)
TA = 25 °C
conforming to AEC-Q100-002
H1C
2000
V
VESD(MM) Electrostatic discharge voltage
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
VESD(CDM) Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
C3A
500
Symbol
Ratings
750 (corners)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
3
Data based on characterization results, not tested in production
3.11.3.2
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 32. Latch-up results
Symbol
LU
3.12
Parameter
Static latch-up class
Conditions
TA = 125 °C
conforming to JESD 78
Class
II level A
Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics
The device provides an oscillator/resonator driver. Figure 12 describes a simple model of the internal oscillator driver and
provides an example of a connection for an oscillator or a resonator.
Table 33 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations.
MPC5606BK Microcontroller Data Sheet, Rev. 5
58
NXP Semiconductors
EXTAL
C1
Crystal
EXTAL
XTAL
C2
DEVICE
VDD
I
R
EXTAL
XTAL
Resonator
DEVICE
XTAL
DEVICE
Figure 12. Crystal oscillator and resonator connection scheme
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
Table 33. Crystal description
Crystal
motional
capacitance
(Cm) fF
Crystal
motional
inductance
(Lm) mH
Load on
xtalin/xtalout
C1 = C2
(pF)1
Shunt
capacitance
between
xtalout
and xtalin
C02 (pF)
Nominal
frequency
(MHz)
NDK crystal
reference
Crystal
equivalent
series
resistance
ESR Ω
4
NX8045GB
300
2.68
591.0
21
2.93
8
NX5032GA
300
2.46
160.7
17
3.01
10
150
2.93
86.6
15
2.91
12
120
3.11
56.5
15
2.93
16
120
3.90
25.3
10
3.00
1
The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing
includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
2 The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads,
package, etc.).
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
59
S_MTRANS bit (ME_GS register)
1
0
VXTAL
1/fMXOSC
VMXOSC
90%
VMXOSCOP
10%
TMXOSCSU
valid internal clock
Figure 13. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Table 34. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
fFXOSC
SR — Fast external crystal
oscillator frequency
—
4.0
—
16.0
MHz
gmFXOSC
CC C Fast external crystal
oscillator
transconductance
VDD = 3.3 V ± 10%,
PAD3V5V = 1
OSCILLATOR_MARGIN = 0
2.2
—
8.2
mA/V
CC P
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 0
2.0
—
7.4
CC C
VDD = 3.3 V ± 10%,
PAD3V5V = 1
OSCILLATOR_MARGIN = 1
2.7
—
9.7
CC C
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 1
2.5
—
9.2
CC T Oscillation amplitude at
EXTAL
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
1.3
—
—
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1
1.3
—
—
—
—
0.95
—
—
2
VFXOSC
VFXOSCOP CC P Oscillation operating point
IFXOSC2
CC T Fast external crystal
oscillator consumption
V
V
3
mA
MPC5606BK Microcontroller Data Sheet, Rev. 5
60
NXP Semiconductors
Table 34. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued)
Symbol
TFXOSCSU
1
2
3.13
C
CC T Fast external crystal
oscillator start-up time
Value
Conditions1
Parameter
Unit
Min
Typ
Max
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
—
—
6
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1
—
—
1.8
ms
VIH
SR P Input high level CMOS
(Schmitt Trigger)
Oscillator bypass mode
0.65VDD
—
VDD + 0.4
V
VIL
SR P Input low level CMOS
(Schmitt Trigger)
Oscillator bypass mode
−0.4
—
0.35VDD
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
Stated values take into account only analog module consumption but not the digital contributor (clock tree and
enabled peripherals).
Slow external crystal oscillator (32 kHz) electrical characteristics
The device provides a low power oscillator/resonator driver.
OSC32K_EXTAL
OSC32K_EXTAL
Resonator
Crystal
C1
RP
OSC32K_XTAL
DEVICE
OSC32K_XTAL
C2
DEVICE
Figure 14. Crystal oscillator and resonator connection scheme
NOTE
OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
61
l
C0
C1
Crystal
Cm
C2
Rm
Lm
C1
C2
Figure 15. Equivalent circuit of a quartz crystal
Table 35. Crystal motional characteristics1
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
Lm
Motional inductance
—
—
11.796
—
KH
Cm
Motional capacitance
—
—
2
—
fF
—
18
—
28
pF
kΩ
C1/C2 Load capacitance at OSC32K_XTAL and
OSC32K_EXTAL with respect to ground2
Rm3
Motional resistance
AC coupled at C0 = 2.85 pF4
—
—
65
AC coupled at C0 = 4.9
pF4
—
—
50
AC coupled at C0 = 7.0
pF4
—
—
35
AC coupled at C0 = 9.0 pF4
—
—
30
1
The crystal used is Epson Toyocom MC306.
This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to
ground. It includes all the parasitics due to board traces, crystal and package.
3 Maximum ESR (R ) of the crystal is 50 kΩ
m
4
C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins.
2
MPC5606BK Microcontroller Data Sheet, Rev. 5
62
NXP Semiconductors
OSCON bit (OSC_CTL register)
1
0
VOSC32K_XTAL
1/fLPXOSC32K
VLPXOSC32K
90%
10%
TLPXOSC32KSU
valid internal clock
Figure 16. Slow external crystal oscillator (32 kHz) electrical characteristics
Table 36. Slow external crystal oscillator (32 kHz) electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
fSXOSC
SR — Slow external crystal oscillator
frequency
—
32
32.768
40
kHz
VSXOSC
CC T Oscillation amplitude
—
—
2.1
—
V
ISXOSCBIAS CC T Oscillation bias current
—
2.5
µA
ISXOSC
CC T Slow external crystal oscillator
consumption
—
—
—
8
µA
TSXOSCSU
CC T Slow external crystal oscillator
start-up time
—
—
—
22
s
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal.
2
3.14
FMPLL electrical characteristics
The device provides a frequency modulated phase locked loop (FMPLL) module to generate a fast system clock from the
FXOSC or FIRC sources.
Table 37. FMPLL electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
fPLLIN
SR — FMPLL reference clock2
—
4
—
64
MHz
ΔPLLIN
SR — FMPLL reference clock duty
cycle2
—
40
—
60
%
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
63
Table 37. FMPLL electrical characteristics (continued)
Symbol
C
fPLLOUT CC P FMPLL output clock frequency
fVCO3
Value
Conditions1
Parameter
CC P VCO frequency without
frequency modulation
P VCO frequency with frequency
modulation
Unit
Min
Typ
Max
—
16
—
64
MHz
—
256
—
512
MHz
—
245.76
—
532.48
fCPU
SR — System clock frequency
—
—
—
644
MHz
fFREE
CC P Free-running frequency
—
20
—
150
MHz
tLOCK
CC P FMPLL lock time
40
100
µs
ΔtSTJIT CC — FMPLL short term
Stable oscillator (fPLLIN = 16 MHz)
jitter5
ΔtLTJIT CC — FMPLL long term jitter
IPLL
CC C FMPLL consumption
fsys maximum
–4
—
4
%
fPLLCLK at 64 MHz, 4000 cycles
—
—
10
ns
TA = 25 °C
—
—
4
mA
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in
functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN.
3 Frequency modulation is considered ± 4%.
4 f
CPU 64 MHz can be achieved only at up to 105 °C.
5 Short term jitter is measured on the clock rising edge at cycle n and n + 4.
2
3.15
Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a 16 MHz main internal RC oscillator. This is used as the default clock at the power-up of the device.
Table 38. Fast internal RC oscillator (16 MHz) electrical characteristics
Symbol
Parameter
2,
IFIRCPWD
Value
Conditions1
CC P Fast internal RC oscillator high TA = 25 °C, trimmed
frequency
SR —
—
fFIRC
IFIRCRUN
C
Unit
Min
Typ
Max
—
16
—
12
MHz
20
CC T Fast internal RC oscillator high TA = 25 °C, trimmed
frequency current in running
mode
—
—
200
µA
CC D Fast internal RC oscillator high TA = 25 °C
frequency current in power
down mode
—
—
10
µA
sysclk = off
—
500
—
µA
sysclk = 2 MHz
—
600
—
sysclk = 4 MHz
—
700
—
sysclk = 8 MHz
—
900
—
sysclk = 16 MHz
—
1250
—
IFIRCSTOP CC T Fast internal RC oscillator high TA = 25 °C
frequency and system clock
current in stop mode
MPC5606BK Microcontroller Data Sheet, Rev. 5
64
NXP Semiconductors
Table 38. Fast internal RC oscillator (16 MHz) electrical characteristics (continued)
Symbol
C
Value
Conditions1
Parameter
Unit
Min
Typ
Max
TFIRCSU
CC C Fast internal RC oscillator
start-up time
VDD = 5.0 V ± 10%
—
1.1
2.0
µs
ΔFIRCPRE
CC C Fast internal RC oscillator
precision after software
trimming of fFIRC
TA = 25 °C
−1
—
1
%
ΔFIRCTRIM CC C Fast internal RC oscillator
trimming step
TA = 25 °C
—
1.6
−5
—
ΔFIRCVAR
1
CC C Fast internal RC oscillator
variation over temperature and
supply with respect to fFIRC at
TA = 25 °C in high-frequency
configuration
—
%
5
%
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
2
3.16
Slow internal RC oscillator (128 kHz) electrical characteristics
The device provides a 128 kHz low power internal RC oscillator. This can be used as the reference clock for the RTC module.
Table 39. Slow internal RC oscillator (128 kHz) electrical characteristics
Symbol
1
Parameter
Value
Conditions1
Unit
Min
Typ
Max
—
128
—
100
—
150
—
—
5
µA
CC P Slow internal RC oscillator low
frequency
SR —
TA = 25 °C, trimmed
ISIRC2,
CC C Slow internal RC oscillator low
frequency current
TA = 25 °C, trimmed
TSIRCSU
CC P Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V ± 10%
time
—
8
12
µs
ΔSIRCPRE
CC C Slow internal RC oscillator precision TA = 25 °C
after software trimming of fSIRC
−2
—
2
%
ΔSIRCTRIM
CC C Slow internal RC oscillator trimming
step
—
2.7
—
ΔSIRCVAR
CC C Slow internal RC oscillator variation High frequency configuration
in temperature and supply with
respect to fSIRC at TA = 55 °C in high
frequency configuration
−10
—
10
fSIRC
2
C
—
—
kHz
%
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
65
3.17
3.17.1
ADC electrical characteristics
Introduction
The device provides two Successive Approximation Register (SAR) analog-to-digital converters (10-bit and 12-bit).
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = VDD_ADC / 1024
1018
(2)
code out
7
(1)
6
(1) Example of an actual transfer curve
5
(2) The ideal transfer curve
(5)
(3) Differential non-linearity error (DNL)
4
(4) Integral non-linearity error (INL)
(4)
(5) Center of a step of the actual transfer curve
3
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset Error OSE
Figure 17. ADC_0 characteristic and error definitions
3.17.2
Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
MPC5606BK Microcontroller Data Sheet, Rev. 5
66
NXP Semiconductors
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources
charge during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 kΩ is obtained (REQ
= 1 / (fc × CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage
partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit
must be designed to respect the Equation 4:
Eqn. 4
R S + R F + R L + R SW + R AD 1
V A • -------------------------------------------------------------------------- < --- LSB
R EQ
2
Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW
and RAD) can be neglected with respect to external resistances.
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
VA
Filter
RF
Current Limiter
RL
CF
Channel
Selection
Sampling
RSW1
RAD
CP1
CP2
CS
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL
Current Limiter Resistance
RSW1 Channel Selection Switch Impedance
RAD Sampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
Figure 18. Input equivalent circuit (precise channels)
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
67
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
Filter
RF
Current Limiter
RL
CF
VA
RS
RF
CF
RL
RSW
RAD
CP
CS
CP1
Channel
Selection
Extended
Switch
Sampling
RSW1
RSW2
RAD
CP3
CP2
CS
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance (two contributions RSW1 and RSW2)
Sampling Switch Impedance
Pin Capacitance (three contributions, CP1, CP2 and CP3)
Sampling Capacitance
Figure 19. Input equivalent circuit (extended channels)
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are
initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 18): A charge sharing phenomenon
is installed when the sampling phase is started (A/D switch close).
Voltage Transient on CS
VCS
VA
VA2
ΔV < 0.5 LSB
1
2
τ1 < (RSW + RAD) CS 2048 • C S
ADC_1 (12-bit)
Eqn. 13
C F > 8192 • C S
MPC5606BK Microcontroller Data Sheet, Rev. 5
70
NXP Semiconductors
3.17.3
ADC electrical characteristics
Table 40. ADC input leakage current
Value
Symbol C
Parameter
Conditions
Unit
Min
Typ
Max
—
1
—
—
1
—
3
100
ILKG CC C Input leakage current TA = −40 °C No current injection on adjacent pin
C
TA = 25 °C
D
TA = 85°C
C
TA = 105 °C
—
8
200
P
TA = 125 °C
—
45
400
nA
Table 41. ADC_0 conversion characteristics (10-bit ADC_0)
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
VSS_ADC0 SR — Voltage on VSS_HV_ADC0
(ADC_0 reference) pin with
respect to ground (VSS)2
—
−0.1
—
0.1
V
VDD_ADC0 SR — Voltage on VDD_HV_ADC pin
(ADC reference) with respect
to ground (VSS)
—
VDD − 0.1
—
VDD + 0.1
V
—
VSS_ADC0
− 0.1
—
VDD_ADC0
+ 0.1
V
IADC0pwd SR — ADC_0 consumption in power
down mode
—
—
—
50
µA
IADC0run SR — ADC_0 consumption in
running mode
—
—
—
5
mA
—
6
—
14
45
—
55
%
—
—
—
1.5
µs
fADC = 32 MHz,
ADC0_conf_sample_input = 17
0.5
—
fADC = 6 MHz,
INPSAMP = 255
—
—
42
0.625
—
—
µs
VAINx
fADC0
SR — Analog input voltage3
SR — ADC_0 analog frequency
ΔADC0_SYS SR — ADC_0 digital clock duty cycle ADCLKSEL =
(ipg_clk)
tADC0_PU SR — ADC_0 power up delay
tADC0_S CC T Sample
time5
tADC0_C CC P Conversion time6
fADC = 32 MHz,
ADC_conf_comp = 2
32 + 4% MHz
µs
CS
CC D ADC_0 input sampling
capacitance
—
—
—
3
pF
CP1
CC D ADC_0 input pin capacitance 1
—
—
—
3
pF
CP2
CC D ADC_0 input pin capacitance 2
—
—
—
1
pF
CP3
CC D ADC_0 input pin capacitance 3
—
—
—
1
pF
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
71
Table 41. ADC_0 conversion characteristics (10-bit ADC_0) (continued)
Symbol
3
4
5
6
7
Value
Conditions1
Unit
Min
Typ
Max
CC D Internal resistance of analog
source
—
—
—
3
kΩ
RSW2
CC D Internal resistance of analog
source
—
—
—
2
kΩ
RAD
CC D Internal resistance of analog
source
—
—
—
2
kΩ
IINJ
SR — Input current Injection
VDD =
3.3 V ± 10%
−5
—
5
mA
VDD =
5.0 V ± 10%
−5
—
5
Current injection
on one ADC_0
input, different
from the
converted one
| INL |
CC T Absolute value for integral
nonlinearity
No overload
—
0.5
1.5
LSB
| DNL |
CC T Absolute differential
nonlinearity
No overload
—
0.5
1.0
LSB
| OFS |
CC T Absolute offset error
—
—
0.5
—
LSB
| GNE |
CC T Absolute gain error
—
—
0.6
—
LSB
LSB
TUEX
2
Parameter
RSW1
TUEP
1
C
error7
CC P Total unadjusted
for
precise channels, input only
T
pins
Without current injection
−2
0.6
2
With current injection
−3
—
3
CC T Total unadjusted error7 for
extended channel
T
Without current injection
−3
1
3
With current injection
−4
LSB
4
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
Analog and digital VSS must be common (to be tied together externally).
VAINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured
by internal divider by 2.
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC0_S. After the
end of the sample time tADC0_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC0_S depend on programming.
This parameter does not include the sample time tADC0_S, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
MPC5606BK Microcontroller Data Sheet, Rev. 5
72
NXP Semiconductors
Offset Error OSE
Gain Error GE
4095
4094
4093
4092
4091
1 LSB ideal = AVDD / 4096
4090
(2)
code out
7
(1)
6
(1) Example of an actual transfer curve
5
(5)
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
4
(4) Integral non-linearity error (INL)
(4)
(5) Center of a step of the actual transfer curve
3
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal)
Offset Error OSE
Figure 22. ADC_1 characteristic and error definitions
Table 42. ADC_1 conversion characteristics (12-bit ADC_1)
Symbol
C
Parameter
Value
Conditions1
VSS_ADC1 SR — Voltage on VSS_HV_ADC1
(ADC_1 reference) pin with
respect to ground (VSS)2
—
VDD_ADC1 SR — Voltage on VDD_HV_ADC1 pin
(ADC_1 reference) with
respect to ground (VSS)
—
Unit
Min
Typ
Max
–0.1
—
0.1
V
VDD + 0.1
V
VDD – 0.1 —
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
73
Table 42. ADC_1 conversion characteristics (12-bit ADC_1) (continued)
Symbol
C
Parameter
Value
Conditions1
Unit
Min
VAINx
SR — Analog input voltage3
—
Typ
VSS_ADC1 —
– 0.1
Max
VDD_ADC1
+ 0.1
V
IADC1pwd SR — ADC_1 consumption in power
down mode
—
—
—
50
µA
IADC1run
—
—
—
6
mA
VDD = 3.3 V
3.33
—
20 + 4%
MHz
VDD = 5 V
3.33
—
32 + 4%
—
—
—
1.5
µs
ns
fADC1
SR — ADC_1 consumption in running
mode
SR — ADC_1 analog frequency
tADC1_PU SR — ADC_1 power up delay
tADC1_S
tADC1_C
time4
fADC1 = 20 MHz,
ADC1_conf_sample_input = 12
600
—
—
Sample time4
VDD = 5.0 V
fADC1= 32 MHz,
ADC1_conf_sample_input = 17
500
—
—
Sample time4
VDD = 3.3 V
fADC1= 3.33 MHz,
ADC1_conf_sample_input = 255
—
—
76.2
Sample time4
VDD = 5.0 V
fADC1= 3.33 MHz,
ADC1_conf_sample_input = 255
—
—
76.2
CC P Conversion time5
VDD = 3.3 V
fADC1 = 20MHz,
ADC1_conf_comp = 0
2.4
—
—
µs
Conversion time5
VDD = 5.0 V
fADC 1 = 32 MHz,
ADC1_conf_comp = 0
1.5
—
—
µs
Conversion time5
VDD = 3.3 V
fADC 1 = 13.33 MHz,
ADC1_conf_comp = 0
—
—
3.6
µs
Conversion time5
VDD = 5.0 V
fADC1 = 13.33 MHz,
ADC1_conf_comp = 0
—
—
3.6
µs
45
—
55
%
CC T Sample
VDD = 3.3 V
ΔADC1_SYS SR — ADC_1 digital clock duty cycle ADCLKSEL = 16
µs
CS
CC D ADC_1 input sampling
capacitance
—
—
—
5
pF
CP1
CC D ADC_1 input pin capacitance 1
—
—
—
3
pF
CP2
CC D ADC_1 input pin capacitance 2
—
—
—
1
pF
CP3
CC D ADC_1 input pin capacitance 3
—
—
—
1.5
pF
RSW1
CC D Internal resistance of analog
source
—
—
—
1
kΩ
RSW2
CC D Internal resistance of analog
source
—
—
—
2
kΩ
RAD
CC D Internal resistance of analog
source
—
—
—
0.3
kΩ
MPC5606BK Microcontroller Data Sheet, Rev. 5
74
NXP Semiconductors
Table 42. ADC_1 conversion characteristics (12-bit ADC_1) (continued)
Symbol
IINJ
3
4
5
6
7
SR — Input current Injection
Value
Conditions1
Current
VDD = 3.3 V ± 10%
injection on
VDD = 5.0 V ± 10%
one ADC_1
input, different
from the
converted one
Unit
Min
Typ
Max
–5
—
5
–5
—
5
mA
CC T Absolute Integral
No overload
non-linearity-Precise channels
—
1
3
LSB
INLX
CC T Absolute Integral
non-linearity-Extended
channels
No overload
—
1.5
5
LSB
DNL
CC T Absolute Differential
non-linearity
No overload
—
0.5
1
LSB
OFS
CC T Absolute Offset error
—
—
2
—
LSB
GNE
CC T Absolute Gain error
—
—
2
—
LSB
LSB
TUEX7
2
Parameter
INLP
TUEP7
1
C
CC P Total Unadjusted Error for
precise channels, input only
T
pins
Without current injection
–6
—
6
With current injection
–8
—
8
CC T Total Unadjusted Error for
extended channel
T
Without current injection
–10
—
10
With current injection
–12
—
12
LSB
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified
Analog and digital VSS must be common (to be tied together externally).
VAINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0xFFF.
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the end
of the sample time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tADC1_S depend on programming.
This parameter does not include the sample time tADC1_S, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by
internal divider by 2.
Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
75
3.18
On-chip peripherals
3.18.1
Current consumption
Table 43. On-chip peripherals current consumption1
Value
Symbol
C
Parameter
Conditions
Unit
Typ
IDD_BV(CAN)
IDD_BV(eMIOS)
CC T CAN
Bit rate =
(FlexCAN)
500 KB/s
supply current
Bit rate =
on VDD_BV
125 KB/s
Total (static + dynamic)
consumption:
• FlexCAN in loop-back
mode
• XTAL at 8 MHz used as
CAN engine clock
source
• Message sending
period is 580 µs
CC T eMIOS supply Static consumption:
current on
• eMIOS channel OFF
VDD_BV
• Global prescaler enabled
Dynamic consumption:
• It does not change varying the
frequency (0.003 mA)
IDD_BV(SCI)
CC T SCI (LINFlex) Total (static + dynamic) consumption:
supply current • LIN mode
on VDD_BV
• Baud rate: 20 KB/s
IDD_BV(SPI)
CC T SPI (DSPI)
Ballast static consumption (only
supply current clocked)
on VDD_BV
Ballast dynamic consumption
(continuous communication):
• Baud rate: 2 Mb/s
• Transmission every 8 µs
• Frame: 16 bits
IDD_BV
(ADC_0/ADC_1)
IDD_HV_ADC0
8 * fperiph + 85
µA
8 * fperiph + 27
29 * fperiph
3
5 * fperiph + 31
1
16 * fperiph
CC T ADC_0/ADC_1 VDD = 5.5 V Ballast static consumption
supply current
(no conversion)
on VDD_BV
VDD = 5.5 V Ballast dynamic
consumption (continuous
conversion)
41 * fperiph
CC T ADC_0 supply VDD = 5.5 V Analog static consumption
current on
(no conversion)
VDD_HV_ADC0
VDD = 5.5 V Analog dynamic
consumption (continuous
conversion)
200
µA
46 * fperiph
3
mA
MPC5606BK Microcontroller Data Sheet, Rev. 5
76
NXP Semiconductors
Table 43. On-chip peripherals current consumption1 (continued)
Value
Symbol
C
Parameter
Conditions
Unit
Typ
IDD_HV_ADC1
IDD_HV(FLASH)
IDD_BV(PLL)
1
CC T ADC_1 supply VDD = 5.5 V Analog static consumption
current on
(no conversion)
VDD_HV_ADC1
VDD = 5.5 V Analog dynamic
consumption (continuous
conversion)
300 * fperiph
µA
4
mA
CC T CFlash +
VDD = 5.5 V
DFlash supply
current on
VDD_HV
—
12
mA
CC T PLL supply
current on
VDD_BV
—
2.5
mA
VDD = 5.5 V
Operating conditions: TA = 25 °C, fperiph = 8 MHz to 64 MHz
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
77
DSPI characteristics
Table 44. DSPI characteristics1
DSPI0/DSPI1/DSPI5/DSPI6
No.
1
Symbol
C
MPC5606BK Microcontroller Data Sheet, Rev. 5
—
fDSPI
2
tCSCext3
3
tASCext
4
4
tSDC
Unit
Min
Typ
Max
Min
Typ
Max
Master mode
(MTFE = 0)
125
—
—
3332
—
—
D
Slave mode
(MTFE = 0)
125
—
—
333
—
—
D
Master mode
(MTFE = 1)
83
—
—
145
—
—
D
Slave mode
(MTFE = 1)
83
—
—
145
—
—
SR D DSPI digital controller frequency
—
—
fCPU
—
—
fCPU
MHz
SR D CS to SCK delay
Slave mode
32
—
—
32
—
—
ns
SR D After SCK delay
Slave mode
1/fDSPI + 5
—
—
1/fDSPI + 5
—
—
ns
CC D SCK duty cycle
Master mode
—
tSCK/2
—
—
tSCK/2
—
ns
SR D
Slave mode
tSCK/2
—
—
tSCK/2
—
—
SR D SCK cycle time
tSCK
DSPI2/DSPI4
Parameter
ns
5
tA
SR D Slave access time
Slave mode
—
—
1/fDSPI + 70
—
—
1/fDSPI + 130
ns
6
tDI
SR D Slave SOUT disable time Slave mode
7
—
—
7
—
—
ns
7
tPCSC
—
135
—
—
135
—
—
—
—
135
—
—
CC D PCSx to PCSS time
8
tPASC
CC D PCSS to PCSx time
—
135
9
tSUI
SR D Data setup time for
inputs
Master mode
43
—
—
145
—
—
Slave mode
5
—
—
5
—
—
0
—
—
0
—
—
Slave mode
26
—
—
26
—
—
CC D Data valid after SCK
edge
Master mode
—
—
32
—
—
50
Slave mode
—
—
52
—
—
160
CC D Data hold time for
outputs
Master mode
0
—
—
0
—
—
Slave mode
8
—
—
13
—
—
10
NXP Semiconductors
11
12
SR D Data hold time for inputs Master mode
tHI
tSUO
7
tHO7
ns
ns
ns
ns
Electrical characteristics
78
3.18.2
NXP Semiconductors
1
2
3
4
5
6
7
Operating conditions: Cout = 10 to 50 pF, SlewIN = 3.5 to 15 ns.
For DSPI4, if SOUT is mapped to a SLOW pad while SCK is mapped to a MEDIUM pad (or vice versa), the minimum cycle time for SCK
should be calculated based on the rise and fall times of the SLOW pad. For MTFE=1, SOUT must not be mapped to a SLOW pad while SCK
is mapped to a MEDIUM pad.
The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers),
delay between internal CS and internal SCK must be higher than ΔtCSC to ensure positive tCSCext.
The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay
between internal CS and internal SCK must be higher than ΔtASC to ensure positive tASCext.
For DSPIx_CTARn[PCSSCK] = 11.
This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.
SCK and SOUT are configured as MEDIUM pad.
MPC5606BK Microcontroller Data Sheet, Rev. 5
2
3
PCSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
SIN
10
First Data
Data
12
SOUT
First Data
Last Data
11
Data
Last Data
Figure 23. DSPI classic SPI timing — master, CPHA = 0
79
Electrical characteristics
Note: Numbers shown reference Table 44.
PCSx
SCK Output
(CPOL = 0)
10
SCK Output
(CPOL = 1)
9
Data
First Data
SIN
Last Data
12
SOUT
11
Data
First Data
Last Data
Note: Numbers shown reference Table 44.
Figure 24. DSPI classic SPI timing — master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
SOUT
First Data
9
SIN
12
11
Data
Last Data
Data
Last Data
6
10
First Data
Note: Numbers shown reference Table 44.
Figure 25. DSPI classic SPI timing — slave, CPHA = 0
MPC5606BK Microcontroller Data Sheet, Rev. 5
80
NXP Semiconductors
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
10
First Data
Note: Numbers shown reference Table 44.
Figure 26. DSPI classic SPI timing — slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
SIN
First Data
10
Last Data
Data
12
SOUT
First Data
11
Data
Last Data
Note: Numbers shown reference Table 44.
Figure 27. DSPI modified transfer format timing — master, CPHA = 0
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
81
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
SIN
First Data
Last Data
Data
12
First Data
SOUT
11
Last Data
Data
Note: Numbers shown reference Table 44.
Figure 28. DSPI modified transfer format timing — master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
SOUT
First Data
Data
First Data
6
Last Data
10
9
SIN
12
11
5
Data
Last Data
Note: Numbers shown reference Table 44.
Figure 29. DSPI modified transfer format timing — slave, CPHA = 0
MPC5606BK Microcontroller Data Sheet, Rev. 5
82
NXP Semiconductors
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
First Data
SOUT
9
Last Data
Data
Last Data
10
First Data
SIN
Data
Note: Numbers shown reference Table 44.
Figure 30. DSPI modified transfer format timing — slave, CPHA = 1
8
7
PCSS
PCSx
Note: Numbers shown reference Table 44.
Figure 31. DSPI PCS strobe (PCSS) timing
3.18.3
JTAG characteristics
Table 45. JTAG characteristics
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
1
tJCYC
CC
D TCK cycle time
64
—
—
ns
2
tTDIS
CC
D TDI setup time
15
—
—
ns
3
tTDIH
CC
D TDI hold time
5
—
—
ns
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
83
Table 45. JTAG characteristics (continued)
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
4
tTMSS
CC
D TMS setup time
15
—
—
ns
5
tTMSH
CC
D TMS hold time
5
—
—
ns
6
tTDOV
CC
D TCK low to TDO valid
—
—
33
ns
7
tTDOI
CC
D TCK low to TDO invalid
6
—
—
ns
TCK
2/4
DATA INPUTS
3/5
INPUT DATA VALID
6
DATA OUTPUTS
OUTPUT DATA VALID
7
DATA OUTPUTS
Note: Numbers shown reference Table 45.
Figure 32. Timing diagram — JTAG boundary scan
MPC5606BK Microcontroller Data Sheet, Rev. 5
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NXP Semiconductors
4
Package characteristics
4.1
Package mechanical data
4.1.1
176 LQFP
Figure 33. 176 LQFP package mechanical drawing (Part 1 of 3)
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
85
Figure 34. 176 LQFP package mechanical drawing (Part 2 of 3)
MPC5606BK Microcontroller Data Sheet, Rev. 5
86
NXP Semiconductors
Figure 35. 176 LQFP package mechanical drawing (Part 3 of 3)
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
87
4.1.2
144 LQFP
Figure 36. 144 LQFP package mechanical drawing (Part 1 of 2)
MPC5606BK Microcontroller Data Sheet, Rev. 5
88
NXP Semiconductors
Figure 37. 144 LQFP package mechanical drawing (Part 2 of 2)
MPC5606BK Microcontroller Data Sheet, Rev. 5
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89
4.1.3
100 LQFP
Figure 38. 100 LQFP package mechanical drawing (Part 1 of 3)
MPC5606BK Microcontroller Data Sheet, Rev. 5
90
NXP Semiconductors
Figure 39. 100 LQFP package mechanical drawing (Part 2 of 3)
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
91
Figure 40. 100 LQFP package mechanical drawing (Part 3 of 3)
MPC5606BK Microcontroller Data Sheet, Rev. 5
92
NXP Semiconductors
5
Ordering information
Example code:
M
PC
56
0
6
B
K0A
M
LL
6
R
Qualification status
Power Architecture Core
Automotive platform
Core version
Flash memory size (core dependent)
Product
Fab and mask Indicator
Temperature spec.
Package code
Frequency
R = Tape & Reel (blank if Tray)
Qualification status
M = General market qualified
S = Automotive qualified
P = Engineering samples
Automotive Platform
56 = Power Architecture in 90nm
Flash memory size (for z0 core)
5 = 768 KB
6 = 1024 KB
Product
B = Body
Fab and mask Indicator
K = TSMC Fab
0 = Version of the maskset
A = Mask set indicator (Blank = 1st
production maskset, A = 2nd,
B = 3rd, etc)
Core version
0 = e200z0
Temperature spec.
C = –40 to 85 °C
V = –40 to 105 °C
M = –40 to 125 °C
Package code
LL = 100 LQFP
LQ = 144 LQFP
LU = 176 LQFP
Frequency
4 = Up to 48 MHz
6 = Up to 64 MHz
Note: Not all options are available on all devices.
Figure 41. Commercial product code structure
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
93
6
Revision history
Table 46. Revision history
Revision
Date
Description of changes
1
22 Apr 2011
Initial release.
2
15 May 2013
Changed device number to MPC5606BK.
In Table 2 (Functional port pins), updated PA[11] AF2, PD[13] AF2, and PH[11] AF3 I/O
direction to “I/O”.
In Table 3 (Pad types), corrected “Fast” in the “S” row to “Slow.”
In Table 5 (PAD3V5V field description), updated footnote 2.
In Table 6 (OSCILLATOR_MARGIN field description), updated footnote 2.
Inserted Section 3.2.3, NVUSRO[WATCHDOG_EN] field description.
In Table 8 (Absolute maximum ratings), Table 9 (Recommended operating conditions (3.3 V)),
and Table 10 (Recommended operating conditions (5.0 V)), corrected the parameter
description for VDD_ADC to “Voltage on VDD_HV_ADC0, VDD_HV_ADC1 (ADC reference)
with respect to ground (VSS)”
In Section 3.6.1, I/O pad types bullet item, removed Nexus reference.
In Table 12 (I/O input DC electrical characteristics), added specifications for 85 °C.
In Table 13 (I/O pull-up/pull-down DC electrical characteristics), Table 14 (SLOW configuration
output buffer electrical characteristics), Table 15 (MEDIUM configuration output buffer
electrical characteristics), and Table 16 (FAST configuration output buffer electrical
characteristics), changed sentence in footnote 2 to “All pads but RESET are configured in
input or in high impedance state.”
In Table 15 (MEDIUM configuration output buffer electrical characteristics), for VOL, changed
IOH to IOL.
Updated Table 20 (I/O weight).
In Table 21 (Reset electrical characteristics) changed sentence in footnote 4 to “All pads but
RESET are configured in input or in high impedance state.”
in Table 22 (Voltage regulator electrical characteristics), corrected the maximum value for
IDD_BV in Table 22 (Voltage regulator electrical characteristics) to 300 mA.
In Table 23 (Low voltage monitor electrical characteristics), changed VPORUP classification tag
from “P” (Production testing guaranteed) to “D” (Design simulation). Changed VLVDHV3BH
classification tag from “P” (Production testing guaranteed) to “T” (Design characterization).
In Table 23 (Low voltage monitor electrical characteristics), changed VLVDHV3L, VLVDHV3BL
minimums from 2.7 V to 2.6 V.
MPC5606BK Microcontroller Data Sheet, Rev. 5
94
NXP Semiconductors
Table 46. Revision history (continued)
Revision
Date
Description of changes
2
(cont.)
15 May 2013
In Table 24 (Electrical characteristics in different application modes),
— Changed IDDMAX Typ to 81 mA and IDDMAX Typ to 130 mA.
— Changed IDDRUN Typ for fCPU = 32 MHz to 40 mA.
— Changed IDDRUN Typ for fCPU = 48 MHz to 54 mA. Added IDDRUN Max of 96 mA.
— Changed IDDRUN Typ for fCPU = 64 MHz to 67 mA. Added IDDRUN Max of 120 mA.
— Changed IDDHALT at TA = 25 °C Typ to 10 mA and IDDHALT Max to 15 mA.
— Changed IDDHALT at TA = 125 °C Typ to 15 mA and IDDHALT Max to 28 mA.
— Changed IDDSTOP TA temperature from –40 °C to 25 °C.
— Changed IDDSTOP at TA = 25 °C Typ to 130 µA and IDDSTOP Max to 500 µA.
— Changed IDDSTOP at TA = 55 °C Typ to 180 µA.
— Changed IDDSTOP at TA = 85 °C Typ to 1 mA and IDDSTOP Max to 5 mA.
— Changed IDDSTOP at TA = 105 °C Typ to 3 mA and IDDSTOP Max to 9 mA.
— Changed IDDSTOP at TA = 125 °C Typ to 5 mA and IDDSTOP Max to 14 mA.
— Changed IDDSTDBY2 at TA = 25 °C Typ to 17 µA and Max to 80 µA.
— Changed IDDSTDBY2 at TA = 55 °C Typ to 30 µA.
— Changed IDDSTDBY2 at TA = 85 °C Typ to 100 µA.
— Changed IDDSTDBY2 at TA = 105 °C Typ to 280 µA and Max to 950 µA.
— Changed IDDSTDBY2 at TA = 125 °C Typ to 460 µA and Max to 1700 µA.
— Changed the parameter classification for IDDSTANDBY2 (TA = 125 °C)
— Changed IDDSTDBY1 at TA = 25 °C Typ to 12 µA and Max to 50 µA.
— Changed IDDSTDBY1 at TA = 55 °C Typ to 24 µA.
— Changed IDDSTDBY1 at TA = 85 °C Typ to 48 µA.
— Changed IDDSTDBY1 at TA = 105 °C Typ to 150 µA and Max to 500 µA.
— Changed IDDSTDBY1 at TA = 125 °C Typ to 260 µA.
— Changed the third sentence of Footnote 3 to begin with “The given value is thought to be
a worst case value (64 MHz at 125 °C) with all peripherals running.”
— Removed footnotes 8 and 9 regarding IDDHALT and IDDSTOP.
— Corrected “C” characteristics to reflect testing status.
In Section 3.10, Flash memory electrical characteristics, removed the "FLASH_BIU settings
vs. frequency of operation" table.
In Table 28 (Flash power supply DC electrical characteristics), corrected Footnote 2 to specify
125 °C.
In Section 3.14, FMPLL electrical characteristics, changed the text “the main oscillator driver”
to “the FXOSC or FIRC sources.”
In Table 40 (ADC input leakage current), added specifications for 85 °C.
In Table 44 (DSPI characteristics), added tSCK specifications for MTFE=1.
In Table 44 (DSPI characteristics), updated specifications 7 and 8 to 13 ns, all DSPIs.
in ADC section, corrected Equation 11.
In Figure 41 (Commercial product code structure), added “Note: Not all options are available
on all devices.”
Removed Section 6, Abbreviations.
3
11 Sep 2013
Updated the temperature in table note 2 in Table 1 (MPC5606BK family comparison) from 105
o
C to 125 oC.
4
25 Nov2015
Updated the Max value current for IADC0run from 40 mA to 5 mA in Table 41 (ADC_0 conversion
characteristics (10-bit ADC_0)).
5
7 Nov 2017
In Table 9 (Recommended operating conditions (3.3 V)) added Min value for TVDD.
In Table 10 (Recommended operating conditions (5.0 V)) added Min value for TVDD.
In Table 44 (DSPI characteristics) changed the for DSPI 2 and 4, in MTFE=1 mode from 125
to 145.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
95
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MPC5606B
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11/2017
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