NXP Semiconductors
Data Sheet: Technical Data
Document Number: MPC5643L
Rev. 10, 11/2021
MPC5643L
MPC5643L Microcontroller
Data Sheet
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High-performance e200z4d dual core
— 32-bit Power Architecture® technology CPU
— Core frequency as high as 120 MHz
— Dual issue five-stage pipeline core
— Variable Length Encoding (VLE)
— Memory Management Unit (MMU)
— 4 KB instruction cache with error detection code
— Signal processing engine (SPE)
Memory available
— 1 MB flash memory with ECC
— 128 KB on-chip SRAM with ECC
— Built-in RWW capabilities for EEPROM emulation
SIL3/ASILD innovative safety concept: LockStep mode and
Fail-safe protection
— Sphere of replication (SoR) for key components (such as
CPU core, eDMA, crossbar switch)
— Fault collection and control unit (FCCU)
— Redundancy control and checker unit (RCCU) on outputs
of the SoR connected to FCCU
— Boot-time Built-In Self-Test for Memory (MBIST) and
Logic (LBIST) triggered by hardware
— Boot-time Built-In Self-Test for ADC and flash memory
triggered by software
— Replicated safety enhanced watchdog
— Replicated junction temperature sensor
— Non-maskable interrupt (NMI)
— 16-region memory protection unit (MPU)
— Clock monitoring units (CMU)
— Power management unit (PMU)
MAPBGA–225
15 mm x 15 mm
QFN12
##_mm_x_##mm
SOT-343R
##_mm_x_##mm
PKG-TBD
## mm x ## mm
144 LQFP
(20 x 20 x 1.4 mm)
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TBD
257 MAPBGA
(14 x 14 x 0.8 mm)
— Cyclic redundancy check (CRC) unit
Decoupled Parallel mode for high-performance use of
replicated cores
Nexus Class 3+ interface
Interrupts
— Replicated 16-priority controller
— Replicated 16-channel eDMA controller
GPIOs individually programmable as input, output or
special function
Three 6-channel general-purpose eTimer units
2 FlexPWM units
— Four 16-bit channels per module
Communications interfaces
— 2 LINFlexD channels
— 3 DSPI channels with automatic chip select
generation
— 2 FlexCAN interfaces (2.0B Active) with 32
message objects
— FlexRay module (V2.1 Rev. A) with 2 channels,
64 message buffers and data rates up to 10 Mbit/s
Two 12-bit analog-to-digital converters (ADCs)
— 16 input channels
— Programmable cross triggering unit (CTU) to
synchronize ADCs conversion with timer and
PWM
Sine wave generator (D/A with low pass filter)
On-chip CAN/UART bootstrap loader
Single 3.0 V to 3.6 V voltage supply
Ambient temperature range –40 °C to 125 °C
Junction temperature range –40 °C to 150 °C
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.5.1 High-performance e200z4d core . . . . . . . . . . . . .7
1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . .8
1.5.3 Memory Protection Unit (MPU) . . . . . . . . . . . . . .8
1.5.4 Enhanced Direct Memory Access (eDMA) . . . . .8
1.5.5 On-chip flash memory with ECC . . . . . . . . . . . . .9
1.5.6 On-chip SRAM with ECC. . . . . . . . . . . . . . . . . . .9
1.5.7 Platform flash memory controller. . . . . . . . . . . . .9
1.5.8 Platform Static RAM Controller (SRAMC) . . . . .10
1.5.9 Memory subsystem access time . . . . . . . . . . . .10
1.5.10 Error Correction Status Module (ECSM) . . . . . .11
1.5.11 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . .11
1.5.12 Interrupt Controller (INTC). . . . . . . . . . . . . . . . .11
1.5.13 System clocks and clock generation . . . . . . . . .12
1.5.14 Frequency-Modulated Phase-Locked Loop
(FMPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.5.15 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.5.16 Internal Reference Clock (RC) oscillator . . . . . .13
1.5.17 Clock, reset, power, mode and test control
modules (MC_CGM, MC_RGM, MC_PCU, and MC_ME)
13
1.5.18 Periodic Interrupt Timer Module (PIT) . . . . . . . .13
1.5.19 System Timer Module (STM). . . . . . . . . . . . . . .13
1.5.20 Software Watchdog Timer (SWT) . . . . . . . . . . .14
1.5.21 Fault Collection and Control Unit (FCCU) . . . . .14
1.5.22 System Integration Unit Lite (SIUL) . . . . . . . . . .14
1.5.23 Non-Maskable Interrupt (NMI) . . . . . . . . . . . . . .14
1.5.24 Boot Assist Module (BAM). . . . . . . . . . . . . . . . .14
1.5.25 System Status and Configuration Module
(SSCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.5.26 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.5.27 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.5.28 Serial communication interface module
(LINFlexD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.5.29 Deserial Serial Peripheral Interface (DSPI) . . . .17
1.5.30 FlexPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.5.31 eTimer module. . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5.32 Sine Wave Generator (SWG) . . . . . . . . . . . . . .19
1.5.33 Analog-to-Digital Converter module (ADC) . . . .19
1.5.34 Cross Triggering Unit (CTU) . . . . . . . . . . . . . . .19
1.5.35 Cyclic Redundancy Checker (CRC) Unit . . . . . .20
1.5.36 Redundancy Control and Checker Unit (RCCU)20
1.5.37 Junction temperature sensor . . . . . . . . . . . . . . .20
1.5.38 Nexus Port Controller (NPC) . . . . . . . . . . . . . . .20
1.5.39 IEEE 1149.1 JTAG Controller (JTAGC) . . . . . . .21
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1.5.40 Voltage regulator / Power Management Unit
(PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.5.41 Built-In Self-Test (BIST) capability . . . . . . . . . . 22
Package pinouts and signal descriptions . . . . . . . . . . . . . . . 23
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2 Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.3 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.4 Pin muxing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . 76
3.3 Recommended operating conditions . . . . . . . . . . . . . . 77
3.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 78
3.4.1 General notes for specifications at maximum
junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.5 Electromagnetic Interference (EMI) characteristics . . . 81
3.6 Electrostatic discharge (ESD) characteristics . . . . . . . 82
3.7 Static latch-up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.8 Voltage regulator electrical characteristics . . . . . . . . . 83
3.9 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . 86
3.10 Supply current characteristics . . . . . . . . . . . . . . . . . . . 87
3.11 Temperature sensor electrical characteristics . . . . . . . 90
3.12 Main oscillator electrical characteristics . . . . . . . . . . . 90
3.13 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 92
3.14 16 MHz RC oscillator electrical characteristics . . . . . . 94
3.15 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 94
3.15.1 Input Impedance and ADC Accuracy . . . . . . . . 94
3.16 Flash memory electrical characteristics . . . . . . . . . . . 99
3.17 SWG electrical characteristics. . . . . . . . . . . . . . . . . . 100
3.18 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
3.18.1 Pad AC specifications. . . . . . . . . . . . . . . . . . . 101
3.19 Reset sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.19.1 Reset sequence duration . . . . . . . . . . . . . . . . 102
3.19.2 Reset sequence description. . . . . . . . . . . . . . 102
3.19.3 Reset sequence trigger mapping . . . . . . . . . . 105
3.19.4 Reset sequence — start condition . . . . . . . . . 106
3.19.5 External watchdog window. . . . . . . . . . . . . . . 107
3.20 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . 107
3.20.1 RESET pin characteristics . . . . . . . . . . . . . . . 108
3.20.2 WKUP/NMI timing . . . . . . . . . . . . . . . . . . . . . 109
3.20.3 IEEE 1149.1 JTAG interface timing . . . . . . . . 109
3.20.4 Nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . 111
3.20.5 External interrupt timing (IRQ pin) . . . . . . . . . 114
3.20.6 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 120
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MPC5643L Microcontroller Data Sheet, Rev. 10
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NXP Semiconductors
Introduction
1
Introduction
1.1
Document overview
This document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the devices.
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5643L series of
microcontroller units (MCUs). For functional characteristics, see the MPC5643L Microcontroller Reference Manual. For use
of the MPC5643Lin a fail-safe system according to safety standard ISO26262, see the Safety Application Guide for MPC5643L.
1.2
Description
The MPC5643L series microcontrollers are system-on-chip devices that are built on Power Architecture technology and contain
enhancements that improve the architecture’s fit in embedded applications, include additional instruction support for digital
signal processing (DSP) and integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital
converter, Controller Area Network, and an enhanced modular input-output system.
The MPC5643L family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It
belongs to an expanding range of automotive-focused products designed to address electrical hydraulic power steering (EHPS),
electric power steering (EPS) and airbag applications. The advanced and cost-efficient host processor core of the MPC5643L
automotive controller family complies with the Power Architecture embedded category. It operates at speeds as high as
120 MHz and offers high-performance processing optimized for low power consumption. It capitalizes on the available
development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and
configuration code to assist with users’ implementations.
1.3
Device comparison
Table 1. MPC5643L device summary
MPC5643L
Feature
CPU
Type
2 × e200z4
(in lock-step or decoupled operation)
Architecture
Harvard
Execution speed
0–120 MHz (+2% FM)
DMIPS intrinsic performance
>240 MIPS
SIMD (DSP + FPU)
Yes
MMU
16 entry
Instruction set PPC
Yes
Instruction set VLE
Yes
Instruction cache
4 KB, EDC
MPU-16 regions
Yes, replicated module
Semaphore unit (SEMA4)
Buses
Core bus
AHB, 32-bit address, 64-bit data
Internal periphery bus
Crossbar
Yes
Master × slave ports
32-bit address, 32-bit data
Lock Step Mode: 4 × 3
Decoupled Parallel Mode: 6 × 3
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
3
Introduction
Table 1. MPC5643L device summary (continued)
MPC5643L
Feature
Memory
Flash
1 MB, ECC, RWW
Static RAM (SRAM)
Modules
Interrupt Controller (INTC)
128 KB, ECC
16 interrupt levels, replicated module
Periodic Interrupt Timer (PIT)
1 × 4 channels
System Timer Module (STM)
1 × 4 channels, replicated module
Software Watchdog Timer (SWT)
eDMA
Yes, replicated module
16 channels, replicated module
FlexRay
1 × 64 message buffers, dual channel
FlexCAN
2 × 32 message buffers
LINFlexD (UART and LIN with DMA support)
2
Clock out
Yes
Fault Collection and Control Unit (FCCU)
Yes
Cross Triggering Unit (CTU)
Yes
3 × 6 channels1
eTimer
2 Module 4 × (2 + 1) channels2
FlexPWM
Analog-to-Digital Converter (ADC)
2 × 12-bit ADC, 16 channels per ADC
(3 internal, 4 shared and 9 external)
Sine Wave Generator (SWG)
Modules
(cont.)
Deserial Serial Peripheral Interface (DSPI)
32 point
3 × DSPI
as many as 8 chip selects
Cyclic Redundancy Checker (CRC) unit
Junction temperature sensor (TSENS)
Yes
Yes, replicated module
≥ 16
Digital I/Os
Supply
Device power supply
Analog reference voltage
Clocking
3.3 V with integrated bypassable ballast transistor
External ballast transistor not needed for bare die
3.0 V – 3.6 V and 4.5 V – 5.5 V
Frequency-modulated phase-locked loop (FMPLL)
Internal RC oscillator
External crystal oscillator
Debug
Nexus
2
16 MHz
4 – 40 MHz
Level 3+
MPC5643L Microcontroller Data Sheet, Rev. 10
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NXP Semiconductors
Introduction
Table 1. MPC5643L device summary (continued)
Feature
Packages
Temperature
LQFP
MPC5643L
144 pins
MAPBGA
257 MAPBGA
Temperature range (junction)
–40 to 150 °C
Ambient temperature range using external ballast
transistor (LQFP)
–40 to 125 °C
Ambient temperature range using external ballast
transistor (BGA)
–40 to 125 °C
1
The third eTimer (eTimer_2) is available with external I/O access only in the BGA package, on the LQFP package
eTimer_2 is available internally only without any external I/O access.
2
The second FlexPWM module is available only in the BGA package.
1.4
Block diagram
Figure 1 shows a top-level block diagram of the MPC5643L device.
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
5
Introduction
PMU
JTAG
Nexus
e200z4
SWT
ECSM
STM
INTC
SPE
VLE
VLE
ECSM
STM
INTC
MMU
FlexRay
I-CACHE
eDMA
SWT
SPE
MMU
SEMA4
e200z4
SEMA4
I-CACHE
RC
eDMA
Crossbar Switch
Crossbar Switch
Memory Protection Unit
Memory Protection Unit
ECC logic for SRAM
ECC logic for SRAM
PBRIDGE
RC
TSENS
PBRIDGE
RC
Flash memory
ECC bits + logic
TSENS
SRAM
ECC bits
ADC
BAM
CMU
CRC
CTU
DSPI
ECC
ECSM
eDMA
FCCU
FlexCAN
FMPLL
INTC
IRCOSC
JTAG
– Analog-to-Digital Converter
– Boot Assist Module
– Clock Monitoring Unit
– Cyclic Redundancy Check unit
– Cross Triggering Unit
– Serial Peripherals Interface
– Error Correction Code
– Error Correction Status Module
– Enhanced Direct Memory Access controller
– Fault Collection and Control Unit
– Controller Area Network controller
– Frequency Modulated Phase Locked Loop
– Interrupt Controller
– Internal RC Oscillator
– Joint Test Action Group interface
LINFlexD
MC
PBRIDGE
PIT
PMU
RC
RTC
SEMA4
SIUL
SSCM
STM
SWG
SWT
TSENS
XOSC
SWG
PIT
FCCU
DSPI
DSPI
DSPI
LINFlexD
LINFlexD
FlexCAN
FlexCAN
eTimer
eTimer
eTimer
FlexPWM
FlexPWM
CRC
CMU
IRCOSC
ADC
CTU
FMPLL
WakeUp
CMU
Secondary FMPLL
SIUL
CMU
SSCM
XOSC
ADC
BAM
MC
RC
– LIN controller with DMA support
– Mode Entry, Clock, Reset, & Power
– Peripheral bridge
– Periodic Interrupt Timer
– Power Management Unit
– Redundancy Checker
– Real Time Clock
– Semaphore Unit
– System Integration Unit Lite
– System Status and Configuration Module
– System Timer Module
– Sine Wave Generator
– Software Watchdog Timer
– Temperature Sensor
– Crystal Oscillator
Figure 1. MPC5643L block diagram
MPC5643L Microcontroller Data Sheet, Rev. 10
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NXP Semiconductors
Introduction
1.5
1.5.1
Feature details
High-performance e200z4d core
The e200z4d Power Architecture® core provides the following features:
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2 independent execution units, both supporting fixed-point and floating-point operations
Dual issue 32-bit Power Architecture technology compliant
— 5-stage pipeline (IF, DEC, EX1, EX2, WB)
— In-order execution and instruction retirement
Full support for Power Architecture instruction set and Variable Length Encoding (VLE)
— Mix of classic 32-bit and 16-bit instruction allowed
— Optimization of code size possible
Thirty-two 64-bit general purpose registers (GPRs)
Harvard bus (32-bit address, 64-bit data)
— I-Bus interface capable of one outstanding transaction plus one piped with no wait-on-data return
— D-Bus interface capable of two transactions outstanding to fill AHB pipe
I-cache and I-cache controller
— 4 KB, 256-bit cache line (programmable for 2- or 4-way)
No data cache
16-entry MMU
8-entry branch table buffer
Branch look-ahead instruction buffer to accelerate branching
Dedicated branch address calculator
3 cycles worst case for missed branch
Load/store unit
— Fully pipelined
— Single-cycle load latency
— Big- and little-endian modes supported
— Misaligned access support
— Single stall cycle on load to use
Single-cycle throughput (2-cycle latency) integer 32 × 32 multiplication
4 – 14 cycles integer 32 × 32 division (average division on various benchmark of nine cycles)
Single precision floating-point unit
— 1 cycle throughput (2-cycle latency) floating-point 32 × 32 multiplication
— Target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 × 32 division
— Special square root and min/max function implemented
Signal processing support: APU-SPE 1.1
— Support for vectorized mode: as many as two floating-point instructions per clock
Vectored interrupt support
Reservation instruction to support read-modify-write constructs
Extensive system development and tracing support via Nexus debug port
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
7
Introduction
1.5.2
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. The
crossbar supports a 32-bit address bus width and a 64-bit data bus width.
The crossbar allows four concurrent transactions to occur from any master port to any slave port, although one of those transfers
must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master
port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting
that slave port are stalled until the higher priority master completes its transactions.
The crossbar provides the following features:
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4 masters and 3 slaves supported per each replicated crossbar
— Masters allocation for each crossbar: e200z4d core with two independent bus interface units (BIU) for I and D
access (2 masters), one eDMA, one FlexRay
— Slaves allocation for each crossbar: a redundant flash-memory controller with 2 slave ports to guarantee maximum
flexibility to handle Instruction and Data array, one redundant SRAM controller with 1 slave port each and 1
redundant peripheral bus bridge
32-bit address bus and 64-bit data bus
Programmable arbitration priority
— Requesting masters can be treated with equal priority and are granted access to a slave port in round-robin method,
based upon the ID of the last master to be granted access or a priority order can be assigned by software at
application run time
Temporary dynamic priority elevation of masters
The XBAR is replicated for each processing channel.
1.5.3
Memory Protection Unit (MPU)
The Memory Protection Unit splits the physical memory into 16 different regions. Each master (eDMA, FlexRay, CPU) can be
assigned different access rights to each region.
•
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16-region MPU with concurrent checks against each master access
32-byte granularity for protected address region
The memory protection unit is replicated for each processing channel.
1.5.4
Enhanced Direct Memory Access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data
movements via 16 programmable channels, with minimal intervention from the host processor. The hardware microarchitecture
includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,
along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation
is used to minimize the overall block size.
The eDMA module provides the following features:
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16 channels supporting 8-, 16-, and 32-bit value single or block transfers
Support variable sized queues and circular buffered queue
Source and destination address registers independently configured to post-increment or stay constant
Support major and minor loop offset
Support minor and major loop done signals
DMA task initiated either by hardware requestor or by software
Each DMA task can optionally generate an interrupt at completion and retirement of the task
Signal to indicate closure of last minor loop
MPC5643L Microcontroller Data Sheet, Rev. 10
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Introduction
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Transfer control descriptors mapped inside the SRAM
The eDMA controller is replicated for each processing channel.
1.5.5
On-chip flash memory with ECC
This device includes programmable, non-volatile flash memory. The non-volatile memory (NVM) can be used for instruction
storage or data storage, or both. The flash memory module interfaces with the system bus through a dedicated flash memory
array controller. It supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory.
The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow no-wait responses. Buffer misses incur a 3 wait
state response at 120 MHz.
The flash memory module provides the following features
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1.5.6
1 MB of flash memory in unique multi-partitioned hard macro
Sectorization: 16 KB + 2 × 48 KB + 16 KB + 2 × 64 KB + 2 × 128 KB + 2 × 256 KB
EEPROM emulation (in software) within same module but on different partition
16 KB test sector and 16 KB shadow block for test, censorship device and user option bits
Wait states:
— 3 wait states for frequencies =< 120 MHz
— 2 wait states for frequencies =< 80 MHz
— 1 wait state for frequencies =< 60 MHz
Flash memory line 128-bit wide with 8-bit ECC on 64-bit word (total 144 bits)
Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations
1-bit error correction, 2-bit error detection
On-chip SRAM with ECC
The MPC5643L SRAM provides a general-purpose single port memory.
ECC handling is done on a 32-bit boundary for data and it is extended to the address to have the highest possible diagnostic
coverage including the array internal address decoder.
The SRAM module provides the following features:
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1.5.7
System SRAM: 128 KB
ECC on 32-bit word (syndrome of 7 bits)
— ECC covers SRAM bus address
1-bit error correction, 2-bit error detection
Wait states:
— 1 wait state for frequencies =< 120 MHz
— 0 wait states for frequencies =< 80 MHz
Platform flash memory controller
The following list summarizes the key features of the flash memory controller:
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Single AHB port interface supports a 64-bit data bus. All AHB aligned and unaligned reads within the 32-bit container
are supported. Only aligned word writes are supported.
Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank.
Code flash (bank0) interface provides configurable read buffering and page prefetch support.
— Four page-read buffers (each 128 bits wide) and a prefetch controller support speculative reading and optimized
flash access.
MPC5643L Microcontroller Data Sheet, Rev. 10
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Introduction
•
Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The buffers implement a
least-recently-used replacement algorithm to maximize performance.
Programmable response for read-while-write sequences including support for stall-while-write, optional stall
notification interrupt, optional flash operation abort , and optional abort notification interrupt.
Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of
platforms and frequencies.
Support of address-based read access timing for emulation of other memory types.
Support for reporting of single- and multi-bit error events.
Typical operating configuration loaded into programming model by system reset.
•
•
•
•
•
The platform flash controller is replicated for each processor.
1.5.8
Platform Static RAM Controller (SRAMC)
The SRAMC module is the platform SRAM array controller, with integrated error detection and correction.
The main features of the SRAMC provide connectivity for the following interfaces:
•
•
•
XBAR Slave Port (64-bit data path)
ECSM (ECC Error Reporting, error injection and configuration)
SRAM array
The following functions are implemented:
•
•
•
ECC encoding (32-bit boundary for data and complete address bus)
ECC decoding (32-bit boundary and entire address)
Address translation from the AHB protocol on the XBAR to the SRAM array
The platform SRAM controller is replicated for each processor.
1.5.9
Memory subsystem access time
Every memory access the CPU performs requires at least one system clock cycle for the data phase of the access. Slower
memories or peripherals may require additional data phase wait states. Additional data phase wait states may also occur if the
slave being accessed is not parked on the requesting master in the crossbar.
Table 2 shows the number of additional data phase wait states required for a range of memory accesses.
Table 2. Platform memory access time summary
AHB transfer
Data phase
wait states
Description
e200z4d instruction fetch
0
Flash memory prefetch buffer hit (page hit)
e200z4d instruction fetch
3
Flash memory prefetch buffer miss
(based on 4-cycle random flash array access time)
e200z4d data read
0–1
e200z4d data write
0
SRAM read
SRAM 32-bit write
MPC5643L Microcontroller Data Sheet, Rev. 10
10
NXP Semiconductors
Introduction
Table 2. Platform memory access time summary (continued)
AHB transfer
Data phase
wait states
e200z4d data write
0
e200z4d data write
0–2
Description
SRAM 64-bit write (executed as 2 x 32-bit writes)
SRAM 8-,16-bit write
(Read-modify-Write for ECC)
e200z4d flash memory read
0
Flash memory prefetch buffer hit (page hit)
e200z4d flash memory read
3
Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle
of program flash memory controller arbitration)
1.5.10
Error Correction Status Module (ECSM)
The ECSM on this device manages the ECC configuration and reporting for the platform memories (flash memory and SRAM).
It does not implement the actual ECC calculation. A detected error (double error for flash memory or SRAM) is also reported
to the FCCU. The following errors and indications are reported into the ECSM dedicated registers:
•
•
•
•
ECC error status and configuration for flash memory and SRAM
ECC error reporting for flash memory
ECC error reporting for SRAM
ECC error injection for SRAM
1.5.11
Peripheral bridge (PBRIDGE)
The PBRIDGE implements the following features:
•
•
•
•
Duplicated periphery
Master access privilege level per peripheral (per master: read access enable; write access enable)
Checker applied on PBRIDGE output toward periphery
Byte endianess swap capability
1.5.12
Interrupt Controller (INTC)
The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time
systems.
For high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can
be raised temporarily so that all tasks which share the resource can not preempt each other.
The INTC provides the following features:
•
•
•
•
Duplicated periphery
Unique 9-bit vector per interrupt source
16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
Priority elevation for shared resource
The INTC is replicated for each processor.
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
11
Introduction
1.5.13
System clocks and clock generation
The following list summarizes the system clock and clock generation on this device:
•
•
•
•
•
•
•
•
Lock status continuously monitored by lock detect circuitry
Loss-of-clock (LOC) detection for reference and feedback clocks
On-chip loop filter (for improved electromagnetic interference performance and fewer external components required)
Programmable output clock divider of system clock (÷1, ÷2, ÷4, ÷8)
FlexPWM module and as many as three eTimer modules running on an auxiliary clock independent from system clock
(with max frequency 120 MHz)
On-chip crystal oscillator with automatic level control
Dedicated internal 16 MHz internal RC oscillator for rapid start-up
— Supports automated frequency trimming by hardware during device startup and by user application
Auxiliary clock domain for motor control periphery (FlexPWM, eTimer, CTU, ADC, and SWG)
1.5.14
Frequency-Modulated Phase-Locked Loop (FMPLL)
Each device has two FMPLLs.
Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock.
Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor,
output clock divider ratio are all software configurable. The FMPLLs have the following major features:
•
•
•
•
•
•
•
•
•
•
•
Input frequency: 4–40 MHz continuous range (limited by the crystal oscillator)
Voltage controlled oscillator (VCO) range: 256–512 MHz
Frequency modulation via software control to reduce and control emission peaks
— Modulation depth ±2% if centered or 0% to –4% if downshifted via software control register
— Modulation frequency: triangular modulation with 25 kHz nominal rate
Option to switch modulation on and off via software interface
Output divider (ODF) for reduced frequency operation without re-lock
3 modes of operation
— Bypass mode
— Normal FMPLL mode with crystal reference (default)
— Normal FMPLL mode with external reference
Lock monitor circuitry with lock status
Loss-of-lock detection for reference and feedback clocks
Self-clocked mode (SCM) operation
On-chip loop filter
Auxiliary FMPLL
— Used for FlexRay due to precise symbol rate requirement by the protocol
— Used for motor control periphery and connected IP (A/D digital interface CTU) to allow independent frequencies
of operation for PWM and timers and jitter-free control
— Option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in
electric motor control loop
— Allows to run motor control periphery at different (precisely lower, equal or higher as required) frequency than
the system to ensure higher resolution
MPC5643L Microcontroller Data Sheet, Rev. 10
12
NXP Semiconductors
Introduction
1.5.15
Main oscillator
The main oscillator provides these features:
•
•
•
•
Input frequency range 4–40 MHz
Crystal input mode
External reference clock (3.3 V) input mode
FMPLL reference
1.5.16
Internal Reference Clock (RC) oscillator
The architecture uses constant current charging of a capacitor. The voltage at the capacitor is compared to the stable bandgap
reference voltage. The RC oscillator is the device safe clock.
The RC oscillator provides these features:
•
•
•
•
Nominal frequency 16 MHz
±5% variation over voltage and temperature after process trim
Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the
FMPLL
RC oscillator is used as the default system clock during startup and can be used as back-up input source of FMPLL(s)
in case XOSC fails
1.5.17
Clock, reset, power, mode and test control modules (MC_CGM,
MC_RGM, MC_PCU, and MC_ME)
These modules provide the following:
•
•
•
•
Clock gating and clock distribution control
Halt, stop mode control
Flexible configurable system and auxiliary clock dividers
Various execution modes
— HALT and STOP mode as reduced activity low power mode
— Reset, Idle, Test, Safe
— Various RUN modes with software selectable powered modules
— No stand-by mode implemented (no internal switchable power domains)
1.5.18
Periodic Interrupt Timer Module (PIT)
The PIT module implements the following features:
•
•
•
4 general purpose interrupt timers
32-bit counter resolution
Can be used for software tick or DMA trigger operation
1.5.19
System Timer Module (STM)
The STM implements the following features:
•
•
Up-counter with 4 output compare registers
OS task protection and hardware tick implementation per AUTOSAR1 requirement
1.Automotive Open System Architecture
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
13
Introduction
The STM is replicated for each processor.
1.5.20
Software Watchdog Timer (SWT)
This module implements the following features:
•
•
•
•
•
Fault tolerant output
Safe internal RC oscillator as reference clock
Windowed watchdog
Program flow control monitor with 16-bit pseudorandom key generation
Allows a high level of safety (SIL3 monitor)
The SWT module is replicated for each processor.
1.5.21
Fault Collection and Control Unit (FCCU)
The FCCU module has the following features:
•
•
•
•
Redundant collection of hardware checker results
Redundant collection of error information and latch of faults from critical modules on the device
Collection of self-test results
Configurable and graded fault control
— Internal reactions (no internal reaction, IRQ, Functional Reset, Destructive Reset, or Safe mode entered)
— External reaction (failure is reported to the external/surrounding system via configurable output pins)
1.5.22
System Integration Unit Lite (SIUL)
The SIUL controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal
peripheral multiplexing, and system reset operation. The reset configuration block contains the external pin boot configuration
logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform
and discrete input/output control of the I/O pins of the MCU.
The SIU provides the following features:
•
•
Centralized pad control on a per-pin basis
— Pin function selection
— Configurable weak pull-up/down
— Configurable slew rate control (slow/medium/fast)
— Hysteresis on GPIO pins
— Configurable automatic safe mode pad control
Input filtering for external interrupts
1.5.23
Non-Maskable Interrupt (NMI)
The non-maskable interrupt with de-glitching filter supports high-priority core exceptions.
1.5.24
Boot Assist Module (BAM)
The BAM is a block of read-only memory with hard-coded content. The BAM program is executed only if serial booting mode
is selected via boot configuration pins.
MPC5643L Microcontroller Data Sheet, Rev. 10
14
NXP Semiconductors
Introduction
The BAM provides the following features:
•
•
•
•
Enables booting via serial mode (FlexCAN or LINFlex-UART)
Supports programmable 64-bit password protection for serial boot mode
Supports serial bootloading of either Power Architecture code (default) or Freescale VLE code
Automatic switch to serial boot mode if internal flash memory is blank or invalid
1.5.25
System Status and Configuration Module (SSCM)
The SSCM on this device features the following:
•
•
•
•
•
System configuration and status
Debug port status and debug port enable
Multiple boot code starting locations out of reset through implementation of search for valid Reset Configuration Half
Word
Sets up the MMU to allow user boot code to execute as either Power Architecture code (default) or as Freescale VLE
code out of flash memory
Triggering of device self-tests during reset phase of device boot
1.5.26
FlexCAN
The FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version
2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of
this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required
bandwidth.
The FlexCAN module provides the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Full implementation of the CAN protocol specification, version 2.0B
— Standard data and remote frames
— Extended data and remote frames
— 0 to 8 bytes data length
— Programmable bit rate as fast as 1Mbit/s
32 message buffers of 0 to 8 bytes data length
Each message buffer configurable as receive or transmit buffer, all supporting standard and extended messages
Programmable loop-back mode supporting self-test operation
3 programmable mask registers
Programmable transmit-first scheme: lowest ID or lowest buffer number
Time stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Independent of the transmission medium (an external transceiver is assumed)
High immunity to EMI
Short latency time due to an arbitration scheme for high-priority messages
Transmit features
— Supports configuration of multiple mailboxes to form message queues of scalable depth
— Arbitration scheme according to message ID or message buffer number
— Internal arbitration to guarantee no inner or outer priority inversion
— Transmit abort procedure and notification
Receive features
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
15
Introduction
•
— Individual programmable filters for each mailbox
— 8 mailboxes configurable as a 6-entry receive FIFO
— 8 programmable acceptance filters for receive FIFO
Programmable clock source
— System clock
— Direct oscillator clock to avoid FMPLL jitter
1.5.27
FlexRay
The FlexRay module provides the following features:
•
•
•
•
•
•
•
•
•
Full implementation of FlexRay Protocol Specification 2.1 Rev. A
64 configurable message buffers can be handled
Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate
Message buffers configurable as transmit or receive
Message buffer size configurable
Message filtering for all message buffers based on Frame ID, cycle count, and message ID
Programmable acceptance filters for receive FIFO
Message buffer header, status, and payload data stored in system memory (SRAM)
Internal FlexRay memories have error detection and correction
1.5.28
Serial communication interface module (LINFlexD)
The LINFlexD module (LINFlex with DMA support) on this device features the following:
•
•
•
•
•
•
Supports LIN Master mode, LIN Slave mode and UART mode
LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications
Manages LIN frame transmission and reception without CPU intervention
LIN features
— Autonomous LIN frame handling
— Message buffer to store as many as 8 data bytes
— Supports messages as long as 64 bytes
— Detection and flagging of LIN errors (Sync field, delimiter, ID parity, bit framing, checksum and Time-out errors)
— Classic or extended checksum calculation
— Configurable break duration of up to 50-bit times
— Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)
— Diagnostic features (Loop back, LIN bus stuck dominant detection)
— Interrupt driven operation with 16 interrupt sources
LIN slave mode features
— Autonomous LIN header handling
— Autonomous LIN response handling
UART mode
— Full-duplex operation
— Standard non return-to-zero (NRZ) mark/space format
— Data buffers with 4-byte receive, 4-byte transmit
— Configurable word length (8-bit, 9-bit, 16-bit, or 17-bit words)
— Configurable parity scheme: none, odd, even, always 0
— Speed as fast as 2 Mbit/s
MPC5643L Microcontroller Data Sheet, Rev. 10
16
NXP Semiconductors
Introduction
•
— Error detection and flagging (Parity, Noise and Framing errors)
— Interrupt driven operation with four interrupt sources
— Separate transmitter and receiver CPU interrupt sources
— 16-bit programmable baud-rate modulus counter and 16-bit fractional
— Two receiver wake-up methods
Support for DMA enabled transfers
1.5.29
Deserial Serial Peripheral Interface (DSPI)
The DSPI modules provide a synchronous serial interface for communication between the MPC5643L and external devices.
A DSPI module provides these features:
•
•
•
•
•
•
•
•
•
•
•
•
•
Full duplex, synchronous transfers
Master or slave operation
Programmable master bit rates
Programmable clock polarity and phase
End-of-transmission interrupt flag
Programmable transfer baud rate
Programmable data frames from 4 to 16 bits
As many as 8 chip select lines available, depending on package and pin multiplexing
4 clock and transfer attributes registers
Chip select strobe available as alternate function on one of the chip select pins for de-glitching
FIFOs for buffering as many as 5 transfers on the transmit and receive side
Queueing operation possible through use of the eDMA
General purpose I/O functionality on pins when not used for SPI
1.5.30
FlexPWM
The pulse width modulator module (FlexPWM) contains four PWM channels, each of which is configured to control a single
half-bridge power stage. Two modules are included on 257 MAPBGA devices; on the 144 LQFP package, only one module is
present. Additionally, four fault input channels are provided per FlexPWM module.
This PWM is capable of controlling most motor types, including:
•
•
•
•
•
AC induction motors (ACIM)
Permanent Magnet AC motors (PMAC)
Brushless (BLDC) and brush DC motors (BDC)
Switched (SRM) and variable reluctance motors (VRM)
Stepper motors
A FlexPWM module implements the following features:
•
•
•
•
•
•
•
16 bits of resolution for center, edge aligned, and asymmetrical PWMs
Maximum operating frequency as high as 120 MHz
— Clock source not modulated and independent from system clock (generated via secondary FMPLL)
Fine granularity control for enhanced resolution of the PWM period
PWM outputs can operate as complementary pairs or independent channels
Ability to accept signed numbers for PWM generation
Independent control of both edges of each PWM output
Synchronization to external hardware or other PWM supported
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
17
Introduction
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Double buffered PWM registers
— Integral reload rates from 1 to 16
— Half cycle reload capability
Multiple ADC trigger events can be generated per PWM cycle via hardware
Fault inputs can be assigned to control multiple PWM outputs
Programmable filters for fault inputs
Independently programmable PWM output polarity
Independent top and bottom deadtime insertion
Each complementary pair can operate with its own PWM frequency and deadtime values
Individual software control for each PWM output
All outputs can be forced to a value simultaneously
PWMX pin can optionally output a third signal from each channel
Channels not used for PWM generation can be used for buffered output compare functions
Channels not used for PWM generation can be used for input capture functions
Enhanced dual edge capture functionality
Option to supply the source for each complementary PWM signal pair from any of the following:
— External digital pin
— Internal timer channel
— External ADC input, taking into account values set in ADC high- and low-limit registers
DMA support
1.5.31
eTimer module
The MPC5643L provides three eTimer modules (on the LQFP package eTimer_2 is available internally only without any
external I/O access). Six 16-bit general purpose up/down timer/counters per module are implemented with the following
features:
•
•
•
•
•
•
•
•
•
•
•
Maximum clock frequency of 120 MHz
Individual channel capability
— Input capture trigger
— Output compare
— Double buffer (to capture rising edge and falling edge)
— Separate prescaler for each counter
— Selectable clock source
— 0–100% pulse measurement
— Rotation direction flag (Quad decoder mode)
Maximum count rate
— Equals peripheral clock divided by 2 for external event counting
— Equals peripheral clock for internal clock counting
Cascadeable counters
Programmable count modulo
Quadrature decode capabilities
Counters can share available input pins
Count once or repeatedly
Preloadable counters
Pins available as GPIO when timer functionality not in use
DMA support
MPC5643L Microcontroller Data Sheet, Rev. 10
18
NXP Semiconductors
Introduction
1.5.32
Sine Wave Generator (SWG)
A digital-to-analog converter is available to generate a sine wave based on 32 stored values for external devices (ex: resolver).
1.5.33
Analog-to-Digital Converter module (ADC)
The ADC module features include:
Analog part:
•
2 on-chip ADCs
— 12-bit resolution SAR architecture
— Same digital interface as in the MPC5604P family
— A/D Channels: 9 external, 3 internal and 4 shared with other A/D (total 16 channels)
— One channel dedicated to each T-sensor to enable temperature reading during application
— Separated reference for each ADC
— Shared analog supply voltage for both ADCs
— One sample and hold unit per ADC
— Adjustable sampling and conversion time
Digital part:
•
•
•
•
•
4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in
the appropriate ADC result location
2 modes of operation: CPU Mode or CTU Mode
CPU mode features
— Register based interface with the CPU: one result register per channel
— ADC state machine managing three request flows: regular command, hardware injected command, software
injected command
— Selectable priority between software and hardware injected commands
— 4 analog watchdogs comparing ADC results against predefined levels (low, high, range)
— DMA compatible interface
CTU mode features
— Triggered mode only
— 4 independent result queues (1 × 16 entries, 2 × 8 entries, 1 × 4 entries)
— Result alignment circuitry (left justified; right justified)
— 32-bit read mode allows to have channel ID on one of the 16-bit parts
— DMA compatible interfaces
Built-in self-test features triggered by software
1.5.34
Cross Triggering Unit (CTU)
The ADC cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without
CPU load during the PWM period and with minimized CPU load for dynamic configuration.
The CTU implements the following features:
•
•
•
•
•
Cross triggering between ADC, FlexPWM, eTimer, and external pins
Double buffered trigger generation unit with as many as 8 independent triggers generated from external triggers
Maximum operating frequency less than or equal to 120 MHz
Trigger generation unit configurable in sequential mode or in triggered mode
Trigger delay unit to compensate the delay of external low pass filter
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
19
Introduction
•
•
•
•
•
•
Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation
Double buffered ADC command list pointers to minimize ADC-trigger unit update
Double buffered ADC conversion command list with as many as 24 ADC commands
Each trigger capable of generating consecutive commands
ADC conversion command allows control of ADC channel from each ADC, single or synchronous sampling,
independent result queue selection
DMA support with safety features
1.5.35
Cyclic Redundancy Checker (CRC) Unit
The CRC module is a configurable multiple data flow unit to compute CRC signatures on data written to its input register.
The CRC unit has the following features:
•
•
•
•
•
•
3 sets of registers to allow 3 concurrent contexts with possibly different CRC computations, each with a selectable
polynomial and seed
Computes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores result in internal register.
The following standard CRC polynomials are implemented:
— x8 + x4 + x3 + x2 + 1 [8-bit CRC]
— x16 + x12 + x5 + 1 [16-bit CRC-CCITT]
— x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
[32-bit CRC-ethernet(32)]
Key engine to be coupled with communication periphery where CRC application is added to allow implementation of
safe communication protocol
Offloads core from cycle-consuming CRC and helps checking configuration signature for safe start-up or periodic
procedures
CRC unit connected as peripheral bus on internal peripheral bus
DMA support
1.5.36
Redundancy Control and Checker Unit (RCCU)
The RCCU checks all outputs of the sphere of replication (addresses, data, control signals). It has the following features:
•
•
Duplicated module to guarantee highest possible diagnostic coverage (check of checker)
Multiple times replicated IPs are used as checkers on the SoR outputs
1.5.37
Junction temperature sensor
The junction temperature sensor provides a value via an ADC channel that can be used by software to calculate the device
junction temperature.
The key parameters of the junction temperature sensor include:
•
•
Nominal temperature range from –40 to 150 °C
Software temperature alarm via analog ADC comparator possible
1.5.38
Nexus Port Controller (NPC)
The NPC module provides real-time development support capabilities for this device in compliance with the IEEE-ISTO
5001-2003. This development support is supplied for MCUs without requiring external address and data pins for internal
visibility.
MPC5643L Microcontroller Data Sheet, Rev. 10
20
NXP Semiconductors
Introduction
The NPC block interfaces to the host processor and internal buses to provide development support as per the IEEE-ISTO
5001-2003 Class 3+, including selected features from Class 4 standard.
The development support provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the
MCUs internal memory map and access to the Power Architecture internal registers during halt. The Nexus interface also
supports a JTAG only mode using only the JTAG pins. The following features are implemented:
•
Full and reduced port modes
•
MCKO (message clock out) pin
•
4 or 12 MDO (message data out) pins1
•
2 MSEO (message start/end out) pins
•
EVTO (event out) pin
— Auxiliary input port
•
EVTI (event in) pin
•
5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)
— Supports JTAG mode
•
Host processor (e200) development support features
— Data trace via data write messaging (DWM) and data read messaging (DRM). This allows the development tool
to trace reads or writes, or both, to selected internal memory resources.
— Ownership trace via ownership trace messaging (OTM). OTM facilitates ownership trace by providing visibility
of which process ID or operating system task is activated. An ownership trace message is transmitted when a
new process/task is activated, allowing development tools to trace ownership flow.
— Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities
(direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what
transpires between the discontinuities. Thus, static code may be traced.
— Watchpoint messaging (WPM) via the auxiliary port
— Watchpoint trigger enable of program and/or data trace messaging
— Data tracing of instruction fetches via private opcodes
1.5.39
IEEE 1149.1 JTAG Controller (JTAGC)
The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic
when not in test mode. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block
is compliant with the IEEE standard.
The JTAG controller provides the following features:
•
•
•
IEEE Test Access Port (TAP) interface with 5 pins:
— TDI
— TMS
— TCK
— TDO
— JCOMP
Selectable modes of operation include JTAGC/debug or normal system operation
5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:
— BYPASS
— IDCODE
1. 4 MDO pins on 144 LQFP package, 12 MDO pins on 257 MAPBGA package.
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
21
Introduction
•
•
— EXTEST
— SAMPLE
— SAMPLE/PRELOAD
3 test data registers: a bypass register, a boundary scan register, and a device identification register. The size of the
boundary scan register is parameterized to support a variety of boundary scan chain lengths.
TAP controller state machine that controls the operation of the data registers, instruction register and associated
circuitry
1.5.40
Voltage regulator / Power Management Unit (PMU)
The on-chip voltage regulator module provides the following features:
•
•
•
•
Single external rail required
Single high supply required: nominal 3.3 V both for packaged and Known Good Die option
— Packaged option requires external ballast transistor due to reduced dissipation capacity at high temperature but
can use embedded transistor if power dissipation is maintained within package dissipation capacity (lower
frequency of operation)
— Known Good Die option uses embedded ballast transistor as dissipation capacity is increased to reduce system
cost
All I/Os are at same voltage as external supply (3.3 V nominal)
Duplicated Low-Voltage Detectors (LVD) to guarantee proper operation at all stages (reset, configuration, normal
operation) and, to maximize safety coverage, one LVD can be tested while the other operates (on-line self-testing
feature)
1.5.41
Built-In Self-Test (BIST) capability
This device includes the following protection against latent faults:
•
•
•
•
Boot-time Memory Built-In Self-Test (MBIST)
Boot-time scan-based Logic Built-In Self-Test (LBIST)
Run-time ADC Built-In Self-Test (BIST)
Run-time Built-In Self Test of LVDs
MPC5643L Microcontroller Data Sheet, Rev. 10
22
NXP Semiconductors
Package pinouts and signal descriptions
2
Package pinouts and signal descriptions
2.1
Package pinouts
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144 LQFP package
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
A[4]
VPP_TEST
F[12]
D[14]
G[3]
C[14]
G[2]
C[13]
G[4]
D[12]
G[6]
VDD_HV_FLA
VSS_HV_FLA
VDD_HV_REG_1
VSS_LV_COR
VDD_LV_COR
A[3]
VDD_HV_IO
VSS_HV_IO
B[4]
TCK
TMS
B[5]
G[5]
A[2]
G[7]
C[12]
G[8]
C[11]
G[9]
D[11]
G[10]
D[10]
G[11]
A[1]
A[0]
D[7]
FCCU_F[0]
VDD_LV_COR
VSS_LV_COR
C[1]
E[4]
B[7]
E[5]
C[2]
E[6]
B[8]
E[7]
E[2]
VDD_HV_ADR0
VSS_HV_ADR0
B[9]
B[10]
B[11]
B[12]
VDD_HV_ADR1
VSS_HV_ADR1
VDD_HV_ADV
VSS_HV_ADV
B[13]
E[9]
B[15]
E[10]
B[14]
E[11]
C[0]
E[12]
E[0]
BCTRL
VDD_LV_COR
VSS_LV_COR
VDD_HV_PMU
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NMI
A[6]
D[1]
F[4]
F[5]
VDD_HV_IO
VSS_HV_IO
F[6]
MDO0
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
VDD_HV_REG_0
VSS_LV_COR
VDD_LV_COR
F[7]
F[8]
VDD_HV_IO
VSS_HV_IO
F[9]
F[10]
F[11]
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
D[5]
D[6]
VSS_LV_PLL0_PLL1
VDD_LV_PLL0_PLL1
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
A[15]
A[14]
C[6]
FCCU_F[1]
D[2]
F[3]
B[6]
VSS_LV_COR
A[13]
VDD_LV_COR
A[9]
F[0]
VSS_LV_COR
VDD_LV_COR
VDD_HV_REG_2
D[4]
D[3]
VSS_HV_IO
VDD_HV_IO
D[0]
C[15]
JCOMP
A[12]
E[15]
A[11]
E[14]
A[10]
E[13]
B[3]
F[14]
B[2]
F[15]
F[13]
C[10]
B[1]
B[0]
Figure 2 shows the MPC5643L in the 144 LQFP package.
Figure 2. MPC5643L 144 LQFP pinout (top view)
Figure 3 shows the MPC5643L in the 257 MAPBGA package.
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
23
Package pinouts and signal descriptions
1
A
C
_IO
VSS_HV VSS_HV
_IO
_IO
VDD_HV
NC1
_IO
D
3
VSS_HV VSS_HV VDD_HV
_IO
B
2
F[5]
F[4]
4
H[2]
5
6
7
8
9
10
11
12
13
14
15
H[0]
G[14]
D[3]
C[15]
VDD_HV
A[12]
H[10]
H[14]
A[10]
B[2]
C[10]
VSS_HV VSS_HV
B[0]
VDD_HV VSS_HV
_IO
B[6]
_IO
A[14]
F[3]
A[9]
VSS_HV FCCU_
F[1]
_IO
A[15]
C[6]
E
MDO0
F[6]
D[1]
NMI
F
H[1]
G[12]
A[7]
A[8]
D[2]
A[13]
VDD_HV
C[5]
VSS_LV_ VDD_LV_
G[13]
VSS_HV
F[7]
G[15]
F[9]
F[8]
L
F[10]
F[11]
M
VDD_HV VDD_HV
_OSC
N
XTAL
VSS_HV
RESET
T
EXTAL
VSS_HV VDD_HV
_IO
U
1
FCCU
_F[0]
F[13]
I[0]
JCOMP
H[11]
I[1]
F[14]
COR
_IO
NC
A[11]
E[13]
F[15]
A[4]
F[12]
D[14]
G[3]
COR
COR
COR
COR
VPP
NC
C[14]
G[2]
I[3]
NC
C[13]
I[2]
G[4]
D[12]
H[13]
H[9]
G[6]
COR
VSS_LV
VSS_LV VDD_LV
VSS_LV
VDD_LV VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV VDD_LV
VDD_LV
C[7]
VDD_LV VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV VDD_LV
D[9]
NC
VDD_LV VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV VDD_LV
D[8]
NC
VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV
D[5]
VSS_LV_
_REG_0
_IO
_TEST
VSS_LV
VDD_HV VDD_HV
_IO
_IO
VSS_LV
A[5]
_IO
VDD_HV
VDD_LV VSS_LV
C[4]
COR
VSS_HV
17
_IO
VDD_HV VSS_HV
_IO
COR
B[1]
_REG_2
COR
COR
VDD_HV VDD_HV
_REG_1
H[6]
_FLA
VDD_HV VSS_HV
H[15]
_REG_1
_FLA
NC
H[8]
H[7]
A[3]
NC
TCK
H[4]
B[4]
C[11]
B[5]
TMS
H[5]
NC
C[12]
A[2]
G[5]
G[10]
G[8]
G[7]
VSS_HV
D[11]
G[9]
PLL
D[6]
_OSC
R
B[3]
COR
_IO
P
E[14]
COR
_IO
VSS_HV
F[0]
COR
COR
_REG_0
K
E[15]
VDD_LV_ VSS_LV_ VSS_LV_ VSS_LV_ VSS_LV_ VSS_LV_ VDD_LV_
A[6]
_IO
J
H[12]
VDD_LV_ VDD_LV_ VDD_LV_ VDD_LV_ VDD_LV_ VDD_LV_ VDD_LV_
_IO
H
VDD_HV VDD_HV
_REG_2
COR
H[3]
D[0]
_IO
_IO
COR
G
D[4]
VSS_HV
16
VSS_HV
VDD_LV_ VDD_LV_ VSS_LV_
PLL
COR
COR
D[7]
B[7]
E[6]
_IO
NC
B[8]
NC
_IO
VDD_HV
B[10]
_ADR0
C[1]
E[5]
E[7]
_IO
VSS_HV
_IO
_IO
NC
1
2
3
E[4]
4
C[2]
5
E[2]
6
B[9]
7
VDD_HV
B[14]
_IO
B[13]
B[15]
VDD_LV_ VSS_LV_ VDD_HV
COR
COR
_IO
C[0]
BCTRL
A[1]
_ADR1
B[11]
_ADR0
VSS_HV VSS_HV
VSS_HV VDD_HV
VSS_HV
_IO
E[9]
E[10]
E[12]
E[0]
A[0]
D[10]
_ADR1
B[12]
8
VDD_HV VSS_HV
_IO
VDD_HV VSS_HV
_ADV
_ADV
9
10
E[11]
NC
NC
VDD_HV
G[11]
_PMU
11
12
13
14
15
_IO
VSS_HV VSS_HV
_IO
_IO
16
17
NC = Not connected (the pin is physically not connected to anything on the device)
Figure 3. MPC5643L 257 MAPBGA pinout (top view)
Table 3 and Table 4 provide the pin function summaries for the 144-pin and 257-pin packages, respectively, listing all the
signals multiplexed to each pin.
MPC5643L Microcontroller Data Sheet, Rev. 10
24
NXP Semiconductors
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary
Pin #
Port/function
1
NMI
2
A[6]
3
4
5
Peripheral
Output function
—
D[1]
F[4]
F[5]
SIUL
GPIO[6]
GPIO[6]
DSPI_1
SCK
SCK
SIUL
—
EIRQ[6]
SIUL
GPIO[49]
GPIO[49]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
FlexRay
—
CA_RX
SIUL
GPIO[84]
GPIO[84]
NPC
MDO[3]
—
SIUL
GPIO[85]
GPIO[85]
NPC
MDO[2]
—
6
VDD_HV_IO
—
7
VSS_HV_IO
—
8
F[6]
9
MDO0
10
A[7]
11
12
13
C[4]
A[8]
C[5]
Input function
SIUL
GPIO[86]
GPIO[86]
NPC
MDO[1]
—
—
SIUL
GPIO[7]
GPIO[7]
DSPI_1
SOUT
—
SIUL
—
EIRQ[7]
SIUL
GPIO[36]
GPIO[36]
DSPI_0
CS0
CS0
FlexPWM_0
X[1]
X[1]
SSCM
DEBUG[4]
—
SIUL
—
EIRQ[22]
SIUL
GPIO[8]
GPIO[8]
DSPI_1
—
SIN
SIUL
—
EIRQ[8]
SIUL
GPIO[37]
GPIO[37]
DSPI_0
SCK
SCK
SSCM
DEBUG[5]
—
FlexPWM_0
—
FAULT[3]
SIUL
—
EIRQ[23]
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
25
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
14
A[5]
SIUL
GPIO[5]
GPIO[5]
DSPI_1
CS0
CS0
eTimer_1
ETC[5]
ETC[5]
DSPI_0
CS7
—
SIUL
—
EIRQ[5]
SIUL
GPIO[39]
GPIO[39]
FlexPWM_0
A[1]
A[1]
SSCM
DEBUG[7]
—
DSPI_0
—
SIN
15
C[7]
16
VDD_HV_REG_0
—
17
VSS_LV_COR
—
18
VDD_LV_COR
—
19
F[7]
20
F[8]
SIUL
GPIO[87]
GPIO[87]
NPC
MCKO
—
SIUL
GPIO[88]
GPIO[88]
NPC
MSEO[1]
—
21
VDD_HV_IO
—
22
VSS_HV_IO
—
23
F[9]
24
25
26
F[10]
F[11]
D[9]
SIUL
GPIO[89]
GPIO[89]
NPC
MSEO[0]
—
SIUL
GPIO[90]
GPIO[90]
NPC
EVTO
—
SIUL
GPIO[91]
GPIO[91]
NPC
—
EVTI
SIUL
GPIO[57]
GPIO[57]
FlexPWM_0
X[0]
X[0]
LINFlexD_1
TXD
—
27
VDD_HV_OSC
—
28
VSS_HV_OSC
—
29
XTAL
—
30
EXTAL
—
31
RESET
—
MPC5643L Microcontroller Data Sheet, Rev. 10
26
NXP Semiconductors
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
32
D[8]
SIUL
GPIO[56]
GPIO[56]
DSPI_1
CS2
—
eTimer_1
ETC[4]
ETC[4]
DSPI_0
CS5
—
FlexPWM_0
—
FAULT[3]
SIUL
GPIO[53]
GPIO[53]
DSPI_0
CS3
—
FlexPWM_0
—
FAULT[2]
SIUL
GPIO[54]
GPIO[54]
DSPI_0
CS2
—
FlexPWM_0
X[3]
X[3]
FlexPWM_0
—
FAULT[1]
33
34
D[5]
D[6]
35
VSS_LV_PLL0_PLL1
—
36
VDD_LV_PLL0_PLL1
—
37
D[7]
SIUL
GPIO[55]
GPIO[55]
DSPI_1
CS3
—
DSPI_0
CS4
—
SWG
analog output
—
FCCU
F[0]
F[0]
38
FCCU_F[0]
39
VDD_LV_COR
—
40
VSS_LV_COR
—
41
C[1]
42
43
44
45
46
E[4]
B[7]
E[5]
C[2]
E[6]
SIUL
—
GPIO[33]
ADC_0
—
AN[2]
SIUL
—
GPIO[68]
ADC_0
—
AN[7]
SIUL
—
GPIO[23]
LINFlexD_0
—
RXD
ADC_0
—
AN[0]
SIUL
—
GPIO[69]
ADC_0
—
AN[8]
SIUL
—
GPIO[34]
ADC_0
—
AN[3]
SIUL
—
GPIO[70]
ADC_0
—
AN[4]
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
27
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
47
B[8]
SIUL
—
GPIO[24]
eTimer_0
—
ETC[5]
ADC_0
—
AN[1]
SIUL
—
GPIO[71]
ADC_0
—
AN[6]
SIUL
—
GPIO[66]
ADC_0
—
AN[5]
48
49
E[7]
E[2]
50
VDD_HV_ADR0
—
51
VSS_HV_ADR0
—
52
B[9]
53
54
55
B[10]
B[11]
B[12]
SIUL
—
GPIO[25]
ADC_0
ADC_1
—
AN[11]
SIUL
—
GPIO[26]
ADC_0
ADC_1
—
AN[12]
SIUL
—
GPIO[27]
ADC_0
ADC_1
—
AN[13]
SIUL
—
GPIO[28]
ADC_0
ADC_1
—
AN[14]
56
VDD_HV_ADR1
—
57
VSS_HV_ADR1
—
58
VDD_HV_ADV
—
59
VSS_HV_ADV
—
60
B[13]
61
62
63
E[9]
B[15]
E[10]
SIUL
—
GPIO[29]
LINFlexD_1
—
RXD
ADC_1
—
AN[0]
SIUL
—
GPIO[73]
ADC_1
—
AN[7]
SIUL
—
GPIO[31]
SIUL
—
EIRQ[20]
ADC_1
—
AN[2]
SIUL
—
GPIO[74]
ADC_1
—
AN[8]
MPC5643L Microcontroller Data Sheet, Rev. 10
28
NXP Semiconductors
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
64
B[14]
SIUL
—
GPIO[30]
eTimer_0
—
ETC[4]
SIUL
—
EIRQ[19]
ADC_1
—
AN[1]
SIUL
—
GPIO[75]
ADC_1
—
AN[4]
SIUL
—
GPIO[32]
ADC_1
—
AN[3]
SIUL
—
GPIO[76]
ADC_1
—
AN[6]
SIUL
—
GPIO[64]
ADC_1
—
AN[5]
65
66
67
68
E[11]
C[0]
E[12]
E[0]
69
BCTRL
—
70
VDD_LV_COR
—
71
VSS_LV_COR
—
72
VDD_HV_PMU
—
73
A[0]
74
75
76
77
A[1]
G[11]
D[10]
G[10]
SIUL
GPIO[0]
GPIO[0]
eTimer_0
ETC[0]
ETC[0]
DSPI_2
SCK
SCK
SIUL
—
EIRQ[0]
SIUL
GPIO[1]
GPIO[1]
eTimer_0
ETC[1]
ETC[1]
DSPI_2
SOUT
—
SIUL
—
EIRQ[1]
SIUL
GPIO[107]
GPIO[107]
FlexRay
DBG3
—
FlexPWM_0
—
FAULT[3]
SIUL
GPIO[58]
GPIO[58]
FlexPWM_0
A[0]
A[0]
eTimer_0
—
ETC[0]
SIUL
GPIO[106]
GPIO[106]
FlexRay
DBG2
—
DSPI_2
CS3
—
FlexPWM_0
—
FAULT[2]
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
29
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
78
D[11]
SIUL
GPIO[59]
GPIO[59]
FlexPWM_0
B[0]
B[0]
eTimer_0
—
ETC[1]
SIUL
GPIO[105]
GPIO[105]
FlexRay
DBG1
—
DSPI_1
CS1
—
FlexPWM_0
—
FAULT[1]
SIUL
—
EIRQ[29]
SIUL
GPIO[43]
GPIO[43]
eTimer_0
ETC[4]
ETC[4]
DSPI_2
CS2
—
SIUL
GPIO[104]
GPIO[104]
FlexRay
DBG0
—
DSPI_0
CS1
—
FlexPWM_0
—
FAULT[0]
SIUL
—
EIRQ[21]
SIUL
GPIO[44]
GPIO[44]
eTimer_0
ETC[5]
ETC[5]
DSPI_2
CS3
—
SIUL
GPIO[103]
GPIO[103]
FlexPWM_0
B[3]
B[3]
SIUL
GPIO[2]
GPIO[2]
eTimer_0
ETC[2]
ETC[2]
FlexPWM_0
A[3]
A[3]
DSPI_2
—
SIN
MC_RGM
—
ABS[0]
SIUL
—
EIRQ[2]
SIUL
GPIO[101]
GPIO[101]
FlexPWM_0
X[3]
X[3]
DSPI_2
CS3
—
SIUL
GPIO[21]
GPIO[21]
JTAGC
—
TDI
79
80
81
82
83
84
85
86
G[9]
C[11]
G[8]
C[12]
G[7]
A[2]
G[5]
B[5]
87
TMS
—
88
TCK
—
MPC5643L Microcontroller Data Sheet, Rev. 10
30
NXP Semiconductors
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
89
B[4]
SIUL
GPIO[20]
GPIO[20]
JTAGC
TDO
—
90
VSS_HV_IO
—
91
VDD_HV_IO
—
92
A[3]
SIUL
GPIO[3]
GPIO[3]
eTimer_0
ETC[3]
ETC[3]
DSPI_2
CS0
CS0
FlexPWM_0
B[3]
B[3]
MC_RGM
—
ABS[2]
SIUL
—
EIRQ[3]
93
VDD_LV_COR
—
94
VSS_LV_COR
—
95
VDD_HV_REG_1
—
96
VSS_HV_FLA
—
97
VDD_HV_FLA
—
98
G[6]
99
100
101
102
103
D[12]
G[4]
C[13]
G[2]
C[14]
SIUL
GPIO[102]
GPIO[102]
FlexPWM_0
A[3]
A[3]
SIUL
GPIO[60]
GPIO[60]
FlexPWM_0
X[1]
X[1]
LINFlexD_1
—
RXD
SIUL
GPIO[100]
GPIO[100]
FlexPWM_0
B[2]
B[2]
eTimer_0
—
ETC[5]
SIUL
GPIO[45]
GPIO[45]
eTimer_1
ETC[1]
ETC[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
SIUL
GPIO[98]
GPIO[98]
FlexPWM_0
X[2]
X[2]
DSPI_1
CS1
—
SIUL
GPIO[46]
GPIO[46]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
31
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
104
G[3]
SIUL
GPIO[99]
GPIO[99]
FlexPWM_0
A[2]
A[2]
eTimer_0
—
ETC[4]
SIUL
GPIO[62]
GPIO[62]
FlexPWM_0
B[1]
B[1]
eTimer_0
—
ETC[3]
SIUL
GPIO[92]
GPIO[92]
eTimer_1
ETC[3]
ETC[3]
SIUL
—
EIRQ[30]
105
106
D[14]
F[12]
107
VPP_TEST
108
A[4]
109
110
111
112
B[0]
B[1]
C[10]
F[13]
1
—
SIUL
GPIO[4]
GPIO[4]
eTimer_1
ETC[0]
ETC[0]
DSPI_2
CS1
—
eTimer_0
ETC[4]
ETC[4]
MC_RGM
—
FAB
SIUL
—
EIRQ[4]
SIUL
GPIO[16]
GPIO[16]
FlexCAN_0
TXD
—
eTimer_1
ETC[2]
ETC[2]
SSCM
DEBUG[0]
—
SIUL
—
EIRQ[15]
SIUL
GPIO[17]
GPIO[17]
eTimer_1
ETC[3]
ETC[3]
SSCM
DEBUG[1]
—
FlexCAN_0
—
RXD
FlexCAN_1
—
RXD
SIUL
—
EIRQ[16]
SIUL
GPIO[42]
GPIO[42]
DSPI_2
CS2
—
FlexPWM_0
A[3]
A[3]
FlexPWM_0
—
FAULT[1]
SIUL
GPIO[93]
GPIO[93]
eTimer_1
ETC[4]
ETC[4]
SIUL
—
EIRQ[31]
MPC5643L Microcontroller Data Sheet, Rev. 10
32
NXP Semiconductors
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
113
F[15]
SIUL
GPIO[95]
GPIO[95]
LINFlexD_1
—
RXD
SIUL
GPIO[18]
GPIO[18]
LINFlexD_0
TXD
—
SSCM
DEBUG[2]
—
SIUL
—
EIRQ[17]
SIUL
GPIO[94]
GPIO[94]
LINFlexD_1
TXD
—
SIUL
GPIO[19]
GPIO[19]
SSCM
DEBUG[3]
—
LINFlexD_0
—
RXD
SIUL
GPIO[77]
GPIO[77]
eTimer_0
ETC[5]
ETC[5]
DSPI_2
CS3
—
SIUL
—
EIRQ[25]
SIUL
GPIO[10]
GPIO[10]
DSPI_2
CS0
CS0
FlexPWM_0
B[0]
B[0]
FlexPWM_0
X[2]
X[2]
SIUL
—
EIRQ[9]
SIUL
GPIO[78]
GPIO[78]
eTimer_1
ETC[5]
ETC[5]
SIUL
—
EIRQ[26]
SIUL
GPIO[11]
GPIO[11]
DSPI_2
SCK
SCK
FlexPWM_0
A[0]
A[0]
FlexPWM_0
A[2]
A[2]
SIUL
—
EIRQ[10]
SIUL
GPIO[79]
GPIO[79]
DSPI_0
CS1
—
SIUL
—
EIRQ[27]
114
115
116
117
118
119
120
121
B[2]
F[14]
B[3]
E[13]
A[10]
E[14]
A[11]
E[15]
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
33
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
122
A[12]
SIUL
GPIO[12]
GPIO[12]
DSPI_2
SOUT
—
FlexPWM_0
A[2]
A[2]
FlexPWM_0
B[2]
B[2]
SIUL
—
EIRQ[11]
123
JCOMP
—
—
JCOMP
124
C[15]
SIUL
GPIO[47]
GPIO[47]
FlexRay
CA_TR_EN
—
eTimer_1
ETC[0]
ETC[0]
FlexPWM_0
A[1]
A[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
SIUL
GPIO[48]
GPIO[48]
FlexRay
CA_TX
—
eTimer_1
ETC[1]
ETC[1]
FlexPWM_0
B[1]
B[1]
125
D[0]
126
VDD_HV_IO
—
127
VSS_HV_IO
—
128
D[3]
129
D[4]
SIUL
GPIO[51]
GPIO[51]
FlexRay
CB_TX
—
eTimer_1
ETC[4]
ETC[4]
FlexPWM_0
A[3]
A[3]
SIUL
GPIO[52]
GPIO[52]
FlexRay
CB_TR_EN
—
eTimer_1
ETC[5]
ETC[5]
FlexPWM_0
B[3]
B[3]
130
VDD_HV_REG_2
—
131
VDD_LV_COR
—
132
VSS_LV_COR
—
133
F[0]
SIUL
GPIO[80]
GPIO[80]
FlexPWM_0
A[1]
A[1]
eTimer_0
—
ETC[2]
SIUL
—
EIRQ[28]
MPC5643L Microcontroller Data Sheet, Rev. 10
34
NXP Semiconductors
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
134
A[9]
SIUL
GPIO[9]
GPIO[9]
DSPI_2
CS1
—
FlexPWM_0
B[3]
B[3]
FlexPWM_0
—
FAULT[0]
135
VDD_LV_COR
136
A[13]
137
VSS_LV_COR
138
B[6]
139
140
F[3]
D[2]
—
SIUL
GPIO[13]
GPIO[13]
FlexPWM_0
B[2]
B[2]
DSPI_2
—
SIN
FlexPWM_0
—
FAULT[0]
SIUL
—
EIRQ[12]
—
SIUL
GPIO[22]
GPIO[22]
MC_CGM
clk_out
—
DSPI_2
CS2
—
SIUL
—
EIRQ[18]
SIUL
GPIO[83]
GPIO[83]
DSPI_0
CS6
—
SIUL
GPIO[50]
GPIO[50]
eTimer_1
ETC[3]
ETC[3]
FlexPWM_0
X[3]
X[3]
FlexRay
—
CB_RX
141
FCCU_F[1]
FCCU
F[1]
F[1]
142
C[6]
SIUL
GPIO[38]
GPIO[38]
DSPI_0
SOUT
—
FlexPWM_0
B[1]
B[1]
SSCM
DEBUG[6]
—
SIUL
—
EIRQ[24]
SIUL
GPIO[14]
GPIO[14]
FlexCAN_1
TXD
—
eTimer_1
ETC[4]
ETC[4]
SIUL
—
EIRQ[13]
143
A[14]
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
35
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
1
Pin #
Port/function
Peripheral
Output function
Input function
144
A[15]
SIUL
GPIO[15]
GPIO[15]
eTimer_1
ETC[5]
ETC[5]
FlexCAN_1
—
RXD
FlexCAN_0
—
RXD
SIUL
—
EIRQ[14]
VPP_TEST should always be tied to ground (VSS) for normal operations.
Table 4. 257 MAPBGA pin function summary
Pin #
Port/function
A1
VSS_HV_IO_RING
—
A2
VSS_HV_IO_RING
—
A3
VDD_HV_IO_RING
—
A4
H[2]
A5
A6
A7
A8
H[0]
G[14]
D[3]
C[15]
A9
VDD_HV_IO_RING
A10
A[12]
Peripheral
Output function
Input function
SIUL
GPIO[114]
GPIO[114]
NPC
MDO[5]
—
SIUL
GPIO[112]
GPIO[112]
NPC
MDO[7]
—
SIUL
GPIO[110]
GPIO[110]
NPC
MDO[9]
—
SIUL
GPIO[51]
GPIO[51]
FlexRay
CB_TX
—
eTimer_1
ETC[4]
ETC[4]
FlexPWM_0
A[3]
A[3]
SIUL
GPIO[47]
GPIO[47]
FlexRay
CA_TR_EN
—
eTimer_1
ETC[0]
ETC[0]
FlexPWM_0
A[1]
A[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
—
SIUL
GPIO[12]
GPIO[12]
DSPI_2
SOUT
—
FlexPWM_0
A[2]
A[2]
FlexPWM_0
B[2]
B[2]
SIUL
—
EIRQ[11]
MPC5643L Microcontroller Data Sheet, Rev. 10
36
NXP Semiconductors
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
A11
H[10]
SIUL
GPIO[122]
GPIO[122]
FlexPWM_1
X[2]
X[2]
eTimer_2
ETC[2]
ETC[2]
SIUL
GPIO[126]
GPIO[126]
FlexPWM_1
A[3]
A[3]
eTimer_2
ETC[4]
ETC[4]
SIUL
GPIO[10]
GPIO[10]
DSPI_2
CS0
CS0
FlexPWM_0
B[0]
B[0]
FlexPWM_0
X[2]
X[2]
SIUL
—
EIRQ[9]
SIUL
GPIO[18]
GPIO[18]
LINFlexD_0
TXD
—
SSCM
DEBUG[2]
—
SIUL
—
EIRQ[17]
SIUL
GPIO[42]
GPIO[42]
DSPI_2
CS2
—
FlexPWM_0
A[3]
A[3]
FlexPWM_0
—
FAULT[1]
A12
A13
A14
A15
H[14]
A[10]
B[2]
C[10]
A16
VSS_HV_IO_RING
—
A17
VSS_HV_IO_RING
—
B1
VSS_HV_IO_RING
—
B2
VSS_HV_IO_RING
—
B3
B[6]
B4
B5
A[14]
F[3]
SIUL
GPIO[22]
GPIO[22]
MC_CGM
clk_out
—
DSPI_2
CS2
—
SIUL
—
EIRQ[18]
SIUL
GPIO[14]
GPIO[14]
FlexCAN_1
TXD
—
eTimer_1
ETC[4]
ETC[4]
SIUL
—
EIRQ[13]
SIUL
GPIO[83]
GPIO[83]
DSPI_0
CS6
—
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
37
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
B6
A[9]
SIUL
GPIO[9]
GPIO[9]
DSPI_2
CS1
—
FlexPWM_0
B[3]
B[3]
FlexPWM_0
—
FAULT[0]
SIUL
GPIO[52]
GPIO[52]
FlexRay
CB_TR_EN
—
eTimer_1
ETC[5]
ETC[5]
FlexPWM_0
B[3]
B[3]
SIUL
GPIO[48]
GPIO[48]
FlexRay
CA_TX
—
eTimer_1
ETC[1]
ETC[1]
FlexPWM_0
B[1]
B[1]
B7
B8
D[4]
D[0]
B9
VSS_HV_IO_RING
B10
H[12]
B11
B12
B13
B14
B15
E[15]
E[14]
B[3]
F[13]
B[0]
—
SIUL
GPIO[124]
GPIO[124]
FlexPWM_1
B[2]
B[2]
SIUL
GPIO[79]
GPIO[79]
DSPI_0
CS1
—
SIUL
—
EIRQ[27]
SIUL
GPIO[78]
GPIO[78]
eTimer_1
ETC[5]
ETC[5]
SIUL
—
EIRQ[26]
SIUL
GPIO[19]
GPIO[19]
SSCM
DEBUG[3]
—
LINFlexD_0
—
RXD
SIUL
GPIO[93]
GPIO[93]
eTimer_1
ETC[4]
ETC[4]
SIUL
—
EIRQ[31]
SIUL
GPIO[16]
GPIO[16]
FlexCAN_0
TXD
—
eTimer_1
ETC[2]
ETC[2]
SSCM
DEBUG[0]
—
SIUL
—
EIRQ[15]
B16
VDD_HV_IO_RING
—
B17
VSS_HV_IO_RING
—
C1
VDD_HV_IO_RING
—
MPC5643L Microcontroller Data Sheet, Rev. 10
38
NXP Semiconductors
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
C2
Not connected
—
C3
VSS_HV_IO_RING
—
C4
FCCU_F[1]
FCCU
F[1]
F[1]
C5
D[2]
SIUL
GPIO[50]
GPIO[50]
eTimer_1
ETC[3]
ETC[3]
FlexPWM_0
X[3]
X[3]
FlexRay
—
CB_RX
SIUL
GPIO[13]
GPIO[13]
FlexPWM_0
B[2]
B[2]
DSPI_2
—
SIN
FlexPWM_0
—
FAULT[0]
SIUL
—
EIRQ[12]
C6
A[13]
Peripheral
Output function
C7
VDD_HV_REG_2
—
C8
VDD_HV_REG_2
—
C9
I[0]
Input function
SIUL
GPIO[128]
GPIO[128]
eTimer_2
ETC[0]
ETC[0]
DSPI_0
CS4
—
FlexPWM_1
—
FAULT[0]
C10
JCOMP
—
—
JCOMP
C11
H[11]
SIUL
GPIO[123]
GPIO[123]
FlexPWM_1
A[2]
A[2]
SIUL
GPIO[129]
GPIO[129]
eTimer_2
ETC[1]
ETC[1]
DSPI_0
CS5
—
FlexPWM_1
—
FAULT[1]
SIUL
GPIO[94]
GPIO[94]
LINFlexD_1
TXD
—
SIUL
GPIO[17]
GPIO[17]
eTimer_1
ETC[3]
ETC[3]
SSCM
DEBUG[1]
—
FlexCAN_0
—
RXD
FlexCAN_1
—
RXD
SIUL
—
EIRQ[16]
C12
C13
C14
C15
I[1]
F[14]
B[1]
VSS_HV_IO_RING
—
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
39
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
C16
A[4]
SIUL
GPIO[4]
GPIO[4]
eTimer_1
ETC[0]
ETC[0]
DSPI_2
CS1
—
eTimer_0
ETC[4]
ETC[4]
MC_RGM
—
FAB
SIUL
—
EIRQ[4]
SIUL
GPIO[92]
GPIO[92]
eTimer_1
ETC[3]
ETC[3]
SIUL
—
EIRQ[30]
SIUL
GPIO[85]
GPIO[85]
NPC
MDO[2]
—
SIUL
GPIO[84]
GPIO[84]
NPC
MDO[3]
—
SIUL
GPIO[15]
GPIO[15]
eTimer_1
ETC[5]
ETC[5]
FlexCAN_1
—
RXD
FlexCAN_0
—
RXD
SIUL
—
EIRQ[14]
SIUL
GPIO[38]
GPIO[38]
DSPI_0
SOUT
—
FlexPWM_0
B[1]
B[1]
SSCM
DEBUG[6]
—
SIUL
—
EIRQ[24]
C17
D1
D2
D3
D4
F[12]
F[5]
F[4]
A[15]
C[6]
D5
VSS_LV_CORE_RING
—
D6
VDD_LV_CORE_RING
—
D7
F[0]
SIUL
GPIO[80]
GPIO[80]
FlexPWM_0
A[1]
A[1]
eTimer_0
—
ETC[2]
SIUL
—
EIRQ[28]
D8
VDD_HV_IO_RING
—
D9
VSS_HV_IO_RING
—
D10
Not connected
—
MPC5643L Microcontroller Data Sheet, Rev. 10
40
NXP Semiconductors
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
D11
A[11]
SIUL
GPIO[11]
GPIO[11]
DSPI_2
SCK
SCK
FlexPWM_0
A[0]
A[0]
FlexPWM_0
A[2]
A[2]
SIUL
—
EIRQ[10]
SIUL
GPIO[77]
GPIO[77]
eTimer_0
ETC[5]
ETC[5]
DSPI_2
CS3
—
SIUL
—
EIRQ[25]
SIUL
GPIO[95]
GPIO[95]
LINFlexD_1
—
RXD
D12
D13
D14
E[13]
F[15]
D15
VPP_TEST
D16
D[14]
D17
1
G[3]
E1
MDO0
E2
F[6]
E3
—
VDD_HV_IO_RING
—
SIUL
GPIO[62]
GPIO[62]
FlexPWM_0
B[1]
B[1]
eTimer_0
—
ETC[3]
SIUL
GPIO[99]
GPIO[99]
FlexPWM_0
A[2]
A[2]
eTimer_0
—
ETC[4]
—
D[1]
SIUL
GPIO[86]
GPIO[86]
NPC
MDO[1]
—
SIUL
GPIO[49]
GPIO[49]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
FlexRay
—
CA_RX
E4
NMI
—
E14
Not connected
—
E15
C[14]
E16
G[2]
SIUL
GPIO[46]
GPIO[46]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
SIUL
GPIO[98]
GPIO[98]
FlexPWM_0
X[2]
X[2]
DSPI_1
CS1
—
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
41
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
E17
I[3]
SIUL
GPIO[131]
GPIO[131]
eTimer_2
ETC[3]
ETC[3]
DSPI_0
CS7
—
CTU_0
EXT_TGR
—
FlexPWM_1
—
FAULT[3]
SIUL
GPIO[113]
GPIO[113]
NPC
MDO[6]
—
SIUL
GPIO[108]
GPIO[108]
NPC
MDO[11]
—
SIUL
GPIO[7]
GPIO[7]
DSPI_1
SOUT
—
SIUL
—
EIRQ[7]
SIUL
GPIO[8]
GPIO[8]
DSPI_1
—
SIN
SIUL
—
EIRQ[8]
F1
F2
F3
F4
H[1]
G[12]
A[7]
A[8]
F6
VDD_LV_CORE_RING
—
F7
VDD_LV_CORE_RING
—
F8
VDD_LV_CORE_RING
—
F9
VDD_LV_CORE_RING
—
F10
VDD_LV_CORE_RING
—
F11
VDD_LV_CORE_RING
—
F12
VDD_LV_CORE_RING
—
F14
Not connected
—
F15
C[13]
F16
F17
I[2]
G[4]
SIUL
GPIO[45]
GPIO[45]
eTimer_1
ETC[1]
ETC[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
SIUL
GPIO[130]
GPIO[130]
eTimer_2
ETC[2]
ETC[2]
DSPI_0
CS6
—
FlexPWM_1
—
FAULT[2]
SIUL
GPIO[100]
GPIO[100]
FlexPWM_0
B[2]
B[2]
eTimer_0
—
ETC[5]
MPC5643L Microcontroller Data Sheet, Rev. 10
42
NXP Semiconductors
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
G1
H[3]
SIUL
GPIO[115]
GPIO[115]
NPC
MDO[4]
—
G2
VDD_HV_IO_RING
G3
C[5]
G4
A[6]
—
SIUL
GPIO[37]
GPIO[37]
DSPI_0
SCK
SCK
SSCM
DEBUG[5]
—
FlexPWM_0
—
FAULT[3]
SIUL
—
EIRQ[23]
SIUL
GPIO[6]
GPIO[6]
DSPI_1
SCK
SCK
SIUL
—
EIRQ[6]
G6
VDD_LV_CORE_RING
—
G7
VSS_LV_CORE_RING
—
G8
VSS_LV_CORE_RING
—
G9
VSS_LV_CORE_RING
—
G10
VSS_LV_CORE_RING
—
G11
VSS_LV_CORE_RING
—
G12
VDD_LV_CORE_RING
—
G14
D[12]
G15
G16
G17
H1
H2
H[13]
H[9]
G[6]
G[13]
VSS_HV_IO_RING
SIUL
GPIO[60]
GPIO[60]
FlexPWM_0
X[1]
X[1]
LINFlexD_1
—
RXD
SIUL
GPIO[125]
GPIO[125]
FlexPWM_1
X[3]
X[3]
eTimer_2
ETC[3]
ETC[3]
SIUL
GPIO[121]
GPIO[121]
FlexPWM_1
B[1]
B[1]
DSPI_0
CS7
—
SIUL
GPIO[102]
GPIO[102]
FlexPWM_0
A[3]
A[3]
SIUL
GPIO[109]
GPIO[109]
NPC
MDO[10]
—
—
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
43
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
H3
C[4]
SIUL
GPIO[36]
GPIO[36]
DSPI_0
CS0
CS0
FlexPWM_0
X[1]
X[1]
SSCM
DEBUG[4]
—
SIUL
—
EIRQ[22]
SIUL
GPIO[5]
GPIO[5]
DSPI_1
CS0
CS0
eTimer_1
ETC[5]
ETC[5]
DSPI_0
CS7
—
SIUL
—
EIRQ[5]
H4
A[5]
H6
VDD_LV
—
H7
VSS_LV
—
H8
VSS_LV
—
H9
VSS_LV
—
H10
VSS_LV
—
H11
VSS_LV
—
H12
VDD_LV
—
H14
VSS_LV
—
H15
VDD_HV_REG_1
—
H16
VDD_HV_FLA
—
H17
H[6]
J1
J2
F[7]
G[15]
SIUL
GPIO[118]
GPIO[118]
FlexPWM_1
B[0]
B[0]
DSPI_0
CS5
—
SIUL
GPIO[87]
GPIO[87]
NPC
MCKO
—
SIUL
GPIO[111]
GPIO[111]
NPC
MDO[8]
—
J3
VDD_HV_REG_0
—
J4
VDD_HV_REG_0
—
J6
VDD_LV
—
J7
VSS_LV
—
J8
VSS_LV
—
J9
VSS_LV
—
J10
VSS_LV
—
J11
VSS_LV
—
MPC5643L Microcontroller Data Sheet, Rev. 10
44
NXP Semiconductors
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
J12
VDD_LV
—
J14
VDD_LV
—
J15
VDD_HV_REG_1
—
J16
VSS_HV_FLA
—
J17
H[15]
K1
K2
K3
K4
F[9]
F[8]
RDY
C[7]
Peripheral
Output function
SIUL
GPIO[127]
GPIO[127]
FlexPWM_1
B[3]
B[3]
eTimer_2
ETC[5]
ETC[5]
SIUL
GPIO[89]
GPIO[89]
NPC
MSEO[0]
—
SIUL
GPIO[88]
GPIO[88]
NPC
MSEO[1]
—
NPC
RDY
—
SIUL
GPIO[132]
GPIO[132]
SIUL
GPIO[39]
GPIO[39]
FlexPWM_0
A[1]
A[1]
SSCM
DEBUG[7]
—
DSPI_0
—
SIN
K6
VDD_LV
—
K7
VSS_LV
—
K8
VSS_LV
—
K9
VSS_LV
—
K10
VSS_LV
—
K11
VSS_LV
—
K12
VDD_LV
—
K14
Not connected
—
K15
H[8]
K16
H[7]
Input function
SIUL
GPIO[120]
GPIO[120]
FlexPWM_1
A[1]
A[1]
DSPI_0
CS6
—
SIUL
GPIO[119]
GPIO[119]
FlexPWM_1
X[1]
X[1]
eTimer_2
ETC[1]
ETC[1]
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
45
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
K17
A[3]
SIUL
GPIO[3]
GPIO[3]
eTimer_0
ETC[3]
ETC[3]
DSPI_2
CS0
CS0
FlexPWM_0
B[3]
B[3]
MC_RGM
—
ABS[2]
SIUL
—
EIRQ[3]
SIUL
GPIO[90]
GPIO[90]
NPC
EVTO
—
SIUL
GPIO[91]
GPIO[91]
NPC
—
EVTI
SIUL
GPIO[57]
GPIO[57]
FlexPWM_0
X[0]
X[0]
LINFlexD_1
TXD
—
L1
L2
L3
F[10]
F[11]
D[9]
L4
Not connected
—
L6
VDD_LV
—
L7
VSS_LV
—
L8
VSS_LV
—
L9
VSS_LV
—
L10
VSS_LV
—
L11
VSS_LV
—
L12
VDD_LV
—
L14
Not connected
—
L15
TCK
—
L16
H[4]
L17
B[4]
SIUL
GPIO[116]
GPIO[116]
FlexPWM_1
X[0]
X[0]
eTimer_2
ETC[0]
ETC[0]
SIUL
GPIO[20]
GPIO[20]
JTAGC
TDO
—
M1
VDD_HV_OSC
—
M2
VDD_HV_IO_RING
—
M3
D[8]
SIUL
GPIO[56]
GPIO[56]
DSPI_1
CS2
—
eTimer_1
ETC[4]
ETC[4]
DSPI_0
CS5
—
FlexPWM_0
—
FAULT[3]
MPC5643L Microcontroller Data Sheet, Rev. 10
46
NXP Semiconductors
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
M4
Not connected
—
M6
VDD_LV
—
M7
VDD_LV
—
M8
VDD_LV
—
M9
VDD_LV
—
M10
VDD_LV
—
M11
VDD_LV
—
M12
VDD_LV
—
M14
C[11]
M15
B[5]
M16
TMS
M17
H[5]
Peripheral
Output function
SIUL
GPIO[43]
GPIO[43]
eTimer_0
ETC[4]
ETC[4]
DSPI_2
CS2
—
SIUL
GPIO[21]
GPIO[21]
JTAGC
—
TDI
—
SIUL
GPIO[117]
GPIO[117]
FlexPWM_1
A[0]
A[0]
DSPI_0
CS4
—
N1
XTAL
—
N2
VSS_HV_IO_RING
—
N3
D[5]
SIUL
GPIO[53]
GPIO[53]
DSPI_0
CS3
—
FlexPWM_0
—
FAULT[2]
N4
VSS_LV_PLL0_PLL1
—
N14
Not connected
—
N15
C[12]
N16
A[2]
Input function
SIUL
GPIO[44]
GPIO[44]
eTimer_0
ETC[5]
ETC[5]
DSPI_2
CS3
—
SIUL
GPIO[2]
GPIO[2]
eTimer_0
ETC[2]
ETC[2]
FlexPWM_0
A[3]
A[3]
DSPI_2
—
SIN
MC_RGM
—
ABS[0]
SIUL
—
EIRQ[2]
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
47
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
N17
G[5]
SIUL
GPIO[101]
GPIO[101]
FlexPWM_0
X[3]
X[3]
DSPI_2
CS3
—
P1
VSS_HV_OSC
—
P2
RESET
—
P3
D[6]
SIUL
GPIO[54]
GPIO[54]
DSPI_0
CS2
—
FlexPWM_0
X[3]
X[3]
FlexPWM_0
—
FAULT[1]
P4
VDD_LV_PLL0_PLL1
—
P5
VDD_LV_CORE_RING
—
P6
VSS_LV_CORE_RING
—
P7
B[8]
SIUL
—
GPIO[24]
eTimer_0
—
ETC[5]
ADC_0
—
AN[1]
P8
Not connected
—
P9
VSS_HV_IO_RING
—
P10
VDD_HV_IO_RING
—
P11
B[14]
SIUL
—
GPIO[30]
eTimer_0
—
ETC[4]
SIUL
—
EIRQ[19]
ADC_1
—
AN[1]
P12
VDD_LV_CORE_RING
—
P13
VSS_LV_CORE_RING
—
P14
VDD_HV_IO_RING
—
P15
G[10]
P16
G[8]
SIUL
GPIO[106]
GPIO[106]
FlexRay
DBG2
—
DSPI_2
CS3
—
FlexPWM_0
—
FAULT[2]
SIUL
GPIO[104]
GPIO[104]
FlexRay
DBG0
—
DSPI_0
CS1
—
FlexPWM_0
—
FAULT[0]
SIUL
—
EIRQ[21]
MPC5643L Microcontroller Data Sheet, Rev. 10
48
NXP Semiconductors
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
P17
G[7]
SIUL
GPIO[103]
GPIO[103]
FlexPWM_0
B[3]
B[3]
R1
EXTAL
R2
FCCU_F[0]
R3
VSS_HV_IO_RING
R4
D[7]
R5
R6
—
B[7]
E[6]
R7
VDD_HV_ADR0
R8
B[10]
R9
VDD_HV_ADR1
R10
B[13]
R11
R12
B[15]
C[0]
R13
BCTRL
R14
A[1]
R15
FCCU
F[0]
F[0]
—
SIUL
GPIO[55]
GPIO[55]
DSPI_1
CS3
—
DSPI_0
CS4
—
SWG
analog output
—
SIUL
—
GPIO[23]
LINFlexD_0
—
RXD
ADC_0
—
AN[0]
SIUL
—
GPIO[70]
ADC_0
—
AN[4]
—
SIUL
—
GPIO[26]
ADC_0
ADC_1
—
AN[12]
—
SIUL
—
GPIO[29]
LINFlexD_1
—
RXD
ADC_1
—
AN[0]
SIUL
—
GPIO[31]
SIUL
—
EIRQ[20]
ADC_1
—
AN[2]
SIUL
—
GPIO[32]
ADC_1
—
AN[3]
—
VSS_HV_IO_RING
SIUL
GPIO[1]
GPIO[1]
eTimer_0
ETC[1]
ETC[1]
DSPI_2
SOUT
—
SIUL
—
EIRQ[1]
—
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
49
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
R16
D[11]
SIUL
GPIO[59]
GPIO[59]
FlexPWM_0
B[0]
B[0]
eTimer_0
—
ETC[1]
SIUL
GPIO[105]
GPIO[105]
FlexRay
DBG1
—
DSPI_1
CS1
—
FlexPWM_0
—
FAULT[1]
SIUL
—
EIRQ[29]
R17
G[9]
T1
VSS_HV_IO_RING
—
T2
VDD_HV_IO_RING
—
T3
Not connected
—
T4
C[1]
T5
T6
E[5]
E[7]
T7
VSS_HV_ADR0
T8
B[11]
T9
VSS_HV_ADR1
T10
E[9]
T11
T12
T13
T14
E[10]
E[12]
E[0]
A[0]
SIUL
—
GPIO[33]
ADC_0
—
AN[2]
SIUL
—
GPIO[69]
ADC_0
—
AN[8]
SIUL
—
GPIO[71]
ADC_0
—
AN[6]
—
SIUL
—
GPIO[27]
ADC_0
ADC_1
—
AN[13]
—
SIUL
—
GPIO[73]
ADC_1
—
AN[7]
SIUL
—
GPIO[74]
ADC_1
—
AN[8]
SIUL
—
GPIO[76]
ADC_1
—
AN[6]
SIUL
—
GPIO[64]
ADC_1
—
AN[5]
SIUL
GPIO[0]
GPIO[0]
eTimer_0
ETC[0]
ETC[0]
DSPI_2
SCK
SCK
SIUL
—
EIRQ[0]
MPC5643L Microcontroller Data Sheet, Rev. 10
50
NXP Semiconductors
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
T15
D[10]
SIUL
GPIO[58]
GPIO[58]
FlexPWM_0
A[0]
A[0]
eTimer_0
—
ETC[0]
T16
VDD_HV_IO_RING
—
T17
VSS_HV_IO_RING
—
U1
VSS_HV_IO_RING
—
U2
VSS_HV_IO_RING
—
U3
Not connected
—
U4
E[4]
U5
U6
U7
U8
1
C[2]
E[2]
B[9]
B[12]
SIUL
—
GPIO[68]
ADC_0
—
AN[7]
SIUL
—
GPIO[34]
ADC_0
—
AN[3]
SIUL
—
GPIO[66]
ADC_0
—
AN[5]
SIUL
—
GPIO[25]
ADC_0
ADC_1
—
AN[11]
SIUL
—
GPIO[28]
ADC_0
ADC_1
—
AN[14]
U9
VDD_HV_ADV
—
U10
VSS_HV_ADV
—
U11
E[11]
SIUL
—
GPIO[75]
ADC_1
—
AN[4]
U12
Not connected
—
U13
Not connected
—
U14
VDD_HV_PMU
—
U15
G[11]
SIUL
GPIO[107]
GPIO[107]
FlexRay
DBG3
—
FlexPWM_0
—
FAULT[3]
U16
VSS_HV_IO_RING
—
U17
VSS_HV_IO_RING
—
VPP_TEST should always be tied to ground (VSS) for normal operations.
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
51
Package pinouts and signal descriptions
2.2
Supply pins
Table 5. Supply pins
Supply
Pin #
144
pkg
257
pkg
Voltage regulator external NPN ballast base control pin
69
R13
VDD_LV_COR
Core logic supply
70
VDD_LV1
VSS_LV_COR
Core regulator ground
71
VSS_LV2
VDD_HV_PMU
Voltage regulator supply
72
U14
Symbol
Description
VREG control and power supply pins
BCTRL
ADC_0/ADC_1 reference voltage and ADC supply
VDD_HV_ADR0
ADC_0 high reference voltage
50
R7
VSS_HV_ADR0
ADC_0 low reference voltage
51
T7
VDD_HV_ADR1
ADC_1 high reference voltage
56
R9
VSS_HV_ADR1
ADC_1 low reference voltage
57
T9
VDD_HV_ADV
ADC voltage supply for ADC_0 and ADC_1
58
U9
VSS_HV_ADV
ADC ground for ADC_0 and ADC_1
59
U10
Power supply pins (3.3 V)
VDD_HV_IO
3.3 V Input/Output supply voltage
6
VDD_HV3
VSS_HV_IO
3.3 V Input/Output ground
7
VSS_HV4
16
J3
VDD_HV_REG_0 VDD_HV_REG_0
VDD_HV_IO
3.3 V Input/Output supply voltage
21
VDD_HV3
VSS_HV_IO
3.3 V Input/Output ground
22
VSS_HV4
VDD_HV_OSC
Crystal oscillator amplifier supply voltage
27
M1
VSS_HV_OSC
Crystal oscillator amplifier ground
28
P1
VSS_HV_IO
3.3 V Input/Output ground
90
VSS_HV4
VDD_HV_IO
3.3 V Input/Output supply voltage
91
VDD_HV3
95
H15
VDD_HV_REG_1 VDD_HV_REG_1
VSS_HV_FLA
VSS_HV_FLA
96
J16
VDD_HV_FLA
VDD_HV_FLA
97
H16
VDD_HV_IO
VDD_HV_IO
126
VDD_HV3
VSS_HV_IO
VSS_HV_IO
127
VSS_HV4
130
C7
VDD_HV_REG_2 VDD_HV_REG_2
Power supply pins (1.2 V)
MPC5643L Microcontroller Data Sheet, Rev. 10
52
NXP Semiconductors
Package pinouts and signal descriptions
Table 5. Supply pins (continued)
Supply
1
Pin #
144
pkg
257
pkg
VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
17
VSS_HV2
VDD_LV_COR
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
18
VDD_LV1
VSS 1V2
VSS_LV_PLL0_PLL1 /
1.2 V Decoupling pins for on-chip FMPLL modules. Decoupling capacitor
must be connected between this pin and VDD_LV_PLL.
35
N4
VDD 1V2
VDD_LV_PLL0_PLL1
Decoupling pins for on-chip FMPLL modules. Decoupling capacitor must
be connected between this pin and VSS_LV_PLL.
36
P4
VDD_LV_COR
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
39
VDD_LV1
VSS_LV_COR
VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
40
VSS_LV2
VDD_LV_COR
VDD_LV_COR
Decoupling pins for core logic and Regulator feedback. Decoupling
capacitor must be connected between this pins and VSS_LV_REGCOR.
70
VDD_LV1
VSS_LV_COR
VSS_LV_REGCOR0
Decoupling pins for core logic and Regulator feedback. Decoupling
capacitor must be connected between this pins and VDD_LV_REGCOR.
71
VSS_LV2
VDD_LV_COR
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
93
VDD_LV1
VSS_LV_COR
VSS_LV_COR
/ 1.2 V Decoupling pins for core logic. Decoupling capacitor must be
connected between these pins and the nearest VDD_LV_COR pin.
94
VSS_LV2
VDD 1V2
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
131
VDD_LV1
VSS 1V2
VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
132
VSS_LV2
VDD 1V2
VDD_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
135
VDD_LV1
VSS 1V2
VSS_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
137
VSS_LV2
Symbol
Description
VSS_LV_COR
VDD_LV balls are tied together on the 257 MAPBGA substrate.
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
53
Package pinouts and signal descriptions
2
VSS_LV balls are tied together on the 257 MAPBGA substrate.
VDD_HV balls are tied together on the 257 MAPBGA substrate.
4
VSS_HV balls are tied together on the 257 MAPBGA substrate.
3
2.3
System pins
Table 6. System pins
Pin #
Symbol
Description
Direction
144
pkg
257
pkg
Output only
9
E1
Dedicated pins
MDO01
2
Nexus Message Data Output — line
NMI
Non Maskable Interrupt
Input only
1
E4
XTAL
Input for oscillator amplifier circuit and internal clock generator
Input only
29
N1
Input/Output4
30
R1
JTAG state machine control
Input only
87
M16
JTAG clock
Input only
88
L15
JTAG compliance select
Input only
123
C10
Bidirectional
31
P2
107
D15
EXTAL3
TMS2
TCK2
5
JCOMP
Oscillator amplifier output
Reset pin
RESET
Bidirectional reset with Schmitt-Trigger characteristics and noise filter.
This pin has medium drive strength. Output drive is open drain and
must be terminated by an external resistor of value 1KOhm.6
Test pin
VPP TEST
1
2
3
4
5
6
Pin for testing purpose only. To be tied to ground in normal
operating mode.
This pad is configured for Fast (F) pad speed.
This pad contains a weak pull-up.
EXTAL is an "Output" in "crystal" mode, and is an "Input" in "ext clock" mode.
In XOSC Bypass Mode, the analog portion of crystal oscillator (amplifier) is disabled. An external clock can be applied
at EXTAL as an input. In XOSC Normal Mode, EXTAL is an output
This pad contains a weak pull-down.
RESET output shall be considered valid only after the 3.3V supply reaches its stable value.
NOTE
None of system pins (except RESET) provides an open drain output.
MPC5643L Microcontroller Data Sheet, Rev. 10
54
NXP Semiconductors
NXP Semiconductors
2.4
Pin muxing
Table 7 defines the pin list and muxing for this device.
Each entry of Table 7 shows all the possible configurations for each pin, via the alternate functions. The default function assigned to each pin after reset is
indicated by ALT0.
NOTE
Pins labeled “NC” are to be left unconnected. Any connection to an external circuit or voltage may cause unpredictable
device behavior or damage.
Pins labeled “Reserved” are to be tied to ground. Not doing so may cause unpredictable device behavior.
Table 7. Pin muxing
PCR
Peripheral
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
Port A
A[0]
A[1]
PCR[0]
PCR[1]
SIUL
GPIO[0]
ALT0
GPIO[0]
—
eTimer_0
ETC[0]
ALT1
ETC[0]
PSMI[35];
PADSEL=0
DSPI_2
SCK
ALT2
SCK
PSMI[1];
PADSEL=0
SIUL
—
—
EIRQ[0]
—
SIUL
GPIO[1]
ALT0
GPIO[1]
—
eTimer_0
ETC[1]
ALT1
ETC[1]
PSMI[36];
PADSEL=0
DSPI_2
SOUT
ALT2
—
—
SIUL
—
—
EIRQ[1]
—
—
M
S
73
T14
—
M
S
74
R14
55
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 10
Port
name
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
Port
name
PCR
Peripheral
Alternate
output
function
A[2]
PCR[2]
SIUL
GPIO[2]
ALT0
GPIO[2]
—
eTimer_0
ETC[2]
ALT1
ETC[2]
PSMI[37];
PADSEL=0
FlexPWM_0
A[3]
ALT3
A[3]
PSMI[23];
PADSEL=0
DSPI_2
—
—
SIN
PSMI[2];
PADSEL=0
MC_RGM
—
—
ABS[0]
—
SIUL
—
—
EIRQ[2]
—
SIUL
GPIO[3]
ALT0
GPIO[3]
—
eTimer_0
ETC[3]
ALT1
ETC[3]
PSMI[38];
PADSEL=0
DSPI_2
CS0
ALT2
CS0
PSMI[3];
PADSEL=0
FlexPWM_0
B[3]
ALT3
B[3]
PSMI[27];
PADSEL=0
MC_RGM
—
—
ABS[2]
—
SIUL
—
—
EIRQ[3]
—
SIUL
GPIO[4]
ALT0
GPIO[4]
—
eTimer_1
ETC[0]
ALT1
ETC[0]
PSMI[9];
PADSEL=0
DSPI_2
CS1
ALT2
—
—
eTimer_0
ETC[4]
ALT3
ETC[4]
PSMI[7];
PADSEL=0
MC_RGM
—
—
FAB
—
SIUL
—
—
EIRQ[4]
—
A[3]
A[4]
PCR[3]
PCR[4]
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
Pull down
M
S
84
N16
Pull down
M
S
92
K17
Pull down
M
S
108
C16
Package pinouts and signal descriptions
56
Table 7. Pin muxing (continued)
MPC5643L Microcontroller Data Sheet, Rev. 10
Port
name
PCR
Peripheral
Alternate
output
function
A[5]
PCR[5]
SIUL
GPIO[5]
ALT0
GPIO[5]
—
DSPI_1
CS0
ALT1
CS0
—
eTimer_1
ETC[5]
ALT2
ETC[5]
PSMI[14];
PADSEL=0
DSPI_0
CS7
ALT3
—
—
SIUL
—
—
EIRQ[5]
—
SIUL
GPIO[6]
ALT0
GPIO[6]
—
DSPI_1
SCK
ALT1
SCK
—
SIUL
—
—
EIRQ[6]
—
SIUL
GPIO[7]
ALT0
GPIO[7]
—
DSPI_1
SOUT
ALT1
—
—
SIUL
—
—
EIRQ[7]
—
SIUL
GPIO[8]
ALT0
GPIO[8]
—
DSPI_1
—
—
SIN
—
SIUL
—
—
EIRQ[8]
—
SIUL
GPIO[9]
ALT0
GPIO[9]
—
DSPI_2
CS1
ALT1
—
—
FlexPWM_0
B[3]
ALT3
B[3]
PSMI[27];
PADSEL=1
FlexPWM_0
—
—
FAULT[0]
PSMI[16];
PADSEL=0
A[6]
A[7]
A[8]
A[9]
PCR[6]
PCR[7]
PCR[8]
PCR[9]
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
M
S
14
H4
—
M
S
2
G4
—
M
S
10
F3
—
M
S
12
F4
—
M
S
134
B6
Package pinouts and signal descriptions
57
Table 7. Pin muxing (continued)
NXP Semiconductors
MPC5643L Microcontroller Data Sheet, Rev. 10
Port
name
PCR
Peripheral
Alternate
output
function
A[10]
PCR[10]
SIUL
GPIO[10]
ALT0
GPIO[10]
—
DSPI_2
CS0
ALT1
CS0
PSMI[3];
PADSEL=1
FlexPWM_0
B[0]
ALT2
B[0]
PSMI[24];
PADSEL=0
FlexPWM_0
X[2]
ALT3
X[2]
PSMI[29];
PADSEL=0
SIUL
—
—
EIRQ[9]
—
SIUL
GPIO[11]
ALT0
GPIO[11]
—
DSPI_2
SCK
ALT1
SCK
PSMI[1];
PADSEL=1
FlexPWM_0
A[0]
ALT2
A[0]
PSMI[20];
PADSEL=0
FlexPWM_0
A[2]
ALT3
A[2]
PSMI[22];
PADSEL=0
SIUL
—
—
EIRQ[10]
—
SIUL
GPIO[12]
ALT0
GPIO[12]
—
DSPI_2
SOUT
ALT1
—
—
FlexPWM_0
A[2]
ALT2
A[2]
PSMI[22];
PADSEL=1
FlexPWM_0
B[2]
ALT3
B[2]
PSMI[26];
PADSEL=0
SIUL
—
—
EIRQ[11]
—
A[11]
A[12]
PCR[11]
PCR[12]
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
M
S
118
A13
—
M
S
120
D11
—
M
S
122
A10
Package pinouts and signal descriptions
58
Table 7. Pin muxing (continued)
NXP Semiconductors
MPC5643L Microcontroller Data Sheet, Rev. 10
Port
name
PCR
Peripheral
Alternate
output
function
A[13]
PCR[13]
SIUL
GPIO[13]
ALT0
GPIO[13]
—
FlexPWM_0
B[2]
ALT2
B[2]
PSMI[26];
PADSEL=1
DSPI_2
—
—
SIN
PSMI[2];
PADSEL=1
FlexPWM_0
—
—
FAULT[0]
PSMI[16];
PADSEL=1
SIUL
—
—
EIRQ[12]
—
SIUL
GPIO[14]
ALT0
GPIO[14]
—
FlexCAN_1
TXD
ALT1
—
—
eTimer_1
ETC[4]
ALT2
ETC[4]
PSMI[13];
PADSEL=0
SIUL
—
—
EIRQ[13]
—
SIUL
GPIO[15]
ALT0
GPIO[15]
—
eTimer_1
ETC[5]
ALT2
ETC[5]
PSMI[14];
PADSEL=1
FlexCAN_1
—
—
RXD
PSMI[34];
PADSEL=0
FlexCAN_0
—
—
RXD
PSMI[33];
PADSEL=0
SIUL
—
—
EIRQ[14]
—
A[14]
A[15]
PCR[14]
PCR[15]
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
M
S
136
C6
—
M
S
143
B4
—
M
S
144
D3
—
M
S
109
B15
Port B
B[0]
PCR[16]
NXP Semiconductors
SIUL
GPIO[16]
ALT0
GPIO[16]
—
FlexCAN_0
TXD
ALT1
—
—
eTimer_1
ETC[2]
ALT2
ETC[2]
PSMI[11];
PADSEL=0
SSCM
DEBUG[0]
ALT3
—
—
SIUL
—
—
EIRQ[15]
—
Package pinouts and signal descriptions
59
Table 7. Pin muxing (continued)
MPC5643L Microcontroller Data Sheet, Rev. 10
Port
name
PCR
Peripheral
Alternate
output
function
B[1]
PCR[17]
SIUL
GPIO[17]
ALT0
GPIO[17]
—
eTimer_1
ETC[3]
ALT2
ETC[3]
PSMI[12];
PADSEL=0
SSCM
DEBUG[1]
ALT3
—
—
FlexCAN_0
—
—
RXD
PSMI[33];
PADSEL=1
FlexCAN_1
—
—
RXD
PSMI[34];
PADSEL=1
SIUL
—
—
EIRQ[16]
—
SIUL
GPIO[18]
ALT0
GPIO[18]
—
LINFlexD_0
TXD
ALT1
—
—
SSCM
DEBUG[2]
ALT3
—
—
SIUL
—
—
EIRQ[17]
—
SIUL
GPIO[19]
ALT0
GPIO[19]
—
SSCM
DEBUG[3]
ALT3
—
—
LINFlexD_0
—
—
RXD
PSMI[31];
PADSEL=0
SIUL
GPIO[20]
ALT0
GPIO[20]
—
JTAGC
TDO
ALT1
—
—
SIUL
GPIO[21]
ALT0
GPIO[21]
—
JTAGC
—
—
TDI
—
SIUL
GPIO[22]
ALT0
GPIO[22]
—
MC_CGM
clk_out
ALT1
—
—
DSPI_2
CS2
ALT2
—
—
SIUL
—
EIRQ[18]
—
B[2]
B[3]
B[4]2
B[5]
B[6]
PCR[18]
PCR[19]
PCR[20]
PCR[21]
PCR[22]
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
M
S
110
C14
—
M
S
114
A14
—
M
S
116
B13
—
F
S
89
L17
Pull up
M
S
86
M15
—
F
S
138
B3
Package pinouts and signal descriptions
60
Table 7. Pin muxing (continued)
NXP Semiconductors
Port
name
PCR
Peripheral
Alternate
output
function
B[7]
PCR[23]
SIUL
—
ALT0
GPI[23]
—
LINFlexD_0
—
—
RXD
PSMI[31];
PADSEL=1
ADC_0
—
—
AN[0]3
—
SIUL
—
ALT0
GPI[24]
—
eTimer_0
—
—
ETC[5]
PSMI[8];
PADSEL=2
ADC_0
—
—
AN[1]3
—
SIUL
—
ALT0
GPI[25]
—
—
B[8]
MPC5643L Microcontroller Data Sheet, Rev. 10
B[9]
B[10]
B[11]
B[12]
B[13]
PCR[24]
PCR[25]
PCR[26]
PCR[27]
PCR[28]
PCR[29]
Output
mux sel
Input
functions
Input mux
select
ADC_0
ADC_1
—
—
AN[11]3
SIUL
—
ALT0
GPI[26]
—
—
NXP Semiconductors
ADC_0
ADC_1
—
—
AN[12]3
SIUL
—
ALT0
GPI[27]
—
ADC_0
ADC_1
—
—
AN[13]3
—
SIUL
—
ALT0
GPI[28]
—
ADC_0
ADC_1
—
—
AN[14]3
—
SIUL
—
ALT0
GPI[29]
—
LINFlexD_1
—
—
RXD
PSMI[32];
PADSEL=0
ADC_1
—
—
AN[0]3
—
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
—
—
43
R5
—
—
—
47
P7
—
—
—
52
U7
—
—
—
53
R8
—
—
—
54
T8
—
—
—
55
U8
—
—
—
60
R10
Package pinouts and signal descriptions
61
Table 7. Pin muxing (continued)
Port
name
PCR
Peripheral
Alternate
output
function
B[14]
PCR[30]
SIUL
—
ALT0
GPI[30]
—
eTimer_0
—
—
ETC[4]
PSMI[7];
PADSEL=2
SIUL
—
—
EIRQ[19]
—
MPC5643L Microcontroller Data Sheet, Rev. 10
B[15]
PCR[31]
Output
mux sel
Input
functions
Input mux
select
3
ADC_1
—
—
AN[1]
—
SIUL
—
ALT0
GPI[31]
—
SIUL
—
—
EIRQ[20]
—
ADC_1
—
3
—
ALT0
GPI[32]
—
—
—
AN[2]
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
—
—
64
P11
—
—
—
62
R11
—
—
—
66
R12
—
—
—
41
T4
—
—
—
45
U5
—
M
S
11
H3
Port C
C[0]
C[1]
C[2]
C[4]
PCR[32]
PCR[33]
PCR[34]
PCR[36]
SIUL
—
ADC_1
—
—
AN[3]3
SIUL
—
ALT0
GPI[33]
—
—
ADC_0
—
—
AN[2]3
SIUL
—
ALT0
GPI[34]
—
3
ADC_0
—
—
AN[3]
—
SIUL
GPIO[36]
ALT0
GPIO[36]
—
DSPI_0
CS0
ALT1
CS0
—
FlexPWM_0
X[1]
ALT2
X[1]
PSMI[28];
PADSEL=0
SSCM
DEBUG[4]
ALT3
—
—
SIUL
—
—
EIRQ[22]
—
Package pinouts and signal descriptions
62
Table 7. Pin muxing (continued)
NXP Semiconductors
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
Port
name
PCR
Peripheral
Alternate
output
function
C[5]
PCR[37]
SIUL
GPIO[37]
ALT0
GPIO[37]
—
DSPI_0
SCK
ALT1
SCK
—
SSCM
DEBUG[5]
ALT3
—
—
FlexPWM_0
—
—
FAULT[3]
PSMI[19];
PADSEL=0
SIUL
—
—
EIRQ[23]
—
SIUL
GPIO[38]
ALT0
GPIO[38]
—
DSPI_0
SOUT
ALT1
—
—
FlexPWM_0
B[1]
ALT2
B[1]
PSMI[25];
PADSEL=0
SSCM
DEBUG[6]
ALT3
—
—
SIUL
—
—
EIRQ[24]
—
SIUL
GPIO[39]
ALT0
GPIO[39]
—
FlexPWM_0
A[1]
ALT2
A[1]
PSMI[21];
PADSEL=0
SSCM
DEBUG[7]
ALT3
—
—
DSPI_0
—
—
SIN
—
SIUL
GPIO[42]
ALT0
GPIO[42]
—
DSPI_2
CS2
ALT1
—
—
FlexPWM_0
A[3]
ALT3
A[3]
PSMI[23];
PADSEL=1
FlexPWM_0
—
—
FAULT[1]
PSMI[17];
PADSEL=0
SIUL
GPIO[43]
ALT0
GPIO[43]
—
eTimer_0
ETC[4]
ALT1
ETC[4]
PSMI[7];
PADSEL=1
DSPI_2
CS2
ALT2
—
—
C[6]
C[7]
C[10]
C[11]
PCR[38]
PCR[39]
PCR[42]
PCR[43]
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
M
S
13
G3
—
M
S
142
D4
—
M
S
15
K4
—
M
S
111
A15
—
M
S
80
M14
Package pinouts and signal descriptions
63
Table 7. Pin muxing (continued)
Port
name
PCR
Peripheral
Alternate
output
function
C[12]
PCR[44]
SIUL
GPIO[44]
ALT0
GPIO[44]
—
eTimer_0
ETC[5]
ALT1
ETC[5]
PSMI[8];
PADSEL=0
DSPI_2
CS3
ALT2
—
—
SIUL
GPIO[45]
ALT0
GPIO[45]
—
eTimer_1
ETC[1]
ALT1
ETC[1]
PSMI[10];
PADSEL=0
CTU_0
—
—
EXT_IN
PSMI[0];
PADSEL=0
FlexPWM_0
—
—
EXT_SYNC
PSMI[15];
PADSEL=0
SIUL
GPIO[46]
ALT0
GPIO[46]
—
eTimer_1
ETC[2]
ALT1
ETC[2]
PSMI[11];
PADSEL=1
CTU_0
EXT_TGR
ALT2
—
—
SIUL
GPIO[47]
ALT0
GPIO[47]
—
FlexRay
CA_TR_EN
ALT1
—
—
eTimer_1
ETC[0]
ALT2
ETC[0]
PSMI[9];
PADSEL=1
FlexPWM_0
A[1]
ALT3
A[1]
PSMI[21];
PADSEL=1
CTU_0
—
—
EXT_IN
PSMI[0];
PADSEL=1
FlexPWM_0
—
—
EXT_SYNC
PSMI[15];
PADSEL=1
C[13]
MPC5643L Microcontroller Data Sheet, Rev. 10
C[14]
C[15]
PCR[45]
PCR[46]
PCR[47]
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
M
S
82
N15
—
M
S
101
F15
—
M
S
103
E15
—
SYM
S
124
A8
Package pinouts and signal descriptions
64
Table 7. Pin muxing (continued)
NXP Semiconductors
Port
name
PCR
Peripheral
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
Port D
D[0]
MPC5643L Microcontroller Data Sheet, Rev. 10
D[1]
D[2]
D[3]
PCR[48]
PCR[49]
PCR[50]
PCR[51]
NXP Semiconductors
SIUL
GPIO[48]
ALT0
GPIO[48]
—
FlexRay
CA_TX
ALT1
—
—
eTimer_1
ETC[1]
ALT2
ETC[1]
PSMI[10];
PADSEL=1
FlexPWM_0
B[1]
ALT3
B[1]
PSMI[25];
PADSEL=1
SIUL
GPIO[49]
ALT0
GPIO[49]
—
eTimer_1
ETC[2]
ALT2
ETC[2]
PSMI[11];
PADSEL=2
CTU_0
EXT_TGR
ALT3
—
—
FlexRay
—
—
CA_RX
—
SIUL
GPIO[50]
ALT0
GPIO[50]
—
eTimer_1
ETC[3]
ALT2
ETC[3]
PSMI[12];
PADSEL=1
FlexPWM_0
X[3]
ALT3
X[3]
PSMI[30];
PADSEL=0
FlexRay
—
—
CB_RX
—
SIUL
GPIO[51]
ALT0
GPIO[51]
—
FlexRay
CB_TX
ALT1
—
—
eTimer_1
ETC[4]
ALT2
ETC[4]
PSMI[13];
PADSEL=1
FlexPWM_0
A[3]
ALT3
A[3]
PSMI[23];
PADSEL=2
—
SYM
S
125
B8
—
M
S
3
E3
—
M
S
140
C5
—
SYM
S
128
A7
Package pinouts and signal descriptions
65
Table 7. Pin muxing (continued)
MPC5643L Microcontroller Data Sheet, Rev. 10
Port
name
PCR
Peripheral
Alternate
output
function
D[4]
PCR[52]
SIUL
GPIO[52]
ALT0
GPIO[52]
—
FlexRay
CB_TR_EN
ALT1
—
—
eTimer_1
ETC[5]
ALT2
ETC[5]
PSMI[14];
PADSEL=2
FlexPWM_0
B[3]
ALT3
B[3]
PSMI[27];
PADSEL=2
SIUL
GPIO[53]
ALT0
GPIO[53]
—
DSPI_0
CS3
ALT1
—
—
FlexPWM_0
—
—
FAULT[2]
PSMI[18];
PADSEL=0
SIUL
GPIO[54]
ALT0
GPIO[54]
—
DSPI_0
CS2
ALT1
—
—
FlexPWM_0
X[3]
ALT3
X[3]
PSMI[30];
PADSEL=1
FlexPWM_0
—
—
FAULT[1]
PSMI[17];
PADSEL=1
SIUL
GPIO[55]
ALT0
GPIO[55]
—
DSPI_1
CS3
ALT1
—
—
DSPI_0
CS4
ALT3
—
—
SWG
analog output
—
—
—
SIUL
GPIO[56]
ALT0
GPIO[56]
—
DSPI_1
CS2
ALT1
—
—
eTimer_1
ETC[4]
ALT2
ETC[4]
PSMI[13];
PADSEL=2
DSPI_0
CS5
ALT3
—
—
FlexPWM_0
—
—
FAULT[3]
PSMI[19];
PADSEL=1
D[5]
D[6]
D[7]
D[8]
PCR[53]
PCR[54]
PCR[55]
PCR[56]
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
SYM
S
129
B7
—
M
S
33
N3
—
M
S
34
P3
—
M
S
37
R4
—
M
S
32
M3
Package pinouts and signal descriptions
66
Table 7. Pin muxing (continued)
NXP Semiconductors
Port
name
PCR
Peripheral
Alternate
output
function
D[9]
PCR[57]
SIUL
GPIO[57]
ALT0
GPIO[57]
—
FlexPWM_0
X[0]
ALT1
X[0]
—
LINFlexD_1
TXD
ALT2
—
—
SIUL
GPIO[58]
ALT0
GPIO[58]
—
FlexPWM_0
A[0]
ALT1
A[0]
PSMI[20];
PADSEL=1
eTimer_0
—
—
ETC[0]
PSMI[35];
PADSEL=1
SIUL
GPIO[59]
ALT0
GPIO[59]
—
FlexPWM_0
B[0]
ALT1
B[0]
PSMI[24];
PADSEL=1
eTimer_0
—
—
ETC[1]
PSMI[36];
PADSEL=1
SIUL
GPIO[60]
ALT0
GPIO[60]
FlexPWM_0
X[1]
ALT1
X[1]
PSMI[28];
PADSEL=1
LINFlexD_1
—
—
RXD
PSMI[32];
PADSEL=1
SIUL
GPIO[62]
ALT0
GPIO[62]
—
FlexPWM_0
B[1]
ALT1
B[1]
PSMI[25];
PADSEL=2
eTimer_0
—
—
ETC[3]
PSMI[38];
PADSEL=1
D[10]
MPC5643L Microcontroller Data Sheet, Rev. 10
D[11]
D[12]
D[14]
PCR[58]
PCR[59]
PCR[60]
PCR[62]
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
NXP Semiconductors
—
M
S
26
L3
—
M
S
76
T15
—
M
S
78
R16
—
M
S
99
G14
—
M
S
105
D16
—
—
—
68
T13
—
—
—
49
U6
Port E
E[0]
E[2]
PCR[64]
PCR[66]
SIUL
—
ALT0
GPI[64]
—
—
ADC_1
—
—
AN[5]3
SIUL
—
ALT0
GPI[66]
—
ADC_0
—
—
AN[5]3
—
Package pinouts and signal descriptions
67
Table 7. Pin muxing (continued)
Port
name
PCR
Peripheral
Alternate
output
function
E[4]
PCR[68]
SIUL
—
E[5]
E[6]
MPC5643L Microcontroller Data Sheet, Rev. 10
E[7]
E[9]
E[10]
E[11]
E[12]
E[13]
NXP Semiconductors
E[14]
PCR[69]
PCR[70]
PCR[71]
PCR[73]
PCR[74]
PCR[75]
PCR[76]
PCR[77]
PCR[78]
Output
mux sel
Input
functions
Input mux
select
ALT0
GPI[68]
—
3
ADC_0
—
—
AN[7]
—
SIUL
—
ALT0
GPI[69]
—
ADC_0
—
—
AN[8]3
—
SIUL
—
ALT0
GPI[70]
—
3
ADC_0
—
—
AN[4]
—
SIUL
—
ALT0
GPI[71]
—
ADC_0
—
—
AN[6]3
—
SIUL
—
ALT0
GPI[73]
—
—
ADC_1
—
—
AN[7]3
SIUL
—
ALT0
GPI[74]
—
ADC_1
—
—
AN[8]3
—
SIUL
—
ALT0
GPI[75]
—
—
ADC_1
—
—
AN[4]3
SIUL
—
ALT0
GPI[76]
—
ADC_1
—
—
AN[6]3
—
SIUL
GPIO[77]
ALT0
GPIO[77]
—
eTimer_0
ETC[5]
ALT1
ETC[5]
PSMI[8];
PADSEL=1
DSPI_2
CS3
ALT2
—
—
SIUL
—
—
EIRQ[25]
—
SIUL
GPIO[78]
ALT0
GPIO[78]
—
eTimer_1
ETC[5]
ALT1
ETC[5]
PSMI[14];
PADSEL=3
SIUL
—
—
EIRQ[26]
—
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
—
—
42
U4
—
—
—
44
T5
—
—
—
46
R6
—
—
—
48
T6
—
—
—
61
T10
—
—
—
63
T11
—
—
—
65
U11
—
—
—
67
T12
—
M
S
117
D12
—
M
S
119
B12
Package pinouts and signal descriptions
68
Table 7. Pin muxing (continued)
Port
name
PCR
Peripheral
Alternate
output
function
E[15]
PCR[79]
SIUL
GPIO[79]
ALT0
GPIO[79]
—
DSPI_0
CS1
ALT1
—
—
SIUL
—
—
EIRQ[27]
—
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
M
S
121
B11
—
M
S
133
D7
—
M
S
139
B5
—
F
S
4
D2
—
F
S
5
D1
—
F
S
8
E2
—
F
S
19
J1
—
F
S
20
K2
—
F
S
23
K1
—
F
S
24
L1
Port F
F[0]
MPC5643L Microcontroller Data Sheet, Rev. 10
F[3]
F[4]
F[5]
F[6]
F[7]
F[8]
NXP Semiconductors
F[9]
F[10]
PCR[80]
PCR[83]
PCR[84]
PCR[85]
PCR[86]
PCR[87]
PCR[88]
PCR[89]
PCR[90]
SIUL
GPIO[80]
ALT0
GPIO[80]
—
FlexPWM_0
A[1]
ALT1
A[1]
PSMI[21];
PADSEL=2
eTimer_0
—
—
ETC[2]
PSMI[37];
PADSEL=1
SIUL
—
—
EIRQ[28]
—
SIUL
GPIO[83]
ALT0
GPIO[83]
—
DSPI_0
CS6
ALT1
—
—
SIUL
GPIO[84]
ALT0
GPIO[84]
—
NPC
MDO[3]
ALT2
—
—
SIUL
GPIO[85]
ALT0
GPIO[85]
—
NPC
MDO[2]
ALT2
—
—
SIUL
GPIO[86]
ALT0
GPIO[86]
—
NPC
MDO[1]
ALT2
—
—
SIUL
GPIO[87]
ALT0
GPIO[87]
—
NPC
MCKO
ALT2
—
—
SIUL
GPIO[88]
ALT0
GPIO[88]
—
NPC
MSEO[1]
ALT2
—
—
SIUL
GPIO[89]
ALT0
GPIO[89]
—
NPC
MSEO[0]
ALT2
—
—
SIUL
GPIO[90]
ALT0
GPIO[90]
—
NPC
EVTO
ALT2
—
—
Package pinouts and signal descriptions
69
Table 7. Pin muxing (continued)
NXP Semiconductors
Table 7. Pin muxing (continued)
Port
name
PCR
Peripheral
Alternate
output
function
F[11]
PCR[91]
SIUL
GPIO[91]
ALT0
GPIO[91]
—
NPC
—
ALT2
EVTI
—
SIUL
GPIO[92]
ALT0
GPIO[92]
—
eTimer_1
ETC[3]
ALT1
ETC[3]
PSMI[12];
PADSEL=2
SIUL
—
—
EIRQ[30]
—
SIUL
GPIO[93]
ALT0
GPIO[93]
—
eTimer_1
ETC[4]
ALT1
ETC[4]
PSMI[13];
PADSEL=3
SIUL
—
—
EIRQ[31]
—
SIUL
GPIO[94]
ALT0
GPIO[94]
—
LINFlexD_1
TXD
ALT1
—
—
SIUL
GPIO[95]
ALT0
GPIO[95]
—
LINFlexD_1
—
—
RXD
PSMI[32];
PADSEL=2
F[12]
F[14]
F[15]
PCR[93]
PCR[94]
PCR[95]
Input
functions
Input mux
select
Pin #
144
pkg
257
pkg
—
M
S
25
L2
—
M
S
106
C17
—
M
S
112
B14
—
M
S
115
C13
—
M
S
113
D13
FCCU
FCCU_
F[0]
—
FCCU
F[0]
ALT0
F[0]
—
—
S
S
38
R2
FCCU_
F[1]
—
FCCU
F[1]
ALT0
F[1]
—
—
S
S
141
C4
—
M
S
102
E16
Port G
G[2]
PCR[98]
SIUL
GPIO[98]
ALT0
GPIO[98]
—
FlexPWM_0
X[2]
ALT1
X[2]
PSMI[29];
PADSEL=1
DSPI_1
CS1
ALT2
—
—
70
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 10
F[13]
PCR[92]
Output
mux sel
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
MPC5643L Microcontroller Data Sheet, Rev. 10
Port
name
PCR
Peripheral
Alternate
output
function
G[3]
PCR[99]
SIUL
GPIO[99]
ALT0
GPIO[99]
—
FlexPWM_0
A[2]
ALT1
A[2]
PSMI[22];
PADSEL=2
eTimer_0
—
—
ETC[4]
PSMI[7];
PADSEL=3
SIUL
GPIO[100]
ALT0
GPIO[100]
—
FlexPWM_0
B[2]
ALT1
B[2]
PSMI[26];
PADSEL=2
eTimer_0
—
—
ETC[5]
PSMI[8];
PADSEL=3
SIUL
GPIO[101]
ALT0
GPIO[101]
—
FlexPWM_0
X[3]
ALT1
X[3]
PSMI[30];
PADSEL=2
DSPI_2
CS3
ALT2
—
—
SIUL
GPIO[102]
ALT0
GPIO[102]
—
FlexPWM_0
A[3]
ALT1
A[3]
PSMI[23];
PADSEL=3
SIUL
GPIO[103]
ALT0
GPIO[103]
FlexPWM_0
B[3]
ALT1
B[3]
PSMI[27];
PADSEL=3
SIUL
GPIO[104]
ALT0
GPIO[104]
—
FlexRay
DBG0
ALT1
—
—
DSPI_0
CS1
ALT2
—
—
FlexPWM_0
—
—
FAULT[0]
PSMI[16];
PADSEL=2
SIUL
—
—
EIRQ[21]
—
G[4]
G[5]
G[6]
G[7]
G[8]
PCR[100]
PCR[101]
PCR[102]
PCR[103]
PCR[104]
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
M
S
104
D17
—
M
S
100
F17
—
M
S
85
N17
—
M
S
98
G17
—
M
S
83
P17
—
M
S
81
P16
Package pinouts and signal descriptions
71
Table 7. Pin muxing (continued)
NXP Semiconductors
NXP Semiconductors
Table 7. Pin muxing (continued)
PCR
Peripheral
G[9]
PCR[105]
SIUL
GPIO[105]
ALT0
GPIO[105]
—
FlexRay
DBG1
ALT1
—
—
DSPI_1
CS1
ALT2
—
—
FlexPWM_0
—
—
FAULT[1]
PSMI[17];
PADSEL=2
SIUL
—
—
EIRQ[29]
—
SIUL
GPIO[106]
ALT0
GPIO[106]
—
FlexRay
DBG2
ALT1
—
—
DSPI_2
CS3
ALT2
—
—
FlexPWM_0
—
—
FAULT[2]
PSMI[18];
PADSEL=1
SIUL
GPIO[107]
ALT0
GPIO[107]
—
FlexRay
DBG3
ALT1
—
—
FlexPWM_0
—
—
FAULT[3]
PSMI[19];
PADSEL=2
SIUL
GPIO[108]
ALT0
GPIO[108]
—
NPC
MDO[11]
ALT2
—
—
SIUL
GPIO[109]
ALT0
GPIO[109]
—
NPC
MDO[10]
ALT2
—
—
SIUL
GPIO[110]
ALT0
GPIO[110]
—
NPC
MDO[9]
ALT2
—
—
SIUL
GPIO[111]
ALT0
GPIO[111]
—
NPC
MDO[8]
ALT2
—
—
G[10]
G[11]
G[12]
G[13]
G[14]
G[15]
PCR[106]
PCR[107]
PCR[108]
PCR[109]
PCR[110]
PCR[111]
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
M
S
79
R17
—
M
S
77
P15
—
M
S
75
U15
—
F
S
—
F2
—
F
S
—
H1
—
F
S
—
A6
—
F
S
—
J2
—
F
S
—
A5
Port H
H[0]
PCR[112]
SIUL
GPIO[112]
ALT0
GPIO[112]
—
NPC
MDO[7]
ALT2
—
—
72
Package pinouts and signal descriptions
MPC5643L Microcontroller Data Sheet, Rev. 10
Port
name
Alternate
output
function
Port
name
PCR
Peripheral
Alternate
output
function
H[1]
PCR[113]
SIUL
GPIO[113]
ALT0
GPIO[113]
—
NPC
MDO[6]
ALT2
—
—
SIUL
GPIO[114]
ALT0
GPIO[114]
—
NPC
MDO[5]
ALT2
—
—
SIUL
GPIO[115]
ALT0
GPIO[115]
—
NPC
MDO[4]
ALT2
—
—
SIUL
GPIO[116]
ALT0
GPIO[116]
—
FlexPWM_1
X[0]
ALT1
X[0]
—
eTimer_2
ETC[0]
ALT2
ETC[0]
PSMI[39];
PADSEL=0
SIUL
GPIO[117]
ALT0
GPIO[117]
—
FlexPWM_1
A[0]
ALT1
A[0]
—
DSPI_0
CS4
ALT3
—
—
SIUL
GPIO[118]
ALT0
GPIO[118]
—
FlexPWM_1
B[0]
ALT1
B[0]
—
DSPI_0
CS5
ALT3
—
—
SIUL
GPIO[119]
ALT0
GPIO[119]
—
FlexPWM_1
X[1]
ALT1
X[1]
—
eTimer_2
ETC[1]
ALT2
ETC[1]
PSMI[40];
PADSEL=0
SIUL
GPIO[120]
ALT0
GPIO[120]
—
FlexPWM_1
A[1]
ALT1
A[1]
—
DSPI_0
CS6
ALT3
—
—
SIUL
GPIO[121]
ALT0
GPIO[121]
—
FlexPWM_1
B[1]
ALT1
B[1]
—
DSPI_0
CS7
ALT3
—
—
H[2]
H[3]
MPC5643L Microcontroller Data Sheet, Rev. 10
H[4]
H[5]
H[6]
H[7]
H[8]
NXP Semiconductors
H[9]
PCR[114]
PCR[115]
PCR[116]
PCR[117]
PCR[118]
PCR[119]
PCR[120]
PCR[121]
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
F
S
—
F1
—
F
S
—
A4
—
F
S
—
G1
—
M
S
—
L16
—
M
S
—
M17
—
M
S
—
H17
—
M
S
—
K16
—
M
S
—
K15
—
M
S
—
G16
Package pinouts and signal descriptions
73
Table 7. Pin muxing (continued)
Port
name
PCR
Peripheral
Alternate
output
function
H[10]
PCR[122]
SIUL
GPIO[122]
ALT0
GPIO[122]
—
FlexPWM_1
X[2]
ALT1
X[2]
—
eTimer_2
ETC[2]
ALT2
ETC[2]
—
SIUL
GPIO[123]
ALT0
GPIO[123]
—
FlexPWM_1
A[2]
ALT1
A[2]
—
SIUL
GPIO[124]
ALT0
GPIO[124]
—
FlexPWM_1
B[2]
ALT1
B[2]
—
SIUL
GPIO[125]
ALT0
GPIO[125]
—
FlexPWM_1
X[3]
ALT1
X[3]
—
eTimer_2
ETC[3]
ALT2
ETC[3]
PSMI[42];
PADSEL=0
SIUL
GPIO[126]
ALT0
GPIO[126]
—
FlexPWM_1
A[3]
ALT1
A[3]
—
eTimer_2
ETC[4]
ALT2
ETC[4]
—
SIUL
GPIO[127]
ALT0
GPIO[127]
—
FlexPWM_1
B[3]
ALT1
B[3]
—
eTimer_2
ETC[5]
ALT2
ETC[5]
—
H[11]
MPC5643L Microcontroller Data Sheet, Rev. 10
H[12]
H[13]
H[14]
H[15]
PCR[123]
PCR[124]
PCR[125]
PCR[126]
PCR[127]
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
M
S
—
A11
—
M
S
—
C11
—
M
S
—
B10
—
M
S
—
G15
—
M
S
—
A12
—
M
S
—
J17
—
M
S
—
C9
Port I
I[0]
PCR[128]
NXP Semiconductors
SIUL
GPIO[128]
ALT0
GPIO[128]
—
eTimer_2
ETC[0]
ALT1
ETC[0]
PSMI[39];
PADSEL=1
DSPI_0
CS4
ALT2
—
—
FlexPWM_1
—
—
FAULT[0]
—
Package pinouts and signal descriptions
74
Table 7. Pin muxing (continued)
Port
name
PCR
Peripheral
Alternate
output
function
I[1]
PCR[129]
SIUL
GPIO[129]
ALT0
GPIO[129]
—
eTimer_2
ETC[1]
ALT1
ETC[1]
PSMI[40];
PADSEL=1
DSPI_0
CS5
ALT2
—
—
FlexPWM_1
—
—
FAULT[1]
—
SIUL
GPIO[130]
ALT0
GPIO[130]
—
eTimer_2
ETC[2]
ALT1
ETC[2]
PSMI[41];
PADSEL=1
DSPI_0
CS6
ALT2
—
—
FlexPWM_1
—
—
FAULT[2]
—
SIUL
GPIO[131]
ALT0
GPIO[131]
—
eTimer_2
ETC[3]
ALT1
ETC[3]
PSMI[42];
PADSEL=1
DSPI_0
CS7
ALT2
—
—
CTU_0
EXT_TGR
ALT3
—
—
FlexPWM_1
—
—
FAULT[3]
—
SIUL
GPIO[132]
ALT0
GPIO[132]
—
NPC
RDY
ALT2
—
—
MPC5643L Microcontroller Data Sheet, Rev. 10
I[2]
I[3]
RDY
PCR[130]
PCR[131]
PCR[132]
Output
mux sel
Input
functions
Input mux
select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
M
S
—
C12
—
M
S
—
F16
—
M
S
—
E17
—
F
S
—
K3
1
Programmable via the SRC (Slew Rate Control) bit in the respective Pad Configuration Register; S = Slow, M = Medium, F = Fast, SYM =
Symmetric (for FlexRay)
2 The default function of this pin out of reset is ALT1 (TDO).
3 Analog
NXP Semiconductors
NOTE
Open Drain can be configured by the PCRn for all pins used as output (except FCCU_F[0] and FCCU_F[1] ).
Package pinouts and signal descriptions
75
Table 7. Pin muxing (continued)
Electrical characteristics
3
Electrical characteristics
3.1
Introduction
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications for this device.
This device is designed to operate at 120 MHz. The electrical specifications are preliminary and are from previous designs,
design simulations, or initial evaluation. These specifications may not be fully tested or guaranteed at this early stage of the
product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been
completed.
The “Symbol” column of the electrical parameter and timings tables contains an additional column containing “SR”, “CC”, “P”,
“C”, “T”, or “D”.
•
•
•
3.2
“SR” identifies system requirements—conditions that must be provided to ensure normal device operation. An
example is the input voltage of a voltage regulator.
“CC” identifies controller characteristics—indicating the characteristics and timing of the signals that the chip
provides.
“P”, “C”, “T”, or “D” apply only to controller characteristics—specifications that define normal device operation.
They specify how each characteristic is guaranteed.
— P: parameter is guaranteed by production testing of each individual device.
— C: parameter is guaranteed by design characterization. Measurements are taken from a statistically relevant
sample size across process variations.
— T: parameter is guaranteed by design characterization on a small sample size from typical devices under typical
conditions unless otherwise noted. All values are shown in the typical (“typ”) column are within this category.
— D: parameters are derived mainly from simulations.
Absolute maximum ratings
Table 8. Absolute maximum ratings1
Symbol
VDD_HV_REG
Parameter
SR
3.3 V voltage regulator supply voltage
Conditions
Min
Max
Unit
—
–0.3
3.632, 3
V
V
VDD_HV_IOx
SR
3.3 V input/output supply voltage
—
–0.3
3.632, 3
VSS_HV_IOx
SR
Input/output ground voltage
—
–0.1
0.1
V
V
VDD_HV_FLA
SR
3.3 V flash supply voltage
—
–0.3
3.632, 3
VSS_HV_FLA
SR
Flash memory ground
—
–0.1
0.1
V
VDD_HV_OSC
SR
3.3 V crystal oscillator amplifier supply
voltage
—
–0.3
3.632, 3
V
VSS_HV_OSC
SR
3.3 V crystal oscillator amplifier reference
voltage
—
–0.1
0.1
V
3.3 V / 5.0 V ADC_0 high reference voltage
3.3 V / 5.0 V ADC_1 high reference voltage
—
–0.3
6.0
V
VDD_HV_ADR03,4 SR
VDD_HV_ADR1
VSS_HV_ADR0
VSS_HV_ADR1
SR
ADC_0 ground and low reference voltage
ADC_1 ground and low reference voltage
—
–0.1
0.1
V
VDD_HV_ADV
SR
3.3 V ADC supply voltage
—
–0.3
3.632, 3
V
VSS_HV_ADV
SR
3.3 V ADC supply ground
—
–0.1
0.1
V
MPC5643L Microcontroller Data Sheet, Rev. 10
76
NXP Semiconductors
Electrical characteristics
Table 8. Absolute maximum ratings1 (continued)
Symbol
1
2
3
4
5
6
3.3
Parameter
Conditions
Min
TVDD
SR
Supply ramp rate
—
3.0 × 10-6
(3.0 V/sec)
VIN
SR
Voltage on any pin with respect to ground
(VSS_HV_IOx)
—
–0.3
Relative to VDD
Max
Unit
0.5 V/μs
V/μs
6.05
V
5,6
–0.3
VDD + 0.3
IINJPAD
SR
Injected input current on any pin during
overload condition
—
–10
10
mA
IINJSUM
SR
Absolute sum of all injected input currents
during overload condition
—
–50
50
mA
TSTG
SR
Storage temperature
—
–55
150
°C
Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
5.3 V for 10 hours cumulative over lifetime of device, 3.3 V +10% for time remaining.
Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
6.4 V for 10 hours cumulative time, 6.0 V for time remaining.
Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDE supplies, if the
maximum injection current specification is met and VDDE is within the operating voltage specifications.
Only when VDD < 5.2 V.
Recommended operating conditions
Table 9. Recommended operating conditions (3.3 V)
Symbol
Parameter
Conditions
Min1
Max
Unit
VDD_HV_REG
SR 3.3 V voltage regulator supply voltage
—
3.0
3.63
V
VDD_HV_IOx
SR 3.3 V input/output supply voltage
—
3.0
3.63
V
VSS_HV_IOx
SR Input/output ground voltage
—
0
0
V
VDD_HV_FLA
SR 3.3 V flash supply voltage
—
3.0
3.63
V
VSS_HV_FLA
SR Flash memory ground
—
0
0
V
VDD_HV_OSC
SR 3.3 V crystal oscillator amplifier supply voltage
—
3.0
3.63
V
VSS_HV_OSC
SR 3.3 V crystal oscillator amplifier reference voltage
—
0
0
V
SR 3.3 V / 5.0 V ADC_0 high reference voltage
3.3 V / 5.0 V ADC_1 high reference voltage
—
4.5 to 5.5 or
3.0 to 3.63
V
VDD_HV_ADV
SR 3.3 V ADC supply voltage
—
3.0
3.63
V
VSS_HV_AD0
VSS_HV_AD1
SR ADC_0 ground and low reference voltage
ADC_1 ground and low reference voltage
—
0
0
V
VSS_HV_ADV
SR 3.3 V ADC supply ground
—
0
0
V
SR Internal supply voltage
—
—
—
V
—
0
0
V
—
—
—
V
2,3
VDD_HV_ADR0
VDD_HV_ADR1
VDD_LV_REGCOR4
5
VSS_LV_REGCOR SR Internal reference voltage
2
VDD_LV_CORx
SR Internal supply voltage
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
77
Electrical characteristics
Table 9. Recommended operating conditions (3.3 V) (continued)
Symbol
VSS_LV_CORx3
1
2
3
4
5
Parameter
Conditions
Min1
Max
Unit
SR Internal reference voltage
—
0
0
V
VDD_LV_PLL2
SR Internal supply voltage
—
—
—
V
VSS_LV_PLL3
SR Internal reference voltage
—
0
0
V
TA
SR Ambient temperature under bias
fCPU ≤ 120 MHz
–40
125
°C
TJ
SR Junction temperature under bias
—
–40
150
°C
Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics
and I/Os DC electrical specification may not be guaranteed.
VDD_HV_ADR0 and VDD_HV_ADR1 cannot be operated at different voltages, and need to be supplied by the same
voltage source.
VDD_HV_ADRx must always be applied and should be stable before LBIST starts. If this supply is not above its
absolute minimum level, LBIST operations can fail.
Can be connected to emitter of external NPN. Low voltage supplies are not under user control. They are produced
by an on-chip voltage regulator.
For the device to function properly, the low voltage grounds (VSS_LV_xxx) must be shorted to high voltage grounds
(VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast emitter, if one
is used.
3.4
Thermal characteristics
Table 10. Thermal characteristics for 100 LQFP package1
Symbol
RθJA
RθJMA
RθJB
1
2
3
4
5
D
D
D
Parameter
Conditions
Value Unit
Thermal resistance, junction-to-ambient natural Single layer board – 1s
convection2
Four layer board – 2s2p
46
Thermal resistance, junction-to-ambient forced Single layer board – 1s
convection at 200 ft/min
Four layer board – 2s2p
36
°C/W
34
°C/W
28
Thermal resistance
junction-to-board3
—
19
°C/W
junction-to-case4
—
8
°C/W
—
2
°C/W
RθJC
D
Thermal resistance
ΨJT
D
Junction-to-package-top natural convection5
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
MPC5643L Microcontroller Data Sheet, Rev. 10
78
NXP Semiconductors
Electrical characteristics
Table 11. Thermal characteristics for 144 LQFP package1
Symbol
RθJA
RθJMA
2
3
4
5
D
Conditions
44
Thermal resistance, junction-to-ambient forced Single layer board – 1s
convection at 200 ft/min
Four layer board – 2s2p
35
—
24
°C/W
—
8
°C/W
—
2
°C/W
D
Thermal resistance junction-to-board3
RθJC
D
Thermal resistance junction-to-case4
D
Value Unit
Thermal resistance, junction-to-ambient natural Single layer board – 1s
convection2
Four layer board – 2s2p
RθJB
ΨJT
1
D
Parameter
Junction-to-package-top natural convection
5
°C/W
36
°C/W
30
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
Table 12. Thermal characteristics for 257 MAPBGA package1
Symbol
RθJA
RθJMA
2
3
4
5
D
Conditions
46
Thermal resistance, junction-to-ambient forced Single layer board – 1s
convection at 200 ft/min
Four layer board – 2s2p
37
junction-to-board3
D
Thermal resistance
RθJC
D
Thermal resistance junction-to-case4
D
Value Unit
Thermal resistance junction-to-ambient natural Single layer board – 1s
convection2
Four layer board – 2s2p
RθJB
ΨJT
1
D
Parameter
Junction-to-package-top natural
convection5
°C/W
26
°C/W
22
—
13
°C/W
—
8
°C/W
—
2
°C/W
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
79
Electrical characteristics
3.4.1
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:
TJ = TA + (RθJA × PD)
Eqn. 1
where:
TA
= ambient temperature for the package (oC)
RθJA
= junction to ambient thermal resistance (oC/W)
PD
= power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value
obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which
value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a
single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance
and a case to ambient thermal resistance:
RθJA = RθJC + RθCA
Eqn. 2
where:
RθJA
= junction to ambient thermal resistance (°C/W)
RθJC
= junction to case thermal resistance (°C/W)
RθCA = case to ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the
interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit
board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal
Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at
the top center of the package case using Equation 3:
TJ = TT + (ΨJT × PD)
Eqn. 3
where:
TT
= thermocouple temperature on top of the package (°C)
ΨJT
= thermal characterization parameter (°C/W)
PD
= power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
3.4.1.1
References
Semiconductor Equipment and Materials International
3081 Zanker Road
MPC5643L Microcontroller Data Sheet, Rev. 10
80
NXP Semiconductors
Electrical characteristics
San Jose, CA 95134 USA
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1.
2.
3.
3.5
C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic
Packaging and Production, pp. 53–58, March 1998.
B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
Electromagnetic Interference (EMI) characteristics
The characteristics in Table 14 were measured using:
•
•
•
Device configuration, tet conditions, and EM testing per standard IEC61967-2
Supply voltage of 3.3 V DC
Ambient temperature of 25 °C
The configuration information referenced in Table 14 is explained in Table 13.
Table 13. EMI configuration summary
Configuration name
Description
Configuration A
•
•
•
•
•
High emission = all pads have max slew rate, LVDS pads running at 40 MHz
Oscillator frequency = 40 MHz
System bus frequency = 80 MHz
No PLL frequency modulation
IEC level I (≤ 36 dBμV)
Configuration B
•
•
•
•
•
Reference emission = pads use min, mid and max slew rates, LVDS pads disabled
Oscillator frequency = 40 MHz
System bus frequency = 80 MHz
2% PLL frequency modulation
IEC level K(≤ 30 dBμV)
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
81
Electrical characteristics
Table 14. EMI emission testing specifications
Symbol
VEME
Parameter
Conditions
CC Radiated emissions
Min
Typ
Max
Unit
Configuration A; frequency range
150 kHz–50 MHz
—
16
—
dBμV
Configuration A; frequency range
50–150 MHz
—
16
—
Configuration A; frequency range
150–500 MHz
—
32
—
Configuration A; frequency range
500–1000 MHz
—
25
—
Configuration B; frequency range
50–150 MHz
—
15
—
Configuration B; frequency range
50–150 MHz
—
21
—
Configuration B; frequency range
150–500 MHz
—
30
—
Configuration B; frequency range
500–1000 MHz
—
24
—
EMC testing was performed and documented according to these standards: [IEC61508-2-7.4.5.1.b, IEC61508-2-7.2.3.2.e,
IEC61508-2-Table-A.17 (partially), IEC61508-2-Table-B.5(partially),SRS2110]
EME testing was performed and documented according to these standards: [IEC 61967-2 & -4]
EMS testing was performed and documented according to these standards: [IEC 62132-2 & -4]
Refer MPC5643L for detailed information pertaining to the EMC, EME, and EMS testing and results.
3.6
Electrostatic discharge (ESD) characteristics
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according
to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n + 1) supply pin).
This test conforms to the AEC-Q100-002/-003/-011 standard.
Table 15. ESD ratings1, 2
No.
Symbol
Parameter
Conditions
Class
Max value3
Unit
1
VESD(HBM)
SR Electrostatic discharge
(Human Body Model)
TA = 25 °C
conforming to AEC-Q100-002
H1C
2000
V
2
VESD(MM)
SR Electrostatic discharge
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
V
3
VESD(CDM)
SR Electrostatic discharge TA = 25 °C
(Charged Device Model) conforming to AEC-Q100-011
C3A
500
V
750 (corners)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
MPC5643L Microcontroller Data Sheet, Rev. 10
82
NXP Semiconductors
Electrical characteristics
3
Data based on characterization results, not tested in production.
3.7
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 16. Latch-up results
No.
Symbol
1
3.8
LU
Parameter
SR
Static latch-up class
Conditions
Class
TA = 125 °C conforming to JESD 78
II level A
Voltage regulator electrical characteristics
The voltage regulator is composed of the following blocks:
•
•
•
•
•
•
•
•
•
•
High power regulator HPREG1 (internal ballast to support core current)
High power regulator HPREG2 (external NPN to support core current)
Low voltage detector (LVD_MAIN_1) for 3.3 V supply to IO (VDDIO)
Low voltage detector (LVD_MAIN_2) for 3.3 V supply (VDDREG)
Low voltage detector (LVD_MAIN_3) for 3.3 V flash supply (VDDFLASH)
Low voltage detector (LVD_DIG_MAIN) for 1.2 V digital core supply (HPVDD)
Low voltage detector (LVD_DIG_BKUP) for the self-test of LVD_DIG_MAIN
High voltage detector (HVD_DIG_MAIN) for 1.2 V digital CORE supply (HPVDD)
High voltage detector (HVD_DIG_BKUP) for the self-test of HVD_DIG_MAIN.
Power on Reset (POR)
HPREG1 uses an internal ballast to support the core current. HPREG2 is used only when external NPN transistor is present on
board to supply core current. The MPC5643L always powers up using HPREG1 if an external NPN transistor is present. Then
the MPC5643L makes a transition from HPREG1 to HPREG2. This transition is dynamic. Once HPREG2 is fully operational,
the controller part of HPREG1 is switched off.
The following bipolar transistors are supported:
•
•
BCP68 from ON Semiconductor
BCX68 from Infineon
Table 17. Recommended operating characteristics
Symbol
hFE( β )
1
Parameter
DC current gain (Beta)
Value
Unit
85 - 375
—
PD
Maximum power dissipation @
TA=25°C1
1.5
W
ICMaxDC
Maximum peak collector current
1.0
A
VCESAT
Collector-to-emitter saturation
voltage(Max)
6002
mV
VBE
Base-to-emitter voltage (Max)
1.0
V
derating factor 12mW/degC
MPC5643L Microcontroller Data Sheet, Rev. 10
NXP Semiconductors
83
Electrical characteristics
2
Adjust resistor at bipolar transistor collector for 3.3V to avoid VCE